1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_target.h" 9 10 #include <linux/delay.h> 11 #include <linux/gfp.h> 12 13 14 /* 15 * qla2x00_mailbox_command 16 * Issue mailbox command and waits for completion. 17 * 18 * Input: 19 * ha = adapter block pointer. 20 * mcp = driver internal mbx struct pointer. 21 * 22 * Output: 23 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data. 24 * 25 * Returns: 26 * 0 : QLA_SUCCESS = cmd performed success 27 * 1 : QLA_FUNCTION_FAILED (error encountered) 28 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered) 29 * 30 * Context: 31 * Kernel context. 32 */ 33 static int 34 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) 35 { 36 int rval; 37 unsigned long flags = 0; 38 device_reg_t *reg; 39 uint8_t abort_active; 40 uint8_t io_lock_on; 41 uint16_t command = 0; 42 uint16_t *iptr; 43 uint16_t __iomem *optr; 44 uint32_t cnt; 45 uint32_t mboxes; 46 unsigned long wait_time; 47 struct qla_hw_data *ha = vha->hw; 48 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 49 50 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__); 51 52 if (ha->pdev->error_state > pci_channel_io_frozen) { 53 ql_log(ql_log_warn, vha, 0x1001, 54 "error_state is greater than pci_channel_io_frozen, " 55 "exiting.\n"); 56 return QLA_FUNCTION_TIMEOUT; 57 } 58 59 if (vha->device_flags & DFLG_DEV_FAILED) { 60 ql_log(ql_log_warn, vha, 0x1002, 61 "Device in failed state, exiting.\n"); 62 return QLA_FUNCTION_TIMEOUT; 63 } 64 65 reg = ha->iobase; 66 io_lock_on = base_vha->flags.init_done; 67 68 rval = QLA_SUCCESS; 69 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 70 71 72 if (ha->flags.pci_channel_io_perm_failure) { 73 ql_log(ql_log_warn, vha, 0x1003, 74 "Perm failure on EEH timeout MBX, exiting.\n"); 75 return QLA_FUNCTION_TIMEOUT; 76 } 77 78 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 79 /* Setting Link-Down error */ 80 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 81 ql_log(ql_log_warn, vha, 0x1004, 82 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 83 return QLA_FUNCTION_TIMEOUT; 84 } 85 86 /* 87 * Wait for active mailbox commands to finish by waiting at most tov 88 * seconds. This is to serialize actual issuing of mailbox cmds during 89 * non ISP abort time. 90 */ 91 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) { 92 /* Timeout occurred. Return error. */ 93 ql_log(ql_log_warn, vha, 0x1005, 94 "Cmd access timeout, cmd=0x%x, Exiting.\n", 95 mcp->mb[0]); 96 return QLA_FUNCTION_TIMEOUT; 97 } 98 99 ha->flags.mbox_busy = 1; 100 /* Save mailbox command for debug */ 101 ha->mcp = mcp; 102 103 ql_dbg(ql_dbg_mbx, vha, 0x1006, 104 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); 105 106 spin_lock_irqsave(&ha->hardware_lock, flags); 107 108 /* Load mailbox registers. */ 109 if (IS_P3P_TYPE(ha)) 110 optr = (uint16_t __iomem *)®->isp82.mailbox_in[0]; 111 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) 112 optr = (uint16_t __iomem *)®->isp24.mailbox0; 113 else 114 optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); 115 116 iptr = mcp->mb; 117 command = mcp->mb[0]; 118 mboxes = mcp->out_mb; 119 120 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111, 121 "Mailbox registers (OUT):\n"); 122 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 123 if (IS_QLA2200(ha) && cnt == 8) 124 optr = 125 (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 8); 126 if (mboxes & BIT_0) { 127 ql_dbg(ql_dbg_mbx, vha, 0x1112, 128 "mbox[%d]<-0x%04x\n", cnt, *iptr); 129 WRT_REG_WORD(optr, *iptr); 130 } 131 132 mboxes >>= 1; 133 optr++; 134 iptr++; 135 } 136 137 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117, 138 "I/O Address = %p.\n", optr); 139 140 /* Issue set host interrupt command to send cmd out. */ 141 ha->flags.mbox_int = 0; 142 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 143 144 /* Unlock mbx registers and wait for interrupt */ 145 ql_dbg(ql_dbg_mbx, vha, 0x100f, 146 "Going to unlock irq & waiting for interrupts. " 147 "jiffies=%lx.\n", jiffies); 148 149 /* Wait for mbx cmd completion until timeout */ 150 151 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { 152 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 153 154 if (IS_P3P_TYPE(ha)) { 155 if (RD_REG_DWORD(®->isp82.hint) & 156 HINT_MBX_INT_PENDING) { 157 spin_unlock_irqrestore(&ha->hardware_lock, 158 flags); 159 ha->flags.mbox_busy = 0; 160 ql_dbg(ql_dbg_mbx, vha, 0x1010, 161 "Pending mailbox timeout, exiting.\n"); 162 rval = QLA_FUNCTION_TIMEOUT; 163 goto premature_exit; 164 } 165 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 166 } else if (IS_FWI2_CAPABLE(ha)) 167 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 168 else 169 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 170 spin_unlock_irqrestore(&ha->hardware_lock, flags); 171 172 if (!wait_for_completion_timeout(&ha->mbx_intr_comp, 173 mcp->tov * HZ)) { 174 ql_dbg(ql_dbg_mbx, vha, 0x117a, 175 "cmd=%x Timeout.\n", command); 176 spin_lock_irqsave(&ha->hardware_lock, flags); 177 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 178 spin_unlock_irqrestore(&ha->hardware_lock, flags); 179 } 180 } else { 181 ql_dbg(ql_dbg_mbx, vha, 0x1011, 182 "Cmd=%x Polling Mode.\n", command); 183 184 if (IS_P3P_TYPE(ha)) { 185 if (RD_REG_DWORD(®->isp82.hint) & 186 HINT_MBX_INT_PENDING) { 187 spin_unlock_irqrestore(&ha->hardware_lock, 188 flags); 189 ha->flags.mbox_busy = 0; 190 ql_dbg(ql_dbg_mbx, vha, 0x1012, 191 "Pending mailbox timeout, exiting.\n"); 192 rval = QLA_FUNCTION_TIMEOUT; 193 goto premature_exit; 194 } 195 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 196 } else if (IS_FWI2_CAPABLE(ha)) 197 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 198 else 199 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 200 spin_unlock_irqrestore(&ha->hardware_lock, flags); 201 202 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */ 203 while (!ha->flags.mbox_int) { 204 if (time_after(jiffies, wait_time)) 205 break; 206 207 /* Check for pending interrupts. */ 208 qla2x00_poll(ha->rsp_q_map[0]); 209 210 if (!ha->flags.mbox_int && 211 !(IS_QLA2200(ha) && 212 command == MBC_LOAD_RISC_RAM_EXTENDED)) 213 msleep(10); 214 } /* while */ 215 ql_dbg(ql_dbg_mbx, vha, 0x1013, 216 "Waited %d sec.\n", 217 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ)); 218 } 219 220 /* Check whether we timed out */ 221 if (ha->flags.mbox_int) { 222 uint16_t *iptr2; 223 224 ql_dbg(ql_dbg_mbx, vha, 0x1014, 225 "Cmd=%x completed.\n", command); 226 227 /* Got interrupt. Clear the flag. */ 228 ha->flags.mbox_int = 0; 229 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 230 231 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 232 ha->flags.mbox_busy = 0; 233 /* Setting Link-Down error */ 234 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 235 ha->mcp = NULL; 236 rval = QLA_FUNCTION_FAILED; 237 ql_log(ql_log_warn, vha, 0x1015, 238 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 239 goto premature_exit; 240 } 241 242 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) 243 rval = QLA_FUNCTION_FAILED; 244 245 /* Load return mailbox registers. */ 246 iptr2 = mcp->mb; 247 iptr = (uint16_t *)&ha->mailbox_out[0]; 248 mboxes = mcp->in_mb; 249 250 ql_dbg(ql_dbg_mbx, vha, 0x1113, 251 "Mailbox registers (IN):\n"); 252 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 253 if (mboxes & BIT_0) { 254 *iptr2 = *iptr; 255 ql_dbg(ql_dbg_mbx, vha, 0x1114, 256 "mbox[%d]->0x%04x\n", cnt, *iptr2); 257 } 258 259 mboxes >>= 1; 260 iptr2++; 261 iptr++; 262 } 263 } else { 264 265 uint16_t mb0; 266 uint32_t ictrl; 267 268 if (IS_FWI2_CAPABLE(ha)) { 269 mb0 = RD_REG_WORD(®->isp24.mailbox0); 270 ictrl = RD_REG_DWORD(®->isp24.ictrl); 271 } else { 272 mb0 = RD_MAILBOX_REG(ha, ®->isp, 0); 273 ictrl = RD_REG_WORD(®->isp.ictrl); 274 } 275 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119, 276 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx " 277 "mb[0]=0x%x\n", command, ictrl, jiffies, mb0); 278 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019); 279 280 /* 281 * Attempt to capture a firmware dump for further analysis 282 * of the current firmware state. We do not need to do this 283 * if we are intentionally generating a dump. 284 */ 285 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) 286 ha->isp_ops->fw_dump(vha, 0); 287 288 rval = QLA_FUNCTION_TIMEOUT; 289 } 290 291 ha->flags.mbox_busy = 0; 292 293 /* Clean up */ 294 ha->mcp = NULL; 295 296 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) { 297 ql_dbg(ql_dbg_mbx, vha, 0x101a, 298 "Checking for additional resp interrupt.\n"); 299 300 /* polling mode for non isp_abort commands. */ 301 qla2x00_poll(ha->rsp_q_map[0]); 302 } 303 304 if (rval == QLA_FUNCTION_TIMEOUT && 305 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) { 306 if (!io_lock_on || (mcp->flags & IOCTL_CMD) || 307 ha->flags.eeh_busy) { 308 /* not in dpc. schedule it for dpc to take over. */ 309 ql_dbg(ql_dbg_mbx, vha, 0x101b, 310 "Timeout, schedule isp_abort_needed.\n"); 311 312 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 313 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 314 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 315 if (IS_QLA82XX(ha)) { 316 ql_dbg(ql_dbg_mbx, vha, 0x112a, 317 "disabling pause transmit on port " 318 "0 & 1.\n"); 319 qla82xx_wr_32(ha, 320 QLA82XX_CRB_NIU + 0x98, 321 CRB_NIU_XG_PAUSE_CTL_P0| 322 CRB_NIU_XG_PAUSE_CTL_P1); 323 } 324 ql_log(ql_log_info, base_vha, 0x101c, 325 "Mailbox cmd timeout occurred, cmd=0x%x, " 326 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP " 327 "abort.\n", command, mcp->mb[0], 328 ha->flags.eeh_busy); 329 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 330 qla2xxx_wake_dpc(vha); 331 } 332 } else if (!abort_active) { 333 /* call abort directly since we are in the DPC thread */ 334 ql_dbg(ql_dbg_mbx, vha, 0x101d, 335 "Timeout, calling abort_isp.\n"); 336 337 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 338 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 339 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 340 if (IS_QLA82XX(ha)) { 341 ql_dbg(ql_dbg_mbx, vha, 0x112b, 342 "disabling pause transmit on port " 343 "0 & 1.\n"); 344 qla82xx_wr_32(ha, 345 QLA82XX_CRB_NIU + 0x98, 346 CRB_NIU_XG_PAUSE_CTL_P0| 347 CRB_NIU_XG_PAUSE_CTL_P1); 348 } 349 ql_log(ql_log_info, base_vha, 0x101e, 350 "Mailbox cmd timeout occurred, cmd=0x%x, " 351 "mb[0]=0x%x. Scheduling ISP abort ", 352 command, mcp->mb[0]); 353 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 354 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 355 /* Allow next mbx cmd to come in. */ 356 complete(&ha->mbx_cmd_comp); 357 if (ha->isp_ops->abort_isp(vha)) { 358 /* Failed. retry later. */ 359 set_bit(ISP_ABORT_NEEDED, 360 &vha->dpc_flags); 361 } 362 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 363 ql_dbg(ql_dbg_mbx, vha, 0x101f, 364 "Finished abort_isp.\n"); 365 goto mbx_done; 366 } 367 } 368 } 369 370 premature_exit: 371 /* Allow next mbx cmd to come in. */ 372 complete(&ha->mbx_cmd_comp); 373 374 mbx_done: 375 if (rval) { 376 ql_log(ql_log_warn, base_vha, 0x1020, 377 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n", 378 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command); 379 } else { 380 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__); 381 } 382 383 return rval; 384 } 385 386 int 387 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr, 388 uint32_t risc_code_size) 389 { 390 int rval; 391 struct qla_hw_data *ha = vha->hw; 392 mbx_cmd_t mc; 393 mbx_cmd_t *mcp = &mc; 394 395 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022, 396 "Entered %s.\n", __func__); 397 398 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) { 399 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; 400 mcp->mb[8] = MSW(risc_addr); 401 mcp->out_mb = MBX_8|MBX_0; 402 } else { 403 mcp->mb[0] = MBC_LOAD_RISC_RAM; 404 mcp->out_mb = MBX_0; 405 } 406 mcp->mb[1] = LSW(risc_addr); 407 mcp->mb[2] = MSW(req_dma); 408 mcp->mb[3] = LSW(req_dma); 409 mcp->mb[6] = MSW(MSD(req_dma)); 410 mcp->mb[7] = LSW(MSD(req_dma)); 411 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 412 if (IS_FWI2_CAPABLE(ha)) { 413 mcp->mb[4] = MSW(risc_code_size); 414 mcp->mb[5] = LSW(risc_code_size); 415 mcp->out_mb |= MBX_5|MBX_4; 416 } else { 417 mcp->mb[4] = LSW(risc_code_size); 418 mcp->out_mb |= MBX_4; 419 } 420 421 mcp->in_mb = MBX_0; 422 mcp->tov = MBX_TOV_SECONDS; 423 mcp->flags = 0; 424 rval = qla2x00_mailbox_command(vha, mcp); 425 426 if (rval != QLA_SUCCESS) { 427 ql_dbg(ql_dbg_mbx, vha, 0x1023, 428 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 429 } else { 430 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024, 431 "Done %s.\n", __func__); 432 } 433 434 return rval; 435 } 436 437 #define EXTENDED_BB_CREDITS BIT_0 438 /* 439 * qla2x00_execute_fw 440 * Start adapter firmware. 441 * 442 * Input: 443 * ha = adapter block pointer. 444 * TARGET_QUEUE_LOCK must be released. 445 * ADAPTER_STATE_LOCK must be released. 446 * 447 * Returns: 448 * qla2x00 local function return status code. 449 * 450 * Context: 451 * Kernel context. 452 */ 453 int 454 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr) 455 { 456 int rval; 457 struct qla_hw_data *ha = vha->hw; 458 mbx_cmd_t mc; 459 mbx_cmd_t *mcp = &mc; 460 461 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025, 462 "Entered %s.\n", __func__); 463 464 mcp->mb[0] = MBC_EXECUTE_FIRMWARE; 465 mcp->out_mb = MBX_0; 466 mcp->in_mb = MBX_0; 467 if (IS_FWI2_CAPABLE(ha)) { 468 mcp->mb[1] = MSW(risc_addr); 469 mcp->mb[2] = LSW(risc_addr); 470 mcp->mb[3] = 0; 471 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 472 IS_QLA27XX(ha)) { 473 struct nvram_81xx *nv = ha->nvram; 474 mcp->mb[4] = (nv->enhanced_features & 475 EXTENDED_BB_CREDITS); 476 } else 477 mcp->mb[4] = 0; 478 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1; 479 mcp->in_mb |= MBX_1; 480 } else { 481 mcp->mb[1] = LSW(risc_addr); 482 mcp->out_mb |= MBX_1; 483 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 484 mcp->mb[2] = 0; 485 mcp->out_mb |= MBX_2; 486 } 487 } 488 489 mcp->tov = MBX_TOV_SECONDS; 490 mcp->flags = 0; 491 rval = qla2x00_mailbox_command(vha, mcp); 492 493 if (rval != QLA_SUCCESS) { 494 ql_dbg(ql_dbg_mbx, vha, 0x1026, 495 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 496 } else { 497 if (IS_FWI2_CAPABLE(ha)) { 498 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027, 499 "Done exchanges=%x.\n", mcp->mb[1]); 500 } else { 501 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028, 502 "Done %s.\n", __func__); 503 } 504 } 505 506 return rval; 507 } 508 509 /* 510 * qla2x00_get_fw_version 511 * Get firmware version. 512 * 513 * Input: 514 * ha: adapter state pointer. 515 * major: pointer for major number. 516 * minor: pointer for minor number. 517 * subminor: pointer for subminor number. 518 * 519 * Returns: 520 * qla2x00 local function return status code. 521 * 522 * Context: 523 * Kernel context. 524 */ 525 int 526 qla2x00_get_fw_version(scsi_qla_host_t *vha) 527 { 528 int rval; 529 mbx_cmd_t mc; 530 mbx_cmd_t *mcp = &mc; 531 struct qla_hw_data *ha = vha->hw; 532 533 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029, 534 "Entered %s.\n", __func__); 535 536 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION; 537 mcp->out_mb = MBX_0; 538 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 539 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha)) 540 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8; 541 if (IS_FWI2_CAPABLE(ha)) 542 mcp->in_mb |= MBX_17|MBX_16|MBX_15; 543 if (IS_QLA27XX(ha)) 544 mcp->in_mb |= MBX_21|MBX_20|MBX_19|MBX_18; 545 mcp->flags = 0; 546 mcp->tov = MBX_TOV_SECONDS; 547 rval = qla2x00_mailbox_command(vha, mcp); 548 if (rval != QLA_SUCCESS) 549 goto failed; 550 551 /* Return mailbox data. */ 552 ha->fw_major_version = mcp->mb[1]; 553 ha->fw_minor_version = mcp->mb[2]; 554 ha->fw_subminor_version = mcp->mb[3]; 555 ha->fw_attributes = mcp->mb[6]; 556 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw)) 557 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */ 558 else 559 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4]; 560 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) { 561 ha->mpi_version[0] = mcp->mb[10] & 0xff; 562 ha->mpi_version[1] = mcp->mb[11] >> 8; 563 ha->mpi_version[2] = mcp->mb[11] & 0xff; 564 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13]; 565 ha->phy_version[0] = mcp->mb[8] & 0xff; 566 ha->phy_version[1] = mcp->mb[9] >> 8; 567 ha->phy_version[2] = mcp->mb[9] & 0xff; 568 } 569 if (IS_FWI2_CAPABLE(ha)) { 570 ha->fw_attributes_h = mcp->mb[15]; 571 ha->fw_attributes_ext[0] = mcp->mb[16]; 572 ha->fw_attributes_ext[1] = mcp->mb[17]; 573 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139, 574 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n", 575 __func__, mcp->mb[15], mcp->mb[6]); 576 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f, 577 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n", 578 __func__, mcp->mb[17], mcp->mb[16]); 579 } 580 if (IS_QLA27XX(ha)) { 581 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18]; 582 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20]; 583 } 584 585 failed: 586 if (rval != QLA_SUCCESS) { 587 /*EMPTY*/ 588 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval); 589 } else { 590 /*EMPTY*/ 591 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b, 592 "Done %s.\n", __func__); 593 } 594 return rval; 595 } 596 597 /* 598 * qla2x00_get_fw_options 599 * Set firmware options. 600 * 601 * Input: 602 * ha = adapter block pointer. 603 * fwopt = pointer for firmware options. 604 * 605 * Returns: 606 * qla2x00 local function return status code. 607 * 608 * Context: 609 * Kernel context. 610 */ 611 int 612 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 613 { 614 int rval; 615 mbx_cmd_t mc; 616 mbx_cmd_t *mcp = &mc; 617 618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c, 619 "Entered %s.\n", __func__); 620 621 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION; 622 mcp->out_mb = MBX_0; 623 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 624 mcp->tov = MBX_TOV_SECONDS; 625 mcp->flags = 0; 626 rval = qla2x00_mailbox_command(vha, mcp); 627 628 if (rval != QLA_SUCCESS) { 629 /*EMPTY*/ 630 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval); 631 } else { 632 fwopts[0] = mcp->mb[0]; 633 fwopts[1] = mcp->mb[1]; 634 fwopts[2] = mcp->mb[2]; 635 fwopts[3] = mcp->mb[3]; 636 637 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e, 638 "Done %s.\n", __func__); 639 } 640 641 return rval; 642 } 643 644 645 /* 646 * qla2x00_set_fw_options 647 * Set firmware options. 648 * 649 * Input: 650 * ha = adapter block pointer. 651 * fwopt = pointer for firmware options. 652 * 653 * Returns: 654 * qla2x00 local function return status code. 655 * 656 * Context: 657 * Kernel context. 658 */ 659 int 660 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 661 { 662 int rval; 663 mbx_cmd_t mc; 664 mbx_cmd_t *mcp = &mc; 665 666 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f, 667 "Entered %s.\n", __func__); 668 669 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION; 670 mcp->mb[1] = fwopts[1]; 671 mcp->mb[2] = fwopts[2]; 672 mcp->mb[3] = fwopts[3]; 673 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 674 mcp->in_mb = MBX_0; 675 if (IS_FWI2_CAPABLE(vha->hw)) { 676 mcp->in_mb |= MBX_1; 677 } else { 678 mcp->mb[10] = fwopts[10]; 679 mcp->mb[11] = fwopts[11]; 680 mcp->mb[12] = 0; /* Undocumented, but used */ 681 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 682 } 683 mcp->tov = MBX_TOV_SECONDS; 684 mcp->flags = 0; 685 rval = qla2x00_mailbox_command(vha, mcp); 686 687 fwopts[0] = mcp->mb[0]; 688 689 if (rval != QLA_SUCCESS) { 690 /*EMPTY*/ 691 ql_dbg(ql_dbg_mbx, vha, 0x1030, 692 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]); 693 } else { 694 /*EMPTY*/ 695 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031, 696 "Done %s.\n", __func__); 697 } 698 699 return rval; 700 } 701 702 /* 703 * qla2x00_mbx_reg_test 704 * Mailbox register wrap test. 705 * 706 * Input: 707 * ha = adapter block pointer. 708 * TARGET_QUEUE_LOCK must be released. 709 * ADAPTER_STATE_LOCK must be released. 710 * 711 * Returns: 712 * qla2x00 local function return status code. 713 * 714 * Context: 715 * Kernel context. 716 */ 717 int 718 qla2x00_mbx_reg_test(scsi_qla_host_t *vha) 719 { 720 int rval; 721 mbx_cmd_t mc; 722 mbx_cmd_t *mcp = &mc; 723 724 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032, 725 "Entered %s.\n", __func__); 726 727 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; 728 mcp->mb[1] = 0xAAAA; 729 mcp->mb[2] = 0x5555; 730 mcp->mb[3] = 0xAA55; 731 mcp->mb[4] = 0x55AA; 732 mcp->mb[5] = 0xA5A5; 733 mcp->mb[6] = 0x5A5A; 734 mcp->mb[7] = 0x2525; 735 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 736 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 737 mcp->tov = MBX_TOV_SECONDS; 738 mcp->flags = 0; 739 rval = qla2x00_mailbox_command(vha, mcp); 740 741 if (rval == QLA_SUCCESS) { 742 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 || 743 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA) 744 rval = QLA_FUNCTION_FAILED; 745 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A || 746 mcp->mb[7] != 0x2525) 747 rval = QLA_FUNCTION_FAILED; 748 } 749 750 if (rval != QLA_SUCCESS) { 751 /*EMPTY*/ 752 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval); 753 } else { 754 /*EMPTY*/ 755 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034, 756 "Done %s.\n", __func__); 757 } 758 759 return rval; 760 } 761 762 /* 763 * qla2x00_verify_checksum 764 * Verify firmware checksum. 765 * 766 * Input: 767 * ha = adapter block pointer. 768 * TARGET_QUEUE_LOCK must be released. 769 * ADAPTER_STATE_LOCK must be released. 770 * 771 * Returns: 772 * qla2x00 local function return status code. 773 * 774 * Context: 775 * Kernel context. 776 */ 777 int 778 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr) 779 { 780 int rval; 781 mbx_cmd_t mc; 782 mbx_cmd_t *mcp = &mc; 783 784 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035, 785 "Entered %s.\n", __func__); 786 787 mcp->mb[0] = MBC_VERIFY_CHECKSUM; 788 mcp->out_mb = MBX_0; 789 mcp->in_mb = MBX_0; 790 if (IS_FWI2_CAPABLE(vha->hw)) { 791 mcp->mb[1] = MSW(risc_addr); 792 mcp->mb[2] = LSW(risc_addr); 793 mcp->out_mb |= MBX_2|MBX_1; 794 mcp->in_mb |= MBX_2|MBX_1; 795 } else { 796 mcp->mb[1] = LSW(risc_addr); 797 mcp->out_mb |= MBX_1; 798 mcp->in_mb |= MBX_1; 799 } 800 801 mcp->tov = MBX_TOV_SECONDS; 802 mcp->flags = 0; 803 rval = qla2x00_mailbox_command(vha, mcp); 804 805 if (rval != QLA_SUCCESS) { 806 ql_dbg(ql_dbg_mbx, vha, 0x1036, 807 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ? 808 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]); 809 } else { 810 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037, 811 "Done %s.\n", __func__); 812 } 813 814 return rval; 815 } 816 817 /* 818 * qla2x00_issue_iocb 819 * Issue IOCB using mailbox command 820 * 821 * Input: 822 * ha = adapter state pointer. 823 * buffer = buffer pointer. 824 * phys_addr = physical address of buffer. 825 * size = size of buffer. 826 * TARGET_QUEUE_LOCK must be released. 827 * ADAPTER_STATE_LOCK must be released. 828 * 829 * Returns: 830 * qla2x00 local function return status code. 831 * 832 * Context: 833 * Kernel context. 834 */ 835 int 836 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer, 837 dma_addr_t phys_addr, size_t size, uint32_t tov) 838 { 839 int rval; 840 mbx_cmd_t mc; 841 mbx_cmd_t *mcp = &mc; 842 843 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038, 844 "Entered %s.\n", __func__); 845 846 mcp->mb[0] = MBC_IOCB_COMMAND_A64; 847 mcp->mb[1] = 0; 848 mcp->mb[2] = MSW(phys_addr); 849 mcp->mb[3] = LSW(phys_addr); 850 mcp->mb[6] = MSW(MSD(phys_addr)); 851 mcp->mb[7] = LSW(MSD(phys_addr)); 852 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 853 mcp->in_mb = MBX_2|MBX_0; 854 mcp->tov = tov; 855 mcp->flags = 0; 856 rval = qla2x00_mailbox_command(vha, mcp); 857 858 if (rval != QLA_SUCCESS) { 859 /*EMPTY*/ 860 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval); 861 } else { 862 sts_entry_t *sts_entry = (sts_entry_t *) buffer; 863 864 /* Mask reserved bits. */ 865 sts_entry->entry_status &= 866 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK; 867 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a, 868 "Done %s.\n", __func__); 869 } 870 871 return rval; 872 } 873 874 int 875 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr, 876 size_t size) 877 { 878 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size, 879 MBX_TOV_SECONDS); 880 } 881 882 /* 883 * qla2x00_abort_command 884 * Abort command aborts a specified IOCB. 885 * 886 * Input: 887 * ha = adapter block pointer. 888 * sp = SB structure pointer. 889 * 890 * Returns: 891 * qla2x00 local function return status code. 892 * 893 * Context: 894 * Kernel context. 895 */ 896 int 897 qla2x00_abort_command(srb_t *sp) 898 { 899 unsigned long flags = 0; 900 int rval; 901 uint32_t handle = 0; 902 mbx_cmd_t mc; 903 mbx_cmd_t *mcp = &mc; 904 fc_port_t *fcport = sp->fcport; 905 scsi_qla_host_t *vha = fcport->vha; 906 struct qla_hw_data *ha = vha->hw; 907 struct req_que *req = vha->req; 908 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 909 910 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b, 911 "Entered %s.\n", __func__); 912 913 spin_lock_irqsave(&ha->hardware_lock, flags); 914 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 915 if (req->outstanding_cmds[handle] == sp) 916 break; 917 } 918 spin_unlock_irqrestore(&ha->hardware_lock, flags); 919 920 if (handle == req->num_outstanding_cmds) { 921 /* command not found */ 922 return QLA_FUNCTION_FAILED; 923 } 924 925 mcp->mb[0] = MBC_ABORT_COMMAND; 926 if (HAS_EXTENDED_IDS(ha)) 927 mcp->mb[1] = fcport->loop_id; 928 else 929 mcp->mb[1] = fcport->loop_id << 8; 930 mcp->mb[2] = (uint16_t)handle; 931 mcp->mb[3] = (uint16_t)(handle >> 16); 932 mcp->mb[6] = (uint16_t)cmd->device->lun; 933 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 934 mcp->in_mb = MBX_0; 935 mcp->tov = MBX_TOV_SECONDS; 936 mcp->flags = 0; 937 rval = qla2x00_mailbox_command(vha, mcp); 938 939 if (rval != QLA_SUCCESS) { 940 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval); 941 } else { 942 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d, 943 "Done %s.\n", __func__); 944 } 945 946 return rval; 947 } 948 949 int 950 qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag) 951 { 952 int rval, rval2; 953 mbx_cmd_t mc; 954 mbx_cmd_t *mcp = &mc; 955 scsi_qla_host_t *vha; 956 struct req_que *req; 957 struct rsp_que *rsp; 958 959 l = l; 960 vha = fcport->vha; 961 962 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e, 963 "Entered %s.\n", __func__); 964 965 req = vha->hw->req_q_map[0]; 966 rsp = req->rsp; 967 mcp->mb[0] = MBC_ABORT_TARGET; 968 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0; 969 if (HAS_EXTENDED_IDS(vha->hw)) { 970 mcp->mb[1] = fcport->loop_id; 971 mcp->mb[10] = 0; 972 mcp->out_mb |= MBX_10; 973 } else { 974 mcp->mb[1] = fcport->loop_id << 8; 975 } 976 mcp->mb[2] = vha->hw->loop_reset_delay; 977 mcp->mb[9] = vha->vp_idx; 978 979 mcp->in_mb = MBX_0; 980 mcp->tov = MBX_TOV_SECONDS; 981 mcp->flags = 0; 982 rval = qla2x00_mailbox_command(vha, mcp); 983 if (rval != QLA_SUCCESS) { 984 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f, 985 "Failed=%x.\n", rval); 986 } 987 988 /* Issue marker IOCB. */ 989 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0, 990 MK_SYNC_ID); 991 if (rval2 != QLA_SUCCESS) { 992 ql_dbg(ql_dbg_mbx, vha, 0x1040, 993 "Failed to issue marker IOCB (%x).\n", rval2); 994 } else { 995 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041, 996 "Done %s.\n", __func__); 997 } 998 999 return rval; 1000 } 1001 1002 int 1003 qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag) 1004 { 1005 int rval, rval2; 1006 mbx_cmd_t mc; 1007 mbx_cmd_t *mcp = &mc; 1008 scsi_qla_host_t *vha; 1009 struct req_que *req; 1010 struct rsp_que *rsp; 1011 1012 vha = fcport->vha; 1013 1014 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042, 1015 "Entered %s.\n", __func__); 1016 1017 req = vha->hw->req_q_map[0]; 1018 rsp = req->rsp; 1019 mcp->mb[0] = MBC_LUN_RESET; 1020 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 1021 if (HAS_EXTENDED_IDS(vha->hw)) 1022 mcp->mb[1] = fcport->loop_id; 1023 else 1024 mcp->mb[1] = fcport->loop_id << 8; 1025 mcp->mb[2] = l; 1026 mcp->mb[3] = 0; 1027 mcp->mb[9] = vha->vp_idx; 1028 1029 mcp->in_mb = MBX_0; 1030 mcp->tov = MBX_TOV_SECONDS; 1031 mcp->flags = 0; 1032 rval = qla2x00_mailbox_command(vha, mcp); 1033 if (rval != QLA_SUCCESS) { 1034 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval); 1035 } 1036 1037 /* Issue marker IOCB. */ 1038 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 1039 MK_SYNC_ID_LUN); 1040 if (rval2 != QLA_SUCCESS) { 1041 ql_dbg(ql_dbg_mbx, vha, 0x1044, 1042 "Failed to issue marker IOCB (%x).\n", rval2); 1043 } else { 1044 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045, 1045 "Done %s.\n", __func__); 1046 } 1047 1048 return rval; 1049 } 1050 1051 /* 1052 * qla2x00_get_adapter_id 1053 * Get adapter ID and topology. 1054 * 1055 * Input: 1056 * ha = adapter block pointer. 1057 * id = pointer for loop ID. 1058 * al_pa = pointer for AL_PA. 1059 * area = pointer for area. 1060 * domain = pointer for domain. 1061 * top = pointer for topology. 1062 * TARGET_QUEUE_LOCK must be released. 1063 * ADAPTER_STATE_LOCK must be released. 1064 * 1065 * Returns: 1066 * qla2x00 local function return status code. 1067 * 1068 * Context: 1069 * Kernel context. 1070 */ 1071 int 1072 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa, 1073 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap) 1074 { 1075 int rval; 1076 mbx_cmd_t mc; 1077 mbx_cmd_t *mcp = &mc; 1078 1079 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046, 1080 "Entered %s.\n", __func__); 1081 1082 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID; 1083 mcp->mb[9] = vha->vp_idx; 1084 mcp->out_mb = MBX_9|MBX_0; 1085 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1086 if (IS_CNA_CAPABLE(vha->hw)) 1087 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; 1088 mcp->tov = MBX_TOV_SECONDS; 1089 mcp->flags = 0; 1090 rval = qla2x00_mailbox_command(vha, mcp); 1091 if (mcp->mb[0] == MBS_COMMAND_ERROR) 1092 rval = QLA_COMMAND_ERROR; 1093 else if (mcp->mb[0] == MBS_INVALID_COMMAND) 1094 rval = QLA_INVALID_COMMAND; 1095 1096 /* Return data. */ 1097 *id = mcp->mb[1]; 1098 *al_pa = LSB(mcp->mb[2]); 1099 *area = MSB(mcp->mb[2]); 1100 *domain = LSB(mcp->mb[3]); 1101 *top = mcp->mb[6]; 1102 *sw_cap = mcp->mb[7]; 1103 1104 if (rval != QLA_SUCCESS) { 1105 /*EMPTY*/ 1106 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval); 1107 } else { 1108 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048, 1109 "Done %s.\n", __func__); 1110 1111 if (IS_CNA_CAPABLE(vha->hw)) { 1112 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; 1113 vha->fcoe_fcf_idx = mcp->mb[10]; 1114 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; 1115 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff; 1116 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8; 1117 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff; 1118 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8; 1119 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff; 1120 } 1121 } 1122 1123 return rval; 1124 } 1125 1126 /* 1127 * qla2x00_get_retry_cnt 1128 * Get current firmware login retry count and delay. 1129 * 1130 * Input: 1131 * ha = adapter block pointer. 1132 * retry_cnt = pointer to login retry count. 1133 * tov = pointer to login timeout value. 1134 * 1135 * Returns: 1136 * qla2x00 local function return status code. 1137 * 1138 * Context: 1139 * Kernel context. 1140 */ 1141 int 1142 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov, 1143 uint16_t *r_a_tov) 1144 { 1145 int rval; 1146 uint16_t ratov; 1147 mbx_cmd_t mc; 1148 mbx_cmd_t *mcp = &mc; 1149 1150 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049, 1151 "Entered %s.\n", __func__); 1152 1153 mcp->mb[0] = MBC_GET_RETRY_COUNT; 1154 mcp->out_mb = MBX_0; 1155 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1156 mcp->tov = MBX_TOV_SECONDS; 1157 mcp->flags = 0; 1158 rval = qla2x00_mailbox_command(vha, mcp); 1159 1160 if (rval != QLA_SUCCESS) { 1161 /*EMPTY*/ 1162 ql_dbg(ql_dbg_mbx, vha, 0x104a, 1163 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 1164 } else { 1165 /* Convert returned data and check our values. */ 1166 *r_a_tov = mcp->mb[3] / 2; 1167 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */ 1168 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) { 1169 /* Update to the larger values */ 1170 *retry_cnt = (uint8_t)mcp->mb[1]; 1171 *tov = ratov; 1172 } 1173 1174 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b, 1175 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov); 1176 } 1177 1178 return rval; 1179 } 1180 1181 /* 1182 * qla2x00_init_firmware 1183 * Initialize adapter firmware. 1184 * 1185 * Input: 1186 * ha = adapter block pointer. 1187 * dptr = Initialization control block pointer. 1188 * size = size of initialization control block. 1189 * TARGET_QUEUE_LOCK must be released. 1190 * ADAPTER_STATE_LOCK must be released. 1191 * 1192 * Returns: 1193 * qla2x00 local function return status code. 1194 * 1195 * Context: 1196 * Kernel context. 1197 */ 1198 int 1199 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size) 1200 { 1201 int rval; 1202 mbx_cmd_t mc; 1203 mbx_cmd_t *mcp = &mc; 1204 struct qla_hw_data *ha = vha->hw; 1205 1206 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c, 1207 "Entered %s.\n", __func__); 1208 1209 if (IS_P3P_TYPE(ha) && ql2xdbwr) 1210 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, 1211 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16))); 1212 1213 if (ha->flags.npiv_supported) 1214 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE; 1215 else 1216 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; 1217 1218 mcp->mb[1] = 0; 1219 mcp->mb[2] = MSW(ha->init_cb_dma); 1220 mcp->mb[3] = LSW(ha->init_cb_dma); 1221 mcp->mb[6] = MSW(MSD(ha->init_cb_dma)); 1222 mcp->mb[7] = LSW(MSD(ha->init_cb_dma)); 1223 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1224 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) { 1225 mcp->mb[1] = BIT_0; 1226 mcp->mb[10] = MSW(ha->ex_init_cb_dma); 1227 mcp->mb[11] = LSW(ha->ex_init_cb_dma); 1228 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma)); 1229 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma)); 1230 mcp->mb[14] = sizeof(*ha->ex_init_cb); 1231 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10; 1232 } 1233 /* 1 and 2 should normally be captured. */ 1234 mcp->in_mb = MBX_2|MBX_1|MBX_0; 1235 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 1236 /* mb3 is additional info about the installed SFP. */ 1237 mcp->in_mb |= MBX_3; 1238 mcp->buf_size = size; 1239 mcp->flags = MBX_DMA_OUT; 1240 mcp->tov = MBX_TOV_SECONDS; 1241 rval = qla2x00_mailbox_command(vha, mcp); 1242 1243 if (rval != QLA_SUCCESS) { 1244 /*EMPTY*/ 1245 ql_dbg(ql_dbg_mbx, vha, 0x104d, 1246 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n", 1247 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]); 1248 } else { 1249 /*EMPTY*/ 1250 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e, 1251 "Done %s.\n", __func__); 1252 } 1253 1254 return rval; 1255 } 1256 1257 /* 1258 * qla2x00_get_node_name_list 1259 * Issue get node name list mailbox command, kmalloc() 1260 * and return the resulting list. Caller must kfree() it! 1261 * 1262 * Input: 1263 * ha = adapter state pointer. 1264 * out_data = resulting list 1265 * out_len = length of the resulting list 1266 * 1267 * Returns: 1268 * qla2x00 local function return status code. 1269 * 1270 * Context: 1271 * Kernel context. 1272 */ 1273 int 1274 qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len) 1275 { 1276 struct qla_hw_data *ha = vha->hw; 1277 struct qla_port_24xx_data *list = NULL; 1278 void *pmap; 1279 mbx_cmd_t mc; 1280 dma_addr_t pmap_dma; 1281 ulong dma_size; 1282 int rval, left; 1283 1284 left = 1; 1285 while (left > 0) { 1286 dma_size = left * sizeof(*list); 1287 pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size, 1288 &pmap_dma, GFP_KERNEL); 1289 if (!pmap) { 1290 ql_log(ql_log_warn, vha, 0x113f, 1291 "%s(%ld): DMA Alloc failed of %ld\n", 1292 __func__, vha->host_no, dma_size); 1293 rval = QLA_MEMORY_ALLOC_FAILED; 1294 goto out; 1295 } 1296 1297 mc.mb[0] = MBC_PORT_NODE_NAME_LIST; 1298 mc.mb[1] = BIT_1 | BIT_3; 1299 mc.mb[2] = MSW(pmap_dma); 1300 mc.mb[3] = LSW(pmap_dma); 1301 mc.mb[6] = MSW(MSD(pmap_dma)); 1302 mc.mb[7] = LSW(MSD(pmap_dma)); 1303 mc.mb[8] = dma_size; 1304 mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8; 1305 mc.in_mb = MBX_0|MBX_1; 1306 mc.tov = 30; 1307 mc.flags = MBX_DMA_IN; 1308 1309 rval = qla2x00_mailbox_command(vha, &mc); 1310 if (rval != QLA_SUCCESS) { 1311 if ((mc.mb[0] == MBS_COMMAND_ERROR) && 1312 (mc.mb[1] == 0xA)) { 1313 left += le16_to_cpu(mc.mb[2]) / 1314 sizeof(struct qla_port_24xx_data); 1315 goto restart; 1316 } 1317 goto out_free; 1318 } 1319 1320 left = 0; 1321 1322 list = kzalloc(dma_size, GFP_KERNEL); 1323 if (!list) { 1324 ql_log(ql_log_warn, vha, 0x1140, 1325 "%s(%ld): failed to allocate node names list " 1326 "structure.\n", __func__, vha->host_no); 1327 rval = QLA_MEMORY_ALLOC_FAILED; 1328 goto out_free; 1329 } 1330 1331 memcpy(list, pmap, dma_size); 1332 restart: 1333 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma); 1334 } 1335 1336 *out_data = list; 1337 *out_len = dma_size; 1338 1339 out: 1340 return rval; 1341 1342 out_free: 1343 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma); 1344 return rval; 1345 } 1346 1347 /* 1348 * qla2x00_get_port_database 1349 * Issue normal/enhanced get port database mailbox command 1350 * and copy device name as necessary. 1351 * 1352 * Input: 1353 * ha = adapter state pointer. 1354 * dev = structure pointer. 1355 * opt = enhanced cmd option byte. 1356 * 1357 * Returns: 1358 * qla2x00 local function return status code. 1359 * 1360 * Context: 1361 * Kernel context. 1362 */ 1363 int 1364 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt) 1365 { 1366 int rval; 1367 mbx_cmd_t mc; 1368 mbx_cmd_t *mcp = &mc; 1369 port_database_t *pd; 1370 struct port_database_24xx *pd24; 1371 dma_addr_t pd_dma; 1372 struct qla_hw_data *ha = vha->hw; 1373 1374 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f, 1375 "Entered %s.\n", __func__); 1376 1377 pd24 = NULL; 1378 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1379 if (pd == NULL) { 1380 ql_log(ql_log_warn, vha, 0x1050, 1381 "Failed to allocate port database structure.\n"); 1382 return QLA_MEMORY_ALLOC_FAILED; 1383 } 1384 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE)); 1385 1386 mcp->mb[0] = MBC_GET_PORT_DATABASE; 1387 if (opt != 0 && !IS_FWI2_CAPABLE(ha)) 1388 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE; 1389 mcp->mb[2] = MSW(pd_dma); 1390 mcp->mb[3] = LSW(pd_dma); 1391 mcp->mb[6] = MSW(MSD(pd_dma)); 1392 mcp->mb[7] = LSW(MSD(pd_dma)); 1393 mcp->mb[9] = vha->vp_idx; 1394 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 1395 mcp->in_mb = MBX_0; 1396 if (IS_FWI2_CAPABLE(ha)) { 1397 mcp->mb[1] = fcport->loop_id; 1398 mcp->mb[10] = opt; 1399 mcp->out_mb |= MBX_10|MBX_1; 1400 mcp->in_mb |= MBX_1; 1401 } else if (HAS_EXTENDED_IDS(ha)) { 1402 mcp->mb[1] = fcport->loop_id; 1403 mcp->mb[10] = opt; 1404 mcp->out_mb |= MBX_10|MBX_1; 1405 } else { 1406 mcp->mb[1] = fcport->loop_id << 8 | opt; 1407 mcp->out_mb |= MBX_1; 1408 } 1409 mcp->buf_size = IS_FWI2_CAPABLE(ha) ? 1410 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE; 1411 mcp->flags = MBX_DMA_IN; 1412 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1413 rval = qla2x00_mailbox_command(vha, mcp); 1414 if (rval != QLA_SUCCESS) 1415 goto gpd_error_out; 1416 1417 if (IS_FWI2_CAPABLE(ha)) { 1418 uint64_t zero = 0; 1419 pd24 = (struct port_database_24xx *) pd; 1420 1421 /* Check for logged in state. */ 1422 if (pd24->current_login_state != PDS_PRLI_COMPLETE && 1423 pd24->last_login_state != PDS_PRLI_COMPLETE) { 1424 ql_dbg(ql_dbg_mbx, vha, 0x1051, 1425 "Unable to verify login-state (%x/%x) for " 1426 "loop_id %x.\n", pd24->current_login_state, 1427 pd24->last_login_state, fcport->loop_id); 1428 rval = QLA_FUNCTION_FAILED; 1429 goto gpd_error_out; 1430 } 1431 1432 if (fcport->loop_id == FC_NO_LOOP_ID || 1433 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1434 memcmp(fcport->port_name, pd24->port_name, 8))) { 1435 /* We lost the device mid way. */ 1436 rval = QLA_NOT_LOGGED_IN; 1437 goto gpd_error_out; 1438 } 1439 1440 /* Names are little-endian. */ 1441 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE); 1442 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE); 1443 1444 /* Get port_id of device. */ 1445 fcport->d_id.b.domain = pd24->port_id[0]; 1446 fcport->d_id.b.area = pd24->port_id[1]; 1447 fcport->d_id.b.al_pa = pd24->port_id[2]; 1448 fcport->d_id.b.rsvd_1 = 0; 1449 1450 /* If not target must be initiator or unknown type. */ 1451 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0) 1452 fcport->port_type = FCT_INITIATOR; 1453 else 1454 fcport->port_type = FCT_TARGET; 1455 1456 /* Passback COS information. */ 1457 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ? 1458 FC_COS_CLASS2 : FC_COS_CLASS3; 1459 1460 if (pd24->prli_svc_param_word_3[0] & BIT_7) 1461 fcport->flags |= FCF_CONF_COMP_SUPPORTED; 1462 } else { 1463 uint64_t zero = 0; 1464 1465 /* Check for logged in state. */ 1466 if (pd->master_state != PD_STATE_PORT_LOGGED_IN && 1467 pd->slave_state != PD_STATE_PORT_LOGGED_IN) { 1468 ql_dbg(ql_dbg_mbx, vha, 0x100a, 1469 "Unable to verify login-state (%x/%x) - " 1470 "portid=%02x%02x%02x.\n", pd->master_state, 1471 pd->slave_state, fcport->d_id.b.domain, 1472 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1473 rval = QLA_FUNCTION_FAILED; 1474 goto gpd_error_out; 1475 } 1476 1477 if (fcport->loop_id == FC_NO_LOOP_ID || 1478 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1479 memcmp(fcport->port_name, pd->port_name, 8))) { 1480 /* We lost the device mid way. */ 1481 rval = QLA_NOT_LOGGED_IN; 1482 goto gpd_error_out; 1483 } 1484 1485 /* Names are little-endian. */ 1486 memcpy(fcport->node_name, pd->node_name, WWN_SIZE); 1487 memcpy(fcport->port_name, pd->port_name, WWN_SIZE); 1488 1489 /* Get port_id of device. */ 1490 fcport->d_id.b.domain = pd->port_id[0]; 1491 fcport->d_id.b.area = pd->port_id[3]; 1492 fcport->d_id.b.al_pa = pd->port_id[2]; 1493 fcport->d_id.b.rsvd_1 = 0; 1494 1495 /* If not target must be initiator or unknown type. */ 1496 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 1497 fcport->port_type = FCT_INITIATOR; 1498 else 1499 fcport->port_type = FCT_TARGET; 1500 1501 /* Passback COS information. */ 1502 fcport->supported_classes = (pd->options & BIT_4) ? 1503 FC_COS_CLASS2: FC_COS_CLASS3; 1504 } 1505 1506 gpd_error_out: 1507 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1508 1509 if (rval != QLA_SUCCESS) { 1510 ql_dbg(ql_dbg_mbx, vha, 0x1052, 1511 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval, 1512 mcp->mb[0], mcp->mb[1]); 1513 } else { 1514 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053, 1515 "Done %s.\n", __func__); 1516 } 1517 1518 return rval; 1519 } 1520 1521 /* 1522 * qla2x00_get_firmware_state 1523 * Get adapter firmware state. 1524 * 1525 * Input: 1526 * ha = adapter block pointer. 1527 * dptr = pointer for firmware state. 1528 * TARGET_QUEUE_LOCK must be released. 1529 * ADAPTER_STATE_LOCK must be released. 1530 * 1531 * Returns: 1532 * qla2x00 local function return status code. 1533 * 1534 * Context: 1535 * Kernel context. 1536 */ 1537 int 1538 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states) 1539 { 1540 int rval; 1541 mbx_cmd_t mc; 1542 mbx_cmd_t *mcp = &mc; 1543 1544 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054, 1545 "Entered %s.\n", __func__); 1546 1547 mcp->mb[0] = MBC_GET_FIRMWARE_STATE; 1548 mcp->out_mb = MBX_0; 1549 if (IS_FWI2_CAPABLE(vha->hw)) 1550 mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1551 else 1552 mcp->in_mb = MBX_1|MBX_0; 1553 mcp->tov = MBX_TOV_SECONDS; 1554 mcp->flags = 0; 1555 rval = qla2x00_mailbox_command(vha, mcp); 1556 1557 /* Return firmware states. */ 1558 states[0] = mcp->mb[1]; 1559 if (IS_FWI2_CAPABLE(vha->hw)) { 1560 states[1] = mcp->mb[2]; 1561 states[2] = mcp->mb[3]; 1562 states[3] = mcp->mb[4]; 1563 states[4] = mcp->mb[5]; 1564 } 1565 1566 if (rval != QLA_SUCCESS) { 1567 /*EMPTY*/ 1568 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval); 1569 } else { 1570 /*EMPTY*/ 1571 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056, 1572 "Done %s.\n", __func__); 1573 } 1574 1575 return rval; 1576 } 1577 1578 /* 1579 * qla2x00_get_port_name 1580 * Issue get port name mailbox command. 1581 * Returned name is in big endian format. 1582 * 1583 * Input: 1584 * ha = adapter block pointer. 1585 * loop_id = loop ID of device. 1586 * name = pointer for name. 1587 * TARGET_QUEUE_LOCK must be released. 1588 * ADAPTER_STATE_LOCK must be released. 1589 * 1590 * Returns: 1591 * qla2x00 local function return status code. 1592 * 1593 * Context: 1594 * Kernel context. 1595 */ 1596 int 1597 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name, 1598 uint8_t opt) 1599 { 1600 int rval; 1601 mbx_cmd_t mc; 1602 mbx_cmd_t *mcp = &mc; 1603 1604 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057, 1605 "Entered %s.\n", __func__); 1606 1607 mcp->mb[0] = MBC_GET_PORT_NAME; 1608 mcp->mb[9] = vha->vp_idx; 1609 mcp->out_mb = MBX_9|MBX_1|MBX_0; 1610 if (HAS_EXTENDED_IDS(vha->hw)) { 1611 mcp->mb[1] = loop_id; 1612 mcp->mb[10] = opt; 1613 mcp->out_mb |= MBX_10; 1614 } else { 1615 mcp->mb[1] = loop_id << 8 | opt; 1616 } 1617 1618 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1619 mcp->tov = MBX_TOV_SECONDS; 1620 mcp->flags = 0; 1621 rval = qla2x00_mailbox_command(vha, mcp); 1622 1623 if (rval != QLA_SUCCESS) { 1624 /*EMPTY*/ 1625 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval); 1626 } else { 1627 if (name != NULL) { 1628 /* This function returns name in big endian. */ 1629 name[0] = MSB(mcp->mb[2]); 1630 name[1] = LSB(mcp->mb[2]); 1631 name[2] = MSB(mcp->mb[3]); 1632 name[3] = LSB(mcp->mb[3]); 1633 name[4] = MSB(mcp->mb[6]); 1634 name[5] = LSB(mcp->mb[6]); 1635 name[6] = MSB(mcp->mb[7]); 1636 name[7] = LSB(mcp->mb[7]); 1637 } 1638 1639 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059, 1640 "Done %s.\n", __func__); 1641 } 1642 1643 return rval; 1644 } 1645 1646 /* 1647 * qla24xx_link_initialization 1648 * Issue link initialization mailbox command. 1649 * 1650 * Input: 1651 * ha = adapter block pointer. 1652 * TARGET_QUEUE_LOCK must be released. 1653 * ADAPTER_STATE_LOCK must be released. 1654 * 1655 * Returns: 1656 * qla2x00 local function return status code. 1657 * 1658 * Context: 1659 * Kernel context. 1660 */ 1661 int 1662 qla24xx_link_initialize(scsi_qla_host_t *vha) 1663 { 1664 int rval; 1665 mbx_cmd_t mc; 1666 mbx_cmd_t *mcp = &mc; 1667 1668 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152, 1669 "Entered %s.\n", __func__); 1670 1671 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw)) 1672 return QLA_FUNCTION_FAILED; 1673 1674 mcp->mb[0] = MBC_LINK_INITIALIZATION; 1675 mcp->mb[1] = BIT_4; 1676 if (vha->hw->operating_mode == LOOP) 1677 mcp->mb[1] |= BIT_6; 1678 else 1679 mcp->mb[1] |= BIT_5; 1680 mcp->mb[2] = 0; 1681 mcp->mb[3] = 0; 1682 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1683 mcp->in_mb = MBX_0; 1684 mcp->tov = MBX_TOV_SECONDS; 1685 mcp->flags = 0; 1686 rval = qla2x00_mailbox_command(vha, mcp); 1687 1688 if (rval != QLA_SUCCESS) { 1689 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval); 1690 } else { 1691 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154, 1692 "Done %s.\n", __func__); 1693 } 1694 1695 return rval; 1696 } 1697 1698 /* 1699 * qla2x00_lip_reset 1700 * Issue LIP reset mailbox command. 1701 * 1702 * Input: 1703 * ha = adapter block pointer. 1704 * TARGET_QUEUE_LOCK must be released. 1705 * ADAPTER_STATE_LOCK must be released. 1706 * 1707 * Returns: 1708 * qla2x00 local function return status code. 1709 * 1710 * Context: 1711 * Kernel context. 1712 */ 1713 int 1714 qla2x00_lip_reset(scsi_qla_host_t *vha) 1715 { 1716 int rval; 1717 mbx_cmd_t mc; 1718 mbx_cmd_t *mcp = &mc; 1719 1720 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a, 1721 "Entered %s.\n", __func__); 1722 1723 if (IS_CNA_CAPABLE(vha->hw)) { 1724 /* Logout across all FCFs. */ 1725 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1726 mcp->mb[1] = BIT_1; 1727 mcp->mb[2] = 0; 1728 mcp->out_mb = MBX_2|MBX_1|MBX_0; 1729 } else if (IS_FWI2_CAPABLE(vha->hw)) { 1730 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1731 mcp->mb[1] = BIT_6; 1732 mcp->mb[2] = 0; 1733 mcp->mb[3] = vha->hw->loop_reset_delay; 1734 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1735 } else { 1736 mcp->mb[0] = MBC_LIP_RESET; 1737 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1738 if (HAS_EXTENDED_IDS(vha->hw)) { 1739 mcp->mb[1] = 0x00ff; 1740 mcp->mb[10] = 0; 1741 mcp->out_mb |= MBX_10; 1742 } else { 1743 mcp->mb[1] = 0xff00; 1744 } 1745 mcp->mb[2] = vha->hw->loop_reset_delay; 1746 mcp->mb[3] = 0; 1747 } 1748 mcp->in_mb = MBX_0; 1749 mcp->tov = MBX_TOV_SECONDS; 1750 mcp->flags = 0; 1751 rval = qla2x00_mailbox_command(vha, mcp); 1752 1753 if (rval != QLA_SUCCESS) { 1754 /*EMPTY*/ 1755 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval); 1756 } else { 1757 /*EMPTY*/ 1758 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c, 1759 "Done %s.\n", __func__); 1760 } 1761 1762 return rval; 1763 } 1764 1765 /* 1766 * qla2x00_send_sns 1767 * Send SNS command. 1768 * 1769 * Input: 1770 * ha = adapter block pointer. 1771 * sns = pointer for command. 1772 * cmd_size = command size. 1773 * buf_size = response/command size. 1774 * TARGET_QUEUE_LOCK must be released. 1775 * ADAPTER_STATE_LOCK must be released. 1776 * 1777 * Returns: 1778 * qla2x00 local function return status code. 1779 * 1780 * Context: 1781 * Kernel context. 1782 */ 1783 int 1784 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address, 1785 uint16_t cmd_size, size_t buf_size) 1786 { 1787 int rval; 1788 mbx_cmd_t mc; 1789 mbx_cmd_t *mcp = &mc; 1790 1791 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d, 1792 "Entered %s.\n", __func__); 1793 1794 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e, 1795 "Retry cnt=%d ratov=%d total tov=%d.\n", 1796 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov); 1797 1798 mcp->mb[0] = MBC_SEND_SNS_COMMAND; 1799 mcp->mb[1] = cmd_size; 1800 mcp->mb[2] = MSW(sns_phys_address); 1801 mcp->mb[3] = LSW(sns_phys_address); 1802 mcp->mb[6] = MSW(MSD(sns_phys_address)); 1803 mcp->mb[7] = LSW(MSD(sns_phys_address)); 1804 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1805 mcp->in_mb = MBX_0|MBX_1; 1806 mcp->buf_size = buf_size; 1807 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN; 1808 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2); 1809 rval = qla2x00_mailbox_command(vha, mcp); 1810 1811 if (rval != QLA_SUCCESS) { 1812 /*EMPTY*/ 1813 ql_dbg(ql_dbg_mbx, vha, 0x105f, 1814 "Failed=%x mb[0]=%x mb[1]=%x.\n", 1815 rval, mcp->mb[0], mcp->mb[1]); 1816 } else { 1817 /*EMPTY*/ 1818 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060, 1819 "Done %s.\n", __func__); 1820 } 1821 1822 return rval; 1823 } 1824 1825 int 1826 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 1827 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 1828 { 1829 int rval; 1830 1831 struct logio_entry_24xx *lg; 1832 dma_addr_t lg_dma; 1833 uint32_t iop[2]; 1834 struct qla_hw_data *ha = vha->hw; 1835 struct req_que *req; 1836 struct rsp_que *rsp; 1837 1838 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061, 1839 "Entered %s.\n", __func__); 1840 1841 if (ha->flags.cpu_affinity_enabled) 1842 req = ha->req_q_map[0]; 1843 else 1844 req = vha->req; 1845 rsp = req->rsp; 1846 1847 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 1848 if (lg == NULL) { 1849 ql_log(ql_log_warn, vha, 0x1062, 1850 "Failed to allocate login IOCB.\n"); 1851 return QLA_MEMORY_ALLOC_FAILED; 1852 } 1853 memset(lg, 0, sizeof(struct logio_entry_24xx)); 1854 1855 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 1856 lg->entry_count = 1; 1857 lg->handle = MAKE_HANDLE(req->id, lg->handle); 1858 lg->nport_handle = cpu_to_le16(loop_id); 1859 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI); 1860 if (opt & BIT_0) 1861 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI); 1862 if (opt & BIT_1) 1863 lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI); 1864 lg->port_id[0] = al_pa; 1865 lg->port_id[1] = area; 1866 lg->port_id[2] = domain; 1867 lg->vp_index = vha->vp_idx; 1868 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 1869 (ha->r_a_tov / 10 * 2) + 2); 1870 if (rval != QLA_SUCCESS) { 1871 ql_dbg(ql_dbg_mbx, vha, 0x1063, 1872 "Failed to issue login IOCB (%x).\n", rval); 1873 } else if (lg->entry_status != 0) { 1874 ql_dbg(ql_dbg_mbx, vha, 0x1064, 1875 "Failed to complete IOCB -- error status (%x).\n", 1876 lg->entry_status); 1877 rval = QLA_FUNCTION_FAILED; 1878 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 1879 iop[0] = le32_to_cpu(lg->io_parameter[0]); 1880 iop[1] = le32_to_cpu(lg->io_parameter[1]); 1881 1882 ql_dbg(ql_dbg_mbx, vha, 0x1065, 1883 "Failed to complete IOCB -- completion status (%x) " 1884 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 1885 iop[0], iop[1]); 1886 1887 switch (iop[0]) { 1888 case LSC_SCODE_PORTID_USED: 1889 mb[0] = MBS_PORT_ID_USED; 1890 mb[1] = LSW(iop[1]); 1891 break; 1892 case LSC_SCODE_NPORT_USED: 1893 mb[0] = MBS_LOOP_ID_USED; 1894 break; 1895 case LSC_SCODE_NOLINK: 1896 case LSC_SCODE_NOIOCB: 1897 case LSC_SCODE_NOXCB: 1898 case LSC_SCODE_CMD_FAILED: 1899 case LSC_SCODE_NOFABRIC: 1900 case LSC_SCODE_FW_NOT_READY: 1901 case LSC_SCODE_NOT_LOGGED_IN: 1902 case LSC_SCODE_NOPCB: 1903 case LSC_SCODE_ELS_REJECT: 1904 case LSC_SCODE_CMD_PARAM_ERR: 1905 case LSC_SCODE_NONPORT: 1906 case LSC_SCODE_LOGGED_IN: 1907 case LSC_SCODE_NOFLOGI_ACC: 1908 default: 1909 mb[0] = MBS_COMMAND_ERROR; 1910 break; 1911 } 1912 } else { 1913 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066, 1914 "Done %s.\n", __func__); 1915 1916 iop[0] = le32_to_cpu(lg->io_parameter[0]); 1917 1918 mb[0] = MBS_COMMAND_COMPLETE; 1919 mb[1] = 0; 1920 if (iop[0] & BIT_4) { 1921 if (iop[0] & BIT_8) 1922 mb[1] |= BIT_1; 1923 } else 1924 mb[1] = BIT_0; 1925 1926 /* Passback COS information. */ 1927 mb[10] = 0; 1928 if (lg->io_parameter[7] || lg->io_parameter[8]) 1929 mb[10] |= BIT_0; /* Class 2. */ 1930 if (lg->io_parameter[9] || lg->io_parameter[10]) 1931 mb[10] |= BIT_1; /* Class 3. */ 1932 if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7)) 1933 mb[10] |= BIT_7; /* Confirmed Completion 1934 * Allowed 1935 */ 1936 } 1937 1938 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 1939 1940 return rval; 1941 } 1942 1943 /* 1944 * qla2x00_login_fabric 1945 * Issue login fabric port mailbox command. 1946 * 1947 * Input: 1948 * ha = adapter block pointer. 1949 * loop_id = device loop ID. 1950 * domain = device domain. 1951 * area = device area. 1952 * al_pa = device AL_PA. 1953 * status = pointer for return status. 1954 * opt = command options. 1955 * TARGET_QUEUE_LOCK must be released. 1956 * ADAPTER_STATE_LOCK must be released. 1957 * 1958 * Returns: 1959 * qla2x00 local function return status code. 1960 * 1961 * Context: 1962 * Kernel context. 1963 */ 1964 int 1965 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 1966 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 1967 { 1968 int rval; 1969 mbx_cmd_t mc; 1970 mbx_cmd_t *mcp = &mc; 1971 struct qla_hw_data *ha = vha->hw; 1972 1973 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067, 1974 "Entered %s.\n", __func__); 1975 1976 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT; 1977 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1978 if (HAS_EXTENDED_IDS(ha)) { 1979 mcp->mb[1] = loop_id; 1980 mcp->mb[10] = opt; 1981 mcp->out_mb |= MBX_10; 1982 } else { 1983 mcp->mb[1] = (loop_id << 8) | opt; 1984 } 1985 mcp->mb[2] = domain; 1986 mcp->mb[3] = area << 8 | al_pa; 1987 1988 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0; 1989 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1990 mcp->flags = 0; 1991 rval = qla2x00_mailbox_command(vha, mcp); 1992 1993 /* Return mailbox statuses. */ 1994 if (mb != NULL) { 1995 mb[0] = mcp->mb[0]; 1996 mb[1] = mcp->mb[1]; 1997 mb[2] = mcp->mb[2]; 1998 mb[6] = mcp->mb[6]; 1999 mb[7] = mcp->mb[7]; 2000 /* COS retrieved from Get-Port-Database mailbox command. */ 2001 mb[10] = 0; 2002 } 2003 2004 if (rval != QLA_SUCCESS) { 2005 /* RLU tmp code: need to change main mailbox_command function to 2006 * return ok even when the mailbox completion value is not 2007 * SUCCESS. The caller needs to be responsible to interpret 2008 * the return values of this mailbox command if we're not 2009 * to change too much of the existing code. 2010 */ 2011 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 || 2012 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 || 2013 mcp->mb[0] == 0x4006) 2014 rval = QLA_SUCCESS; 2015 2016 /*EMPTY*/ 2017 ql_dbg(ql_dbg_mbx, vha, 0x1068, 2018 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 2019 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 2020 } else { 2021 /*EMPTY*/ 2022 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069, 2023 "Done %s.\n", __func__); 2024 } 2025 2026 return rval; 2027 } 2028 2029 /* 2030 * qla2x00_login_local_device 2031 * Issue login loop port mailbox command. 2032 * 2033 * Input: 2034 * ha = adapter block pointer. 2035 * loop_id = device loop ID. 2036 * opt = command options. 2037 * 2038 * Returns: 2039 * Return status code. 2040 * 2041 * Context: 2042 * Kernel context. 2043 * 2044 */ 2045 int 2046 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport, 2047 uint16_t *mb_ret, uint8_t opt) 2048 { 2049 int rval; 2050 mbx_cmd_t mc; 2051 mbx_cmd_t *mcp = &mc; 2052 struct qla_hw_data *ha = vha->hw; 2053 2054 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a, 2055 "Entered %s.\n", __func__); 2056 2057 if (IS_FWI2_CAPABLE(ha)) 2058 return qla24xx_login_fabric(vha, fcport->loop_id, 2059 fcport->d_id.b.domain, fcport->d_id.b.area, 2060 fcport->d_id.b.al_pa, mb_ret, opt); 2061 2062 mcp->mb[0] = MBC_LOGIN_LOOP_PORT; 2063 if (HAS_EXTENDED_IDS(ha)) 2064 mcp->mb[1] = fcport->loop_id; 2065 else 2066 mcp->mb[1] = fcport->loop_id << 8; 2067 mcp->mb[2] = opt; 2068 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2069 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0; 2070 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2071 mcp->flags = 0; 2072 rval = qla2x00_mailbox_command(vha, mcp); 2073 2074 /* Return mailbox statuses. */ 2075 if (mb_ret != NULL) { 2076 mb_ret[0] = mcp->mb[0]; 2077 mb_ret[1] = mcp->mb[1]; 2078 mb_ret[6] = mcp->mb[6]; 2079 mb_ret[7] = mcp->mb[7]; 2080 } 2081 2082 if (rval != QLA_SUCCESS) { 2083 /* AV tmp code: need to change main mailbox_command function to 2084 * return ok even when the mailbox completion value is not 2085 * SUCCESS. The caller needs to be responsible to interpret 2086 * the return values of this mailbox command if we're not 2087 * to change too much of the existing code. 2088 */ 2089 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006) 2090 rval = QLA_SUCCESS; 2091 2092 ql_dbg(ql_dbg_mbx, vha, 0x106b, 2093 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n", 2094 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]); 2095 } else { 2096 /*EMPTY*/ 2097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c, 2098 "Done %s.\n", __func__); 2099 } 2100 2101 return (rval); 2102 } 2103 2104 int 2105 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2106 uint8_t area, uint8_t al_pa) 2107 { 2108 int rval; 2109 struct logio_entry_24xx *lg; 2110 dma_addr_t lg_dma; 2111 struct qla_hw_data *ha = vha->hw; 2112 struct req_que *req; 2113 struct rsp_que *rsp; 2114 2115 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d, 2116 "Entered %s.\n", __func__); 2117 2118 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2119 if (lg == NULL) { 2120 ql_log(ql_log_warn, vha, 0x106e, 2121 "Failed to allocate logout IOCB.\n"); 2122 return QLA_MEMORY_ALLOC_FAILED; 2123 } 2124 memset(lg, 0, sizeof(struct logio_entry_24xx)); 2125 2126 if (ql2xmaxqueues > 1) 2127 req = ha->req_q_map[0]; 2128 else 2129 req = vha->req; 2130 rsp = req->rsp; 2131 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2132 lg->entry_count = 1; 2133 lg->handle = MAKE_HANDLE(req->id, lg->handle); 2134 lg->nport_handle = cpu_to_le16(loop_id); 2135 lg->control_flags = 2136 __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO| 2137 LCF_FREE_NPORT); 2138 lg->port_id[0] = al_pa; 2139 lg->port_id[1] = area; 2140 lg->port_id[2] = domain; 2141 lg->vp_index = vha->vp_idx; 2142 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2143 (ha->r_a_tov / 10 * 2) + 2); 2144 if (rval != QLA_SUCCESS) { 2145 ql_dbg(ql_dbg_mbx, vha, 0x106f, 2146 "Failed to issue logout IOCB (%x).\n", rval); 2147 } else if (lg->entry_status != 0) { 2148 ql_dbg(ql_dbg_mbx, vha, 0x1070, 2149 "Failed to complete IOCB -- error status (%x).\n", 2150 lg->entry_status); 2151 rval = QLA_FUNCTION_FAILED; 2152 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 2153 ql_dbg(ql_dbg_mbx, vha, 0x1071, 2154 "Failed to complete IOCB -- completion status (%x) " 2155 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2156 le32_to_cpu(lg->io_parameter[0]), 2157 le32_to_cpu(lg->io_parameter[1])); 2158 } else { 2159 /*EMPTY*/ 2160 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072, 2161 "Done %s.\n", __func__); 2162 } 2163 2164 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2165 2166 return rval; 2167 } 2168 2169 /* 2170 * qla2x00_fabric_logout 2171 * Issue logout fabric port mailbox command. 2172 * 2173 * Input: 2174 * ha = adapter block pointer. 2175 * loop_id = device loop ID. 2176 * TARGET_QUEUE_LOCK must be released. 2177 * ADAPTER_STATE_LOCK must be released. 2178 * 2179 * Returns: 2180 * qla2x00 local function return status code. 2181 * 2182 * Context: 2183 * Kernel context. 2184 */ 2185 int 2186 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2187 uint8_t area, uint8_t al_pa) 2188 { 2189 int rval; 2190 mbx_cmd_t mc; 2191 mbx_cmd_t *mcp = &mc; 2192 2193 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073, 2194 "Entered %s.\n", __func__); 2195 2196 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT; 2197 mcp->out_mb = MBX_1|MBX_0; 2198 if (HAS_EXTENDED_IDS(vha->hw)) { 2199 mcp->mb[1] = loop_id; 2200 mcp->mb[10] = 0; 2201 mcp->out_mb |= MBX_10; 2202 } else { 2203 mcp->mb[1] = loop_id << 8; 2204 } 2205 2206 mcp->in_mb = MBX_1|MBX_0; 2207 mcp->tov = MBX_TOV_SECONDS; 2208 mcp->flags = 0; 2209 rval = qla2x00_mailbox_command(vha, mcp); 2210 2211 if (rval != QLA_SUCCESS) { 2212 /*EMPTY*/ 2213 ql_dbg(ql_dbg_mbx, vha, 0x1074, 2214 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]); 2215 } else { 2216 /*EMPTY*/ 2217 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075, 2218 "Done %s.\n", __func__); 2219 } 2220 2221 return rval; 2222 } 2223 2224 /* 2225 * qla2x00_full_login_lip 2226 * Issue full login LIP mailbox command. 2227 * 2228 * Input: 2229 * ha = adapter block pointer. 2230 * TARGET_QUEUE_LOCK must be released. 2231 * ADAPTER_STATE_LOCK must be released. 2232 * 2233 * Returns: 2234 * qla2x00 local function return status code. 2235 * 2236 * Context: 2237 * Kernel context. 2238 */ 2239 int 2240 qla2x00_full_login_lip(scsi_qla_host_t *vha) 2241 { 2242 int rval; 2243 mbx_cmd_t mc; 2244 mbx_cmd_t *mcp = &mc; 2245 2246 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076, 2247 "Entered %s.\n", __func__); 2248 2249 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2250 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0; 2251 mcp->mb[2] = 0; 2252 mcp->mb[3] = 0; 2253 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2254 mcp->in_mb = MBX_0; 2255 mcp->tov = MBX_TOV_SECONDS; 2256 mcp->flags = 0; 2257 rval = qla2x00_mailbox_command(vha, mcp); 2258 2259 if (rval != QLA_SUCCESS) { 2260 /*EMPTY*/ 2261 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval); 2262 } else { 2263 /*EMPTY*/ 2264 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078, 2265 "Done %s.\n", __func__); 2266 } 2267 2268 return rval; 2269 } 2270 2271 /* 2272 * qla2x00_get_id_list 2273 * 2274 * Input: 2275 * ha = adapter block pointer. 2276 * 2277 * Returns: 2278 * qla2x00 local function return status code. 2279 * 2280 * Context: 2281 * Kernel context. 2282 */ 2283 int 2284 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma, 2285 uint16_t *entries) 2286 { 2287 int rval; 2288 mbx_cmd_t mc; 2289 mbx_cmd_t *mcp = &mc; 2290 2291 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079, 2292 "Entered %s.\n", __func__); 2293 2294 if (id_list == NULL) 2295 return QLA_FUNCTION_FAILED; 2296 2297 mcp->mb[0] = MBC_GET_ID_LIST; 2298 mcp->out_mb = MBX_0; 2299 if (IS_FWI2_CAPABLE(vha->hw)) { 2300 mcp->mb[2] = MSW(id_list_dma); 2301 mcp->mb[3] = LSW(id_list_dma); 2302 mcp->mb[6] = MSW(MSD(id_list_dma)); 2303 mcp->mb[7] = LSW(MSD(id_list_dma)); 2304 mcp->mb[8] = 0; 2305 mcp->mb[9] = vha->vp_idx; 2306 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2; 2307 } else { 2308 mcp->mb[1] = MSW(id_list_dma); 2309 mcp->mb[2] = LSW(id_list_dma); 2310 mcp->mb[3] = MSW(MSD(id_list_dma)); 2311 mcp->mb[6] = LSW(MSD(id_list_dma)); 2312 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1; 2313 } 2314 mcp->in_mb = MBX_1|MBX_0; 2315 mcp->tov = MBX_TOV_SECONDS; 2316 mcp->flags = 0; 2317 rval = qla2x00_mailbox_command(vha, mcp); 2318 2319 if (rval != QLA_SUCCESS) { 2320 /*EMPTY*/ 2321 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval); 2322 } else { 2323 *entries = mcp->mb[1]; 2324 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b, 2325 "Done %s.\n", __func__); 2326 } 2327 2328 return rval; 2329 } 2330 2331 /* 2332 * qla2x00_get_resource_cnts 2333 * Get current firmware resource counts. 2334 * 2335 * Input: 2336 * ha = adapter block pointer. 2337 * 2338 * Returns: 2339 * qla2x00 local function return status code. 2340 * 2341 * Context: 2342 * Kernel context. 2343 */ 2344 int 2345 qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt, 2346 uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt, 2347 uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs) 2348 { 2349 int rval; 2350 mbx_cmd_t mc; 2351 mbx_cmd_t *mcp = &mc; 2352 2353 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c, 2354 "Entered %s.\n", __func__); 2355 2356 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS; 2357 mcp->out_mb = MBX_0; 2358 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2359 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw)) 2360 mcp->in_mb |= MBX_12; 2361 mcp->tov = MBX_TOV_SECONDS; 2362 mcp->flags = 0; 2363 rval = qla2x00_mailbox_command(vha, mcp); 2364 2365 if (rval != QLA_SUCCESS) { 2366 /*EMPTY*/ 2367 ql_dbg(ql_dbg_mbx, vha, 0x107d, 2368 "Failed mb[0]=%x.\n", mcp->mb[0]); 2369 } else { 2370 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e, 2371 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x " 2372 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2], 2373 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10], 2374 mcp->mb[11], mcp->mb[12]); 2375 2376 if (cur_xchg_cnt) 2377 *cur_xchg_cnt = mcp->mb[3]; 2378 if (orig_xchg_cnt) 2379 *orig_xchg_cnt = mcp->mb[6]; 2380 if (cur_iocb_cnt) 2381 *cur_iocb_cnt = mcp->mb[7]; 2382 if (orig_iocb_cnt) 2383 *orig_iocb_cnt = mcp->mb[10]; 2384 if (vha->hw->flags.npiv_supported && max_npiv_vports) 2385 *max_npiv_vports = mcp->mb[11]; 2386 if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs) 2387 *max_fcfs = mcp->mb[12]; 2388 } 2389 2390 return (rval); 2391 } 2392 2393 /* 2394 * qla2x00_get_fcal_position_map 2395 * Get FCAL (LILP) position map using mailbox command 2396 * 2397 * Input: 2398 * ha = adapter state pointer. 2399 * pos_map = buffer pointer (can be NULL). 2400 * 2401 * Returns: 2402 * qla2x00 local function return status code. 2403 * 2404 * Context: 2405 * Kernel context. 2406 */ 2407 int 2408 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map) 2409 { 2410 int rval; 2411 mbx_cmd_t mc; 2412 mbx_cmd_t *mcp = &mc; 2413 char *pmap; 2414 dma_addr_t pmap_dma; 2415 struct qla_hw_data *ha = vha->hw; 2416 2417 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f, 2418 "Entered %s.\n", __func__); 2419 2420 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma); 2421 if (pmap == NULL) { 2422 ql_log(ql_log_warn, vha, 0x1080, 2423 "Memory alloc failed.\n"); 2424 return QLA_MEMORY_ALLOC_FAILED; 2425 } 2426 memset(pmap, 0, FCAL_MAP_SIZE); 2427 2428 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP; 2429 mcp->mb[2] = MSW(pmap_dma); 2430 mcp->mb[3] = LSW(pmap_dma); 2431 mcp->mb[6] = MSW(MSD(pmap_dma)); 2432 mcp->mb[7] = LSW(MSD(pmap_dma)); 2433 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2434 mcp->in_mb = MBX_1|MBX_0; 2435 mcp->buf_size = FCAL_MAP_SIZE; 2436 mcp->flags = MBX_DMA_IN; 2437 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2438 rval = qla2x00_mailbox_command(vha, mcp); 2439 2440 if (rval == QLA_SUCCESS) { 2441 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081, 2442 "mb0/mb1=%x/%X FC/AL position map size (%x).\n", 2443 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]); 2444 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d, 2445 pmap, pmap[0] + 1); 2446 2447 if (pos_map) 2448 memcpy(pos_map, pmap, FCAL_MAP_SIZE); 2449 } 2450 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma); 2451 2452 if (rval != QLA_SUCCESS) { 2453 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval); 2454 } else { 2455 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083, 2456 "Done %s.\n", __func__); 2457 } 2458 2459 return rval; 2460 } 2461 2462 /* 2463 * qla2x00_get_link_status 2464 * 2465 * Input: 2466 * ha = adapter block pointer. 2467 * loop_id = device loop ID. 2468 * ret_buf = pointer to link status return buffer. 2469 * 2470 * Returns: 2471 * 0 = success. 2472 * BIT_0 = mem alloc error. 2473 * BIT_1 = mailbox error. 2474 */ 2475 int 2476 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id, 2477 struct link_statistics *stats, dma_addr_t stats_dma) 2478 { 2479 int rval; 2480 mbx_cmd_t mc; 2481 mbx_cmd_t *mcp = &mc; 2482 uint32_t *siter, *diter, dwords; 2483 struct qla_hw_data *ha = vha->hw; 2484 2485 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084, 2486 "Entered %s.\n", __func__); 2487 2488 mcp->mb[0] = MBC_GET_LINK_STATUS; 2489 mcp->mb[2] = MSW(stats_dma); 2490 mcp->mb[3] = LSW(stats_dma); 2491 mcp->mb[6] = MSW(MSD(stats_dma)); 2492 mcp->mb[7] = LSW(MSD(stats_dma)); 2493 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2494 mcp->in_mb = MBX_0; 2495 if (IS_FWI2_CAPABLE(ha)) { 2496 mcp->mb[1] = loop_id; 2497 mcp->mb[4] = 0; 2498 mcp->mb[10] = 0; 2499 mcp->out_mb |= MBX_10|MBX_4|MBX_1; 2500 mcp->in_mb |= MBX_1; 2501 } else if (HAS_EXTENDED_IDS(ha)) { 2502 mcp->mb[1] = loop_id; 2503 mcp->mb[10] = 0; 2504 mcp->out_mb |= MBX_10|MBX_1; 2505 } else { 2506 mcp->mb[1] = loop_id << 8; 2507 mcp->out_mb |= MBX_1; 2508 } 2509 mcp->tov = MBX_TOV_SECONDS; 2510 mcp->flags = IOCTL_CMD; 2511 rval = qla2x00_mailbox_command(vha, mcp); 2512 2513 if (rval == QLA_SUCCESS) { 2514 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2515 ql_dbg(ql_dbg_mbx, vha, 0x1085, 2516 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2517 rval = QLA_FUNCTION_FAILED; 2518 } else { 2519 /* Copy over data -- firmware data is LE. */ 2520 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086, 2521 "Done %s.\n", __func__); 2522 dwords = offsetof(struct link_statistics, unused1) / 4; 2523 siter = diter = &stats->link_fail_cnt; 2524 while (dwords--) 2525 *diter++ = le32_to_cpu(*siter++); 2526 } 2527 } else { 2528 /* Failed. */ 2529 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval); 2530 } 2531 2532 return rval; 2533 } 2534 2535 int 2536 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats, 2537 dma_addr_t stats_dma) 2538 { 2539 int rval; 2540 mbx_cmd_t mc; 2541 mbx_cmd_t *mcp = &mc; 2542 uint32_t *siter, *diter, dwords; 2543 2544 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088, 2545 "Entered %s.\n", __func__); 2546 2547 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS; 2548 mcp->mb[2] = MSW(stats_dma); 2549 mcp->mb[3] = LSW(stats_dma); 2550 mcp->mb[6] = MSW(MSD(stats_dma)); 2551 mcp->mb[7] = LSW(MSD(stats_dma)); 2552 mcp->mb[8] = sizeof(struct link_statistics) / 4; 2553 mcp->mb[9] = vha->vp_idx; 2554 mcp->mb[10] = 0; 2555 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2556 mcp->in_mb = MBX_2|MBX_1|MBX_0; 2557 mcp->tov = MBX_TOV_SECONDS; 2558 mcp->flags = IOCTL_CMD; 2559 rval = qla2x00_mailbox_command(vha, mcp); 2560 2561 if (rval == QLA_SUCCESS) { 2562 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2563 ql_dbg(ql_dbg_mbx, vha, 0x1089, 2564 "Failed mb[0]=%x.\n", mcp->mb[0]); 2565 rval = QLA_FUNCTION_FAILED; 2566 } else { 2567 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a, 2568 "Done %s.\n", __func__); 2569 /* Copy over data -- firmware data is LE. */ 2570 dwords = sizeof(struct link_statistics) / 4; 2571 siter = diter = &stats->link_fail_cnt; 2572 while (dwords--) 2573 *diter++ = le32_to_cpu(*siter++); 2574 } 2575 } else { 2576 /* Failed. */ 2577 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval); 2578 } 2579 2580 return rval; 2581 } 2582 2583 int 2584 qla24xx_abort_command(srb_t *sp) 2585 { 2586 int rval; 2587 unsigned long flags = 0; 2588 2589 struct abort_entry_24xx *abt; 2590 dma_addr_t abt_dma; 2591 uint32_t handle; 2592 fc_port_t *fcport = sp->fcport; 2593 struct scsi_qla_host *vha = fcport->vha; 2594 struct qla_hw_data *ha = vha->hw; 2595 struct req_que *req = vha->req; 2596 2597 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c, 2598 "Entered %s.\n", __func__); 2599 2600 if (ql2xasynctmfenable) 2601 return qla24xx_async_abort_command(sp); 2602 2603 spin_lock_irqsave(&ha->hardware_lock, flags); 2604 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 2605 if (req->outstanding_cmds[handle] == sp) 2606 break; 2607 } 2608 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2609 if (handle == req->num_outstanding_cmds) { 2610 /* Command not found. */ 2611 return QLA_FUNCTION_FAILED; 2612 } 2613 2614 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma); 2615 if (abt == NULL) { 2616 ql_log(ql_log_warn, vha, 0x108d, 2617 "Failed to allocate abort IOCB.\n"); 2618 return QLA_MEMORY_ALLOC_FAILED; 2619 } 2620 memset(abt, 0, sizeof(struct abort_entry_24xx)); 2621 2622 abt->entry_type = ABORT_IOCB_TYPE; 2623 abt->entry_count = 1; 2624 abt->handle = MAKE_HANDLE(req->id, abt->handle); 2625 abt->nport_handle = cpu_to_le16(fcport->loop_id); 2626 abt->handle_to_abort = MAKE_HANDLE(req->id, handle); 2627 abt->port_id[0] = fcport->d_id.b.al_pa; 2628 abt->port_id[1] = fcport->d_id.b.area; 2629 abt->port_id[2] = fcport->d_id.b.domain; 2630 abt->vp_index = fcport->vha->vp_idx; 2631 2632 abt->req_que_no = cpu_to_le16(req->id); 2633 2634 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0); 2635 if (rval != QLA_SUCCESS) { 2636 ql_dbg(ql_dbg_mbx, vha, 0x108e, 2637 "Failed to issue IOCB (%x).\n", rval); 2638 } else if (abt->entry_status != 0) { 2639 ql_dbg(ql_dbg_mbx, vha, 0x108f, 2640 "Failed to complete IOCB -- error status (%x).\n", 2641 abt->entry_status); 2642 rval = QLA_FUNCTION_FAILED; 2643 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) { 2644 ql_dbg(ql_dbg_mbx, vha, 0x1090, 2645 "Failed to complete IOCB -- completion status (%x).\n", 2646 le16_to_cpu(abt->nport_handle)); 2647 rval = QLA_FUNCTION_FAILED; 2648 } else { 2649 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091, 2650 "Done %s.\n", __func__); 2651 } 2652 2653 dma_pool_free(ha->s_dma_pool, abt, abt_dma); 2654 2655 return rval; 2656 } 2657 2658 struct tsk_mgmt_cmd { 2659 union { 2660 struct tsk_mgmt_entry tsk; 2661 struct sts_entry_24xx sts; 2662 } p; 2663 }; 2664 2665 static int 2666 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport, 2667 unsigned int l, int tag) 2668 { 2669 int rval, rval2; 2670 struct tsk_mgmt_cmd *tsk; 2671 struct sts_entry_24xx *sts; 2672 dma_addr_t tsk_dma; 2673 scsi_qla_host_t *vha; 2674 struct qla_hw_data *ha; 2675 struct req_que *req; 2676 struct rsp_que *rsp; 2677 2678 vha = fcport->vha; 2679 ha = vha->hw; 2680 req = vha->req; 2681 2682 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092, 2683 "Entered %s.\n", __func__); 2684 2685 if (ha->flags.cpu_affinity_enabled) 2686 rsp = ha->rsp_q_map[tag + 1]; 2687 else 2688 rsp = req->rsp; 2689 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma); 2690 if (tsk == NULL) { 2691 ql_log(ql_log_warn, vha, 0x1093, 2692 "Failed to allocate task management IOCB.\n"); 2693 return QLA_MEMORY_ALLOC_FAILED; 2694 } 2695 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd)); 2696 2697 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE; 2698 tsk->p.tsk.entry_count = 1; 2699 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle); 2700 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id); 2701 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2); 2702 tsk->p.tsk.control_flags = cpu_to_le32(type); 2703 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa; 2704 tsk->p.tsk.port_id[1] = fcport->d_id.b.area; 2705 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain; 2706 tsk->p.tsk.vp_index = fcport->vha->vp_idx; 2707 if (type == TCF_LUN_RESET) { 2708 int_to_scsilun(l, &tsk->p.tsk.lun); 2709 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun, 2710 sizeof(tsk->p.tsk.lun)); 2711 } 2712 2713 sts = &tsk->p.sts; 2714 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0); 2715 if (rval != QLA_SUCCESS) { 2716 ql_dbg(ql_dbg_mbx, vha, 0x1094, 2717 "Failed to issue %s reset IOCB (%x).\n", name, rval); 2718 } else if (sts->entry_status != 0) { 2719 ql_dbg(ql_dbg_mbx, vha, 0x1095, 2720 "Failed to complete IOCB -- error status (%x).\n", 2721 sts->entry_status); 2722 rval = QLA_FUNCTION_FAILED; 2723 } else if (sts->comp_status != 2724 __constant_cpu_to_le16(CS_COMPLETE)) { 2725 ql_dbg(ql_dbg_mbx, vha, 0x1096, 2726 "Failed to complete IOCB -- completion status (%x).\n", 2727 le16_to_cpu(sts->comp_status)); 2728 rval = QLA_FUNCTION_FAILED; 2729 } else if (le16_to_cpu(sts->scsi_status) & 2730 SS_RESPONSE_INFO_LEN_VALID) { 2731 if (le32_to_cpu(sts->rsp_data_len) < 4) { 2732 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097, 2733 "Ignoring inconsistent data length -- not enough " 2734 "response info (%d).\n", 2735 le32_to_cpu(sts->rsp_data_len)); 2736 } else if (sts->data[3]) { 2737 ql_dbg(ql_dbg_mbx, vha, 0x1098, 2738 "Failed to complete IOCB -- response (%x).\n", 2739 sts->data[3]); 2740 rval = QLA_FUNCTION_FAILED; 2741 } 2742 } 2743 2744 /* Issue marker IOCB. */ 2745 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 2746 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID); 2747 if (rval2 != QLA_SUCCESS) { 2748 ql_dbg(ql_dbg_mbx, vha, 0x1099, 2749 "Failed to issue marker IOCB (%x).\n", rval2); 2750 } else { 2751 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a, 2752 "Done %s.\n", __func__); 2753 } 2754 2755 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma); 2756 2757 return rval; 2758 } 2759 2760 int 2761 qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag) 2762 { 2763 struct qla_hw_data *ha = fcport->vha->hw; 2764 2765 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 2766 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag); 2767 2768 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag); 2769 } 2770 2771 int 2772 qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag) 2773 { 2774 struct qla_hw_data *ha = fcport->vha->hw; 2775 2776 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 2777 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag); 2778 2779 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag); 2780 } 2781 2782 int 2783 qla2x00_system_error(scsi_qla_host_t *vha) 2784 { 2785 int rval; 2786 mbx_cmd_t mc; 2787 mbx_cmd_t *mcp = &mc; 2788 struct qla_hw_data *ha = vha->hw; 2789 2790 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha)) 2791 return QLA_FUNCTION_FAILED; 2792 2793 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b, 2794 "Entered %s.\n", __func__); 2795 2796 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR; 2797 mcp->out_mb = MBX_0; 2798 mcp->in_mb = MBX_0; 2799 mcp->tov = 5; 2800 mcp->flags = 0; 2801 rval = qla2x00_mailbox_command(vha, mcp); 2802 2803 if (rval != QLA_SUCCESS) { 2804 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval); 2805 } else { 2806 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d, 2807 "Done %s.\n", __func__); 2808 } 2809 2810 return rval; 2811 } 2812 2813 int 2814 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data) 2815 { 2816 int rval; 2817 mbx_cmd_t mc; 2818 mbx_cmd_t *mcp = &mc; 2819 2820 if (!IS_QLA2031(vha->hw)) 2821 return QLA_FUNCTION_FAILED; 2822 2823 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182, 2824 "Entered %s.\n", __func__); 2825 2826 mcp->mb[0] = MBC_WRITE_SERDES; 2827 mcp->mb[1] = addr; 2828 mcp->mb[2] = data & 0xff; 2829 mcp->mb[3] = 0; 2830 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2831 mcp->in_mb = MBX_0; 2832 mcp->tov = MBX_TOV_SECONDS; 2833 mcp->flags = 0; 2834 rval = qla2x00_mailbox_command(vha, mcp); 2835 2836 if (rval != QLA_SUCCESS) { 2837 ql_dbg(ql_dbg_mbx, vha, 0x1183, 2838 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2839 } else { 2840 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184, 2841 "Done %s.\n", __func__); 2842 } 2843 2844 return rval; 2845 } 2846 2847 int 2848 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data) 2849 { 2850 int rval; 2851 mbx_cmd_t mc; 2852 mbx_cmd_t *mcp = &mc; 2853 2854 if (!IS_QLA2031(vha->hw)) 2855 return QLA_FUNCTION_FAILED; 2856 2857 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185, 2858 "Entered %s.\n", __func__); 2859 2860 mcp->mb[0] = MBC_READ_SERDES; 2861 mcp->mb[1] = addr; 2862 mcp->mb[3] = 0; 2863 mcp->out_mb = MBX_3|MBX_1|MBX_0; 2864 mcp->in_mb = MBX_1|MBX_0; 2865 mcp->tov = MBX_TOV_SECONDS; 2866 mcp->flags = 0; 2867 rval = qla2x00_mailbox_command(vha, mcp); 2868 2869 *data = mcp->mb[1] & 0xff; 2870 2871 if (rval != QLA_SUCCESS) { 2872 ql_dbg(ql_dbg_mbx, vha, 0x1186, 2873 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2874 } else { 2875 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187, 2876 "Done %s.\n", __func__); 2877 } 2878 2879 return rval; 2880 } 2881 2882 /** 2883 * qla2x00_set_serdes_params() - 2884 * @ha: HA context 2885 * 2886 * Returns 2887 */ 2888 int 2889 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g, 2890 uint16_t sw_em_2g, uint16_t sw_em_4g) 2891 { 2892 int rval; 2893 mbx_cmd_t mc; 2894 mbx_cmd_t *mcp = &mc; 2895 2896 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e, 2897 "Entered %s.\n", __func__); 2898 2899 mcp->mb[0] = MBC_SERDES_PARAMS; 2900 mcp->mb[1] = BIT_0; 2901 mcp->mb[2] = sw_em_1g | BIT_15; 2902 mcp->mb[3] = sw_em_2g | BIT_15; 2903 mcp->mb[4] = sw_em_4g | BIT_15; 2904 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 2905 mcp->in_mb = MBX_0; 2906 mcp->tov = MBX_TOV_SECONDS; 2907 mcp->flags = 0; 2908 rval = qla2x00_mailbox_command(vha, mcp); 2909 2910 if (rval != QLA_SUCCESS) { 2911 /*EMPTY*/ 2912 ql_dbg(ql_dbg_mbx, vha, 0x109f, 2913 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2914 } else { 2915 /*EMPTY*/ 2916 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0, 2917 "Done %s.\n", __func__); 2918 } 2919 2920 return rval; 2921 } 2922 2923 int 2924 qla2x00_stop_firmware(scsi_qla_host_t *vha) 2925 { 2926 int rval; 2927 mbx_cmd_t mc; 2928 mbx_cmd_t *mcp = &mc; 2929 2930 if (!IS_FWI2_CAPABLE(vha->hw)) 2931 return QLA_FUNCTION_FAILED; 2932 2933 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1, 2934 "Entered %s.\n", __func__); 2935 2936 mcp->mb[0] = MBC_STOP_FIRMWARE; 2937 mcp->mb[1] = 0; 2938 mcp->out_mb = MBX_1|MBX_0; 2939 mcp->in_mb = MBX_0; 2940 mcp->tov = 5; 2941 mcp->flags = 0; 2942 rval = qla2x00_mailbox_command(vha, mcp); 2943 2944 if (rval != QLA_SUCCESS) { 2945 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval); 2946 if (mcp->mb[0] == MBS_INVALID_COMMAND) 2947 rval = QLA_INVALID_COMMAND; 2948 } else { 2949 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3, 2950 "Done %s.\n", __func__); 2951 } 2952 2953 return rval; 2954 } 2955 2956 int 2957 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma, 2958 uint16_t buffers) 2959 { 2960 int rval; 2961 mbx_cmd_t mc; 2962 mbx_cmd_t *mcp = &mc; 2963 2964 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4, 2965 "Entered %s.\n", __func__); 2966 2967 if (!IS_FWI2_CAPABLE(vha->hw)) 2968 return QLA_FUNCTION_FAILED; 2969 2970 if (unlikely(pci_channel_offline(vha->hw->pdev))) 2971 return QLA_FUNCTION_FAILED; 2972 2973 mcp->mb[0] = MBC_TRACE_CONTROL; 2974 mcp->mb[1] = TC_EFT_ENABLE; 2975 mcp->mb[2] = LSW(eft_dma); 2976 mcp->mb[3] = MSW(eft_dma); 2977 mcp->mb[4] = LSW(MSD(eft_dma)); 2978 mcp->mb[5] = MSW(MSD(eft_dma)); 2979 mcp->mb[6] = buffers; 2980 mcp->mb[7] = TC_AEN_DISABLE; 2981 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 2982 mcp->in_mb = MBX_1|MBX_0; 2983 mcp->tov = MBX_TOV_SECONDS; 2984 mcp->flags = 0; 2985 rval = qla2x00_mailbox_command(vha, mcp); 2986 if (rval != QLA_SUCCESS) { 2987 ql_dbg(ql_dbg_mbx, vha, 0x10a5, 2988 "Failed=%x mb[0]=%x mb[1]=%x.\n", 2989 rval, mcp->mb[0], mcp->mb[1]); 2990 } else { 2991 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6, 2992 "Done %s.\n", __func__); 2993 } 2994 2995 return rval; 2996 } 2997 2998 int 2999 qla2x00_disable_eft_trace(scsi_qla_host_t *vha) 3000 { 3001 int rval; 3002 mbx_cmd_t mc; 3003 mbx_cmd_t *mcp = &mc; 3004 3005 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7, 3006 "Entered %s.\n", __func__); 3007 3008 if (!IS_FWI2_CAPABLE(vha->hw)) 3009 return QLA_FUNCTION_FAILED; 3010 3011 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3012 return QLA_FUNCTION_FAILED; 3013 3014 mcp->mb[0] = MBC_TRACE_CONTROL; 3015 mcp->mb[1] = TC_EFT_DISABLE; 3016 mcp->out_mb = MBX_1|MBX_0; 3017 mcp->in_mb = MBX_1|MBX_0; 3018 mcp->tov = MBX_TOV_SECONDS; 3019 mcp->flags = 0; 3020 rval = qla2x00_mailbox_command(vha, mcp); 3021 if (rval != QLA_SUCCESS) { 3022 ql_dbg(ql_dbg_mbx, vha, 0x10a8, 3023 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3024 rval, mcp->mb[0], mcp->mb[1]); 3025 } else { 3026 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9, 3027 "Done %s.\n", __func__); 3028 } 3029 3030 return rval; 3031 } 3032 3033 int 3034 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma, 3035 uint16_t buffers, uint16_t *mb, uint32_t *dwords) 3036 { 3037 int rval; 3038 mbx_cmd_t mc; 3039 mbx_cmd_t *mcp = &mc; 3040 3041 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa, 3042 "Entered %s.\n", __func__); 3043 3044 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) && 3045 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw)) 3046 return QLA_FUNCTION_FAILED; 3047 3048 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3049 return QLA_FUNCTION_FAILED; 3050 3051 mcp->mb[0] = MBC_TRACE_CONTROL; 3052 mcp->mb[1] = TC_FCE_ENABLE; 3053 mcp->mb[2] = LSW(fce_dma); 3054 mcp->mb[3] = MSW(fce_dma); 3055 mcp->mb[4] = LSW(MSD(fce_dma)); 3056 mcp->mb[5] = MSW(MSD(fce_dma)); 3057 mcp->mb[6] = buffers; 3058 mcp->mb[7] = TC_AEN_DISABLE; 3059 mcp->mb[8] = 0; 3060 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE; 3061 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE; 3062 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3063 MBX_1|MBX_0; 3064 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3065 mcp->tov = MBX_TOV_SECONDS; 3066 mcp->flags = 0; 3067 rval = qla2x00_mailbox_command(vha, mcp); 3068 if (rval != QLA_SUCCESS) { 3069 ql_dbg(ql_dbg_mbx, vha, 0x10ab, 3070 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3071 rval, mcp->mb[0], mcp->mb[1]); 3072 } else { 3073 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac, 3074 "Done %s.\n", __func__); 3075 3076 if (mb) 3077 memcpy(mb, mcp->mb, 8 * sizeof(*mb)); 3078 if (dwords) 3079 *dwords = buffers; 3080 } 3081 3082 return rval; 3083 } 3084 3085 int 3086 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd) 3087 { 3088 int rval; 3089 mbx_cmd_t mc; 3090 mbx_cmd_t *mcp = &mc; 3091 3092 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad, 3093 "Entered %s.\n", __func__); 3094 3095 if (!IS_FWI2_CAPABLE(vha->hw)) 3096 return QLA_FUNCTION_FAILED; 3097 3098 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3099 return QLA_FUNCTION_FAILED; 3100 3101 mcp->mb[0] = MBC_TRACE_CONTROL; 3102 mcp->mb[1] = TC_FCE_DISABLE; 3103 mcp->mb[2] = TC_FCE_DISABLE_TRACE; 3104 mcp->out_mb = MBX_2|MBX_1|MBX_0; 3105 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3106 MBX_1|MBX_0; 3107 mcp->tov = MBX_TOV_SECONDS; 3108 mcp->flags = 0; 3109 rval = qla2x00_mailbox_command(vha, mcp); 3110 if (rval != QLA_SUCCESS) { 3111 ql_dbg(ql_dbg_mbx, vha, 0x10ae, 3112 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3113 rval, mcp->mb[0], mcp->mb[1]); 3114 } else { 3115 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af, 3116 "Done %s.\n", __func__); 3117 3118 if (wr) 3119 *wr = (uint64_t) mcp->mb[5] << 48 | 3120 (uint64_t) mcp->mb[4] << 32 | 3121 (uint64_t) mcp->mb[3] << 16 | 3122 (uint64_t) mcp->mb[2]; 3123 if (rd) 3124 *rd = (uint64_t) mcp->mb[9] << 48 | 3125 (uint64_t) mcp->mb[8] << 32 | 3126 (uint64_t) mcp->mb[7] << 16 | 3127 (uint64_t) mcp->mb[6]; 3128 } 3129 3130 return rval; 3131 } 3132 3133 int 3134 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3135 uint16_t *port_speed, uint16_t *mb) 3136 { 3137 int rval; 3138 mbx_cmd_t mc; 3139 mbx_cmd_t *mcp = &mc; 3140 3141 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0, 3142 "Entered %s.\n", __func__); 3143 3144 if (!IS_IIDMA_CAPABLE(vha->hw)) 3145 return QLA_FUNCTION_FAILED; 3146 3147 mcp->mb[0] = MBC_PORT_PARAMS; 3148 mcp->mb[1] = loop_id; 3149 mcp->mb[2] = mcp->mb[3] = 0; 3150 mcp->mb[9] = vha->vp_idx; 3151 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3152 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3153 mcp->tov = MBX_TOV_SECONDS; 3154 mcp->flags = 0; 3155 rval = qla2x00_mailbox_command(vha, mcp); 3156 3157 /* Return mailbox statuses. */ 3158 if (mb != NULL) { 3159 mb[0] = mcp->mb[0]; 3160 mb[1] = mcp->mb[1]; 3161 mb[3] = mcp->mb[3]; 3162 } 3163 3164 if (rval != QLA_SUCCESS) { 3165 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval); 3166 } else { 3167 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2, 3168 "Done %s.\n", __func__); 3169 if (port_speed) 3170 *port_speed = mcp->mb[3]; 3171 } 3172 3173 return rval; 3174 } 3175 3176 int 3177 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3178 uint16_t port_speed, uint16_t *mb) 3179 { 3180 int rval; 3181 mbx_cmd_t mc; 3182 mbx_cmd_t *mcp = &mc; 3183 3184 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3, 3185 "Entered %s.\n", __func__); 3186 3187 if (!IS_IIDMA_CAPABLE(vha->hw)) 3188 return QLA_FUNCTION_FAILED; 3189 3190 mcp->mb[0] = MBC_PORT_PARAMS; 3191 mcp->mb[1] = loop_id; 3192 mcp->mb[2] = BIT_0; 3193 if (IS_CNA_CAPABLE(vha->hw)) 3194 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); 3195 else 3196 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); 3197 mcp->mb[9] = vha->vp_idx; 3198 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3199 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3200 mcp->tov = MBX_TOV_SECONDS; 3201 mcp->flags = 0; 3202 rval = qla2x00_mailbox_command(vha, mcp); 3203 3204 /* Return mailbox statuses. */ 3205 if (mb != NULL) { 3206 mb[0] = mcp->mb[0]; 3207 mb[1] = mcp->mb[1]; 3208 mb[3] = mcp->mb[3]; 3209 } 3210 3211 if (rval != QLA_SUCCESS) { 3212 ql_dbg(ql_dbg_mbx, vha, 0x10b4, 3213 "Failed=%x.\n", rval); 3214 } else { 3215 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5, 3216 "Done %s.\n", __func__); 3217 } 3218 3219 return rval; 3220 } 3221 3222 void 3223 qla24xx_report_id_acquisition(scsi_qla_host_t *vha, 3224 struct vp_rpt_id_entry_24xx *rptid_entry) 3225 { 3226 uint8_t vp_idx; 3227 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx); 3228 struct qla_hw_data *ha = vha->hw; 3229 scsi_qla_host_t *vp; 3230 unsigned long flags; 3231 int found; 3232 3233 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6, 3234 "Entered %s.\n", __func__); 3235 3236 if (rptid_entry->entry_status != 0) 3237 return; 3238 3239 if (rptid_entry->format == 0) { 3240 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7, 3241 "Format 0 : Number of VPs setup %d, number of " 3242 "VPs acquired %d.\n", 3243 MSB(le16_to_cpu(rptid_entry->vp_count)), 3244 LSB(le16_to_cpu(rptid_entry->vp_count))); 3245 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8, 3246 "Primary port id %02x%02x%02x.\n", 3247 rptid_entry->port_id[2], rptid_entry->port_id[1], 3248 rptid_entry->port_id[0]); 3249 } else if (rptid_entry->format == 1) { 3250 vp_idx = LSB(stat); 3251 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9, 3252 "Format 1: VP[%d] enabled - status %d - with " 3253 "port id %02x%02x%02x.\n", vp_idx, MSB(stat), 3254 rptid_entry->port_id[2], rptid_entry->port_id[1], 3255 rptid_entry->port_id[0]); 3256 3257 vp = vha; 3258 if (vp_idx == 0 && (MSB(stat) != 1)) 3259 goto reg_needed; 3260 3261 if (MSB(stat) != 0 && MSB(stat) != 2) { 3262 ql_dbg(ql_dbg_mbx, vha, 0x10ba, 3263 "Could not acquire ID for VP[%d].\n", vp_idx); 3264 return; 3265 } 3266 3267 found = 0; 3268 spin_lock_irqsave(&ha->vport_slock, flags); 3269 list_for_each_entry(vp, &ha->vp_list, list) { 3270 if (vp_idx == vp->vp_idx) { 3271 found = 1; 3272 break; 3273 } 3274 } 3275 spin_unlock_irqrestore(&ha->vport_slock, flags); 3276 3277 if (!found) 3278 return; 3279 3280 vp->d_id.b.domain = rptid_entry->port_id[2]; 3281 vp->d_id.b.area = rptid_entry->port_id[1]; 3282 vp->d_id.b.al_pa = rptid_entry->port_id[0]; 3283 3284 /* 3285 * Cannot configure here as we are still sitting on the 3286 * response queue. Handle it in dpc context. 3287 */ 3288 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags); 3289 3290 reg_needed: 3291 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags); 3292 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags); 3293 set_bit(VP_DPC_NEEDED, &vha->dpc_flags); 3294 qla2xxx_wake_dpc(vha); 3295 } 3296 } 3297 3298 /* 3299 * qla24xx_modify_vp_config 3300 * Change VP configuration for vha 3301 * 3302 * Input: 3303 * vha = adapter block pointer. 3304 * 3305 * Returns: 3306 * qla2xxx local function return status code. 3307 * 3308 * Context: 3309 * Kernel context. 3310 */ 3311 int 3312 qla24xx_modify_vp_config(scsi_qla_host_t *vha) 3313 { 3314 int rval; 3315 struct vp_config_entry_24xx *vpmod; 3316 dma_addr_t vpmod_dma; 3317 struct qla_hw_data *ha = vha->hw; 3318 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3319 3320 /* This can be called by the parent */ 3321 3322 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb, 3323 "Entered %s.\n", __func__); 3324 3325 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma); 3326 if (!vpmod) { 3327 ql_log(ql_log_warn, vha, 0x10bc, 3328 "Failed to allocate modify VP IOCB.\n"); 3329 return QLA_MEMORY_ALLOC_FAILED; 3330 } 3331 3332 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx)); 3333 vpmod->entry_type = VP_CONFIG_IOCB_TYPE; 3334 vpmod->entry_count = 1; 3335 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS; 3336 vpmod->vp_count = 1; 3337 vpmod->vp_index1 = vha->vp_idx; 3338 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; 3339 3340 qlt_modify_vp_config(vha, vpmod); 3341 3342 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE); 3343 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE); 3344 vpmod->entry_count = 1; 3345 3346 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0); 3347 if (rval != QLA_SUCCESS) { 3348 ql_dbg(ql_dbg_mbx, vha, 0x10bd, 3349 "Failed to issue VP config IOCB (%x).\n", rval); 3350 } else if (vpmod->comp_status != 0) { 3351 ql_dbg(ql_dbg_mbx, vha, 0x10be, 3352 "Failed to complete IOCB -- error status (%x).\n", 3353 vpmod->comp_status); 3354 rval = QLA_FUNCTION_FAILED; 3355 } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 3356 ql_dbg(ql_dbg_mbx, vha, 0x10bf, 3357 "Failed to complete IOCB -- completion status (%x).\n", 3358 le16_to_cpu(vpmod->comp_status)); 3359 rval = QLA_FUNCTION_FAILED; 3360 } else { 3361 /* EMPTY */ 3362 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0, 3363 "Done %s.\n", __func__); 3364 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING); 3365 } 3366 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma); 3367 3368 return rval; 3369 } 3370 3371 /* 3372 * qla24xx_control_vp 3373 * Enable a virtual port for given host 3374 * 3375 * Input: 3376 * ha = adapter block pointer. 3377 * vhba = virtual adapter (unused) 3378 * index = index number for enabled VP 3379 * 3380 * Returns: 3381 * qla2xxx local function return status code. 3382 * 3383 * Context: 3384 * Kernel context. 3385 */ 3386 int 3387 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd) 3388 { 3389 int rval; 3390 int map, pos; 3391 struct vp_ctrl_entry_24xx *vce; 3392 dma_addr_t vce_dma; 3393 struct qla_hw_data *ha = vha->hw; 3394 int vp_index = vha->vp_idx; 3395 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3396 3397 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1, 3398 "Entered %s enabling index %d.\n", __func__, vp_index); 3399 3400 if (vp_index == 0 || vp_index >= ha->max_npiv_vports) 3401 return QLA_PARAMETER_ERROR; 3402 3403 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma); 3404 if (!vce) { 3405 ql_log(ql_log_warn, vha, 0x10c2, 3406 "Failed to allocate VP control IOCB.\n"); 3407 return QLA_MEMORY_ALLOC_FAILED; 3408 } 3409 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx)); 3410 3411 vce->entry_type = VP_CTRL_IOCB_TYPE; 3412 vce->entry_count = 1; 3413 vce->command = cpu_to_le16(cmd); 3414 vce->vp_count = __constant_cpu_to_le16(1); 3415 3416 /* index map in firmware starts with 1; decrement index 3417 * this is ok as we never use index 0 3418 */ 3419 map = (vp_index - 1) / 8; 3420 pos = (vp_index - 1) & 7; 3421 mutex_lock(&ha->vport_lock); 3422 vce->vp_idx_map[map] |= 1 << pos; 3423 mutex_unlock(&ha->vport_lock); 3424 3425 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0); 3426 if (rval != QLA_SUCCESS) { 3427 ql_dbg(ql_dbg_mbx, vha, 0x10c3, 3428 "Failed to issue VP control IOCB (%x).\n", rval); 3429 } else if (vce->entry_status != 0) { 3430 ql_dbg(ql_dbg_mbx, vha, 0x10c4, 3431 "Failed to complete IOCB -- error status (%x).\n", 3432 vce->entry_status); 3433 rval = QLA_FUNCTION_FAILED; 3434 } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 3435 ql_dbg(ql_dbg_mbx, vha, 0x10c5, 3436 "Failed to complet IOCB -- completion status (%x).\n", 3437 le16_to_cpu(vce->comp_status)); 3438 rval = QLA_FUNCTION_FAILED; 3439 } else { 3440 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6, 3441 "Done %s.\n", __func__); 3442 } 3443 3444 dma_pool_free(ha->s_dma_pool, vce, vce_dma); 3445 3446 return rval; 3447 } 3448 3449 /* 3450 * qla2x00_send_change_request 3451 * Receive or disable RSCN request from fabric controller 3452 * 3453 * Input: 3454 * ha = adapter block pointer 3455 * format = registration format: 3456 * 0 - Reserved 3457 * 1 - Fabric detected registration 3458 * 2 - N_port detected registration 3459 * 3 - Full registration 3460 * FF - clear registration 3461 * vp_idx = Virtual port index 3462 * 3463 * Returns: 3464 * qla2x00 local function return status code. 3465 * 3466 * Context: 3467 * Kernel Context 3468 */ 3469 3470 int 3471 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format, 3472 uint16_t vp_idx) 3473 { 3474 int rval; 3475 mbx_cmd_t mc; 3476 mbx_cmd_t *mcp = &mc; 3477 3478 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7, 3479 "Entered %s.\n", __func__); 3480 3481 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST; 3482 mcp->mb[1] = format; 3483 mcp->mb[9] = vp_idx; 3484 mcp->out_mb = MBX_9|MBX_1|MBX_0; 3485 mcp->in_mb = MBX_0|MBX_1; 3486 mcp->tov = MBX_TOV_SECONDS; 3487 mcp->flags = 0; 3488 rval = qla2x00_mailbox_command(vha, mcp); 3489 3490 if (rval == QLA_SUCCESS) { 3491 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 3492 rval = BIT_1; 3493 } 3494 } else 3495 rval = BIT_1; 3496 3497 return rval; 3498 } 3499 3500 int 3501 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 3502 uint32_t size) 3503 { 3504 int rval; 3505 mbx_cmd_t mc; 3506 mbx_cmd_t *mcp = &mc; 3507 3508 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009, 3509 "Entered %s.\n", __func__); 3510 3511 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) { 3512 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 3513 mcp->mb[8] = MSW(addr); 3514 mcp->out_mb = MBX_8|MBX_0; 3515 } else { 3516 mcp->mb[0] = MBC_DUMP_RISC_RAM; 3517 mcp->out_mb = MBX_0; 3518 } 3519 mcp->mb[1] = LSW(addr); 3520 mcp->mb[2] = MSW(req_dma); 3521 mcp->mb[3] = LSW(req_dma); 3522 mcp->mb[6] = MSW(MSD(req_dma)); 3523 mcp->mb[7] = LSW(MSD(req_dma)); 3524 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 3525 if (IS_FWI2_CAPABLE(vha->hw)) { 3526 mcp->mb[4] = MSW(size); 3527 mcp->mb[5] = LSW(size); 3528 mcp->out_mb |= MBX_5|MBX_4; 3529 } else { 3530 mcp->mb[4] = LSW(size); 3531 mcp->out_mb |= MBX_4; 3532 } 3533 3534 mcp->in_mb = MBX_0; 3535 mcp->tov = MBX_TOV_SECONDS; 3536 mcp->flags = 0; 3537 rval = qla2x00_mailbox_command(vha, mcp); 3538 3539 if (rval != QLA_SUCCESS) { 3540 ql_dbg(ql_dbg_mbx, vha, 0x1008, 3541 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3542 } else { 3543 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007, 3544 "Done %s.\n", __func__); 3545 } 3546 3547 return rval; 3548 } 3549 /* 84XX Support **************************************************************/ 3550 3551 struct cs84xx_mgmt_cmd { 3552 union { 3553 struct verify_chip_entry_84xx req; 3554 struct verify_chip_rsp_84xx rsp; 3555 } p; 3556 }; 3557 3558 int 3559 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status) 3560 { 3561 int rval, retry; 3562 struct cs84xx_mgmt_cmd *mn; 3563 dma_addr_t mn_dma; 3564 uint16_t options; 3565 unsigned long flags; 3566 struct qla_hw_data *ha = vha->hw; 3567 3568 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8, 3569 "Entered %s.\n", __func__); 3570 3571 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma); 3572 if (mn == NULL) { 3573 return QLA_MEMORY_ALLOC_FAILED; 3574 } 3575 3576 /* Force Update? */ 3577 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0; 3578 /* Diagnostic firmware? */ 3579 /* options |= MENLO_DIAG_FW; */ 3580 /* We update the firmware with only one data sequence. */ 3581 options |= VCO_END_OF_DATA; 3582 3583 do { 3584 retry = 0; 3585 memset(mn, 0, sizeof(*mn)); 3586 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE; 3587 mn->p.req.entry_count = 1; 3588 mn->p.req.options = cpu_to_le16(options); 3589 3590 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c, 3591 "Dump of Verify Request.\n"); 3592 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e, 3593 (uint8_t *)mn, sizeof(*mn)); 3594 3595 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120); 3596 if (rval != QLA_SUCCESS) { 3597 ql_dbg(ql_dbg_mbx, vha, 0x10cb, 3598 "Failed to issue verify IOCB (%x).\n", rval); 3599 goto verify_done; 3600 } 3601 3602 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110, 3603 "Dump of Verify Response.\n"); 3604 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118, 3605 (uint8_t *)mn, sizeof(*mn)); 3606 3607 status[0] = le16_to_cpu(mn->p.rsp.comp_status); 3608 status[1] = status[0] == CS_VCS_CHIP_FAILURE ? 3609 le16_to_cpu(mn->p.rsp.failure_code) : 0; 3610 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce, 3611 "cs=%x fc=%x.\n", status[0], status[1]); 3612 3613 if (status[0] != CS_COMPLETE) { 3614 rval = QLA_FUNCTION_FAILED; 3615 if (!(options & VCO_DONT_UPDATE_FW)) { 3616 ql_dbg(ql_dbg_mbx, vha, 0x10cf, 3617 "Firmware update failed. Retrying " 3618 "without update firmware.\n"); 3619 options |= VCO_DONT_UPDATE_FW; 3620 options &= ~VCO_FORCE_UPDATE; 3621 retry = 1; 3622 } 3623 } else { 3624 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0, 3625 "Firmware updated to %x.\n", 3626 le32_to_cpu(mn->p.rsp.fw_ver)); 3627 3628 /* NOTE: we only update OP firmware. */ 3629 spin_lock_irqsave(&ha->cs84xx->access_lock, flags); 3630 ha->cs84xx->op_fw_version = 3631 le32_to_cpu(mn->p.rsp.fw_ver); 3632 spin_unlock_irqrestore(&ha->cs84xx->access_lock, 3633 flags); 3634 } 3635 } while (retry); 3636 3637 verify_done: 3638 dma_pool_free(ha->s_dma_pool, mn, mn_dma); 3639 3640 if (rval != QLA_SUCCESS) { 3641 ql_dbg(ql_dbg_mbx, vha, 0x10d1, 3642 "Failed=%x.\n", rval); 3643 } else { 3644 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2, 3645 "Done %s.\n", __func__); 3646 } 3647 3648 return rval; 3649 } 3650 3651 int 3652 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req) 3653 { 3654 int rval; 3655 unsigned long flags; 3656 mbx_cmd_t mc; 3657 mbx_cmd_t *mcp = &mc; 3658 struct qla_hw_data *ha = vha->hw; 3659 3660 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3, 3661 "Entered %s.\n", __func__); 3662 3663 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 3664 mcp->mb[1] = req->options; 3665 mcp->mb[2] = MSW(LSD(req->dma)); 3666 mcp->mb[3] = LSW(LSD(req->dma)); 3667 mcp->mb[6] = MSW(MSD(req->dma)); 3668 mcp->mb[7] = LSW(MSD(req->dma)); 3669 mcp->mb[5] = req->length; 3670 if (req->rsp) 3671 mcp->mb[10] = req->rsp->id; 3672 mcp->mb[12] = req->qos; 3673 mcp->mb[11] = req->vp_idx; 3674 mcp->mb[13] = req->rid; 3675 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3676 mcp->mb[15] = 0; 3677 3678 mcp->mb[4] = req->id; 3679 /* que in ptr index */ 3680 mcp->mb[8] = 0; 3681 /* que out ptr index */ 3682 mcp->mb[9] = 0; 3683 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7| 3684 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3685 mcp->in_mb = MBX_0; 3686 mcp->flags = MBX_DMA_OUT; 3687 mcp->tov = MBX_TOV_SECONDS * 2; 3688 3689 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3690 mcp->in_mb |= MBX_1; 3691 if (IS_QLA83XX(ha) || !IS_QLA27XX(ha)) { 3692 mcp->out_mb |= MBX_15; 3693 /* debug q create issue in SR-IOV */ 3694 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 3695 } 3696 3697 spin_lock_irqsave(&ha->hardware_lock, flags); 3698 if (!(req->options & BIT_0)) { 3699 WRT_REG_DWORD(req->req_q_in, 0); 3700 if (!IS_QLA83XX(ha) || !IS_QLA27XX(ha)) 3701 WRT_REG_DWORD(req->req_q_out, 0); 3702 } 3703 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3704 3705 rval = qla2x00_mailbox_command(vha, mcp); 3706 if (rval != QLA_SUCCESS) { 3707 ql_dbg(ql_dbg_mbx, vha, 0x10d4, 3708 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3709 } else { 3710 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5, 3711 "Done %s.\n", __func__); 3712 } 3713 3714 return rval; 3715 } 3716 3717 int 3718 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp) 3719 { 3720 int rval; 3721 unsigned long flags; 3722 mbx_cmd_t mc; 3723 mbx_cmd_t *mcp = &mc; 3724 struct qla_hw_data *ha = vha->hw; 3725 3726 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6, 3727 "Entered %s.\n", __func__); 3728 3729 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 3730 mcp->mb[1] = rsp->options; 3731 mcp->mb[2] = MSW(LSD(rsp->dma)); 3732 mcp->mb[3] = LSW(LSD(rsp->dma)); 3733 mcp->mb[6] = MSW(MSD(rsp->dma)); 3734 mcp->mb[7] = LSW(MSD(rsp->dma)); 3735 mcp->mb[5] = rsp->length; 3736 mcp->mb[14] = rsp->msix->entry; 3737 mcp->mb[13] = rsp->rid; 3738 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3739 mcp->mb[15] = 0; 3740 3741 mcp->mb[4] = rsp->id; 3742 /* que in ptr index */ 3743 mcp->mb[8] = 0; 3744 /* que out ptr index */ 3745 mcp->mb[9] = 0; 3746 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7 3747 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3748 mcp->in_mb = MBX_0; 3749 mcp->flags = MBX_DMA_OUT; 3750 mcp->tov = MBX_TOV_SECONDS * 2; 3751 3752 if (IS_QLA81XX(ha)) { 3753 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 3754 mcp->in_mb |= MBX_1; 3755 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3756 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10; 3757 mcp->in_mb |= MBX_1; 3758 /* debug q create issue in SR-IOV */ 3759 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 3760 } 3761 3762 spin_lock_irqsave(&ha->hardware_lock, flags); 3763 if (!(rsp->options & BIT_0)) { 3764 WRT_REG_DWORD(rsp->rsp_q_out, 0); 3765 if (!IS_QLA83XX(ha)) 3766 WRT_REG_DWORD(rsp->rsp_q_in, 0); 3767 } 3768 3769 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3770 3771 rval = qla2x00_mailbox_command(vha, mcp); 3772 if (rval != QLA_SUCCESS) { 3773 ql_dbg(ql_dbg_mbx, vha, 0x10d7, 3774 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3775 } else { 3776 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8, 3777 "Done %s.\n", __func__); 3778 } 3779 3780 return rval; 3781 } 3782 3783 int 3784 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb) 3785 { 3786 int rval; 3787 mbx_cmd_t mc; 3788 mbx_cmd_t *mcp = &mc; 3789 3790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9, 3791 "Entered %s.\n", __func__); 3792 3793 mcp->mb[0] = MBC_IDC_ACK; 3794 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3795 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3796 mcp->in_mb = MBX_0; 3797 mcp->tov = MBX_TOV_SECONDS; 3798 mcp->flags = 0; 3799 rval = qla2x00_mailbox_command(vha, mcp); 3800 3801 if (rval != QLA_SUCCESS) { 3802 ql_dbg(ql_dbg_mbx, vha, 0x10da, 3803 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3804 } else { 3805 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db, 3806 "Done %s.\n", __func__); 3807 } 3808 3809 return rval; 3810 } 3811 3812 int 3813 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size) 3814 { 3815 int rval; 3816 mbx_cmd_t mc; 3817 mbx_cmd_t *mcp = &mc; 3818 3819 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc, 3820 "Entered %s.\n", __func__); 3821 3822 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 3823 !IS_QLA27XX(vha->hw)) 3824 return QLA_FUNCTION_FAILED; 3825 3826 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 3827 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE; 3828 mcp->out_mb = MBX_1|MBX_0; 3829 mcp->in_mb = MBX_1|MBX_0; 3830 mcp->tov = MBX_TOV_SECONDS; 3831 mcp->flags = 0; 3832 rval = qla2x00_mailbox_command(vha, mcp); 3833 3834 if (rval != QLA_SUCCESS) { 3835 ql_dbg(ql_dbg_mbx, vha, 0x10dd, 3836 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3837 rval, mcp->mb[0], mcp->mb[1]); 3838 } else { 3839 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de, 3840 "Done %s.\n", __func__); 3841 *sector_size = mcp->mb[1]; 3842 } 3843 3844 return rval; 3845 } 3846 3847 int 3848 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable) 3849 { 3850 int rval; 3851 mbx_cmd_t mc; 3852 mbx_cmd_t *mcp = &mc; 3853 3854 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 3855 !IS_QLA27XX(vha->hw)) 3856 return QLA_FUNCTION_FAILED; 3857 3858 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df, 3859 "Entered %s.\n", __func__); 3860 3861 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 3862 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE : 3863 FAC_OPT_CMD_WRITE_PROTECT; 3864 mcp->out_mb = MBX_1|MBX_0; 3865 mcp->in_mb = MBX_1|MBX_0; 3866 mcp->tov = MBX_TOV_SECONDS; 3867 mcp->flags = 0; 3868 rval = qla2x00_mailbox_command(vha, mcp); 3869 3870 if (rval != QLA_SUCCESS) { 3871 ql_dbg(ql_dbg_mbx, vha, 0x10e0, 3872 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3873 rval, mcp->mb[0], mcp->mb[1]); 3874 } else { 3875 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1, 3876 "Done %s.\n", __func__); 3877 } 3878 3879 return rval; 3880 } 3881 3882 int 3883 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish) 3884 { 3885 int rval; 3886 mbx_cmd_t mc; 3887 mbx_cmd_t *mcp = &mc; 3888 3889 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 3890 !IS_QLA27XX(vha->hw)) 3891 return QLA_FUNCTION_FAILED; 3892 3893 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2, 3894 "Entered %s.\n", __func__); 3895 3896 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 3897 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR; 3898 mcp->mb[2] = LSW(start); 3899 mcp->mb[3] = MSW(start); 3900 mcp->mb[4] = LSW(finish); 3901 mcp->mb[5] = MSW(finish); 3902 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3903 mcp->in_mb = MBX_2|MBX_1|MBX_0; 3904 mcp->tov = MBX_TOV_SECONDS; 3905 mcp->flags = 0; 3906 rval = qla2x00_mailbox_command(vha, mcp); 3907 3908 if (rval != QLA_SUCCESS) { 3909 ql_dbg(ql_dbg_mbx, vha, 0x10e3, 3910 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 3911 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 3912 } else { 3913 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4, 3914 "Done %s.\n", __func__); 3915 } 3916 3917 return rval; 3918 } 3919 3920 int 3921 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha) 3922 { 3923 int rval = 0; 3924 mbx_cmd_t mc; 3925 mbx_cmd_t *mcp = &mc; 3926 3927 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5, 3928 "Entered %s.\n", __func__); 3929 3930 mcp->mb[0] = MBC_RESTART_MPI_FW; 3931 mcp->out_mb = MBX_0; 3932 mcp->in_mb = MBX_0|MBX_1; 3933 mcp->tov = MBX_TOV_SECONDS; 3934 mcp->flags = 0; 3935 rval = qla2x00_mailbox_command(vha, mcp); 3936 3937 if (rval != QLA_SUCCESS) { 3938 ql_dbg(ql_dbg_mbx, vha, 0x10e6, 3939 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3940 rval, mcp->mb[0], mcp->mb[1]); 3941 } else { 3942 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7, 3943 "Done %s.\n", __func__); 3944 } 3945 3946 return rval; 3947 } 3948 3949 int 3950 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version) 3951 { 3952 int rval; 3953 mbx_cmd_t mc; 3954 mbx_cmd_t *mcp = &mc; 3955 int i; 3956 int len; 3957 uint16_t *str; 3958 struct qla_hw_data *ha = vha->hw; 3959 3960 if (!IS_P3P_TYPE(ha)) 3961 return QLA_FUNCTION_FAILED; 3962 3963 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b, 3964 "Entered %s.\n", __func__); 3965 3966 str = (void *)version; 3967 len = strlen(version); 3968 3969 mcp->mb[0] = MBC_SET_RNID_PARAMS; 3970 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8; 3971 mcp->out_mb = MBX_1|MBX_0; 3972 for (i = 4; i < 16 && len; i++, str++, len -= 2) { 3973 mcp->mb[i] = cpu_to_le16p(str); 3974 mcp->out_mb |= 1<<i; 3975 } 3976 for (; i < 16; i++) { 3977 mcp->mb[i] = 0; 3978 mcp->out_mb |= 1<<i; 3979 } 3980 mcp->in_mb = MBX_1|MBX_0; 3981 mcp->tov = MBX_TOV_SECONDS; 3982 mcp->flags = 0; 3983 rval = qla2x00_mailbox_command(vha, mcp); 3984 3985 if (rval != QLA_SUCCESS) { 3986 ql_dbg(ql_dbg_mbx, vha, 0x117c, 3987 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 3988 } else { 3989 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d, 3990 "Done %s.\n", __func__); 3991 } 3992 3993 return rval; 3994 } 3995 3996 int 3997 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version) 3998 { 3999 int rval; 4000 mbx_cmd_t mc; 4001 mbx_cmd_t *mcp = &mc; 4002 int len; 4003 uint16_t dwlen; 4004 uint8_t *str; 4005 dma_addr_t str_dma; 4006 struct qla_hw_data *ha = vha->hw; 4007 4008 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) || 4009 IS_P3P_TYPE(ha)) 4010 return QLA_FUNCTION_FAILED; 4011 4012 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e, 4013 "Entered %s.\n", __func__); 4014 4015 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma); 4016 if (!str) { 4017 ql_log(ql_log_warn, vha, 0x117f, 4018 "Failed to allocate driver version param.\n"); 4019 return QLA_MEMORY_ALLOC_FAILED; 4020 } 4021 4022 memcpy(str, "\x7\x3\x11\x0", 4); 4023 dwlen = str[0]; 4024 len = dwlen * 4 - 4; 4025 memset(str + 4, 0, len); 4026 if (len > strlen(version)) 4027 len = strlen(version); 4028 memcpy(str + 4, version, len); 4029 4030 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4031 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen; 4032 mcp->mb[2] = MSW(LSD(str_dma)); 4033 mcp->mb[3] = LSW(LSD(str_dma)); 4034 mcp->mb[6] = MSW(MSD(str_dma)); 4035 mcp->mb[7] = LSW(MSD(str_dma)); 4036 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4037 mcp->in_mb = MBX_1|MBX_0; 4038 mcp->tov = MBX_TOV_SECONDS; 4039 mcp->flags = 0; 4040 rval = qla2x00_mailbox_command(vha, mcp); 4041 4042 if (rval != QLA_SUCCESS) { 4043 ql_dbg(ql_dbg_mbx, vha, 0x1180, 4044 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4045 } else { 4046 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181, 4047 "Done %s.\n", __func__); 4048 } 4049 4050 dma_pool_free(ha->s_dma_pool, str, str_dma); 4051 4052 return rval; 4053 } 4054 4055 static int 4056 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp) 4057 { 4058 int rval; 4059 mbx_cmd_t mc; 4060 mbx_cmd_t *mcp = &mc; 4061 4062 if (!IS_FWI2_CAPABLE(vha->hw)) 4063 return QLA_FUNCTION_FAILED; 4064 4065 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159, 4066 "Entered %s.\n", __func__); 4067 4068 mcp->mb[0] = MBC_GET_RNID_PARAMS; 4069 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8; 4070 mcp->out_mb = MBX_1|MBX_0; 4071 mcp->in_mb = MBX_1|MBX_0; 4072 mcp->tov = MBX_TOV_SECONDS; 4073 mcp->flags = 0; 4074 rval = qla2x00_mailbox_command(vha, mcp); 4075 *temp = mcp->mb[1]; 4076 4077 if (rval != QLA_SUCCESS) { 4078 ql_dbg(ql_dbg_mbx, vha, 0x115a, 4079 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4080 } else { 4081 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b, 4082 "Done %s.\n", __func__); 4083 } 4084 4085 return rval; 4086 } 4087 4088 int 4089 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4090 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4091 { 4092 int rval; 4093 mbx_cmd_t mc; 4094 mbx_cmd_t *mcp = &mc; 4095 struct qla_hw_data *ha = vha->hw; 4096 4097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8, 4098 "Entered %s.\n", __func__); 4099 4100 if (!IS_FWI2_CAPABLE(ha)) 4101 return QLA_FUNCTION_FAILED; 4102 4103 if (len == 1) 4104 opt |= BIT_0; 4105 4106 mcp->mb[0] = MBC_READ_SFP; 4107 mcp->mb[1] = dev; 4108 mcp->mb[2] = MSW(sfp_dma); 4109 mcp->mb[3] = LSW(sfp_dma); 4110 mcp->mb[6] = MSW(MSD(sfp_dma)); 4111 mcp->mb[7] = LSW(MSD(sfp_dma)); 4112 mcp->mb[8] = len; 4113 mcp->mb[9] = off; 4114 mcp->mb[10] = opt; 4115 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4116 mcp->in_mb = MBX_1|MBX_0; 4117 mcp->tov = MBX_TOV_SECONDS; 4118 mcp->flags = 0; 4119 rval = qla2x00_mailbox_command(vha, mcp); 4120 4121 if (opt & BIT_0) 4122 *sfp = mcp->mb[1]; 4123 4124 if (rval != QLA_SUCCESS) { 4125 ql_dbg(ql_dbg_mbx, vha, 0x10e9, 4126 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4127 } else { 4128 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea, 4129 "Done %s.\n", __func__); 4130 } 4131 4132 return rval; 4133 } 4134 4135 int 4136 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4137 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4138 { 4139 int rval; 4140 mbx_cmd_t mc; 4141 mbx_cmd_t *mcp = &mc; 4142 struct qla_hw_data *ha = vha->hw; 4143 4144 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb, 4145 "Entered %s.\n", __func__); 4146 4147 if (!IS_FWI2_CAPABLE(ha)) 4148 return QLA_FUNCTION_FAILED; 4149 4150 if (len == 1) 4151 opt |= BIT_0; 4152 4153 if (opt & BIT_0) 4154 len = *sfp; 4155 4156 mcp->mb[0] = MBC_WRITE_SFP; 4157 mcp->mb[1] = dev; 4158 mcp->mb[2] = MSW(sfp_dma); 4159 mcp->mb[3] = LSW(sfp_dma); 4160 mcp->mb[6] = MSW(MSD(sfp_dma)); 4161 mcp->mb[7] = LSW(MSD(sfp_dma)); 4162 mcp->mb[8] = len; 4163 mcp->mb[9] = off; 4164 mcp->mb[10] = opt; 4165 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4166 mcp->in_mb = MBX_1|MBX_0; 4167 mcp->tov = MBX_TOV_SECONDS; 4168 mcp->flags = 0; 4169 rval = qla2x00_mailbox_command(vha, mcp); 4170 4171 if (rval != QLA_SUCCESS) { 4172 ql_dbg(ql_dbg_mbx, vha, 0x10ec, 4173 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4174 } else { 4175 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed, 4176 "Done %s.\n", __func__); 4177 } 4178 4179 return rval; 4180 } 4181 4182 int 4183 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma, 4184 uint16_t size_in_bytes, uint16_t *actual_size) 4185 { 4186 int rval; 4187 mbx_cmd_t mc; 4188 mbx_cmd_t *mcp = &mc; 4189 4190 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee, 4191 "Entered %s.\n", __func__); 4192 4193 if (!IS_CNA_CAPABLE(vha->hw)) 4194 return QLA_FUNCTION_FAILED; 4195 4196 mcp->mb[0] = MBC_GET_XGMAC_STATS; 4197 mcp->mb[2] = MSW(stats_dma); 4198 mcp->mb[3] = LSW(stats_dma); 4199 mcp->mb[6] = MSW(MSD(stats_dma)); 4200 mcp->mb[7] = LSW(MSD(stats_dma)); 4201 mcp->mb[8] = size_in_bytes >> 2; 4202 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 4203 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4204 mcp->tov = MBX_TOV_SECONDS; 4205 mcp->flags = 0; 4206 rval = qla2x00_mailbox_command(vha, mcp); 4207 4208 if (rval != QLA_SUCCESS) { 4209 ql_dbg(ql_dbg_mbx, vha, 0x10ef, 4210 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4211 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4212 } else { 4213 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0, 4214 "Done %s.\n", __func__); 4215 4216 4217 *actual_size = mcp->mb[2] << 2; 4218 } 4219 4220 return rval; 4221 } 4222 4223 int 4224 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma, 4225 uint16_t size) 4226 { 4227 int rval; 4228 mbx_cmd_t mc; 4229 mbx_cmd_t *mcp = &mc; 4230 4231 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1, 4232 "Entered %s.\n", __func__); 4233 4234 if (!IS_CNA_CAPABLE(vha->hw)) 4235 return QLA_FUNCTION_FAILED; 4236 4237 mcp->mb[0] = MBC_GET_DCBX_PARAMS; 4238 mcp->mb[1] = 0; 4239 mcp->mb[2] = MSW(tlv_dma); 4240 mcp->mb[3] = LSW(tlv_dma); 4241 mcp->mb[6] = MSW(MSD(tlv_dma)); 4242 mcp->mb[7] = LSW(MSD(tlv_dma)); 4243 mcp->mb[8] = size; 4244 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4245 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4246 mcp->tov = MBX_TOV_SECONDS; 4247 mcp->flags = 0; 4248 rval = qla2x00_mailbox_command(vha, mcp); 4249 4250 if (rval != QLA_SUCCESS) { 4251 ql_dbg(ql_dbg_mbx, vha, 0x10f2, 4252 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4253 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4254 } else { 4255 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3, 4256 "Done %s.\n", __func__); 4257 } 4258 4259 return rval; 4260 } 4261 4262 int 4263 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data) 4264 { 4265 int rval; 4266 mbx_cmd_t mc; 4267 mbx_cmd_t *mcp = &mc; 4268 4269 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4, 4270 "Entered %s.\n", __func__); 4271 4272 if (!IS_FWI2_CAPABLE(vha->hw)) 4273 return QLA_FUNCTION_FAILED; 4274 4275 mcp->mb[0] = MBC_READ_RAM_EXTENDED; 4276 mcp->mb[1] = LSW(risc_addr); 4277 mcp->mb[8] = MSW(risc_addr); 4278 mcp->out_mb = MBX_8|MBX_1|MBX_0; 4279 mcp->in_mb = MBX_3|MBX_2|MBX_0; 4280 mcp->tov = 30; 4281 mcp->flags = 0; 4282 rval = qla2x00_mailbox_command(vha, mcp); 4283 if (rval != QLA_SUCCESS) { 4284 ql_dbg(ql_dbg_mbx, vha, 0x10f5, 4285 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4286 } else { 4287 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6, 4288 "Done %s.\n", __func__); 4289 *data = mcp->mb[3] << 16 | mcp->mb[2]; 4290 } 4291 4292 return rval; 4293 } 4294 4295 int 4296 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4297 uint16_t *mresp) 4298 { 4299 int rval; 4300 mbx_cmd_t mc; 4301 mbx_cmd_t *mcp = &mc; 4302 4303 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7, 4304 "Entered %s.\n", __func__); 4305 4306 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4307 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK; 4308 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing 4309 4310 /* transfer count */ 4311 mcp->mb[10] = LSW(mreq->transfer_size); 4312 mcp->mb[11] = MSW(mreq->transfer_size); 4313 4314 /* send data address */ 4315 mcp->mb[14] = LSW(mreq->send_dma); 4316 mcp->mb[15] = MSW(mreq->send_dma); 4317 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4318 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4319 4320 /* receive data address */ 4321 mcp->mb[16] = LSW(mreq->rcv_dma); 4322 mcp->mb[17] = MSW(mreq->rcv_dma); 4323 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4324 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4325 4326 /* Iteration count */ 4327 mcp->mb[18] = LSW(mreq->iteration_count); 4328 mcp->mb[19] = MSW(mreq->iteration_count); 4329 4330 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| 4331 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4332 if (IS_CNA_CAPABLE(vha->hw)) 4333 mcp->out_mb |= MBX_2; 4334 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; 4335 4336 mcp->buf_size = mreq->transfer_size; 4337 mcp->tov = MBX_TOV_SECONDS; 4338 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4339 4340 rval = qla2x00_mailbox_command(vha, mcp); 4341 4342 if (rval != QLA_SUCCESS) { 4343 ql_dbg(ql_dbg_mbx, vha, 0x10f8, 4344 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x " 4345 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], 4346 mcp->mb[3], mcp->mb[18], mcp->mb[19]); 4347 } else { 4348 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9, 4349 "Done %s.\n", __func__); 4350 } 4351 4352 /* Copy mailbox information */ 4353 memcpy( mresp, mcp->mb, 64); 4354 return rval; 4355 } 4356 4357 int 4358 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4359 uint16_t *mresp) 4360 { 4361 int rval; 4362 mbx_cmd_t mc; 4363 mbx_cmd_t *mcp = &mc; 4364 struct qla_hw_data *ha = vha->hw; 4365 4366 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa, 4367 "Entered %s.\n", __func__); 4368 4369 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4370 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; 4371 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */ 4372 if (IS_CNA_CAPABLE(ha)) { 4373 mcp->mb[1] |= BIT_15; 4374 mcp->mb[2] = vha->fcoe_fcf_idx; 4375 } 4376 mcp->mb[16] = LSW(mreq->rcv_dma); 4377 mcp->mb[17] = MSW(mreq->rcv_dma); 4378 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4379 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4380 4381 mcp->mb[10] = LSW(mreq->transfer_size); 4382 4383 mcp->mb[14] = LSW(mreq->send_dma); 4384 mcp->mb[15] = MSW(mreq->send_dma); 4385 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4386 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4387 4388 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| 4389 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4390 if (IS_CNA_CAPABLE(ha)) 4391 mcp->out_mb |= MBX_2; 4392 4393 mcp->in_mb = MBX_0; 4394 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || 4395 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4396 mcp->in_mb |= MBX_1; 4397 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4398 mcp->in_mb |= MBX_3; 4399 4400 mcp->tov = MBX_TOV_SECONDS; 4401 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4402 mcp->buf_size = mreq->transfer_size; 4403 4404 rval = qla2x00_mailbox_command(vha, mcp); 4405 4406 if (rval != QLA_SUCCESS) { 4407 ql_dbg(ql_dbg_mbx, vha, 0x10fb, 4408 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4409 rval, mcp->mb[0], mcp->mb[1]); 4410 } else { 4411 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc, 4412 "Done %s.\n", __func__); 4413 } 4414 4415 /* Copy mailbox information */ 4416 memcpy(mresp, mcp->mb, 64); 4417 return rval; 4418 } 4419 4420 int 4421 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic) 4422 { 4423 int rval; 4424 mbx_cmd_t mc; 4425 mbx_cmd_t *mcp = &mc; 4426 4427 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd, 4428 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic); 4429 4430 mcp->mb[0] = MBC_ISP84XX_RESET; 4431 mcp->mb[1] = enable_diagnostic; 4432 mcp->out_mb = MBX_1|MBX_0; 4433 mcp->in_mb = MBX_1|MBX_0; 4434 mcp->tov = MBX_TOV_SECONDS; 4435 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4436 rval = qla2x00_mailbox_command(vha, mcp); 4437 4438 if (rval != QLA_SUCCESS) 4439 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval); 4440 else 4441 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff, 4442 "Done %s.\n", __func__); 4443 4444 return rval; 4445 } 4446 4447 int 4448 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data) 4449 { 4450 int rval; 4451 mbx_cmd_t mc; 4452 mbx_cmd_t *mcp = &mc; 4453 4454 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100, 4455 "Entered %s.\n", __func__); 4456 4457 if (!IS_FWI2_CAPABLE(vha->hw)) 4458 return QLA_FUNCTION_FAILED; 4459 4460 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED; 4461 mcp->mb[1] = LSW(risc_addr); 4462 mcp->mb[2] = LSW(data); 4463 mcp->mb[3] = MSW(data); 4464 mcp->mb[8] = MSW(risc_addr); 4465 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0; 4466 mcp->in_mb = MBX_0; 4467 mcp->tov = 30; 4468 mcp->flags = 0; 4469 rval = qla2x00_mailbox_command(vha, mcp); 4470 if (rval != QLA_SUCCESS) { 4471 ql_dbg(ql_dbg_mbx, vha, 0x1101, 4472 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4473 } else { 4474 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102, 4475 "Done %s.\n", __func__); 4476 } 4477 4478 return rval; 4479 } 4480 4481 int 4482 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb) 4483 { 4484 int rval; 4485 uint32_t stat, timer; 4486 uint16_t mb0 = 0; 4487 struct qla_hw_data *ha = vha->hw; 4488 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 4489 4490 rval = QLA_SUCCESS; 4491 4492 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103, 4493 "Entered %s.\n", __func__); 4494 4495 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 4496 4497 /* Write the MBC data to the registers */ 4498 WRT_REG_WORD(®->mailbox0, MBC_WRITE_MPI_REGISTER); 4499 WRT_REG_WORD(®->mailbox1, mb[0]); 4500 WRT_REG_WORD(®->mailbox2, mb[1]); 4501 WRT_REG_WORD(®->mailbox3, mb[2]); 4502 WRT_REG_WORD(®->mailbox4, mb[3]); 4503 4504 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 4505 4506 /* Poll for MBC interrupt */ 4507 for (timer = 6000000; timer; timer--) { 4508 /* Check for pending interrupts. */ 4509 stat = RD_REG_DWORD(®->host_status); 4510 if (stat & HSRX_RISC_INT) { 4511 stat &= 0xff; 4512 4513 if (stat == 0x1 || stat == 0x2 || 4514 stat == 0x10 || stat == 0x11) { 4515 set_bit(MBX_INTERRUPT, 4516 &ha->mbx_cmd_flags); 4517 mb0 = RD_REG_WORD(®->mailbox0); 4518 WRT_REG_DWORD(®->hccr, 4519 HCCRX_CLR_RISC_INT); 4520 RD_REG_DWORD(®->hccr); 4521 break; 4522 } 4523 } 4524 udelay(5); 4525 } 4526 4527 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) 4528 rval = mb0 & MBS_MASK; 4529 else 4530 rval = QLA_FUNCTION_FAILED; 4531 4532 if (rval != QLA_SUCCESS) { 4533 ql_dbg(ql_dbg_mbx, vha, 0x1104, 4534 "Failed=%x mb[0]=%x.\n", rval, mb[0]); 4535 } else { 4536 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105, 4537 "Done %s.\n", __func__); 4538 } 4539 4540 return rval; 4541 } 4542 4543 int 4544 qla2x00_get_data_rate(scsi_qla_host_t *vha) 4545 { 4546 int rval; 4547 mbx_cmd_t mc; 4548 mbx_cmd_t *mcp = &mc; 4549 struct qla_hw_data *ha = vha->hw; 4550 4551 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106, 4552 "Entered %s.\n", __func__); 4553 4554 if (!IS_FWI2_CAPABLE(ha)) 4555 return QLA_FUNCTION_FAILED; 4556 4557 mcp->mb[0] = MBC_DATA_RATE; 4558 mcp->mb[1] = 0; 4559 mcp->out_mb = MBX_1|MBX_0; 4560 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4561 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4562 mcp->in_mb |= MBX_3; 4563 mcp->tov = MBX_TOV_SECONDS; 4564 mcp->flags = 0; 4565 rval = qla2x00_mailbox_command(vha, mcp); 4566 if (rval != QLA_SUCCESS) { 4567 ql_dbg(ql_dbg_mbx, vha, 0x1107, 4568 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4569 } else { 4570 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108, 4571 "Done %s.\n", __func__); 4572 if (mcp->mb[1] != 0x7) 4573 ha->link_data_rate = mcp->mb[1]; 4574 } 4575 4576 return rval; 4577 } 4578 4579 int 4580 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb) 4581 { 4582 int rval; 4583 mbx_cmd_t mc; 4584 mbx_cmd_t *mcp = &mc; 4585 struct qla_hw_data *ha = vha->hw; 4586 4587 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109, 4588 "Entered %s.\n", __func__); 4589 4590 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) && 4591 !IS_QLA27XX(ha)) 4592 return QLA_FUNCTION_FAILED; 4593 mcp->mb[0] = MBC_GET_PORT_CONFIG; 4594 mcp->out_mb = MBX_0; 4595 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4596 mcp->tov = MBX_TOV_SECONDS; 4597 mcp->flags = 0; 4598 4599 rval = qla2x00_mailbox_command(vha, mcp); 4600 4601 if (rval != QLA_SUCCESS) { 4602 ql_dbg(ql_dbg_mbx, vha, 0x110a, 4603 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4604 } else { 4605 /* Copy all bits to preserve original value */ 4606 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4); 4607 4608 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b, 4609 "Done %s.\n", __func__); 4610 } 4611 return rval; 4612 } 4613 4614 int 4615 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb) 4616 { 4617 int rval; 4618 mbx_cmd_t mc; 4619 mbx_cmd_t *mcp = &mc; 4620 4621 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c, 4622 "Entered %s.\n", __func__); 4623 4624 mcp->mb[0] = MBC_SET_PORT_CONFIG; 4625 /* Copy all bits to preserve original setting */ 4626 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4); 4627 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4628 mcp->in_mb = MBX_0; 4629 mcp->tov = MBX_TOV_SECONDS; 4630 mcp->flags = 0; 4631 rval = qla2x00_mailbox_command(vha, mcp); 4632 4633 if (rval != QLA_SUCCESS) { 4634 ql_dbg(ql_dbg_mbx, vha, 0x110d, 4635 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4636 } else 4637 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e, 4638 "Done %s.\n", __func__); 4639 4640 return rval; 4641 } 4642 4643 4644 int 4645 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority, 4646 uint16_t *mb) 4647 { 4648 int rval; 4649 mbx_cmd_t mc; 4650 mbx_cmd_t *mcp = &mc; 4651 struct qla_hw_data *ha = vha->hw; 4652 4653 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f, 4654 "Entered %s.\n", __func__); 4655 4656 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 4657 return QLA_FUNCTION_FAILED; 4658 4659 mcp->mb[0] = MBC_PORT_PARAMS; 4660 mcp->mb[1] = loop_id; 4661 if (ha->flags.fcp_prio_enabled) 4662 mcp->mb[2] = BIT_1; 4663 else 4664 mcp->mb[2] = BIT_2; 4665 mcp->mb[4] = priority & 0xf; 4666 mcp->mb[9] = vha->vp_idx; 4667 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4668 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 4669 mcp->tov = 30; 4670 mcp->flags = 0; 4671 rval = qla2x00_mailbox_command(vha, mcp); 4672 if (mb != NULL) { 4673 mb[0] = mcp->mb[0]; 4674 mb[1] = mcp->mb[1]; 4675 mb[3] = mcp->mb[3]; 4676 mb[4] = mcp->mb[4]; 4677 } 4678 4679 if (rval != QLA_SUCCESS) { 4680 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval); 4681 } else { 4682 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc, 4683 "Done %s.\n", __func__); 4684 } 4685 4686 return rval; 4687 } 4688 4689 int 4690 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp) 4691 { 4692 int rval = QLA_FUNCTION_FAILED; 4693 struct qla_hw_data *ha = vha->hw; 4694 uint8_t byte; 4695 4696 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) { 4697 ql_dbg(ql_dbg_mbx, vha, 0x1150, 4698 "Thermal not supported by this card.\n"); 4699 return rval; 4700 } 4701 4702 if (IS_QLA25XX(ha)) { 4703 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 4704 ha->pdev->subsystem_device == 0x0175) { 4705 rval = qla2x00_read_sfp(vha, 0, &byte, 4706 0x98, 0x1, 1, BIT_13|BIT_0); 4707 *temp = byte; 4708 return rval; 4709 } 4710 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 4711 ha->pdev->subsystem_device == 0x338e) { 4712 rval = qla2x00_read_sfp(vha, 0, &byte, 4713 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0); 4714 *temp = byte; 4715 return rval; 4716 } 4717 ql_dbg(ql_dbg_mbx, vha, 0x10c9, 4718 "Thermal not supported by this card.\n"); 4719 return rval; 4720 } 4721 4722 if (IS_QLA82XX(ha)) { 4723 *temp = qla82xx_read_temperature(vha); 4724 rval = QLA_SUCCESS; 4725 return rval; 4726 } else if (IS_QLA8044(ha)) { 4727 *temp = qla8044_read_temperature(vha); 4728 rval = QLA_SUCCESS; 4729 return rval; 4730 } 4731 4732 rval = qla2x00_read_asic_temperature(vha, temp); 4733 return rval; 4734 } 4735 4736 int 4737 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha) 4738 { 4739 int rval; 4740 struct qla_hw_data *ha = vha->hw; 4741 mbx_cmd_t mc; 4742 mbx_cmd_t *mcp = &mc; 4743 4744 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017, 4745 "Entered %s.\n", __func__); 4746 4747 if (!IS_FWI2_CAPABLE(ha)) 4748 return QLA_FUNCTION_FAILED; 4749 4750 memset(mcp, 0, sizeof(mbx_cmd_t)); 4751 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 4752 mcp->mb[1] = 1; 4753 4754 mcp->out_mb = MBX_1|MBX_0; 4755 mcp->in_mb = MBX_0; 4756 mcp->tov = 30; 4757 mcp->flags = 0; 4758 4759 rval = qla2x00_mailbox_command(vha, mcp); 4760 if (rval != QLA_SUCCESS) { 4761 ql_dbg(ql_dbg_mbx, vha, 0x1016, 4762 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4763 } else { 4764 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e, 4765 "Done %s.\n", __func__); 4766 } 4767 4768 return rval; 4769 } 4770 4771 int 4772 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha) 4773 { 4774 int rval; 4775 struct qla_hw_data *ha = vha->hw; 4776 mbx_cmd_t mc; 4777 mbx_cmd_t *mcp = &mc; 4778 4779 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d, 4780 "Entered %s.\n", __func__); 4781 4782 if (!IS_P3P_TYPE(ha)) 4783 return QLA_FUNCTION_FAILED; 4784 4785 memset(mcp, 0, sizeof(mbx_cmd_t)); 4786 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 4787 mcp->mb[1] = 0; 4788 4789 mcp->out_mb = MBX_1|MBX_0; 4790 mcp->in_mb = MBX_0; 4791 mcp->tov = 30; 4792 mcp->flags = 0; 4793 4794 rval = qla2x00_mailbox_command(vha, mcp); 4795 if (rval != QLA_SUCCESS) { 4796 ql_dbg(ql_dbg_mbx, vha, 0x100c, 4797 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4798 } else { 4799 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b, 4800 "Done %s.\n", __func__); 4801 } 4802 4803 return rval; 4804 } 4805 4806 int 4807 qla82xx_md_get_template_size(scsi_qla_host_t *vha) 4808 { 4809 struct qla_hw_data *ha = vha->hw; 4810 mbx_cmd_t mc; 4811 mbx_cmd_t *mcp = &mc; 4812 int rval = QLA_FUNCTION_FAILED; 4813 4814 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f, 4815 "Entered %s.\n", __func__); 4816 4817 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4818 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4819 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4820 mcp->mb[2] = LSW(RQST_TMPLT_SIZE); 4821 mcp->mb[3] = MSW(RQST_TMPLT_SIZE); 4822 4823 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 4824 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| 4825 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4826 4827 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4828 mcp->tov = MBX_TOV_SECONDS; 4829 rval = qla2x00_mailbox_command(vha, mcp); 4830 4831 /* Always copy back return mailbox values. */ 4832 if (rval != QLA_SUCCESS) { 4833 ql_dbg(ql_dbg_mbx, vha, 0x1120, 4834 "mailbox command FAILED=0x%x, subcode=%x.\n", 4835 (mcp->mb[1] << 16) | mcp->mb[0], 4836 (mcp->mb[3] << 16) | mcp->mb[2]); 4837 } else { 4838 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121, 4839 "Done %s.\n", __func__); 4840 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]); 4841 if (!ha->md_template_size) { 4842 ql_dbg(ql_dbg_mbx, vha, 0x1122, 4843 "Null template size obtained.\n"); 4844 rval = QLA_FUNCTION_FAILED; 4845 } 4846 } 4847 return rval; 4848 } 4849 4850 int 4851 qla82xx_md_get_template(scsi_qla_host_t *vha) 4852 { 4853 struct qla_hw_data *ha = vha->hw; 4854 mbx_cmd_t mc; 4855 mbx_cmd_t *mcp = &mc; 4856 int rval = QLA_FUNCTION_FAILED; 4857 4858 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123, 4859 "Entered %s.\n", __func__); 4860 4861 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 4862 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 4863 if (!ha->md_tmplt_hdr) { 4864 ql_log(ql_log_warn, vha, 0x1124, 4865 "Unable to allocate memory for Minidump template.\n"); 4866 return rval; 4867 } 4868 4869 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4870 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4871 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4872 mcp->mb[2] = LSW(RQST_TMPLT); 4873 mcp->mb[3] = MSW(RQST_TMPLT); 4874 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma)); 4875 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma)); 4876 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma)); 4877 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma)); 4878 mcp->mb[8] = LSW(ha->md_template_size); 4879 mcp->mb[9] = MSW(ha->md_template_size); 4880 4881 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4882 mcp->tov = MBX_TOV_SECONDS; 4883 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 4884 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4885 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 4886 rval = qla2x00_mailbox_command(vha, mcp); 4887 4888 if (rval != QLA_SUCCESS) { 4889 ql_dbg(ql_dbg_mbx, vha, 0x1125, 4890 "mailbox command FAILED=0x%x, subcode=%x.\n", 4891 ((mcp->mb[1] << 16) | mcp->mb[0]), 4892 ((mcp->mb[3] << 16) | mcp->mb[2])); 4893 } else 4894 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126, 4895 "Done %s.\n", __func__); 4896 return rval; 4897 } 4898 4899 int 4900 qla8044_md_get_template(scsi_qla_host_t *vha) 4901 { 4902 struct qla_hw_data *ha = vha->hw; 4903 mbx_cmd_t mc; 4904 mbx_cmd_t *mcp = &mc; 4905 int rval = QLA_FUNCTION_FAILED; 4906 int offset = 0, size = MINIDUMP_SIZE_36K; 4907 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f, 4908 "Entered %s.\n", __func__); 4909 4910 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 4911 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 4912 if (!ha->md_tmplt_hdr) { 4913 ql_log(ql_log_warn, vha, 0xb11b, 4914 "Unable to allocate memory for Minidump template.\n"); 4915 return rval; 4916 } 4917 4918 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4919 while (offset < ha->md_template_size) { 4920 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4921 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4922 mcp->mb[2] = LSW(RQST_TMPLT); 4923 mcp->mb[3] = MSW(RQST_TMPLT); 4924 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset)); 4925 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset)); 4926 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset)); 4927 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset)); 4928 mcp->mb[8] = LSW(size); 4929 mcp->mb[9] = MSW(size); 4930 mcp->mb[10] = offset & 0x0000FFFF; 4931 mcp->mb[11] = offset & 0xFFFF0000; 4932 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4933 mcp->tov = MBX_TOV_SECONDS; 4934 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 4935 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4936 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 4937 rval = qla2x00_mailbox_command(vha, mcp); 4938 4939 if (rval != QLA_SUCCESS) { 4940 ql_dbg(ql_dbg_mbx, vha, 0xb11c, 4941 "mailbox command FAILED=0x%x, subcode=%x.\n", 4942 ((mcp->mb[1] << 16) | mcp->mb[0]), 4943 ((mcp->mb[3] << 16) | mcp->mb[2])); 4944 return rval; 4945 } else 4946 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d, 4947 "Done %s.\n", __func__); 4948 offset = offset + size; 4949 } 4950 return rval; 4951 } 4952 4953 int 4954 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 4955 { 4956 int rval; 4957 struct qla_hw_data *ha = vha->hw; 4958 mbx_cmd_t mc; 4959 mbx_cmd_t *mcp = &mc; 4960 4961 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 4962 return QLA_FUNCTION_FAILED; 4963 4964 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133, 4965 "Entered %s.\n", __func__); 4966 4967 memset(mcp, 0, sizeof(mbx_cmd_t)); 4968 mcp->mb[0] = MBC_SET_LED_CONFIG; 4969 mcp->mb[1] = led_cfg[0]; 4970 mcp->mb[2] = led_cfg[1]; 4971 if (IS_QLA8031(ha)) { 4972 mcp->mb[3] = led_cfg[2]; 4973 mcp->mb[4] = led_cfg[3]; 4974 mcp->mb[5] = led_cfg[4]; 4975 mcp->mb[6] = led_cfg[5]; 4976 } 4977 4978 mcp->out_mb = MBX_2|MBX_1|MBX_0; 4979 if (IS_QLA8031(ha)) 4980 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 4981 mcp->in_mb = MBX_0; 4982 mcp->tov = 30; 4983 mcp->flags = 0; 4984 4985 rval = qla2x00_mailbox_command(vha, mcp); 4986 if (rval != QLA_SUCCESS) { 4987 ql_dbg(ql_dbg_mbx, vha, 0x1134, 4988 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4989 } else { 4990 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135, 4991 "Done %s.\n", __func__); 4992 } 4993 4994 return rval; 4995 } 4996 4997 int 4998 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 4999 { 5000 int rval; 5001 struct qla_hw_data *ha = vha->hw; 5002 mbx_cmd_t mc; 5003 mbx_cmd_t *mcp = &mc; 5004 5005 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5006 return QLA_FUNCTION_FAILED; 5007 5008 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136, 5009 "Entered %s.\n", __func__); 5010 5011 memset(mcp, 0, sizeof(mbx_cmd_t)); 5012 mcp->mb[0] = MBC_GET_LED_CONFIG; 5013 5014 mcp->out_mb = MBX_0; 5015 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5016 if (IS_QLA8031(ha)) 5017 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5018 mcp->tov = 30; 5019 mcp->flags = 0; 5020 5021 rval = qla2x00_mailbox_command(vha, mcp); 5022 if (rval != QLA_SUCCESS) { 5023 ql_dbg(ql_dbg_mbx, vha, 0x1137, 5024 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5025 } else { 5026 led_cfg[0] = mcp->mb[1]; 5027 led_cfg[1] = mcp->mb[2]; 5028 if (IS_QLA8031(ha)) { 5029 led_cfg[2] = mcp->mb[3]; 5030 led_cfg[3] = mcp->mb[4]; 5031 led_cfg[4] = mcp->mb[5]; 5032 led_cfg[5] = mcp->mb[6]; 5033 } 5034 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138, 5035 "Done %s.\n", __func__); 5036 } 5037 5038 return rval; 5039 } 5040 5041 int 5042 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable) 5043 { 5044 int rval; 5045 struct qla_hw_data *ha = vha->hw; 5046 mbx_cmd_t mc; 5047 mbx_cmd_t *mcp = &mc; 5048 5049 if (!IS_P3P_TYPE(ha)) 5050 return QLA_FUNCTION_FAILED; 5051 5052 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127, 5053 "Entered %s.\n", __func__); 5054 5055 memset(mcp, 0, sizeof(mbx_cmd_t)); 5056 mcp->mb[0] = MBC_SET_LED_CONFIG; 5057 if (enable) 5058 mcp->mb[7] = 0xE; 5059 else 5060 mcp->mb[7] = 0xD; 5061 5062 mcp->out_mb = MBX_7|MBX_0; 5063 mcp->in_mb = MBX_0; 5064 mcp->tov = MBX_TOV_SECONDS; 5065 mcp->flags = 0; 5066 5067 rval = qla2x00_mailbox_command(vha, mcp); 5068 if (rval != QLA_SUCCESS) { 5069 ql_dbg(ql_dbg_mbx, vha, 0x1128, 5070 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5071 } else { 5072 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129, 5073 "Done %s.\n", __func__); 5074 } 5075 5076 return rval; 5077 } 5078 5079 int 5080 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data) 5081 { 5082 int rval; 5083 struct qla_hw_data *ha = vha->hw; 5084 mbx_cmd_t mc; 5085 mbx_cmd_t *mcp = &mc; 5086 5087 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5088 return QLA_FUNCTION_FAILED; 5089 5090 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130, 5091 "Entered %s.\n", __func__); 5092 5093 mcp->mb[0] = MBC_WRITE_REMOTE_REG; 5094 mcp->mb[1] = LSW(reg); 5095 mcp->mb[2] = MSW(reg); 5096 mcp->mb[3] = LSW(data); 5097 mcp->mb[4] = MSW(data); 5098 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5099 5100 mcp->in_mb = MBX_1|MBX_0; 5101 mcp->tov = MBX_TOV_SECONDS; 5102 mcp->flags = 0; 5103 rval = qla2x00_mailbox_command(vha, mcp); 5104 5105 if (rval != QLA_SUCCESS) { 5106 ql_dbg(ql_dbg_mbx, vha, 0x1131, 5107 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5108 } else { 5109 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132, 5110 "Done %s.\n", __func__); 5111 } 5112 5113 return rval; 5114 } 5115 5116 int 5117 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport) 5118 { 5119 int rval; 5120 struct qla_hw_data *ha = vha->hw; 5121 mbx_cmd_t mc; 5122 mbx_cmd_t *mcp = &mc; 5123 5124 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 5125 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b, 5126 "Implicit LOGO Unsupported.\n"); 5127 return QLA_FUNCTION_FAILED; 5128 } 5129 5130 5131 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c, 5132 "Entering %s.\n", __func__); 5133 5134 /* Perform Implicit LOGO. */ 5135 mcp->mb[0] = MBC_PORT_LOGOUT; 5136 mcp->mb[1] = fcport->loop_id; 5137 mcp->mb[10] = BIT_15; 5138 mcp->out_mb = MBX_10|MBX_1|MBX_0; 5139 mcp->in_mb = MBX_0; 5140 mcp->tov = MBX_TOV_SECONDS; 5141 mcp->flags = 0; 5142 rval = qla2x00_mailbox_command(vha, mcp); 5143 if (rval != QLA_SUCCESS) 5144 ql_dbg(ql_dbg_mbx, vha, 0x113d, 5145 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5146 else 5147 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e, 5148 "Done %s.\n", __func__); 5149 5150 return rval; 5151 } 5152 5153 int 5154 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data) 5155 { 5156 int rval; 5157 mbx_cmd_t mc; 5158 mbx_cmd_t *mcp = &mc; 5159 struct qla_hw_data *ha = vha->hw; 5160 unsigned long retry_max_time = jiffies + (2 * HZ); 5161 5162 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5163 return QLA_FUNCTION_FAILED; 5164 5165 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__); 5166 5167 retry_rd_reg: 5168 mcp->mb[0] = MBC_READ_REMOTE_REG; 5169 mcp->mb[1] = LSW(reg); 5170 mcp->mb[2] = MSW(reg); 5171 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5172 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5173 mcp->tov = MBX_TOV_SECONDS; 5174 mcp->flags = 0; 5175 rval = qla2x00_mailbox_command(vha, mcp); 5176 5177 if (rval != QLA_SUCCESS) { 5178 ql_dbg(ql_dbg_mbx, vha, 0x114c, 5179 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5180 rval, mcp->mb[0], mcp->mb[1]); 5181 } else { 5182 *data = (mcp->mb[3] | (mcp->mb[4] << 16)); 5183 if (*data == QLA8XXX_BAD_VALUE) { 5184 /* 5185 * During soft-reset CAMRAM register reads might 5186 * return 0xbad0bad0. So retry for MAX of 2 sec 5187 * while reading camram registers. 5188 */ 5189 if (time_after(jiffies, retry_max_time)) { 5190 ql_dbg(ql_dbg_mbx, vha, 0x1141, 5191 "Failure to read CAMRAM register. " 5192 "data=0x%x.\n", *data); 5193 return QLA_FUNCTION_FAILED; 5194 } 5195 msleep(100); 5196 goto retry_rd_reg; 5197 } 5198 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__); 5199 } 5200 5201 return rval; 5202 } 5203 5204 int 5205 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha) 5206 { 5207 int rval; 5208 mbx_cmd_t mc; 5209 mbx_cmd_t *mcp = &mc; 5210 struct qla_hw_data *ha = vha->hw; 5211 5212 if (!IS_QLA83XX(ha)) 5213 return QLA_FUNCTION_FAILED; 5214 5215 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__); 5216 5217 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE; 5218 mcp->out_mb = MBX_0; 5219 mcp->in_mb = MBX_1|MBX_0; 5220 mcp->tov = MBX_TOV_SECONDS; 5221 mcp->flags = 0; 5222 rval = qla2x00_mailbox_command(vha, mcp); 5223 5224 if (rval != QLA_SUCCESS) { 5225 ql_dbg(ql_dbg_mbx, vha, 0x1144, 5226 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5227 rval, mcp->mb[0], mcp->mb[1]); 5228 ha->isp_ops->fw_dump(vha, 0); 5229 } else { 5230 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__); 5231 } 5232 5233 return rval; 5234 } 5235 5236 int 5237 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options, 5238 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size) 5239 { 5240 int rval; 5241 mbx_cmd_t mc; 5242 mbx_cmd_t *mcp = &mc; 5243 uint8_t subcode = (uint8_t)options; 5244 struct qla_hw_data *ha = vha->hw; 5245 5246 if (!IS_QLA8031(ha)) 5247 return QLA_FUNCTION_FAILED; 5248 5249 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__); 5250 5251 mcp->mb[0] = MBC_SET_ACCESS_CONTROL; 5252 mcp->mb[1] = options; 5253 mcp->out_mb = MBX_1|MBX_0; 5254 if (subcode & BIT_2) { 5255 mcp->mb[2] = LSW(start_addr); 5256 mcp->mb[3] = MSW(start_addr); 5257 mcp->mb[4] = LSW(end_addr); 5258 mcp->mb[5] = MSW(end_addr); 5259 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2; 5260 } 5261 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5262 if (!(subcode & (BIT_2 | BIT_5))) 5263 mcp->in_mb |= MBX_4|MBX_3; 5264 mcp->tov = MBX_TOV_SECONDS; 5265 mcp->flags = 0; 5266 rval = qla2x00_mailbox_command(vha, mcp); 5267 5268 if (rval != QLA_SUCCESS) { 5269 ql_dbg(ql_dbg_mbx, vha, 0x1147, 5270 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n", 5271 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], 5272 mcp->mb[4]); 5273 ha->isp_ops->fw_dump(vha, 0); 5274 } else { 5275 if (subcode & BIT_5) 5276 *sector_size = mcp->mb[1]; 5277 else if (subcode & (BIT_6 | BIT_7)) { 5278 ql_dbg(ql_dbg_mbx, vha, 0x1148, 5279 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5280 } else if (subcode & (BIT_3 | BIT_4)) { 5281 ql_dbg(ql_dbg_mbx, vha, 0x1149, 5282 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5283 } 5284 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__); 5285 } 5286 5287 return rval; 5288 } 5289 5290 int 5291 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 5292 uint32_t size) 5293 { 5294 int rval; 5295 mbx_cmd_t mc; 5296 mbx_cmd_t *mcp = &mc; 5297 5298 if (!IS_MCTP_CAPABLE(vha->hw)) 5299 return QLA_FUNCTION_FAILED; 5300 5301 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f, 5302 "Entered %s.\n", __func__); 5303 5304 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 5305 mcp->mb[1] = LSW(addr); 5306 mcp->mb[2] = MSW(req_dma); 5307 mcp->mb[3] = LSW(req_dma); 5308 mcp->mb[4] = MSW(size); 5309 mcp->mb[5] = LSW(size); 5310 mcp->mb[6] = MSW(MSD(req_dma)); 5311 mcp->mb[7] = LSW(MSD(req_dma)); 5312 mcp->mb[8] = MSW(addr); 5313 /* Setting RAM ID to valid */ 5314 mcp->mb[10] |= BIT_7; 5315 /* For MCTP RAM ID is 0x40 */ 5316 mcp->mb[10] |= 0x40; 5317 5318 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1| 5319 MBX_0; 5320 5321 mcp->in_mb = MBX_0; 5322 mcp->tov = MBX_TOV_SECONDS; 5323 mcp->flags = 0; 5324 rval = qla2x00_mailbox_command(vha, mcp); 5325 5326 if (rval != QLA_SUCCESS) { 5327 ql_dbg(ql_dbg_mbx, vha, 0x114e, 5328 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5329 } else { 5330 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d, 5331 "Done %s.\n", __func__); 5332 } 5333 5334 return rval; 5335 } 5336