1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_target.h" 9 10 #include <linux/delay.h> 11 #include <linux/gfp.h> 12 13 static struct rom_cmd { 14 uint16_t cmd; 15 } rom_cmds[] = { 16 { MBC_LOAD_RAM }, 17 { MBC_EXECUTE_FIRMWARE }, 18 { MBC_READ_RAM_WORD }, 19 { MBC_MAILBOX_REGISTER_TEST }, 20 { MBC_VERIFY_CHECKSUM }, 21 { MBC_GET_FIRMWARE_VERSION }, 22 { MBC_LOAD_RISC_RAM }, 23 { MBC_DUMP_RISC_RAM }, 24 { MBC_LOAD_RISC_RAM_EXTENDED }, 25 { MBC_DUMP_RISC_RAM_EXTENDED }, 26 { MBC_WRITE_RAM_WORD_EXTENDED }, 27 { MBC_READ_RAM_EXTENDED }, 28 { MBC_GET_RESOURCE_COUNTS }, 29 { MBC_SET_FIRMWARE_OPTION }, 30 { MBC_MID_INITIALIZE_FIRMWARE }, 31 { MBC_GET_FIRMWARE_STATE }, 32 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT }, 33 { MBC_GET_RETRY_COUNT }, 34 { MBC_TRACE_CONTROL }, 35 }; 36 37 static int is_rom_cmd(uint16_t cmd) 38 { 39 int i; 40 struct rom_cmd *wc; 41 42 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) { 43 wc = rom_cmds + i; 44 if (wc->cmd == cmd) 45 return 1; 46 } 47 48 return 0; 49 } 50 51 /* 52 * qla2x00_mailbox_command 53 * Issue mailbox command and waits for completion. 54 * 55 * Input: 56 * ha = adapter block pointer. 57 * mcp = driver internal mbx struct pointer. 58 * 59 * Output: 60 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data. 61 * 62 * Returns: 63 * 0 : QLA_SUCCESS = cmd performed success 64 * 1 : QLA_FUNCTION_FAILED (error encountered) 65 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered) 66 * 67 * Context: 68 * Kernel context. 69 */ 70 static int 71 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) 72 { 73 int rval, i; 74 unsigned long flags = 0; 75 device_reg_t *reg; 76 uint8_t abort_active; 77 uint8_t io_lock_on; 78 uint16_t command = 0; 79 uint16_t *iptr; 80 uint16_t __iomem *optr; 81 uint32_t cnt; 82 uint32_t mboxes; 83 uint16_t __iomem *mbx_reg; 84 unsigned long wait_time; 85 struct qla_hw_data *ha = vha->hw; 86 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 87 88 89 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__); 90 91 if (ha->pdev->error_state > pci_channel_io_frozen) { 92 ql_log(ql_log_warn, vha, 0x1001, 93 "error_state is greater than pci_channel_io_frozen, " 94 "exiting.\n"); 95 return QLA_FUNCTION_TIMEOUT; 96 } 97 98 if (vha->device_flags & DFLG_DEV_FAILED) { 99 ql_log(ql_log_warn, vha, 0x1002, 100 "Device in failed state, exiting.\n"); 101 return QLA_FUNCTION_TIMEOUT; 102 } 103 104 /* if PCI error, then avoid mbx processing.*/ 105 if (test_bit(PCI_ERR, &base_vha->dpc_flags)) { 106 ql_log(ql_log_warn, vha, 0x1191, 107 "PCI error, exiting.\n"); 108 return QLA_FUNCTION_TIMEOUT; 109 } 110 111 reg = ha->iobase; 112 io_lock_on = base_vha->flags.init_done; 113 114 rval = QLA_SUCCESS; 115 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 116 117 118 if (ha->flags.pci_channel_io_perm_failure) { 119 ql_log(ql_log_warn, vha, 0x1003, 120 "Perm failure on EEH timeout MBX, exiting.\n"); 121 return QLA_FUNCTION_TIMEOUT; 122 } 123 124 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 125 /* Setting Link-Down error */ 126 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 127 ql_log(ql_log_warn, vha, 0x1004, 128 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 129 return QLA_FUNCTION_TIMEOUT; 130 } 131 132 /* check if ISP abort is active and return cmd with timeout */ 133 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 134 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 135 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) && 136 !is_rom_cmd(mcp->mb[0])) { 137 ql_log(ql_log_info, vha, 0x1005, 138 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n", 139 mcp->mb[0]); 140 return QLA_FUNCTION_TIMEOUT; 141 } 142 143 /* 144 * Wait for active mailbox commands to finish by waiting at most tov 145 * seconds. This is to serialize actual issuing of mailbox cmds during 146 * non ISP abort time. 147 */ 148 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) { 149 /* Timeout occurred. Return error. */ 150 ql_log(ql_log_warn, vha, 0x1005, 151 "Cmd access timeout, cmd=0x%x, Exiting.\n", 152 mcp->mb[0]); 153 return QLA_FUNCTION_TIMEOUT; 154 } 155 156 ha->flags.mbox_busy = 1; 157 /* Save mailbox command for debug */ 158 ha->mcp = mcp; 159 160 ql_dbg(ql_dbg_mbx, vha, 0x1006, 161 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); 162 163 spin_lock_irqsave(&ha->hardware_lock, flags); 164 165 /* Load mailbox registers. */ 166 if (IS_P3P_TYPE(ha)) 167 optr = (uint16_t __iomem *)®->isp82.mailbox_in[0]; 168 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) 169 optr = (uint16_t __iomem *)®->isp24.mailbox0; 170 else 171 optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); 172 173 iptr = mcp->mb; 174 command = mcp->mb[0]; 175 mboxes = mcp->out_mb; 176 177 ql_dbg(ql_dbg_mbx, vha, 0x1111, 178 "Mailbox registers (OUT):\n"); 179 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 180 if (IS_QLA2200(ha) && cnt == 8) 181 optr = 182 (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 8); 183 if (mboxes & BIT_0) { 184 ql_dbg(ql_dbg_mbx, vha, 0x1112, 185 "mbox[%d]<-0x%04x\n", cnt, *iptr); 186 WRT_REG_WORD(optr, *iptr); 187 } 188 189 mboxes >>= 1; 190 optr++; 191 iptr++; 192 } 193 194 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117, 195 "I/O Address = %p.\n", optr); 196 197 /* Issue set host interrupt command to send cmd out. */ 198 ha->flags.mbox_int = 0; 199 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 200 201 /* Unlock mbx registers and wait for interrupt */ 202 ql_dbg(ql_dbg_mbx, vha, 0x100f, 203 "Going to unlock irq & waiting for interrupts. " 204 "jiffies=%lx.\n", jiffies); 205 206 /* Wait for mbx cmd completion until timeout */ 207 208 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { 209 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 210 211 if (IS_P3P_TYPE(ha)) { 212 if (RD_REG_DWORD(®->isp82.hint) & 213 HINT_MBX_INT_PENDING) { 214 spin_unlock_irqrestore(&ha->hardware_lock, 215 flags); 216 ha->flags.mbox_busy = 0; 217 ql_dbg(ql_dbg_mbx, vha, 0x1010, 218 "Pending mailbox timeout, exiting.\n"); 219 rval = QLA_FUNCTION_TIMEOUT; 220 goto premature_exit; 221 } 222 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 223 } else if (IS_FWI2_CAPABLE(ha)) 224 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 225 else 226 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 227 spin_unlock_irqrestore(&ha->hardware_lock, flags); 228 229 wait_time = jiffies; 230 if (!wait_for_completion_timeout(&ha->mbx_intr_comp, 231 mcp->tov * HZ)) { 232 ql_dbg(ql_dbg_mbx, vha, 0x117a, 233 "cmd=%x Timeout.\n", command); 234 spin_lock_irqsave(&ha->hardware_lock, flags); 235 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 236 spin_unlock_irqrestore(&ha->hardware_lock, flags); 237 } 238 if (time_after(jiffies, wait_time + 5 * HZ)) 239 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n", 240 command, jiffies_to_msecs(jiffies - wait_time)); 241 } else { 242 ql_dbg(ql_dbg_mbx, vha, 0x1011, 243 "Cmd=%x Polling Mode.\n", command); 244 245 if (IS_P3P_TYPE(ha)) { 246 if (RD_REG_DWORD(®->isp82.hint) & 247 HINT_MBX_INT_PENDING) { 248 spin_unlock_irqrestore(&ha->hardware_lock, 249 flags); 250 ha->flags.mbox_busy = 0; 251 ql_dbg(ql_dbg_mbx, vha, 0x1012, 252 "Pending mailbox timeout, exiting.\n"); 253 rval = QLA_FUNCTION_TIMEOUT; 254 goto premature_exit; 255 } 256 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 257 } else if (IS_FWI2_CAPABLE(ha)) 258 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 259 else 260 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 261 spin_unlock_irqrestore(&ha->hardware_lock, flags); 262 263 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */ 264 while (!ha->flags.mbox_int) { 265 if (time_after(jiffies, wait_time)) 266 break; 267 268 /* Check for pending interrupts. */ 269 qla2x00_poll(ha->rsp_q_map[0]); 270 271 if (!ha->flags.mbox_int && 272 !(IS_QLA2200(ha) && 273 command == MBC_LOAD_RISC_RAM_EXTENDED)) 274 msleep(10); 275 } /* while */ 276 ql_dbg(ql_dbg_mbx, vha, 0x1013, 277 "Waited %d sec.\n", 278 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ)); 279 } 280 281 /* Check whether we timed out */ 282 if (ha->flags.mbox_int) { 283 uint16_t *iptr2; 284 285 ql_dbg(ql_dbg_mbx, vha, 0x1014, 286 "Cmd=%x completed.\n", command); 287 288 /* Got interrupt. Clear the flag. */ 289 ha->flags.mbox_int = 0; 290 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 291 292 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 293 ha->flags.mbox_busy = 0; 294 /* Setting Link-Down error */ 295 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 296 ha->mcp = NULL; 297 rval = QLA_FUNCTION_FAILED; 298 ql_log(ql_log_warn, vha, 0x1015, 299 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 300 goto premature_exit; 301 } 302 303 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) 304 rval = QLA_FUNCTION_FAILED; 305 306 /* Load return mailbox registers. */ 307 iptr2 = mcp->mb; 308 iptr = (uint16_t *)&ha->mailbox_out[0]; 309 mboxes = mcp->in_mb; 310 311 ql_dbg(ql_dbg_mbx, vha, 0x1113, 312 "Mailbox registers (IN):\n"); 313 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 314 if (mboxes & BIT_0) { 315 *iptr2 = *iptr; 316 ql_dbg(ql_dbg_mbx, vha, 0x1114, 317 "mbox[%d]->0x%04x\n", cnt, *iptr2); 318 } 319 320 mboxes >>= 1; 321 iptr2++; 322 iptr++; 323 } 324 } else { 325 326 uint16_t mb[8]; 327 uint32_t ictrl, host_status, hccr; 328 uint16_t w; 329 330 if (IS_FWI2_CAPABLE(ha)) { 331 mb[0] = RD_REG_WORD(®->isp24.mailbox0); 332 mb[1] = RD_REG_WORD(®->isp24.mailbox1); 333 mb[2] = RD_REG_WORD(®->isp24.mailbox2); 334 mb[3] = RD_REG_WORD(®->isp24.mailbox3); 335 mb[7] = RD_REG_WORD(®->isp24.mailbox7); 336 ictrl = RD_REG_DWORD(®->isp24.ictrl); 337 host_status = RD_REG_DWORD(®->isp24.host_status); 338 hccr = RD_REG_DWORD(®->isp24.hccr); 339 340 ql_log(ql_log_warn, vha, 0x1119, 341 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx " 342 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n", 343 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3], 344 mb[7], host_status, hccr); 345 346 } else { 347 mb[0] = RD_MAILBOX_REG(ha, ®->isp, 0); 348 ictrl = RD_REG_WORD(®->isp.ictrl); 349 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119, 350 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx " 351 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]); 352 } 353 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019); 354 355 /* Capture FW dump only, if PCI device active */ 356 if (!pci_channel_offline(vha->hw->pdev)) { 357 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 358 if (w == 0xffff || ictrl == 0xffffffff) { 359 /* This is special case if there is unload 360 * of driver happening and if PCI device go 361 * into bad state due to PCI error condition 362 * then only PCI ERR flag would be set. 363 * we will do premature exit for above case. 364 */ 365 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 366 set_bit(PCI_ERR, &base_vha->dpc_flags); 367 ha->flags.mbox_busy = 0; 368 rval = QLA_FUNCTION_TIMEOUT; 369 goto premature_exit; 370 } 371 372 /* Attempt to capture firmware dump for further 373 * anallysis of the current formware state. we do not 374 * need to do this if we are intentionally generating 375 * a dump 376 */ 377 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) 378 ha->isp_ops->fw_dump(vha, 0); 379 rval = QLA_FUNCTION_TIMEOUT; 380 } 381 } 382 383 ha->flags.mbox_busy = 0; 384 385 /* Clean up */ 386 ha->mcp = NULL; 387 388 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) { 389 ql_dbg(ql_dbg_mbx, vha, 0x101a, 390 "Checking for additional resp interrupt.\n"); 391 392 /* polling mode for non isp_abort commands. */ 393 qla2x00_poll(ha->rsp_q_map[0]); 394 } 395 396 if (rval == QLA_FUNCTION_TIMEOUT && 397 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) { 398 if (!io_lock_on || (mcp->flags & IOCTL_CMD) || 399 ha->flags.eeh_busy) { 400 /* not in dpc. schedule it for dpc to take over. */ 401 ql_dbg(ql_dbg_mbx, vha, 0x101b, 402 "Timeout, schedule isp_abort_needed.\n"); 403 404 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 405 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 406 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 407 if (IS_QLA82XX(ha)) { 408 ql_dbg(ql_dbg_mbx, vha, 0x112a, 409 "disabling pause transmit on port " 410 "0 & 1.\n"); 411 qla82xx_wr_32(ha, 412 QLA82XX_CRB_NIU + 0x98, 413 CRB_NIU_XG_PAUSE_CTL_P0| 414 CRB_NIU_XG_PAUSE_CTL_P1); 415 } 416 ql_log(ql_log_info, base_vha, 0x101c, 417 "Mailbox cmd timeout occurred, cmd=0x%x, " 418 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP " 419 "abort.\n", command, mcp->mb[0], 420 ha->flags.eeh_busy); 421 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 422 qla2xxx_wake_dpc(vha); 423 } 424 } else if (!abort_active) { 425 /* call abort directly since we are in the DPC thread */ 426 ql_dbg(ql_dbg_mbx, vha, 0x101d, 427 "Timeout, calling abort_isp.\n"); 428 429 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 430 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 431 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 432 if (IS_QLA82XX(ha)) { 433 ql_dbg(ql_dbg_mbx, vha, 0x112b, 434 "disabling pause transmit on port " 435 "0 & 1.\n"); 436 qla82xx_wr_32(ha, 437 QLA82XX_CRB_NIU + 0x98, 438 CRB_NIU_XG_PAUSE_CTL_P0| 439 CRB_NIU_XG_PAUSE_CTL_P1); 440 } 441 ql_log(ql_log_info, base_vha, 0x101e, 442 "Mailbox cmd timeout occurred, cmd=0x%x, " 443 "mb[0]=0x%x. Scheduling ISP abort ", 444 command, mcp->mb[0]); 445 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 446 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 447 /* Allow next mbx cmd to come in. */ 448 complete(&ha->mbx_cmd_comp); 449 if (ha->isp_ops->abort_isp(vha)) { 450 /* Failed. retry later. */ 451 set_bit(ISP_ABORT_NEEDED, 452 &vha->dpc_flags); 453 } 454 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 455 ql_dbg(ql_dbg_mbx, vha, 0x101f, 456 "Finished abort_isp.\n"); 457 goto mbx_done; 458 } 459 } 460 } 461 462 premature_exit: 463 /* Allow next mbx cmd to come in. */ 464 complete(&ha->mbx_cmd_comp); 465 466 mbx_done: 467 if (rval) { 468 ql_dbg(ql_dbg_disc, base_vha, 0x1020, 469 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n", 470 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command); 471 472 ql_dbg(ql_dbg_mbx, vha, 0x1198, 473 "host status: 0x%x, flags:0x%lx, intr ctrl reg:0x%x, intr status:0x%x\n", 474 RD_REG_DWORD(®->isp24.host_status), 475 ha->fw_dump_cap_flags, 476 RD_REG_DWORD(®->isp24.ictrl), 477 RD_REG_DWORD(®->isp24.istatus)); 478 479 mbx_reg = ®->isp24.mailbox0; 480 for (i = 0; i < 6; i++) 481 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1199, 482 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); 483 } else { 484 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__); 485 } 486 487 return rval; 488 } 489 490 int 491 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr, 492 uint32_t risc_code_size) 493 { 494 int rval; 495 struct qla_hw_data *ha = vha->hw; 496 mbx_cmd_t mc; 497 mbx_cmd_t *mcp = &mc; 498 499 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022, 500 "Entered %s.\n", __func__); 501 502 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) { 503 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; 504 mcp->mb[8] = MSW(risc_addr); 505 mcp->out_mb = MBX_8|MBX_0; 506 } else { 507 mcp->mb[0] = MBC_LOAD_RISC_RAM; 508 mcp->out_mb = MBX_0; 509 } 510 mcp->mb[1] = LSW(risc_addr); 511 mcp->mb[2] = MSW(req_dma); 512 mcp->mb[3] = LSW(req_dma); 513 mcp->mb[6] = MSW(MSD(req_dma)); 514 mcp->mb[7] = LSW(MSD(req_dma)); 515 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 516 if (IS_FWI2_CAPABLE(ha)) { 517 mcp->mb[4] = MSW(risc_code_size); 518 mcp->mb[5] = LSW(risc_code_size); 519 mcp->out_mb |= MBX_5|MBX_4; 520 } else { 521 mcp->mb[4] = LSW(risc_code_size); 522 mcp->out_mb |= MBX_4; 523 } 524 525 mcp->in_mb = MBX_0; 526 mcp->tov = MBX_TOV_SECONDS; 527 mcp->flags = 0; 528 rval = qla2x00_mailbox_command(vha, mcp); 529 530 if (rval != QLA_SUCCESS) { 531 ql_dbg(ql_dbg_mbx, vha, 0x1023, 532 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 533 } else { 534 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024, 535 "Done %s.\n", __func__); 536 } 537 538 return rval; 539 } 540 541 #define EXTENDED_BB_CREDITS BIT_0 542 /* 543 * qla2x00_execute_fw 544 * Start adapter firmware. 545 * 546 * Input: 547 * ha = adapter block pointer. 548 * TARGET_QUEUE_LOCK must be released. 549 * ADAPTER_STATE_LOCK must be released. 550 * 551 * Returns: 552 * qla2x00 local function return status code. 553 * 554 * Context: 555 * Kernel context. 556 */ 557 int 558 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr) 559 { 560 int rval; 561 struct qla_hw_data *ha = vha->hw; 562 mbx_cmd_t mc; 563 mbx_cmd_t *mcp = &mc; 564 565 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025, 566 "Entered %s.\n", __func__); 567 568 mcp->mb[0] = MBC_EXECUTE_FIRMWARE; 569 mcp->out_mb = MBX_0; 570 mcp->in_mb = MBX_0; 571 if (IS_FWI2_CAPABLE(ha)) { 572 mcp->mb[1] = MSW(risc_addr); 573 mcp->mb[2] = LSW(risc_addr); 574 mcp->mb[3] = 0; 575 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 576 IS_QLA27XX(ha)) { 577 struct nvram_81xx *nv = ha->nvram; 578 mcp->mb[4] = (nv->enhanced_features & 579 EXTENDED_BB_CREDITS); 580 } else 581 mcp->mb[4] = 0; 582 583 if (ha->flags.exlogins_enabled) 584 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN; 585 586 if (ha->flags.exchoffld_enabled) 587 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD; 588 589 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1; 590 mcp->in_mb |= MBX_1; 591 } else { 592 mcp->mb[1] = LSW(risc_addr); 593 mcp->out_mb |= MBX_1; 594 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 595 mcp->mb[2] = 0; 596 mcp->out_mb |= MBX_2; 597 } 598 } 599 600 mcp->tov = MBX_TOV_SECONDS; 601 mcp->flags = 0; 602 rval = qla2x00_mailbox_command(vha, mcp); 603 604 if (rval != QLA_SUCCESS) { 605 ql_dbg(ql_dbg_mbx, vha, 0x1026, 606 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 607 } else { 608 if (IS_FWI2_CAPABLE(ha)) { 609 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027, 610 "Done exchanges=%x.\n", mcp->mb[1]); 611 } else { 612 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028, 613 "Done %s.\n", __func__); 614 } 615 } 616 617 return rval; 618 } 619 620 /* 621 * qla_get_exlogin_status 622 * Get extended login status 623 * uses the memory offload control/status Mailbox 624 * 625 * Input: 626 * ha: adapter state pointer. 627 * fwopt: firmware options 628 * 629 * Returns: 630 * qla2x00 local function status 631 * 632 * Context: 633 * Kernel context. 634 */ 635 #define FETCH_XLOGINS_STAT 0x8 636 int 637 qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz, 638 uint16_t *ex_logins_cnt) 639 { 640 int rval; 641 mbx_cmd_t mc; 642 mbx_cmd_t *mcp = &mc; 643 644 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f, 645 "Entered %s\n", __func__); 646 647 memset(mcp->mb, 0 , sizeof(mcp->mb)); 648 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 649 mcp->mb[1] = FETCH_XLOGINS_STAT; 650 mcp->out_mb = MBX_1|MBX_0; 651 mcp->in_mb = MBX_10|MBX_4|MBX_0; 652 mcp->tov = MBX_TOV_SECONDS; 653 mcp->flags = 0; 654 655 rval = qla2x00_mailbox_command(vha, mcp); 656 if (rval != QLA_SUCCESS) { 657 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval); 658 } else { 659 *buf_sz = mcp->mb[4]; 660 *ex_logins_cnt = mcp->mb[10]; 661 662 ql_log(ql_log_info, vha, 0x1190, 663 "buffer size 0x%x, exchange login count=%d\n", 664 mcp->mb[4], mcp->mb[10]); 665 666 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116, 667 "Done %s.\n", __func__); 668 } 669 670 return rval; 671 } 672 673 /* 674 * qla_set_exlogin_mem_cfg 675 * set extended login memory configuration 676 * Mbx needs to be issues before init_cb is set 677 * 678 * Input: 679 * ha: adapter state pointer. 680 * buffer: buffer pointer 681 * phys_addr: physical address of buffer 682 * size: size of buffer 683 * TARGET_QUEUE_LOCK must be released 684 * ADAPTER_STATE_LOCK must be release 685 * 686 * Returns: 687 * qla2x00 local funxtion status code. 688 * 689 * Context: 690 * Kernel context. 691 */ 692 #define CONFIG_XLOGINS_MEM 0x3 693 int 694 qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr) 695 { 696 int rval; 697 mbx_cmd_t mc; 698 mbx_cmd_t *mcp = &mc; 699 struct qla_hw_data *ha = vha->hw; 700 701 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a, 702 "Entered %s.\n", __func__); 703 704 memset(mcp->mb, 0 , sizeof(mcp->mb)); 705 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 706 mcp->mb[1] = CONFIG_XLOGINS_MEM; 707 mcp->mb[2] = MSW(phys_addr); 708 mcp->mb[3] = LSW(phys_addr); 709 mcp->mb[6] = MSW(MSD(phys_addr)); 710 mcp->mb[7] = LSW(MSD(phys_addr)); 711 mcp->mb[8] = MSW(ha->exlogin_size); 712 mcp->mb[9] = LSW(ha->exlogin_size); 713 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 714 mcp->in_mb = MBX_11|MBX_0; 715 mcp->tov = MBX_TOV_SECONDS; 716 mcp->flags = 0; 717 rval = qla2x00_mailbox_command(vha, mcp); 718 if (rval != QLA_SUCCESS) { 719 /*EMPTY*/ 720 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval); 721 } else { 722 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c, 723 "Done %s.\n", __func__); 724 } 725 726 return rval; 727 } 728 729 /* 730 * qla_get_exchoffld_status 731 * Get exchange offload status 732 * uses the memory offload control/status Mailbox 733 * 734 * Input: 735 * ha: adapter state pointer. 736 * fwopt: firmware options 737 * 738 * Returns: 739 * qla2x00 local function status 740 * 741 * Context: 742 * Kernel context. 743 */ 744 #define FETCH_XCHOFFLD_STAT 0x2 745 int 746 qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz, 747 uint16_t *ex_logins_cnt) 748 { 749 int rval; 750 mbx_cmd_t mc; 751 mbx_cmd_t *mcp = &mc; 752 753 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019, 754 "Entered %s\n", __func__); 755 756 memset(mcp->mb, 0 , sizeof(mcp->mb)); 757 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 758 mcp->mb[1] = FETCH_XCHOFFLD_STAT; 759 mcp->out_mb = MBX_1|MBX_0; 760 mcp->in_mb = MBX_10|MBX_4|MBX_0; 761 mcp->tov = MBX_TOV_SECONDS; 762 mcp->flags = 0; 763 764 rval = qla2x00_mailbox_command(vha, mcp); 765 if (rval != QLA_SUCCESS) { 766 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval); 767 } else { 768 *buf_sz = mcp->mb[4]; 769 *ex_logins_cnt = mcp->mb[10]; 770 771 ql_log(ql_log_info, vha, 0x118e, 772 "buffer size 0x%x, exchange offload count=%d\n", 773 mcp->mb[4], mcp->mb[10]); 774 775 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156, 776 "Done %s.\n", __func__); 777 } 778 779 return rval; 780 } 781 782 /* 783 * qla_set_exchoffld_mem_cfg 784 * Set exchange offload memory configuration 785 * Mbx needs to be issues before init_cb is set 786 * 787 * Input: 788 * ha: adapter state pointer. 789 * buffer: buffer pointer 790 * phys_addr: physical address of buffer 791 * size: size of buffer 792 * TARGET_QUEUE_LOCK must be released 793 * ADAPTER_STATE_LOCK must be release 794 * 795 * Returns: 796 * qla2x00 local funxtion status code. 797 * 798 * Context: 799 * Kernel context. 800 */ 801 #define CONFIG_XCHOFFLD_MEM 0x3 802 int 803 qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr) 804 { 805 int rval; 806 mbx_cmd_t mc; 807 mbx_cmd_t *mcp = &mc; 808 struct qla_hw_data *ha = vha->hw; 809 810 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157, 811 "Entered %s.\n", __func__); 812 813 memset(mcp->mb, 0 , sizeof(mcp->mb)); 814 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 815 mcp->mb[1] = CONFIG_XCHOFFLD_MEM; 816 mcp->mb[2] = MSW(phys_addr); 817 mcp->mb[3] = LSW(phys_addr); 818 mcp->mb[6] = MSW(MSD(phys_addr)); 819 mcp->mb[7] = LSW(MSD(phys_addr)); 820 mcp->mb[8] = MSW(ha->exlogin_size); 821 mcp->mb[9] = LSW(ha->exlogin_size); 822 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 823 mcp->in_mb = MBX_11|MBX_0; 824 mcp->tov = MBX_TOV_SECONDS; 825 mcp->flags = 0; 826 rval = qla2x00_mailbox_command(vha, mcp); 827 if (rval != QLA_SUCCESS) { 828 /*EMPTY*/ 829 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval); 830 } else { 831 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192, 832 "Done %s.\n", __func__); 833 } 834 835 return rval; 836 } 837 838 /* 839 * qla2x00_get_fw_version 840 * Get firmware version. 841 * 842 * Input: 843 * ha: adapter state pointer. 844 * major: pointer for major number. 845 * minor: pointer for minor number. 846 * subminor: pointer for subminor number. 847 * 848 * Returns: 849 * qla2x00 local function return status code. 850 * 851 * Context: 852 * Kernel context. 853 */ 854 int 855 qla2x00_get_fw_version(scsi_qla_host_t *vha) 856 { 857 int rval; 858 mbx_cmd_t mc; 859 mbx_cmd_t *mcp = &mc; 860 struct qla_hw_data *ha = vha->hw; 861 862 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029, 863 "Entered %s.\n", __func__); 864 865 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION; 866 mcp->out_mb = MBX_0; 867 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 868 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha)) 869 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8; 870 if (IS_FWI2_CAPABLE(ha)) 871 mcp->in_mb |= MBX_17|MBX_16|MBX_15; 872 if (IS_QLA27XX(ha)) 873 mcp->in_mb |= 874 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18| 875 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8; 876 877 mcp->flags = 0; 878 mcp->tov = MBX_TOV_SECONDS; 879 rval = qla2x00_mailbox_command(vha, mcp); 880 if (rval != QLA_SUCCESS) 881 goto failed; 882 883 /* Return mailbox data. */ 884 ha->fw_major_version = mcp->mb[1]; 885 ha->fw_minor_version = mcp->mb[2]; 886 ha->fw_subminor_version = mcp->mb[3]; 887 ha->fw_attributes = mcp->mb[6]; 888 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw)) 889 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */ 890 else 891 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4]; 892 893 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) { 894 ha->mpi_version[0] = mcp->mb[10] & 0xff; 895 ha->mpi_version[1] = mcp->mb[11] >> 8; 896 ha->mpi_version[2] = mcp->mb[11] & 0xff; 897 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13]; 898 ha->phy_version[0] = mcp->mb[8] & 0xff; 899 ha->phy_version[1] = mcp->mb[9] >> 8; 900 ha->phy_version[2] = mcp->mb[9] & 0xff; 901 } 902 903 if (IS_FWI2_CAPABLE(ha)) { 904 ha->fw_attributes_h = mcp->mb[15]; 905 ha->fw_attributes_ext[0] = mcp->mb[16]; 906 ha->fw_attributes_ext[1] = mcp->mb[17]; 907 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139, 908 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n", 909 __func__, mcp->mb[15], mcp->mb[6]); 910 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f, 911 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n", 912 __func__, mcp->mb[17], mcp->mb[16]); 913 914 if (ha->fw_attributes_h & 0x4) 915 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d, 916 "%s: Firmware supports Extended Login 0x%x\n", 917 __func__, ha->fw_attributes_h); 918 919 if (ha->fw_attributes_h & 0x8) 920 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191, 921 "%s: Firmware supports Exchange Offload 0x%x\n", 922 __func__, ha->fw_attributes_h); 923 } 924 925 if (IS_QLA27XX(ha)) { 926 ha->mpi_version[0] = mcp->mb[10] & 0xff; 927 ha->mpi_version[1] = mcp->mb[11] >> 8; 928 ha->mpi_version[2] = mcp->mb[11] & 0xff; 929 ha->pep_version[0] = mcp->mb[13] & 0xff; 930 ha->pep_version[1] = mcp->mb[14] >> 8; 931 ha->pep_version[2] = mcp->mb[14] & 0xff; 932 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18]; 933 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20]; 934 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22]; 935 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24]; 936 } 937 938 failed: 939 if (rval != QLA_SUCCESS) { 940 /*EMPTY*/ 941 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval); 942 } else { 943 /*EMPTY*/ 944 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b, 945 "Done %s.\n", __func__); 946 } 947 return rval; 948 } 949 950 /* 951 * qla2x00_get_fw_options 952 * Set firmware options. 953 * 954 * Input: 955 * ha = adapter block pointer. 956 * fwopt = pointer for firmware options. 957 * 958 * Returns: 959 * qla2x00 local function return status code. 960 * 961 * Context: 962 * Kernel context. 963 */ 964 int 965 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 966 { 967 int rval; 968 mbx_cmd_t mc; 969 mbx_cmd_t *mcp = &mc; 970 971 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c, 972 "Entered %s.\n", __func__); 973 974 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION; 975 mcp->out_mb = MBX_0; 976 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 977 mcp->tov = MBX_TOV_SECONDS; 978 mcp->flags = 0; 979 rval = qla2x00_mailbox_command(vha, mcp); 980 981 if (rval != QLA_SUCCESS) { 982 /*EMPTY*/ 983 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval); 984 } else { 985 fwopts[0] = mcp->mb[0]; 986 fwopts[1] = mcp->mb[1]; 987 fwopts[2] = mcp->mb[2]; 988 fwopts[3] = mcp->mb[3]; 989 990 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e, 991 "Done %s.\n", __func__); 992 } 993 994 return rval; 995 } 996 997 998 /* 999 * qla2x00_set_fw_options 1000 * Set firmware options. 1001 * 1002 * Input: 1003 * ha = adapter block pointer. 1004 * fwopt = pointer for firmware options. 1005 * 1006 * Returns: 1007 * qla2x00 local function return status code. 1008 * 1009 * Context: 1010 * Kernel context. 1011 */ 1012 int 1013 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 1014 { 1015 int rval; 1016 mbx_cmd_t mc; 1017 mbx_cmd_t *mcp = &mc; 1018 1019 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f, 1020 "Entered %s.\n", __func__); 1021 1022 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION; 1023 mcp->mb[1] = fwopts[1]; 1024 mcp->mb[2] = fwopts[2]; 1025 mcp->mb[3] = fwopts[3]; 1026 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1027 mcp->in_mb = MBX_0; 1028 if (IS_FWI2_CAPABLE(vha->hw)) { 1029 mcp->in_mb |= MBX_1; 1030 } else { 1031 mcp->mb[10] = fwopts[10]; 1032 mcp->mb[11] = fwopts[11]; 1033 mcp->mb[12] = 0; /* Undocumented, but used */ 1034 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 1035 } 1036 mcp->tov = MBX_TOV_SECONDS; 1037 mcp->flags = 0; 1038 rval = qla2x00_mailbox_command(vha, mcp); 1039 1040 fwopts[0] = mcp->mb[0]; 1041 1042 if (rval != QLA_SUCCESS) { 1043 /*EMPTY*/ 1044 ql_dbg(ql_dbg_mbx, vha, 0x1030, 1045 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]); 1046 } else { 1047 /*EMPTY*/ 1048 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031, 1049 "Done %s.\n", __func__); 1050 } 1051 1052 return rval; 1053 } 1054 1055 /* 1056 * qla2x00_mbx_reg_test 1057 * Mailbox register wrap test. 1058 * 1059 * Input: 1060 * ha = adapter block pointer. 1061 * TARGET_QUEUE_LOCK must be released. 1062 * ADAPTER_STATE_LOCK must be released. 1063 * 1064 * Returns: 1065 * qla2x00 local function return status code. 1066 * 1067 * Context: 1068 * Kernel context. 1069 */ 1070 int 1071 qla2x00_mbx_reg_test(scsi_qla_host_t *vha) 1072 { 1073 int rval; 1074 mbx_cmd_t mc; 1075 mbx_cmd_t *mcp = &mc; 1076 1077 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032, 1078 "Entered %s.\n", __func__); 1079 1080 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; 1081 mcp->mb[1] = 0xAAAA; 1082 mcp->mb[2] = 0x5555; 1083 mcp->mb[3] = 0xAA55; 1084 mcp->mb[4] = 0x55AA; 1085 mcp->mb[5] = 0xA5A5; 1086 mcp->mb[6] = 0x5A5A; 1087 mcp->mb[7] = 0x2525; 1088 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1089 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1090 mcp->tov = MBX_TOV_SECONDS; 1091 mcp->flags = 0; 1092 rval = qla2x00_mailbox_command(vha, mcp); 1093 1094 if (rval == QLA_SUCCESS) { 1095 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 || 1096 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA) 1097 rval = QLA_FUNCTION_FAILED; 1098 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A || 1099 mcp->mb[7] != 0x2525) 1100 rval = QLA_FUNCTION_FAILED; 1101 } 1102 1103 if (rval != QLA_SUCCESS) { 1104 /*EMPTY*/ 1105 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval); 1106 } else { 1107 /*EMPTY*/ 1108 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034, 1109 "Done %s.\n", __func__); 1110 } 1111 1112 return rval; 1113 } 1114 1115 /* 1116 * qla2x00_verify_checksum 1117 * Verify firmware checksum. 1118 * 1119 * Input: 1120 * ha = adapter block pointer. 1121 * TARGET_QUEUE_LOCK must be released. 1122 * ADAPTER_STATE_LOCK must be released. 1123 * 1124 * Returns: 1125 * qla2x00 local function return status code. 1126 * 1127 * Context: 1128 * Kernel context. 1129 */ 1130 int 1131 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr) 1132 { 1133 int rval; 1134 mbx_cmd_t mc; 1135 mbx_cmd_t *mcp = &mc; 1136 1137 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035, 1138 "Entered %s.\n", __func__); 1139 1140 mcp->mb[0] = MBC_VERIFY_CHECKSUM; 1141 mcp->out_mb = MBX_0; 1142 mcp->in_mb = MBX_0; 1143 if (IS_FWI2_CAPABLE(vha->hw)) { 1144 mcp->mb[1] = MSW(risc_addr); 1145 mcp->mb[2] = LSW(risc_addr); 1146 mcp->out_mb |= MBX_2|MBX_1; 1147 mcp->in_mb |= MBX_2|MBX_1; 1148 } else { 1149 mcp->mb[1] = LSW(risc_addr); 1150 mcp->out_mb |= MBX_1; 1151 mcp->in_mb |= MBX_1; 1152 } 1153 1154 mcp->tov = MBX_TOV_SECONDS; 1155 mcp->flags = 0; 1156 rval = qla2x00_mailbox_command(vha, mcp); 1157 1158 if (rval != QLA_SUCCESS) { 1159 ql_dbg(ql_dbg_mbx, vha, 0x1036, 1160 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ? 1161 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]); 1162 } else { 1163 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037, 1164 "Done %s.\n", __func__); 1165 } 1166 1167 return rval; 1168 } 1169 1170 /* 1171 * qla2x00_issue_iocb 1172 * Issue IOCB using mailbox command 1173 * 1174 * Input: 1175 * ha = adapter state pointer. 1176 * buffer = buffer pointer. 1177 * phys_addr = physical address of buffer. 1178 * size = size of buffer. 1179 * TARGET_QUEUE_LOCK must be released. 1180 * ADAPTER_STATE_LOCK must be released. 1181 * 1182 * Returns: 1183 * qla2x00 local function return status code. 1184 * 1185 * Context: 1186 * Kernel context. 1187 */ 1188 int 1189 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer, 1190 dma_addr_t phys_addr, size_t size, uint32_t tov) 1191 { 1192 int rval; 1193 mbx_cmd_t mc; 1194 mbx_cmd_t *mcp = &mc; 1195 1196 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038, 1197 "Entered %s.\n", __func__); 1198 1199 mcp->mb[0] = MBC_IOCB_COMMAND_A64; 1200 mcp->mb[1] = 0; 1201 mcp->mb[2] = MSW(phys_addr); 1202 mcp->mb[3] = LSW(phys_addr); 1203 mcp->mb[6] = MSW(MSD(phys_addr)); 1204 mcp->mb[7] = LSW(MSD(phys_addr)); 1205 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1206 mcp->in_mb = MBX_2|MBX_0; 1207 mcp->tov = tov; 1208 mcp->flags = 0; 1209 rval = qla2x00_mailbox_command(vha, mcp); 1210 1211 if (rval != QLA_SUCCESS) { 1212 /*EMPTY*/ 1213 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval); 1214 } else { 1215 sts_entry_t *sts_entry = (sts_entry_t *) buffer; 1216 1217 /* Mask reserved bits. */ 1218 sts_entry->entry_status &= 1219 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK; 1220 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a, 1221 "Done %s.\n", __func__); 1222 } 1223 1224 return rval; 1225 } 1226 1227 int 1228 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr, 1229 size_t size) 1230 { 1231 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size, 1232 MBX_TOV_SECONDS); 1233 } 1234 1235 /* 1236 * qla2x00_abort_command 1237 * Abort command aborts a specified IOCB. 1238 * 1239 * Input: 1240 * ha = adapter block pointer. 1241 * sp = SB structure pointer. 1242 * 1243 * Returns: 1244 * qla2x00 local function return status code. 1245 * 1246 * Context: 1247 * Kernel context. 1248 */ 1249 int 1250 qla2x00_abort_command(srb_t *sp) 1251 { 1252 unsigned long flags = 0; 1253 int rval; 1254 uint32_t handle = 0; 1255 mbx_cmd_t mc; 1256 mbx_cmd_t *mcp = &mc; 1257 fc_port_t *fcport = sp->fcport; 1258 scsi_qla_host_t *vha = fcport->vha; 1259 struct qla_hw_data *ha = vha->hw; 1260 struct req_que *req; 1261 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1262 1263 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b, 1264 "Entered %s.\n", __func__); 1265 1266 if (vha->flags.qpairs_available && sp->qpair) 1267 req = sp->qpair->req; 1268 else 1269 req = vha->req; 1270 1271 spin_lock_irqsave(&ha->hardware_lock, flags); 1272 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 1273 if (req->outstanding_cmds[handle] == sp) 1274 break; 1275 } 1276 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1277 1278 if (handle == req->num_outstanding_cmds) { 1279 /* command not found */ 1280 return QLA_FUNCTION_FAILED; 1281 } 1282 1283 mcp->mb[0] = MBC_ABORT_COMMAND; 1284 if (HAS_EXTENDED_IDS(ha)) 1285 mcp->mb[1] = fcport->loop_id; 1286 else 1287 mcp->mb[1] = fcport->loop_id << 8; 1288 mcp->mb[2] = (uint16_t)handle; 1289 mcp->mb[3] = (uint16_t)(handle >> 16); 1290 mcp->mb[6] = (uint16_t)cmd->device->lun; 1291 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1292 mcp->in_mb = MBX_0; 1293 mcp->tov = MBX_TOV_SECONDS; 1294 mcp->flags = 0; 1295 rval = qla2x00_mailbox_command(vha, mcp); 1296 1297 if (rval != QLA_SUCCESS) { 1298 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval); 1299 } else { 1300 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d, 1301 "Done %s.\n", __func__); 1302 } 1303 1304 return rval; 1305 } 1306 1307 int 1308 qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag) 1309 { 1310 int rval, rval2; 1311 mbx_cmd_t mc; 1312 mbx_cmd_t *mcp = &mc; 1313 scsi_qla_host_t *vha; 1314 struct req_que *req; 1315 struct rsp_que *rsp; 1316 1317 l = l; 1318 vha = fcport->vha; 1319 1320 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e, 1321 "Entered %s.\n", __func__); 1322 1323 req = vha->hw->req_q_map[0]; 1324 rsp = req->rsp; 1325 mcp->mb[0] = MBC_ABORT_TARGET; 1326 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0; 1327 if (HAS_EXTENDED_IDS(vha->hw)) { 1328 mcp->mb[1] = fcport->loop_id; 1329 mcp->mb[10] = 0; 1330 mcp->out_mb |= MBX_10; 1331 } else { 1332 mcp->mb[1] = fcport->loop_id << 8; 1333 } 1334 mcp->mb[2] = vha->hw->loop_reset_delay; 1335 mcp->mb[9] = vha->vp_idx; 1336 1337 mcp->in_mb = MBX_0; 1338 mcp->tov = MBX_TOV_SECONDS; 1339 mcp->flags = 0; 1340 rval = qla2x00_mailbox_command(vha, mcp); 1341 if (rval != QLA_SUCCESS) { 1342 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f, 1343 "Failed=%x.\n", rval); 1344 } 1345 1346 /* Issue marker IOCB. */ 1347 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0, 1348 MK_SYNC_ID); 1349 if (rval2 != QLA_SUCCESS) { 1350 ql_dbg(ql_dbg_mbx, vha, 0x1040, 1351 "Failed to issue marker IOCB (%x).\n", rval2); 1352 } else { 1353 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041, 1354 "Done %s.\n", __func__); 1355 } 1356 1357 return rval; 1358 } 1359 1360 int 1361 qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 1362 { 1363 int rval, rval2; 1364 mbx_cmd_t mc; 1365 mbx_cmd_t *mcp = &mc; 1366 scsi_qla_host_t *vha; 1367 struct req_que *req; 1368 struct rsp_que *rsp; 1369 1370 vha = fcport->vha; 1371 1372 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042, 1373 "Entered %s.\n", __func__); 1374 1375 req = vha->hw->req_q_map[0]; 1376 rsp = req->rsp; 1377 mcp->mb[0] = MBC_LUN_RESET; 1378 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 1379 if (HAS_EXTENDED_IDS(vha->hw)) 1380 mcp->mb[1] = fcport->loop_id; 1381 else 1382 mcp->mb[1] = fcport->loop_id << 8; 1383 mcp->mb[2] = (u32)l; 1384 mcp->mb[3] = 0; 1385 mcp->mb[9] = vha->vp_idx; 1386 1387 mcp->in_mb = MBX_0; 1388 mcp->tov = MBX_TOV_SECONDS; 1389 mcp->flags = 0; 1390 rval = qla2x00_mailbox_command(vha, mcp); 1391 if (rval != QLA_SUCCESS) { 1392 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval); 1393 } 1394 1395 /* Issue marker IOCB. */ 1396 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 1397 MK_SYNC_ID_LUN); 1398 if (rval2 != QLA_SUCCESS) { 1399 ql_dbg(ql_dbg_mbx, vha, 0x1044, 1400 "Failed to issue marker IOCB (%x).\n", rval2); 1401 } else { 1402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045, 1403 "Done %s.\n", __func__); 1404 } 1405 1406 return rval; 1407 } 1408 1409 /* 1410 * qla2x00_get_adapter_id 1411 * Get adapter ID and topology. 1412 * 1413 * Input: 1414 * ha = adapter block pointer. 1415 * id = pointer for loop ID. 1416 * al_pa = pointer for AL_PA. 1417 * area = pointer for area. 1418 * domain = pointer for domain. 1419 * top = pointer for topology. 1420 * TARGET_QUEUE_LOCK must be released. 1421 * ADAPTER_STATE_LOCK must be released. 1422 * 1423 * Returns: 1424 * qla2x00 local function return status code. 1425 * 1426 * Context: 1427 * Kernel context. 1428 */ 1429 int 1430 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa, 1431 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap) 1432 { 1433 int rval; 1434 mbx_cmd_t mc; 1435 mbx_cmd_t *mcp = &mc; 1436 1437 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046, 1438 "Entered %s.\n", __func__); 1439 1440 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID; 1441 mcp->mb[9] = vha->vp_idx; 1442 mcp->out_mb = MBX_9|MBX_0; 1443 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1444 if (IS_CNA_CAPABLE(vha->hw)) 1445 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; 1446 if (IS_FWI2_CAPABLE(vha->hw)) 1447 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16; 1448 if (IS_QLA27XX(vha->hw)) 1449 mcp->in_mb |= MBX_15; 1450 mcp->tov = MBX_TOV_SECONDS; 1451 mcp->flags = 0; 1452 rval = qla2x00_mailbox_command(vha, mcp); 1453 if (mcp->mb[0] == MBS_COMMAND_ERROR) 1454 rval = QLA_COMMAND_ERROR; 1455 else if (mcp->mb[0] == MBS_INVALID_COMMAND) 1456 rval = QLA_INVALID_COMMAND; 1457 1458 /* Return data. */ 1459 *id = mcp->mb[1]; 1460 *al_pa = LSB(mcp->mb[2]); 1461 *area = MSB(mcp->mb[2]); 1462 *domain = LSB(mcp->mb[3]); 1463 *top = mcp->mb[6]; 1464 *sw_cap = mcp->mb[7]; 1465 1466 if (rval != QLA_SUCCESS) { 1467 /*EMPTY*/ 1468 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval); 1469 } else { 1470 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048, 1471 "Done %s.\n", __func__); 1472 1473 if (IS_CNA_CAPABLE(vha->hw)) { 1474 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; 1475 vha->fcoe_fcf_idx = mcp->mb[10]; 1476 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; 1477 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff; 1478 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8; 1479 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff; 1480 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8; 1481 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff; 1482 } 1483 /* If FA-WWN supported */ 1484 if (IS_FAWWN_CAPABLE(vha->hw)) { 1485 if (mcp->mb[7] & BIT_14) { 1486 vha->port_name[0] = MSB(mcp->mb[16]); 1487 vha->port_name[1] = LSB(mcp->mb[16]); 1488 vha->port_name[2] = MSB(mcp->mb[17]); 1489 vha->port_name[3] = LSB(mcp->mb[17]); 1490 vha->port_name[4] = MSB(mcp->mb[18]); 1491 vha->port_name[5] = LSB(mcp->mb[18]); 1492 vha->port_name[6] = MSB(mcp->mb[19]); 1493 vha->port_name[7] = LSB(mcp->mb[19]); 1494 fc_host_port_name(vha->host) = 1495 wwn_to_u64(vha->port_name); 1496 ql_dbg(ql_dbg_mbx, vha, 0x10ca, 1497 "FA-WWN acquired %016llx\n", 1498 wwn_to_u64(vha->port_name)); 1499 } 1500 } 1501 1502 if (IS_QLA27XX(vha->hw)) 1503 vha->bbcr = mcp->mb[15]; 1504 } 1505 1506 return rval; 1507 } 1508 1509 /* 1510 * qla2x00_get_retry_cnt 1511 * Get current firmware login retry count and delay. 1512 * 1513 * Input: 1514 * ha = adapter block pointer. 1515 * retry_cnt = pointer to login retry count. 1516 * tov = pointer to login timeout value. 1517 * 1518 * Returns: 1519 * qla2x00 local function return status code. 1520 * 1521 * Context: 1522 * Kernel context. 1523 */ 1524 int 1525 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov, 1526 uint16_t *r_a_tov) 1527 { 1528 int rval; 1529 uint16_t ratov; 1530 mbx_cmd_t mc; 1531 mbx_cmd_t *mcp = &mc; 1532 1533 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049, 1534 "Entered %s.\n", __func__); 1535 1536 mcp->mb[0] = MBC_GET_RETRY_COUNT; 1537 mcp->out_mb = MBX_0; 1538 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1539 mcp->tov = MBX_TOV_SECONDS; 1540 mcp->flags = 0; 1541 rval = qla2x00_mailbox_command(vha, mcp); 1542 1543 if (rval != QLA_SUCCESS) { 1544 /*EMPTY*/ 1545 ql_dbg(ql_dbg_mbx, vha, 0x104a, 1546 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 1547 } else { 1548 /* Convert returned data and check our values. */ 1549 *r_a_tov = mcp->mb[3] / 2; 1550 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */ 1551 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) { 1552 /* Update to the larger values */ 1553 *retry_cnt = (uint8_t)mcp->mb[1]; 1554 *tov = ratov; 1555 } 1556 1557 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b, 1558 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov); 1559 } 1560 1561 return rval; 1562 } 1563 1564 /* 1565 * qla2x00_init_firmware 1566 * Initialize adapter firmware. 1567 * 1568 * Input: 1569 * ha = adapter block pointer. 1570 * dptr = Initialization control block pointer. 1571 * size = size of initialization control block. 1572 * TARGET_QUEUE_LOCK must be released. 1573 * ADAPTER_STATE_LOCK must be released. 1574 * 1575 * Returns: 1576 * qla2x00 local function return status code. 1577 * 1578 * Context: 1579 * Kernel context. 1580 */ 1581 int 1582 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size) 1583 { 1584 int rval; 1585 mbx_cmd_t mc; 1586 mbx_cmd_t *mcp = &mc; 1587 struct qla_hw_data *ha = vha->hw; 1588 1589 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c, 1590 "Entered %s.\n", __func__); 1591 1592 if (IS_P3P_TYPE(ha) && ql2xdbwr) 1593 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr, 1594 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16))); 1595 1596 if (ha->flags.npiv_supported) 1597 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE; 1598 else 1599 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; 1600 1601 mcp->mb[1] = 0; 1602 mcp->mb[2] = MSW(ha->init_cb_dma); 1603 mcp->mb[3] = LSW(ha->init_cb_dma); 1604 mcp->mb[6] = MSW(MSD(ha->init_cb_dma)); 1605 mcp->mb[7] = LSW(MSD(ha->init_cb_dma)); 1606 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1607 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) { 1608 mcp->mb[1] = BIT_0; 1609 mcp->mb[10] = MSW(ha->ex_init_cb_dma); 1610 mcp->mb[11] = LSW(ha->ex_init_cb_dma); 1611 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma)); 1612 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma)); 1613 mcp->mb[14] = sizeof(*ha->ex_init_cb); 1614 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10; 1615 } 1616 /* 1 and 2 should normally be captured. */ 1617 mcp->in_mb = MBX_2|MBX_1|MBX_0; 1618 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 1619 /* mb3 is additional info about the installed SFP. */ 1620 mcp->in_mb |= MBX_3; 1621 mcp->buf_size = size; 1622 mcp->flags = MBX_DMA_OUT; 1623 mcp->tov = MBX_TOV_SECONDS; 1624 rval = qla2x00_mailbox_command(vha, mcp); 1625 1626 if (rval != QLA_SUCCESS) { 1627 /*EMPTY*/ 1628 ql_dbg(ql_dbg_mbx, vha, 0x104d, 1629 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n", 1630 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]); 1631 } else { 1632 /*EMPTY*/ 1633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e, 1634 "Done %s.\n", __func__); 1635 } 1636 1637 return rval; 1638 } 1639 1640 1641 /* 1642 * qla2x00_get_port_database 1643 * Issue normal/enhanced get port database mailbox command 1644 * and copy device name as necessary. 1645 * 1646 * Input: 1647 * ha = adapter state pointer. 1648 * dev = structure pointer. 1649 * opt = enhanced cmd option byte. 1650 * 1651 * Returns: 1652 * qla2x00 local function return status code. 1653 * 1654 * Context: 1655 * Kernel context. 1656 */ 1657 int 1658 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt) 1659 { 1660 int rval; 1661 mbx_cmd_t mc; 1662 mbx_cmd_t *mcp = &mc; 1663 port_database_t *pd; 1664 struct port_database_24xx *pd24; 1665 dma_addr_t pd_dma; 1666 struct qla_hw_data *ha = vha->hw; 1667 1668 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f, 1669 "Entered %s.\n", __func__); 1670 1671 pd24 = NULL; 1672 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1673 if (pd == NULL) { 1674 ql_log(ql_log_warn, vha, 0x1050, 1675 "Failed to allocate port database structure.\n"); 1676 return QLA_MEMORY_ALLOC_FAILED; 1677 } 1678 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE)); 1679 1680 mcp->mb[0] = MBC_GET_PORT_DATABASE; 1681 if (opt != 0 && !IS_FWI2_CAPABLE(ha)) 1682 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE; 1683 mcp->mb[2] = MSW(pd_dma); 1684 mcp->mb[3] = LSW(pd_dma); 1685 mcp->mb[6] = MSW(MSD(pd_dma)); 1686 mcp->mb[7] = LSW(MSD(pd_dma)); 1687 mcp->mb[9] = vha->vp_idx; 1688 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 1689 mcp->in_mb = MBX_0; 1690 if (IS_FWI2_CAPABLE(ha)) { 1691 mcp->mb[1] = fcport->loop_id; 1692 mcp->mb[10] = opt; 1693 mcp->out_mb |= MBX_10|MBX_1; 1694 mcp->in_mb |= MBX_1; 1695 } else if (HAS_EXTENDED_IDS(ha)) { 1696 mcp->mb[1] = fcport->loop_id; 1697 mcp->mb[10] = opt; 1698 mcp->out_mb |= MBX_10|MBX_1; 1699 } else { 1700 mcp->mb[1] = fcport->loop_id << 8 | opt; 1701 mcp->out_mb |= MBX_1; 1702 } 1703 mcp->buf_size = IS_FWI2_CAPABLE(ha) ? 1704 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE; 1705 mcp->flags = MBX_DMA_IN; 1706 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1707 rval = qla2x00_mailbox_command(vha, mcp); 1708 if (rval != QLA_SUCCESS) 1709 goto gpd_error_out; 1710 1711 if (IS_FWI2_CAPABLE(ha)) { 1712 uint64_t zero = 0; 1713 pd24 = (struct port_database_24xx *) pd; 1714 1715 /* Check for logged in state. */ 1716 if (pd24->current_login_state != PDS_PRLI_COMPLETE && 1717 pd24->last_login_state != PDS_PRLI_COMPLETE) { 1718 ql_dbg(ql_dbg_mbx, vha, 0x1051, 1719 "Unable to verify login-state (%x/%x) for " 1720 "loop_id %x.\n", pd24->current_login_state, 1721 pd24->last_login_state, fcport->loop_id); 1722 rval = QLA_FUNCTION_FAILED; 1723 goto gpd_error_out; 1724 } 1725 1726 if (fcport->loop_id == FC_NO_LOOP_ID || 1727 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1728 memcmp(fcport->port_name, pd24->port_name, 8))) { 1729 /* We lost the device mid way. */ 1730 rval = QLA_NOT_LOGGED_IN; 1731 goto gpd_error_out; 1732 } 1733 1734 /* Names are little-endian. */ 1735 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE); 1736 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE); 1737 1738 /* Get port_id of device. */ 1739 fcport->d_id.b.domain = pd24->port_id[0]; 1740 fcport->d_id.b.area = pd24->port_id[1]; 1741 fcport->d_id.b.al_pa = pd24->port_id[2]; 1742 fcport->d_id.b.rsvd_1 = 0; 1743 1744 /* If not target must be initiator or unknown type. */ 1745 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0) 1746 fcport->port_type = FCT_INITIATOR; 1747 else 1748 fcport->port_type = FCT_TARGET; 1749 1750 /* Passback COS information. */ 1751 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ? 1752 FC_COS_CLASS2 : FC_COS_CLASS3; 1753 1754 if (pd24->prli_svc_param_word_3[0] & BIT_7) 1755 fcport->flags |= FCF_CONF_COMP_SUPPORTED; 1756 } else { 1757 uint64_t zero = 0; 1758 1759 /* Check for logged in state. */ 1760 if (pd->master_state != PD_STATE_PORT_LOGGED_IN && 1761 pd->slave_state != PD_STATE_PORT_LOGGED_IN) { 1762 ql_dbg(ql_dbg_mbx, vha, 0x100a, 1763 "Unable to verify login-state (%x/%x) - " 1764 "portid=%02x%02x%02x.\n", pd->master_state, 1765 pd->slave_state, fcport->d_id.b.domain, 1766 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1767 rval = QLA_FUNCTION_FAILED; 1768 goto gpd_error_out; 1769 } 1770 1771 if (fcport->loop_id == FC_NO_LOOP_ID || 1772 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1773 memcmp(fcport->port_name, pd->port_name, 8))) { 1774 /* We lost the device mid way. */ 1775 rval = QLA_NOT_LOGGED_IN; 1776 goto gpd_error_out; 1777 } 1778 1779 /* Names are little-endian. */ 1780 memcpy(fcport->node_name, pd->node_name, WWN_SIZE); 1781 memcpy(fcport->port_name, pd->port_name, WWN_SIZE); 1782 1783 /* Get port_id of device. */ 1784 fcport->d_id.b.domain = pd->port_id[0]; 1785 fcport->d_id.b.area = pd->port_id[3]; 1786 fcport->d_id.b.al_pa = pd->port_id[2]; 1787 fcport->d_id.b.rsvd_1 = 0; 1788 1789 /* If not target must be initiator or unknown type. */ 1790 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 1791 fcport->port_type = FCT_INITIATOR; 1792 else 1793 fcport->port_type = FCT_TARGET; 1794 1795 /* Passback COS information. */ 1796 fcport->supported_classes = (pd->options & BIT_4) ? 1797 FC_COS_CLASS2: FC_COS_CLASS3; 1798 } 1799 1800 gpd_error_out: 1801 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1802 1803 if (rval != QLA_SUCCESS) { 1804 ql_dbg(ql_dbg_mbx, vha, 0x1052, 1805 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval, 1806 mcp->mb[0], mcp->mb[1]); 1807 } else { 1808 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053, 1809 "Done %s.\n", __func__); 1810 } 1811 1812 return rval; 1813 } 1814 1815 /* 1816 * qla2x00_get_firmware_state 1817 * Get adapter firmware state. 1818 * 1819 * Input: 1820 * ha = adapter block pointer. 1821 * dptr = pointer for firmware state. 1822 * TARGET_QUEUE_LOCK must be released. 1823 * ADAPTER_STATE_LOCK must be released. 1824 * 1825 * Returns: 1826 * qla2x00 local function return status code. 1827 * 1828 * Context: 1829 * Kernel context. 1830 */ 1831 int 1832 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states) 1833 { 1834 int rval; 1835 mbx_cmd_t mc; 1836 mbx_cmd_t *mcp = &mc; 1837 1838 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054, 1839 "Entered %s.\n", __func__); 1840 1841 mcp->mb[0] = MBC_GET_FIRMWARE_STATE; 1842 mcp->out_mb = MBX_0; 1843 if (IS_FWI2_CAPABLE(vha->hw)) 1844 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1845 else 1846 mcp->in_mb = MBX_1|MBX_0; 1847 mcp->tov = MBX_TOV_SECONDS; 1848 mcp->flags = 0; 1849 rval = qla2x00_mailbox_command(vha, mcp); 1850 1851 /* Return firmware states. */ 1852 states[0] = mcp->mb[1]; 1853 if (IS_FWI2_CAPABLE(vha->hw)) { 1854 states[1] = mcp->mb[2]; 1855 states[2] = mcp->mb[3]; /* SFP info */ 1856 states[3] = mcp->mb[4]; 1857 states[4] = mcp->mb[5]; 1858 states[5] = mcp->mb[6]; /* DPORT status */ 1859 } 1860 1861 if (rval != QLA_SUCCESS) { 1862 /*EMPTY*/ 1863 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval); 1864 } else { 1865 /*EMPTY*/ 1866 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056, 1867 "Done %s.\n", __func__); 1868 } 1869 1870 return rval; 1871 } 1872 1873 /* 1874 * qla2x00_get_port_name 1875 * Issue get port name mailbox command. 1876 * Returned name is in big endian format. 1877 * 1878 * Input: 1879 * ha = adapter block pointer. 1880 * loop_id = loop ID of device. 1881 * name = pointer for name. 1882 * TARGET_QUEUE_LOCK must be released. 1883 * ADAPTER_STATE_LOCK must be released. 1884 * 1885 * Returns: 1886 * qla2x00 local function return status code. 1887 * 1888 * Context: 1889 * Kernel context. 1890 */ 1891 int 1892 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name, 1893 uint8_t opt) 1894 { 1895 int rval; 1896 mbx_cmd_t mc; 1897 mbx_cmd_t *mcp = &mc; 1898 1899 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057, 1900 "Entered %s.\n", __func__); 1901 1902 mcp->mb[0] = MBC_GET_PORT_NAME; 1903 mcp->mb[9] = vha->vp_idx; 1904 mcp->out_mb = MBX_9|MBX_1|MBX_0; 1905 if (HAS_EXTENDED_IDS(vha->hw)) { 1906 mcp->mb[1] = loop_id; 1907 mcp->mb[10] = opt; 1908 mcp->out_mb |= MBX_10; 1909 } else { 1910 mcp->mb[1] = loop_id << 8 | opt; 1911 } 1912 1913 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1914 mcp->tov = MBX_TOV_SECONDS; 1915 mcp->flags = 0; 1916 rval = qla2x00_mailbox_command(vha, mcp); 1917 1918 if (rval != QLA_SUCCESS) { 1919 /*EMPTY*/ 1920 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval); 1921 } else { 1922 if (name != NULL) { 1923 /* This function returns name in big endian. */ 1924 name[0] = MSB(mcp->mb[2]); 1925 name[1] = LSB(mcp->mb[2]); 1926 name[2] = MSB(mcp->mb[3]); 1927 name[3] = LSB(mcp->mb[3]); 1928 name[4] = MSB(mcp->mb[6]); 1929 name[5] = LSB(mcp->mb[6]); 1930 name[6] = MSB(mcp->mb[7]); 1931 name[7] = LSB(mcp->mb[7]); 1932 } 1933 1934 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059, 1935 "Done %s.\n", __func__); 1936 } 1937 1938 return rval; 1939 } 1940 1941 /* 1942 * qla24xx_link_initialization 1943 * Issue link initialization mailbox command. 1944 * 1945 * Input: 1946 * ha = adapter block pointer. 1947 * TARGET_QUEUE_LOCK must be released. 1948 * ADAPTER_STATE_LOCK must be released. 1949 * 1950 * Returns: 1951 * qla2x00 local function return status code. 1952 * 1953 * Context: 1954 * Kernel context. 1955 */ 1956 int 1957 qla24xx_link_initialize(scsi_qla_host_t *vha) 1958 { 1959 int rval; 1960 mbx_cmd_t mc; 1961 mbx_cmd_t *mcp = &mc; 1962 1963 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152, 1964 "Entered %s.\n", __func__); 1965 1966 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw)) 1967 return QLA_FUNCTION_FAILED; 1968 1969 mcp->mb[0] = MBC_LINK_INITIALIZATION; 1970 mcp->mb[1] = BIT_4; 1971 if (vha->hw->operating_mode == LOOP) 1972 mcp->mb[1] |= BIT_6; 1973 else 1974 mcp->mb[1] |= BIT_5; 1975 mcp->mb[2] = 0; 1976 mcp->mb[3] = 0; 1977 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1978 mcp->in_mb = MBX_0; 1979 mcp->tov = MBX_TOV_SECONDS; 1980 mcp->flags = 0; 1981 rval = qla2x00_mailbox_command(vha, mcp); 1982 1983 if (rval != QLA_SUCCESS) { 1984 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval); 1985 } else { 1986 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154, 1987 "Done %s.\n", __func__); 1988 } 1989 1990 return rval; 1991 } 1992 1993 /* 1994 * qla2x00_lip_reset 1995 * Issue LIP reset mailbox command. 1996 * 1997 * Input: 1998 * ha = adapter block pointer. 1999 * TARGET_QUEUE_LOCK must be released. 2000 * ADAPTER_STATE_LOCK must be released. 2001 * 2002 * Returns: 2003 * qla2x00 local function return status code. 2004 * 2005 * Context: 2006 * Kernel context. 2007 */ 2008 int 2009 qla2x00_lip_reset(scsi_qla_host_t *vha) 2010 { 2011 int rval; 2012 mbx_cmd_t mc; 2013 mbx_cmd_t *mcp = &mc; 2014 2015 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a, 2016 "Entered %s.\n", __func__); 2017 2018 if (IS_CNA_CAPABLE(vha->hw)) { 2019 /* Logout across all FCFs. */ 2020 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2021 mcp->mb[1] = BIT_1; 2022 mcp->mb[2] = 0; 2023 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2024 } else if (IS_FWI2_CAPABLE(vha->hw)) { 2025 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2026 mcp->mb[1] = BIT_6; 2027 mcp->mb[2] = 0; 2028 mcp->mb[3] = vha->hw->loop_reset_delay; 2029 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2030 } else { 2031 mcp->mb[0] = MBC_LIP_RESET; 2032 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2033 if (HAS_EXTENDED_IDS(vha->hw)) { 2034 mcp->mb[1] = 0x00ff; 2035 mcp->mb[10] = 0; 2036 mcp->out_mb |= MBX_10; 2037 } else { 2038 mcp->mb[1] = 0xff00; 2039 } 2040 mcp->mb[2] = vha->hw->loop_reset_delay; 2041 mcp->mb[3] = 0; 2042 } 2043 mcp->in_mb = MBX_0; 2044 mcp->tov = MBX_TOV_SECONDS; 2045 mcp->flags = 0; 2046 rval = qla2x00_mailbox_command(vha, mcp); 2047 2048 if (rval != QLA_SUCCESS) { 2049 /*EMPTY*/ 2050 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval); 2051 } else { 2052 /*EMPTY*/ 2053 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c, 2054 "Done %s.\n", __func__); 2055 } 2056 2057 return rval; 2058 } 2059 2060 /* 2061 * qla2x00_send_sns 2062 * Send SNS command. 2063 * 2064 * Input: 2065 * ha = adapter block pointer. 2066 * sns = pointer for command. 2067 * cmd_size = command size. 2068 * buf_size = response/command size. 2069 * TARGET_QUEUE_LOCK must be released. 2070 * ADAPTER_STATE_LOCK must be released. 2071 * 2072 * Returns: 2073 * qla2x00 local function return status code. 2074 * 2075 * Context: 2076 * Kernel context. 2077 */ 2078 int 2079 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address, 2080 uint16_t cmd_size, size_t buf_size) 2081 { 2082 int rval; 2083 mbx_cmd_t mc; 2084 mbx_cmd_t *mcp = &mc; 2085 2086 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d, 2087 "Entered %s.\n", __func__); 2088 2089 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e, 2090 "Retry cnt=%d ratov=%d total tov=%d.\n", 2091 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov); 2092 2093 mcp->mb[0] = MBC_SEND_SNS_COMMAND; 2094 mcp->mb[1] = cmd_size; 2095 mcp->mb[2] = MSW(sns_phys_address); 2096 mcp->mb[3] = LSW(sns_phys_address); 2097 mcp->mb[6] = MSW(MSD(sns_phys_address)); 2098 mcp->mb[7] = LSW(MSD(sns_phys_address)); 2099 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2100 mcp->in_mb = MBX_0|MBX_1; 2101 mcp->buf_size = buf_size; 2102 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN; 2103 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2); 2104 rval = qla2x00_mailbox_command(vha, mcp); 2105 2106 if (rval != QLA_SUCCESS) { 2107 /*EMPTY*/ 2108 ql_dbg(ql_dbg_mbx, vha, 0x105f, 2109 "Failed=%x mb[0]=%x mb[1]=%x.\n", 2110 rval, mcp->mb[0], mcp->mb[1]); 2111 } else { 2112 /*EMPTY*/ 2113 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060, 2114 "Done %s.\n", __func__); 2115 } 2116 2117 return rval; 2118 } 2119 2120 int 2121 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2122 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 2123 { 2124 int rval; 2125 2126 struct logio_entry_24xx *lg; 2127 dma_addr_t lg_dma; 2128 uint32_t iop[2]; 2129 struct qla_hw_data *ha = vha->hw; 2130 struct req_que *req; 2131 2132 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061, 2133 "Entered %s.\n", __func__); 2134 2135 if (vha->vp_idx && vha->qpair) 2136 req = vha->qpair->req; 2137 else 2138 req = ha->req_q_map[0]; 2139 2140 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2141 if (lg == NULL) { 2142 ql_log(ql_log_warn, vha, 0x1062, 2143 "Failed to allocate login IOCB.\n"); 2144 return QLA_MEMORY_ALLOC_FAILED; 2145 } 2146 memset(lg, 0, sizeof(struct logio_entry_24xx)); 2147 2148 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2149 lg->entry_count = 1; 2150 lg->handle = MAKE_HANDLE(req->id, lg->handle); 2151 lg->nport_handle = cpu_to_le16(loop_id); 2152 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI); 2153 if (opt & BIT_0) 2154 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI); 2155 if (opt & BIT_1) 2156 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI); 2157 lg->port_id[0] = al_pa; 2158 lg->port_id[1] = area; 2159 lg->port_id[2] = domain; 2160 lg->vp_index = vha->vp_idx; 2161 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2162 (ha->r_a_tov / 10 * 2) + 2); 2163 if (rval != QLA_SUCCESS) { 2164 ql_dbg(ql_dbg_mbx, vha, 0x1063, 2165 "Failed to issue login IOCB (%x).\n", rval); 2166 } else if (lg->entry_status != 0) { 2167 ql_dbg(ql_dbg_mbx, vha, 0x1064, 2168 "Failed to complete IOCB -- error status (%x).\n", 2169 lg->entry_status); 2170 rval = QLA_FUNCTION_FAILED; 2171 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 2172 iop[0] = le32_to_cpu(lg->io_parameter[0]); 2173 iop[1] = le32_to_cpu(lg->io_parameter[1]); 2174 2175 ql_dbg(ql_dbg_mbx, vha, 0x1065, 2176 "Failed to complete IOCB -- completion status (%x) " 2177 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2178 iop[0], iop[1]); 2179 2180 switch (iop[0]) { 2181 case LSC_SCODE_PORTID_USED: 2182 mb[0] = MBS_PORT_ID_USED; 2183 mb[1] = LSW(iop[1]); 2184 break; 2185 case LSC_SCODE_NPORT_USED: 2186 mb[0] = MBS_LOOP_ID_USED; 2187 break; 2188 case LSC_SCODE_NOLINK: 2189 case LSC_SCODE_NOIOCB: 2190 case LSC_SCODE_NOXCB: 2191 case LSC_SCODE_CMD_FAILED: 2192 case LSC_SCODE_NOFABRIC: 2193 case LSC_SCODE_FW_NOT_READY: 2194 case LSC_SCODE_NOT_LOGGED_IN: 2195 case LSC_SCODE_NOPCB: 2196 case LSC_SCODE_ELS_REJECT: 2197 case LSC_SCODE_CMD_PARAM_ERR: 2198 case LSC_SCODE_NONPORT: 2199 case LSC_SCODE_LOGGED_IN: 2200 case LSC_SCODE_NOFLOGI_ACC: 2201 default: 2202 mb[0] = MBS_COMMAND_ERROR; 2203 break; 2204 } 2205 } else { 2206 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066, 2207 "Done %s.\n", __func__); 2208 2209 iop[0] = le32_to_cpu(lg->io_parameter[0]); 2210 2211 mb[0] = MBS_COMMAND_COMPLETE; 2212 mb[1] = 0; 2213 if (iop[0] & BIT_4) { 2214 if (iop[0] & BIT_8) 2215 mb[1] |= BIT_1; 2216 } else 2217 mb[1] = BIT_0; 2218 2219 /* Passback COS information. */ 2220 mb[10] = 0; 2221 if (lg->io_parameter[7] || lg->io_parameter[8]) 2222 mb[10] |= BIT_0; /* Class 2. */ 2223 if (lg->io_parameter[9] || lg->io_parameter[10]) 2224 mb[10] |= BIT_1; /* Class 3. */ 2225 if (lg->io_parameter[0] & cpu_to_le32(BIT_7)) 2226 mb[10] |= BIT_7; /* Confirmed Completion 2227 * Allowed 2228 */ 2229 } 2230 2231 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2232 2233 return rval; 2234 } 2235 2236 /* 2237 * qla2x00_login_fabric 2238 * Issue login fabric port mailbox command. 2239 * 2240 * Input: 2241 * ha = adapter block pointer. 2242 * loop_id = device loop ID. 2243 * domain = device domain. 2244 * area = device area. 2245 * al_pa = device AL_PA. 2246 * status = pointer for return status. 2247 * opt = command options. 2248 * TARGET_QUEUE_LOCK must be released. 2249 * ADAPTER_STATE_LOCK must be released. 2250 * 2251 * Returns: 2252 * qla2x00 local function return status code. 2253 * 2254 * Context: 2255 * Kernel context. 2256 */ 2257 int 2258 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2259 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 2260 { 2261 int rval; 2262 mbx_cmd_t mc; 2263 mbx_cmd_t *mcp = &mc; 2264 struct qla_hw_data *ha = vha->hw; 2265 2266 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067, 2267 "Entered %s.\n", __func__); 2268 2269 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT; 2270 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2271 if (HAS_EXTENDED_IDS(ha)) { 2272 mcp->mb[1] = loop_id; 2273 mcp->mb[10] = opt; 2274 mcp->out_mb |= MBX_10; 2275 } else { 2276 mcp->mb[1] = (loop_id << 8) | opt; 2277 } 2278 mcp->mb[2] = domain; 2279 mcp->mb[3] = area << 8 | al_pa; 2280 2281 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0; 2282 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2283 mcp->flags = 0; 2284 rval = qla2x00_mailbox_command(vha, mcp); 2285 2286 /* Return mailbox statuses. */ 2287 if (mb != NULL) { 2288 mb[0] = mcp->mb[0]; 2289 mb[1] = mcp->mb[1]; 2290 mb[2] = mcp->mb[2]; 2291 mb[6] = mcp->mb[6]; 2292 mb[7] = mcp->mb[7]; 2293 /* COS retrieved from Get-Port-Database mailbox command. */ 2294 mb[10] = 0; 2295 } 2296 2297 if (rval != QLA_SUCCESS) { 2298 /* RLU tmp code: need to change main mailbox_command function to 2299 * return ok even when the mailbox completion value is not 2300 * SUCCESS. The caller needs to be responsible to interpret 2301 * the return values of this mailbox command if we're not 2302 * to change too much of the existing code. 2303 */ 2304 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 || 2305 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 || 2306 mcp->mb[0] == 0x4006) 2307 rval = QLA_SUCCESS; 2308 2309 /*EMPTY*/ 2310 ql_dbg(ql_dbg_mbx, vha, 0x1068, 2311 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 2312 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 2313 } else { 2314 /*EMPTY*/ 2315 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069, 2316 "Done %s.\n", __func__); 2317 } 2318 2319 return rval; 2320 } 2321 2322 /* 2323 * qla2x00_login_local_device 2324 * Issue login loop port mailbox command. 2325 * 2326 * Input: 2327 * ha = adapter block pointer. 2328 * loop_id = device loop ID. 2329 * opt = command options. 2330 * 2331 * Returns: 2332 * Return status code. 2333 * 2334 * Context: 2335 * Kernel context. 2336 * 2337 */ 2338 int 2339 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport, 2340 uint16_t *mb_ret, uint8_t opt) 2341 { 2342 int rval; 2343 mbx_cmd_t mc; 2344 mbx_cmd_t *mcp = &mc; 2345 struct qla_hw_data *ha = vha->hw; 2346 2347 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a, 2348 "Entered %s.\n", __func__); 2349 2350 if (IS_FWI2_CAPABLE(ha)) 2351 return qla24xx_login_fabric(vha, fcport->loop_id, 2352 fcport->d_id.b.domain, fcport->d_id.b.area, 2353 fcport->d_id.b.al_pa, mb_ret, opt); 2354 2355 mcp->mb[0] = MBC_LOGIN_LOOP_PORT; 2356 if (HAS_EXTENDED_IDS(ha)) 2357 mcp->mb[1] = fcport->loop_id; 2358 else 2359 mcp->mb[1] = fcport->loop_id << 8; 2360 mcp->mb[2] = opt; 2361 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2362 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0; 2363 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2364 mcp->flags = 0; 2365 rval = qla2x00_mailbox_command(vha, mcp); 2366 2367 /* Return mailbox statuses. */ 2368 if (mb_ret != NULL) { 2369 mb_ret[0] = mcp->mb[0]; 2370 mb_ret[1] = mcp->mb[1]; 2371 mb_ret[6] = mcp->mb[6]; 2372 mb_ret[7] = mcp->mb[7]; 2373 } 2374 2375 if (rval != QLA_SUCCESS) { 2376 /* AV tmp code: need to change main mailbox_command function to 2377 * return ok even when the mailbox completion value is not 2378 * SUCCESS. The caller needs to be responsible to interpret 2379 * the return values of this mailbox command if we're not 2380 * to change too much of the existing code. 2381 */ 2382 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006) 2383 rval = QLA_SUCCESS; 2384 2385 ql_dbg(ql_dbg_mbx, vha, 0x106b, 2386 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n", 2387 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]); 2388 } else { 2389 /*EMPTY*/ 2390 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c, 2391 "Done %s.\n", __func__); 2392 } 2393 2394 return (rval); 2395 } 2396 2397 int 2398 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2399 uint8_t area, uint8_t al_pa) 2400 { 2401 int rval; 2402 struct logio_entry_24xx *lg; 2403 dma_addr_t lg_dma; 2404 struct qla_hw_data *ha = vha->hw; 2405 struct req_que *req; 2406 2407 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d, 2408 "Entered %s.\n", __func__); 2409 2410 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2411 if (lg == NULL) { 2412 ql_log(ql_log_warn, vha, 0x106e, 2413 "Failed to allocate logout IOCB.\n"); 2414 return QLA_MEMORY_ALLOC_FAILED; 2415 } 2416 memset(lg, 0, sizeof(struct logio_entry_24xx)); 2417 2418 req = vha->req; 2419 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2420 lg->entry_count = 1; 2421 lg->handle = MAKE_HANDLE(req->id, lg->handle); 2422 lg->nport_handle = cpu_to_le16(loop_id); 2423 lg->control_flags = 2424 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO| 2425 LCF_FREE_NPORT); 2426 lg->port_id[0] = al_pa; 2427 lg->port_id[1] = area; 2428 lg->port_id[2] = domain; 2429 lg->vp_index = vha->vp_idx; 2430 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2431 (ha->r_a_tov / 10 * 2) + 2); 2432 if (rval != QLA_SUCCESS) { 2433 ql_dbg(ql_dbg_mbx, vha, 0x106f, 2434 "Failed to issue logout IOCB (%x).\n", rval); 2435 } else if (lg->entry_status != 0) { 2436 ql_dbg(ql_dbg_mbx, vha, 0x1070, 2437 "Failed to complete IOCB -- error status (%x).\n", 2438 lg->entry_status); 2439 rval = QLA_FUNCTION_FAILED; 2440 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 2441 ql_dbg(ql_dbg_mbx, vha, 0x1071, 2442 "Failed to complete IOCB -- completion status (%x) " 2443 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2444 le32_to_cpu(lg->io_parameter[0]), 2445 le32_to_cpu(lg->io_parameter[1])); 2446 } else { 2447 /*EMPTY*/ 2448 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072, 2449 "Done %s.\n", __func__); 2450 } 2451 2452 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2453 2454 return rval; 2455 } 2456 2457 /* 2458 * qla2x00_fabric_logout 2459 * Issue logout fabric port mailbox command. 2460 * 2461 * Input: 2462 * ha = adapter block pointer. 2463 * loop_id = device loop ID. 2464 * TARGET_QUEUE_LOCK must be released. 2465 * ADAPTER_STATE_LOCK must be released. 2466 * 2467 * Returns: 2468 * qla2x00 local function return status code. 2469 * 2470 * Context: 2471 * Kernel context. 2472 */ 2473 int 2474 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2475 uint8_t area, uint8_t al_pa) 2476 { 2477 int rval; 2478 mbx_cmd_t mc; 2479 mbx_cmd_t *mcp = &mc; 2480 2481 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073, 2482 "Entered %s.\n", __func__); 2483 2484 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT; 2485 mcp->out_mb = MBX_1|MBX_0; 2486 if (HAS_EXTENDED_IDS(vha->hw)) { 2487 mcp->mb[1] = loop_id; 2488 mcp->mb[10] = 0; 2489 mcp->out_mb |= MBX_10; 2490 } else { 2491 mcp->mb[1] = loop_id << 8; 2492 } 2493 2494 mcp->in_mb = MBX_1|MBX_0; 2495 mcp->tov = MBX_TOV_SECONDS; 2496 mcp->flags = 0; 2497 rval = qla2x00_mailbox_command(vha, mcp); 2498 2499 if (rval != QLA_SUCCESS) { 2500 /*EMPTY*/ 2501 ql_dbg(ql_dbg_mbx, vha, 0x1074, 2502 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]); 2503 } else { 2504 /*EMPTY*/ 2505 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075, 2506 "Done %s.\n", __func__); 2507 } 2508 2509 return rval; 2510 } 2511 2512 /* 2513 * qla2x00_full_login_lip 2514 * Issue full login LIP mailbox command. 2515 * 2516 * Input: 2517 * ha = adapter block pointer. 2518 * TARGET_QUEUE_LOCK must be released. 2519 * ADAPTER_STATE_LOCK must be released. 2520 * 2521 * Returns: 2522 * qla2x00 local function return status code. 2523 * 2524 * Context: 2525 * Kernel context. 2526 */ 2527 int 2528 qla2x00_full_login_lip(scsi_qla_host_t *vha) 2529 { 2530 int rval; 2531 mbx_cmd_t mc; 2532 mbx_cmd_t *mcp = &mc; 2533 2534 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076, 2535 "Entered %s.\n", __func__); 2536 2537 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2538 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0; 2539 mcp->mb[2] = 0; 2540 mcp->mb[3] = 0; 2541 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2542 mcp->in_mb = MBX_0; 2543 mcp->tov = MBX_TOV_SECONDS; 2544 mcp->flags = 0; 2545 rval = qla2x00_mailbox_command(vha, mcp); 2546 2547 if (rval != QLA_SUCCESS) { 2548 /*EMPTY*/ 2549 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval); 2550 } else { 2551 /*EMPTY*/ 2552 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078, 2553 "Done %s.\n", __func__); 2554 } 2555 2556 return rval; 2557 } 2558 2559 /* 2560 * qla2x00_get_id_list 2561 * 2562 * Input: 2563 * ha = adapter block pointer. 2564 * 2565 * Returns: 2566 * qla2x00 local function return status code. 2567 * 2568 * Context: 2569 * Kernel context. 2570 */ 2571 int 2572 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma, 2573 uint16_t *entries) 2574 { 2575 int rval; 2576 mbx_cmd_t mc; 2577 mbx_cmd_t *mcp = &mc; 2578 2579 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079, 2580 "Entered %s.\n", __func__); 2581 2582 if (id_list == NULL) 2583 return QLA_FUNCTION_FAILED; 2584 2585 mcp->mb[0] = MBC_GET_ID_LIST; 2586 mcp->out_mb = MBX_0; 2587 if (IS_FWI2_CAPABLE(vha->hw)) { 2588 mcp->mb[2] = MSW(id_list_dma); 2589 mcp->mb[3] = LSW(id_list_dma); 2590 mcp->mb[6] = MSW(MSD(id_list_dma)); 2591 mcp->mb[7] = LSW(MSD(id_list_dma)); 2592 mcp->mb[8] = 0; 2593 mcp->mb[9] = vha->vp_idx; 2594 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2; 2595 } else { 2596 mcp->mb[1] = MSW(id_list_dma); 2597 mcp->mb[2] = LSW(id_list_dma); 2598 mcp->mb[3] = MSW(MSD(id_list_dma)); 2599 mcp->mb[6] = LSW(MSD(id_list_dma)); 2600 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1; 2601 } 2602 mcp->in_mb = MBX_1|MBX_0; 2603 mcp->tov = MBX_TOV_SECONDS; 2604 mcp->flags = 0; 2605 rval = qla2x00_mailbox_command(vha, mcp); 2606 2607 if (rval != QLA_SUCCESS) { 2608 /*EMPTY*/ 2609 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval); 2610 } else { 2611 *entries = mcp->mb[1]; 2612 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b, 2613 "Done %s.\n", __func__); 2614 } 2615 2616 return rval; 2617 } 2618 2619 /* 2620 * qla2x00_get_resource_cnts 2621 * Get current firmware resource counts. 2622 * 2623 * Input: 2624 * ha = adapter block pointer. 2625 * 2626 * Returns: 2627 * qla2x00 local function return status code. 2628 * 2629 * Context: 2630 * Kernel context. 2631 */ 2632 int 2633 qla2x00_get_resource_cnts(scsi_qla_host_t *vha) 2634 { 2635 struct qla_hw_data *ha = vha->hw; 2636 int rval; 2637 mbx_cmd_t mc; 2638 mbx_cmd_t *mcp = &mc; 2639 2640 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c, 2641 "Entered %s.\n", __func__); 2642 2643 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS; 2644 mcp->out_mb = MBX_0; 2645 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2646 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw)) 2647 mcp->in_mb |= MBX_12; 2648 mcp->tov = MBX_TOV_SECONDS; 2649 mcp->flags = 0; 2650 rval = qla2x00_mailbox_command(vha, mcp); 2651 2652 if (rval != QLA_SUCCESS) { 2653 /*EMPTY*/ 2654 ql_dbg(ql_dbg_mbx, vha, 0x107d, 2655 "Failed mb[0]=%x.\n", mcp->mb[0]); 2656 } else { 2657 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e, 2658 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x " 2659 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2], 2660 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10], 2661 mcp->mb[11], mcp->mb[12]); 2662 2663 ha->orig_fw_tgt_xcb_count = mcp->mb[1]; 2664 ha->cur_fw_tgt_xcb_count = mcp->mb[2]; 2665 ha->cur_fw_xcb_count = mcp->mb[3]; 2666 ha->orig_fw_xcb_count = mcp->mb[6]; 2667 ha->cur_fw_iocb_count = mcp->mb[7]; 2668 ha->orig_fw_iocb_count = mcp->mb[10]; 2669 if (ha->flags.npiv_supported) 2670 ha->max_npiv_vports = mcp->mb[11]; 2671 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2672 ha->fw_max_fcf_count = mcp->mb[12]; 2673 } 2674 2675 return (rval); 2676 } 2677 2678 /* 2679 * qla2x00_get_fcal_position_map 2680 * Get FCAL (LILP) position map using mailbox command 2681 * 2682 * Input: 2683 * ha = adapter state pointer. 2684 * pos_map = buffer pointer (can be NULL). 2685 * 2686 * Returns: 2687 * qla2x00 local function return status code. 2688 * 2689 * Context: 2690 * Kernel context. 2691 */ 2692 int 2693 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map) 2694 { 2695 int rval; 2696 mbx_cmd_t mc; 2697 mbx_cmd_t *mcp = &mc; 2698 char *pmap; 2699 dma_addr_t pmap_dma; 2700 struct qla_hw_data *ha = vha->hw; 2701 2702 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f, 2703 "Entered %s.\n", __func__); 2704 2705 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma); 2706 if (pmap == NULL) { 2707 ql_log(ql_log_warn, vha, 0x1080, 2708 "Memory alloc failed.\n"); 2709 return QLA_MEMORY_ALLOC_FAILED; 2710 } 2711 memset(pmap, 0, FCAL_MAP_SIZE); 2712 2713 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP; 2714 mcp->mb[2] = MSW(pmap_dma); 2715 mcp->mb[3] = LSW(pmap_dma); 2716 mcp->mb[6] = MSW(MSD(pmap_dma)); 2717 mcp->mb[7] = LSW(MSD(pmap_dma)); 2718 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2719 mcp->in_mb = MBX_1|MBX_0; 2720 mcp->buf_size = FCAL_MAP_SIZE; 2721 mcp->flags = MBX_DMA_IN; 2722 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2723 rval = qla2x00_mailbox_command(vha, mcp); 2724 2725 if (rval == QLA_SUCCESS) { 2726 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081, 2727 "mb0/mb1=%x/%X FC/AL position map size (%x).\n", 2728 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]); 2729 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d, 2730 pmap, pmap[0] + 1); 2731 2732 if (pos_map) 2733 memcpy(pos_map, pmap, FCAL_MAP_SIZE); 2734 } 2735 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma); 2736 2737 if (rval != QLA_SUCCESS) { 2738 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval); 2739 } else { 2740 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083, 2741 "Done %s.\n", __func__); 2742 } 2743 2744 return rval; 2745 } 2746 2747 /* 2748 * qla2x00_get_link_status 2749 * 2750 * Input: 2751 * ha = adapter block pointer. 2752 * loop_id = device loop ID. 2753 * ret_buf = pointer to link status return buffer. 2754 * 2755 * Returns: 2756 * 0 = success. 2757 * BIT_0 = mem alloc error. 2758 * BIT_1 = mailbox error. 2759 */ 2760 int 2761 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id, 2762 struct link_statistics *stats, dma_addr_t stats_dma) 2763 { 2764 int rval; 2765 mbx_cmd_t mc; 2766 mbx_cmd_t *mcp = &mc; 2767 uint32_t *iter = (void *)stats; 2768 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter); 2769 struct qla_hw_data *ha = vha->hw; 2770 2771 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084, 2772 "Entered %s.\n", __func__); 2773 2774 mcp->mb[0] = MBC_GET_LINK_STATUS; 2775 mcp->mb[2] = MSW(LSD(stats_dma)); 2776 mcp->mb[3] = LSW(LSD(stats_dma)); 2777 mcp->mb[6] = MSW(MSD(stats_dma)); 2778 mcp->mb[7] = LSW(MSD(stats_dma)); 2779 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2780 mcp->in_mb = MBX_0; 2781 if (IS_FWI2_CAPABLE(ha)) { 2782 mcp->mb[1] = loop_id; 2783 mcp->mb[4] = 0; 2784 mcp->mb[10] = 0; 2785 mcp->out_mb |= MBX_10|MBX_4|MBX_1; 2786 mcp->in_mb |= MBX_1; 2787 } else if (HAS_EXTENDED_IDS(ha)) { 2788 mcp->mb[1] = loop_id; 2789 mcp->mb[10] = 0; 2790 mcp->out_mb |= MBX_10|MBX_1; 2791 } else { 2792 mcp->mb[1] = loop_id << 8; 2793 mcp->out_mb |= MBX_1; 2794 } 2795 mcp->tov = MBX_TOV_SECONDS; 2796 mcp->flags = IOCTL_CMD; 2797 rval = qla2x00_mailbox_command(vha, mcp); 2798 2799 if (rval == QLA_SUCCESS) { 2800 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2801 ql_dbg(ql_dbg_mbx, vha, 0x1085, 2802 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2803 rval = QLA_FUNCTION_FAILED; 2804 } else { 2805 /* Re-endianize - firmware data is le32. */ 2806 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086, 2807 "Done %s.\n", __func__); 2808 for ( ; dwords--; iter++) 2809 le32_to_cpus(iter); 2810 } 2811 } else { 2812 /* Failed. */ 2813 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval); 2814 } 2815 2816 return rval; 2817 } 2818 2819 int 2820 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats, 2821 dma_addr_t stats_dma, uint options) 2822 { 2823 int rval; 2824 mbx_cmd_t mc; 2825 mbx_cmd_t *mcp = &mc; 2826 uint32_t *iter, dwords; 2827 2828 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088, 2829 "Entered %s.\n", __func__); 2830 2831 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS; 2832 mcp->mb[2] = MSW(stats_dma); 2833 mcp->mb[3] = LSW(stats_dma); 2834 mcp->mb[6] = MSW(MSD(stats_dma)); 2835 mcp->mb[7] = LSW(MSD(stats_dma)); 2836 mcp->mb[8] = sizeof(struct link_statistics) / 4; 2837 mcp->mb[9] = vha->vp_idx; 2838 mcp->mb[10] = options; 2839 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2840 mcp->in_mb = MBX_2|MBX_1|MBX_0; 2841 mcp->tov = MBX_TOV_SECONDS; 2842 mcp->flags = IOCTL_CMD; 2843 rval = qla2x00_mailbox_command(vha, mcp); 2844 2845 if (rval == QLA_SUCCESS) { 2846 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2847 ql_dbg(ql_dbg_mbx, vha, 0x1089, 2848 "Failed mb[0]=%x.\n", mcp->mb[0]); 2849 rval = QLA_FUNCTION_FAILED; 2850 } else { 2851 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a, 2852 "Done %s.\n", __func__); 2853 /* Re-endianize - firmware data is le32. */ 2854 dwords = sizeof(struct link_statistics) / 4; 2855 iter = &stats->link_fail_cnt; 2856 for ( ; dwords--; iter++) 2857 le32_to_cpus(iter); 2858 } 2859 } else { 2860 /* Failed. */ 2861 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval); 2862 } 2863 2864 return rval; 2865 } 2866 2867 int 2868 qla24xx_abort_command(srb_t *sp) 2869 { 2870 int rval; 2871 unsigned long flags = 0; 2872 2873 struct abort_entry_24xx *abt; 2874 dma_addr_t abt_dma; 2875 uint32_t handle; 2876 fc_port_t *fcport = sp->fcport; 2877 struct scsi_qla_host *vha = fcport->vha; 2878 struct qla_hw_data *ha = vha->hw; 2879 struct req_que *req = vha->req; 2880 2881 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c, 2882 "Entered %s.\n", __func__); 2883 2884 if (vha->flags.qpairs_available && sp->qpair) 2885 req = sp->qpair->req; 2886 2887 if (ql2xasynctmfenable) 2888 return qla24xx_async_abort_command(sp); 2889 2890 spin_lock_irqsave(&ha->hardware_lock, flags); 2891 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 2892 if (req->outstanding_cmds[handle] == sp) 2893 break; 2894 } 2895 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2896 if (handle == req->num_outstanding_cmds) { 2897 /* Command not found. */ 2898 return QLA_FUNCTION_FAILED; 2899 } 2900 2901 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma); 2902 if (abt == NULL) { 2903 ql_log(ql_log_warn, vha, 0x108d, 2904 "Failed to allocate abort IOCB.\n"); 2905 return QLA_MEMORY_ALLOC_FAILED; 2906 } 2907 memset(abt, 0, sizeof(struct abort_entry_24xx)); 2908 2909 abt->entry_type = ABORT_IOCB_TYPE; 2910 abt->entry_count = 1; 2911 abt->handle = MAKE_HANDLE(req->id, abt->handle); 2912 abt->nport_handle = cpu_to_le16(fcport->loop_id); 2913 abt->handle_to_abort = MAKE_HANDLE(req->id, handle); 2914 abt->port_id[0] = fcport->d_id.b.al_pa; 2915 abt->port_id[1] = fcport->d_id.b.area; 2916 abt->port_id[2] = fcport->d_id.b.domain; 2917 abt->vp_index = fcport->vha->vp_idx; 2918 2919 abt->req_que_no = cpu_to_le16(req->id); 2920 2921 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0); 2922 if (rval != QLA_SUCCESS) { 2923 ql_dbg(ql_dbg_mbx, vha, 0x108e, 2924 "Failed to issue IOCB (%x).\n", rval); 2925 } else if (abt->entry_status != 0) { 2926 ql_dbg(ql_dbg_mbx, vha, 0x108f, 2927 "Failed to complete IOCB -- error status (%x).\n", 2928 abt->entry_status); 2929 rval = QLA_FUNCTION_FAILED; 2930 } else if (abt->nport_handle != cpu_to_le16(0)) { 2931 ql_dbg(ql_dbg_mbx, vha, 0x1090, 2932 "Failed to complete IOCB -- completion status (%x).\n", 2933 le16_to_cpu(abt->nport_handle)); 2934 if (abt->nport_handle == CS_IOCB_ERROR) 2935 rval = QLA_FUNCTION_PARAMETER_ERROR; 2936 else 2937 rval = QLA_FUNCTION_FAILED; 2938 } else { 2939 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091, 2940 "Done %s.\n", __func__); 2941 } 2942 2943 dma_pool_free(ha->s_dma_pool, abt, abt_dma); 2944 2945 return rval; 2946 } 2947 2948 struct tsk_mgmt_cmd { 2949 union { 2950 struct tsk_mgmt_entry tsk; 2951 struct sts_entry_24xx sts; 2952 } p; 2953 }; 2954 2955 static int 2956 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport, 2957 uint64_t l, int tag) 2958 { 2959 int rval, rval2; 2960 struct tsk_mgmt_cmd *tsk; 2961 struct sts_entry_24xx *sts; 2962 dma_addr_t tsk_dma; 2963 scsi_qla_host_t *vha; 2964 struct qla_hw_data *ha; 2965 struct req_que *req; 2966 struct rsp_que *rsp; 2967 struct qla_qpair *qpair; 2968 2969 vha = fcport->vha; 2970 ha = vha->hw; 2971 req = vha->req; 2972 2973 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092, 2974 "Entered %s.\n", __func__); 2975 2976 if (vha->vp_idx && vha->qpair) { 2977 /* NPIV port */ 2978 qpair = vha->qpair; 2979 rsp = qpair->rsp; 2980 req = qpair->req; 2981 } else { 2982 rsp = req->rsp; 2983 } 2984 2985 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma); 2986 if (tsk == NULL) { 2987 ql_log(ql_log_warn, vha, 0x1093, 2988 "Failed to allocate task management IOCB.\n"); 2989 return QLA_MEMORY_ALLOC_FAILED; 2990 } 2991 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd)); 2992 2993 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE; 2994 tsk->p.tsk.entry_count = 1; 2995 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle); 2996 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id); 2997 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2); 2998 tsk->p.tsk.control_flags = cpu_to_le32(type); 2999 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa; 3000 tsk->p.tsk.port_id[1] = fcport->d_id.b.area; 3001 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain; 3002 tsk->p.tsk.vp_index = fcport->vha->vp_idx; 3003 if (type == TCF_LUN_RESET) { 3004 int_to_scsilun(l, &tsk->p.tsk.lun); 3005 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun, 3006 sizeof(tsk->p.tsk.lun)); 3007 } 3008 3009 sts = &tsk->p.sts; 3010 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0); 3011 if (rval != QLA_SUCCESS) { 3012 ql_dbg(ql_dbg_mbx, vha, 0x1094, 3013 "Failed to issue %s reset IOCB (%x).\n", name, rval); 3014 } else if (sts->entry_status != 0) { 3015 ql_dbg(ql_dbg_mbx, vha, 0x1095, 3016 "Failed to complete IOCB -- error status (%x).\n", 3017 sts->entry_status); 3018 rval = QLA_FUNCTION_FAILED; 3019 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) { 3020 ql_dbg(ql_dbg_mbx, vha, 0x1096, 3021 "Failed to complete IOCB -- completion status (%x).\n", 3022 le16_to_cpu(sts->comp_status)); 3023 rval = QLA_FUNCTION_FAILED; 3024 } else if (le16_to_cpu(sts->scsi_status) & 3025 SS_RESPONSE_INFO_LEN_VALID) { 3026 if (le32_to_cpu(sts->rsp_data_len) < 4) { 3027 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097, 3028 "Ignoring inconsistent data length -- not enough " 3029 "response info (%d).\n", 3030 le32_to_cpu(sts->rsp_data_len)); 3031 } else if (sts->data[3]) { 3032 ql_dbg(ql_dbg_mbx, vha, 0x1098, 3033 "Failed to complete IOCB -- response (%x).\n", 3034 sts->data[3]); 3035 rval = QLA_FUNCTION_FAILED; 3036 } 3037 } 3038 3039 /* Issue marker IOCB. */ 3040 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 3041 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID); 3042 if (rval2 != QLA_SUCCESS) { 3043 ql_dbg(ql_dbg_mbx, vha, 0x1099, 3044 "Failed to issue marker IOCB (%x).\n", rval2); 3045 } else { 3046 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a, 3047 "Done %s.\n", __func__); 3048 } 3049 3050 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma); 3051 3052 return rval; 3053 } 3054 3055 int 3056 qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag) 3057 { 3058 struct qla_hw_data *ha = fcport->vha->hw; 3059 3060 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 3061 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag); 3062 3063 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag); 3064 } 3065 3066 int 3067 qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 3068 { 3069 struct qla_hw_data *ha = fcport->vha->hw; 3070 3071 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 3072 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag); 3073 3074 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag); 3075 } 3076 3077 int 3078 qla2x00_system_error(scsi_qla_host_t *vha) 3079 { 3080 int rval; 3081 mbx_cmd_t mc; 3082 mbx_cmd_t *mcp = &mc; 3083 struct qla_hw_data *ha = vha->hw; 3084 3085 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha)) 3086 return QLA_FUNCTION_FAILED; 3087 3088 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b, 3089 "Entered %s.\n", __func__); 3090 3091 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR; 3092 mcp->out_mb = MBX_0; 3093 mcp->in_mb = MBX_0; 3094 mcp->tov = 5; 3095 mcp->flags = 0; 3096 rval = qla2x00_mailbox_command(vha, mcp); 3097 3098 if (rval != QLA_SUCCESS) { 3099 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval); 3100 } else { 3101 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d, 3102 "Done %s.\n", __func__); 3103 } 3104 3105 return rval; 3106 } 3107 3108 int 3109 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data) 3110 { 3111 int rval; 3112 mbx_cmd_t mc; 3113 mbx_cmd_t *mcp = &mc; 3114 3115 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 3116 !IS_QLA27XX(vha->hw)) 3117 return QLA_FUNCTION_FAILED; 3118 3119 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182, 3120 "Entered %s.\n", __func__); 3121 3122 mcp->mb[0] = MBC_WRITE_SERDES; 3123 mcp->mb[1] = addr; 3124 if (IS_QLA2031(vha->hw)) 3125 mcp->mb[2] = data & 0xff; 3126 else 3127 mcp->mb[2] = data; 3128 3129 mcp->mb[3] = 0; 3130 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 3131 mcp->in_mb = MBX_0; 3132 mcp->tov = MBX_TOV_SECONDS; 3133 mcp->flags = 0; 3134 rval = qla2x00_mailbox_command(vha, mcp); 3135 3136 if (rval != QLA_SUCCESS) { 3137 ql_dbg(ql_dbg_mbx, vha, 0x1183, 3138 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3139 } else { 3140 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184, 3141 "Done %s.\n", __func__); 3142 } 3143 3144 return rval; 3145 } 3146 3147 int 3148 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data) 3149 { 3150 int rval; 3151 mbx_cmd_t mc; 3152 mbx_cmd_t *mcp = &mc; 3153 3154 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 3155 !IS_QLA27XX(vha->hw)) 3156 return QLA_FUNCTION_FAILED; 3157 3158 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185, 3159 "Entered %s.\n", __func__); 3160 3161 mcp->mb[0] = MBC_READ_SERDES; 3162 mcp->mb[1] = addr; 3163 mcp->mb[3] = 0; 3164 mcp->out_mb = MBX_3|MBX_1|MBX_0; 3165 mcp->in_mb = MBX_1|MBX_0; 3166 mcp->tov = MBX_TOV_SECONDS; 3167 mcp->flags = 0; 3168 rval = qla2x00_mailbox_command(vha, mcp); 3169 3170 if (IS_QLA2031(vha->hw)) 3171 *data = mcp->mb[1] & 0xff; 3172 else 3173 *data = mcp->mb[1]; 3174 3175 if (rval != QLA_SUCCESS) { 3176 ql_dbg(ql_dbg_mbx, vha, 0x1186, 3177 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3178 } else { 3179 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187, 3180 "Done %s.\n", __func__); 3181 } 3182 3183 return rval; 3184 } 3185 3186 int 3187 qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) 3188 { 3189 int rval; 3190 mbx_cmd_t mc; 3191 mbx_cmd_t *mcp = &mc; 3192 3193 if (!IS_QLA8044(vha->hw)) 3194 return QLA_FUNCTION_FAILED; 3195 3196 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1186, 3197 "Entered %s.\n", __func__); 3198 3199 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 3200 mcp->mb[1] = HCS_WRITE_SERDES; 3201 mcp->mb[3] = LSW(addr); 3202 mcp->mb[4] = MSW(addr); 3203 mcp->mb[5] = LSW(data); 3204 mcp->mb[6] = MSW(data); 3205 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0; 3206 mcp->in_mb = MBX_0; 3207 mcp->tov = MBX_TOV_SECONDS; 3208 mcp->flags = 0; 3209 rval = qla2x00_mailbox_command(vha, mcp); 3210 3211 if (rval != QLA_SUCCESS) { 3212 ql_dbg(ql_dbg_mbx, vha, 0x1187, 3213 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3214 } else { 3215 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188, 3216 "Done %s.\n", __func__); 3217 } 3218 3219 return rval; 3220 } 3221 3222 int 3223 qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) 3224 { 3225 int rval; 3226 mbx_cmd_t mc; 3227 mbx_cmd_t *mcp = &mc; 3228 3229 if (!IS_QLA8044(vha->hw)) 3230 return QLA_FUNCTION_FAILED; 3231 3232 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189, 3233 "Entered %s.\n", __func__); 3234 3235 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 3236 mcp->mb[1] = HCS_READ_SERDES; 3237 mcp->mb[3] = LSW(addr); 3238 mcp->mb[4] = MSW(addr); 3239 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0; 3240 mcp->in_mb = MBX_2|MBX_1|MBX_0; 3241 mcp->tov = MBX_TOV_SECONDS; 3242 mcp->flags = 0; 3243 rval = qla2x00_mailbox_command(vha, mcp); 3244 3245 *data = mcp->mb[2] << 16 | mcp->mb[1]; 3246 3247 if (rval != QLA_SUCCESS) { 3248 ql_dbg(ql_dbg_mbx, vha, 0x118a, 3249 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3250 } else { 3251 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b, 3252 "Done %s.\n", __func__); 3253 } 3254 3255 return rval; 3256 } 3257 3258 /** 3259 * qla2x00_set_serdes_params() - 3260 * @ha: HA context 3261 * 3262 * Returns 3263 */ 3264 int 3265 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g, 3266 uint16_t sw_em_2g, uint16_t sw_em_4g) 3267 { 3268 int rval; 3269 mbx_cmd_t mc; 3270 mbx_cmd_t *mcp = &mc; 3271 3272 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e, 3273 "Entered %s.\n", __func__); 3274 3275 mcp->mb[0] = MBC_SERDES_PARAMS; 3276 mcp->mb[1] = BIT_0; 3277 mcp->mb[2] = sw_em_1g | BIT_15; 3278 mcp->mb[3] = sw_em_2g | BIT_15; 3279 mcp->mb[4] = sw_em_4g | BIT_15; 3280 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3281 mcp->in_mb = MBX_0; 3282 mcp->tov = MBX_TOV_SECONDS; 3283 mcp->flags = 0; 3284 rval = qla2x00_mailbox_command(vha, mcp); 3285 3286 if (rval != QLA_SUCCESS) { 3287 /*EMPTY*/ 3288 ql_dbg(ql_dbg_mbx, vha, 0x109f, 3289 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3290 } else { 3291 /*EMPTY*/ 3292 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0, 3293 "Done %s.\n", __func__); 3294 } 3295 3296 return rval; 3297 } 3298 3299 int 3300 qla2x00_stop_firmware(scsi_qla_host_t *vha) 3301 { 3302 int rval; 3303 mbx_cmd_t mc; 3304 mbx_cmd_t *mcp = &mc; 3305 3306 if (!IS_FWI2_CAPABLE(vha->hw)) 3307 return QLA_FUNCTION_FAILED; 3308 3309 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1, 3310 "Entered %s.\n", __func__); 3311 3312 mcp->mb[0] = MBC_STOP_FIRMWARE; 3313 mcp->mb[1] = 0; 3314 mcp->out_mb = MBX_1|MBX_0; 3315 mcp->in_mb = MBX_0; 3316 mcp->tov = 5; 3317 mcp->flags = 0; 3318 rval = qla2x00_mailbox_command(vha, mcp); 3319 3320 if (rval != QLA_SUCCESS) { 3321 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval); 3322 if (mcp->mb[0] == MBS_INVALID_COMMAND) 3323 rval = QLA_INVALID_COMMAND; 3324 } else { 3325 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3, 3326 "Done %s.\n", __func__); 3327 } 3328 3329 return rval; 3330 } 3331 3332 int 3333 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma, 3334 uint16_t buffers) 3335 { 3336 int rval; 3337 mbx_cmd_t mc; 3338 mbx_cmd_t *mcp = &mc; 3339 3340 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4, 3341 "Entered %s.\n", __func__); 3342 3343 if (!IS_FWI2_CAPABLE(vha->hw)) 3344 return QLA_FUNCTION_FAILED; 3345 3346 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3347 return QLA_FUNCTION_FAILED; 3348 3349 mcp->mb[0] = MBC_TRACE_CONTROL; 3350 mcp->mb[1] = TC_EFT_ENABLE; 3351 mcp->mb[2] = LSW(eft_dma); 3352 mcp->mb[3] = MSW(eft_dma); 3353 mcp->mb[4] = LSW(MSD(eft_dma)); 3354 mcp->mb[5] = MSW(MSD(eft_dma)); 3355 mcp->mb[6] = buffers; 3356 mcp->mb[7] = TC_AEN_DISABLE; 3357 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3358 mcp->in_mb = MBX_1|MBX_0; 3359 mcp->tov = MBX_TOV_SECONDS; 3360 mcp->flags = 0; 3361 rval = qla2x00_mailbox_command(vha, mcp); 3362 if (rval != QLA_SUCCESS) { 3363 ql_dbg(ql_dbg_mbx, vha, 0x10a5, 3364 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3365 rval, mcp->mb[0], mcp->mb[1]); 3366 } else { 3367 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6, 3368 "Done %s.\n", __func__); 3369 } 3370 3371 return rval; 3372 } 3373 3374 int 3375 qla2x00_disable_eft_trace(scsi_qla_host_t *vha) 3376 { 3377 int rval; 3378 mbx_cmd_t mc; 3379 mbx_cmd_t *mcp = &mc; 3380 3381 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7, 3382 "Entered %s.\n", __func__); 3383 3384 if (!IS_FWI2_CAPABLE(vha->hw)) 3385 return QLA_FUNCTION_FAILED; 3386 3387 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3388 return QLA_FUNCTION_FAILED; 3389 3390 mcp->mb[0] = MBC_TRACE_CONTROL; 3391 mcp->mb[1] = TC_EFT_DISABLE; 3392 mcp->out_mb = MBX_1|MBX_0; 3393 mcp->in_mb = MBX_1|MBX_0; 3394 mcp->tov = MBX_TOV_SECONDS; 3395 mcp->flags = 0; 3396 rval = qla2x00_mailbox_command(vha, mcp); 3397 if (rval != QLA_SUCCESS) { 3398 ql_dbg(ql_dbg_mbx, vha, 0x10a8, 3399 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3400 rval, mcp->mb[0], mcp->mb[1]); 3401 } else { 3402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9, 3403 "Done %s.\n", __func__); 3404 } 3405 3406 return rval; 3407 } 3408 3409 int 3410 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma, 3411 uint16_t buffers, uint16_t *mb, uint32_t *dwords) 3412 { 3413 int rval; 3414 mbx_cmd_t mc; 3415 mbx_cmd_t *mcp = &mc; 3416 3417 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa, 3418 "Entered %s.\n", __func__); 3419 3420 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) && 3421 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw)) 3422 return QLA_FUNCTION_FAILED; 3423 3424 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3425 return QLA_FUNCTION_FAILED; 3426 3427 mcp->mb[0] = MBC_TRACE_CONTROL; 3428 mcp->mb[1] = TC_FCE_ENABLE; 3429 mcp->mb[2] = LSW(fce_dma); 3430 mcp->mb[3] = MSW(fce_dma); 3431 mcp->mb[4] = LSW(MSD(fce_dma)); 3432 mcp->mb[5] = MSW(MSD(fce_dma)); 3433 mcp->mb[6] = buffers; 3434 mcp->mb[7] = TC_AEN_DISABLE; 3435 mcp->mb[8] = 0; 3436 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE; 3437 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE; 3438 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3439 MBX_1|MBX_0; 3440 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3441 mcp->tov = MBX_TOV_SECONDS; 3442 mcp->flags = 0; 3443 rval = qla2x00_mailbox_command(vha, mcp); 3444 if (rval != QLA_SUCCESS) { 3445 ql_dbg(ql_dbg_mbx, vha, 0x10ab, 3446 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3447 rval, mcp->mb[0], mcp->mb[1]); 3448 } else { 3449 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac, 3450 "Done %s.\n", __func__); 3451 3452 if (mb) 3453 memcpy(mb, mcp->mb, 8 * sizeof(*mb)); 3454 if (dwords) 3455 *dwords = buffers; 3456 } 3457 3458 return rval; 3459 } 3460 3461 int 3462 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd) 3463 { 3464 int rval; 3465 mbx_cmd_t mc; 3466 mbx_cmd_t *mcp = &mc; 3467 3468 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad, 3469 "Entered %s.\n", __func__); 3470 3471 if (!IS_FWI2_CAPABLE(vha->hw)) 3472 return QLA_FUNCTION_FAILED; 3473 3474 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3475 return QLA_FUNCTION_FAILED; 3476 3477 mcp->mb[0] = MBC_TRACE_CONTROL; 3478 mcp->mb[1] = TC_FCE_DISABLE; 3479 mcp->mb[2] = TC_FCE_DISABLE_TRACE; 3480 mcp->out_mb = MBX_2|MBX_1|MBX_0; 3481 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3482 MBX_1|MBX_0; 3483 mcp->tov = MBX_TOV_SECONDS; 3484 mcp->flags = 0; 3485 rval = qla2x00_mailbox_command(vha, mcp); 3486 if (rval != QLA_SUCCESS) { 3487 ql_dbg(ql_dbg_mbx, vha, 0x10ae, 3488 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3489 rval, mcp->mb[0], mcp->mb[1]); 3490 } else { 3491 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af, 3492 "Done %s.\n", __func__); 3493 3494 if (wr) 3495 *wr = (uint64_t) mcp->mb[5] << 48 | 3496 (uint64_t) mcp->mb[4] << 32 | 3497 (uint64_t) mcp->mb[3] << 16 | 3498 (uint64_t) mcp->mb[2]; 3499 if (rd) 3500 *rd = (uint64_t) mcp->mb[9] << 48 | 3501 (uint64_t) mcp->mb[8] << 32 | 3502 (uint64_t) mcp->mb[7] << 16 | 3503 (uint64_t) mcp->mb[6]; 3504 } 3505 3506 return rval; 3507 } 3508 3509 int 3510 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3511 uint16_t *port_speed, uint16_t *mb) 3512 { 3513 int rval; 3514 mbx_cmd_t mc; 3515 mbx_cmd_t *mcp = &mc; 3516 3517 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0, 3518 "Entered %s.\n", __func__); 3519 3520 if (!IS_IIDMA_CAPABLE(vha->hw)) 3521 return QLA_FUNCTION_FAILED; 3522 3523 mcp->mb[0] = MBC_PORT_PARAMS; 3524 mcp->mb[1] = loop_id; 3525 mcp->mb[2] = mcp->mb[3] = 0; 3526 mcp->mb[9] = vha->vp_idx; 3527 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3528 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3529 mcp->tov = MBX_TOV_SECONDS; 3530 mcp->flags = 0; 3531 rval = qla2x00_mailbox_command(vha, mcp); 3532 3533 /* Return mailbox statuses. */ 3534 if (mb != NULL) { 3535 mb[0] = mcp->mb[0]; 3536 mb[1] = mcp->mb[1]; 3537 mb[3] = mcp->mb[3]; 3538 } 3539 3540 if (rval != QLA_SUCCESS) { 3541 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval); 3542 } else { 3543 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2, 3544 "Done %s.\n", __func__); 3545 if (port_speed) 3546 *port_speed = mcp->mb[3]; 3547 } 3548 3549 return rval; 3550 } 3551 3552 int 3553 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3554 uint16_t port_speed, uint16_t *mb) 3555 { 3556 int rval; 3557 mbx_cmd_t mc; 3558 mbx_cmd_t *mcp = &mc; 3559 3560 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3, 3561 "Entered %s.\n", __func__); 3562 3563 if (!IS_IIDMA_CAPABLE(vha->hw)) 3564 return QLA_FUNCTION_FAILED; 3565 3566 mcp->mb[0] = MBC_PORT_PARAMS; 3567 mcp->mb[1] = loop_id; 3568 mcp->mb[2] = BIT_0; 3569 if (IS_CNA_CAPABLE(vha->hw)) 3570 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); 3571 else 3572 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); 3573 mcp->mb[9] = vha->vp_idx; 3574 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3575 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3576 mcp->tov = MBX_TOV_SECONDS; 3577 mcp->flags = 0; 3578 rval = qla2x00_mailbox_command(vha, mcp); 3579 3580 /* Return mailbox statuses. */ 3581 if (mb != NULL) { 3582 mb[0] = mcp->mb[0]; 3583 mb[1] = mcp->mb[1]; 3584 mb[3] = mcp->mb[3]; 3585 } 3586 3587 if (rval != QLA_SUCCESS) { 3588 ql_dbg(ql_dbg_mbx, vha, 0x10b4, 3589 "Failed=%x.\n", rval); 3590 } else { 3591 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5, 3592 "Done %s.\n", __func__); 3593 } 3594 3595 return rval; 3596 } 3597 3598 void 3599 qla24xx_report_id_acquisition(scsi_qla_host_t *vha, 3600 struct vp_rpt_id_entry_24xx *rptid_entry) 3601 { 3602 struct qla_hw_data *ha = vha->hw; 3603 scsi_qla_host_t *vp = NULL; 3604 unsigned long flags; 3605 int found; 3606 3607 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6, 3608 "Entered %s.\n", __func__); 3609 3610 if (rptid_entry->entry_status != 0) 3611 return; 3612 3613 if (rptid_entry->format == 0) { 3614 /* loop */ 3615 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7, 3616 "Format 0 : Number of VPs setup %d, number of " 3617 "VPs acquired %d.\n", rptid_entry->vp_setup, 3618 rptid_entry->vp_acquired); 3619 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8, 3620 "Primary port id %02x%02x%02x.\n", 3621 rptid_entry->port_id[2], rptid_entry->port_id[1], 3622 rptid_entry->port_id[0]); 3623 3624 vha->d_id.b.domain = rptid_entry->port_id[2]; 3625 vha->d_id.b.area = rptid_entry->port_id[1]; 3626 vha->d_id.b.al_pa = rptid_entry->port_id[0]; 3627 3628 spin_lock_irqsave(&ha->vport_slock, flags); 3629 qlt_update_vp_map(vha, SET_AL_PA); 3630 spin_unlock_irqrestore(&ha->vport_slock, flags); 3631 3632 } else if (rptid_entry->format == 1) { 3633 /* fabric */ 3634 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9, 3635 "Format 1: VP[%d] enabled - status %d - with " 3636 "port id %02x%02x%02x.\n", rptid_entry->vp_idx, 3637 rptid_entry->vp_status, 3638 rptid_entry->port_id[2], rptid_entry->port_id[1], 3639 rptid_entry->port_id[0]); 3640 3641 /* buffer to buffer credit flag */ 3642 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0; 3643 3644 if (rptid_entry->vp_idx == 0) { 3645 if (rptid_entry->vp_status == VP_STAT_COMPL) { 3646 /* FA-WWN is only for physical port */ 3647 if (qla_ini_mode_enabled(vha) && 3648 ha->flags.fawwpn_enabled && 3649 (rptid_entry->u.f1.flags & 3650 VP_FLAGS_NAME_VALID)) { 3651 memcpy(vha->port_name, 3652 rptid_entry->u.f1.port_name, 3653 WWN_SIZE); 3654 } 3655 3656 vha->d_id.b.domain = rptid_entry->port_id[2]; 3657 vha->d_id.b.area = rptid_entry->port_id[1]; 3658 vha->d_id.b.al_pa = rptid_entry->port_id[0]; 3659 spin_lock_irqsave(&ha->vport_slock, flags); 3660 qlt_update_vp_map(vha, SET_AL_PA); 3661 spin_unlock_irqrestore(&ha->vport_slock, flags); 3662 } 3663 3664 fc_host_port_name(vha->host) = 3665 wwn_to_u64(vha->port_name); 3666 3667 if (qla_ini_mode_enabled(vha)) 3668 ql_dbg(ql_dbg_mbx, vha, 0x1018, 3669 "FA-WWN portname %016llx (%x)\n", 3670 fc_host_port_name(vha->host), 3671 rptid_entry->vp_status); 3672 3673 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags); 3674 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags); 3675 } else { 3676 if (rptid_entry->vp_status != VP_STAT_COMPL && 3677 rptid_entry->vp_status != VP_STAT_ID_CHG) { 3678 ql_dbg(ql_dbg_mbx, vha, 0x10ba, 3679 "Could not acquire ID for VP[%d].\n", 3680 rptid_entry->vp_idx); 3681 return; 3682 } 3683 3684 found = 0; 3685 spin_lock_irqsave(&ha->vport_slock, flags); 3686 list_for_each_entry(vp, &ha->vp_list, list) { 3687 if (rptid_entry->vp_idx == vp->vp_idx) { 3688 found = 1; 3689 break; 3690 } 3691 } 3692 spin_unlock_irqrestore(&ha->vport_slock, flags); 3693 3694 if (!found) 3695 return; 3696 3697 vp->d_id.b.domain = rptid_entry->port_id[2]; 3698 vp->d_id.b.area = rptid_entry->port_id[1]; 3699 vp->d_id.b.al_pa = rptid_entry->port_id[0]; 3700 spin_lock_irqsave(&ha->vport_slock, flags); 3701 qlt_update_vp_map(vp, SET_AL_PA); 3702 spin_unlock_irqrestore(&ha->vport_slock, flags); 3703 3704 /* 3705 * Cannot configure here as we are still sitting on the 3706 * response queue. Handle it in dpc context. 3707 */ 3708 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags); 3709 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags); 3710 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags); 3711 } 3712 set_bit(VP_DPC_NEEDED, &vha->dpc_flags); 3713 qla2xxx_wake_dpc(vha); 3714 } else if (rptid_entry->format == 2) { 3715 ql_dbg(ql_dbg_async, vha, 0xffff, 3716 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n", 3717 rptid_entry->port_id[2], rptid_entry->port_id[1], 3718 rptid_entry->port_id[0]); 3719 3720 ql_dbg(ql_dbg_async, vha, 0xffff, 3721 "N2N: Remote WWPN %8phC.\n", 3722 rptid_entry->u.f2.port_name); 3723 3724 /* N2N. direct connect */ 3725 vha->d_id.b.domain = rptid_entry->port_id[2]; 3726 vha->d_id.b.area = rptid_entry->port_id[1]; 3727 vha->d_id.b.al_pa = rptid_entry->port_id[0]; 3728 3729 spin_lock_irqsave(&ha->vport_slock, flags); 3730 qlt_update_vp_map(vha, SET_AL_PA); 3731 spin_unlock_irqrestore(&ha->vport_slock, flags); 3732 } 3733 } 3734 3735 /* 3736 * qla24xx_modify_vp_config 3737 * Change VP configuration for vha 3738 * 3739 * Input: 3740 * vha = adapter block pointer. 3741 * 3742 * Returns: 3743 * qla2xxx local function return status code. 3744 * 3745 * Context: 3746 * Kernel context. 3747 */ 3748 int 3749 qla24xx_modify_vp_config(scsi_qla_host_t *vha) 3750 { 3751 int rval; 3752 struct vp_config_entry_24xx *vpmod; 3753 dma_addr_t vpmod_dma; 3754 struct qla_hw_data *ha = vha->hw; 3755 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3756 3757 /* This can be called by the parent */ 3758 3759 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb, 3760 "Entered %s.\n", __func__); 3761 3762 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma); 3763 if (!vpmod) { 3764 ql_log(ql_log_warn, vha, 0x10bc, 3765 "Failed to allocate modify VP IOCB.\n"); 3766 return QLA_MEMORY_ALLOC_FAILED; 3767 } 3768 3769 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx)); 3770 vpmod->entry_type = VP_CONFIG_IOCB_TYPE; 3771 vpmod->entry_count = 1; 3772 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS; 3773 vpmod->vp_count = 1; 3774 vpmod->vp_index1 = vha->vp_idx; 3775 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; 3776 3777 qlt_modify_vp_config(vha, vpmod); 3778 3779 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE); 3780 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE); 3781 vpmod->entry_count = 1; 3782 3783 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0); 3784 if (rval != QLA_SUCCESS) { 3785 ql_dbg(ql_dbg_mbx, vha, 0x10bd, 3786 "Failed to issue VP config IOCB (%x).\n", rval); 3787 } else if (vpmod->comp_status != 0) { 3788 ql_dbg(ql_dbg_mbx, vha, 0x10be, 3789 "Failed to complete IOCB -- error status (%x).\n", 3790 vpmod->comp_status); 3791 rval = QLA_FUNCTION_FAILED; 3792 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) { 3793 ql_dbg(ql_dbg_mbx, vha, 0x10bf, 3794 "Failed to complete IOCB -- completion status (%x).\n", 3795 le16_to_cpu(vpmod->comp_status)); 3796 rval = QLA_FUNCTION_FAILED; 3797 } else { 3798 /* EMPTY */ 3799 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0, 3800 "Done %s.\n", __func__); 3801 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING); 3802 } 3803 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma); 3804 3805 return rval; 3806 } 3807 3808 /* 3809 * qla24xx_control_vp 3810 * Enable a virtual port for given host 3811 * 3812 * Input: 3813 * ha = adapter block pointer. 3814 * vhba = virtual adapter (unused) 3815 * index = index number for enabled VP 3816 * 3817 * Returns: 3818 * qla2xxx local function return status code. 3819 * 3820 * Context: 3821 * Kernel context. 3822 */ 3823 int 3824 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd) 3825 { 3826 int rval; 3827 int map, pos; 3828 struct vp_ctrl_entry_24xx *vce; 3829 dma_addr_t vce_dma; 3830 struct qla_hw_data *ha = vha->hw; 3831 int vp_index = vha->vp_idx; 3832 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3833 3834 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1, 3835 "Entered %s enabling index %d.\n", __func__, vp_index); 3836 3837 if (vp_index == 0 || vp_index >= ha->max_npiv_vports) 3838 return QLA_PARAMETER_ERROR; 3839 3840 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma); 3841 if (!vce) { 3842 ql_log(ql_log_warn, vha, 0x10c2, 3843 "Failed to allocate VP control IOCB.\n"); 3844 return QLA_MEMORY_ALLOC_FAILED; 3845 } 3846 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx)); 3847 3848 vce->entry_type = VP_CTRL_IOCB_TYPE; 3849 vce->entry_count = 1; 3850 vce->command = cpu_to_le16(cmd); 3851 vce->vp_count = cpu_to_le16(1); 3852 3853 /* index map in firmware starts with 1; decrement index 3854 * this is ok as we never use index 0 3855 */ 3856 map = (vp_index - 1) / 8; 3857 pos = (vp_index - 1) & 7; 3858 mutex_lock(&ha->vport_lock); 3859 vce->vp_idx_map[map] |= 1 << pos; 3860 mutex_unlock(&ha->vport_lock); 3861 3862 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0); 3863 if (rval != QLA_SUCCESS) { 3864 ql_dbg(ql_dbg_mbx, vha, 0x10c3, 3865 "Failed to issue VP control IOCB (%x).\n", rval); 3866 } else if (vce->entry_status != 0) { 3867 ql_dbg(ql_dbg_mbx, vha, 0x10c4, 3868 "Failed to complete IOCB -- error status (%x).\n", 3869 vce->entry_status); 3870 rval = QLA_FUNCTION_FAILED; 3871 } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) { 3872 ql_dbg(ql_dbg_mbx, vha, 0x10c5, 3873 "Failed to complet IOCB -- completion status (%x).\n", 3874 le16_to_cpu(vce->comp_status)); 3875 rval = QLA_FUNCTION_FAILED; 3876 } else { 3877 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6, 3878 "Done %s.\n", __func__); 3879 } 3880 3881 dma_pool_free(ha->s_dma_pool, vce, vce_dma); 3882 3883 return rval; 3884 } 3885 3886 /* 3887 * qla2x00_send_change_request 3888 * Receive or disable RSCN request from fabric controller 3889 * 3890 * Input: 3891 * ha = adapter block pointer 3892 * format = registration format: 3893 * 0 - Reserved 3894 * 1 - Fabric detected registration 3895 * 2 - N_port detected registration 3896 * 3 - Full registration 3897 * FF - clear registration 3898 * vp_idx = Virtual port index 3899 * 3900 * Returns: 3901 * qla2x00 local function return status code. 3902 * 3903 * Context: 3904 * Kernel Context 3905 */ 3906 3907 int 3908 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format, 3909 uint16_t vp_idx) 3910 { 3911 int rval; 3912 mbx_cmd_t mc; 3913 mbx_cmd_t *mcp = &mc; 3914 3915 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7, 3916 "Entered %s.\n", __func__); 3917 3918 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST; 3919 mcp->mb[1] = format; 3920 mcp->mb[9] = vp_idx; 3921 mcp->out_mb = MBX_9|MBX_1|MBX_0; 3922 mcp->in_mb = MBX_0|MBX_1; 3923 mcp->tov = MBX_TOV_SECONDS; 3924 mcp->flags = 0; 3925 rval = qla2x00_mailbox_command(vha, mcp); 3926 3927 if (rval == QLA_SUCCESS) { 3928 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 3929 rval = BIT_1; 3930 } 3931 } else 3932 rval = BIT_1; 3933 3934 return rval; 3935 } 3936 3937 int 3938 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 3939 uint32_t size) 3940 { 3941 int rval; 3942 mbx_cmd_t mc; 3943 mbx_cmd_t *mcp = &mc; 3944 3945 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009, 3946 "Entered %s.\n", __func__); 3947 3948 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) { 3949 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 3950 mcp->mb[8] = MSW(addr); 3951 mcp->out_mb = MBX_8|MBX_0; 3952 } else { 3953 mcp->mb[0] = MBC_DUMP_RISC_RAM; 3954 mcp->out_mb = MBX_0; 3955 } 3956 mcp->mb[1] = LSW(addr); 3957 mcp->mb[2] = MSW(req_dma); 3958 mcp->mb[3] = LSW(req_dma); 3959 mcp->mb[6] = MSW(MSD(req_dma)); 3960 mcp->mb[7] = LSW(MSD(req_dma)); 3961 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 3962 if (IS_FWI2_CAPABLE(vha->hw)) { 3963 mcp->mb[4] = MSW(size); 3964 mcp->mb[5] = LSW(size); 3965 mcp->out_mb |= MBX_5|MBX_4; 3966 } else { 3967 mcp->mb[4] = LSW(size); 3968 mcp->out_mb |= MBX_4; 3969 } 3970 3971 mcp->in_mb = MBX_0; 3972 mcp->tov = MBX_TOV_SECONDS; 3973 mcp->flags = 0; 3974 rval = qla2x00_mailbox_command(vha, mcp); 3975 3976 if (rval != QLA_SUCCESS) { 3977 ql_dbg(ql_dbg_mbx, vha, 0x1008, 3978 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3979 } else { 3980 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007, 3981 "Done %s.\n", __func__); 3982 } 3983 3984 return rval; 3985 } 3986 /* 84XX Support **************************************************************/ 3987 3988 struct cs84xx_mgmt_cmd { 3989 union { 3990 struct verify_chip_entry_84xx req; 3991 struct verify_chip_rsp_84xx rsp; 3992 } p; 3993 }; 3994 3995 int 3996 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status) 3997 { 3998 int rval, retry; 3999 struct cs84xx_mgmt_cmd *mn; 4000 dma_addr_t mn_dma; 4001 uint16_t options; 4002 unsigned long flags; 4003 struct qla_hw_data *ha = vha->hw; 4004 4005 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8, 4006 "Entered %s.\n", __func__); 4007 4008 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma); 4009 if (mn == NULL) { 4010 return QLA_MEMORY_ALLOC_FAILED; 4011 } 4012 4013 /* Force Update? */ 4014 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0; 4015 /* Diagnostic firmware? */ 4016 /* options |= MENLO_DIAG_FW; */ 4017 /* We update the firmware with only one data sequence. */ 4018 options |= VCO_END_OF_DATA; 4019 4020 do { 4021 retry = 0; 4022 memset(mn, 0, sizeof(*mn)); 4023 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE; 4024 mn->p.req.entry_count = 1; 4025 mn->p.req.options = cpu_to_le16(options); 4026 4027 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c, 4028 "Dump of Verify Request.\n"); 4029 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e, 4030 (uint8_t *)mn, sizeof(*mn)); 4031 4032 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120); 4033 if (rval != QLA_SUCCESS) { 4034 ql_dbg(ql_dbg_mbx, vha, 0x10cb, 4035 "Failed to issue verify IOCB (%x).\n", rval); 4036 goto verify_done; 4037 } 4038 4039 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110, 4040 "Dump of Verify Response.\n"); 4041 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118, 4042 (uint8_t *)mn, sizeof(*mn)); 4043 4044 status[0] = le16_to_cpu(mn->p.rsp.comp_status); 4045 status[1] = status[0] == CS_VCS_CHIP_FAILURE ? 4046 le16_to_cpu(mn->p.rsp.failure_code) : 0; 4047 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce, 4048 "cs=%x fc=%x.\n", status[0], status[1]); 4049 4050 if (status[0] != CS_COMPLETE) { 4051 rval = QLA_FUNCTION_FAILED; 4052 if (!(options & VCO_DONT_UPDATE_FW)) { 4053 ql_dbg(ql_dbg_mbx, vha, 0x10cf, 4054 "Firmware update failed. Retrying " 4055 "without update firmware.\n"); 4056 options |= VCO_DONT_UPDATE_FW; 4057 options &= ~VCO_FORCE_UPDATE; 4058 retry = 1; 4059 } 4060 } else { 4061 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0, 4062 "Firmware updated to %x.\n", 4063 le32_to_cpu(mn->p.rsp.fw_ver)); 4064 4065 /* NOTE: we only update OP firmware. */ 4066 spin_lock_irqsave(&ha->cs84xx->access_lock, flags); 4067 ha->cs84xx->op_fw_version = 4068 le32_to_cpu(mn->p.rsp.fw_ver); 4069 spin_unlock_irqrestore(&ha->cs84xx->access_lock, 4070 flags); 4071 } 4072 } while (retry); 4073 4074 verify_done: 4075 dma_pool_free(ha->s_dma_pool, mn, mn_dma); 4076 4077 if (rval != QLA_SUCCESS) { 4078 ql_dbg(ql_dbg_mbx, vha, 0x10d1, 4079 "Failed=%x.\n", rval); 4080 } else { 4081 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2, 4082 "Done %s.\n", __func__); 4083 } 4084 4085 return rval; 4086 } 4087 4088 int 4089 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req) 4090 { 4091 int rval; 4092 unsigned long flags; 4093 mbx_cmd_t mc; 4094 mbx_cmd_t *mcp = &mc; 4095 struct qla_hw_data *ha = vha->hw; 4096 4097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3, 4098 "Entered %s.\n", __func__); 4099 4100 if (IS_SHADOW_REG_CAPABLE(ha)) 4101 req->options |= BIT_13; 4102 4103 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 4104 mcp->mb[1] = req->options; 4105 mcp->mb[2] = MSW(LSD(req->dma)); 4106 mcp->mb[3] = LSW(LSD(req->dma)); 4107 mcp->mb[6] = MSW(MSD(req->dma)); 4108 mcp->mb[7] = LSW(MSD(req->dma)); 4109 mcp->mb[5] = req->length; 4110 if (req->rsp) 4111 mcp->mb[10] = req->rsp->id; 4112 mcp->mb[12] = req->qos; 4113 mcp->mb[11] = req->vp_idx; 4114 mcp->mb[13] = req->rid; 4115 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4116 mcp->mb[15] = 0; 4117 4118 mcp->mb[4] = req->id; 4119 /* que in ptr index */ 4120 mcp->mb[8] = 0; 4121 /* que out ptr index */ 4122 mcp->mb[9] = *req->out_ptr = 0; 4123 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7| 4124 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4125 mcp->in_mb = MBX_0; 4126 mcp->flags = MBX_DMA_OUT; 4127 mcp->tov = MBX_TOV_SECONDS * 2; 4128 4129 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4130 mcp->in_mb |= MBX_1; 4131 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 4132 mcp->out_mb |= MBX_15; 4133 /* debug q create issue in SR-IOV */ 4134 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 4135 } 4136 4137 spin_lock_irqsave(&ha->hardware_lock, flags); 4138 if (!(req->options & BIT_0)) { 4139 WRT_REG_DWORD(req->req_q_in, 0); 4140 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 4141 WRT_REG_DWORD(req->req_q_out, 0); 4142 } 4143 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4144 4145 rval = qla2x00_mailbox_command(vha, mcp); 4146 if (rval != QLA_SUCCESS) { 4147 ql_dbg(ql_dbg_mbx, vha, 0x10d4, 4148 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4149 } else { 4150 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5, 4151 "Done %s.\n", __func__); 4152 } 4153 4154 return rval; 4155 } 4156 4157 int 4158 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp) 4159 { 4160 int rval; 4161 unsigned long flags; 4162 mbx_cmd_t mc; 4163 mbx_cmd_t *mcp = &mc; 4164 struct qla_hw_data *ha = vha->hw; 4165 4166 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6, 4167 "Entered %s.\n", __func__); 4168 4169 if (IS_SHADOW_REG_CAPABLE(ha)) 4170 rsp->options |= BIT_13; 4171 4172 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 4173 mcp->mb[1] = rsp->options; 4174 mcp->mb[2] = MSW(LSD(rsp->dma)); 4175 mcp->mb[3] = LSW(LSD(rsp->dma)); 4176 mcp->mb[6] = MSW(MSD(rsp->dma)); 4177 mcp->mb[7] = LSW(MSD(rsp->dma)); 4178 mcp->mb[5] = rsp->length; 4179 mcp->mb[14] = rsp->msix->entry; 4180 mcp->mb[13] = rsp->rid; 4181 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4182 mcp->mb[15] = 0; 4183 4184 mcp->mb[4] = rsp->id; 4185 /* que in ptr index */ 4186 mcp->mb[8] = *rsp->in_ptr = 0; 4187 /* que out ptr index */ 4188 mcp->mb[9] = 0; 4189 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7 4190 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4191 mcp->in_mb = MBX_0; 4192 mcp->flags = MBX_DMA_OUT; 4193 mcp->tov = MBX_TOV_SECONDS * 2; 4194 4195 if (IS_QLA81XX(ha)) { 4196 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 4197 mcp->in_mb |= MBX_1; 4198 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 4199 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10; 4200 mcp->in_mb |= MBX_1; 4201 /* debug q create issue in SR-IOV */ 4202 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 4203 } 4204 4205 spin_lock_irqsave(&ha->hardware_lock, flags); 4206 if (!(rsp->options & BIT_0)) { 4207 WRT_REG_DWORD(rsp->rsp_q_out, 0); 4208 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 4209 WRT_REG_DWORD(rsp->rsp_q_in, 0); 4210 } 4211 4212 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4213 4214 rval = qla2x00_mailbox_command(vha, mcp); 4215 if (rval != QLA_SUCCESS) { 4216 ql_dbg(ql_dbg_mbx, vha, 0x10d7, 4217 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4218 } else { 4219 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8, 4220 "Done %s.\n", __func__); 4221 } 4222 4223 return rval; 4224 } 4225 4226 int 4227 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb) 4228 { 4229 int rval; 4230 mbx_cmd_t mc; 4231 mbx_cmd_t *mcp = &mc; 4232 4233 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9, 4234 "Entered %s.\n", __func__); 4235 4236 mcp->mb[0] = MBC_IDC_ACK; 4237 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4238 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4239 mcp->in_mb = MBX_0; 4240 mcp->tov = MBX_TOV_SECONDS; 4241 mcp->flags = 0; 4242 rval = qla2x00_mailbox_command(vha, mcp); 4243 4244 if (rval != QLA_SUCCESS) { 4245 ql_dbg(ql_dbg_mbx, vha, 0x10da, 4246 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4247 } else { 4248 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db, 4249 "Done %s.\n", __func__); 4250 } 4251 4252 return rval; 4253 } 4254 4255 int 4256 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size) 4257 { 4258 int rval; 4259 mbx_cmd_t mc; 4260 mbx_cmd_t *mcp = &mc; 4261 4262 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc, 4263 "Entered %s.\n", __func__); 4264 4265 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4266 !IS_QLA27XX(vha->hw)) 4267 return QLA_FUNCTION_FAILED; 4268 4269 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4270 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE; 4271 mcp->out_mb = MBX_1|MBX_0; 4272 mcp->in_mb = MBX_1|MBX_0; 4273 mcp->tov = MBX_TOV_SECONDS; 4274 mcp->flags = 0; 4275 rval = qla2x00_mailbox_command(vha, mcp); 4276 4277 if (rval != QLA_SUCCESS) { 4278 ql_dbg(ql_dbg_mbx, vha, 0x10dd, 4279 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4280 rval, mcp->mb[0], mcp->mb[1]); 4281 } else { 4282 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de, 4283 "Done %s.\n", __func__); 4284 *sector_size = mcp->mb[1]; 4285 } 4286 4287 return rval; 4288 } 4289 4290 int 4291 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable) 4292 { 4293 int rval; 4294 mbx_cmd_t mc; 4295 mbx_cmd_t *mcp = &mc; 4296 4297 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4298 !IS_QLA27XX(vha->hw)) 4299 return QLA_FUNCTION_FAILED; 4300 4301 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df, 4302 "Entered %s.\n", __func__); 4303 4304 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4305 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE : 4306 FAC_OPT_CMD_WRITE_PROTECT; 4307 mcp->out_mb = MBX_1|MBX_0; 4308 mcp->in_mb = MBX_1|MBX_0; 4309 mcp->tov = MBX_TOV_SECONDS; 4310 mcp->flags = 0; 4311 rval = qla2x00_mailbox_command(vha, mcp); 4312 4313 if (rval != QLA_SUCCESS) { 4314 ql_dbg(ql_dbg_mbx, vha, 0x10e0, 4315 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4316 rval, mcp->mb[0], mcp->mb[1]); 4317 } else { 4318 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1, 4319 "Done %s.\n", __func__); 4320 } 4321 4322 return rval; 4323 } 4324 4325 int 4326 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish) 4327 { 4328 int rval; 4329 mbx_cmd_t mc; 4330 mbx_cmd_t *mcp = &mc; 4331 4332 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4333 !IS_QLA27XX(vha->hw)) 4334 return QLA_FUNCTION_FAILED; 4335 4336 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2, 4337 "Entered %s.\n", __func__); 4338 4339 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4340 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR; 4341 mcp->mb[2] = LSW(start); 4342 mcp->mb[3] = MSW(start); 4343 mcp->mb[4] = LSW(finish); 4344 mcp->mb[5] = MSW(finish); 4345 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4346 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4347 mcp->tov = MBX_TOV_SECONDS; 4348 mcp->flags = 0; 4349 rval = qla2x00_mailbox_command(vha, mcp); 4350 4351 if (rval != QLA_SUCCESS) { 4352 ql_dbg(ql_dbg_mbx, vha, 0x10e3, 4353 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4354 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4355 } else { 4356 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4, 4357 "Done %s.\n", __func__); 4358 } 4359 4360 return rval; 4361 } 4362 4363 int 4364 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha) 4365 { 4366 int rval = 0; 4367 mbx_cmd_t mc; 4368 mbx_cmd_t *mcp = &mc; 4369 4370 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5, 4371 "Entered %s.\n", __func__); 4372 4373 mcp->mb[0] = MBC_RESTART_MPI_FW; 4374 mcp->out_mb = MBX_0; 4375 mcp->in_mb = MBX_0|MBX_1; 4376 mcp->tov = MBX_TOV_SECONDS; 4377 mcp->flags = 0; 4378 rval = qla2x00_mailbox_command(vha, mcp); 4379 4380 if (rval != QLA_SUCCESS) { 4381 ql_dbg(ql_dbg_mbx, vha, 0x10e6, 4382 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4383 rval, mcp->mb[0], mcp->mb[1]); 4384 } else { 4385 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7, 4386 "Done %s.\n", __func__); 4387 } 4388 4389 return rval; 4390 } 4391 4392 int 4393 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4394 { 4395 int rval; 4396 mbx_cmd_t mc; 4397 mbx_cmd_t *mcp = &mc; 4398 int i; 4399 int len; 4400 uint16_t *str; 4401 struct qla_hw_data *ha = vha->hw; 4402 4403 if (!IS_P3P_TYPE(ha)) 4404 return QLA_FUNCTION_FAILED; 4405 4406 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b, 4407 "Entered %s.\n", __func__); 4408 4409 str = (void *)version; 4410 len = strlen(version); 4411 4412 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4413 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8; 4414 mcp->out_mb = MBX_1|MBX_0; 4415 for (i = 4; i < 16 && len; i++, str++, len -= 2) { 4416 mcp->mb[i] = cpu_to_le16p(str); 4417 mcp->out_mb |= 1<<i; 4418 } 4419 for (; i < 16; i++) { 4420 mcp->mb[i] = 0; 4421 mcp->out_mb |= 1<<i; 4422 } 4423 mcp->in_mb = MBX_1|MBX_0; 4424 mcp->tov = MBX_TOV_SECONDS; 4425 mcp->flags = 0; 4426 rval = qla2x00_mailbox_command(vha, mcp); 4427 4428 if (rval != QLA_SUCCESS) { 4429 ql_dbg(ql_dbg_mbx, vha, 0x117c, 4430 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4431 } else { 4432 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d, 4433 "Done %s.\n", __func__); 4434 } 4435 4436 return rval; 4437 } 4438 4439 int 4440 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4441 { 4442 int rval; 4443 mbx_cmd_t mc; 4444 mbx_cmd_t *mcp = &mc; 4445 int len; 4446 uint16_t dwlen; 4447 uint8_t *str; 4448 dma_addr_t str_dma; 4449 struct qla_hw_data *ha = vha->hw; 4450 4451 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) || 4452 IS_P3P_TYPE(ha)) 4453 return QLA_FUNCTION_FAILED; 4454 4455 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e, 4456 "Entered %s.\n", __func__); 4457 4458 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma); 4459 if (!str) { 4460 ql_log(ql_log_warn, vha, 0x117f, 4461 "Failed to allocate driver version param.\n"); 4462 return QLA_MEMORY_ALLOC_FAILED; 4463 } 4464 4465 memcpy(str, "\x7\x3\x11\x0", 4); 4466 dwlen = str[0]; 4467 len = dwlen * 4 - 4; 4468 memset(str + 4, 0, len); 4469 if (len > strlen(version)) 4470 len = strlen(version); 4471 memcpy(str + 4, version, len); 4472 4473 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4474 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen; 4475 mcp->mb[2] = MSW(LSD(str_dma)); 4476 mcp->mb[3] = LSW(LSD(str_dma)); 4477 mcp->mb[6] = MSW(MSD(str_dma)); 4478 mcp->mb[7] = LSW(MSD(str_dma)); 4479 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4480 mcp->in_mb = MBX_1|MBX_0; 4481 mcp->tov = MBX_TOV_SECONDS; 4482 mcp->flags = 0; 4483 rval = qla2x00_mailbox_command(vha, mcp); 4484 4485 if (rval != QLA_SUCCESS) { 4486 ql_dbg(ql_dbg_mbx, vha, 0x1180, 4487 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4488 } else { 4489 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181, 4490 "Done %s.\n", __func__); 4491 } 4492 4493 dma_pool_free(ha->s_dma_pool, str, str_dma); 4494 4495 return rval; 4496 } 4497 4498 static int 4499 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp) 4500 { 4501 int rval; 4502 mbx_cmd_t mc; 4503 mbx_cmd_t *mcp = &mc; 4504 4505 if (!IS_FWI2_CAPABLE(vha->hw)) 4506 return QLA_FUNCTION_FAILED; 4507 4508 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159, 4509 "Entered %s.\n", __func__); 4510 4511 mcp->mb[0] = MBC_GET_RNID_PARAMS; 4512 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8; 4513 mcp->out_mb = MBX_1|MBX_0; 4514 mcp->in_mb = MBX_1|MBX_0; 4515 mcp->tov = MBX_TOV_SECONDS; 4516 mcp->flags = 0; 4517 rval = qla2x00_mailbox_command(vha, mcp); 4518 *temp = mcp->mb[1]; 4519 4520 if (rval != QLA_SUCCESS) { 4521 ql_dbg(ql_dbg_mbx, vha, 0x115a, 4522 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4523 } else { 4524 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b, 4525 "Done %s.\n", __func__); 4526 } 4527 4528 return rval; 4529 } 4530 4531 int 4532 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4533 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4534 { 4535 int rval; 4536 mbx_cmd_t mc; 4537 mbx_cmd_t *mcp = &mc; 4538 struct qla_hw_data *ha = vha->hw; 4539 4540 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8, 4541 "Entered %s.\n", __func__); 4542 4543 if (!IS_FWI2_CAPABLE(ha)) 4544 return QLA_FUNCTION_FAILED; 4545 4546 if (len == 1) 4547 opt |= BIT_0; 4548 4549 mcp->mb[0] = MBC_READ_SFP; 4550 mcp->mb[1] = dev; 4551 mcp->mb[2] = MSW(sfp_dma); 4552 mcp->mb[3] = LSW(sfp_dma); 4553 mcp->mb[6] = MSW(MSD(sfp_dma)); 4554 mcp->mb[7] = LSW(MSD(sfp_dma)); 4555 mcp->mb[8] = len; 4556 mcp->mb[9] = off; 4557 mcp->mb[10] = opt; 4558 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4559 mcp->in_mb = MBX_1|MBX_0; 4560 mcp->tov = MBX_TOV_SECONDS; 4561 mcp->flags = 0; 4562 rval = qla2x00_mailbox_command(vha, mcp); 4563 4564 if (opt & BIT_0) 4565 *sfp = mcp->mb[1]; 4566 4567 if (rval != QLA_SUCCESS) { 4568 ql_dbg(ql_dbg_mbx, vha, 0x10e9, 4569 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4570 } else { 4571 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea, 4572 "Done %s.\n", __func__); 4573 } 4574 4575 return rval; 4576 } 4577 4578 int 4579 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4580 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4581 { 4582 int rval; 4583 mbx_cmd_t mc; 4584 mbx_cmd_t *mcp = &mc; 4585 struct qla_hw_data *ha = vha->hw; 4586 4587 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb, 4588 "Entered %s.\n", __func__); 4589 4590 if (!IS_FWI2_CAPABLE(ha)) 4591 return QLA_FUNCTION_FAILED; 4592 4593 if (len == 1) 4594 opt |= BIT_0; 4595 4596 if (opt & BIT_0) 4597 len = *sfp; 4598 4599 mcp->mb[0] = MBC_WRITE_SFP; 4600 mcp->mb[1] = dev; 4601 mcp->mb[2] = MSW(sfp_dma); 4602 mcp->mb[3] = LSW(sfp_dma); 4603 mcp->mb[6] = MSW(MSD(sfp_dma)); 4604 mcp->mb[7] = LSW(MSD(sfp_dma)); 4605 mcp->mb[8] = len; 4606 mcp->mb[9] = off; 4607 mcp->mb[10] = opt; 4608 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4609 mcp->in_mb = MBX_1|MBX_0; 4610 mcp->tov = MBX_TOV_SECONDS; 4611 mcp->flags = 0; 4612 rval = qla2x00_mailbox_command(vha, mcp); 4613 4614 if (rval != QLA_SUCCESS) { 4615 ql_dbg(ql_dbg_mbx, vha, 0x10ec, 4616 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4617 } else { 4618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed, 4619 "Done %s.\n", __func__); 4620 } 4621 4622 return rval; 4623 } 4624 4625 int 4626 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma, 4627 uint16_t size_in_bytes, uint16_t *actual_size) 4628 { 4629 int rval; 4630 mbx_cmd_t mc; 4631 mbx_cmd_t *mcp = &mc; 4632 4633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee, 4634 "Entered %s.\n", __func__); 4635 4636 if (!IS_CNA_CAPABLE(vha->hw)) 4637 return QLA_FUNCTION_FAILED; 4638 4639 mcp->mb[0] = MBC_GET_XGMAC_STATS; 4640 mcp->mb[2] = MSW(stats_dma); 4641 mcp->mb[3] = LSW(stats_dma); 4642 mcp->mb[6] = MSW(MSD(stats_dma)); 4643 mcp->mb[7] = LSW(MSD(stats_dma)); 4644 mcp->mb[8] = size_in_bytes >> 2; 4645 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 4646 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4647 mcp->tov = MBX_TOV_SECONDS; 4648 mcp->flags = 0; 4649 rval = qla2x00_mailbox_command(vha, mcp); 4650 4651 if (rval != QLA_SUCCESS) { 4652 ql_dbg(ql_dbg_mbx, vha, 0x10ef, 4653 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4654 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4655 } else { 4656 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0, 4657 "Done %s.\n", __func__); 4658 4659 4660 *actual_size = mcp->mb[2] << 2; 4661 } 4662 4663 return rval; 4664 } 4665 4666 int 4667 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma, 4668 uint16_t size) 4669 { 4670 int rval; 4671 mbx_cmd_t mc; 4672 mbx_cmd_t *mcp = &mc; 4673 4674 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1, 4675 "Entered %s.\n", __func__); 4676 4677 if (!IS_CNA_CAPABLE(vha->hw)) 4678 return QLA_FUNCTION_FAILED; 4679 4680 mcp->mb[0] = MBC_GET_DCBX_PARAMS; 4681 mcp->mb[1] = 0; 4682 mcp->mb[2] = MSW(tlv_dma); 4683 mcp->mb[3] = LSW(tlv_dma); 4684 mcp->mb[6] = MSW(MSD(tlv_dma)); 4685 mcp->mb[7] = LSW(MSD(tlv_dma)); 4686 mcp->mb[8] = size; 4687 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4688 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4689 mcp->tov = MBX_TOV_SECONDS; 4690 mcp->flags = 0; 4691 rval = qla2x00_mailbox_command(vha, mcp); 4692 4693 if (rval != QLA_SUCCESS) { 4694 ql_dbg(ql_dbg_mbx, vha, 0x10f2, 4695 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4696 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4697 } else { 4698 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3, 4699 "Done %s.\n", __func__); 4700 } 4701 4702 return rval; 4703 } 4704 4705 int 4706 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data) 4707 { 4708 int rval; 4709 mbx_cmd_t mc; 4710 mbx_cmd_t *mcp = &mc; 4711 4712 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4, 4713 "Entered %s.\n", __func__); 4714 4715 if (!IS_FWI2_CAPABLE(vha->hw)) 4716 return QLA_FUNCTION_FAILED; 4717 4718 mcp->mb[0] = MBC_READ_RAM_EXTENDED; 4719 mcp->mb[1] = LSW(risc_addr); 4720 mcp->mb[8] = MSW(risc_addr); 4721 mcp->out_mb = MBX_8|MBX_1|MBX_0; 4722 mcp->in_mb = MBX_3|MBX_2|MBX_0; 4723 mcp->tov = 30; 4724 mcp->flags = 0; 4725 rval = qla2x00_mailbox_command(vha, mcp); 4726 if (rval != QLA_SUCCESS) { 4727 ql_dbg(ql_dbg_mbx, vha, 0x10f5, 4728 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4729 } else { 4730 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6, 4731 "Done %s.\n", __func__); 4732 *data = mcp->mb[3] << 16 | mcp->mb[2]; 4733 } 4734 4735 return rval; 4736 } 4737 4738 int 4739 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4740 uint16_t *mresp) 4741 { 4742 int rval; 4743 mbx_cmd_t mc; 4744 mbx_cmd_t *mcp = &mc; 4745 4746 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7, 4747 "Entered %s.\n", __func__); 4748 4749 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4750 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK; 4751 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing 4752 4753 /* transfer count */ 4754 mcp->mb[10] = LSW(mreq->transfer_size); 4755 mcp->mb[11] = MSW(mreq->transfer_size); 4756 4757 /* send data address */ 4758 mcp->mb[14] = LSW(mreq->send_dma); 4759 mcp->mb[15] = MSW(mreq->send_dma); 4760 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4761 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4762 4763 /* receive data address */ 4764 mcp->mb[16] = LSW(mreq->rcv_dma); 4765 mcp->mb[17] = MSW(mreq->rcv_dma); 4766 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4767 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4768 4769 /* Iteration count */ 4770 mcp->mb[18] = LSW(mreq->iteration_count); 4771 mcp->mb[19] = MSW(mreq->iteration_count); 4772 4773 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| 4774 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4775 if (IS_CNA_CAPABLE(vha->hw)) 4776 mcp->out_mb |= MBX_2; 4777 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; 4778 4779 mcp->buf_size = mreq->transfer_size; 4780 mcp->tov = MBX_TOV_SECONDS; 4781 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4782 4783 rval = qla2x00_mailbox_command(vha, mcp); 4784 4785 if (rval != QLA_SUCCESS) { 4786 ql_dbg(ql_dbg_mbx, vha, 0x10f8, 4787 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x " 4788 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], 4789 mcp->mb[3], mcp->mb[18], mcp->mb[19]); 4790 } else { 4791 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9, 4792 "Done %s.\n", __func__); 4793 } 4794 4795 /* Copy mailbox information */ 4796 memcpy( mresp, mcp->mb, 64); 4797 return rval; 4798 } 4799 4800 int 4801 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4802 uint16_t *mresp) 4803 { 4804 int rval; 4805 mbx_cmd_t mc; 4806 mbx_cmd_t *mcp = &mc; 4807 struct qla_hw_data *ha = vha->hw; 4808 4809 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa, 4810 "Entered %s.\n", __func__); 4811 4812 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4813 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; 4814 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */ 4815 if (IS_CNA_CAPABLE(ha)) { 4816 mcp->mb[1] |= BIT_15; 4817 mcp->mb[2] = vha->fcoe_fcf_idx; 4818 } 4819 mcp->mb[16] = LSW(mreq->rcv_dma); 4820 mcp->mb[17] = MSW(mreq->rcv_dma); 4821 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4822 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4823 4824 mcp->mb[10] = LSW(mreq->transfer_size); 4825 4826 mcp->mb[14] = LSW(mreq->send_dma); 4827 mcp->mb[15] = MSW(mreq->send_dma); 4828 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4829 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4830 4831 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| 4832 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4833 if (IS_CNA_CAPABLE(ha)) 4834 mcp->out_mb |= MBX_2; 4835 4836 mcp->in_mb = MBX_0; 4837 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || 4838 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4839 mcp->in_mb |= MBX_1; 4840 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4841 mcp->in_mb |= MBX_3; 4842 4843 mcp->tov = MBX_TOV_SECONDS; 4844 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4845 mcp->buf_size = mreq->transfer_size; 4846 4847 rval = qla2x00_mailbox_command(vha, mcp); 4848 4849 if (rval != QLA_SUCCESS) { 4850 ql_dbg(ql_dbg_mbx, vha, 0x10fb, 4851 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4852 rval, mcp->mb[0], mcp->mb[1]); 4853 } else { 4854 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc, 4855 "Done %s.\n", __func__); 4856 } 4857 4858 /* Copy mailbox information */ 4859 memcpy(mresp, mcp->mb, 64); 4860 return rval; 4861 } 4862 4863 int 4864 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic) 4865 { 4866 int rval; 4867 mbx_cmd_t mc; 4868 mbx_cmd_t *mcp = &mc; 4869 4870 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd, 4871 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic); 4872 4873 mcp->mb[0] = MBC_ISP84XX_RESET; 4874 mcp->mb[1] = enable_diagnostic; 4875 mcp->out_mb = MBX_1|MBX_0; 4876 mcp->in_mb = MBX_1|MBX_0; 4877 mcp->tov = MBX_TOV_SECONDS; 4878 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4879 rval = qla2x00_mailbox_command(vha, mcp); 4880 4881 if (rval != QLA_SUCCESS) 4882 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval); 4883 else 4884 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff, 4885 "Done %s.\n", __func__); 4886 4887 return rval; 4888 } 4889 4890 int 4891 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data) 4892 { 4893 int rval; 4894 mbx_cmd_t mc; 4895 mbx_cmd_t *mcp = &mc; 4896 4897 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100, 4898 "Entered %s.\n", __func__); 4899 4900 if (!IS_FWI2_CAPABLE(vha->hw)) 4901 return QLA_FUNCTION_FAILED; 4902 4903 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED; 4904 mcp->mb[1] = LSW(risc_addr); 4905 mcp->mb[2] = LSW(data); 4906 mcp->mb[3] = MSW(data); 4907 mcp->mb[8] = MSW(risc_addr); 4908 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0; 4909 mcp->in_mb = MBX_0; 4910 mcp->tov = 30; 4911 mcp->flags = 0; 4912 rval = qla2x00_mailbox_command(vha, mcp); 4913 if (rval != QLA_SUCCESS) { 4914 ql_dbg(ql_dbg_mbx, vha, 0x1101, 4915 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4916 } else { 4917 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102, 4918 "Done %s.\n", __func__); 4919 } 4920 4921 return rval; 4922 } 4923 4924 int 4925 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb) 4926 { 4927 int rval; 4928 uint32_t stat, timer; 4929 uint16_t mb0 = 0; 4930 struct qla_hw_data *ha = vha->hw; 4931 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 4932 4933 rval = QLA_SUCCESS; 4934 4935 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103, 4936 "Entered %s.\n", __func__); 4937 4938 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 4939 4940 /* Write the MBC data to the registers */ 4941 WRT_REG_WORD(®->mailbox0, MBC_WRITE_MPI_REGISTER); 4942 WRT_REG_WORD(®->mailbox1, mb[0]); 4943 WRT_REG_WORD(®->mailbox2, mb[1]); 4944 WRT_REG_WORD(®->mailbox3, mb[2]); 4945 WRT_REG_WORD(®->mailbox4, mb[3]); 4946 4947 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 4948 4949 /* Poll for MBC interrupt */ 4950 for (timer = 6000000; timer; timer--) { 4951 /* Check for pending interrupts. */ 4952 stat = RD_REG_DWORD(®->host_status); 4953 if (stat & HSRX_RISC_INT) { 4954 stat &= 0xff; 4955 4956 if (stat == 0x1 || stat == 0x2 || 4957 stat == 0x10 || stat == 0x11) { 4958 set_bit(MBX_INTERRUPT, 4959 &ha->mbx_cmd_flags); 4960 mb0 = RD_REG_WORD(®->mailbox0); 4961 WRT_REG_DWORD(®->hccr, 4962 HCCRX_CLR_RISC_INT); 4963 RD_REG_DWORD(®->hccr); 4964 break; 4965 } 4966 } 4967 udelay(5); 4968 } 4969 4970 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) 4971 rval = mb0 & MBS_MASK; 4972 else 4973 rval = QLA_FUNCTION_FAILED; 4974 4975 if (rval != QLA_SUCCESS) { 4976 ql_dbg(ql_dbg_mbx, vha, 0x1104, 4977 "Failed=%x mb[0]=%x.\n", rval, mb[0]); 4978 } else { 4979 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105, 4980 "Done %s.\n", __func__); 4981 } 4982 4983 return rval; 4984 } 4985 4986 int 4987 qla2x00_get_data_rate(scsi_qla_host_t *vha) 4988 { 4989 int rval; 4990 mbx_cmd_t mc; 4991 mbx_cmd_t *mcp = &mc; 4992 struct qla_hw_data *ha = vha->hw; 4993 4994 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106, 4995 "Entered %s.\n", __func__); 4996 4997 if (!IS_FWI2_CAPABLE(ha)) 4998 return QLA_FUNCTION_FAILED; 4999 5000 mcp->mb[0] = MBC_DATA_RATE; 5001 mcp->mb[1] = 0; 5002 mcp->out_mb = MBX_1|MBX_0; 5003 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5004 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 5005 mcp->in_mb |= MBX_3; 5006 mcp->tov = MBX_TOV_SECONDS; 5007 mcp->flags = 0; 5008 rval = qla2x00_mailbox_command(vha, mcp); 5009 if (rval != QLA_SUCCESS) { 5010 ql_dbg(ql_dbg_mbx, vha, 0x1107, 5011 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5012 } else { 5013 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108, 5014 "Done %s.\n", __func__); 5015 if (mcp->mb[1] != 0x7) 5016 ha->link_data_rate = mcp->mb[1]; 5017 } 5018 5019 return rval; 5020 } 5021 5022 int 5023 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb) 5024 { 5025 int rval; 5026 mbx_cmd_t mc; 5027 mbx_cmd_t *mcp = &mc; 5028 struct qla_hw_data *ha = vha->hw; 5029 5030 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109, 5031 "Entered %s.\n", __func__); 5032 5033 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) && 5034 !IS_QLA27XX(ha)) 5035 return QLA_FUNCTION_FAILED; 5036 mcp->mb[0] = MBC_GET_PORT_CONFIG; 5037 mcp->out_mb = MBX_0; 5038 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5039 mcp->tov = MBX_TOV_SECONDS; 5040 mcp->flags = 0; 5041 5042 rval = qla2x00_mailbox_command(vha, mcp); 5043 5044 if (rval != QLA_SUCCESS) { 5045 ql_dbg(ql_dbg_mbx, vha, 0x110a, 5046 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5047 } else { 5048 /* Copy all bits to preserve original value */ 5049 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4); 5050 5051 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b, 5052 "Done %s.\n", __func__); 5053 } 5054 return rval; 5055 } 5056 5057 int 5058 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb) 5059 { 5060 int rval; 5061 mbx_cmd_t mc; 5062 mbx_cmd_t *mcp = &mc; 5063 5064 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c, 5065 "Entered %s.\n", __func__); 5066 5067 mcp->mb[0] = MBC_SET_PORT_CONFIG; 5068 /* Copy all bits to preserve original setting */ 5069 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4); 5070 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5071 mcp->in_mb = MBX_0; 5072 mcp->tov = MBX_TOV_SECONDS; 5073 mcp->flags = 0; 5074 rval = qla2x00_mailbox_command(vha, mcp); 5075 5076 if (rval != QLA_SUCCESS) { 5077 ql_dbg(ql_dbg_mbx, vha, 0x110d, 5078 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5079 } else 5080 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e, 5081 "Done %s.\n", __func__); 5082 5083 return rval; 5084 } 5085 5086 5087 int 5088 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority, 5089 uint16_t *mb) 5090 { 5091 int rval; 5092 mbx_cmd_t mc; 5093 mbx_cmd_t *mcp = &mc; 5094 struct qla_hw_data *ha = vha->hw; 5095 5096 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f, 5097 "Entered %s.\n", __func__); 5098 5099 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 5100 return QLA_FUNCTION_FAILED; 5101 5102 mcp->mb[0] = MBC_PORT_PARAMS; 5103 mcp->mb[1] = loop_id; 5104 if (ha->flags.fcp_prio_enabled) 5105 mcp->mb[2] = BIT_1; 5106 else 5107 mcp->mb[2] = BIT_2; 5108 mcp->mb[4] = priority & 0xf; 5109 mcp->mb[9] = vha->vp_idx; 5110 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5111 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5112 mcp->tov = 30; 5113 mcp->flags = 0; 5114 rval = qla2x00_mailbox_command(vha, mcp); 5115 if (mb != NULL) { 5116 mb[0] = mcp->mb[0]; 5117 mb[1] = mcp->mb[1]; 5118 mb[3] = mcp->mb[3]; 5119 mb[4] = mcp->mb[4]; 5120 } 5121 5122 if (rval != QLA_SUCCESS) { 5123 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval); 5124 } else { 5125 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc, 5126 "Done %s.\n", __func__); 5127 } 5128 5129 return rval; 5130 } 5131 5132 int 5133 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp) 5134 { 5135 int rval = QLA_FUNCTION_FAILED; 5136 struct qla_hw_data *ha = vha->hw; 5137 uint8_t byte; 5138 5139 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) { 5140 ql_dbg(ql_dbg_mbx, vha, 0x1150, 5141 "Thermal not supported by this card.\n"); 5142 return rval; 5143 } 5144 5145 if (IS_QLA25XX(ha)) { 5146 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 5147 ha->pdev->subsystem_device == 0x0175) { 5148 rval = qla2x00_read_sfp(vha, 0, &byte, 5149 0x98, 0x1, 1, BIT_13|BIT_0); 5150 *temp = byte; 5151 return rval; 5152 } 5153 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 5154 ha->pdev->subsystem_device == 0x338e) { 5155 rval = qla2x00_read_sfp(vha, 0, &byte, 5156 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0); 5157 *temp = byte; 5158 return rval; 5159 } 5160 ql_dbg(ql_dbg_mbx, vha, 0x10c9, 5161 "Thermal not supported by this card.\n"); 5162 return rval; 5163 } 5164 5165 if (IS_QLA82XX(ha)) { 5166 *temp = qla82xx_read_temperature(vha); 5167 rval = QLA_SUCCESS; 5168 return rval; 5169 } else if (IS_QLA8044(ha)) { 5170 *temp = qla8044_read_temperature(vha); 5171 rval = QLA_SUCCESS; 5172 return rval; 5173 } 5174 5175 rval = qla2x00_read_asic_temperature(vha, temp); 5176 return rval; 5177 } 5178 5179 int 5180 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha) 5181 { 5182 int rval; 5183 struct qla_hw_data *ha = vha->hw; 5184 mbx_cmd_t mc; 5185 mbx_cmd_t *mcp = &mc; 5186 5187 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017, 5188 "Entered %s.\n", __func__); 5189 5190 if (!IS_FWI2_CAPABLE(ha)) 5191 return QLA_FUNCTION_FAILED; 5192 5193 memset(mcp, 0, sizeof(mbx_cmd_t)); 5194 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 5195 mcp->mb[1] = 1; 5196 5197 mcp->out_mb = MBX_1|MBX_0; 5198 mcp->in_mb = MBX_0; 5199 mcp->tov = 30; 5200 mcp->flags = 0; 5201 5202 rval = qla2x00_mailbox_command(vha, mcp); 5203 if (rval != QLA_SUCCESS) { 5204 ql_dbg(ql_dbg_mbx, vha, 0x1016, 5205 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5206 } else { 5207 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e, 5208 "Done %s.\n", __func__); 5209 } 5210 5211 return rval; 5212 } 5213 5214 int 5215 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha) 5216 { 5217 int rval; 5218 struct qla_hw_data *ha = vha->hw; 5219 mbx_cmd_t mc; 5220 mbx_cmd_t *mcp = &mc; 5221 5222 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d, 5223 "Entered %s.\n", __func__); 5224 5225 if (!IS_P3P_TYPE(ha)) 5226 return QLA_FUNCTION_FAILED; 5227 5228 memset(mcp, 0, sizeof(mbx_cmd_t)); 5229 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 5230 mcp->mb[1] = 0; 5231 5232 mcp->out_mb = MBX_1|MBX_0; 5233 mcp->in_mb = MBX_0; 5234 mcp->tov = 30; 5235 mcp->flags = 0; 5236 5237 rval = qla2x00_mailbox_command(vha, mcp); 5238 if (rval != QLA_SUCCESS) { 5239 ql_dbg(ql_dbg_mbx, vha, 0x100c, 5240 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5241 } else { 5242 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b, 5243 "Done %s.\n", __func__); 5244 } 5245 5246 return rval; 5247 } 5248 5249 int 5250 qla82xx_md_get_template_size(scsi_qla_host_t *vha) 5251 { 5252 struct qla_hw_data *ha = vha->hw; 5253 mbx_cmd_t mc; 5254 mbx_cmd_t *mcp = &mc; 5255 int rval = QLA_FUNCTION_FAILED; 5256 5257 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f, 5258 "Entered %s.\n", __func__); 5259 5260 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5261 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5262 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5263 mcp->mb[2] = LSW(RQST_TMPLT_SIZE); 5264 mcp->mb[3] = MSW(RQST_TMPLT_SIZE); 5265 5266 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5267 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| 5268 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5269 5270 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5271 mcp->tov = MBX_TOV_SECONDS; 5272 rval = qla2x00_mailbox_command(vha, mcp); 5273 5274 /* Always copy back return mailbox values. */ 5275 if (rval != QLA_SUCCESS) { 5276 ql_dbg(ql_dbg_mbx, vha, 0x1120, 5277 "mailbox command FAILED=0x%x, subcode=%x.\n", 5278 (mcp->mb[1] << 16) | mcp->mb[0], 5279 (mcp->mb[3] << 16) | mcp->mb[2]); 5280 } else { 5281 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121, 5282 "Done %s.\n", __func__); 5283 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]); 5284 if (!ha->md_template_size) { 5285 ql_dbg(ql_dbg_mbx, vha, 0x1122, 5286 "Null template size obtained.\n"); 5287 rval = QLA_FUNCTION_FAILED; 5288 } 5289 } 5290 return rval; 5291 } 5292 5293 int 5294 qla82xx_md_get_template(scsi_qla_host_t *vha) 5295 { 5296 struct qla_hw_data *ha = vha->hw; 5297 mbx_cmd_t mc; 5298 mbx_cmd_t *mcp = &mc; 5299 int rval = QLA_FUNCTION_FAILED; 5300 5301 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123, 5302 "Entered %s.\n", __func__); 5303 5304 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5305 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5306 if (!ha->md_tmplt_hdr) { 5307 ql_log(ql_log_warn, vha, 0x1124, 5308 "Unable to allocate memory for Minidump template.\n"); 5309 return rval; 5310 } 5311 5312 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5313 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5314 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5315 mcp->mb[2] = LSW(RQST_TMPLT); 5316 mcp->mb[3] = MSW(RQST_TMPLT); 5317 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma)); 5318 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma)); 5319 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma)); 5320 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma)); 5321 mcp->mb[8] = LSW(ha->md_template_size); 5322 mcp->mb[9] = MSW(ha->md_template_size); 5323 5324 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5325 mcp->tov = MBX_TOV_SECONDS; 5326 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5327 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5328 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5329 rval = qla2x00_mailbox_command(vha, mcp); 5330 5331 if (rval != QLA_SUCCESS) { 5332 ql_dbg(ql_dbg_mbx, vha, 0x1125, 5333 "mailbox command FAILED=0x%x, subcode=%x.\n", 5334 ((mcp->mb[1] << 16) | mcp->mb[0]), 5335 ((mcp->mb[3] << 16) | mcp->mb[2])); 5336 } else 5337 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126, 5338 "Done %s.\n", __func__); 5339 return rval; 5340 } 5341 5342 int 5343 qla8044_md_get_template(scsi_qla_host_t *vha) 5344 { 5345 struct qla_hw_data *ha = vha->hw; 5346 mbx_cmd_t mc; 5347 mbx_cmd_t *mcp = &mc; 5348 int rval = QLA_FUNCTION_FAILED; 5349 int offset = 0, size = MINIDUMP_SIZE_36K; 5350 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f, 5351 "Entered %s.\n", __func__); 5352 5353 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5354 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5355 if (!ha->md_tmplt_hdr) { 5356 ql_log(ql_log_warn, vha, 0xb11b, 5357 "Unable to allocate memory for Minidump template.\n"); 5358 return rval; 5359 } 5360 5361 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5362 while (offset < ha->md_template_size) { 5363 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5364 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5365 mcp->mb[2] = LSW(RQST_TMPLT); 5366 mcp->mb[3] = MSW(RQST_TMPLT); 5367 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5368 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5369 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5370 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5371 mcp->mb[8] = LSW(size); 5372 mcp->mb[9] = MSW(size); 5373 mcp->mb[10] = offset & 0x0000FFFF; 5374 mcp->mb[11] = offset & 0xFFFF0000; 5375 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5376 mcp->tov = MBX_TOV_SECONDS; 5377 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5378 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5379 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5380 rval = qla2x00_mailbox_command(vha, mcp); 5381 5382 if (rval != QLA_SUCCESS) { 5383 ql_dbg(ql_dbg_mbx, vha, 0xb11c, 5384 "mailbox command FAILED=0x%x, subcode=%x.\n", 5385 ((mcp->mb[1] << 16) | mcp->mb[0]), 5386 ((mcp->mb[3] << 16) | mcp->mb[2])); 5387 return rval; 5388 } else 5389 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d, 5390 "Done %s.\n", __func__); 5391 offset = offset + size; 5392 } 5393 return rval; 5394 } 5395 5396 int 5397 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5398 { 5399 int rval; 5400 struct qla_hw_data *ha = vha->hw; 5401 mbx_cmd_t mc; 5402 mbx_cmd_t *mcp = &mc; 5403 5404 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5405 return QLA_FUNCTION_FAILED; 5406 5407 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133, 5408 "Entered %s.\n", __func__); 5409 5410 memset(mcp, 0, sizeof(mbx_cmd_t)); 5411 mcp->mb[0] = MBC_SET_LED_CONFIG; 5412 mcp->mb[1] = led_cfg[0]; 5413 mcp->mb[2] = led_cfg[1]; 5414 if (IS_QLA8031(ha)) { 5415 mcp->mb[3] = led_cfg[2]; 5416 mcp->mb[4] = led_cfg[3]; 5417 mcp->mb[5] = led_cfg[4]; 5418 mcp->mb[6] = led_cfg[5]; 5419 } 5420 5421 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5422 if (IS_QLA8031(ha)) 5423 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5424 mcp->in_mb = MBX_0; 5425 mcp->tov = 30; 5426 mcp->flags = 0; 5427 5428 rval = qla2x00_mailbox_command(vha, mcp); 5429 if (rval != QLA_SUCCESS) { 5430 ql_dbg(ql_dbg_mbx, vha, 0x1134, 5431 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5432 } else { 5433 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135, 5434 "Done %s.\n", __func__); 5435 } 5436 5437 return rval; 5438 } 5439 5440 int 5441 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5442 { 5443 int rval; 5444 struct qla_hw_data *ha = vha->hw; 5445 mbx_cmd_t mc; 5446 mbx_cmd_t *mcp = &mc; 5447 5448 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5449 return QLA_FUNCTION_FAILED; 5450 5451 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136, 5452 "Entered %s.\n", __func__); 5453 5454 memset(mcp, 0, sizeof(mbx_cmd_t)); 5455 mcp->mb[0] = MBC_GET_LED_CONFIG; 5456 5457 mcp->out_mb = MBX_0; 5458 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5459 if (IS_QLA8031(ha)) 5460 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5461 mcp->tov = 30; 5462 mcp->flags = 0; 5463 5464 rval = qla2x00_mailbox_command(vha, mcp); 5465 if (rval != QLA_SUCCESS) { 5466 ql_dbg(ql_dbg_mbx, vha, 0x1137, 5467 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5468 } else { 5469 led_cfg[0] = mcp->mb[1]; 5470 led_cfg[1] = mcp->mb[2]; 5471 if (IS_QLA8031(ha)) { 5472 led_cfg[2] = mcp->mb[3]; 5473 led_cfg[3] = mcp->mb[4]; 5474 led_cfg[4] = mcp->mb[5]; 5475 led_cfg[5] = mcp->mb[6]; 5476 } 5477 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138, 5478 "Done %s.\n", __func__); 5479 } 5480 5481 return rval; 5482 } 5483 5484 int 5485 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable) 5486 { 5487 int rval; 5488 struct qla_hw_data *ha = vha->hw; 5489 mbx_cmd_t mc; 5490 mbx_cmd_t *mcp = &mc; 5491 5492 if (!IS_P3P_TYPE(ha)) 5493 return QLA_FUNCTION_FAILED; 5494 5495 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127, 5496 "Entered %s.\n", __func__); 5497 5498 memset(mcp, 0, sizeof(mbx_cmd_t)); 5499 mcp->mb[0] = MBC_SET_LED_CONFIG; 5500 if (enable) 5501 mcp->mb[7] = 0xE; 5502 else 5503 mcp->mb[7] = 0xD; 5504 5505 mcp->out_mb = MBX_7|MBX_0; 5506 mcp->in_mb = MBX_0; 5507 mcp->tov = MBX_TOV_SECONDS; 5508 mcp->flags = 0; 5509 5510 rval = qla2x00_mailbox_command(vha, mcp); 5511 if (rval != QLA_SUCCESS) { 5512 ql_dbg(ql_dbg_mbx, vha, 0x1128, 5513 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5514 } else { 5515 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129, 5516 "Done %s.\n", __func__); 5517 } 5518 5519 return rval; 5520 } 5521 5522 int 5523 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data) 5524 { 5525 int rval; 5526 struct qla_hw_data *ha = vha->hw; 5527 mbx_cmd_t mc; 5528 mbx_cmd_t *mcp = &mc; 5529 5530 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5531 return QLA_FUNCTION_FAILED; 5532 5533 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130, 5534 "Entered %s.\n", __func__); 5535 5536 mcp->mb[0] = MBC_WRITE_REMOTE_REG; 5537 mcp->mb[1] = LSW(reg); 5538 mcp->mb[2] = MSW(reg); 5539 mcp->mb[3] = LSW(data); 5540 mcp->mb[4] = MSW(data); 5541 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5542 5543 mcp->in_mb = MBX_1|MBX_0; 5544 mcp->tov = MBX_TOV_SECONDS; 5545 mcp->flags = 0; 5546 rval = qla2x00_mailbox_command(vha, mcp); 5547 5548 if (rval != QLA_SUCCESS) { 5549 ql_dbg(ql_dbg_mbx, vha, 0x1131, 5550 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5551 } else { 5552 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132, 5553 "Done %s.\n", __func__); 5554 } 5555 5556 return rval; 5557 } 5558 5559 int 5560 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport) 5561 { 5562 int rval; 5563 struct qla_hw_data *ha = vha->hw; 5564 mbx_cmd_t mc; 5565 mbx_cmd_t *mcp = &mc; 5566 5567 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 5568 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b, 5569 "Implicit LOGO Unsupported.\n"); 5570 return QLA_FUNCTION_FAILED; 5571 } 5572 5573 5574 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c, 5575 "Entering %s.\n", __func__); 5576 5577 /* Perform Implicit LOGO. */ 5578 mcp->mb[0] = MBC_PORT_LOGOUT; 5579 mcp->mb[1] = fcport->loop_id; 5580 mcp->mb[10] = BIT_15; 5581 mcp->out_mb = MBX_10|MBX_1|MBX_0; 5582 mcp->in_mb = MBX_0; 5583 mcp->tov = MBX_TOV_SECONDS; 5584 mcp->flags = 0; 5585 rval = qla2x00_mailbox_command(vha, mcp); 5586 if (rval != QLA_SUCCESS) 5587 ql_dbg(ql_dbg_mbx, vha, 0x113d, 5588 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5589 else 5590 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e, 5591 "Done %s.\n", __func__); 5592 5593 return rval; 5594 } 5595 5596 int 5597 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data) 5598 { 5599 int rval; 5600 mbx_cmd_t mc; 5601 mbx_cmd_t *mcp = &mc; 5602 struct qla_hw_data *ha = vha->hw; 5603 unsigned long retry_max_time = jiffies + (2 * HZ); 5604 5605 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5606 return QLA_FUNCTION_FAILED; 5607 5608 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__); 5609 5610 retry_rd_reg: 5611 mcp->mb[0] = MBC_READ_REMOTE_REG; 5612 mcp->mb[1] = LSW(reg); 5613 mcp->mb[2] = MSW(reg); 5614 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5615 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5616 mcp->tov = MBX_TOV_SECONDS; 5617 mcp->flags = 0; 5618 rval = qla2x00_mailbox_command(vha, mcp); 5619 5620 if (rval != QLA_SUCCESS) { 5621 ql_dbg(ql_dbg_mbx, vha, 0x114c, 5622 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5623 rval, mcp->mb[0], mcp->mb[1]); 5624 } else { 5625 *data = (mcp->mb[3] | (mcp->mb[4] << 16)); 5626 if (*data == QLA8XXX_BAD_VALUE) { 5627 /* 5628 * During soft-reset CAMRAM register reads might 5629 * return 0xbad0bad0. So retry for MAX of 2 sec 5630 * while reading camram registers. 5631 */ 5632 if (time_after(jiffies, retry_max_time)) { 5633 ql_dbg(ql_dbg_mbx, vha, 0x1141, 5634 "Failure to read CAMRAM register. " 5635 "data=0x%x.\n", *data); 5636 return QLA_FUNCTION_FAILED; 5637 } 5638 msleep(100); 5639 goto retry_rd_reg; 5640 } 5641 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__); 5642 } 5643 5644 return rval; 5645 } 5646 5647 int 5648 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha) 5649 { 5650 int rval; 5651 mbx_cmd_t mc; 5652 mbx_cmd_t *mcp = &mc; 5653 struct qla_hw_data *ha = vha->hw; 5654 5655 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5656 return QLA_FUNCTION_FAILED; 5657 5658 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__); 5659 5660 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE; 5661 mcp->out_mb = MBX_0; 5662 mcp->in_mb = MBX_1|MBX_0; 5663 mcp->tov = MBX_TOV_SECONDS; 5664 mcp->flags = 0; 5665 rval = qla2x00_mailbox_command(vha, mcp); 5666 5667 if (rval != QLA_SUCCESS) { 5668 ql_dbg(ql_dbg_mbx, vha, 0x1144, 5669 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5670 rval, mcp->mb[0], mcp->mb[1]); 5671 ha->isp_ops->fw_dump(vha, 0); 5672 } else { 5673 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__); 5674 } 5675 5676 return rval; 5677 } 5678 5679 int 5680 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options, 5681 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size) 5682 { 5683 int rval; 5684 mbx_cmd_t mc; 5685 mbx_cmd_t *mcp = &mc; 5686 uint8_t subcode = (uint8_t)options; 5687 struct qla_hw_data *ha = vha->hw; 5688 5689 if (!IS_QLA8031(ha)) 5690 return QLA_FUNCTION_FAILED; 5691 5692 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__); 5693 5694 mcp->mb[0] = MBC_SET_ACCESS_CONTROL; 5695 mcp->mb[1] = options; 5696 mcp->out_mb = MBX_1|MBX_0; 5697 if (subcode & BIT_2) { 5698 mcp->mb[2] = LSW(start_addr); 5699 mcp->mb[3] = MSW(start_addr); 5700 mcp->mb[4] = LSW(end_addr); 5701 mcp->mb[5] = MSW(end_addr); 5702 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2; 5703 } 5704 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5705 if (!(subcode & (BIT_2 | BIT_5))) 5706 mcp->in_mb |= MBX_4|MBX_3; 5707 mcp->tov = MBX_TOV_SECONDS; 5708 mcp->flags = 0; 5709 rval = qla2x00_mailbox_command(vha, mcp); 5710 5711 if (rval != QLA_SUCCESS) { 5712 ql_dbg(ql_dbg_mbx, vha, 0x1147, 5713 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n", 5714 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], 5715 mcp->mb[4]); 5716 ha->isp_ops->fw_dump(vha, 0); 5717 } else { 5718 if (subcode & BIT_5) 5719 *sector_size = mcp->mb[1]; 5720 else if (subcode & (BIT_6 | BIT_7)) { 5721 ql_dbg(ql_dbg_mbx, vha, 0x1148, 5722 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5723 } else if (subcode & (BIT_3 | BIT_4)) { 5724 ql_dbg(ql_dbg_mbx, vha, 0x1149, 5725 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5726 } 5727 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__); 5728 } 5729 5730 return rval; 5731 } 5732 5733 int 5734 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 5735 uint32_t size) 5736 { 5737 int rval; 5738 mbx_cmd_t mc; 5739 mbx_cmd_t *mcp = &mc; 5740 5741 if (!IS_MCTP_CAPABLE(vha->hw)) 5742 return QLA_FUNCTION_FAILED; 5743 5744 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f, 5745 "Entered %s.\n", __func__); 5746 5747 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 5748 mcp->mb[1] = LSW(addr); 5749 mcp->mb[2] = MSW(req_dma); 5750 mcp->mb[3] = LSW(req_dma); 5751 mcp->mb[4] = MSW(size); 5752 mcp->mb[5] = LSW(size); 5753 mcp->mb[6] = MSW(MSD(req_dma)); 5754 mcp->mb[7] = LSW(MSD(req_dma)); 5755 mcp->mb[8] = MSW(addr); 5756 /* Setting RAM ID to valid */ 5757 mcp->mb[10] |= BIT_7; 5758 /* For MCTP RAM ID is 0x40 */ 5759 mcp->mb[10] |= 0x40; 5760 5761 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1| 5762 MBX_0; 5763 5764 mcp->in_mb = MBX_0; 5765 mcp->tov = MBX_TOV_SECONDS; 5766 mcp->flags = 0; 5767 rval = qla2x00_mailbox_command(vha, mcp); 5768 5769 if (rval != QLA_SUCCESS) { 5770 ql_dbg(ql_dbg_mbx, vha, 0x114e, 5771 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5772 } else { 5773 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d, 5774 "Done %s.\n", __func__); 5775 } 5776 5777 return rval; 5778 } 5779 5780 int 5781 qla26xx_dport_diagnostics(scsi_qla_host_t *vha, 5782 void *dd_buf, uint size, uint options) 5783 { 5784 int rval; 5785 mbx_cmd_t mc; 5786 mbx_cmd_t *mcp = &mc; 5787 dma_addr_t dd_dma; 5788 5789 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw)) 5790 return QLA_FUNCTION_FAILED; 5791 5792 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192, 5793 "Entered %s.\n", __func__); 5794 5795 dd_dma = dma_map_single(&vha->hw->pdev->dev, 5796 dd_buf, size, DMA_FROM_DEVICE); 5797 if (!dd_dma) { 5798 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n"); 5799 return QLA_MEMORY_ALLOC_FAILED; 5800 } 5801 5802 memset(dd_buf, 0, size); 5803 5804 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS; 5805 mcp->mb[1] = options; 5806 mcp->mb[2] = MSW(LSD(dd_dma)); 5807 mcp->mb[3] = LSW(LSD(dd_dma)); 5808 mcp->mb[6] = MSW(MSD(dd_dma)); 5809 mcp->mb[7] = LSW(MSD(dd_dma)); 5810 mcp->mb[8] = size; 5811 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 5812 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5813 mcp->buf_size = size; 5814 mcp->flags = MBX_DMA_IN; 5815 mcp->tov = MBX_TOV_SECONDS * 4; 5816 rval = qla2x00_mailbox_command(vha, mcp); 5817 5818 if (rval != QLA_SUCCESS) { 5819 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval); 5820 } else { 5821 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196, 5822 "Done %s.\n", __func__); 5823 } 5824 5825 dma_unmap_single(&vha->hw->pdev->dev, dd_dma, 5826 size, DMA_FROM_DEVICE); 5827 5828 return rval; 5829 } 5830