1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_target.h" 9 10 #include <linux/delay.h> 11 #include <linux/gfp.h> 12 13 14 /* 15 * qla2x00_mailbox_command 16 * Issue mailbox command and waits for completion. 17 * 18 * Input: 19 * ha = adapter block pointer. 20 * mcp = driver internal mbx struct pointer. 21 * 22 * Output: 23 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data. 24 * 25 * Returns: 26 * 0 : QLA_SUCCESS = cmd performed success 27 * 1 : QLA_FUNCTION_FAILED (error encountered) 28 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered) 29 * 30 * Context: 31 * Kernel context. 32 */ 33 static int 34 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) 35 { 36 int rval, i; 37 unsigned long flags = 0; 38 device_reg_t *reg; 39 uint8_t abort_active; 40 uint8_t io_lock_on; 41 uint16_t command = 0; 42 uint16_t *iptr; 43 uint16_t __iomem *optr; 44 uint32_t cnt; 45 uint32_t mboxes; 46 uint16_t __iomem *mbx_reg; 47 unsigned long wait_time; 48 struct qla_hw_data *ha = vha->hw; 49 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 50 51 52 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__); 53 54 if (ha->pdev->error_state > pci_channel_io_frozen) { 55 ql_log(ql_log_warn, vha, 0x1001, 56 "error_state is greater than pci_channel_io_frozen, " 57 "exiting.\n"); 58 return QLA_FUNCTION_TIMEOUT; 59 } 60 61 if (vha->device_flags & DFLG_DEV_FAILED) { 62 ql_log(ql_log_warn, vha, 0x1002, 63 "Device in failed state, exiting.\n"); 64 return QLA_FUNCTION_TIMEOUT; 65 } 66 67 reg = ha->iobase; 68 io_lock_on = base_vha->flags.init_done; 69 70 rval = QLA_SUCCESS; 71 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 72 73 74 if (ha->flags.pci_channel_io_perm_failure) { 75 ql_log(ql_log_warn, vha, 0x1003, 76 "Perm failure on EEH timeout MBX, exiting.\n"); 77 return QLA_FUNCTION_TIMEOUT; 78 } 79 80 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 81 /* Setting Link-Down error */ 82 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 83 ql_log(ql_log_warn, vha, 0x1004, 84 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 85 return QLA_FUNCTION_TIMEOUT; 86 } 87 88 /* 89 * Wait for active mailbox commands to finish by waiting at most tov 90 * seconds. This is to serialize actual issuing of mailbox cmds during 91 * non ISP abort time. 92 */ 93 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) { 94 /* Timeout occurred. Return error. */ 95 ql_log(ql_log_warn, vha, 0x1005, 96 "Cmd access timeout, cmd=0x%x, Exiting.\n", 97 mcp->mb[0]); 98 return QLA_FUNCTION_TIMEOUT; 99 } 100 101 ha->flags.mbox_busy = 1; 102 /* Save mailbox command for debug */ 103 ha->mcp = mcp; 104 105 ql_dbg(ql_dbg_mbx, vha, 0x1006, 106 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); 107 108 spin_lock_irqsave(&ha->hardware_lock, flags); 109 110 /* Load mailbox registers. */ 111 if (IS_P3P_TYPE(ha)) 112 optr = (uint16_t __iomem *)®->isp82.mailbox_in[0]; 113 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) 114 optr = (uint16_t __iomem *)®->isp24.mailbox0; 115 else 116 optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); 117 118 iptr = mcp->mb; 119 command = mcp->mb[0]; 120 mboxes = mcp->out_mb; 121 122 ql_dbg(ql_dbg_mbx, vha, 0x1111, 123 "Mailbox registers (OUT):\n"); 124 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 125 if (IS_QLA2200(ha) && cnt == 8) 126 optr = 127 (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 8); 128 if (mboxes & BIT_0) { 129 ql_dbg(ql_dbg_mbx, vha, 0x1112, 130 "mbox[%d]<-0x%04x\n", cnt, *iptr); 131 WRT_REG_WORD(optr, *iptr); 132 } 133 134 mboxes >>= 1; 135 optr++; 136 iptr++; 137 } 138 139 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117, 140 "I/O Address = %p.\n", optr); 141 142 /* Issue set host interrupt command to send cmd out. */ 143 ha->flags.mbox_int = 0; 144 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 145 146 /* Unlock mbx registers and wait for interrupt */ 147 ql_dbg(ql_dbg_mbx, vha, 0x100f, 148 "Going to unlock irq & waiting for interrupts. " 149 "jiffies=%lx.\n", jiffies); 150 151 /* Wait for mbx cmd completion until timeout */ 152 153 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { 154 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 155 156 if (IS_P3P_TYPE(ha)) { 157 if (RD_REG_DWORD(®->isp82.hint) & 158 HINT_MBX_INT_PENDING) { 159 spin_unlock_irqrestore(&ha->hardware_lock, 160 flags); 161 ha->flags.mbox_busy = 0; 162 ql_dbg(ql_dbg_mbx, vha, 0x1010, 163 "Pending mailbox timeout, exiting.\n"); 164 rval = QLA_FUNCTION_TIMEOUT; 165 goto premature_exit; 166 } 167 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 168 } else if (IS_FWI2_CAPABLE(ha)) 169 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 170 else 171 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 172 spin_unlock_irqrestore(&ha->hardware_lock, flags); 173 174 if (!wait_for_completion_timeout(&ha->mbx_intr_comp, 175 mcp->tov * HZ)) { 176 ql_dbg(ql_dbg_mbx, vha, 0x117a, 177 "cmd=%x Timeout.\n", command); 178 spin_lock_irqsave(&ha->hardware_lock, flags); 179 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 180 spin_unlock_irqrestore(&ha->hardware_lock, flags); 181 } 182 } else { 183 ql_dbg(ql_dbg_mbx, vha, 0x1011, 184 "Cmd=%x Polling Mode.\n", command); 185 186 if (IS_P3P_TYPE(ha)) { 187 if (RD_REG_DWORD(®->isp82.hint) & 188 HINT_MBX_INT_PENDING) { 189 spin_unlock_irqrestore(&ha->hardware_lock, 190 flags); 191 ha->flags.mbox_busy = 0; 192 ql_dbg(ql_dbg_mbx, vha, 0x1012, 193 "Pending mailbox timeout, exiting.\n"); 194 rval = QLA_FUNCTION_TIMEOUT; 195 goto premature_exit; 196 } 197 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 198 } else if (IS_FWI2_CAPABLE(ha)) 199 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 200 else 201 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 202 spin_unlock_irqrestore(&ha->hardware_lock, flags); 203 204 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */ 205 while (!ha->flags.mbox_int) { 206 if (time_after(jiffies, wait_time)) 207 break; 208 209 /* Check for pending interrupts. */ 210 qla2x00_poll(ha->rsp_q_map[0]); 211 212 if (!ha->flags.mbox_int && 213 !(IS_QLA2200(ha) && 214 command == MBC_LOAD_RISC_RAM_EXTENDED)) 215 msleep(10); 216 } /* while */ 217 ql_dbg(ql_dbg_mbx, vha, 0x1013, 218 "Waited %d sec.\n", 219 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ)); 220 } 221 222 /* Check whether we timed out */ 223 if (ha->flags.mbox_int) { 224 uint16_t *iptr2; 225 226 ql_dbg(ql_dbg_mbx, vha, 0x1014, 227 "Cmd=%x completed.\n", command); 228 229 /* Got interrupt. Clear the flag. */ 230 ha->flags.mbox_int = 0; 231 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 232 233 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 234 ha->flags.mbox_busy = 0; 235 /* Setting Link-Down error */ 236 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 237 ha->mcp = NULL; 238 rval = QLA_FUNCTION_FAILED; 239 ql_log(ql_log_warn, vha, 0x1015, 240 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 241 goto premature_exit; 242 } 243 244 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) 245 rval = QLA_FUNCTION_FAILED; 246 247 /* Load return mailbox registers. */ 248 iptr2 = mcp->mb; 249 iptr = (uint16_t *)&ha->mailbox_out[0]; 250 mboxes = mcp->in_mb; 251 252 ql_dbg(ql_dbg_mbx, vha, 0x1113, 253 "Mailbox registers (IN):\n"); 254 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 255 if (mboxes & BIT_0) { 256 *iptr2 = *iptr; 257 ql_dbg(ql_dbg_mbx, vha, 0x1114, 258 "mbox[%d]->0x%04x\n", cnt, *iptr2); 259 } 260 261 mboxes >>= 1; 262 iptr2++; 263 iptr++; 264 } 265 } else { 266 267 uint16_t mb0; 268 uint32_t ictrl; 269 270 if (IS_FWI2_CAPABLE(ha)) { 271 mb0 = RD_REG_WORD(®->isp24.mailbox0); 272 ictrl = RD_REG_DWORD(®->isp24.ictrl); 273 } else { 274 mb0 = RD_MAILBOX_REG(ha, ®->isp, 0); 275 ictrl = RD_REG_WORD(®->isp.ictrl); 276 } 277 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119, 278 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx " 279 "mb[0]=0x%x\n", command, ictrl, jiffies, mb0); 280 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019); 281 282 /* 283 * Attempt to capture a firmware dump for further analysis 284 * of the current firmware state. We do not need to do this 285 * if we are intentionally generating a dump. 286 */ 287 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) 288 ha->isp_ops->fw_dump(vha, 0); 289 290 rval = QLA_FUNCTION_TIMEOUT; 291 } 292 293 ha->flags.mbox_busy = 0; 294 295 /* Clean up */ 296 ha->mcp = NULL; 297 298 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) { 299 ql_dbg(ql_dbg_mbx, vha, 0x101a, 300 "Checking for additional resp interrupt.\n"); 301 302 /* polling mode for non isp_abort commands. */ 303 qla2x00_poll(ha->rsp_q_map[0]); 304 } 305 306 if (rval == QLA_FUNCTION_TIMEOUT && 307 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) { 308 if (!io_lock_on || (mcp->flags & IOCTL_CMD) || 309 ha->flags.eeh_busy) { 310 /* not in dpc. schedule it for dpc to take over. */ 311 ql_dbg(ql_dbg_mbx, vha, 0x101b, 312 "Timeout, schedule isp_abort_needed.\n"); 313 314 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 315 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 316 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 317 if (IS_QLA82XX(ha)) { 318 ql_dbg(ql_dbg_mbx, vha, 0x112a, 319 "disabling pause transmit on port " 320 "0 & 1.\n"); 321 qla82xx_wr_32(ha, 322 QLA82XX_CRB_NIU + 0x98, 323 CRB_NIU_XG_PAUSE_CTL_P0| 324 CRB_NIU_XG_PAUSE_CTL_P1); 325 } 326 ql_log(ql_log_info, base_vha, 0x101c, 327 "Mailbox cmd timeout occurred, cmd=0x%x, " 328 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP " 329 "abort.\n", command, mcp->mb[0], 330 ha->flags.eeh_busy); 331 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 332 qla2xxx_wake_dpc(vha); 333 } 334 } else if (!abort_active) { 335 /* call abort directly since we are in the DPC thread */ 336 ql_dbg(ql_dbg_mbx, vha, 0x101d, 337 "Timeout, calling abort_isp.\n"); 338 339 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 340 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 341 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 342 if (IS_QLA82XX(ha)) { 343 ql_dbg(ql_dbg_mbx, vha, 0x112b, 344 "disabling pause transmit on port " 345 "0 & 1.\n"); 346 qla82xx_wr_32(ha, 347 QLA82XX_CRB_NIU + 0x98, 348 CRB_NIU_XG_PAUSE_CTL_P0| 349 CRB_NIU_XG_PAUSE_CTL_P1); 350 } 351 ql_log(ql_log_info, base_vha, 0x101e, 352 "Mailbox cmd timeout occurred, cmd=0x%x, " 353 "mb[0]=0x%x. Scheduling ISP abort ", 354 command, mcp->mb[0]); 355 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 356 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 357 /* Allow next mbx cmd to come in. */ 358 complete(&ha->mbx_cmd_comp); 359 if (ha->isp_ops->abort_isp(vha)) { 360 /* Failed. retry later. */ 361 set_bit(ISP_ABORT_NEEDED, 362 &vha->dpc_flags); 363 } 364 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 365 ql_dbg(ql_dbg_mbx, vha, 0x101f, 366 "Finished abort_isp.\n"); 367 goto mbx_done; 368 } 369 } 370 } 371 372 premature_exit: 373 /* Allow next mbx cmd to come in. */ 374 complete(&ha->mbx_cmd_comp); 375 376 mbx_done: 377 if (rval) { 378 ql_dbg(ql_dbg_disc, base_vha, 0x1020, 379 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n", 380 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command); 381 382 ql_dbg(ql_dbg_disc, vha, 0x1115, 383 "host status: 0x%x, flags:0x%lx, intr ctrl reg:0x%x, intr status:0x%x\n", 384 RD_REG_DWORD(®->isp24.host_status), 385 ha->fw_dump_cap_flags, 386 RD_REG_DWORD(®->isp24.ictrl), 387 RD_REG_DWORD(®->isp24.istatus)); 388 389 mbx_reg = ®->isp24.mailbox0; 390 for (i = 0; i < 6; i++) 391 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x1116, 392 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); 393 } else { 394 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__); 395 } 396 397 return rval; 398 } 399 400 int 401 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr, 402 uint32_t risc_code_size) 403 { 404 int rval; 405 struct qla_hw_data *ha = vha->hw; 406 mbx_cmd_t mc; 407 mbx_cmd_t *mcp = &mc; 408 409 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022, 410 "Entered %s.\n", __func__); 411 412 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) { 413 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; 414 mcp->mb[8] = MSW(risc_addr); 415 mcp->out_mb = MBX_8|MBX_0; 416 } else { 417 mcp->mb[0] = MBC_LOAD_RISC_RAM; 418 mcp->out_mb = MBX_0; 419 } 420 mcp->mb[1] = LSW(risc_addr); 421 mcp->mb[2] = MSW(req_dma); 422 mcp->mb[3] = LSW(req_dma); 423 mcp->mb[6] = MSW(MSD(req_dma)); 424 mcp->mb[7] = LSW(MSD(req_dma)); 425 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 426 if (IS_FWI2_CAPABLE(ha)) { 427 mcp->mb[4] = MSW(risc_code_size); 428 mcp->mb[5] = LSW(risc_code_size); 429 mcp->out_mb |= MBX_5|MBX_4; 430 } else { 431 mcp->mb[4] = LSW(risc_code_size); 432 mcp->out_mb |= MBX_4; 433 } 434 435 mcp->in_mb = MBX_0; 436 mcp->tov = MBX_TOV_SECONDS; 437 mcp->flags = 0; 438 rval = qla2x00_mailbox_command(vha, mcp); 439 440 if (rval != QLA_SUCCESS) { 441 ql_dbg(ql_dbg_mbx, vha, 0x1023, 442 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 443 } else { 444 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024, 445 "Done %s.\n", __func__); 446 } 447 448 return rval; 449 } 450 451 #define EXTENDED_BB_CREDITS BIT_0 452 /* 453 * qla2x00_execute_fw 454 * Start adapter firmware. 455 * 456 * Input: 457 * ha = adapter block pointer. 458 * TARGET_QUEUE_LOCK must be released. 459 * ADAPTER_STATE_LOCK must be released. 460 * 461 * Returns: 462 * qla2x00 local function return status code. 463 * 464 * Context: 465 * Kernel context. 466 */ 467 int 468 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr) 469 { 470 int rval; 471 struct qla_hw_data *ha = vha->hw; 472 mbx_cmd_t mc; 473 mbx_cmd_t *mcp = &mc; 474 475 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025, 476 "Entered %s.\n", __func__); 477 478 mcp->mb[0] = MBC_EXECUTE_FIRMWARE; 479 mcp->out_mb = MBX_0; 480 mcp->in_mb = MBX_0; 481 if (IS_FWI2_CAPABLE(ha)) { 482 mcp->mb[1] = MSW(risc_addr); 483 mcp->mb[2] = LSW(risc_addr); 484 mcp->mb[3] = 0; 485 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 486 IS_QLA27XX(ha)) { 487 struct nvram_81xx *nv = ha->nvram; 488 mcp->mb[4] = (nv->enhanced_features & 489 EXTENDED_BB_CREDITS); 490 } else 491 mcp->mb[4] = 0; 492 493 if (ha->flags.exlogins_enabled) 494 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN; 495 496 if (ha->flags.exchoffld_enabled) 497 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD; 498 499 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1; 500 mcp->in_mb |= MBX_1; 501 } else { 502 mcp->mb[1] = LSW(risc_addr); 503 mcp->out_mb |= MBX_1; 504 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 505 mcp->mb[2] = 0; 506 mcp->out_mb |= MBX_2; 507 } 508 } 509 510 mcp->tov = MBX_TOV_SECONDS; 511 mcp->flags = 0; 512 rval = qla2x00_mailbox_command(vha, mcp); 513 514 if (rval != QLA_SUCCESS) { 515 ql_dbg(ql_dbg_mbx, vha, 0x1026, 516 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 517 } else { 518 if (IS_FWI2_CAPABLE(ha)) { 519 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027, 520 "Done exchanges=%x.\n", mcp->mb[1]); 521 } else { 522 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028, 523 "Done %s.\n", __func__); 524 } 525 } 526 527 return rval; 528 } 529 530 /* 531 * qla_get_exlogin_status 532 * Get extended login status 533 * uses the memory offload control/status Mailbox 534 * 535 * Input: 536 * ha: adapter state pointer. 537 * fwopt: firmware options 538 * 539 * Returns: 540 * qla2x00 local function status 541 * 542 * Context: 543 * Kernel context. 544 */ 545 #define FETCH_XLOGINS_STAT 0x8 546 int 547 qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz, 548 uint16_t *ex_logins_cnt) 549 { 550 int rval; 551 mbx_cmd_t mc; 552 mbx_cmd_t *mcp = &mc; 553 554 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f, 555 "Entered %s\n", __func__); 556 557 memset(mcp->mb, 0 , sizeof(mcp->mb)); 558 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 559 mcp->mb[1] = FETCH_XLOGINS_STAT; 560 mcp->out_mb = MBX_1|MBX_0; 561 mcp->in_mb = MBX_10|MBX_4|MBX_0; 562 mcp->tov = MBX_TOV_SECONDS; 563 mcp->flags = 0; 564 565 rval = qla2x00_mailbox_command(vha, mcp); 566 if (rval != QLA_SUCCESS) { 567 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval); 568 } else { 569 *buf_sz = mcp->mb[4]; 570 *ex_logins_cnt = mcp->mb[10]; 571 572 ql_log(ql_log_info, vha, 0x1190, 573 "buffer size 0x%x, exchange login count=%d\n", 574 mcp->mb[4], mcp->mb[10]); 575 576 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116, 577 "Done %s.\n", __func__); 578 } 579 580 return rval; 581 } 582 583 /* 584 * qla_set_exlogin_mem_cfg 585 * set extended login memory configuration 586 * Mbx needs to be issues before init_cb is set 587 * 588 * Input: 589 * ha: adapter state pointer. 590 * buffer: buffer pointer 591 * phys_addr: physical address of buffer 592 * size: size of buffer 593 * TARGET_QUEUE_LOCK must be released 594 * ADAPTER_STATE_LOCK must be release 595 * 596 * Returns: 597 * qla2x00 local funxtion status code. 598 * 599 * Context: 600 * Kernel context. 601 */ 602 #define CONFIG_XLOGINS_MEM 0x3 603 int 604 qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr) 605 { 606 int rval; 607 mbx_cmd_t mc; 608 mbx_cmd_t *mcp = &mc; 609 struct qla_hw_data *ha = vha->hw; 610 int configured_count; 611 612 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a, 613 "Entered %s.\n", __func__); 614 615 memset(mcp->mb, 0 , sizeof(mcp->mb)); 616 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 617 mcp->mb[1] = CONFIG_XLOGINS_MEM; 618 mcp->mb[2] = MSW(phys_addr); 619 mcp->mb[3] = LSW(phys_addr); 620 mcp->mb[6] = MSW(MSD(phys_addr)); 621 mcp->mb[7] = LSW(MSD(phys_addr)); 622 mcp->mb[8] = MSW(ha->exlogin_size); 623 mcp->mb[9] = LSW(ha->exlogin_size); 624 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 625 mcp->in_mb = MBX_11|MBX_0; 626 mcp->tov = MBX_TOV_SECONDS; 627 mcp->flags = 0; 628 rval = qla2x00_mailbox_command(vha, mcp); 629 if (rval != QLA_SUCCESS) { 630 /*EMPTY*/ 631 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval); 632 } else { 633 configured_count = mcp->mb[11]; 634 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c, 635 "Done %s.\n", __func__); 636 } 637 638 return rval; 639 } 640 641 /* 642 * qla_get_exchoffld_status 643 * Get exchange offload status 644 * uses the memory offload control/status Mailbox 645 * 646 * Input: 647 * ha: adapter state pointer. 648 * fwopt: firmware options 649 * 650 * Returns: 651 * qla2x00 local function status 652 * 653 * Context: 654 * Kernel context. 655 */ 656 #define FETCH_XCHOFFLD_STAT 0x2 657 int 658 qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz, 659 uint16_t *ex_logins_cnt) 660 { 661 int rval; 662 mbx_cmd_t mc; 663 mbx_cmd_t *mcp = &mc; 664 665 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019, 666 "Entered %s\n", __func__); 667 668 memset(mcp->mb, 0 , sizeof(mcp->mb)); 669 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 670 mcp->mb[1] = FETCH_XCHOFFLD_STAT; 671 mcp->out_mb = MBX_1|MBX_0; 672 mcp->in_mb = MBX_10|MBX_4|MBX_0; 673 mcp->tov = MBX_TOV_SECONDS; 674 mcp->flags = 0; 675 676 rval = qla2x00_mailbox_command(vha, mcp); 677 if (rval != QLA_SUCCESS) { 678 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval); 679 } else { 680 *buf_sz = mcp->mb[4]; 681 *ex_logins_cnt = mcp->mb[10]; 682 683 ql_log(ql_log_info, vha, 0x118e, 684 "buffer size 0x%x, exchange offload count=%d\n", 685 mcp->mb[4], mcp->mb[10]); 686 687 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156, 688 "Done %s.\n", __func__); 689 } 690 691 return rval; 692 } 693 694 /* 695 * qla_set_exchoffld_mem_cfg 696 * Set exchange offload memory configuration 697 * Mbx needs to be issues before init_cb is set 698 * 699 * Input: 700 * ha: adapter state pointer. 701 * buffer: buffer pointer 702 * phys_addr: physical address of buffer 703 * size: size of buffer 704 * TARGET_QUEUE_LOCK must be released 705 * ADAPTER_STATE_LOCK must be release 706 * 707 * Returns: 708 * qla2x00 local funxtion status code. 709 * 710 * Context: 711 * Kernel context. 712 */ 713 #define CONFIG_XCHOFFLD_MEM 0x3 714 int 715 qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr) 716 { 717 int rval; 718 mbx_cmd_t mc; 719 mbx_cmd_t *mcp = &mc; 720 struct qla_hw_data *ha = vha->hw; 721 722 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157, 723 "Entered %s.\n", __func__); 724 725 memset(mcp->mb, 0 , sizeof(mcp->mb)); 726 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 727 mcp->mb[1] = CONFIG_XCHOFFLD_MEM; 728 mcp->mb[2] = MSW(phys_addr); 729 mcp->mb[3] = LSW(phys_addr); 730 mcp->mb[6] = MSW(MSD(phys_addr)); 731 mcp->mb[7] = LSW(MSD(phys_addr)); 732 mcp->mb[8] = MSW(ha->exlogin_size); 733 mcp->mb[9] = LSW(ha->exlogin_size); 734 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 735 mcp->in_mb = MBX_11|MBX_0; 736 mcp->tov = MBX_TOV_SECONDS; 737 mcp->flags = 0; 738 rval = qla2x00_mailbox_command(vha, mcp); 739 if (rval != QLA_SUCCESS) { 740 /*EMPTY*/ 741 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval); 742 } else { 743 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192, 744 "Done %s.\n", __func__); 745 } 746 747 return rval; 748 } 749 750 /* 751 * qla2x00_get_fw_version 752 * Get firmware version. 753 * 754 * Input: 755 * ha: adapter state pointer. 756 * major: pointer for major number. 757 * minor: pointer for minor number. 758 * subminor: pointer for subminor number. 759 * 760 * Returns: 761 * qla2x00 local function return status code. 762 * 763 * Context: 764 * Kernel context. 765 */ 766 int 767 qla2x00_get_fw_version(scsi_qla_host_t *vha) 768 { 769 int rval; 770 mbx_cmd_t mc; 771 mbx_cmd_t *mcp = &mc; 772 struct qla_hw_data *ha = vha->hw; 773 774 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029, 775 "Entered %s.\n", __func__); 776 777 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION; 778 mcp->out_mb = MBX_0; 779 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 780 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha)) 781 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8; 782 if (IS_FWI2_CAPABLE(ha)) 783 mcp->in_mb |= MBX_17|MBX_16|MBX_15; 784 if (IS_QLA27XX(ha)) 785 mcp->in_mb |= MBX_23 | MBX_22 | MBX_21 | MBX_20 | MBX_19 | 786 MBX_18 | MBX_14 | MBX_13 | MBX_11 | MBX_10 | MBX_9 | MBX_8; 787 788 mcp->flags = 0; 789 mcp->tov = MBX_TOV_SECONDS; 790 rval = qla2x00_mailbox_command(vha, mcp); 791 if (rval != QLA_SUCCESS) 792 goto failed; 793 794 /* Return mailbox data. */ 795 ha->fw_major_version = mcp->mb[1]; 796 ha->fw_minor_version = mcp->mb[2]; 797 ha->fw_subminor_version = mcp->mb[3]; 798 ha->fw_attributes = mcp->mb[6]; 799 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw)) 800 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */ 801 else 802 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4]; 803 804 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) { 805 ha->mpi_version[0] = mcp->mb[10] & 0xff; 806 ha->mpi_version[1] = mcp->mb[11] >> 8; 807 ha->mpi_version[2] = mcp->mb[11] & 0xff; 808 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13]; 809 ha->phy_version[0] = mcp->mb[8] & 0xff; 810 ha->phy_version[1] = mcp->mb[9] >> 8; 811 ha->phy_version[2] = mcp->mb[9] & 0xff; 812 } 813 814 if (IS_FWI2_CAPABLE(ha)) { 815 ha->fw_attributes_h = mcp->mb[15]; 816 ha->fw_attributes_ext[0] = mcp->mb[16]; 817 ha->fw_attributes_ext[1] = mcp->mb[17]; 818 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139, 819 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n", 820 __func__, mcp->mb[15], mcp->mb[6]); 821 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f, 822 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n", 823 __func__, mcp->mb[17], mcp->mb[16]); 824 825 if (ha->fw_attributes_h & 0x4) 826 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d, 827 "%s: Firmware supports Extended Login 0x%x\n", 828 __func__, ha->fw_attributes_h); 829 830 if (ha->fw_attributes_h & 0x8) 831 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191, 832 "%s: Firmware supports Exchange Offload 0x%x\n", 833 __func__, ha->fw_attributes_h); 834 } 835 836 if (IS_QLA27XX(ha)) { 837 ha->mpi_version[0] = mcp->mb[10] & 0xff; 838 ha->mpi_version[1] = mcp->mb[11] >> 8; 839 ha->mpi_version[2] = mcp->mb[11] & 0xff; 840 ha->pep_version[0] = mcp->mb[13] & 0xff; 841 ha->pep_version[1] = mcp->mb[14] >> 8; 842 ha->pep_version[2] = mcp->mb[14] & 0xff; 843 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18]; 844 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20]; 845 } 846 847 failed: 848 if (rval != QLA_SUCCESS) { 849 /*EMPTY*/ 850 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval); 851 } else { 852 /*EMPTY*/ 853 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b, 854 "Done %s.\n", __func__); 855 } 856 return rval; 857 } 858 859 /* 860 * qla2x00_get_fw_options 861 * Set firmware options. 862 * 863 * Input: 864 * ha = adapter block pointer. 865 * fwopt = pointer for firmware options. 866 * 867 * Returns: 868 * qla2x00 local function return status code. 869 * 870 * Context: 871 * Kernel context. 872 */ 873 int 874 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 875 { 876 int rval; 877 mbx_cmd_t mc; 878 mbx_cmd_t *mcp = &mc; 879 880 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c, 881 "Entered %s.\n", __func__); 882 883 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION; 884 mcp->out_mb = MBX_0; 885 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 886 mcp->tov = MBX_TOV_SECONDS; 887 mcp->flags = 0; 888 rval = qla2x00_mailbox_command(vha, mcp); 889 890 if (rval != QLA_SUCCESS) { 891 /*EMPTY*/ 892 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval); 893 } else { 894 fwopts[0] = mcp->mb[0]; 895 fwopts[1] = mcp->mb[1]; 896 fwopts[2] = mcp->mb[2]; 897 fwopts[3] = mcp->mb[3]; 898 899 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e, 900 "Done %s.\n", __func__); 901 } 902 903 return rval; 904 } 905 906 907 /* 908 * qla2x00_set_fw_options 909 * Set firmware options. 910 * 911 * Input: 912 * ha = adapter block pointer. 913 * fwopt = pointer for firmware options. 914 * 915 * Returns: 916 * qla2x00 local function return status code. 917 * 918 * Context: 919 * Kernel context. 920 */ 921 int 922 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 923 { 924 int rval; 925 mbx_cmd_t mc; 926 mbx_cmd_t *mcp = &mc; 927 928 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f, 929 "Entered %s.\n", __func__); 930 931 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION; 932 mcp->mb[1] = fwopts[1]; 933 mcp->mb[2] = fwopts[2]; 934 mcp->mb[3] = fwopts[3]; 935 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 936 mcp->in_mb = MBX_0; 937 if (IS_FWI2_CAPABLE(vha->hw)) { 938 mcp->in_mb |= MBX_1; 939 } else { 940 mcp->mb[10] = fwopts[10]; 941 mcp->mb[11] = fwopts[11]; 942 mcp->mb[12] = 0; /* Undocumented, but used */ 943 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 944 } 945 mcp->tov = MBX_TOV_SECONDS; 946 mcp->flags = 0; 947 rval = qla2x00_mailbox_command(vha, mcp); 948 949 fwopts[0] = mcp->mb[0]; 950 951 if (rval != QLA_SUCCESS) { 952 /*EMPTY*/ 953 ql_dbg(ql_dbg_mbx, vha, 0x1030, 954 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]); 955 } else { 956 /*EMPTY*/ 957 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031, 958 "Done %s.\n", __func__); 959 } 960 961 return rval; 962 } 963 964 /* 965 * qla2x00_mbx_reg_test 966 * Mailbox register wrap test. 967 * 968 * Input: 969 * ha = adapter block pointer. 970 * TARGET_QUEUE_LOCK must be released. 971 * ADAPTER_STATE_LOCK must be released. 972 * 973 * Returns: 974 * qla2x00 local function return status code. 975 * 976 * Context: 977 * Kernel context. 978 */ 979 int 980 qla2x00_mbx_reg_test(scsi_qla_host_t *vha) 981 { 982 int rval; 983 mbx_cmd_t mc; 984 mbx_cmd_t *mcp = &mc; 985 986 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032, 987 "Entered %s.\n", __func__); 988 989 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; 990 mcp->mb[1] = 0xAAAA; 991 mcp->mb[2] = 0x5555; 992 mcp->mb[3] = 0xAA55; 993 mcp->mb[4] = 0x55AA; 994 mcp->mb[5] = 0xA5A5; 995 mcp->mb[6] = 0x5A5A; 996 mcp->mb[7] = 0x2525; 997 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 998 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 999 mcp->tov = MBX_TOV_SECONDS; 1000 mcp->flags = 0; 1001 rval = qla2x00_mailbox_command(vha, mcp); 1002 1003 if (rval == QLA_SUCCESS) { 1004 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 || 1005 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA) 1006 rval = QLA_FUNCTION_FAILED; 1007 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A || 1008 mcp->mb[7] != 0x2525) 1009 rval = QLA_FUNCTION_FAILED; 1010 } 1011 1012 if (rval != QLA_SUCCESS) { 1013 /*EMPTY*/ 1014 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval); 1015 } else { 1016 /*EMPTY*/ 1017 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034, 1018 "Done %s.\n", __func__); 1019 } 1020 1021 return rval; 1022 } 1023 1024 /* 1025 * qla2x00_verify_checksum 1026 * Verify firmware checksum. 1027 * 1028 * Input: 1029 * ha = adapter block pointer. 1030 * TARGET_QUEUE_LOCK must be released. 1031 * ADAPTER_STATE_LOCK must be released. 1032 * 1033 * Returns: 1034 * qla2x00 local function return status code. 1035 * 1036 * Context: 1037 * Kernel context. 1038 */ 1039 int 1040 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr) 1041 { 1042 int rval; 1043 mbx_cmd_t mc; 1044 mbx_cmd_t *mcp = &mc; 1045 1046 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035, 1047 "Entered %s.\n", __func__); 1048 1049 mcp->mb[0] = MBC_VERIFY_CHECKSUM; 1050 mcp->out_mb = MBX_0; 1051 mcp->in_mb = MBX_0; 1052 if (IS_FWI2_CAPABLE(vha->hw)) { 1053 mcp->mb[1] = MSW(risc_addr); 1054 mcp->mb[2] = LSW(risc_addr); 1055 mcp->out_mb |= MBX_2|MBX_1; 1056 mcp->in_mb |= MBX_2|MBX_1; 1057 } else { 1058 mcp->mb[1] = LSW(risc_addr); 1059 mcp->out_mb |= MBX_1; 1060 mcp->in_mb |= MBX_1; 1061 } 1062 1063 mcp->tov = MBX_TOV_SECONDS; 1064 mcp->flags = 0; 1065 rval = qla2x00_mailbox_command(vha, mcp); 1066 1067 if (rval != QLA_SUCCESS) { 1068 ql_dbg(ql_dbg_mbx, vha, 0x1036, 1069 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ? 1070 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]); 1071 } else { 1072 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037, 1073 "Done %s.\n", __func__); 1074 } 1075 1076 return rval; 1077 } 1078 1079 /* 1080 * qla2x00_issue_iocb 1081 * Issue IOCB using mailbox command 1082 * 1083 * Input: 1084 * ha = adapter state pointer. 1085 * buffer = buffer pointer. 1086 * phys_addr = physical address of buffer. 1087 * size = size of buffer. 1088 * TARGET_QUEUE_LOCK must be released. 1089 * ADAPTER_STATE_LOCK must be released. 1090 * 1091 * Returns: 1092 * qla2x00 local function return status code. 1093 * 1094 * Context: 1095 * Kernel context. 1096 */ 1097 int 1098 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer, 1099 dma_addr_t phys_addr, size_t size, uint32_t tov) 1100 { 1101 int rval; 1102 mbx_cmd_t mc; 1103 mbx_cmd_t *mcp = &mc; 1104 1105 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038, 1106 "Entered %s.\n", __func__); 1107 1108 mcp->mb[0] = MBC_IOCB_COMMAND_A64; 1109 mcp->mb[1] = 0; 1110 mcp->mb[2] = MSW(phys_addr); 1111 mcp->mb[3] = LSW(phys_addr); 1112 mcp->mb[6] = MSW(MSD(phys_addr)); 1113 mcp->mb[7] = LSW(MSD(phys_addr)); 1114 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1115 mcp->in_mb = MBX_2|MBX_0; 1116 mcp->tov = tov; 1117 mcp->flags = 0; 1118 rval = qla2x00_mailbox_command(vha, mcp); 1119 1120 if (rval != QLA_SUCCESS) { 1121 /*EMPTY*/ 1122 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval); 1123 } else { 1124 sts_entry_t *sts_entry = (sts_entry_t *) buffer; 1125 1126 /* Mask reserved bits. */ 1127 sts_entry->entry_status &= 1128 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK; 1129 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a, 1130 "Done %s.\n", __func__); 1131 } 1132 1133 return rval; 1134 } 1135 1136 int 1137 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr, 1138 size_t size) 1139 { 1140 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size, 1141 MBX_TOV_SECONDS); 1142 } 1143 1144 /* 1145 * qla2x00_abort_command 1146 * Abort command aborts a specified IOCB. 1147 * 1148 * Input: 1149 * ha = adapter block pointer. 1150 * sp = SB structure pointer. 1151 * 1152 * Returns: 1153 * qla2x00 local function return status code. 1154 * 1155 * Context: 1156 * Kernel context. 1157 */ 1158 int 1159 qla2x00_abort_command(srb_t *sp) 1160 { 1161 unsigned long flags = 0; 1162 int rval; 1163 uint32_t handle = 0; 1164 mbx_cmd_t mc; 1165 mbx_cmd_t *mcp = &mc; 1166 fc_port_t *fcport = sp->fcport; 1167 scsi_qla_host_t *vha = fcport->vha; 1168 struct qla_hw_data *ha = vha->hw; 1169 struct req_que *req = vha->req; 1170 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1171 1172 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b, 1173 "Entered %s.\n", __func__); 1174 1175 spin_lock_irqsave(&ha->hardware_lock, flags); 1176 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 1177 if (req->outstanding_cmds[handle] == sp) 1178 break; 1179 } 1180 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1181 1182 if (handle == req->num_outstanding_cmds) { 1183 /* command not found */ 1184 return QLA_FUNCTION_FAILED; 1185 } 1186 1187 mcp->mb[0] = MBC_ABORT_COMMAND; 1188 if (HAS_EXTENDED_IDS(ha)) 1189 mcp->mb[1] = fcport->loop_id; 1190 else 1191 mcp->mb[1] = fcport->loop_id << 8; 1192 mcp->mb[2] = (uint16_t)handle; 1193 mcp->mb[3] = (uint16_t)(handle >> 16); 1194 mcp->mb[6] = (uint16_t)cmd->device->lun; 1195 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1196 mcp->in_mb = MBX_0; 1197 mcp->tov = MBX_TOV_SECONDS; 1198 mcp->flags = 0; 1199 rval = qla2x00_mailbox_command(vha, mcp); 1200 1201 if (rval != QLA_SUCCESS) { 1202 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval); 1203 } else { 1204 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d, 1205 "Done %s.\n", __func__); 1206 } 1207 1208 return rval; 1209 } 1210 1211 int 1212 qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag) 1213 { 1214 int rval, rval2; 1215 mbx_cmd_t mc; 1216 mbx_cmd_t *mcp = &mc; 1217 scsi_qla_host_t *vha; 1218 struct req_que *req; 1219 struct rsp_que *rsp; 1220 1221 l = l; 1222 vha = fcport->vha; 1223 1224 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e, 1225 "Entered %s.\n", __func__); 1226 1227 req = vha->hw->req_q_map[0]; 1228 rsp = req->rsp; 1229 mcp->mb[0] = MBC_ABORT_TARGET; 1230 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0; 1231 if (HAS_EXTENDED_IDS(vha->hw)) { 1232 mcp->mb[1] = fcport->loop_id; 1233 mcp->mb[10] = 0; 1234 mcp->out_mb |= MBX_10; 1235 } else { 1236 mcp->mb[1] = fcport->loop_id << 8; 1237 } 1238 mcp->mb[2] = vha->hw->loop_reset_delay; 1239 mcp->mb[9] = vha->vp_idx; 1240 1241 mcp->in_mb = MBX_0; 1242 mcp->tov = MBX_TOV_SECONDS; 1243 mcp->flags = 0; 1244 rval = qla2x00_mailbox_command(vha, mcp); 1245 if (rval != QLA_SUCCESS) { 1246 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f, 1247 "Failed=%x.\n", rval); 1248 } 1249 1250 /* Issue marker IOCB. */ 1251 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0, 1252 MK_SYNC_ID); 1253 if (rval2 != QLA_SUCCESS) { 1254 ql_dbg(ql_dbg_mbx, vha, 0x1040, 1255 "Failed to issue marker IOCB (%x).\n", rval2); 1256 } else { 1257 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041, 1258 "Done %s.\n", __func__); 1259 } 1260 1261 return rval; 1262 } 1263 1264 int 1265 qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 1266 { 1267 int rval, rval2; 1268 mbx_cmd_t mc; 1269 mbx_cmd_t *mcp = &mc; 1270 scsi_qla_host_t *vha; 1271 struct req_que *req; 1272 struct rsp_que *rsp; 1273 1274 vha = fcport->vha; 1275 1276 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042, 1277 "Entered %s.\n", __func__); 1278 1279 req = vha->hw->req_q_map[0]; 1280 rsp = req->rsp; 1281 mcp->mb[0] = MBC_LUN_RESET; 1282 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 1283 if (HAS_EXTENDED_IDS(vha->hw)) 1284 mcp->mb[1] = fcport->loop_id; 1285 else 1286 mcp->mb[1] = fcport->loop_id << 8; 1287 mcp->mb[2] = (u32)l; 1288 mcp->mb[3] = 0; 1289 mcp->mb[9] = vha->vp_idx; 1290 1291 mcp->in_mb = MBX_0; 1292 mcp->tov = MBX_TOV_SECONDS; 1293 mcp->flags = 0; 1294 rval = qla2x00_mailbox_command(vha, mcp); 1295 if (rval != QLA_SUCCESS) { 1296 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval); 1297 } 1298 1299 /* Issue marker IOCB. */ 1300 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 1301 MK_SYNC_ID_LUN); 1302 if (rval2 != QLA_SUCCESS) { 1303 ql_dbg(ql_dbg_mbx, vha, 0x1044, 1304 "Failed to issue marker IOCB (%x).\n", rval2); 1305 } else { 1306 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045, 1307 "Done %s.\n", __func__); 1308 } 1309 1310 return rval; 1311 } 1312 1313 /* 1314 * qla2x00_get_adapter_id 1315 * Get adapter ID and topology. 1316 * 1317 * Input: 1318 * ha = adapter block pointer. 1319 * id = pointer for loop ID. 1320 * al_pa = pointer for AL_PA. 1321 * area = pointer for area. 1322 * domain = pointer for domain. 1323 * top = pointer for topology. 1324 * TARGET_QUEUE_LOCK must be released. 1325 * ADAPTER_STATE_LOCK must be released. 1326 * 1327 * Returns: 1328 * qla2x00 local function return status code. 1329 * 1330 * Context: 1331 * Kernel context. 1332 */ 1333 int 1334 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa, 1335 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap) 1336 { 1337 int rval; 1338 mbx_cmd_t mc; 1339 mbx_cmd_t *mcp = &mc; 1340 1341 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046, 1342 "Entered %s.\n", __func__); 1343 1344 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID; 1345 mcp->mb[9] = vha->vp_idx; 1346 mcp->out_mb = MBX_9|MBX_0; 1347 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1348 if (IS_CNA_CAPABLE(vha->hw)) 1349 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; 1350 if (IS_FWI2_CAPABLE(vha->hw)) 1351 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16; 1352 mcp->tov = MBX_TOV_SECONDS; 1353 mcp->flags = 0; 1354 rval = qla2x00_mailbox_command(vha, mcp); 1355 if (mcp->mb[0] == MBS_COMMAND_ERROR) 1356 rval = QLA_COMMAND_ERROR; 1357 else if (mcp->mb[0] == MBS_INVALID_COMMAND) 1358 rval = QLA_INVALID_COMMAND; 1359 1360 /* Return data. */ 1361 *id = mcp->mb[1]; 1362 *al_pa = LSB(mcp->mb[2]); 1363 *area = MSB(mcp->mb[2]); 1364 *domain = LSB(mcp->mb[3]); 1365 *top = mcp->mb[6]; 1366 *sw_cap = mcp->mb[7]; 1367 1368 if (rval != QLA_SUCCESS) { 1369 /*EMPTY*/ 1370 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval); 1371 } else { 1372 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048, 1373 "Done %s.\n", __func__); 1374 1375 if (IS_CNA_CAPABLE(vha->hw)) { 1376 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; 1377 vha->fcoe_fcf_idx = mcp->mb[10]; 1378 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; 1379 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff; 1380 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8; 1381 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff; 1382 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8; 1383 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff; 1384 } 1385 /* If FA-WWN supported */ 1386 if (IS_FAWWN_CAPABLE(vha->hw)) { 1387 if (mcp->mb[7] & BIT_14) { 1388 vha->port_name[0] = MSB(mcp->mb[16]); 1389 vha->port_name[1] = LSB(mcp->mb[16]); 1390 vha->port_name[2] = MSB(mcp->mb[17]); 1391 vha->port_name[3] = LSB(mcp->mb[17]); 1392 vha->port_name[4] = MSB(mcp->mb[18]); 1393 vha->port_name[5] = LSB(mcp->mb[18]); 1394 vha->port_name[6] = MSB(mcp->mb[19]); 1395 vha->port_name[7] = LSB(mcp->mb[19]); 1396 fc_host_port_name(vha->host) = 1397 wwn_to_u64(vha->port_name); 1398 ql_dbg(ql_dbg_mbx, vha, 0x10ca, 1399 "FA-WWN acquired %016llx\n", 1400 wwn_to_u64(vha->port_name)); 1401 } 1402 } 1403 } 1404 1405 return rval; 1406 } 1407 1408 /* 1409 * qla2x00_get_retry_cnt 1410 * Get current firmware login retry count and delay. 1411 * 1412 * Input: 1413 * ha = adapter block pointer. 1414 * retry_cnt = pointer to login retry count. 1415 * tov = pointer to login timeout value. 1416 * 1417 * Returns: 1418 * qla2x00 local function return status code. 1419 * 1420 * Context: 1421 * Kernel context. 1422 */ 1423 int 1424 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov, 1425 uint16_t *r_a_tov) 1426 { 1427 int rval; 1428 uint16_t ratov; 1429 mbx_cmd_t mc; 1430 mbx_cmd_t *mcp = &mc; 1431 1432 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049, 1433 "Entered %s.\n", __func__); 1434 1435 mcp->mb[0] = MBC_GET_RETRY_COUNT; 1436 mcp->out_mb = MBX_0; 1437 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1438 mcp->tov = MBX_TOV_SECONDS; 1439 mcp->flags = 0; 1440 rval = qla2x00_mailbox_command(vha, mcp); 1441 1442 if (rval != QLA_SUCCESS) { 1443 /*EMPTY*/ 1444 ql_dbg(ql_dbg_mbx, vha, 0x104a, 1445 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 1446 } else { 1447 /* Convert returned data and check our values. */ 1448 *r_a_tov = mcp->mb[3] / 2; 1449 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */ 1450 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) { 1451 /* Update to the larger values */ 1452 *retry_cnt = (uint8_t)mcp->mb[1]; 1453 *tov = ratov; 1454 } 1455 1456 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b, 1457 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov); 1458 } 1459 1460 return rval; 1461 } 1462 1463 /* 1464 * qla2x00_init_firmware 1465 * Initialize adapter firmware. 1466 * 1467 * Input: 1468 * ha = adapter block pointer. 1469 * dptr = Initialization control block pointer. 1470 * size = size of initialization control block. 1471 * TARGET_QUEUE_LOCK must be released. 1472 * ADAPTER_STATE_LOCK must be released. 1473 * 1474 * Returns: 1475 * qla2x00 local function return status code. 1476 * 1477 * Context: 1478 * Kernel context. 1479 */ 1480 int 1481 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size) 1482 { 1483 int rval; 1484 mbx_cmd_t mc; 1485 mbx_cmd_t *mcp = &mc; 1486 struct qla_hw_data *ha = vha->hw; 1487 1488 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c, 1489 "Entered %s.\n", __func__); 1490 1491 if (IS_P3P_TYPE(ha) && ql2xdbwr) 1492 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr, 1493 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16))); 1494 1495 if (ha->flags.npiv_supported) 1496 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE; 1497 else 1498 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; 1499 1500 mcp->mb[1] = 0; 1501 mcp->mb[2] = MSW(ha->init_cb_dma); 1502 mcp->mb[3] = LSW(ha->init_cb_dma); 1503 mcp->mb[6] = MSW(MSD(ha->init_cb_dma)); 1504 mcp->mb[7] = LSW(MSD(ha->init_cb_dma)); 1505 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1506 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) { 1507 mcp->mb[1] = BIT_0; 1508 mcp->mb[10] = MSW(ha->ex_init_cb_dma); 1509 mcp->mb[11] = LSW(ha->ex_init_cb_dma); 1510 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma)); 1511 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma)); 1512 mcp->mb[14] = sizeof(*ha->ex_init_cb); 1513 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10; 1514 } 1515 /* 1 and 2 should normally be captured. */ 1516 mcp->in_mb = MBX_2|MBX_1|MBX_0; 1517 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 1518 /* mb3 is additional info about the installed SFP. */ 1519 mcp->in_mb |= MBX_3; 1520 mcp->buf_size = size; 1521 mcp->flags = MBX_DMA_OUT; 1522 mcp->tov = MBX_TOV_SECONDS; 1523 rval = qla2x00_mailbox_command(vha, mcp); 1524 1525 if (rval != QLA_SUCCESS) { 1526 /*EMPTY*/ 1527 ql_dbg(ql_dbg_mbx, vha, 0x104d, 1528 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n", 1529 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]); 1530 } else { 1531 /*EMPTY*/ 1532 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e, 1533 "Done %s.\n", __func__); 1534 } 1535 1536 return rval; 1537 } 1538 1539 /* 1540 * qla2x00_get_node_name_list 1541 * Issue get node name list mailbox command, kmalloc() 1542 * and return the resulting list. Caller must kfree() it! 1543 * 1544 * Input: 1545 * ha = adapter state pointer. 1546 * out_data = resulting list 1547 * out_len = length of the resulting list 1548 * 1549 * Returns: 1550 * qla2x00 local function return status code. 1551 * 1552 * Context: 1553 * Kernel context. 1554 */ 1555 int 1556 qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len) 1557 { 1558 struct qla_hw_data *ha = vha->hw; 1559 struct qla_port_24xx_data *list = NULL; 1560 void *pmap; 1561 mbx_cmd_t mc; 1562 dma_addr_t pmap_dma; 1563 ulong dma_size; 1564 int rval, left; 1565 1566 left = 1; 1567 while (left > 0) { 1568 dma_size = left * sizeof(*list); 1569 pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size, 1570 &pmap_dma, GFP_KERNEL); 1571 if (!pmap) { 1572 ql_log(ql_log_warn, vha, 0x113f, 1573 "%s(%ld): DMA Alloc failed of %ld\n", 1574 __func__, vha->host_no, dma_size); 1575 rval = QLA_MEMORY_ALLOC_FAILED; 1576 goto out; 1577 } 1578 1579 mc.mb[0] = MBC_PORT_NODE_NAME_LIST; 1580 mc.mb[1] = BIT_1 | BIT_3; 1581 mc.mb[2] = MSW(pmap_dma); 1582 mc.mb[3] = LSW(pmap_dma); 1583 mc.mb[6] = MSW(MSD(pmap_dma)); 1584 mc.mb[7] = LSW(MSD(pmap_dma)); 1585 mc.mb[8] = dma_size; 1586 mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8; 1587 mc.in_mb = MBX_0|MBX_1; 1588 mc.tov = 30; 1589 mc.flags = MBX_DMA_IN; 1590 1591 rval = qla2x00_mailbox_command(vha, &mc); 1592 if (rval != QLA_SUCCESS) { 1593 if ((mc.mb[0] == MBS_COMMAND_ERROR) && 1594 (mc.mb[1] == 0xA)) { 1595 left += le16_to_cpu(mc.mb[2]) / 1596 sizeof(struct qla_port_24xx_data); 1597 goto restart; 1598 } 1599 goto out_free; 1600 } 1601 1602 left = 0; 1603 1604 list = kmemdup(pmap, dma_size, GFP_KERNEL); 1605 if (!list) { 1606 ql_log(ql_log_warn, vha, 0x1140, 1607 "%s(%ld): failed to allocate node names list " 1608 "structure.\n", __func__, vha->host_no); 1609 rval = QLA_MEMORY_ALLOC_FAILED; 1610 goto out_free; 1611 } 1612 1613 restart: 1614 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma); 1615 } 1616 1617 *out_data = list; 1618 *out_len = dma_size; 1619 1620 out: 1621 return rval; 1622 1623 out_free: 1624 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma); 1625 return rval; 1626 } 1627 1628 /* 1629 * qla2x00_get_port_database 1630 * Issue normal/enhanced get port database mailbox command 1631 * and copy device name as necessary. 1632 * 1633 * Input: 1634 * ha = adapter state pointer. 1635 * dev = structure pointer. 1636 * opt = enhanced cmd option byte. 1637 * 1638 * Returns: 1639 * qla2x00 local function return status code. 1640 * 1641 * Context: 1642 * Kernel context. 1643 */ 1644 int 1645 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt) 1646 { 1647 int rval; 1648 mbx_cmd_t mc; 1649 mbx_cmd_t *mcp = &mc; 1650 port_database_t *pd; 1651 struct port_database_24xx *pd24; 1652 dma_addr_t pd_dma; 1653 struct qla_hw_data *ha = vha->hw; 1654 1655 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f, 1656 "Entered %s.\n", __func__); 1657 1658 pd24 = NULL; 1659 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1660 if (pd == NULL) { 1661 ql_log(ql_log_warn, vha, 0x1050, 1662 "Failed to allocate port database structure.\n"); 1663 return QLA_MEMORY_ALLOC_FAILED; 1664 } 1665 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE)); 1666 1667 mcp->mb[0] = MBC_GET_PORT_DATABASE; 1668 if (opt != 0 && !IS_FWI2_CAPABLE(ha)) 1669 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE; 1670 mcp->mb[2] = MSW(pd_dma); 1671 mcp->mb[3] = LSW(pd_dma); 1672 mcp->mb[6] = MSW(MSD(pd_dma)); 1673 mcp->mb[7] = LSW(MSD(pd_dma)); 1674 mcp->mb[9] = vha->vp_idx; 1675 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 1676 mcp->in_mb = MBX_0; 1677 if (IS_FWI2_CAPABLE(ha)) { 1678 mcp->mb[1] = fcport->loop_id; 1679 mcp->mb[10] = opt; 1680 mcp->out_mb |= MBX_10|MBX_1; 1681 mcp->in_mb |= MBX_1; 1682 } else if (HAS_EXTENDED_IDS(ha)) { 1683 mcp->mb[1] = fcport->loop_id; 1684 mcp->mb[10] = opt; 1685 mcp->out_mb |= MBX_10|MBX_1; 1686 } else { 1687 mcp->mb[1] = fcport->loop_id << 8 | opt; 1688 mcp->out_mb |= MBX_1; 1689 } 1690 mcp->buf_size = IS_FWI2_CAPABLE(ha) ? 1691 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE; 1692 mcp->flags = MBX_DMA_IN; 1693 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1694 rval = qla2x00_mailbox_command(vha, mcp); 1695 if (rval != QLA_SUCCESS) 1696 goto gpd_error_out; 1697 1698 if (IS_FWI2_CAPABLE(ha)) { 1699 uint64_t zero = 0; 1700 pd24 = (struct port_database_24xx *) pd; 1701 1702 /* Check for logged in state. */ 1703 if (pd24->current_login_state != PDS_PRLI_COMPLETE && 1704 pd24->last_login_state != PDS_PRLI_COMPLETE) { 1705 ql_dbg(ql_dbg_mbx, vha, 0x1051, 1706 "Unable to verify login-state (%x/%x) for " 1707 "loop_id %x.\n", pd24->current_login_state, 1708 pd24->last_login_state, fcport->loop_id); 1709 rval = QLA_FUNCTION_FAILED; 1710 goto gpd_error_out; 1711 } 1712 1713 if (fcport->loop_id == FC_NO_LOOP_ID || 1714 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1715 memcmp(fcport->port_name, pd24->port_name, 8))) { 1716 /* We lost the device mid way. */ 1717 rval = QLA_NOT_LOGGED_IN; 1718 goto gpd_error_out; 1719 } 1720 1721 /* Names are little-endian. */ 1722 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE); 1723 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE); 1724 1725 /* Get port_id of device. */ 1726 fcport->d_id.b.domain = pd24->port_id[0]; 1727 fcport->d_id.b.area = pd24->port_id[1]; 1728 fcport->d_id.b.al_pa = pd24->port_id[2]; 1729 fcport->d_id.b.rsvd_1 = 0; 1730 1731 /* If not target must be initiator or unknown type. */ 1732 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0) 1733 fcport->port_type = FCT_INITIATOR; 1734 else 1735 fcport->port_type = FCT_TARGET; 1736 1737 /* Passback COS information. */ 1738 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ? 1739 FC_COS_CLASS2 : FC_COS_CLASS3; 1740 1741 if (pd24->prli_svc_param_word_3[0] & BIT_7) 1742 fcport->flags |= FCF_CONF_COMP_SUPPORTED; 1743 } else { 1744 uint64_t zero = 0; 1745 1746 /* Check for logged in state. */ 1747 if (pd->master_state != PD_STATE_PORT_LOGGED_IN && 1748 pd->slave_state != PD_STATE_PORT_LOGGED_IN) { 1749 ql_dbg(ql_dbg_mbx, vha, 0x100a, 1750 "Unable to verify login-state (%x/%x) - " 1751 "portid=%02x%02x%02x.\n", pd->master_state, 1752 pd->slave_state, fcport->d_id.b.domain, 1753 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1754 rval = QLA_FUNCTION_FAILED; 1755 goto gpd_error_out; 1756 } 1757 1758 if (fcport->loop_id == FC_NO_LOOP_ID || 1759 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1760 memcmp(fcport->port_name, pd->port_name, 8))) { 1761 /* We lost the device mid way. */ 1762 rval = QLA_NOT_LOGGED_IN; 1763 goto gpd_error_out; 1764 } 1765 1766 /* Names are little-endian. */ 1767 memcpy(fcport->node_name, pd->node_name, WWN_SIZE); 1768 memcpy(fcport->port_name, pd->port_name, WWN_SIZE); 1769 1770 /* Get port_id of device. */ 1771 fcport->d_id.b.domain = pd->port_id[0]; 1772 fcport->d_id.b.area = pd->port_id[3]; 1773 fcport->d_id.b.al_pa = pd->port_id[2]; 1774 fcport->d_id.b.rsvd_1 = 0; 1775 1776 /* If not target must be initiator or unknown type. */ 1777 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 1778 fcport->port_type = FCT_INITIATOR; 1779 else 1780 fcport->port_type = FCT_TARGET; 1781 1782 /* Passback COS information. */ 1783 fcport->supported_classes = (pd->options & BIT_4) ? 1784 FC_COS_CLASS2: FC_COS_CLASS3; 1785 } 1786 1787 gpd_error_out: 1788 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1789 1790 if (rval != QLA_SUCCESS) { 1791 ql_dbg(ql_dbg_mbx, vha, 0x1052, 1792 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval, 1793 mcp->mb[0], mcp->mb[1]); 1794 } else { 1795 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053, 1796 "Done %s.\n", __func__); 1797 } 1798 1799 return rval; 1800 } 1801 1802 /* 1803 * qla2x00_get_firmware_state 1804 * Get adapter firmware state. 1805 * 1806 * Input: 1807 * ha = adapter block pointer. 1808 * dptr = pointer for firmware state. 1809 * TARGET_QUEUE_LOCK must be released. 1810 * ADAPTER_STATE_LOCK must be released. 1811 * 1812 * Returns: 1813 * qla2x00 local function return status code. 1814 * 1815 * Context: 1816 * Kernel context. 1817 */ 1818 int 1819 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states) 1820 { 1821 int rval; 1822 mbx_cmd_t mc; 1823 mbx_cmd_t *mcp = &mc; 1824 1825 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054, 1826 "Entered %s.\n", __func__); 1827 1828 mcp->mb[0] = MBC_GET_FIRMWARE_STATE; 1829 mcp->out_mb = MBX_0; 1830 if (IS_FWI2_CAPABLE(vha->hw)) 1831 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1832 else 1833 mcp->in_mb = MBX_1|MBX_0; 1834 mcp->tov = MBX_TOV_SECONDS; 1835 mcp->flags = 0; 1836 rval = qla2x00_mailbox_command(vha, mcp); 1837 1838 /* Return firmware states. */ 1839 states[0] = mcp->mb[1]; 1840 if (IS_FWI2_CAPABLE(vha->hw)) { 1841 states[1] = mcp->mb[2]; 1842 states[2] = mcp->mb[3]; 1843 states[3] = mcp->mb[4]; 1844 states[4] = mcp->mb[5]; 1845 states[5] = mcp->mb[6]; /* DPORT status */ 1846 } 1847 1848 if (rval != QLA_SUCCESS) { 1849 /*EMPTY*/ 1850 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval); 1851 } else { 1852 /*EMPTY*/ 1853 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056, 1854 "Done %s.\n", __func__); 1855 } 1856 1857 return rval; 1858 } 1859 1860 /* 1861 * qla2x00_get_port_name 1862 * Issue get port name mailbox command. 1863 * Returned name is in big endian format. 1864 * 1865 * Input: 1866 * ha = adapter block pointer. 1867 * loop_id = loop ID of device. 1868 * name = pointer for name. 1869 * TARGET_QUEUE_LOCK must be released. 1870 * ADAPTER_STATE_LOCK must be released. 1871 * 1872 * Returns: 1873 * qla2x00 local function return status code. 1874 * 1875 * Context: 1876 * Kernel context. 1877 */ 1878 int 1879 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name, 1880 uint8_t opt) 1881 { 1882 int rval; 1883 mbx_cmd_t mc; 1884 mbx_cmd_t *mcp = &mc; 1885 1886 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057, 1887 "Entered %s.\n", __func__); 1888 1889 mcp->mb[0] = MBC_GET_PORT_NAME; 1890 mcp->mb[9] = vha->vp_idx; 1891 mcp->out_mb = MBX_9|MBX_1|MBX_0; 1892 if (HAS_EXTENDED_IDS(vha->hw)) { 1893 mcp->mb[1] = loop_id; 1894 mcp->mb[10] = opt; 1895 mcp->out_mb |= MBX_10; 1896 } else { 1897 mcp->mb[1] = loop_id << 8 | opt; 1898 } 1899 1900 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1901 mcp->tov = MBX_TOV_SECONDS; 1902 mcp->flags = 0; 1903 rval = qla2x00_mailbox_command(vha, mcp); 1904 1905 if (rval != QLA_SUCCESS) { 1906 /*EMPTY*/ 1907 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval); 1908 } else { 1909 if (name != NULL) { 1910 /* This function returns name in big endian. */ 1911 name[0] = MSB(mcp->mb[2]); 1912 name[1] = LSB(mcp->mb[2]); 1913 name[2] = MSB(mcp->mb[3]); 1914 name[3] = LSB(mcp->mb[3]); 1915 name[4] = MSB(mcp->mb[6]); 1916 name[5] = LSB(mcp->mb[6]); 1917 name[6] = MSB(mcp->mb[7]); 1918 name[7] = LSB(mcp->mb[7]); 1919 } 1920 1921 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059, 1922 "Done %s.\n", __func__); 1923 } 1924 1925 return rval; 1926 } 1927 1928 /* 1929 * qla24xx_link_initialization 1930 * Issue link initialization mailbox command. 1931 * 1932 * Input: 1933 * ha = adapter block pointer. 1934 * TARGET_QUEUE_LOCK must be released. 1935 * ADAPTER_STATE_LOCK must be released. 1936 * 1937 * Returns: 1938 * qla2x00 local function return status code. 1939 * 1940 * Context: 1941 * Kernel context. 1942 */ 1943 int 1944 qla24xx_link_initialize(scsi_qla_host_t *vha) 1945 { 1946 int rval; 1947 mbx_cmd_t mc; 1948 mbx_cmd_t *mcp = &mc; 1949 1950 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152, 1951 "Entered %s.\n", __func__); 1952 1953 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw)) 1954 return QLA_FUNCTION_FAILED; 1955 1956 mcp->mb[0] = MBC_LINK_INITIALIZATION; 1957 mcp->mb[1] = BIT_4; 1958 if (vha->hw->operating_mode == LOOP) 1959 mcp->mb[1] |= BIT_6; 1960 else 1961 mcp->mb[1] |= BIT_5; 1962 mcp->mb[2] = 0; 1963 mcp->mb[3] = 0; 1964 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1965 mcp->in_mb = MBX_0; 1966 mcp->tov = MBX_TOV_SECONDS; 1967 mcp->flags = 0; 1968 rval = qla2x00_mailbox_command(vha, mcp); 1969 1970 if (rval != QLA_SUCCESS) { 1971 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval); 1972 } else { 1973 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154, 1974 "Done %s.\n", __func__); 1975 } 1976 1977 return rval; 1978 } 1979 1980 /* 1981 * qla2x00_lip_reset 1982 * Issue LIP reset mailbox command. 1983 * 1984 * Input: 1985 * ha = adapter block pointer. 1986 * TARGET_QUEUE_LOCK must be released. 1987 * ADAPTER_STATE_LOCK must be released. 1988 * 1989 * Returns: 1990 * qla2x00 local function return status code. 1991 * 1992 * Context: 1993 * Kernel context. 1994 */ 1995 int 1996 qla2x00_lip_reset(scsi_qla_host_t *vha) 1997 { 1998 int rval; 1999 mbx_cmd_t mc; 2000 mbx_cmd_t *mcp = &mc; 2001 2002 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a, 2003 "Entered %s.\n", __func__); 2004 2005 if (IS_CNA_CAPABLE(vha->hw)) { 2006 /* Logout across all FCFs. */ 2007 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2008 mcp->mb[1] = BIT_1; 2009 mcp->mb[2] = 0; 2010 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2011 } else if (IS_FWI2_CAPABLE(vha->hw)) { 2012 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2013 mcp->mb[1] = BIT_6; 2014 mcp->mb[2] = 0; 2015 mcp->mb[3] = vha->hw->loop_reset_delay; 2016 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2017 } else { 2018 mcp->mb[0] = MBC_LIP_RESET; 2019 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2020 if (HAS_EXTENDED_IDS(vha->hw)) { 2021 mcp->mb[1] = 0x00ff; 2022 mcp->mb[10] = 0; 2023 mcp->out_mb |= MBX_10; 2024 } else { 2025 mcp->mb[1] = 0xff00; 2026 } 2027 mcp->mb[2] = vha->hw->loop_reset_delay; 2028 mcp->mb[3] = 0; 2029 } 2030 mcp->in_mb = MBX_0; 2031 mcp->tov = MBX_TOV_SECONDS; 2032 mcp->flags = 0; 2033 rval = qla2x00_mailbox_command(vha, mcp); 2034 2035 if (rval != QLA_SUCCESS) { 2036 /*EMPTY*/ 2037 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval); 2038 } else { 2039 /*EMPTY*/ 2040 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c, 2041 "Done %s.\n", __func__); 2042 } 2043 2044 return rval; 2045 } 2046 2047 /* 2048 * qla2x00_send_sns 2049 * Send SNS command. 2050 * 2051 * Input: 2052 * ha = adapter block pointer. 2053 * sns = pointer for command. 2054 * cmd_size = command size. 2055 * buf_size = response/command size. 2056 * TARGET_QUEUE_LOCK must be released. 2057 * ADAPTER_STATE_LOCK must be released. 2058 * 2059 * Returns: 2060 * qla2x00 local function return status code. 2061 * 2062 * Context: 2063 * Kernel context. 2064 */ 2065 int 2066 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address, 2067 uint16_t cmd_size, size_t buf_size) 2068 { 2069 int rval; 2070 mbx_cmd_t mc; 2071 mbx_cmd_t *mcp = &mc; 2072 2073 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d, 2074 "Entered %s.\n", __func__); 2075 2076 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e, 2077 "Retry cnt=%d ratov=%d total tov=%d.\n", 2078 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov); 2079 2080 mcp->mb[0] = MBC_SEND_SNS_COMMAND; 2081 mcp->mb[1] = cmd_size; 2082 mcp->mb[2] = MSW(sns_phys_address); 2083 mcp->mb[3] = LSW(sns_phys_address); 2084 mcp->mb[6] = MSW(MSD(sns_phys_address)); 2085 mcp->mb[7] = LSW(MSD(sns_phys_address)); 2086 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2087 mcp->in_mb = MBX_0|MBX_1; 2088 mcp->buf_size = buf_size; 2089 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN; 2090 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2); 2091 rval = qla2x00_mailbox_command(vha, mcp); 2092 2093 if (rval != QLA_SUCCESS) { 2094 /*EMPTY*/ 2095 ql_dbg(ql_dbg_mbx, vha, 0x105f, 2096 "Failed=%x mb[0]=%x mb[1]=%x.\n", 2097 rval, mcp->mb[0], mcp->mb[1]); 2098 } else { 2099 /*EMPTY*/ 2100 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060, 2101 "Done %s.\n", __func__); 2102 } 2103 2104 return rval; 2105 } 2106 2107 int 2108 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2109 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 2110 { 2111 int rval; 2112 2113 struct logio_entry_24xx *lg; 2114 dma_addr_t lg_dma; 2115 uint32_t iop[2]; 2116 struct qla_hw_data *ha = vha->hw; 2117 struct req_que *req; 2118 2119 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061, 2120 "Entered %s.\n", __func__); 2121 2122 if (ha->flags.cpu_affinity_enabled) 2123 req = ha->req_q_map[0]; 2124 else 2125 req = vha->req; 2126 2127 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2128 if (lg == NULL) { 2129 ql_log(ql_log_warn, vha, 0x1062, 2130 "Failed to allocate login IOCB.\n"); 2131 return QLA_MEMORY_ALLOC_FAILED; 2132 } 2133 memset(lg, 0, sizeof(struct logio_entry_24xx)); 2134 2135 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2136 lg->entry_count = 1; 2137 lg->handle = MAKE_HANDLE(req->id, lg->handle); 2138 lg->nport_handle = cpu_to_le16(loop_id); 2139 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI); 2140 if (opt & BIT_0) 2141 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI); 2142 if (opt & BIT_1) 2143 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI); 2144 lg->port_id[0] = al_pa; 2145 lg->port_id[1] = area; 2146 lg->port_id[2] = domain; 2147 lg->vp_index = vha->vp_idx; 2148 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2149 (ha->r_a_tov / 10 * 2) + 2); 2150 if (rval != QLA_SUCCESS) { 2151 ql_dbg(ql_dbg_mbx, vha, 0x1063, 2152 "Failed to issue login IOCB (%x).\n", rval); 2153 } else if (lg->entry_status != 0) { 2154 ql_dbg(ql_dbg_mbx, vha, 0x1064, 2155 "Failed to complete IOCB -- error status (%x).\n", 2156 lg->entry_status); 2157 rval = QLA_FUNCTION_FAILED; 2158 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 2159 iop[0] = le32_to_cpu(lg->io_parameter[0]); 2160 iop[1] = le32_to_cpu(lg->io_parameter[1]); 2161 2162 ql_dbg(ql_dbg_mbx, vha, 0x1065, 2163 "Failed to complete IOCB -- completion status (%x) " 2164 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2165 iop[0], iop[1]); 2166 2167 switch (iop[0]) { 2168 case LSC_SCODE_PORTID_USED: 2169 mb[0] = MBS_PORT_ID_USED; 2170 mb[1] = LSW(iop[1]); 2171 break; 2172 case LSC_SCODE_NPORT_USED: 2173 mb[0] = MBS_LOOP_ID_USED; 2174 break; 2175 case LSC_SCODE_NOLINK: 2176 case LSC_SCODE_NOIOCB: 2177 case LSC_SCODE_NOXCB: 2178 case LSC_SCODE_CMD_FAILED: 2179 case LSC_SCODE_NOFABRIC: 2180 case LSC_SCODE_FW_NOT_READY: 2181 case LSC_SCODE_NOT_LOGGED_IN: 2182 case LSC_SCODE_NOPCB: 2183 case LSC_SCODE_ELS_REJECT: 2184 case LSC_SCODE_CMD_PARAM_ERR: 2185 case LSC_SCODE_NONPORT: 2186 case LSC_SCODE_LOGGED_IN: 2187 case LSC_SCODE_NOFLOGI_ACC: 2188 default: 2189 mb[0] = MBS_COMMAND_ERROR; 2190 break; 2191 } 2192 } else { 2193 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066, 2194 "Done %s.\n", __func__); 2195 2196 iop[0] = le32_to_cpu(lg->io_parameter[0]); 2197 2198 mb[0] = MBS_COMMAND_COMPLETE; 2199 mb[1] = 0; 2200 if (iop[0] & BIT_4) { 2201 if (iop[0] & BIT_8) 2202 mb[1] |= BIT_1; 2203 } else 2204 mb[1] = BIT_0; 2205 2206 /* Passback COS information. */ 2207 mb[10] = 0; 2208 if (lg->io_parameter[7] || lg->io_parameter[8]) 2209 mb[10] |= BIT_0; /* Class 2. */ 2210 if (lg->io_parameter[9] || lg->io_parameter[10]) 2211 mb[10] |= BIT_1; /* Class 3. */ 2212 if (lg->io_parameter[0] & cpu_to_le32(BIT_7)) 2213 mb[10] |= BIT_7; /* Confirmed Completion 2214 * Allowed 2215 */ 2216 } 2217 2218 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2219 2220 return rval; 2221 } 2222 2223 /* 2224 * qla2x00_login_fabric 2225 * Issue login fabric port mailbox command. 2226 * 2227 * Input: 2228 * ha = adapter block pointer. 2229 * loop_id = device loop ID. 2230 * domain = device domain. 2231 * area = device area. 2232 * al_pa = device AL_PA. 2233 * status = pointer for return status. 2234 * opt = command options. 2235 * TARGET_QUEUE_LOCK must be released. 2236 * ADAPTER_STATE_LOCK must be released. 2237 * 2238 * Returns: 2239 * qla2x00 local function return status code. 2240 * 2241 * Context: 2242 * Kernel context. 2243 */ 2244 int 2245 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2246 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 2247 { 2248 int rval; 2249 mbx_cmd_t mc; 2250 mbx_cmd_t *mcp = &mc; 2251 struct qla_hw_data *ha = vha->hw; 2252 2253 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067, 2254 "Entered %s.\n", __func__); 2255 2256 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT; 2257 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2258 if (HAS_EXTENDED_IDS(ha)) { 2259 mcp->mb[1] = loop_id; 2260 mcp->mb[10] = opt; 2261 mcp->out_mb |= MBX_10; 2262 } else { 2263 mcp->mb[1] = (loop_id << 8) | opt; 2264 } 2265 mcp->mb[2] = domain; 2266 mcp->mb[3] = area << 8 | al_pa; 2267 2268 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0; 2269 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2270 mcp->flags = 0; 2271 rval = qla2x00_mailbox_command(vha, mcp); 2272 2273 /* Return mailbox statuses. */ 2274 if (mb != NULL) { 2275 mb[0] = mcp->mb[0]; 2276 mb[1] = mcp->mb[1]; 2277 mb[2] = mcp->mb[2]; 2278 mb[6] = mcp->mb[6]; 2279 mb[7] = mcp->mb[7]; 2280 /* COS retrieved from Get-Port-Database mailbox command. */ 2281 mb[10] = 0; 2282 } 2283 2284 if (rval != QLA_SUCCESS) { 2285 /* RLU tmp code: need to change main mailbox_command function to 2286 * return ok even when the mailbox completion value is not 2287 * SUCCESS. The caller needs to be responsible to interpret 2288 * the return values of this mailbox command if we're not 2289 * to change too much of the existing code. 2290 */ 2291 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 || 2292 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 || 2293 mcp->mb[0] == 0x4006) 2294 rval = QLA_SUCCESS; 2295 2296 /*EMPTY*/ 2297 ql_dbg(ql_dbg_mbx, vha, 0x1068, 2298 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 2299 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 2300 } else { 2301 /*EMPTY*/ 2302 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069, 2303 "Done %s.\n", __func__); 2304 } 2305 2306 return rval; 2307 } 2308 2309 /* 2310 * qla2x00_login_local_device 2311 * Issue login loop port mailbox command. 2312 * 2313 * Input: 2314 * ha = adapter block pointer. 2315 * loop_id = device loop ID. 2316 * opt = command options. 2317 * 2318 * Returns: 2319 * Return status code. 2320 * 2321 * Context: 2322 * Kernel context. 2323 * 2324 */ 2325 int 2326 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport, 2327 uint16_t *mb_ret, uint8_t opt) 2328 { 2329 int rval; 2330 mbx_cmd_t mc; 2331 mbx_cmd_t *mcp = &mc; 2332 struct qla_hw_data *ha = vha->hw; 2333 2334 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a, 2335 "Entered %s.\n", __func__); 2336 2337 if (IS_FWI2_CAPABLE(ha)) 2338 return qla24xx_login_fabric(vha, fcport->loop_id, 2339 fcport->d_id.b.domain, fcport->d_id.b.area, 2340 fcport->d_id.b.al_pa, mb_ret, opt); 2341 2342 mcp->mb[0] = MBC_LOGIN_LOOP_PORT; 2343 if (HAS_EXTENDED_IDS(ha)) 2344 mcp->mb[1] = fcport->loop_id; 2345 else 2346 mcp->mb[1] = fcport->loop_id << 8; 2347 mcp->mb[2] = opt; 2348 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2349 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0; 2350 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2351 mcp->flags = 0; 2352 rval = qla2x00_mailbox_command(vha, mcp); 2353 2354 /* Return mailbox statuses. */ 2355 if (mb_ret != NULL) { 2356 mb_ret[0] = mcp->mb[0]; 2357 mb_ret[1] = mcp->mb[1]; 2358 mb_ret[6] = mcp->mb[6]; 2359 mb_ret[7] = mcp->mb[7]; 2360 } 2361 2362 if (rval != QLA_SUCCESS) { 2363 /* AV tmp code: need to change main mailbox_command function to 2364 * return ok even when the mailbox completion value is not 2365 * SUCCESS. The caller needs to be responsible to interpret 2366 * the return values of this mailbox command if we're not 2367 * to change too much of the existing code. 2368 */ 2369 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006) 2370 rval = QLA_SUCCESS; 2371 2372 ql_dbg(ql_dbg_mbx, vha, 0x106b, 2373 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n", 2374 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]); 2375 } else { 2376 /*EMPTY*/ 2377 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c, 2378 "Done %s.\n", __func__); 2379 } 2380 2381 return (rval); 2382 } 2383 2384 int 2385 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2386 uint8_t area, uint8_t al_pa) 2387 { 2388 int rval; 2389 struct logio_entry_24xx *lg; 2390 dma_addr_t lg_dma; 2391 struct qla_hw_data *ha = vha->hw; 2392 struct req_que *req; 2393 2394 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d, 2395 "Entered %s.\n", __func__); 2396 2397 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2398 if (lg == NULL) { 2399 ql_log(ql_log_warn, vha, 0x106e, 2400 "Failed to allocate logout IOCB.\n"); 2401 return QLA_MEMORY_ALLOC_FAILED; 2402 } 2403 memset(lg, 0, sizeof(struct logio_entry_24xx)); 2404 2405 if (ql2xmaxqueues > 1) 2406 req = ha->req_q_map[0]; 2407 else 2408 req = vha->req; 2409 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2410 lg->entry_count = 1; 2411 lg->handle = MAKE_HANDLE(req->id, lg->handle); 2412 lg->nport_handle = cpu_to_le16(loop_id); 2413 lg->control_flags = 2414 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO| 2415 LCF_FREE_NPORT); 2416 lg->port_id[0] = al_pa; 2417 lg->port_id[1] = area; 2418 lg->port_id[2] = domain; 2419 lg->vp_index = vha->vp_idx; 2420 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2421 (ha->r_a_tov / 10 * 2) + 2); 2422 if (rval != QLA_SUCCESS) { 2423 ql_dbg(ql_dbg_mbx, vha, 0x106f, 2424 "Failed to issue logout IOCB (%x).\n", rval); 2425 } else if (lg->entry_status != 0) { 2426 ql_dbg(ql_dbg_mbx, vha, 0x1070, 2427 "Failed to complete IOCB -- error status (%x).\n", 2428 lg->entry_status); 2429 rval = QLA_FUNCTION_FAILED; 2430 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 2431 ql_dbg(ql_dbg_mbx, vha, 0x1071, 2432 "Failed to complete IOCB -- completion status (%x) " 2433 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2434 le32_to_cpu(lg->io_parameter[0]), 2435 le32_to_cpu(lg->io_parameter[1])); 2436 } else { 2437 /*EMPTY*/ 2438 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072, 2439 "Done %s.\n", __func__); 2440 } 2441 2442 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2443 2444 return rval; 2445 } 2446 2447 /* 2448 * qla2x00_fabric_logout 2449 * Issue logout fabric port mailbox command. 2450 * 2451 * Input: 2452 * ha = adapter block pointer. 2453 * loop_id = device loop ID. 2454 * TARGET_QUEUE_LOCK must be released. 2455 * ADAPTER_STATE_LOCK must be released. 2456 * 2457 * Returns: 2458 * qla2x00 local function return status code. 2459 * 2460 * Context: 2461 * Kernel context. 2462 */ 2463 int 2464 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2465 uint8_t area, uint8_t al_pa) 2466 { 2467 int rval; 2468 mbx_cmd_t mc; 2469 mbx_cmd_t *mcp = &mc; 2470 2471 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073, 2472 "Entered %s.\n", __func__); 2473 2474 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT; 2475 mcp->out_mb = MBX_1|MBX_0; 2476 if (HAS_EXTENDED_IDS(vha->hw)) { 2477 mcp->mb[1] = loop_id; 2478 mcp->mb[10] = 0; 2479 mcp->out_mb |= MBX_10; 2480 } else { 2481 mcp->mb[1] = loop_id << 8; 2482 } 2483 2484 mcp->in_mb = MBX_1|MBX_0; 2485 mcp->tov = MBX_TOV_SECONDS; 2486 mcp->flags = 0; 2487 rval = qla2x00_mailbox_command(vha, mcp); 2488 2489 if (rval != QLA_SUCCESS) { 2490 /*EMPTY*/ 2491 ql_dbg(ql_dbg_mbx, vha, 0x1074, 2492 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]); 2493 } else { 2494 /*EMPTY*/ 2495 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075, 2496 "Done %s.\n", __func__); 2497 } 2498 2499 return rval; 2500 } 2501 2502 /* 2503 * qla2x00_full_login_lip 2504 * Issue full login LIP mailbox command. 2505 * 2506 * Input: 2507 * ha = adapter block pointer. 2508 * TARGET_QUEUE_LOCK must be released. 2509 * ADAPTER_STATE_LOCK must be released. 2510 * 2511 * Returns: 2512 * qla2x00 local function return status code. 2513 * 2514 * Context: 2515 * Kernel context. 2516 */ 2517 int 2518 qla2x00_full_login_lip(scsi_qla_host_t *vha) 2519 { 2520 int rval; 2521 mbx_cmd_t mc; 2522 mbx_cmd_t *mcp = &mc; 2523 2524 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076, 2525 "Entered %s.\n", __func__); 2526 2527 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2528 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0; 2529 mcp->mb[2] = 0; 2530 mcp->mb[3] = 0; 2531 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2532 mcp->in_mb = MBX_0; 2533 mcp->tov = MBX_TOV_SECONDS; 2534 mcp->flags = 0; 2535 rval = qla2x00_mailbox_command(vha, mcp); 2536 2537 if (rval != QLA_SUCCESS) { 2538 /*EMPTY*/ 2539 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval); 2540 } else { 2541 /*EMPTY*/ 2542 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078, 2543 "Done %s.\n", __func__); 2544 } 2545 2546 return rval; 2547 } 2548 2549 /* 2550 * qla2x00_get_id_list 2551 * 2552 * Input: 2553 * ha = adapter block pointer. 2554 * 2555 * Returns: 2556 * qla2x00 local function return status code. 2557 * 2558 * Context: 2559 * Kernel context. 2560 */ 2561 int 2562 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma, 2563 uint16_t *entries) 2564 { 2565 int rval; 2566 mbx_cmd_t mc; 2567 mbx_cmd_t *mcp = &mc; 2568 2569 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079, 2570 "Entered %s.\n", __func__); 2571 2572 if (id_list == NULL) 2573 return QLA_FUNCTION_FAILED; 2574 2575 mcp->mb[0] = MBC_GET_ID_LIST; 2576 mcp->out_mb = MBX_0; 2577 if (IS_FWI2_CAPABLE(vha->hw)) { 2578 mcp->mb[2] = MSW(id_list_dma); 2579 mcp->mb[3] = LSW(id_list_dma); 2580 mcp->mb[6] = MSW(MSD(id_list_dma)); 2581 mcp->mb[7] = LSW(MSD(id_list_dma)); 2582 mcp->mb[8] = 0; 2583 mcp->mb[9] = vha->vp_idx; 2584 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2; 2585 } else { 2586 mcp->mb[1] = MSW(id_list_dma); 2587 mcp->mb[2] = LSW(id_list_dma); 2588 mcp->mb[3] = MSW(MSD(id_list_dma)); 2589 mcp->mb[6] = LSW(MSD(id_list_dma)); 2590 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1; 2591 } 2592 mcp->in_mb = MBX_1|MBX_0; 2593 mcp->tov = MBX_TOV_SECONDS; 2594 mcp->flags = 0; 2595 rval = qla2x00_mailbox_command(vha, mcp); 2596 2597 if (rval != QLA_SUCCESS) { 2598 /*EMPTY*/ 2599 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval); 2600 } else { 2601 *entries = mcp->mb[1]; 2602 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b, 2603 "Done %s.\n", __func__); 2604 } 2605 2606 return rval; 2607 } 2608 2609 /* 2610 * qla2x00_get_resource_cnts 2611 * Get current firmware resource counts. 2612 * 2613 * Input: 2614 * ha = adapter block pointer. 2615 * 2616 * Returns: 2617 * qla2x00 local function return status code. 2618 * 2619 * Context: 2620 * Kernel context. 2621 */ 2622 int 2623 qla2x00_get_resource_cnts(scsi_qla_host_t *vha) 2624 { 2625 struct qla_hw_data *ha = vha->hw; 2626 int rval; 2627 mbx_cmd_t mc; 2628 mbx_cmd_t *mcp = &mc; 2629 2630 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c, 2631 "Entered %s.\n", __func__); 2632 2633 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS; 2634 mcp->out_mb = MBX_0; 2635 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2636 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw)) 2637 mcp->in_mb |= MBX_12; 2638 mcp->tov = MBX_TOV_SECONDS; 2639 mcp->flags = 0; 2640 rval = qla2x00_mailbox_command(vha, mcp); 2641 2642 if (rval != QLA_SUCCESS) { 2643 /*EMPTY*/ 2644 ql_dbg(ql_dbg_mbx, vha, 0x107d, 2645 "Failed mb[0]=%x.\n", mcp->mb[0]); 2646 } else { 2647 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e, 2648 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x " 2649 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2], 2650 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10], 2651 mcp->mb[11], mcp->mb[12]); 2652 2653 ha->orig_fw_tgt_xcb_count = mcp->mb[1]; 2654 ha->cur_fw_tgt_xcb_count = mcp->mb[2]; 2655 ha->cur_fw_xcb_count = mcp->mb[3]; 2656 ha->orig_fw_xcb_count = mcp->mb[6]; 2657 ha->cur_fw_iocb_count = mcp->mb[7]; 2658 ha->orig_fw_iocb_count = mcp->mb[10]; 2659 if (ha->flags.npiv_supported) 2660 ha->max_npiv_vports = mcp->mb[11]; 2661 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2662 ha->fw_max_fcf_count = mcp->mb[12]; 2663 } 2664 2665 return (rval); 2666 } 2667 2668 /* 2669 * qla2x00_get_fcal_position_map 2670 * Get FCAL (LILP) position map using mailbox command 2671 * 2672 * Input: 2673 * ha = adapter state pointer. 2674 * pos_map = buffer pointer (can be NULL). 2675 * 2676 * Returns: 2677 * qla2x00 local function return status code. 2678 * 2679 * Context: 2680 * Kernel context. 2681 */ 2682 int 2683 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map) 2684 { 2685 int rval; 2686 mbx_cmd_t mc; 2687 mbx_cmd_t *mcp = &mc; 2688 char *pmap; 2689 dma_addr_t pmap_dma; 2690 struct qla_hw_data *ha = vha->hw; 2691 2692 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f, 2693 "Entered %s.\n", __func__); 2694 2695 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma); 2696 if (pmap == NULL) { 2697 ql_log(ql_log_warn, vha, 0x1080, 2698 "Memory alloc failed.\n"); 2699 return QLA_MEMORY_ALLOC_FAILED; 2700 } 2701 memset(pmap, 0, FCAL_MAP_SIZE); 2702 2703 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP; 2704 mcp->mb[2] = MSW(pmap_dma); 2705 mcp->mb[3] = LSW(pmap_dma); 2706 mcp->mb[6] = MSW(MSD(pmap_dma)); 2707 mcp->mb[7] = LSW(MSD(pmap_dma)); 2708 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2709 mcp->in_mb = MBX_1|MBX_0; 2710 mcp->buf_size = FCAL_MAP_SIZE; 2711 mcp->flags = MBX_DMA_IN; 2712 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2713 rval = qla2x00_mailbox_command(vha, mcp); 2714 2715 if (rval == QLA_SUCCESS) { 2716 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081, 2717 "mb0/mb1=%x/%X FC/AL position map size (%x).\n", 2718 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]); 2719 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d, 2720 pmap, pmap[0] + 1); 2721 2722 if (pos_map) 2723 memcpy(pos_map, pmap, FCAL_MAP_SIZE); 2724 } 2725 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma); 2726 2727 if (rval != QLA_SUCCESS) { 2728 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval); 2729 } else { 2730 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083, 2731 "Done %s.\n", __func__); 2732 } 2733 2734 return rval; 2735 } 2736 2737 /* 2738 * qla2x00_get_link_status 2739 * 2740 * Input: 2741 * ha = adapter block pointer. 2742 * loop_id = device loop ID. 2743 * ret_buf = pointer to link status return buffer. 2744 * 2745 * Returns: 2746 * 0 = success. 2747 * BIT_0 = mem alloc error. 2748 * BIT_1 = mailbox error. 2749 */ 2750 int 2751 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id, 2752 struct link_statistics *stats, dma_addr_t stats_dma) 2753 { 2754 int rval; 2755 mbx_cmd_t mc; 2756 mbx_cmd_t *mcp = &mc; 2757 uint32_t *siter, *diter, dwords; 2758 struct qla_hw_data *ha = vha->hw; 2759 2760 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084, 2761 "Entered %s.\n", __func__); 2762 2763 mcp->mb[0] = MBC_GET_LINK_STATUS; 2764 mcp->mb[2] = MSW(stats_dma); 2765 mcp->mb[3] = LSW(stats_dma); 2766 mcp->mb[6] = MSW(MSD(stats_dma)); 2767 mcp->mb[7] = LSW(MSD(stats_dma)); 2768 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2769 mcp->in_mb = MBX_0; 2770 if (IS_FWI2_CAPABLE(ha)) { 2771 mcp->mb[1] = loop_id; 2772 mcp->mb[4] = 0; 2773 mcp->mb[10] = 0; 2774 mcp->out_mb |= MBX_10|MBX_4|MBX_1; 2775 mcp->in_mb |= MBX_1; 2776 } else if (HAS_EXTENDED_IDS(ha)) { 2777 mcp->mb[1] = loop_id; 2778 mcp->mb[10] = 0; 2779 mcp->out_mb |= MBX_10|MBX_1; 2780 } else { 2781 mcp->mb[1] = loop_id << 8; 2782 mcp->out_mb |= MBX_1; 2783 } 2784 mcp->tov = MBX_TOV_SECONDS; 2785 mcp->flags = IOCTL_CMD; 2786 rval = qla2x00_mailbox_command(vha, mcp); 2787 2788 if (rval == QLA_SUCCESS) { 2789 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2790 ql_dbg(ql_dbg_mbx, vha, 0x1085, 2791 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2792 rval = QLA_FUNCTION_FAILED; 2793 } else { 2794 /* Copy over data -- firmware data is LE. */ 2795 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086, 2796 "Done %s.\n", __func__); 2797 dwords = offsetof(struct link_statistics, unused1) / 4; 2798 siter = diter = &stats->link_fail_cnt; 2799 while (dwords--) 2800 *diter++ = le32_to_cpu(*siter++); 2801 } 2802 } else { 2803 /* Failed. */ 2804 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval); 2805 } 2806 2807 return rval; 2808 } 2809 2810 int 2811 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats, 2812 dma_addr_t stats_dma) 2813 { 2814 int rval; 2815 mbx_cmd_t mc; 2816 mbx_cmd_t *mcp = &mc; 2817 uint32_t *siter, *diter, dwords; 2818 2819 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088, 2820 "Entered %s.\n", __func__); 2821 2822 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS; 2823 mcp->mb[2] = MSW(stats_dma); 2824 mcp->mb[3] = LSW(stats_dma); 2825 mcp->mb[6] = MSW(MSD(stats_dma)); 2826 mcp->mb[7] = LSW(MSD(stats_dma)); 2827 mcp->mb[8] = sizeof(struct link_statistics) / 4; 2828 mcp->mb[9] = vha->vp_idx; 2829 mcp->mb[10] = 0; 2830 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2831 mcp->in_mb = MBX_2|MBX_1|MBX_0; 2832 mcp->tov = MBX_TOV_SECONDS; 2833 mcp->flags = IOCTL_CMD; 2834 rval = qla2x00_mailbox_command(vha, mcp); 2835 2836 if (rval == QLA_SUCCESS) { 2837 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2838 ql_dbg(ql_dbg_mbx, vha, 0x1089, 2839 "Failed mb[0]=%x.\n", mcp->mb[0]); 2840 rval = QLA_FUNCTION_FAILED; 2841 } else { 2842 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a, 2843 "Done %s.\n", __func__); 2844 /* Copy over data -- firmware data is LE. */ 2845 dwords = sizeof(struct link_statistics) / 4; 2846 siter = diter = &stats->link_fail_cnt; 2847 while (dwords--) 2848 *diter++ = le32_to_cpu(*siter++); 2849 } 2850 } else { 2851 /* Failed. */ 2852 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval); 2853 } 2854 2855 return rval; 2856 } 2857 2858 int 2859 qla24xx_abort_command(srb_t *sp) 2860 { 2861 int rval; 2862 unsigned long flags = 0; 2863 2864 struct abort_entry_24xx *abt; 2865 dma_addr_t abt_dma; 2866 uint32_t handle; 2867 fc_port_t *fcport = sp->fcport; 2868 struct scsi_qla_host *vha = fcport->vha; 2869 struct qla_hw_data *ha = vha->hw; 2870 struct req_que *req = vha->req; 2871 2872 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c, 2873 "Entered %s.\n", __func__); 2874 2875 if (ql2xasynctmfenable) 2876 return qla24xx_async_abort_command(sp); 2877 2878 spin_lock_irqsave(&ha->hardware_lock, flags); 2879 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 2880 if (req->outstanding_cmds[handle] == sp) 2881 break; 2882 } 2883 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2884 if (handle == req->num_outstanding_cmds) { 2885 /* Command not found. */ 2886 return QLA_FUNCTION_FAILED; 2887 } 2888 2889 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma); 2890 if (abt == NULL) { 2891 ql_log(ql_log_warn, vha, 0x108d, 2892 "Failed to allocate abort IOCB.\n"); 2893 return QLA_MEMORY_ALLOC_FAILED; 2894 } 2895 memset(abt, 0, sizeof(struct abort_entry_24xx)); 2896 2897 abt->entry_type = ABORT_IOCB_TYPE; 2898 abt->entry_count = 1; 2899 abt->handle = MAKE_HANDLE(req->id, abt->handle); 2900 abt->nport_handle = cpu_to_le16(fcport->loop_id); 2901 abt->handle_to_abort = MAKE_HANDLE(req->id, handle); 2902 abt->port_id[0] = fcport->d_id.b.al_pa; 2903 abt->port_id[1] = fcport->d_id.b.area; 2904 abt->port_id[2] = fcport->d_id.b.domain; 2905 abt->vp_index = fcport->vha->vp_idx; 2906 2907 abt->req_que_no = cpu_to_le16(req->id); 2908 2909 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0); 2910 if (rval != QLA_SUCCESS) { 2911 ql_dbg(ql_dbg_mbx, vha, 0x108e, 2912 "Failed to issue IOCB (%x).\n", rval); 2913 } else if (abt->entry_status != 0) { 2914 ql_dbg(ql_dbg_mbx, vha, 0x108f, 2915 "Failed to complete IOCB -- error status (%x).\n", 2916 abt->entry_status); 2917 rval = QLA_FUNCTION_FAILED; 2918 } else if (abt->nport_handle != cpu_to_le16(0)) { 2919 ql_dbg(ql_dbg_mbx, vha, 0x1090, 2920 "Failed to complete IOCB -- completion status (%x).\n", 2921 le16_to_cpu(abt->nport_handle)); 2922 if (abt->nport_handle == CS_IOCB_ERROR) 2923 rval = QLA_FUNCTION_PARAMETER_ERROR; 2924 else 2925 rval = QLA_FUNCTION_FAILED; 2926 } else { 2927 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091, 2928 "Done %s.\n", __func__); 2929 } 2930 2931 dma_pool_free(ha->s_dma_pool, abt, abt_dma); 2932 2933 return rval; 2934 } 2935 2936 struct tsk_mgmt_cmd { 2937 union { 2938 struct tsk_mgmt_entry tsk; 2939 struct sts_entry_24xx sts; 2940 } p; 2941 }; 2942 2943 static int 2944 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport, 2945 uint64_t l, int tag) 2946 { 2947 int rval, rval2; 2948 struct tsk_mgmt_cmd *tsk; 2949 struct sts_entry_24xx *sts; 2950 dma_addr_t tsk_dma; 2951 scsi_qla_host_t *vha; 2952 struct qla_hw_data *ha; 2953 struct req_que *req; 2954 struct rsp_que *rsp; 2955 2956 vha = fcport->vha; 2957 ha = vha->hw; 2958 req = vha->req; 2959 2960 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092, 2961 "Entered %s.\n", __func__); 2962 2963 if (ha->flags.cpu_affinity_enabled) 2964 rsp = ha->rsp_q_map[tag + 1]; 2965 else 2966 rsp = req->rsp; 2967 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma); 2968 if (tsk == NULL) { 2969 ql_log(ql_log_warn, vha, 0x1093, 2970 "Failed to allocate task management IOCB.\n"); 2971 return QLA_MEMORY_ALLOC_FAILED; 2972 } 2973 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd)); 2974 2975 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE; 2976 tsk->p.tsk.entry_count = 1; 2977 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle); 2978 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id); 2979 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2); 2980 tsk->p.tsk.control_flags = cpu_to_le32(type); 2981 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa; 2982 tsk->p.tsk.port_id[1] = fcport->d_id.b.area; 2983 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain; 2984 tsk->p.tsk.vp_index = fcport->vha->vp_idx; 2985 if (type == TCF_LUN_RESET) { 2986 int_to_scsilun(l, &tsk->p.tsk.lun); 2987 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun, 2988 sizeof(tsk->p.tsk.lun)); 2989 } 2990 2991 sts = &tsk->p.sts; 2992 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0); 2993 if (rval != QLA_SUCCESS) { 2994 ql_dbg(ql_dbg_mbx, vha, 0x1094, 2995 "Failed to issue %s reset IOCB (%x).\n", name, rval); 2996 } else if (sts->entry_status != 0) { 2997 ql_dbg(ql_dbg_mbx, vha, 0x1095, 2998 "Failed to complete IOCB -- error status (%x).\n", 2999 sts->entry_status); 3000 rval = QLA_FUNCTION_FAILED; 3001 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) { 3002 ql_dbg(ql_dbg_mbx, vha, 0x1096, 3003 "Failed to complete IOCB -- completion status (%x).\n", 3004 le16_to_cpu(sts->comp_status)); 3005 rval = QLA_FUNCTION_FAILED; 3006 } else if (le16_to_cpu(sts->scsi_status) & 3007 SS_RESPONSE_INFO_LEN_VALID) { 3008 if (le32_to_cpu(sts->rsp_data_len) < 4) { 3009 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097, 3010 "Ignoring inconsistent data length -- not enough " 3011 "response info (%d).\n", 3012 le32_to_cpu(sts->rsp_data_len)); 3013 } else if (sts->data[3]) { 3014 ql_dbg(ql_dbg_mbx, vha, 0x1098, 3015 "Failed to complete IOCB -- response (%x).\n", 3016 sts->data[3]); 3017 rval = QLA_FUNCTION_FAILED; 3018 } 3019 } 3020 3021 /* Issue marker IOCB. */ 3022 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 3023 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID); 3024 if (rval2 != QLA_SUCCESS) { 3025 ql_dbg(ql_dbg_mbx, vha, 0x1099, 3026 "Failed to issue marker IOCB (%x).\n", rval2); 3027 } else { 3028 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a, 3029 "Done %s.\n", __func__); 3030 } 3031 3032 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma); 3033 3034 return rval; 3035 } 3036 3037 int 3038 qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag) 3039 { 3040 struct qla_hw_data *ha = fcport->vha->hw; 3041 3042 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 3043 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag); 3044 3045 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag); 3046 } 3047 3048 int 3049 qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 3050 { 3051 struct qla_hw_data *ha = fcport->vha->hw; 3052 3053 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 3054 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag); 3055 3056 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag); 3057 } 3058 3059 int 3060 qla2x00_system_error(scsi_qla_host_t *vha) 3061 { 3062 int rval; 3063 mbx_cmd_t mc; 3064 mbx_cmd_t *mcp = &mc; 3065 struct qla_hw_data *ha = vha->hw; 3066 3067 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha)) 3068 return QLA_FUNCTION_FAILED; 3069 3070 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b, 3071 "Entered %s.\n", __func__); 3072 3073 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR; 3074 mcp->out_mb = MBX_0; 3075 mcp->in_mb = MBX_0; 3076 mcp->tov = 5; 3077 mcp->flags = 0; 3078 rval = qla2x00_mailbox_command(vha, mcp); 3079 3080 if (rval != QLA_SUCCESS) { 3081 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval); 3082 } else { 3083 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d, 3084 "Done %s.\n", __func__); 3085 } 3086 3087 return rval; 3088 } 3089 3090 int 3091 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data) 3092 { 3093 int rval; 3094 mbx_cmd_t mc; 3095 mbx_cmd_t *mcp = &mc; 3096 3097 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 3098 !IS_QLA27XX(vha->hw)) 3099 return QLA_FUNCTION_FAILED; 3100 3101 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182, 3102 "Entered %s.\n", __func__); 3103 3104 mcp->mb[0] = MBC_WRITE_SERDES; 3105 mcp->mb[1] = addr; 3106 if (IS_QLA2031(vha->hw)) 3107 mcp->mb[2] = data & 0xff; 3108 else 3109 mcp->mb[2] = data; 3110 3111 mcp->mb[3] = 0; 3112 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 3113 mcp->in_mb = MBX_0; 3114 mcp->tov = MBX_TOV_SECONDS; 3115 mcp->flags = 0; 3116 rval = qla2x00_mailbox_command(vha, mcp); 3117 3118 if (rval != QLA_SUCCESS) { 3119 ql_dbg(ql_dbg_mbx, vha, 0x1183, 3120 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3121 } else { 3122 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184, 3123 "Done %s.\n", __func__); 3124 } 3125 3126 return rval; 3127 } 3128 3129 int 3130 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data) 3131 { 3132 int rval; 3133 mbx_cmd_t mc; 3134 mbx_cmd_t *mcp = &mc; 3135 3136 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 3137 !IS_QLA27XX(vha->hw)) 3138 return QLA_FUNCTION_FAILED; 3139 3140 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185, 3141 "Entered %s.\n", __func__); 3142 3143 mcp->mb[0] = MBC_READ_SERDES; 3144 mcp->mb[1] = addr; 3145 mcp->mb[3] = 0; 3146 mcp->out_mb = MBX_3|MBX_1|MBX_0; 3147 mcp->in_mb = MBX_1|MBX_0; 3148 mcp->tov = MBX_TOV_SECONDS; 3149 mcp->flags = 0; 3150 rval = qla2x00_mailbox_command(vha, mcp); 3151 3152 if (IS_QLA2031(vha->hw)) 3153 *data = mcp->mb[1] & 0xff; 3154 else 3155 *data = mcp->mb[1]; 3156 3157 if (rval != QLA_SUCCESS) { 3158 ql_dbg(ql_dbg_mbx, vha, 0x1186, 3159 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3160 } else { 3161 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187, 3162 "Done %s.\n", __func__); 3163 } 3164 3165 return rval; 3166 } 3167 3168 int 3169 qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) 3170 { 3171 int rval; 3172 mbx_cmd_t mc; 3173 mbx_cmd_t *mcp = &mc; 3174 3175 if (!IS_QLA8044(vha->hw)) 3176 return QLA_FUNCTION_FAILED; 3177 3178 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1186, 3179 "Entered %s.\n", __func__); 3180 3181 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 3182 mcp->mb[1] = HCS_WRITE_SERDES; 3183 mcp->mb[3] = LSW(addr); 3184 mcp->mb[4] = MSW(addr); 3185 mcp->mb[5] = LSW(data); 3186 mcp->mb[6] = MSW(data); 3187 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0; 3188 mcp->in_mb = MBX_0; 3189 mcp->tov = MBX_TOV_SECONDS; 3190 mcp->flags = 0; 3191 rval = qla2x00_mailbox_command(vha, mcp); 3192 3193 if (rval != QLA_SUCCESS) { 3194 ql_dbg(ql_dbg_mbx, vha, 0x1187, 3195 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3196 } else { 3197 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188, 3198 "Done %s.\n", __func__); 3199 } 3200 3201 return rval; 3202 } 3203 3204 int 3205 qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) 3206 { 3207 int rval; 3208 mbx_cmd_t mc; 3209 mbx_cmd_t *mcp = &mc; 3210 3211 if (!IS_QLA8044(vha->hw)) 3212 return QLA_FUNCTION_FAILED; 3213 3214 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189, 3215 "Entered %s.\n", __func__); 3216 3217 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 3218 mcp->mb[1] = HCS_READ_SERDES; 3219 mcp->mb[3] = LSW(addr); 3220 mcp->mb[4] = MSW(addr); 3221 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0; 3222 mcp->in_mb = MBX_2|MBX_1|MBX_0; 3223 mcp->tov = MBX_TOV_SECONDS; 3224 mcp->flags = 0; 3225 rval = qla2x00_mailbox_command(vha, mcp); 3226 3227 *data = mcp->mb[2] << 16 | mcp->mb[1]; 3228 3229 if (rval != QLA_SUCCESS) { 3230 ql_dbg(ql_dbg_mbx, vha, 0x118a, 3231 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3232 } else { 3233 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b, 3234 "Done %s.\n", __func__); 3235 } 3236 3237 return rval; 3238 } 3239 3240 /** 3241 * qla2x00_set_serdes_params() - 3242 * @ha: HA context 3243 * 3244 * Returns 3245 */ 3246 int 3247 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g, 3248 uint16_t sw_em_2g, uint16_t sw_em_4g) 3249 { 3250 int rval; 3251 mbx_cmd_t mc; 3252 mbx_cmd_t *mcp = &mc; 3253 3254 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e, 3255 "Entered %s.\n", __func__); 3256 3257 mcp->mb[0] = MBC_SERDES_PARAMS; 3258 mcp->mb[1] = BIT_0; 3259 mcp->mb[2] = sw_em_1g | BIT_15; 3260 mcp->mb[3] = sw_em_2g | BIT_15; 3261 mcp->mb[4] = sw_em_4g | BIT_15; 3262 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3263 mcp->in_mb = MBX_0; 3264 mcp->tov = MBX_TOV_SECONDS; 3265 mcp->flags = 0; 3266 rval = qla2x00_mailbox_command(vha, mcp); 3267 3268 if (rval != QLA_SUCCESS) { 3269 /*EMPTY*/ 3270 ql_dbg(ql_dbg_mbx, vha, 0x109f, 3271 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3272 } else { 3273 /*EMPTY*/ 3274 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0, 3275 "Done %s.\n", __func__); 3276 } 3277 3278 return rval; 3279 } 3280 3281 int 3282 qla2x00_stop_firmware(scsi_qla_host_t *vha) 3283 { 3284 int rval; 3285 mbx_cmd_t mc; 3286 mbx_cmd_t *mcp = &mc; 3287 3288 if (!IS_FWI2_CAPABLE(vha->hw)) 3289 return QLA_FUNCTION_FAILED; 3290 3291 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1, 3292 "Entered %s.\n", __func__); 3293 3294 mcp->mb[0] = MBC_STOP_FIRMWARE; 3295 mcp->mb[1] = 0; 3296 mcp->out_mb = MBX_1|MBX_0; 3297 mcp->in_mb = MBX_0; 3298 mcp->tov = 5; 3299 mcp->flags = 0; 3300 rval = qla2x00_mailbox_command(vha, mcp); 3301 3302 if (rval != QLA_SUCCESS) { 3303 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval); 3304 if (mcp->mb[0] == MBS_INVALID_COMMAND) 3305 rval = QLA_INVALID_COMMAND; 3306 } else { 3307 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3, 3308 "Done %s.\n", __func__); 3309 } 3310 3311 return rval; 3312 } 3313 3314 int 3315 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma, 3316 uint16_t buffers) 3317 { 3318 int rval; 3319 mbx_cmd_t mc; 3320 mbx_cmd_t *mcp = &mc; 3321 3322 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4, 3323 "Entered %s.\n", __func__); 3324 3325 if (!IS_FWI2_CAPABLE(vha->hw)) 3326 return QLA_FUNCTION_FAILED; 3327 3328 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3329 return QLA_FUNCTION_FAILED; 3330 3331 mcp->mb[0] = MBC_TRACE_CONTROL; 3332 mcp->mb[1] = TC_EFT_ENABLE; 3333 mcp->mb[2] = LSW(eft_dma); 3334 mcp->mb[3] = MSW(eft_dma); 3335 mcp->mb[4] = LSW(MSD(eft_dma)); 3336 mcp->mb[5] = MSW(MSD(eft_dma)); 3337 mcp->mb[6] = buffers; 3338 mcp->mb[7] = TC_AEN_DISABLE; 3339 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3340 mcp->in_mb = MBX_1|MBX_0; 3341 mcp->tov = MBX_TOV_SECONDS; 3342 mcp->flags = 0; 3343 rval = qla2x00_mailbox_command(vha, mcp); 3344 if (rval != QLA_SUCCESS) { 3345 ql_dbg(ql_dbg_mbx, vha, 0x10a5, 3346 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3347 rval, mcp->mb[0], mcp->mb[1]); 3348 } else { 3349 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6, 3350 "Done %s.\n", __func__); 3351 } 3352 3353 return rval; 3354 } 3355 3356 int 3357 qla2x00_disable_eft_trace(scsi_qla_host_t *vha) 3358 { 3359 int rval; 3360 mbx_cmd_t mc; 3361 mbx_cmd_t *mcp = &mc; 3362 3363 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7, 3364 "Entered %s.\n", __func__); 3365 3366 if (!IS_FWI2_CAPABLE(vha->hw)) 3367 return QLA_FUNCTION_FAILED; 3368 3369 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3370 return QLA_FUNCTION_FAILED; 3371 3372 mcp->mb[0] = MBC_TRACE_CONTROL; 3373 mcp->mb[1] = TC_EFT_DISABLE; 3374 mcp->out_mb = MBX_1|MBX_0; 3375 mcp->in_mb = MBX_1|MBX_0; 3376 mcp->tov = MBX_TOV_SECONDS; 3377 mcp->flags = 0; 3378 rval = qla2x00_mailbox_command(vha, mcp); 3379 if (rval != QLA_SUCCESS) { 3380 ql_dbg(ql_dbg_mbx, vha, 0x10a8, 3381 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3382 rval, mcp->mb[0], mcp->mb[1]); 3383 } else { 3384 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9, 3385 "Done %s.\n", __func__); 3386 } 3387 3388 return rval; 3389 } 3390 3391 int 3392 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma, 3393 uint16_t buffers, uint16_t *mb, uint32_t *dwords) 3394 { 3395 int rval; 3396 mbx_cmd_t mc; 3397 mbx_cmd_t *mcp = &mc; 3398 3399 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa, 3400 "Entered %s.\n", __func__); 3401 3402 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) && 3403 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw)) 3404 return QLA_FUNCTION_FAILED; 3405 3406 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3407 return QLA_FUNCTION_FAILED; 3408 3409 mcp->mb[0] = MBC_TRACE_CONTROL; 3410 mcp->mb[1] = TC_FCE_ENABLE; 3411 mcp->mb[2] = LSW(fce_dma); 3412 mcp->mb[3] = MSW(fce_dma); 3413 mcp->mb[4] = LSW(MSD(fce_dma)); 3414 mcp->mb[5] = MSW(MSD(fce_dma)); 3415 mcp->mb[6] = buffers; 3416 mcp->mb[7] = TC_AEN_DISABLE; 3417 mcp->mb[8] = 0; 3418 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE; 3419 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE; 3420 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3421 MBX_1|MBX_0; 3422 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3423 mcp->tov = MBX_TOV_SECONDS; 3424 mcp->flags = 0; 3425 rval = qla2x00_mailbox_command(vha, mcp); 3426 if (rval != QLA_SUCCESS) { 3427 ql_dbg(ql_dbg_mbx, vha, 0x10ab, 3428 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3429 rval, mcp->mb[0], mcp->mb[1]); 3430 } else { 3431 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac, 3432 "Done %s.\n", __func__); 3433 3434 if (mb) 3435 memcpy(mb, mcp->mb, 8 * sizeof(*mb)); 3436 if (dwords) 3437 *dwords = buffers; 3438 } 3439 3440 return rval; 3441 } 3442 3443 int 3444 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd) 3445 { 3446 int rval; 3447 mbx_cmd_t mc; 3448 mbx_cmd_t *mcp = &mc; 3449 3450 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad, 3451 "Entered %s.\n", __func__); 3452 3453 if (!IS_FWI2_CAPABLE(vha->hw)) 3454 return QLA_FUNCTION_FAILED; 3455 3456 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3457 return QLA_FUNCTION_FAILED; 3458 3459 mcp->mb[0] = MBC_TRACE_CONTROL; 3460 mcp->mb[1] = TC_FCE_DISABLE; 3461 mcp->mb[2] = TC_FCE_DISABLE_TRACE; 3462 mcp->out_mb = MBX_2|MBX_1|MBX_0; 3463 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3464 MBX_1|MBX_0; 3465 mcp->tov = MBX_TOV_SECONDS; 3466 mcp->flags = 0; 3467 rval = qla2x00_mailbox_command(vha, mcp); 3468 if (rval != QLA_SUCCESS) { 3469 ql_dbg(ql_dbg_mbx, vha, 0x10ae, 3470 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3471 rval, mcp->mb[0], mcp->mb[1]); 3472 } else { 3473 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af, 3474 "Done %s.\n", __func__); 3475 3476 if (wr) 3477 *wr = (uint64_t) mcp->mb[5] << 48 | 3478 (uint64_t) mcp->mb[4] << 32 | 3479 (uint64_t) mcp->mb[3] << 16 | 3480 (uint64_t) mcp->mb[2]; 3481 if (rd) 3482 *rd = (uint64_t) mcp->mb[9] << 48 | 3483 (uint64_t) mcp->mb[8] << 32 | 3484 (uint64_t) mcp->mb[7] << 16 | 3485 (uint64_t) mcp->mb[6]; 3486 } 3487 3488 return rval; 3489 } 3490 3491 int 3492 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3493 uint16_t *port_speed, uint16_t *mb) 3494 { 3495 int rval; 3496 mbx_cmd_t mc; 3497 mbx_cmd_t *mcp = &mc; 3498 3499 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0, 3500 "Entered %s.\n", __func__); 3501 3502 if (!IS_IIDMA_CAPABLE(vha->hw)) 3503 return QLA_FUNCTION_FAILED; 3504 3505 mcp->mb[0] = MBC_PORT_PARAMS; 3506 mcp->mb[1] = loop_id; 3507 mcp->mb[2] = mcp->mb[3] = 0; 3508 mcp->mb[9] = vha->vp_idx; 3509 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3510 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3511 mcp->tov = MBX_TOV_SECONDS; 3512 mcp->flags = 0; 3513 rval = qla2x00_mailbox_command(vha, mcp); 3514 3515 /* Return mailbox statuses. */ 3516 if (mb != NULL) { 3517 mb[0] = mcp->mb[0]; 3518 mb[1] = mcp->mb[1]; 3519 mb[3] = mcp->mb[3]; 3520 } 3521 3522 if (rval != QLA_SUCCESS) { 3523 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval); 3524 } else { 3525 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2, 3526 "Done %s.\n", __func__); 3527 if (port_speed) 3528 *port_speed = mcp->mb[3]; 3529 } 3530 3531 return rval; 3532 } 3533 3534 int 3535 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3536 uint16_t port_speed, uint16_t *mb) 3537 { 3538 int rval; 3539 mbx_cmd_t mc; 3540 mbx_cmd_t *mcp = &mc; 3541 3542 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3, 3543 "Entered %s.\n", __func__); 3544 3545 if (!IS_IIDMA_CAPABLE(vha->hw)) 3546 return QLA_FUNCTION_FAILED; 3547 3548 mcp->mb[0] = MBC_PORT_PARAMS; 3549 mcp->mb[1] = loop_id; 3550 mcp->mb[2] = BIT_0; 3551 if (IS_CNA_CAPABLE(vha->hw)) 3552 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); 3553 else 3554 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); 3555 mcp->mb[9] = vha->vp_idx; 3556 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3557 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3558 mcp->tov = MBX_TOV_SECONDS; 3559 mcp->flags = 0; 3560 rval = qla2x00_mailbox_command(vha, mcp); 3561 3562 /* Return mailbox statuses. */ 3563 if (mb != NULL) { 3564 mb[0] = mcp->mb[0]; 3565 mb[1] = mcp->mb[1]; 3566 mb[3] = mcp->mb[3]; 3567 } 3568 3569 if (rval != QLA_SUCCESS) { 3570 ql_dbg(ql_dbg_mbx, vha, 0x10b4, 3571 "Failed=%x.\n", rval); 3572 } else { 3573 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5, 3574 "Done %s.\n", __func__); 3575 } 3576 3577 return rval; 3578 } 3579 3580 void 3581 qla24xx_report_id_acquisition(scsi_qla_host_t *vha, 3582 struct vp_rpt_id_entry_24xx *rptid_entry) 3583 { 3584 uint8_t vp_idx; 3585 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx); 3586 struct qla_hw_data *ha = vha->hw; 3587 scsi_qla_host_t *vp; 3588 unsigned long flags; 3589 int found; 3590 3591 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6, 3592 "Entered %s.\n", __func__); 3593 3594 if (rptid_entry->entry_status != 0) 3595 return; 3596 3597 if (rptid_entry->format == 0) { 3598 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7, 3599 "Format 0 : Number of VPs setup %d, number of " 3600 "VPs acquired %d.\n", 3601 MSB(le16_to_cpu(rptid_entry->vp_count)), 3602 LSB(le16_to_cpu(rptid_entry->vp_count))); 3603 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8, 3604 "Primary port id %02x%02x%02x.\n", 3605 rptid_entry->port_id[2], rptid_entry->port_id[1], 3606 rptid_entry->port_id[0]); 3607 } else if (rptid_entry->format == 1) { 3608 vp_idx = LSB(stat); 3609 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9, 3610 "Format 1: VP[%d] enabled - status %d - with " 3611 "port id %02x%02x%02x.\n", vp_idx, MSB(stat), 3612 rptid_entry->port_id[2], rptid_entry->port_id[1], 3613 rptid_entry->port_id[0]); 3614 3615 /* FA-WWN is only for physical port */ 3616 if (!vp_idx) { 3617 void *wwpn = ha->init_cb->port_name; 3618 3619 if (!MSB(stat)) { 3620 if (rptid_entry->vp_idx_map[1] & BIT_6) 3621 wwpn = rptid_entry->reserved_4 + 8; 3622 } 3623 memcpy(vha->port_name, wwpn, WWN_SIZE); 3624 fc_host_port_name(vha->host) = 3625 wwn_to_u64(vha->port_name); 3626 ql_dbg(ql_dbg_mbx, vha, 0x1018, 3627 "FA-WWN portname %016llx (%x)\n", 3628 fc_host_port_name(vha->host), MSB(stat)); 3629 } 3630 3631 vp = vha; 3632 if (vp_idx == 0) 3633 goto reg_needed; 3634 3635 if (MSB(stat) != 0 && MSB(stat) != 2) { 3636 ql_dbg(ql_dbg_mbx, vha, 0x10ba, 3637 "Could not acquire ID for VP[%d].\n", vp_idx); 3638 return; 3639 } 3640 3641 found = 0; 3642 spin_lock_irqsave(&ha->vport_slock, flags); 3643 list_for_each_entry(vp, &ha->vp_list, list) { 3644 if (vp_idx == vp->vp_idx) { 3645 found = 1; 3646 break; 3647 } 3648 } 3649 spin_unlock_irqrestore(&ha->vport_slock, flags); 3650 3651 if (!found) 3652 return; 3653 3654 vp->d_id.b.domain = rptid_entry->port_id[2]; 3655 vp->d_id.b.area = rptid_entry->port_id[1]; 3656 vp->d_id.b.al_pa = rptid_entry->port_id[0]; 3657 3658 /* 3659 * Cannot configure here as we are still sitting on the 3660 * response queue. Handle it in dpc context. 3661 */ 3662 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags); 3663 3664 reg_needed: 3665 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags); 3666 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags); 3667 set_bit(VP_DPC_NEEDED, &vha->dpc_flags); 3668 qla2xxx_wake_dpc(vha); 3669 } 3670 } 3671 3672 /* 3673 * qla24xx_modify_vp_config 3674 * Change VP configuration for vha 3675 * 3676 * Input: 3677 * vha = adapter block pointer. 3678 * 3679 * Returns: 3680 * qla2xxx local function return status code. 3681 * 3682 * Context: 3683 * Kernel context. 3684 */ 3685 int 3686 qla24xx_modify_vp_config(scsi_qla_host_t *vha) 3687 { 3688 int rval; 3689 struct vp_config_entry_24xx *vpmod; 3690 dma_addr_t vpmod_dma; 3691 struct qla_hw_data *ha = vha->hw; 3692 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3693 3694 /* This can be called by the parent */ 3695 3696 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb, 3697 "Entered %s.\n", __func__); 3698 3699 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma); 3700 if (!vpmod) { 3701 ql_log(ql_log_warn, vha, 0x10bc, 3702 "Failed to allocate modify VP IOCB.\n"); 3703 return QLA_MEMORY_ALLOC_FAILED; 3704 } 3705 3706 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx)); 3707 vpmod->entry_type = VP_CONFIG_IOCB_TYPE; 3708 vpmod->entry_count = 1; 3709 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS; 3710 vpmod->vp_count = 1; 3711 vpmod->vp_index1 = vha->vp_idx; 3712 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; 3713 3714 qlt_modify_vp_config(vha, vpmod); 3715 3716 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE); 3717 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE); 3718 vpmod->entry_count = 1; 3719 3720 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0); 3721 if (rval != QLA_SUCCESS) { 3722 ql_dbg(ql_dbg_mbx, vha, 0x10bd, 3723 "Failed to issue VP config IOCB (%x).\n", rval); 3724 } else if (vpmod->comp_status != 0) { 3725 ql_dbg(ql_dbg_mbx, vha, 0x10be, 3726 "Failed to complete IOCB -- error status (%x).\n", 3727 vpmod->comp_status); 3728 rval = QLA_FUNCTION_FAILED; 3729 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) { 3730 ql_dbg(ql_dbg_mbx, vha, 0x10bf, 3731 "Failed to complete IOCB -- completion status (%x).\n", 3732 le16_to_cpu(vpmod->comp_status)); 3733 rval = QLA_FUNCTION_FAILED; 3734 } else { 3735 /* EMPTY */ 3736 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0, 3737 "Done %s.\n", __func__); 3738 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING); 3739 } 3740 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma); 3741 3742 return rval; 3743 } 3744 3745 /* 3746 * qla24xx_control_vp 3747 * Enable a virtual port for given host 3748 * 3749 * Input: 3750 * ha = adapter block pointer. 3751 * vhba = virtual adapter (unused) 3752 * index = index number for enabled VP 3753 * 3754 * Returns: 3755 * qla2xxx local function return status code. 3756 * 3757 * Context: 3758 * Kernel context. 3759 */ 3760 int 3761 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd) 3762 { 3763 int rval; 3764 int map, pos; 3765 struct vp_ctrl_entry_24xx *vce; 3766 dma_addr_t vce_dma; 3767 struct qla_hw_data *ha = vha->hw; 3768 int vp_index = vha->vp_idx; 3769 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3770 3771 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1, 3772 "Entered %s enabling index %d.\n", __func__, vp_index); 3773 3774 if (vp_index == 0 || vp_index >= ha->max_npiv_vports) 3775 return QLA_PARAMETER_ERROR; 3776 3777 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma); 3778 if (!vce) { 3779 ql_log(ql_log_warn, vha, 0x10c2, 3780 "Failed to allocate VP control IOCB.\n"); 3781 return QLA_MEMORY_ALLOC_FAILED; 3782 } 3783 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx)); 3784 3785 vce->entry_type = VP_CTRL_IOCB_TYPE; 3786 vce->entry_count = 1; 3787 vce->command = cpu_to_le16(cmd); 3788 vce->vp_count = cpu_to_le16(1); 3789 3790 /* index map in firmware starts with 1; decrement index 3791 * this is ok as we never use index 0 3792 */ 3793 map = (vp_index - 1) / 8; 3794 pos = (vp_index - 1) & 7; 3795 mutex_lock(&ha->vport_lock); 3796 vce->vp_idx_map[map] |= 1 << pos; 3797 mutex_unlock(&ha->vport_lock); 3798 3799 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0); 3800 if (rval != QLA_SUCCESS) { 3801 ql_dbg(ql_dbg_mbx, vha, 0x10c3, 3802 "Failed to issue VP control IOCB (%x).\n", rval); 3803 } else if (vce->entry_status != 0) { 3804 ql_dbg(ql_dbg_mbx, vha, 0x10c4, 3805 "Failed to complete IOCB -- error status (%x).\n", 3806 vce->entry_status); 3807 rval = QLA_FUNCTION_FAILED; 3808 } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) { 3809 ql_dbg(ql_dbg_mbx, vha, 0x10c5, 3810 "Failed to complet IOCB -- completion status (%x).\n", 3811 le16_to_cpu(vce->comp_status)); 3812 rval = QLA_FUNCTION_FAILED; 3813 } else { 3814 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6, 3815 "Done %s.\n", __func__); 3816 } 3817 3818 dma_pool_free(ha->s_dma_pool, vce, vce_dma); 3819 3820 return rval; 3821 } 3822 3823 /* 3824 * qla2x00_send_change_request 3825 * Receive or disable RSCN request from fabric controller 3826 * 3827 * Input: 3828 * ha = adapter block pointer 3829 * format = registration format: 3830 * 0 - Reserved 3831 * 1 - Fabric detected registration 3832 * 2 - N_port detected registration 3833 * 3 - Full registration 3834 * FF - clear registration 3835 * vp_idx = Virtual port index 3836 * 3837 * Returns: 3838 * qla2x00 local function return status code. 3839 * 3840 * Context: 3841 * Kernel Context 3842 */ 3843 3844 int 3845 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format, 3846 uint16_t vp_idx) 3847 { 3848 int rval; 3849 mbx_cmd_t mc; 3850 mbx_cmd_t *mcp = &mc; 3851 3852 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7, 3853 "Entered %s.\n", __func__); 3854 3855 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST; 3856 mcp->mb[1] = format; 3857 mcp->mb[9] = vp_idx; 3858 mcp->out_mb = MBX_9|MBX_1|MBX_0; 3859 mcp->in_mb = MBX_0|MBX_1; 3860 mcp->tov = MBX_TOV_SECONDS; 3861 mcp->flags = 0; 3862 rval = qla2x00_mailbox_command(vha, mcp); 3863 3864 if (rval == QLA_SUCCESS) { 3865 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 3866 rval = BIT_1; 3867 } 3868 } else 3869 rval = BIT_1; 3870 3871 return rval; 3872 } 3873 3874 int 3875 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 3876 uint32_t size) 3877 { 3878 int rval; 3879 mbx_cmd_t mc; 3880 mbx_cmd_t *mcp = &mc; 3881 3882 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009, 3883 "Entered %s.\n", __func__); 3884 3885 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) { 3886 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 3887 mcp->mb[8] = MSW(addr); 3888 mcp->out_mb = MBX_8|MBX_0; 3889 } else { 3890 mcp->mb[0] = MBC_DUMP_RISC_RAM; 3891 mcp->out_mb = MBX_0; 3892 } 3893 mcp->mb[1] = LSW(addr); 3894 mcp->mb[2] = MSW(req_dma); 3895 mcp->mb[3] = LSW(req_dma); 3896 mcp->mb[6] = MSW(MSD(req_dma)); 3897 mcp->mb[7] = LSW(MSD(req_dma)); 3898 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 3899 if (IS_FWI2_CAPABLE(vha->hw)) { 3900 mcp->mb[4] = MSW(size); 3901 mcp->mb[5] = LSW(size); 3902 mcp->out_mb |= MBX_5|MBX_4; 3903 } else { 3904 mcp->mb[4] = LSW(size); 3905 mcp->out_mb |= MBX_4; 3906 } 3907 3908 mcp->in_mb = MBX_0; 3909 mcp->tov = MBX_TOV_SECONDS; 3910 mcp->flags = 0; 3911 rval = qla2x00_mailbox_command(vha, mcp); 3912 3913 if (rval != QLA_SUCCESS) { 3914 ql_dbg(ql_dbg_mbx, vha, 0x1008, 3915 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3916 } else { 3917 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007, 3918 "Done %s.\n", __func__); 3919 } 3920 3921 return rval; 3922 } 3923 /* 84XX Support **************************************************************/ 3924 3925 struct cs84xx_mgmt_cmd { 3926 union { 3927 struct verify_chip_entry_84xx req; 3928 struct verify_chip_rsp_84xx rsp; 3929 } p; 3930 }; 3931 3932 int 3933 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status) 3934 { 3935 int rval, retry; 3936 struct cs84xx_mgmt_cmd *mn; 3937 dma_addr_t mn_dma; 3938 uint16_t options; 3939 unsigned long flags; 3940 struct qla_hw_data *ha = vha->hw; 3941 3942 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8, 3943 "Entered %s.\n", __func__); 3944 3945 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma); 3946 if (mn == NULL) { 3947 return QLA_MEMORY_ALLOC_FAILED; 3948 } 3949 3950 /* Force Update? */ 3951 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0; 3952 /* Diagnostic firmware? */ 3953 /* options |= MENLO_DIAG_FW; */ 3954 /* We update the firmware with only one data sequence. */ 3955 options |= VCO_END_OF_DATA; 3956 3957 do { 3958 retry = 0; 3959 memset(mn, 0, sizeof(*mn)); 3960 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE; 3961 mn->p.req.entry_count = 1; 3962 mn->p.req.options = cpu_to_le16(options); 3963 3964 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c, 3965 "Dump of Verify Request.\n"); 3966 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e, 3967 (uint8_t *)mn, sizeof(*mn)); 3968 3969 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120); 3970 if (rval != QLA_SUCCESS) { 3971 ql_dbg(ql_dbg_mbx, vha, 0x10cb, 3972 "Failed to issue verify IOCB (%x).\n", rval); 3973 goto verify_done; 3974 } 3975 3976 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110, 3977 "Dump of Verify Response.\n"); 3978 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118, 3979 (uint8_t *)mn, sizeof(*mn)); 3980 3981 status[0] = le16_to_cpu(mn->p.rsp.comp_status); 3982 status[1] = status[0] == CS_VCS_CHIP_FAILURE ? 3983 le16_to_cpu(mn->p.rsp.failure_code) : 0; 3984 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce, 3985 "cs=%x fc=%x.\n", status[0], status[1]); 3986 3987 if (status[0] != CS_COMPLETE) { 3988 rval = QLA_FUNCTION_FAILED; 3989 if (!(options & VCO_DONT_UPDATE_FW)) { 3990 ql_dbg(ql_dbg_mbx, vha, 0x10cf, 3991 "Firmware update failed. Retrying " 3992 "without update firmware.\n"); 3993 options |= VCO_DONT_UPDATE_FW; 3994 options &= ~VCO_FORCE_UPDATE; 3995 retry = 1; 3996 } 3997 } else { 3998 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0, 3999 "Firmware updated to %x.\n", 4000 le32_to_cpu(mn->p.rsp.fw_ver)); 4001 4002 /* NOTE: we only update OP firmware. */ 4003 spin_lock_irqsave(&ha->cs84xx->access_lock, flags); 4004 ha->cs84xx->op_fw_version = 4005 le32_to_cpu(mn->p.rsp.fw_ver); 4006 spin_unlock_irqrestore(&ha->cs84xx->access_lock, 4007 flags); 4008 } 4009 } while (retry); 4010 4011 verify_done: 4012 dma_pool_free(ha->s_dma_pool, mn, mn_dma); 4013 4014 if (rval != QLA_SUCCESS) { 4015 ql_dbg(ql_dbg_mbx, vha, 0x10d1, 4016 "Failed=%x.\n", rval); 4017 } else { 4018 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2, 4019 "Done %s.\n", __func__); 4020 } 4021 4022 return rval; 4023 } 4024 4025 int 4026 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req) 4027 { 4028 int rval; 4029 unsigned long flags; 4030 mbx_cmd_t mc; 4031 mbx_cmd_t *mcp = &mc; 4032 struct qla_hw_data *ha = vha->hw; 4033 4034 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3, 4035 "Entered %s.\n", __func__); 4036 4037 if (IS_SHADOW_REG_CAPABLE(ha)) 4038 req->options |= BIT_13; 4039 4040 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 4041 mcp->mb[1] = req->options; 4042 mcp->mb[2] = MSW(LSD(req->dma)); 4043 mcp->mb[3] = LSW(LSD(req->dma)); 4044 mcp->mb[6] = MSW(MSD(req->dma)); 4045 mcp->mb[7] = LSW(MSD(req->dma)); 4046 mcp->mb[5] = req->length; 4047 if (req->rsp) 4048 mcp->mb[10] = req->rsp->id; 4049 mcp->mb[12] = req->qos; 4050 mcp->mb[11] = req->vp_idx; 4051 mcp->mb[13] = req->rid; 4052 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4053 mcp->mb[15] = 0; 4054 4055 mcp->mb[4] = req->id; 4056 /* que in ptr index */ 4057 mcp->mb[8] = 0; 4058 /* que out ptr index */ 4059 mcp->mb[9] = *req->out_ptr = 0; 4060 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7| 4061 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4062 mcp->in_mb = MBX_0; 4063 mcp->flags = MBX_DMA_OUT; 4064 mcp->tov = MBX_TOV_SECONDS * 2; 4065 4066 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4067 mcp->in_mb |= MBX_1; 4068 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 4069 mcp->out_mb |= MBX_15; 4070 /* debug q create issue in SR-IOV */ 4071 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 4072 } 4073 4074 spin_lock_irqsave(&ha->hardware_lock, flags); 4075 if (!(req->options & BIT_0)) { 4076 WRT_REG_DWORD(req->req_q_in, 0); 4077 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 4078 WRT_REG_DWORD(req->req_q_out, 0); 4079 } 4080 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4081 4082 rval = qla2x00_mailbox_command(vha, mcp); 4083 if (rval != QLA_SUCCESS) { 4084 ql_dbg(ql_dbg_mbx, vha, 0x10d4, 4085 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4086 } else { 4087 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5, 4088 "Done %s.\n", __func__); 4089 } 4090 4091 return rval; 4092 } 4093 4094 int 4095 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp) 4096 { 4097 int rval; 4098 unsigned long flags; 4099 mbx_cmd_t mc; 4100 mbx_cmd_t *mcp = &mc; 4101 struct qla_hw_data *ha = vha->hw; 4102 4103 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6, 4104 "Entered %s.\n", __func__); 4105 4106 if (IS_SHADOW_REG_CAPABLE(ha)) 4107 rsp->options |= BIT_13; 4108 4109 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 4110 mcp->mb[1] = rsp->options; 4111 mcp->mb[2] = MSW(LSD(rsp->dma)); 4112 mcp->mb[3] = LSW(LSD(rsp->dma)); 4113 mcp->mb[6] = MSW(MSD(rsp->dma)); 4114 mcp->mb[7] = LSW(MSD(rsp->dma)); 4115 mcp->mb[5] = rsp->length; 4116 mcp->mb[14] = rsp->msix->entry; 4117 mcp->mb[13] = rsp->rid; 4118 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4119 mcp->mb[15] = 0; 4120 4121 mcp->mb[4] = rsp->id; 4122 /* que in ptr index */ 4123 mcp->mb[8] = *rsp->in_ptr = 0; 4124 /* que out ptr index */ 4125 mcp->mb[9] = 0; 4126 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7 4127 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4128 mcp->in_mb = MBX_0; 4129 mcp->flags = MBX_DMA_OUT; 4130 mcp->tov = MBX_TOV_SECONDS * 2; 4131 4132 if (IS_QLA81XX(ha)) { 4133 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 4134 mcp->in_mb |= MBX_1; 4135 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 4136 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10; 4137 mcp->in_mb |= MBX_1; 4138 /* debug q create issue in SR-IOV */ 4139 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 4140 } 4141 4142 spin_lock_irqsave(&ha->hardware_lock, flags); 4143 if (!(rsp->options & BIT_0)) { 4144 WRT_REG_DWORD(rsp->rsp_q_out, 0); 4145 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 4146 WRT_REG_DWORD(rsp->rsp_q_in, 0); 4147 } 4148 4149 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4150 4151 rval = qla2x00_mailbox_command(vha, mcp); 4152 if (rval != QLA_SUCCESS) { 4153 ql_dbg(ql_dbg_mbx, vha, 0x10d7, 4154 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4155 } else { 4156 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8, 4157 "Done %s.\n", __func__); 4158 } 4159 4160 return rval; 4161 } 4162 4163 int 4164 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb) 4165 { 4166 int rval; 4167 mbx_cmd_t mc; 4168 mbx_cmd_t *mcp = &mc; 4169 4170 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9, 4171 "Entered %s.\n", __func__); 4172 4173 mcp->mb[0] = MBC_IDC_ACK; 4174 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4175 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4176 mcp->in_mb = MBX_0; 4177 mcp->tov = MBX_TOV_SECONDS; 4178 mcp->flags = 0; 4179 rval = qla2x00_mailbox_command(vha, mcp); 4180 4181 if (rval != QLA_SUCCESS) { 4182 ql_dbg(ql_dbg_mbx, vha, 0x10da, 4183 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4184 } else { 4185 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db, 4186 "Done %s.\n", __func__); 4187 } 4188 4189 return rval; 4190 } 4191 4192 int 4193 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size) 4194 { 4195 int rval; 4196 mbx_cmd_t mc; 4197 mbx_cmd_t *mcp = &mc; 4198 4199 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc, 4200 "Entered %s.\n", __func__); 4201 4202 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4203 !IS_QLA27XX(vha->hw)) 4204 return QLA_FUNCTION_FAILED; 4205 4206 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4207 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE; 4208 mcp->out_mb = MBX_1|MBX_0; 4209 mcp->in_mb = MBX_1|MBX_0; 4210 mcp->tov = MBX_TOV_SECONDS; 4211 mcp->flags = 0; 4212 rval = qla2x00_mailbox_command(vha, mcp); 4213 4214 if (rval != QLA_SUCCESS) { 4215 ql_dbg(ql_dbg_mbx, vha, 0x10dd, 4216 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4217 rval, mcp->mb[0], mcp->mb[1]); 4218 } else { 4219 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de, 4220 "Done %s.\n", __func__); 4221 *sector_size = mcp->mb[1]; 4222 } 4223 4224 return rval; 4225 } 4226 4227 int 4228 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable) 4229 { 4230 int rval; 4231 mbx_cmd_t mc; 4232 mbx_cmd_t *mcp = &mc; 4233 4234 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4235 !IS_QLA27XX(vha->hw)) 4236 return QLA_FUNCTION_FAILED; 4237 4238 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df, 4239 "Entered %s.\n", __func__); 4240 4241 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4242 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE : 4243 FAC_OPT_CMD_WRITE_PROTECT; 4244 mcp->out_mb = MBX_1|MBX_0; 4245 mcp->in_mb = MBX_1|MBX_0; 4246 mcp->tov = MBX_TOV_SECONDS; 4247 mcp->flags = 0; 4248 rval = qla2x00_mailbox_command(vha, mcp); 4249 4250 if (rval != QLA_SUCCESS) { 4251 ql_dbg(ql_dbg_mbx, vha, 0x10e0, 4252 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4253 rval, mcp->mb[0], mcp->mb[1]); 4254 } else { 4255 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1, 4256 "Done %s.\n", __func__); 4257 } 4258 4259 return rval; 4260 } 4261 4262 int 4263 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish) 4264 { 4265 int rval; 4266 mbx_cmd_t mc; 4267 mbx_cmd_t *mcp = &mc; 4268 4269 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4270 !IS_QLA27XX(vha->hw)) 4271 return QLA_FUNCTION_FAILED; 4272 4273 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2, 4274 "Entered %s.\n", __func__); 4275 4276 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4277 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR; 4278 mcp->mb[2] = LSW(start); 4279 mcp->mb[3] = MSW(start); 4280 mcp->mb[4] = LSW(finish); 4281 mcp->mb[5] = MSW(finish); 4282 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4283 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4284 mcp->tov = MBX_TOV_SECONDS; 4285 mcp->flags = 0; 4286 rval = qla2x00_mailbox_command(vha, mcp); 4287 4288 if (rval != QLA_SUCCESS) { 4289 ql_dbg(ql_dbg_mbx, vha, 0x10e3, 4290 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4291 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4292 } else { 4293 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4, 4294 "Done %s.\n", __func__); 4295 } 4296 4297 return rval; 4298 } 4299 4300 int 4301 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha) 4302 { 4303 int rval = 0; 4304 mbx_cmd_t mc; 4305 mbx_cmd_t *mcp = &mc; 4306 4307 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5, 4308 "Entered %s.\n", __func__); 4309 4310 mcp->mb[0] = MBC_RESTART_MPI_FW; 4311 mcp->out_mb = MBX_0; 4312 mcp->in_mb = MBX_0|MBX_1; 4313 mcp->tov = MBX_TOV_SECONDS; 4314 mcp->flags = 0; 4315 rval = qla2x00_mailbox_command(vha, mcp); 4316 4317 if (rval != QLA_SUCCESS) { 4318 ql_dbg(ql_dbg_mbx, vha, 0x10e6, 4319 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4320 rval, mcp->mb[0], mcp->mb[1]); 4321 } else { 4322 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7, 4323 "Done %s.\n", __func__); 4324 } 4325 4326 return rval; 4327 } 4328 4329 int 4330 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4331 { 4332 int rval; 4333 mbx_cmd_t mc; 4334 mbx_cmd_t *mcp = &mc; 4335 int i; 4336 int len; 4337 uint16_t *str; 4338 struct qla_hw_data *ha = vha->hw; 4339 4340 if (!IS_P3P_TYPE(ha)) 4341 return QLA_FUNCTION_FAILED; 4342 4343 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b, 4344 "Entered %s.\n", __func__); 4345 4346 str = (void *)version; 4347 len = strlen(version); 4348 4349 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4350 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8; 4351 mcp->out_mb = MBX_1|MBX_0; 4352 for (i = 4; i < 16 && len; i++, str++, len -= 2) { 4353 mcp->mb[i] = cpu_to_le16p(str); 4354 mcp->out_mb |= 1<<i; 4355 } 4356 for (; i < 16; i++) { 4357 mcp->mb[i] = 0; 4358 mcp->out_mb |= 1<<i; 4359 } 4360 mcp->in_mb = MBX_1|MBX_0; 4361 mcp->tov = MBX_TOV_SECONDS; 4362 mcp->flags = 0; 4363 rval = qla2x00_mailbox_command(vha, mcp); 4364 4365 if (rval != QLA_SUCCESS) { 4366 ql_dbg(ql_dbg_mbx, vha, 0x117c, 4367 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4368 } else { 4369 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d, 4370 "Done %s.\n", __func__); 4371 } 4372 4373 return rval; 4374 } 4375 4376 int 4377 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4378 { 4379 int rval; 4380 mbx_cmd_t mc; 4381 mbx_cmd_t *mcp = &mc; 4382 int len; 4383 uint16_t dwlen; 4384 uint8_t *str; 4385 dma_addr_t str_dma; 4386 struct qla_hw_data *ha = vha->hw; 4387 4388 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) || 4389 IS_P3P_TYPE(ha)) 4390 return QLA_FUNCTION_FAILED; 4391 4392 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e, 4393 "Entered %s.\n", __func__); 4394 4395 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma); 4396 if (!str) { 4397 ql_log(ql_log_warn, vha, 0x117f, 4398 "Failed to allocate driver version param.\n"); 4399 return QLA_MEMORY_ALLOC_FAILED; 4400 } 4401 4402 memcpy(str, "\x7\x3\x11\x0", 4); 4403 dwlen = str[0]; 4404 len = dwlen * 4 - 4; 4405 memset(str + 4, 0, len); 4406 if (len > strlen(version)) 4407 len = strlen(version); 4408 memcpy(str + 4, version, len); 4409 4410 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4411 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen; 4412 mcp->mb[2] = MSW(LSD(str_dma)); 4413 mcp->mb[3] = LSW(LSD(str_dma)); 4414 mcp->mb[6] = MSW(MSD(str_dma)); 4415 mcp->mb[7] = LSW(MSD(str_dma)); 4416 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4417 mcp->in_mb = MBX_1|MBX_0; 4418 mcp->tov = MBX_TOV_SECONDS; 4419 mcp->flags = 0; 4420 rval = qla2x00_mailbox_command(vha, mcp); 4421 4422 if (rval != QLA_SUCCESS) { 4423 ql_dbg(ql_dbg_mbx, vha, 0x1180, 4424 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4425 } else { 4426 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181, 4427 "Done %s.\n", __func__); 4428 } 4429 4430 dma_pool_free(ha->s_dma_pool, str, str_dma); 4431 4432 return rval; 4433 } 4434 4435 static int 4436 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp) 4437 { 4438 int rval; 4439 mbx_cmd_t mc; 4440 mbx_cmd_t *mcp = &mc; 4441 4442 if (!IS_FWI2_CAPABLE(vha->hw)) 4443 return QLA_FUNCTION_FAILED; 4444 4445 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159, 4446 "Entered %s.\n", __func__); 4447 4448 mcp->mb[0] = MBC_GET_RNID_PARAMS; 4449 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8; 4450 mcp->out_mb = MBX_1|MBX_0; 4451 mcp->in_mb = MBX_1|MBX_0; 4452 mcp->tov = MBX_TOV_SECONDS; 4453 mcp->flags = 0; 4454 rval = qla2x00_mailbox_command(vha, mcp); 4455 *temp = mcp->mb[1]; 4456 4457 if (rval != QLA_SUCCESS) { 4458 ql_dbg(ql_dbg_mbx, vha, 0x115a, 4459 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4460 } else { 4461 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b, 4462 "Done %s.\n", __func__); 4463 } 4464 4465 return rval; 4466 } 4467 4468 int 4469 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4470 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4471 { 4472 int rval; 4473 mbx_cmd_t mc; 4474 mbx_cmd_t *mcp = &mc; 4475 struct qla_hw_data *ha = vha->hw; 4476 4477 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8, 4478 "Entered %s.\n", __func__); 4479 4480 if (!IS_FWI2_CAPABLE(ha)) 4481 return QLA_FUNCTION_FAILED; 4482 4483 if (len == 1) 4484 opt |= BIT_0; 4485 4486 mcp->mb[0] = MBC_READ_SFP; 4487 mcp->mb[1] = dev; 4488 mcp->mb[2] = MSW(sfp_dma); 4489 mcp->mb[3] = LSW(sfp_dma); 4490 mcp->mb[6] = MSW(MSD(sfp_dma)); 4491 mcp->mb[7] = LSW(MSD(sfp_dma)); 4492 mcp->mb[8] = len; 4493 mcp->mb[9] = off; 4494 mcp->mb[10] = opt; 4495 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4496 mcp->in_mb = MBX_1|MBX_0; 4497 mcp->tov = MBX_TOV_SECONDS; 4498 mcp->flags = 0; 4499 rval = qla2x00_mailbox_command(vha, mcp); 4500 4501 if (opt & BIT_0) 4502 *sfp = mcp->mb[1]; 4503 4504 if (rval != QLA_SUCCESS) { 4505 ql_dbg(ql_dbg_mbx, vha, 0x10e9, 4506 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4507 } else { 4508 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea, 4509 "Done %s.\n", __func__); 4510 } 4511 4512 return rval; 4513 } 4514 4515 int 4516 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4517 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4518 { 4519 int rval; 4520 mbx_cmd_t mc; 4521 mbx_cmd_t *mcp = &mc; 4522 struct qla_hw_data *ha = vha->hw; 4523 4524 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb, 4525 "Entered %s.\n", __func__); 4526 4527 if (!IS_FWI2_CAPABLE(ha)) 4528 return QLA_FUNCTION_FAILED; 4529 4530 if (len == 1) 4531 opt |= BIT_0; 4532 4533 if (opt & BIT_0) 4534 len = *sfp; 4535 4536 mcp->mb[0] = MBC_WRITE_SFP; 4537 mcp->mb[1] = dev; 4538 mcp->mb[2] = MSW(sfp_dma); 4539 mcp->mb[3] = LSW(sfp_dma); 4540 mcp->mb[6] = MSW(MSD(sfp_dma)); 4541 mcp->mb[7] = LSW(MSD(sfp_dma)); 4542 mcp->mb[8] = len; 4543 mcp->mb[9] = off; 4544 mcp->mb[10] = opt; 4545 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4546 mcp->in_mb = MBX_1|MBX_0; 4547 mcp->tov = MBX_TOV_SECONDS; 4548 mcp->flags = 0; 4549 rval = qla2x00_mailbox_command(vha, mcp); 4550 4551 if (rval != QLA_SUCCESS) { 4552 ql_dbg(ql_dbg_mbx, vha, 0x10ec, 4553 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4554 } else { 4555 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed, 4556 "Done %s.\n", __func__); 4557 } 4558 4559 return rval; 4560 } 4561 4562 int 4563 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma, 4564 uint16_t size_in_bytes, uint16_t *actual_size) 4565 { 4566 int rval; 4567 mbx_cmd_t mc; 4568 mbx_cmd_t *mcp = &mc; 4569 4570 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee, 4571 "Entered %s.\n", __func__); 4572 4573 if (!IS_CNA_CAPABLE(vha->hw)) 4574 return QLA_FUNCTION_FAILED; 4575 4576 mcp->mb[0] = MBC_GET_XGMAC_STATS; 4577 mcp->mb[2] = MSW(stats_dma); 4578 mcp->mb[3] = LSW(stats_dma); 4579 mcp->mb[6] = MSW(MSD(stats_dma)); 4580 mcp->mb[7] = LSW(MSD(stats_dma)); 4581 mcp->mb[8] = size_in_bytes >> 2; 4582 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 4583 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4584 mcp->tov = MBX_TOV_SECONDS; 4585 mcp->flags = 0; 4586 rval = qla2x00_mailbox_command(vha, mcp); 4587 4588 if (rval != QLA_SUCCESS) { 4589 ql_dbg(ql_dbg_mbx, vha, 0x10ef, 4590 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4591 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4592 } else { 4593 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0, 4594 "Done %s.\n", __func__); 4595 4596 4597 *actual_size = mcp->mb[2] << 2; 4598 } 4599 4600 return rval; 4601 } 4602 4603 int 4604 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma, 4605 uint16_t size) 4606 { 4607 int rval; 4608 mbx_cmd_t mc; 4609 mbx_cmd_t *mcp = &mc; 4610 4611 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1, 4612 "Entered %s.\n", __func__); 4613 4614 if (!IS_CNA_CAPABLE(vha->hw)) 4615 return QLA_FUNCTION_FAILED; 4616 4617 mcp->mb[0] = MBC_GET_DCBX_PARAMS; 4618 mcp->mb[1] = 0; 4619 mcp->mb[2] = MSW(tlv_dma); 4620 mcp->mb[3] = LSW(tlv_dma); 4621 mcp->mb[6] = MSW(MSD(tlv_dma)); 4622 mcp->mb[7] = LSW(MSD(tlv_dma)); 4623 mcp->mb[8] = size; 4624 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4625 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4626 mcp->tov = MBX_TOV_SECONDS; 4627 mcp->flags = 0; 4628 rval = qla2x00_mailbox_command(vha, mcp); 4629 4630 if (rval != QLA_SUCCESS) { 4631 ql_dbg(ql_dbg_mbx, vha, 0x10f2, 4632 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4633 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4634 } else { 4635 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3, 4636 "Done %s.\n", __func__); 4637 } 4638 4639 return rval; 4640 } 4641 4642 int 4643 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data) 4644 { 4645 int rval; 4646 mbx_cmd_t mc; 4647 mbx_cmd_t *mcp = &mc; 4648 4649 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4, 4650 "Entered %s.\n", __func__); 4651 4652 if (!IS_FWI2_CAPABLE(vha->hw)) 4653 return QLA_FUNCTION_FAILED; 4654 4655 mcp->mb[0] = MBC_READ_RAM_EXTENDED; 4656 mcp->mb[1] = LSW(risc_addr); 4657 mcp->mb[8] = MSW(risc_addr); 4658 mcp->out_mb = MBX_8|MBX_1|MBX_0; 4659 mcp->in_mb = MBX_3|MBX_2|MBX_0; 4660 mcp->tov = 30; 4661 mcp->flags = 0; 4662 rval = qla2x00_mailbox_command(vha, mcp); 4663 if (rval != QLA_SUCCESS) { 4664 ql_dbg(ql_dbg_mbx, vha, 0x10f5, 4665 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4666 } else { 4667 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6, 4668 "Done %s.\n", __func__); 4669 *data = mcp->mb[3] << 16 | mcp->mb[2]; 4670 } 4671 4672 return rval; 4673 } 4674 4675 int 4676 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4677 uint16_t *mresp) 4678 { 4679 int rval; 4680 mbx_cmd_t mc; 4681 mbx_cmd_t *mcp = &mc; 4682 4683 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7, 4684 "Entered %s.\n", __func__); 4685 4686 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4687 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK; 4688 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing 4689 4690 /* transfer count */ 4691 mcp->mb[10] = LSW(mreq->transfer_size); 4692 mcp->mb[11] = MSW(mreq->transfer_size); 4693 4694 /* send data address */ 4695 mcp->mb[14] = LSW(mreq->send_dma); 4696 mcp->mb[15] = MSW(mreq->send_dma); 4697 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4698 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4699 4700 /* receive data address */ 4701 mcp->mb[16] = LSW(mreq->rcv_dma); 4702 mcp->mb[17] = MSW(mreq->rcv_dma); 4703 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4704 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4705 4706 /* Iteration count */ 4707 mcp->mb[18] = LSW(mreq->iteration_count); 4708 mcp->mb[19] = MSW(mreq->iteration_count); 4709 4710 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| 4711 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4712 if (IS_CNA_CAPABLE(vha->hw)) 4713 mcp->out_mb |= MBX_2; 4714 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; 4715 4716 mcp->buf_size = mreq->transfer_size; 4717 mcp->tov = MBX_TOV_SECONDS; 4718 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4719 4720 rval = qla2x00_mailbox_command(vha, mcp); 4721 4722 if (rval != QLA_SUCCESS) { 4723 ql_dbg(ql_dbg_mbx, vha, 0x10f8, 4724 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x " 4725 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], 4726 mcp->mb[3], mcp->mb[18], mcp->mb[19]); 4727 } else { 4728 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9, 4729 "Done %s.\n", __func__); 4730 } 4731 4732 /* Copy mailbox information */ 4733 memcpy( mresp, mcp->mb, 64); 4734 return rval; 4735 } 4736 4737 int 4738 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4739 uint16_t *mresp) 4740 { 4741 int rval; 4742 mbx_cmd_t mc; 4743 mbx_cmd_t *mcp = &mc; 4744 struct qla_hw_data *ha = vha->hw; 4745 4746 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa, 4747 "Entered %s.\n", __func__); 4748 4749 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4750 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; 4751 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */ 4752 if (IS_CNA_CAPABLE(ha)) { 4753 mcp->mb[1] |= BIT_15; 4754 mcp->mb[2] = vha->fcoe_fcf_idx; 4755 } 4756 mcp->mb[16] = LSW(mreq->rcv_dma); 4757 mcp->mb[17] = MSW(mreq->rcv_dma); 4758 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4759 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4760 4761 mcp->mb[10] = LSW(mreq->transfer_size); 4762 4763 mcp->mb[14] = LSW(mreq->send_dma); 4764 mcp->mb[15] = MSW(mreq->send_dma); 4765 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4766 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4767 4768 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| 4769 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4770 if (IS_CNA_CAPABLE(ha)) 4771 mcp->out_mb |= MBX_2; 4772 4773 mcp->in_mb = MBX_0; 4774 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || 4775 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4776 mcp->in_mb |= MBX_1; 4777 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4778 mcp->in_mb |= MBX_3; 4779 4780 mcp->tov = MBX_TOV_SECONDS; 4781 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4782 mcp->buf_size = mreq->transfer_size; 4783 4784 rval = qla2x00_mailbox_command(vha, mcp); 4785 4786 if (rval != QLA_SUCCESS) { 4787 ql_dbg(ql_dbg_mbx, vha, 0x10fb, 4788 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4789 rval, mcp->mb[0], mcp->mb[1]); 4790 } else { 4791 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc, 4792 "Done %s.\n", __func__); 4793 } 4794 4795 /* Copy mailbox information */ 4796 memcpy(mresp, mcp->mb, 64); 4797 return rval; 4798 } 4799 4800 int 4801 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic) 4802 { 4803 int rval; 4804 mbx_cmd_t mc; 4805 mbx_cmd_t *mcp = &mc; 4806 4807 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd, 4808 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic); 4809 4810 mcp->mb[0] = MBC_ISP84XX_RESET; 4811 mcp->mb[1] = enable_diagnostic; 4812 mcp->out_mb = MBX_1|MBX_0; 4813 mcp->in_mb = MBX_1|MBX_0; 4814 mcp->tov = MBX_TOV_SECONDS; 4815 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4816 rval = qla2x00_mailbox_command(vha, mcp); 4817 4818 if (rval != QLA_SUCCESS) 4819 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval); 4820 else 4821 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff, 4822 "Done %s.\n", __func__); 4823 4824 return rval; 4825 } 4826 4827 int 4828 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data) 4829 { 4830 int rval; 4831 mbx_cmd_t mc; 4832 mbx_cmd_t *mcp = &mc; 4833 4834 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100, 4835 "Entered %s.\n", __func__); 4836 4837 if (!IS_FWI2_CAPABLE(vha->hw)) 4838 return QLA_FUNCTION_FAILED; 4839 4840 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED; 4841 mcp->mb[1] = LSW(risc_addr); 4842 mcp->mb[2] = LSW(data); 4843 mcp->mb[3] = MSW(data); 4844 mcp->mb[8] = MSW(risc_addr); 4845 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0; 4846 mcp->in_mb = MBX_0; 4847 mcp->tov = 30; 4848 mcp->flags = 0; 4849 rval = qla2x00_mailbox_command(vha, mcp); 4850 if (rval != QLA_SUCCESS) { 4851 ql_dbg(ql_dbg_mbx, vha, 0x1101, 4852 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4853 } else { 4854 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102, 4855 "Done %s.\n", __func__); 4856 } 4857 4858 return rval; 4859 } 4860 4861 int 4862 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb) 4863 { 4864 int rval; 4865 uint32_t stat, timer; 4866 uint16_t mb0 = 0; 4867 struct qla_hw_data *ha = vha->hw; 4868 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 4869 4870 rval = QLA_SUCCESS; 4871 4872 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103, 4873 "Entered %s.\n", __func__); 4874 4875 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 4876 4877 /* Write the MBC data to the registers */ 4878 WRT_REG_WORD(®->mailbox0, MBC_WRITE_MPI_REGISTER); 4879 WRT_REG_WORD(®->mailbox1, mb[0]); 4880 WRT_REG_WORD(®->mailbox2, mb[1]); 4881 WRT_REG_WORD(®->mailbox3, mb[2]); 4882 WRT_REG_WORD(®->mailbox4, mb[3]); 4883 4884 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 4885 4886 /* Poll for MBC interrupt */ 4887 for (timer = 6000000; timer; timer--) { 4888 /* Check for pending interrupts. */ 4889 stat = RD_REG_DWORD(®->host_status); 4890 if (stat & HSRX_RISC_INT) { 4891 stat &= 0xff; 4892 4893 if (stat == 0x1 || stat == 0x2 || 4894 stat == 0x10 || stat == 0x11) { 4895 set_bit(MBX_INTERRUPT, 4896 &ha->mbx_cmd_flags); 4897 mb0 = RD_REG_WORD(®->mailbox0); 4898 WRT_REG_DWORD(®->hccr, 4899 HCCRX_CLR_RISC_INT); 4900 RD_REG_DWORD(®->hccr); 4901 break; 4902 } 4903 } 4904 udelay(5); 4905 } 4906 4907 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) 4908 rval = mb0 & MBS_MASK; 4909 else 4910 rval = QLA_FUNCTION_FAILED; 4911 4912 if (rval != QLA_SUCCESS) { 4913 ql_dbg(ql_dbg_mbx, vha, 0x1104, 4914 "Failed=%x mb[0]=%x.\n", rval, mb[0]); 4915 } else { 4916 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105, 4917 "Done %s.\n", __func__); 4918 } 4919 4920 return rval; 4921 } 4922 4923 int 4924 qla2x00_get_data_rate(scsi_qla_host_t *vha) 4925 { 4926 int rval; 4927 mbx_cmd_t mc; 4928 mbx_cmd_t *mcp = &mc; 4929 struct qla_hw_data *ha = vha->hw; 4930 4931 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106, 4932 "Entered %s.\n", __func__); 4933 4934 if (!IS_FWI2_CAPABLE(ha)) 4935 return QLA_FUNCTION_FAILED; 4936 4937 mcp->mb[0] = MBC_DATA_RATE; 4938 mcp->mb[1] = 0; 4939 mcp->out_mb = MBX_1|MBX_0; 4940 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4941 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4942 mcp->in_mb |= MBX_3; 4943 mcp->tov = MBX_TOV_SECONDS; 4944 mcp->flags = 0; 4945 rval = qla2x00_mailbox_command(vha, mcp); 4946 if (rval != QLA_SUCCESS) { 4947 ql_dbg(ql_dbg_mbx, vha, 0x1107, 4948 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4949 } else { 4950 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108, 4951 "Done %s.\n", __func__); 4952 if (mcp->mb[1] != 0x7) 4953 ha->link_data_rate = mcp->mb[1]; 4954 } 4955 4956 return rval; 4957 } 4958 4959 int 4960 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb) 4961 { 4962 int rval; 4963 mbx_cmd_t mc; 4964 mbx_cmd_t *mcp = &mc; 4965 struct qla_hw_data *ha = vha->hw; 4966 4967 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109, 4968 "Entered %s.\n", __func__); 4969 4970 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) && 4971 !IS_QLA27XX(ha)) 4972 return QLA_FUNCTION_FAILED; 4973 mcp->mb[0] = MBC_GET_PORT_CONFIG; 4974 mcp->out_mb = MBX_0; 4975 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4976 mcp->tov = MBX_TOV_SECONDS; 4977 mcp->flags = 0; 4978 4979 rval = qla2x00_mailbox_command(vha, mcp); 4980 4981 if (rval != QLA_SUCCESS) { 4982 ql_dbg(ql_dbg_mbx, vha, 0x110a, 4983 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4984 } else { 4985 /* Copy all bits to preserve original value */ 4986 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4); 4987 4988 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b, 4989 "Done %s.\n", __func__); 4990 } 4991 return rval; 4992 } 4993 4994 int 4995 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb) 4996 { 4997 int rval; 4998 mbx_cmd_t mc; 4999 mbx_cmd_t *mcp = &mc; 5000 5001 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c, 5002 "Entered %s.\n", __func__); 5003 5004 mcp->mb[0] = MBC_SET_PORT_CONFIG; 5005 /* Copy all bits to preserve original setting */ 5006 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4); 5007 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5008 mcp->in_mb = MBX_0; 5009 mcp->tov = MBX_TOV_SECONDS; 5010 mcp->flags = 0; 5011 rval = qla2x00_mailbox_command(vha, mcp); 5012 5013 if (rval != QLA_SUCCESS) { 5014 ql_dbg(ql_dbg_mbx, vha, 0x110d, 5015 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5016 } else 5017 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e, 5018 "Done %s.\n", __func__); 5019 5020 return rval; 5021 } 5022 5023 5024 int 5025 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority, 5026 uint16_t *mb) 5027 { 5028 int rval; 5029 mbx_cmd_t mc; 5030 mbx_cmd_t *mcp = &mc; 5031 struct qla_hw_data *ha = vha->hw; 5032 5033 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f, 5034 "Entered %s.\n", __func__); 5035 5036 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 5037 return QLA_FUNCTION_FAILED; 5038 5039 mcp->mb[0] = MBC_PORT_PARAMS; 5040 mcp->mb[1] = loop_id; 5041 if (ha->flags.fcp_prio_enabled) 5042 mcp->mb[2] = BIT_1; 5043 else 5044 mcp->mb[2] = BIT_2; 5045 mcp->mb[4] = priority & 0xf; 5046 mcp->mb[9] = vha->vp_idx; 5047 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5048 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5049 mcp->tov = 30; 5050 mcp->flags = 0; 5051 rval = qla2x00_mailbox_command(vha, mcp); 5052 if (mb != NULL) { 5053 mb[0] = mcp->mb[0]; 5054 mb[1] = mcp->mb[1]; 5055 mb[3] = mcp->mb[3]; 5056 mb[4] = mcp->mb[4]; 5057 } 5058 5059 if (rval != QLA_SUCCESS) { 5060 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval); 5061 } else { 5062 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc, 5063 "Done %s.\n", __func__); 5064 } 5065 5066 return rval; 5067 } 5068 5069 int 5070 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp) 5071 { 5072 int rval = QLA_FUNCTION_FAILED; 5073 struct qla_hw_data *ha = vha->hw; 5074 uint8_t byte; 5075 5076 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) { 5077 ql_dbg(ql_dbg_mbx, vha, 0x1150, 5078 "Thermal not supported by this card.\n"); 5079 return rval; 5080 } 5081 5082 if (IS_QLA25XX(ha)) { 5083 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 5084 ha->pdev->subsystem_device == 0x0175) { 5085 rval = qla2x00_read_sfp(vha, 0, &byte, 5086 0x98, 0x1, 1, BIT_13|BIT_0); 5087 *temp = byte; 5088 return rval; 5089 } 5090 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 5091 ha->pdev->subsystem_device == 0x338e) { 5092 rval = qla2x00_read_sfp(vha, 0, &byte, 5093 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0); 5094 *temp = byte; 5095 return rval; 5096 } 5097 ql_dbg(ql_dbg_mbx, vha, 0x10c9, 5098 "Thermal not supported by this card.\n"); 5099 return rval; 5100 } 5101 5102 if (IS_QLA82XX(ha)) { 5103 *temp = qla82xx_read_temperature(vha); 5104 rval = QLA_SUCCESS; 5105 return rval; 5106 } else if (IS_QLA8044(ha)) { 5107 *temp = qla8044_read_temperature(vha); 5108 rval = QLA_SUCCESS; 5109 return rval; 5110 } 5111 5112 rval = qla2x00_read_asic_temperature(vha, temp); 5113 return rval; 5114 } 5115 5116 int 5117 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha) 5118 { 5119 int rval; 5120 struct qla_hw_data *ha = vha->hw; 5121 mbx_cmd_t mc; 5122 mbx_cmd_t *mcp = &mc; 5123 5124 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017, 5125 "Entered %s.\n", __func__); 5126 5127 if (!IS_FWI2_CAPABLE(ha)) 5128 return QLA_FUNCTION_FAILED; 5129 5130 memset(mcp, 0, sizeof(mbx_cmd_t)); 5131 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 5132 mcp->mb[1] = 1; 5133 5134 mcp->out_mb = MBX_1|MBX_0; 5135 mcp->in_mb = MBX_0; 5136 mcp->tov = 30; 5137 mcp->flags = 0; 5138 5139 rval = qla2x00_mailbox_command(vha, mcp); 5140 if (rval != QLA_SUCCESS) { 5141 ql_dbg(ql_dbg_mbx, vha, 0x1016, 5142 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5143 } else { 5144 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e, 5145 "Done %s.\n", __func__); 5146 } 5147 5148 return rval; 5149 } 5150 5151 int 5152 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha) 5153 { 5154 int rval; 5155 struct qla_hw_data *ha = vha->hw; 5156 mbx_cmd_t mc; 5157 mbx_cmd_t *mcp = &mc; 5158 5159 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d, 5160 "Entered %s.\n", __func__); 5161 5162 if (!IS_P3P_TYPE(ha)) 5163 return QLA_FUNCTION_FAILED; 5164 5165 memset(mcp, 0, sizeof(mbx_cmd_t)); 5166 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 5167 mcp->mb[1] = 0; 5168 5169 mcp->out_mb = MBX_1|MBX_0; 5170 mcp->in_mb = MBX_0; 5171 mcp->tov = 30; 5172 mcp->flags = 0; 5173 5174 rval = qla2x00_mailbox_command(vha, mcp); 5175 if (rval != QLA_SUCCESS) { 5176 ql_dbg(ql_dbg_mbx, vha, 0x100c, 5177 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5178 } else { 5179 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b, 5180 "Done %s.\n", __func__); 5181 } 5182 5183 return rval; 5184 } 5185 5186 int 5187 qla82xx_md_get_template_size(scsi_qla_host_t *vha) 5188 { 5189 struct qla_hw_data *ha = vha->hw; 5190 mbx_cmd_t mc; 5191 mbx_cmd_t *mcp = &mc; 5192 int rval = QLA_FUNCTION_FAILED; 5193 5194 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f, 5195 "Entered %s.\n", __func__); 5196 5197 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5198 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5199 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5200 mcp->mb[2] = LSW(RQST_TMPLT_SIZE); 5201 mcp->mb[3] = MSW(RQST_TMPLT_SIZE); 5202 5203 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5204 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| 5205 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5206 5207 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5208 mcp->tov = MBX_TOV_SECONDS; 5209 rval = qla2x00_mailbox_command(vha, mcp); 5210 5211 /* Always copy back return mailbox values. */ 5212 if (rval != QLA_SUCCESS) { 5213 ql_dbg(ql_dbg_mbx, vha, 0x1120, 5214 "mailbox command FAILED=0x%x, subcode=%x.\n", 5215 (mcp->mb[1] << 16) | mcp->mb[0], 5216 (mcp->mb[3] << 16) | mcp->mb[2]); 5217 } else { 5218 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121, 5219 "Done %s.\n", __func__); 5220 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]); 5221 if (!ha->md_template_size) { 5222 ql_dbg(ql_dbg_mbx, vha, 0x1122, 5223 "Null template size obtained.\n"); 5224 rval = QLA_FUNCTION_FAILED; 5225 } 5226 } 5227 return rval; 5228 } 5229 5230 int 5231 qla82xx_md_get_template(scsi_qla_host_t *vha) 5232 { 5233 struct qla_hw_data *ha = vha->hw; 5234 mbx_cmd_t mc; 5235 mbx_cmd_t *mcp = &mc; 5236 int rval = QLA_FUNCTION_FAILED; 5237 5238 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123, 5239 "Entered %s.\n", __func__); 5240 5241 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5242 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5243 if (!ha->md_tmplt_hdr) { 5244 ql_log(ql_log_warn, vha, 0x1124, 5245 "Unable to allocate memory for Minidump template.\n"); 5246 return rval; 5247 } 5248 5249 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5250 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5251 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5252 mcp->mb[2] = LSW(RQST_TMPLT); 5253 mcp->mb[3] = MSW(RQST_TMPLT); 5254 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma)); 5255 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma)); 5256 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma)); 5257 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma)); 5258 mcp->mb[8] = LSW(ha->md_template_size); 5259 mcp->mb[9] = MSW(ha->md_template_size); 5260 5261 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5262 mcp->tov = MBX_TOV_SECONDS; 5263 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5264 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5265 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5266 rval = qla2x00_mailbox_command(vha, mcp); 5267 5268 if (rval != QLA_SUCCESS) { 5269 ql_dbg(ql_dbg_mbx, vha, 0x1125, 5270 "mailbox command FAILED=0x%x, subcode=%x.\n", 5271 ((mcp->mb[1] << 16) | mcp->mb[0]), 5272 ((mcp->mb[3] << 16) | mcp->mb[2])); 5273 } else 5274 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126, 5275 "Done %s.\n", __func__); 5276 return rval; 5277 } 5278 5279 int 5280 qla8044_md_get_template(scsi_qla_host_t *vha) 5281 { 5282 struct qla_hw_data *ha = vha->hw; 5283 mbx_cmd_t mc; 5284 mbx_cmd_t *mcp = &mc; 5285 int rval = QLA_FUNCTION_FAILED; 5286 int offset = 0, size = MINIDUMP_SIZE_36K; 5287 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f, 5288 "Entered %s.\n", __func__); 5289 5290 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5291 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5292 if (!ha->md_tmplt_hdr) { 5293 ql_log(ql_log_warn, vha, 0xb11b, 5294 "Unable to allocate memory for Minidump template.\n"); 5295 return rval; 5296 } 5297 5298 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5299 while (offset < ha->md_template_size) { 5300 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5301 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5302 mcp->mb[2] = LSW(RQST_TMPLT); 5303 mcp->mb[3] = MSW(RQST_TMPLT); 5304 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5305 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5306 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5307 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5308 mcp->mb[8] = LSW(size); 5309 mcp->mb[9] = MSW(size); 5310 mcp->mb[10] = offset & 0x0000FFFF; 5311 mcp->mb[11] = offset & 0xFFFF0000; 5312 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5313 mcp->tov = MBX_TOV_SECONDS; 5314 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5315 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5316 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5317 rval = qla2x00_mailbox_command(vha, mcp); 5318 5319 if (rval != QLA_SUCCESS) { 5320 ql_dbg(ql_dbg_mbx, vha, 0xb11c, 5321 "mailbox command FAILED=0x%x, subcode=%x.\n", 5322 ((mcp->mb[1] << 16) | mcp->mb[0]), 5323 ((mcp->mb[3] << 16) | mcp->mb[2])); 5324 return rval; 5325 } else 5326 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d, 5327 "Done %s.\n", __func__); 5328 offset = offset + size; 5329 } 5330 return rval; 5331 } 5332 5333 int 5334 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5335 { 5336 int rval; 5337 struct qla_hw_data *ha = vha->hw; 5338 mbx_cmd_t mc; 5339 mbx_cmd_t *mcp = &mc; 5340 5341 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5342 return QLA_FUNCTION_FAILED; 5343 5344 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133, 5345 "Entered %s.\n", __func__); 5346 5347 memset(mcp, 0, sizeof(mbx_cmd_t)); 5348 mcp->mb[0] = MBC_SET_LED_CONFIG; 5349 mcp->mb[1] = led_cfg[0]; 5350 mcp->mb[2] = led_cfg[1]; 5351 if (IS_QLA8031(ha)) { 5352 mcp->mb[3] = led_cfg[2]; 5353 mcp->mb[4] = led_cfg[3]; 5354 mcp->mb[5] = led_cfg[4]; 5355 mcp->mb[6] = led_cfg[5]; 5356 } 5357 5358 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5359 if (IS_QLA8031(ha)) 5360 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5361 mcp->in_mb = MBX_0; 5362 mcp->tov = 30; 5363 mcp->flags = 0; 5364 5365 rval = qla2x00_mailbox_command(vha, mcp); 5366 if (rval != QLA_SUCCESS) { 5367 ql_dbg(ql_dbg_mbx, vha, 0x1134, 5368 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5369 } else { 5370 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135, 5371 "Done %s.\n", __func__); 5372 } 5373 5374 return rval; 5375 } 5376 5377 int 5378 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5379 { 5380 int rval; 5381 struct qla_hw_data *ha = vha->hw; 5382 mbx_cmd_t mc; 5383 mbx_cmd_t *mcp = &mc; 5384 5385 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5386 return QLA_FUNCTION_FAILED; 5387 5388 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136, 5389 "Entered %s.\n", __func__); 5390 5391 memset(mcp, 0, sizeof(mbx_cmd_t)); 5392 mcp->mb[0] = MBC_GET_LED_CONFIG; 5393 5394 mcp->out_mb = MBX_0; 5395 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5396 if (IS_QLA8031(ha)) 5397 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5398 mcp->tov = 30; 5399 mcp->flags = 0; 5400 5401 rval = qla2x00_mailbox_command(vha, mcp); 5402 if (rval != QLA_SUCCESS) { 5403 ql_dbg(ql_dbg_mbx, vha, 0x1137, 5404 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5405 } else { 5406 led_cfg[0] = mcp->mb[1]; 5407 led_cfg[1] = mcp->mb[2]; 5408 if (IS_QLA8031(ha)) { 5409 led_cfg[2] = mcp->mb[3]; 5410 led_cfg[3] = mcp->mb[4]; 5411 led_cfg[4] = mcp->mb[5]; 5412 led_cfg[5] = mcp->mb[6]; 5413 } 5414 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138, 5415 "Done %s.\n", __func__); 5416 } 5417 5418 return rval; 5419 } 5420 5421 int 5422 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable) 5423 { 5424 int rval; 5425 struct qla_hw_data *ha = vha->hw; 5426 mbx_cmd_t mc; 5427 mbx_cmd_t *mcp = &mc; 5428 5429 if (!IS_P3P_TYPE(ha)) 5430 return QLA_FUNCTION_FAILED; 5431 5432 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127, 5433 "Entered %s.\n", __func__); 5434 5435 memset(mcp, 0, sizeof(mbx_cmd_t)); 5436 mcp->mb[0] = MBC_SET_LED_CONFIG; 5437 if (enable) 5438 mcp->mb[7] = 0xE; 5439 else 5440 mcp->mb[7] = 0xD; 5441 5442 mcp->out_mb = MBX_7|MBX_0; 5443 mcp->in_mb = MBX_0; 5444 mcp->tov = MBX_TOV_SECONDS; 5445 mcp->flags = 0; 5446 5447 rval = qla2x00_mailbox_command(vha, mcp); 5448 if (rval != QLA_SUCCESS) { 5449 ql_dbg(ql_dbg_mbx, vha, 0x1128, 5450 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5451 } else { 5452 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129, 5453 "Done %s.\n", __func__); 5454 } 5455 5456 return rval; 5457 } 5458 5459 int 5460 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data) 5461 { 5462 int rval; 5463 struct qla_hw_data *ha = vha->hw; 5464 mbx_cmd_t mc; 5465 mbx_cmd_t *mcp = &mc; 5466 5467 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5468 return QLA_FUNCTION_FAILED; 5469 5470 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130, 5471 "Entered %s.\n", __func__); 5472 5473 mcp->mb[0] = MBC_WRITE_REMOTE_REG; 5474 mcp->mb[1] = LSW(reg); 5475 mcp->mb[2] = MSW(reg); 5476 mcp->mb[3] = LSW(data); 5477 mcp->mb[4] = MSW(data); 5478 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5479 5480 mcp->in_mb = MBX_1|MBX_0; 5481 mcp->tov = MBX_TOV_SECONDS; 5482 mcp->flags = 0; 5483 rval = qla2x00_mailbox_command(vha, mcp); 5484 5485 if (rval != QLA_SUCCESS) { 5486 ql_dbg(ql_dbg_mbx, vha, 0x1131, 5487 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5488 } else { 5489 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132, 5490 "Done %s.\n", __func__); 5491 } 5492 5493 return rval; 5494 } 5495 5496 int 5497 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport) 5498 { 5499 int rval; 5500 struct qla_hw_data *ha = vha->hw; 5501 mbx_cmd_t mc; 5502 mbx_cmd_t *mcp = &mc; 5503 5504 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 5505 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b, 5506 "Implicit LOGO Unsupported.\n"); 5507 return QLA_FUNCTION_FAILED; 5508 } 5509 5510 5511 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c, 5512 "Entering %s.\n", __func__); 5513 5514 /* Perform Implicit LOGO. */ 5515 mcp->mb[0] = MBC_PORT_LOGOUT; 5516 mcp->mb[1] = fcport->loop_id; 5517 mcp->mb[10] = BIT_15; 5518 mcp->out_mb = MBX_10|MBX_1|MBX_0; 5519 mcp->in_mb = MBX_0; 5520 mcp->tov = MBX_TOV_SECONDS; 5521 mcp->flags = 0; 5522 rval = qla2x00_mailbox_command(vha, mcp); 5523 if (rval != QLA_SUCCESS) 5524 ql_dbg(ql_dbg_mbx, vha, 0x113d, 5525 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5526 else 5527 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e, 5528 "Done %s.\n", __func__); 5529 5530 return rval; 5531 } 5532 5533 int 5534 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data) 5535 { 5536 int rval; 5537 mbx_cmd_t mc; 5538 mbx_cmd_t *mcp = &mc; 5539 struct qla_hw_data *ha = vha->hw; 5540 unsigned long retry_max_time = jiffies + (2 * HZ); 5541 5542 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5543 return QLA_FUNCTION_FAILED; 5544 5545 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__); 5546 5547 retry_rd_reg: 5548 mcp->mb[0] = MBC_READ_REMOTE_REG; 5549 mcp->mb[1] = LSW(reg); 5550 mcp->mb[2] = MSW(reg); 5551 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5552 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5553 mcp->tov = MBX_TOV_SECONDS; 5554 mcp->flags = 0; 5555 rval = qla2x00_mailbox_command(vha, mcp); 5556 5557 if (rval != QLA_SUCCESS) { 5558 ql_dbg(ql_dbg_mbx, vha, 0x114c, 5559 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5560 rval, mcp->mb[0], mcp->mb[1]); 5561 } else { 5562 *data = (mcp->mb[3] | (mcp->mb[4] << 16)); 5563 if (*data == QLA8XXX_BAD_VALUE) { 5564 /* 5565 * During soft-reset CAMRAM register reads might 5566 * return 0xbad0bad0. So retry for MAX of 2 sec 5567 * while reading camram registers. 5568 */ 5569 if (time_after(jiffies, retry_max_time)) { 5570 ql_dbg(ql_dbg_mbx, vha, 0x1141, 5571 "Failure to read CAMRAM register. " 5572 "data=0x%x.\n", *data); 5573 return QLA_FUNCTION_FAILED; 5574 } 5575 msleep(100); 5576 goto retry_rd_reg; 5577 } 5578 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__); 5579 } 5580 5581 return rval; 5582 } 5583 5584 int 5585 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha) 5586 { 5587 int rval; 5588 mbx_cmd_t mc; 5589 mbx_cmd_t *mcp = &mc; 5590 struct qla_hw_data *ha = vha->hw; 5591 5592 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5593 return QLA_FUNCTION_FAILED; 5594 5595 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__); 5596 5597 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE; 5598 mcp->out_mb = MBX_0; 5599 mcp->in_mb = MBX_1|MBX_0; 5600 mcp->tov = MBX_TOV_SECONDS; 5601 mcp->flags = 0; 5602 rval = qla2x00_mailbox_command(vha, mcp); 5603 5604 if (rval != QLA_SUCCESS) { 5605 ql_dbg(ql_dbg_mbx, vha, 0x1144, 5606 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5607 rval, mcp->mb[0], mcp->mb[1]); 5608 ha->isp_ops->fw_dump(vha, 0); 5609 } else { 5610 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__); 5611 } 5612 5613 return rval; 5614 } 5615 5616 int 5617 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options, 5618 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size) 5619 { 5620 int rval; 5621 mbx_cmd_t mc; 5622 mbx_cmd_t *mcp = &mc; 5623 uint8_t subcode = (uint8_t)options; 5624 struct qla_hw_data *ha = vha->hw; 5625 5626 if (!IS_QLA8031(ha)) 5627 return QLA_FUNCTION_FAILED; 5628 5629 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__); 5630 5631 mcp->mb[0] = MBC_SET_ACCESS_CONTROL; 5632 mcp->mb[1] = options; 5633 mcp->out_mb = MBX_1|MBX_0; 5634 if (subcode & BIT_2) { 5635 mcp->mb[2] = LSW(start_addr); 5636 mcp->mb[3] = MSW(start_addr); 5637 mcp->mb[4] = LSW(end_addr); 5638 mcp->mb[5] = MSW(end_addr); 5639 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2; 5640 } 5641 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5642 if (!(subcode & (BIT_2 | BIT_5))) 5643 mcp->in_mb |= MBX_4|MBX_3; 5644 mcp->tov = MBX_TOV_SECONDS; 5645 mcp->flags = 0; 5646 rval = qla2x00_mailbox_command(vha, mcp); 5647 5648 if (rval != QLA_SUCCESS) { 5649 ql_dbg(ql_dbg_mbx, vha, 0x1147, 5650 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n", 5651 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], 5652 mcp->mb[4]); 5653 ha->isp_ops->fw_dump(vha, 0); 5654 } else { 5655 if (subcode & BIT_5) 5656 *sector_size = mcp->mb[1]; 5657 else if (subcode & (BIT_6 | BIT_7)) { 5658 ql_dbg(ql_dbg_mbx, vha, 0x1148, 5659 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5660 } else if (subcode & (BIT_3 | BIT_4)) { 5661 ql_dbg(ql_dbg_mbx, vha, 0x1149, 5662 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5663 } 5664 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__); 5665 } 5666 5667 return rval; 5668 } 5669 5670 int 5671 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 5672 uint32_t size) 5673 { 5674 int rval; 5675 mbx_cmd_t mc; 5676 mbx_cmd_t *mcp = &mc; 5677 5678 if (!IS_MCTP_CAPABLE(vha->hw)) 5679 return QLA_FUNCTION_FAILED; 5680 5681 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f, 5682 "Entered %s.\n", __func__); 5683 5684 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 5685 mcp->mb[1] = LSW(addr); 5686 mcp->mb[2] = MSW(req_dma); 5687 mcp->mb[3] = LSW(req_dma); 5688 mcp->mb[4] = MSW(size); 5689 mcp->mb[5] = LSW(size); 5690 mcp->mb[6] = MSW(MSD(req_dma)); 5691 mcp->mb[7] = LSW(MSD(req_dma)); 5692 mcp->mb[8] = MSW(addr); 5693 /* Setting RAM ID to valid */ 5694 mcp->mb[10] |= BIT_7; 5695 /* For MCTP RAM ID is 0x40 */ 5696 mcp->mb[10] |= 0x40; 5697 5698 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1| 5699 MBX_0; 5700 5701 mcp->in_mb = MBX_0; 5702 mcp->tov = MBX_TOV_SECONDS; 5703 mcp->flags = 0; 5704 rval = qla2x00_mailbox_command(vha, mcp); 5705 5706 if (rval != QLA_SUCCESS) { 5707 ql_dbg(ql_dbg_mbx, vha, 0x114e, 5708 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5709 } else { 5710 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d, 5711 "Done %s.\n", __func__); 5712 } 5713 5714 return rval; 5715 } 5716