1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_target.h" 9 10 #include <linux/delay.h> 11 #include <linux/gfp.h> 12 13 14 /* 15 * qla2x00_mailbox_command 16 * Issue mailbox command and waits for completion. 17 * 18 * Input: 19 * ha = adapter block pointer. 20 * mcp = driver internal mbx struct pointer. 21 * 22 * Output: 23 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data. 24 * 25 * Returns: 26 * 0 : QLA_SUCCESS = cmd performed success 27 * 1 : QLA_FUNCTION_FAILED (error encountered) 28 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered) 29 * 30 * Context: 31 * Kernel context. 32 */ 33 static int 34 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) 35 { 36 int rval, i; 37 unsigned long flags = 0; 38 device_reg_t *reg; 39 uint8_t abort_active; 40 uint8_t io_lock_on; 41 uint16_t command = 0; 42 uint16_t *iptr; 43 uint16_t __iomem *optr; 44 uint32_t cnt; 45 uint32_t mboxes; 46 uint16_t __iomem *mbx_reg; 47 unsigned long wait_time; 48 struct qla_hw_data *ha = vha->hw; 49 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 50 51 52 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__); 53 54 if (ha->pdev->error_state > pci_channel_io_frozen) { 55 ql_log(ql_log_warn, vha, 0x1001, 56 "error_state is greater than pci_channel_io_frozen, " 57 "exiting.\n"); 58 return QLA_FUNCTION_TIMEOUT; 59 } 60 61 if (vha->device_flags & DFLG_DEV_FAILED) { 62 ql_log(ql_log_warn, vha, 0x1002, 63 "Device in failed state, exiting.\n"); 64 return QLA_FUNCTION_TIMEOUT; 65 } 66 67 reg = ha->iobase; 68 io_lock_on = base_vha->flags.init_done; 69 70 rval = QLA_SUCCESS; 71 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 72 73 74 if (ha->flags.pci_channel_io_perm_failure) { 75 ql_log(ql_log_warn, vha, 0x1003, 76 "Perm failure on EEH timeout MBX, exiting.\n"); 77 return QLA_FUNCTION_TIMEOUT; 78 } 79 80 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 81 /* Setting Link-Down error */ 82 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 83 ql_log(ql_log_warn, vha, 0x1004, 84 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 85 return QLA_FUNCTION_TIMEOUT; 86 } 87 88 /* 89 * Wait for active mailbox commands to finish by waiting at most tov 90 * seconds. This is to serialize actual issuing of mailbox cmds during 91 * non ISP abort time. 92 */ 93 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) { 94 /* Timeout occurred. Return error. */ 95 ql_log(ql_log_warn, vha, 0x1005, 96 "Cmd access timeout, cmd=0x%x, Exiting.\n", 97 mcp->mb[0]); 98 return QLA_FUNCTION_TIMEOUT; 99 } 100 101 ha->flags.mbox_busy = 1; 102 /* Save mailbox command for debug */ 103 ha->mcp = mcp; 104 105 ql_dbg(ql_dbg_mbx, vha, 0x1006, 106 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); 107 108 spin_lock_irqsave(&ha->hardware_lock, flags); 109 110 /* Load mailbox registers. */ 111 if (IS_P3P_TYPE(ha)) 112 optr = (uint16_t __iomem *)®->isp82.mailbox_in[0]; 113 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) 114 optr = (uint16_t __iomem *)®->isp24.mailbox0; 115 else 116 optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); 117 118 iptr = mcp->mb; 119 command = mcp->mb[0]; 120 mboxes = mcp->out_mb; 121 122 ql_dbg(ql_dbg_mbx, vha, 0x1111, 123 "Mailbox registers (OUT):\n"); 124 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 125 if (IS_QLA2200(ha) && cnt == 8) 126 optr = 127 (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 8); 128 if (mboxes & BIT_0) { 129 ql_dbg(ql_dbg_mbx, vha, 0x1112, 130 "mbox[%d]<-0x%04x\n", cnt, *iptr); 131 WRT_REG_WORD(optr, *iptr); 132 } 133 134 mboxes >>= 1; 135 optr++; 136 iptr++; 137 } 138 139 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117, 140 "I/O Address = %p.\n", optr); 141 142 /* Issue set host interrupt command to send cmd out. */ 143 ha->flags.mbox_int = 0; 144 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 145 146 /* Unlock mbx registers and wait for interrupt */ 147 ql_dbg(ql_dbg_mbx, vha, 0x100f, 148 "Going to unlock irq & waiting for interrupts. " 149 "jiffies=%lx.\n", jiffies); 150 151 /* Wait for mbx cmd completion until timeout */ 152 153 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { 154 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 155 156 if (IS_P3P_TYPE(ha)) { 157 if (RD_REG_DWORD(®->isp82.hint) & 158 HINT_MBX_INT_PENDING) { 159 spin_unlock_irqrestore(&ha->hardware_lock, 160 flags); 161 ha->flags.mbox_busy = 0; 162 ql_dbg(ql_dbg_mbx, vha, 0x1010, 163 "Pending mailbox timeout, exiting.\n"); 164 rval = QLA_FUNCTION_TIMEOUT; 165 goto premature_exit; 166 } 167 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 168 } else if (IS_FWI2_CAPABLE(ha)) 169 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 170 else 171 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 172 spin_unlock_irqrestore(&ha->hardware_lock, flags); 173 174 if (!wait_for_completion_timeout(&ha->mbx_intr_comp, 175 mcp->tov * HZ)) { 176 ql_dbg(ql_dbg_mbx, vha, 0x117a, 177 "cmd=%x Timeout.\n", command); 178 spin_lock_irqsave(&ha->hardware_lock, flags); 179 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 180 spin_unlock_irqrestore(&ha->hardware_lock, flags); 181 } 182 } else { 183 ql_dbg(ql_dbg_mbx, vha, 0x1011, 184 "Cmd=%x Polling Mode.\n", command); 185 186 if (IS_P3P_TYPE(ha)) { 187 if (RD_REG_DWORD(®->isp82.hint) & 188 HINT_MBX_INT_PENDING) { 189 spin_unlock_irqrestore(&ha->hardware_lock, 190 flags); 191 ha->flags.mbox_busy = 0; 192 ql_dbg(ql_dbg_mbx, vha, 0x1012, 193 "Pending mailbox timeout, exiting.\n"); 194 rval = QLA_FUNCTION_TIMEOUT; 195 goto premature_exit; 196 } 197 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 198 } else if (IS_FWI2_CAPABLE(ha)) 199 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 200 else 201 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 202 spin_unlock_irqrestore(&ha->hardware_lock, flags); 203 204 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */ 205 while (!ha->flags.mbox_int) { 206 if (time_after(jiffies, wait_time)) 207 break; 208 209 /* Check for pending interrupts. */ 210 qla2x00_poll(ha->rsp_q_map[0]); 211 212 if (!ha->flags.mbox_int && 213 !(IS_QLA2200(ha) && 214 command == MBC_LOAD_RISC_RAM_EXTENDED)) 215 msleep(10); 216 } /* while */ 217 ql_dbg(ql_dbg_mbx, vha, 0x1013, 218 "Waited %d sec.\n", 219 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ)); 220 } 221 222 /* Check whether we timed out */ 223 if (ha->flags.mbox_int) { 224 uint16_t *iptr2; 225 226 ql_dbg(ql_dbg_mbx, vha, 0x1014, 227 "Cmd=%x completed.\n", command); 228 229 /* Got interrupt. Clear the flag. */ 230 ha->flags.mbox_int = 0; 231 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 232 233 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 234 ha->flags.mbox_busy = 0; 235 /* Setting Link-Down error */ 236 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 237 ha->mcp = NULL; 238 rval = QLA_FUNCTION_FAILED; 239 ql_log(ql_log_warn, vha, 0x1015, 240 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 241 goto premature_exit; 242 } 243 244 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) 245 rval = QLA_FUNCTION_FAILED; 246 247 /* Load return mailbox registers. */ 248 iptr2 = mcp->mb; 249 iptr = (uint16_t *)&ha->mailbox_out[0]; 250 mboxes = mcp->in_mb; 251 252 ql_dbg(ql_dbg_mbx, vha, 0x1113, 253 "Mailbox registers (IN):\n"); 254 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 255 if (mboxes & BIT_0) { 256 *iptr2 = *iptr; 257 ql_dbg(ql_dbg_mbx, vha, 0x1114, 258 "mbox[%d]->0x%04x\n", cnt, *iptr2); 259 } 260 261 mboxes >>= 1; 262 iptr2++; 263 iptr++; 264 } 265 } else { 266 267 uint16_t mb0; 268 uint32_t ictrl; 269 270 if (IS_FWI2_CAPABLE(ha)) { 271 mb0 = RD_REG_WORD(®->isp24.mailbox0); 272 ictrl = RD_REG_DWORD(®->isp24.ictrl); 273 } else { 274 mb0 = RD_MAILBOX_REG(ha, ®->isp, 0); 275 ictrl = RD_REG_WORD(®->isp.ictrl); 276 } 277 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119, 278 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx " 279 "mb[0]=0x%x\n", command, ictrl, jiffies, mb0); 280 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019); 281 282 /* 283 * Attempt to capture a firmware dump for further analysis 284 * of the current firmware state. We do not need to do this 285 * if we are intentionally generating a dump. 286 */ 287 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) 288 ha->isp_ops->fw_dump(vha, 0); 289 290 rval = QLA_FUNCTION_TIMEOUT; 291 } 292 293 ha->flags.mbox_busy = 0; 294 295 /* Clean up */ 296 ha->mcp = NULL; 297 298 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) { 299 ql_dbg(ql_dbg_mbx, vha, 0x101a, 300 "Checking for additional resp interrupt.\n"); 301 302 /* polling mode for non isp_abort commands. */ 303 qla2x00_poll(ha->rsp_q_map[0]); 304 } 305 306 if (rval == QLA_FUNCTION_TIMEOUT && 307 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) { 308 if (!io_lock_on || (mcp->flags & IOCTL_CMD) || 309 ha->flags.eeh_busy) { 310 /* not in dpc. schedule it for dpc to take over. */ 311 ql_dbg(ql_dbg_mbx, vha, 0x101b, 312 "Timeout, schedule isp_abort_needed.\n"); 313 314 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 315 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 316 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 317 if (IS_QLA82XX(ha)) { 318 ql_dbg(ql_dbg_mbx, vha, 0x112a, 319 "disabling pause transmit on port " 320 "0 & 1.\n"); 321 qla82xx_wr_32(ha, 322 QLA82XX_CRB_NIU + 0x98, 323 CRB_NIU_XG_PAUSE_CTL_P0| 324 CRB_NIU_XG_PAUSE_CTL_P1); 325 } 326 ql_log(ql_log_info, base_vha, 0x101c, 327 "Mailbox cmd timeout occurred, cmd=0x%x, " 328 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP " 329 "abort.\n", command, mcp->mb[0], 330 ha->flags.eeh_busy); 331 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 332 qla2xxx_wake_dpc(vha); 333 } 334 } else if (!abort_active) { 335 /* call abort directly since we are in the DPC thread */ 336 ql_dbg(ql_dbg_mbx, vha, 0x101d, 337 "Timeout, calling abort_isp.\n"); 338 339 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 340 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 341 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 342 if (IS_QLA82XX(ha)) { 343 ql_dbg(ql_dbg_mbx, vha, 0x112b, 344 "disabling pause transmit on port " 345 "0 & 1.\n"); 346 qla82xx_wr_32(ha, 347 QLA82XX_CRB_NIU + 0x98, 348 CRB_NIU_XG_PAUSE_CTL_P0| 349 CRB_NIU_XG_PAUSE_CTL_P1); 350 } 351 ql_log(ql_log_info, base_vha, 0x101e, 352 "Mailbox cmd timeout occurred, cmd=0x%x, " 353 "mb[0]=0x%x. Scheduling ISP abort ", 354 command, mcp->mb[0]); 355 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 356 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 357 /* Allow next mbx cmd to come in. */ 358 complete(&ha->mbx_cmd_comp); 359 if (ha->isp_ops->abort_isp(vha)) { 360 /* Failed. retry later. */ 361 set_bit(ISP_ABORT_NEEDED, 362 &vha->dpc_flags); 363 } 364 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 365 ql_dbg(ql_dbg_mbx, vha, 0x101f, 366 "Finished abort_isp.\n"); 367 goto mbx_done; 368 } 369 } 370 } 371 372 premature_exit: 373 /* Allow next mbx cmd to come in. */ 374 complete(&ha->mbx_cmd_comp); 375 376 mbx_done: 377 if (rval) { 378 ql_dbg(ql_dbg_disc, base_vha, 0x1020, 379 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n", 380 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command); 381 382 ql_dbg(ql_dbg_disc, vha, 0x1115, 383 "host status: 0x%x, flags:0x%lx, intr ctrl reg:0x%x, intr status:0x%x\n", 384 RD_REG_DWORD(®->isp24.host_status), 385 ha->fw_dump_cap_flags, 386 RD_REG_DWORD(®->isp24.ictrl), 387 RD_REG_DWORD(®->isp24.istatus)); 388 389 mbx_reg = ®->isp24.mailbox0; 390 for (i = 0; i < 6; i++) 391 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x1116, 392 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); 393 } else { 394 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__); 395 } 396 397 return rval; 398 } 399 400 int 401 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr, 402 uint32_t risc_code_size) 403 { 404 int rval; 405 struct qla_hw_data *ha = vha->hw; 406 mbx_cmd_t mc; 407 mbx_cmd_t *mcp = &mc; 408 409 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022, 410 "Entered %s.\n", __func__); 411 412 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) { 413 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; 414 mcp->mb[8] = MSW(risc_addr); 415 mcp->out_mb = MBX_8|MBX_0; 416 } else { 417 mcp->mb[0] = MBC_LOAD_RISC_RAM; 418 mcp->out_mb = MBX_0; 419 } 420 mcp->mb[1] = LSW(risc_addr); 421 mcp->mb[2] = MSW(req_dma); 422 mcp->mb[3] = LSW(req_dma); 423 mcp->mb[6] = MSW(MSD(req_dma)); 424 mcp->mb[7] = LSW(MSD(req_dma)); 425 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 426 if (IS_FWI2_CAPABLE(ha)) { 427 mcp->mb[4] = MSW(risc_code_size); 428 mcp->mb[5] = LSW(risc_code_size); 429 mcp->out_mb |= MBX_5|MBX_4; 430 } else { 431 mcp->mb[4] = LSW(risc_code_size); 432 mcp->out_mb |= MBX_4; 433 } 434 435 mcp->in_mb = MBX_0; 436 mcp->tov = MBX_TOV_SECONDS; 437 mcp->flags = 0; 438 rval = qla2x00_mailbox_command(vha, mcp); 439 440 if (rval != QLA_SUCCESS) { 441 ql_dbg(ql_dbg_mbx, vha, 0x1023, 442 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 443 } else { 444 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024, 445 "Done %s.\n", __func__); 446 } 447 448 return rval; 449 } 450 451 #define EXTENDED_BB_CREDITS BIT_0 452 /* 453 * qla2x00_execute_fw 454 * Start adapter firmware. 455 * 456 * Input: 457 * ha = adapter block pointer. 458 * TARGET_QUEUE_LOCK must be released. 459 * ADAPTER_STATE_LOCK must be released. 460 * 461 * Returns: 462 * qla2x00 local function return status code. 463 * 464 * Context: 465 * Kernel context. 466 */ 467 int 468 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr) 469 { 470 int rval; 471 struct qla_hw_data *ha = vha->hw; 472 mbx_cmd_t mc; 473 mbx_cmd_t *mcp = &mc; 474 475 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025, 476 "Entered %s.\n", __func__); 477 478 mcp->mb[0] = MBC_EXECUTE_FIRMWARE; 479 mcp->out_mb = MBX_0; 480 mcp->in_mb = MBX_0; 481 if (IS_FWI2_CAPABLE(ha)) { 482 mcp->mb[1] = MSW(risc_addr); 483 mcp->mb[2] = LSW(risc_addr); 484 mcp->mb[3] = 0; 485 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 486 IS_QLA27XX(ha)) { 487 struct nvram_81xx *nv = ha->nvram; 488 mcp->mb[4] = (nv->enhanced_features & 489 EXTENDED_BB_CREDITS); 490 } else 491 mcp->mb[4] = 0; 492 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1; 493 mcp->in_mb |= MBX_1; 494 } else { 495 mcp->mb[1] = LSW(risc_addr); 496 mcp->out_mb |= MBX_1; 497 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 498 mcp->mb[2] = 0; 499 mcp->out_mb |= MBX_2; 500 } 501 } 502 503 mcp->tov = MBX_TOV_SECONDS; 504 mcp->flags = 0; 505 rval = qla2x00_mailbox_command(vha, mcp); 506 507 if (rval != QLA_SUCCESS) { 508 ql_dbg(ql_dbg_mbx, vha, 0x1026, 509 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 510 } else { 511 if (IS_FWI2_CAPABLE(ha)) { 512 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027, 513 "Done exchanges=%x.\n", mcp->mb[1]); 514 } else { 515 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028, 516 "Done %s.\n", __func__); 517 } 518 } 519 520 return rval; 521 } 522 523 /* 524 * qla2x00_get_fw_version 525 * Get firmware version. 526 * 527 * Input: 528 * ha: adapter state pointer. 529 * major: pointer for major number. 530 * minor: pointer for minor number. 531 * subminor: pointer for subminor number. 532 * 533 * Returns: 534 * qla2x00 local function return status code. 535 * 536 * Context: 537 * Kernel context. 538 */ 539 int 540 qla2x00_get_fw_version(scsi_qla_host_t *vha) 541 { 542 int rval; 543 mbx_cmd_t mc; 544 mbx_cmd_t *mcp = &mc; 545 struct qla_hw_data *ha = vha->hw; 546 547 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029, 548 "Entered %s.\n", __func__); 549 550 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION; 551 mcp->out_mb = MBX_0; 552 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 553 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha)) 554 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8; 555 if (IS_FWI2_CAPABLE(ha)) 556 mcp->in_mb |= MBX_17|MBX_16|MBX_15; 557 if (IS_QLA27XX(ha)) 558 mcp->in_mb |= MBX_23 | MBX_22 | MBX_21 | MBX_20 | MBX_19 | 559 MBX_18 | MBX_14 | MBX_13 | MBX_11 | MBX_10 | MBX_9 | MBX_8; 560 561 mcp->flags = 0; 562 mcp->tov = MBX_TOV_SECONDS; 563 rval = qla2x00_mailbox_command(vha, mcp); 564 if (rval != QLA_SUCCESS) 565 goto failed; 566 567 /* Return mailbox data. */ 568 ha->fw_major_version = mcp->mb[1]; 569 ha->fw_minor_version = mcp->mb[2]; 570 ha->fw_subminor_version = mcp->mb[3]; 571 ha->fw_attributes = mcp->mb[6]; 572 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw)) 573 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */ 574 else 575 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4]; 576 577 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) { 578 ha->mpi_version[0] = mcp->mb[10] & 0xff; 579 ha->mpi_version[1] = mcp->mb[11] >> 8; 580 ha->mpi_version[2] = mcp->mb[11] & 0xff; 581 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13]; 582 ha->phy_version[0] = mcp->mb[8] & 0xff; 583 ha->phy_version[1] = mcp->mb[9] >> 8; 584 ha->phy_version[2] = mcp->mb[9] & 0xff; 585 } 586 587 if (IS_FWI2_CAPABLE(ha)) { 588 ha->fw_attributes_h = mcp->mb[15]; 589 ha->fw_attributes_ext[0] = mcp->mb[16]; 590 ha->fw_attributes_ext[1] = mcp->mb[17]; 591 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139, 592 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n", 593 __func__, mcp->mb[15], mcp->mb[6]); 594 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f, 595 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n", 596 __func__, mcp->mb[17], mcp->mb[16]); 597 } 598 599 if (IS_QLA27XX(ha)) { 600 ha->mpi_version[0] = mcp->mb[10] & 0xff; 601 ha->mpi_version[1] = mcp->mb[11] >> 8; 602 ha->mpi_version[2] = mcp->mb[11] & 0xff; 603 ha->pep_version[0] = mcp->mb[13] & 0xff; 604 ha->pep_version[1] = mcp->mb[14] >> 8; 605 ha->pep_version[2] = mcp->mb[14] & 0xff; 606 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18]; 607 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20]; 608 } 609 610 failed: 611 if (rval != QLA_SUCCESS) { 612 /*EMPTY*/ 613 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval); 614 } else { 615 /*EMPTY*/ 616 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b, 617 "Done %s.\n", __func__); 618 } 619 return rval; 620 } 621 622 /* 623 * qla2x00_get_fw_options 624 * Set firmware options. 625 * 626 * Input: 627 * ha = adapter block pointer. 628 * fwopt = pointer for firmware options. 629 * 630 * Returns: 631 * qla2x00 local function return status code. 632 * 633 * Context: 634 * Kernel context. 635 */ 636 int 637 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 638 { 639 int rval; 640 mbx_cmd_t mc; 641 mbx_cmd_t *mcp = &mc; 642 643 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c, 644 "Entered %s.\n", __func__); 645 646 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION; 647 mcp->out_mb = MBX_0; 648 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 649 mcp->tov = MBX_TOV_SECONDS; 650 mcp->flags = 0; 651 rval = qla2x00_mailbox_command(vha, mcp); 652 653 if (rval != QLA_SUCCESS) { 654 /*EMPTY*/ 655 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval); 656 } else { 657 fwopts[0] = mcp->mb[0]; 658 fwopts[1] = mcp->mb[1]; 659 fwopts[2] = mcp->mb[2]; 660 fwopts[3] = mcp->mb[3]; 661 662 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e, 663 "Done %s.\n", __func__); 664 } 665 666 return rval; 667 } 668 669 670 /* 671 * qla2x00_set_fw_options 672 * Set firmware options. 673 * 674 * Input: 675 * ha = adapter block pointer. 676 * fwopt = pointer for firmware options. 677 * 678 * Returns: 679 * qla2x00 local function return status code. 680 * 681 * Context: 682 * Kernel context. 683 */ 684 int 685 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 686 { 687 int rval; 688 mbx_cmd_t mc; 689 mbx_cmd_t *mcp = &mc; 690 691 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f, 692 "Entered %s.\n", __func__); 693 694 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION; 695 mcp->mb[1] = fwopts[1]; 696 mcp->mb[2] = fwopts[2]; 697 mcp->mb[3] = fwopts[3]; 698 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 699 mcp->in_mb = MBX_0; 700 if (IS_FWI2_CAPABLE(vha->hw)) { 701 mcp->in_mb |= MBX_1; 702 } else { 703 mcp->mb[10] = fwopts[10]; 704 mcp->mb[11] = fwopts[11]; 705 mcp->mb[12] = 0; /* Undocumented, but used */ 706 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 707 } 708 mcp->tov = MBX_TOV_SECONDS; 709 mcp->flags = 0; 710 rval = qla2x00_mailbox_command(vha, mcp); 711 712 fwopts[0] = mcp->mb[0]; 713 714 if (rval != QLA_SUCCESS) { 715 /*EMPTY*/ 716 ql_dbg(ql_dbg_mbx, vha, 0x1030, 717 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]); 718 } else { 719 /*EMPTY*/ 720 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031, 721 "Done %s.\n", __func__); 722 } 723 724 return rval; 725 } 726 727 /* 728 * qla2x00_mbx_reg_test 729 * Mailbox register wrap test. 730 * 731 * Input: 732 * ha = adapter block pointer. 733 * TARGET_QUEUE_LOCK must be released. 734 * ADAPTER_STATE_LOCK must be released. 735 * 736 * Returns: 737 * qla2x00 local function return status code. 738 * 739 * Context: 740 * Kernel context. 741 */ 742 int 743 qla2x00_mbx_reg_test(scsi_qla_host_t *vha) 744 { 745 int rval; 746 mbx_cmd_t mc; 747 mbx_cmd_t *mcp = &mc; 748 749 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032, 750 "Entered %s.\n", __func__); 751 752 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; 753 mcp->mb[1] = 0xAAAA; 754 mcp->mb[2] = 0x5555; 755 mcp->mb[3] = 0xAA55; 756 mcp->mb[4] = 0x55AA; 757 mcp->mb[5] = 0xA5A5; 758 mcp->mb[6] = 0x5A5A; 759 mcp->mb[7] = 0x2525; 760 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 761 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 762 mcp->tov = MBX_TOV_SECONDS; 763 mcp->flags = 0; 764 rval = qla2x00_mailbox_command(vha, mcp); 765 766 if (rval == QLA_SUCCESS) { 767 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 || 768 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA) 769 rval = QLA_FUNCTION_FAILED; 770 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A || 771 mcp->mb[7] != 0x2525) 772 rval = QLA_FUNCTION_FAILED; 773 } 774 775 if (rval != QLA_SUCCESS) { 776 /*EMPTY*/ 777 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval); 778 } else { 779 /*EMPTY*/ 780 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034, 781 "Done %s.\n", __func__); 782 } 783 784 return rval; 785 } 786 787 /* 788 * qla2x00_verify_checksum 789 * Verify firmware checksum. 790 * 791 * Input: 792 * ha = adapter block pointer. 793 * TARGET_QUEUE_LOCK must be released. 794 * ADAPTER_STATE_LOCK must be released. 795 * 796 * Returns: 797 * qla2x00 local function return status code. 798 * 799 * Context: 800 * Kernel context. 801 */ 802 int 803 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr) 804 { 805 int rval; 806 mbx_cmd_t mc; 807 mbx_cmd_t *mcp = &mc; 808 809 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035, 810 "Entered %s.\n", __func__); 811 812 mcp->mb[0] = MBC_VERIFY_CHECKSUM; 813 mcp->out_mb = MBX_0; 814 mcp->in_mb = MBX_0; 815 if (IS_FWI2_CAPABLE(vha->hw)) { 816 mcp->mb[1] = MSW(risc_addr); 817 mcp->mb[2] = LSW(risc_addr); 818 mcp->out_mb |= MBX_2|MBX_1; 819 mcp->in_mb |= MBX_2|MBX_1; 820 } else { 821 mcp->mb[1] = LSW(risc_addr); 822 mcp->out_mb |= MBX_1; 823 mcp->in_mb |= MBX_1; 824 } 825 826 mcp->tov = MBX_TOV_SECONDS; 827 mcp->flags = 0; 828 rval = qla2x00_mailbox_command(vha, mcp); 829 830 if (rval != QLA_SUCCESS) { 831 ql_dbg(ql_dbg_mbx, vha, 0x1036, 832 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ? 833 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]); 834 } else { 835 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037, 836 "Done %s.\n", __func__); 837 } 838 839 return rval; 840 } 841 842 /* 843 * qla2x00_issue_iocb 844 * Issue IOCB using mailbox command 845 * 846 * Input: 847 * ha = adapter state pointer. 848 * buffer = buffer pointer. 849 * phys_addr = physical address of buffer. 850 * size = size of buffer. 851 * TARGET_QUEUE_LOCK must be released. 852 * ADAPTER_STATE_LOCK must be released. 853 * 854 * Returns: 855 * qla2x00 local function return status code. 856 * 857 * Context: 858 * Kernel context. 859 */ 860 int 861 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer, 862 dma_addr_t phys_addr, size_t size, uint32_t tov) 863 { 864 int rval; 865 mbx_cmd_t mc; 866 mbx_cmd_t *mcp = &mc; 867 868 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038, 869 "Entered %s.\n", __func__); 870 871 mcp->mb[0] = MBC_IOCB_COMMAND_A64; 872 mcp->mb[1] = 0; 873 mcp->mb[2] = MSW(phys_addr); 874 mcp->mb[3] = LSW(phys_addr); 875 mcp->mb[6] = MSW(MSD(phys_addr)); 876 mcp->mb[7] = LSW(MSD(phys_addr)); 877 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 878 mcp->in_mb = MBX_2|MBX_0; 879 mcp->tov = tov; 880 mcp->flags = 0; 881 rval = qla2x00_mailbox_command(vha, mcp); 882 883 if (rval != QLA_SUCCESS) { 884 /*EMPTY*/ 885 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval); 886 } else { 887 sts_entry_t *sts_entry = (sts_entry_t *) buffer; 888 889 /* Mask reserved bits. */ 890 sts_entry->entry_status &= 891 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK; 892 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a, 893 "Done %s.\n", __func__); 894 } 895 896 return rval; 897 } 898 899 int 900 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr, 901 size_t size) 902 { 903 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size, 904 MBX_TOV_SECONDS); 905 } 906 907 /* 908 * qla2x00_abort_command 909 * Abort command aborts a specified IOCB. 910 * 911 * Input: 912 * ha = adapter block pointer. 913 * sp = SB structure pointer. 914 * 915 * Returns: 916 * qla2x00 local function return status code. 917 * 918 * Context: 919 * Kernel context. 920 */ 921 int 922 qla2x00_abort_command(srb_t *sp) 923 { 924 unsigned long flags = 0; 925 int rval; 926 uint32_t handle = 0; 927 mbx_cmd_t mc; 928 mbx_cmd_t *mcp = &mc; 929 fc_port_t *fcport = sp->fcport; 930 scsi_qla_host_t *vha = fcport->vha; 931 struct qla_hw_data *ha = vha->hw; 932 struct req_que *req = vha->req; 933 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 934 935 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b, 936 "Entered %s.\n", __func__); 937 938 spin_lock_irqsave(&ha->hardware_lock, flags); 939 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 940 if (req->outstanding_cmds[handle] == sp) 941 break; 942 } 943 spin_unlock_irqrestore(&ha->hardware_lock, flags); 944 945 if (handle == req->num_outstanding_cmds) { 946 /* command not found */ 947 return QLA_FUNCTION_FAILED; 948 } 949 950 mcp->mb[0] = MBC_ABORT_COMMAND; 951 if (HAS_EXTENDED_IDS(ha)) 952 mcp->mb[1] = fcport->loop_id; 953 else 954 mcp->mb[1] = fcport->loop_id << 8; 955 mcp->mb[2] = (uint16_t)handle; 956 mcp->mb[3] = (uint16_t)(handle >> 16); 957 mcp->mb[6] = (uint16_t)cmd->device->lun; 958 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 959 mcp->in_mb = MBX_0; 960 mcp->tov = MBX_TOV_SECONDS; 961 mcp->flags = 0; 962 rval = qla2x00_mailbox_command(vha, mcp); 963 964 if (rval != QLA_SUCCESS) { 965 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval); 966 } else { 967 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d, 968 "Done %s.\n", __func__); 969 } 970 971 return rval; 972 } 973 974 int 975 qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag) 976 { 977 int rval, rval2; 978 mbx_cmd_t mc; 979 mbx_cmd_t *mcp = &mc; 980 scsi_qla_host_t *vha; 981 struct req_que *req; 982 struct rsp_que *rsp; 983 984 l = l; 985 vha = fcport->vha; 986 987 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e, 988 "Entered %s.\n", __func__); 989 990 req = vha->hw->req_q_map[0]; 991 rsp = req->rsp; 992 mcp->mb[0] = MBC_ABORT_TARGET; 993 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0; 994 if (HAS_EXTENDED_IDS(vha->hw)) { 995 mcp->mb[1] = fcport->loop_id; 996 mcp->mb[10] = 0; 997 mcp->out_mb |= MBX_10; 998 } else { 999 mcp->mb[1] = fcport->loop_id << 8; 1000 } 1001 mcp->mb[2] = vha->hw->loop_reset_delay; 1002 mcp->mb[9] = vha->vp_idx; 1003 1004 mcp->in_mb = MBX_0; 1005 mcp->tov = MBX_TOV_SECONDS; 1006 mcp->flags = 0; 1007 rval = qla2x00_mailbox_command(vha, mcp); 1008 if (rval != QLA_SUCCESS) { 1009 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f, 1010 "Failed=%x.\n", rval); 1011 } 1012 1013 /* Issue marker IOCB. */ 1014 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0, 1015 MK_SYNC_ID); 1016 if (rval2 != QLA_SUCCESS) { 1017 ql_dbg(ql_dbg_mbx, vha, 0x1040, 1018 "Failed to issue marker IOCB (%x).\n", rval2); 1019 } else { 1020 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041, 1021 "Done %s.\n", __func__); 1022 } 1023 1024 return rval; 1025 } 1026 1027 int 1028 qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 1029 { 1030 int rval, rval2; 1031 mbx_cmd_t mc; 1032 mbx_cmd_t *mcp = &mc; 1033 scsi_qla_host_t *vha; 1034 struct req_que *req; 1035 struct rsp_que *rsp; 1036 1037 vha = fcport->vha; 1038 1039 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042, 1040 "Entered %s.\n", __func__); 1041 1042 req = vha->hw->req_q_map[0]; 1043 rsp = req->rsp; 1044 mcp->mb[0] = MBC_LUN_RESET; 1045 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 1046 if (HAS_EXTENDED_IDS(vha->hw)) 1047 mcp->mb[1] = fcport->loop_id; 1048 else 1049 mcp->mb[1] = fcport->loop_id << 8; 1050 mcp->mb[2] = (u32)l; 1051 mcp->mb[3] = 0; 1052 mcp->mb[9] = vha->vp_idx; 1053 1054 mcp->in_mb = MBX_0; 1055 mcp->tov = MBX_TOV_SECONDS; 1056 mcp->flags = 0; 1057 rval = qla2x00_mailbox_command(vha, mcp); 1058 if (rval != QLA_SUCCESS) { 1059 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval); 1060 } 1061 1062 /* Issue marker IOCB. */ 1063 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 1064 MK_SYNC_ID_LUN); 1065 if (rval2 != QLA_SUCCESS) { 1066 ql_dbg(ql_dbg_mbx, vha, 0x1044, 1067 "Failed to issue marker IOCB (%x).\n", rval2); 1068 } else { 1069 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045, 1070 "Done %s.\n", __func__); 1071 } 1072 1073 return rval; 1074 } 1075 1076 /* 1077 * qla2x00_get_adapter_id 1078 * Get adapter ID and topology. 1079 * 1080 * Input: 1081 * ha = adapter block pointer. 1082 * id = pointer for loop ID. 1083 * al_pa = pointer for AL_PA. 1084 * area = pointer for area. 1085 * domain = pointer for domain. 1086 * top = pointer for topology. 1087 * TARGET_QUEUE_LOCK must be released. 1088 * ADAPTER_STATE_LOCK must be released. 1089 * 1090 * Returns: 1091 * qla2x00 local function return status code. 1092 * 1093 * Context: 1094 * Kernel context. 1095 */ 1096 int 1097 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa, 1098 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap) 1099 { 1100 int rval; 1101 mbx_cmd_t mc; 1102 mbx_cmd_t *mcp = &mc; 1103 1104 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046, 1105 "Entered %s.\n", __func__); 1106 1107 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID; 1108 mcp->mb[9] = vha->vp_idx; 1109 mcp->out_mb = MBX_9|MBX_0; 1110 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1111 if (IS_CNA_CAPABLE(vha->hw)) 1112 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; 1113 if (IS_FWI2_CAPABLE(vha->hw)) 1114 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16; 1115 mcp->tov = MBX_TOV_SECONDS; 1116 mcp->flags = 0; 1117 rval = qla2x00_mailbox_command(vha, mcp); 1118 if (mcp->mb[0] == MBS_COMMAND_ERROR) 1119 rval = QLA_COMMAND_ERROR; 1120 else if (mcp->mb[0] == MBS_INVALID_COMMAND) 1121 rval = QLA_INVALID_COMMAND; 1122 1123 /* Return data. */ 1124 *id = mcp->mb[1]; 1125 *al_pa = LSB(mcp->mb[2]); 1126 *area = MSB(mcp->mb[2]); 1127 *domain = LSB(mcp->mb[3]); 1128 *top = mcp->mb[6]; 1129 *sw_cap = mcp->mb[7]; 1130 1131 if (rval != QLA_SUCCESS) { 1132 /*EMPTY*/ 1133 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval); 1134 } else { 1135 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048, 1136 "Done %s.\n", __func__); 1137 1138 if (IS_CNA_CAPABLE(vha->hw)) { 1139 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; 1140 vha->fcoe_fcf_idx = mcp->mb[10]; 1141 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; 1142 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff; 1143 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8; 1144 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff; 1145 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8; 1146 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff; 1147 } 1148 /* If FA-WWN supported */ 1149 if (IS_FAWWN_CAPABLE(vha->hw)) { 1150 if (mcp->mb[7] & BIT_14) { 1151 vha->port_name[0] = MSB(mcp->mb[16]); 1152 vha->port_name[1] = LSB(mcp->mb[16]); 1153 vha->port_name[2] = MSB(mcp->mb[17]); 1154 vha->port_name[3] = LSB(mcp->mb[17]); 1155 vha->port_name[4] = MSB(mcp->mb[18]); 1156 vha->port_name[5] = LSB(mcp->mb[18]); 1157 vha->port_name[6] = MSB(mcp->mb[19]); 1158 vha->port_name[7] = LSB(mcp->mb[19]); 1159 fc_host_port_name(vha->host) = 1160 wwn_to_u64(vha->port_name); 1161 ql_dbg(ql_dbg_mbx, vha, 0x10ca, 1162 "FA-WWN acquired %016llx\n", 1163 wwn_to_u64(vha->port_name)); 1164 } 1165 } 1166 } 1167 1168 return rval; 1169 } 1170 1171 /* 1172 * qla2x00_get_retry_cnt 1173 * Get current firmware login retry count and delay. 1174 * 1175 * Input: 1176 * ha = adapter block pointer. 1177 * retry_cnt = pointer to login retry count. 1178 * tov = pointer to login timeout value. 1179 * 1180 * Returns: 1181 * qla2x00 local function return status code. 1182 * 1183 * Context: 1184 * Kernel context. 1185 */ 1186 int 1187 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov, 1188 uint16_t *r_a_tov) 1189 { 1190 int rval; 1191 uint16_t ratov; 1192 mbx_cmd_t mc; 1193 mbx_cmd_t *mcp = &mc; 1194 1195 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049, 1196 "Entered %s.\n", __func__); 1197 1198 mcp->mb[0] = MBC_GET_RETRY_COUNT; 1199 mcp->out_mb = MBX_0; 1200 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1201 mcp->tov = MBX_TOV_SECONDS; 1202 mcp->flags = 0; 1203 rval = qla2x00_mailbox_command(vha, mcp); 1204 1205 if (rval != QLA_SUCCESS) { 1206 /*EMPTY*/ 1207 ql_dbg(ql_dbg_mbx, vha, 0x104a, 1208 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 1209 } else { 1210 /* Convert returned data and check our values. */ 1211 *r_a_tov = mcp->mb[3] / 2; 1212 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */ 1213 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) { 1214 /* Update to the larger values */ 1215 *retry_cnt = (uint8_t)mcp->mb[1]; 1216 *tov = ratov; 1217 } 1218 1219 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b, 1220 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov); 1221 } 1222 1223 return rval; 1224 } 1225 1226 /* 1227 * qla2x00_init_firmware 1228 * Initialize adapter firmware. 1229 * 1230 * Input: 1231 * ha = adapter block pointer. 1232 * dptr = Initialization control block pointer. 1233 * size = size of initialization control block. 1234 * TARGET_QUEUE_LOCK must be released. 1235 * ADAPTER_STATE_LOCK must be released. 1236 * 1237 * Returns: 1238 * qla2x00 local function return status code. 1239 * 1240 * Context: 1241 * Kernel context. 1242 */ 1243 int 1244 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size) 1245 { 1246 int rval; 1247 mbx_cmd_t mc; 1248 mbx_cmd_t *mcp = &mc; 1249 struct qla_hw_data *ha = vha->hw; 1250 1251 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c, 1252 "Entered %s.\n", __func__); 1253 1254 if (IS_P3P_TYPE(ha) && ql2xdbwr) 1255 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr, 1256 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16))); 1257 1258 if (ha->flags.npiv_supported) 1259 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE; 1260 else 1261 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; 1262 1263 mcp->mb[1] = 0; 1264 mcp->mb[2] = MSW(ha->init_cb_dma); 1265 mcp->mb[3] = LSW(ha->init_cb_dma); 1266 mcp->mb[6] = MSW(MSD(ha->init_cb_dma)); 1267 mcp->mb[7] = LSW(MSD(ha->init_cb_dma)); 1268 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1269 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) { 1270 mcp->mb[1] = BIT_0; 1271 mcp->mb[10] = MSW(ha->ex_init_cb_dma); 1272 mcp->mb[11] = LSW(ha->ex_init_cb_dma); 1273 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma)); 1274 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma)); 1275 mcp->mb[14] = sizeof(*ha->ex_init_cb); 1276 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10; 1277 } 1278 /* 1 and 2 should normally be captured. */ 1279 mcp->in_mb = MBX_2|MBX_1|MBX_0; 1280 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 1281 /* mb3 is additional info about the installed SFP. */ 1282 mcp->in_mb |= MBX_3; 1283 mcp->buf_size = size; 1284 mcp->flags = MBX_DMA_OUT; 1285 mcp->tov = MBX_TOV_SECONDS; 1286 rval = qla2x00_mailbox_command(vha, mcp); 1287 1288 if (rval != QLA_SUCCESS) { 1289 /*EMPTY*/ 1290 ql_dbg(ql_dbg_mbx, vha, 0x104d, 1291 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n", 1292 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]); 1293 } else { 1294 /*EMPTY*/ 1295 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e, 1296 "Done %s.\n", __func__); 1297 } 1298 1299 return rval; 1300 } 1301 1302 /* 1303 * qla2x00_get_node_name_list 1304 * Issue get node name list mailbox command, kmalloc() 1305 * and return the resulting list. Caller must kfree() it! 1306 * 1307 * Input: 1308 * ha = adapter state pointer. 1309 * out_data = resulting list 1310 * out_len = length of the resulting list 1311 * 1312 * Returns: 1313 * qla2x00 local function return status code. 1314 * 1315 * Context: 1316 * Kernel context. 1317 */ 1318 int 1319 qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len) 1320 { 1321 struct qla_hw_data *ha = vha->hw; 1322 struct qla_port_24xx_data *list = NULL; 1323 void *pmap; 1324 mbx_cmd_t mc; 1325 dma_addr_t pmap_dma; 1326 ulong dma_size; 1327 int rval, left; 1328 1329 left = 1; 1330 while (left > 0) { 1331 dma_size = left * sizeof(*list); 1332 pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size, 1333 &pmap_dma, GFP_KERNEL); 1334 if (!pmap) { 1335 ql_log(ql_log_warn, vha, 0x113f, 1336 "%s(%ld): DMA Alloc failed of %ld\n", 1337 __func__, vha->host_no, dma_size); 1338 rval = QLA_MEMORY_ALLOC_FAILED; 1339 goto out; 1340 } 1341 1342 mc.mb[0] = MBC_PORT_NODE_NAME_LIST; 1343 mc.mb[1] = BIT_1 | BIT_3; 1344 mc.mb[2] = MSW(pmap_dma); 1345 mc.mb[3] = LSW(pmap_dma); 1346 mc.mb[6] = MSW(MSD(pmap_dma)); 1347 mc.mb[7] = LSW(MSD(pmap_dma)); 1348 mc.mb[8] = dma_size; 1349 mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8; 1350 mc.in_mb = MBX_0|MBX_1; 1351 mc.tov = 30; 1352 mc.flags = MBX_DMA_IN; 1353 1354 rval = qla2x00_mailbox_command(vha, &mc); 1355 if (rval != QLA_SUCCESS) { 1356 if ((mc.mb[0] == MBS_COMMAND_ERROR) && 1357 (mc.mb[1] == 0xA)) { 1358 left += le16_to_cpu(mc.mb[2]) / 1359 sizeof(struct qla_port_24xx_data); 1360 goto restart; 1361 } 1362 goto out_free; 1363 } 1364 1365 left = 0; 1366 1367 list = kmemdup(pmap, dma_size, GFP_KERNEL); 1368 if (!list) { 1369 ql_log(ql_log_warn, vha, 0x1140, 1370 "%s(%ld): failed to allocate node names list " 1371 "structure.\n", __func__, vha->host_no); 1372 rval = QLA_MEMORY_ALLOC_FAILED; 1373 goto out_free; 1374 } 1375 1376 restart: 1377 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma); 1378 } 1379 1380 *out_data = list; 1381 *out_len = dma_size; 1382 1383 out: 1384 return rval; 1385 1386 out_free: 1387 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma); 1388 return rval; 1389 } 1390 1391 /* 1392 * qla2x00_get_port_database 1393 * Issue normal/enhanced get port database mailbox command 1394 * and copy device name as necessary. 1395 * 1396 * Input: 1397 * ha = adapter state pointer. 1398 * dev = structure pointer. 1399 * opt = enhanced cmd option byte. 1400 * 1401 * Returns: 1402 * qla2x00 local function return status code. 1403 * 1404 * Context: 1405 * Kernel context. 1406 */ 1407 int 1408 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt) 1409 { 1410 int rval; 1411 mbx_cmd_t mc; 1412 mbx_cmd_t *mcp = &mc; 1413 port_database_t *pd; 1414 struct port_database_24xx *pd24; 1415 dma_addr_t pd_dma; 1416 struct qla_hw_data *ha = vha->hw; 1417 1418 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f, 1419 "Entered %s.\n", __func__); 1420 1421 pd24 = NULL; 1422 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1423 if (pd == NULL) { 1424 ql_log(ql_log_warn, vha, 0x1050, 1425 "Failed to allocate port database structure.\n"); 1426 return QLA_MEMORY_ALLOC_FAILED; 1427 } 1428 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE)); 1429 1430 mcp->mb[0] = MBC_GET_PORT_DATABASE; 1431 if (opt != 0 && !IS_FWI2_CAPABLE(ha)) 1432 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE; 1433 mcp->mb[2] = MSW(pd_dma); 1434 mcp->mb[3] = LSW(pd_dma); 1435 mcp->mb[6] = MSW(MSD(pd_dma)); 1436 mcp->mb[7] = LSW(MSD(pd_dma)); 1437 mcp->mb[9] = vha->vp_idx; 1438 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 1439 mcp->in_mb = MBX_0; 1440 if (IS_FWI2_CAPABLE(ha)) { 1441 mcp->mb[1] = fcport->loop_id; 1442 mcp->mb[10] = opt; 1443 mcp->out_mb |= MBX_10|MBX_1; 1444 mcp->in_mb |= MBX_1; 1445 } else if (HAS_EXTENDED_IDS(ha)) { 1446 mcp->mb[1] = fcport->loop_id; 1447 mcp->mb[10] = opt; 1448 mcp->out_mb |= MBX_10|MBX_1; 1449 } else { 1450 mcp->mb[1] = fcport->loop_id << 8 | opt; 1451 mcp->out_mb |= MBX_1; 1452 } 1453 mcp->buf_size = IS_FWI2_CAPABLE(ha) ? 1454 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE; 1455 mcp->flags = MBX_DMA_IN; 1456 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1457 rval = qla2x00_mailbox_command(vha, mcp); 1458 if (rval != QLA_SUCCESS) 1459 goto gpd_error_out; 1460 1461 if (IS_FWI2_CAPABLE(ha)) { 1462 uint64_t zero = 0; 1463 pd24 = (struct port_database_24xx *) pd; 1464 1465 /* Check for logged in state. */ 1466 if (pd24->current_login_state != PDS_PRLI_COMPLETE && 1467 pd24->last_login_state != PDS_PRLI_COMPLETE) { 1468 ql_dbg(ql_dbg_mbx, vha, 0x1051, 1469 "Unable to verify login-state (%x/%x) for " 1470 "loop_id %x.\n", pd24->current_login_state, 1471 pd24->last_login_state, fcport->loop_id); 1472 rval = QLA_FUNCTION_FAILED; 1473 goto gpd_error_out; 1474 } 1475 1476 if (fcport->loop_id == FC_NO_LOOP_ID || 1477 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1478 memcmp(fcport->port_name, pd24->port_name, 8))) { 1479 /* We lost the device mid way. */ 1480 rval = QLA_NOT_LOGGED_IN; 1481 goto gpd_error_out; 1482 } 1483 1484 /* Names are little-endian. */ 1485 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE); 1486 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE); 1487 1488 /* Get port_id of device. */ 1489 fcport->d_id.b.domain = pd24->port_id[0]; 1490 fcport->d_id.b.area = pd24->port_id[1]; 1491 fcport->d_id.b.al_pa = pd24->port_id[2]; 1492 fcport->d_id.b.rsvd_1 = 0; 1493 1494 /* If not target must be initiator or unknown type. */ 1495 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0) 1496 fcport->port_type = FCT_INITIATOR; 1497 else 1498 fcport->port_type = FCT_TARGET; 1499 1500 /* Passback COS information. */ 1501 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ? 1502 FC_COS_CLASS2 : FC_COS_CLASS3; 1503 1504 if (pd24->prli_svc_param_word_3[0] & BIT_7) 1505 fcport->flags |= FCF_CONF_COMP_SUPPORTED; 1506 } else { 1507 uint64_t zero = 0; 1508 1509 /* Check for logged in state. */ 1510 if (pd->master_state != PD_STATE_PORT_LOGGED_IN && 1511 pd->slave_state != PD_STATE_PORT_LOGGED_IN) { 1512 ql_dbg(ql_dbg_mbx, vha, 0x100a, 1513 "Unable to verify login-state (%x/%x) - " 1514 "portid=%02x%02x%02x.\n", pd->master_state, 1515 pd->slave_state, fcport->d_id.b.domain, 1516 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1517 rval = QLA_FUNCTION_FAILED; 1518 goto gpd_error_out; 1519 } 1520 1521 if (fcport->loop_id == FC_NO_LOOP_ID || 1522 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1523 memcmp(fcport->port_name, pd->port_name, 8))) { 1524 /* We lost the device mid way. */ 1525 rval = QLA_NOT_LOGGED_IN; 1526 goto gpd_error_out; 1527 } 1528 1529 /* Names are little-endian. */ 1530 memcpy(fcport->node_name, pd->node_name, WWN_SIZE); 1531 memcpy(fcport->port_name, pd->port_name, WWN_SIZE); 1532 1533 /* Get port_id of device. */ 1534 fcport->d_id.b.domain = pd->port_id[0]; 1535 fcport->d_id.b.area = pd->port_id[3]; 1536 fcport->d_id.b.al_pa = pd->port_id[2]; 1537 fcport->d_id.b.rsvd_1 = 0; 1538 1539 /* If not target must be initiator or unknown type. */ 1540 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 1541 fcport->port_type = FCT_INITIATOR; 1542 else 1543 fcport->port_type = FCT_TARGET; 1544 1545 /* Passback COS information. */ 1546 fcport->supported_classes = (pd->options & BIT_4) ? 1547 FC_COS_CLASS2: FC_COS_CLASS3; 1548 } 1549 1550 gpd_error_out: 1551 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1552 1553 if (rval != QLA_SUCCESS) { 1554 ql_dbg(ql_dbg_mbx, vha, 0x1052, 1555 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval, 1556 mcp->mb[0], mcp->mb[1]); 1557 } else { 1558 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053, 1559 "Done %s.\n", __func__); 1560 } 1561 1562 return rval; 1563 } 1564 1565 /* 1566 * qla2x00_get_firmware_state 1567 * Get adapter firmware state. 1568 * 1569 * Input: 1570 * ha = adapter block pointer. 1571 * dptr = pointer for firmware state. 1572 * TARGET_QUEUE_LOCK must be released. 1573 * ADAPTER_STATE_LOCK must be released. 1574 * 1575 * Returns: 1576 * qla2x00 local function return status code. 1577 * 1578 * Context: 1579 * Kernel context. 1580 */ 1581 int 1582 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states) 1583 { 1584 int rval; 1585 mbx_cmd_t mc; 1586 mbx_cmd_t *mcp = &mc; 1587 1588 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054, 1589 "Entered %s.\n", __func__); 1590 1591 mcp->mb[0] = MBC_GET_FIRMWARE_STATE; 1592 mcp->out_mb = MBX_0; 1593 if (IS_FWI2_CAPABLE(vha->hw)) 1594 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1595 else 1596 mcp->in_mb = MBX_1|MBX_0; 1597 mcp->tov = MBX_TOV_SECONDS; 1598 mcp->flags = 0; 1599 rval = qla2x00_mailbox_command(vha, mcp); 1600 1601 /* Return firmware states. */ 1602 states[0] = mcp->mb[1]; 1603 if (IS_FWI2_CAPABLE(vha->hw)) { 1604 states[1] = mcp->mb[2]; 1605 states[2] = mcp->mb[3]; 1606 states[3] = mcp->mb[4]; 1607 states[4] = mcp->mb[5]; 1608 states[5] = mcp->mb[6]; /* DPORT status */ 1609 } 1610 1611 if (rval != QLA_SUCCESS) { 1612 /*EMPTY*/ 1613 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval); 1614 } else { 1615 /*EMPTY*/ 1616 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056, 1617 "Done %s.\n", __func__); 1618 } 1619 1620 return rval; 1621 } 1622 1623 /* 1624 * qla2x00_get_port_name 1625 * Issue get port name mailbox command. 1626 * Returned name is in big endian format. 1627 * 1628 * Input: 1629 * ha = adapter block pointer. 1630 * loop_id = loop ID of device. 1631 * name = pointer for name. 1632 * TARGET_QUEUE_LOCK must be released. 1633 * ADAPTER_STATE_LOCK must be released. 1634 * 1635 * Returns: 1636 * qla2x00 local function return status code. 1637 * 1638 * Context: 1639 * Kernel context. 1640 */ 1641 int 1642 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name, 1643 uint8_t opt) 1644 { 1645 int rval; 1646 mbx_cmd_t mc; 1647 mbx_cmd_t *mcp = &mc; 1648 1649 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057, 1650 "Entered %s.\n", __func__); 1651 1652 mcp->mb[0] = MBC_GET_PORT_NAME; 1653 mcp->mb[9] = vha->vp_idx; 1654 mcp->out_mb = MBX_9|MBX_1|MBX_0; 1655 if (HAS_EXTENDED_IDS(vha->hw)) { 1656 mcp->mb[1] = loop_id; 1657 mcp->mb[10] = opt; 1658 mcp->out_mb |= MBX_10; 1659 } else { 1660 mcp->mb[1] = loop_id << 8 | opt; 1661 } 1662 1663 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1664 mcp->tov = MBX_TOV_SECONDS; 1665 mcp->flags = 0; 1666 rval = qla2x00_mailbox_command(vha, mcp); 1667 1668 if (rval != QLA_SUCCESS) { 1669 /*EMPTY*/ 1670 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval); 1671 } else { 1672 if (name != NULL) { 1673 /* This function returns name in big endian. */ 1674 name[0] = MSB(mcp->mb[2]); 1675 name[1] = LSB(mcp->mb[2]); 1676 name[2] = MSB(mcp->mb[3]); 1677 name[3] = LSB(mcp->mb[3]); 1678 name[4] = MSB(mcp->mb[6]); 1679 name[5] = LSB(mcp->mb[6]); 1680 name[6] = MSB(mcp->mb[7]); 1681 name[7] = LSB(mcp->mb[7]); 1682 } 1683 1684 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059, 1685 "Done %s.\n", __func__); 1686 } 1687 1688 return rval; 1689 } 1690 1691 /* 1692 * qla24xx_link_initialization 1693 * Issue link initialization mailbox command. 1694 * 1695 * Input: 1696 * ha = adapter block pointer. 1697 * TARGET_QUEUE_LOCK must be released. 1698 * ADAPTER_STATE_LOCK must be released. 1699 * 1700 * Returns: 1701 * qla2x00 local function return status code. 1702 * 1703 * Context: 1704 * Kernel context. 1705 */ 1706 int 1707 qla24xx_link_initialize(scsi_qla_host_t *vha) 1708 { 1709 int rval; 1710 mbx_cmd_t mc; 1711 mbx_cmd_t *mcp = &mc; 1712 1713 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152, 1714 "Entered %s.\n", __func__); 1715 1716 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw)) 1717 return QLA_FUNCTION_FAILED; 1718 1719 mcp->mb[0] = MBC_LINK_INITIALIZATION; 1720 mcp->mb[1] = BIT_4; 1721 if (vha->hw->operating_mode == LOOP) 1722 mcp->mb[1] |= BIT_6; 1723 else 1724 mcp->mb[1] |= BIT_5; 1725 mcp->mb[2] = 0; 1726 mcp->mb[3] = 0; 1727 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1728 mcp->in_mb = MBX_0; 1729 mcp->tov = MBX_TOV_SECONDS; 1730 mcp->flags = 0; 1731 rval = qla2x00_mailbox_command(vha, mcp); 1732 1733 if (rval != QLA_SUCCESS) { 1734 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval); 1735 } else { 1736 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154, 1737 "Done %s.\n", __func__); 1738 } 1739 1740 return rval; 1741 } 1742 1743 /* 1744 * qla2x00_lip_reset 1745 * Issue LIP reset mailbox command. 1746 * 1747 * Input: 1748 * ha = adapter block pointer. 1749 * TARGET_QUEUE_LOCK must be released. 1750 * ADAPTER_STATE_LOCK must be released. 1751 * 1752 * Returns: 1753 * qla2x00 local function return status code. 1754 * 1755 * Context: 1756 * Kernel context. 1757 */ 1758 int 1759 qla2x00_lip_reset(scsi_qla_host_t *vha) 1760 { 1761 int rval; 1762 mbx_cmd_t mc; 1763 mbx_cmd_t *mcp = &mc; 1764 1765 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a, 1766 "Entered %s.\n", __func__); 1767 1768 if (IS_CNA_CAPABLE(vha->hw)) { 1769 /* Logout across all FCFs. */ 1770 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1771 mcp->mb[1] = BIT_1; 1772 mcp->mb[2] = 0; 1773 mcp->out_mb = MBX_2|MBX_1|MBX_0; 1774 } else if (IS_FWI2_CAPABLE(vha->hw)) { 1775 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1776 mcp->mb[1] = BIT_6; 1777 mcp->mb[2] = 0; 1778 mcp->mb[3] = vha->hw->loop_reset_delay; 1779 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1780 } else { 1781 mcp->mb[0] = MBC_LIP_RESET; 1782 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1783 if (HAS_EXTENDED_IDS(vha->hw)) { 1784 mcp->mb[1] = 0x00ff; 1785 mcp->mb[10] = 0; 1786 mcp->out_mb |= MBX_10; 1787 } else { 1788 mcp->mb[1] = 0xff00; 1789 } 1790 mcp->mb[2] = vha->hw->loop_reset_delay; 1791 mcp->mb[3] = 0; 1792 } 1793 mcp->in_mb = MBX_0; 1794 mcp->tov = MBX_TOV_SECONDS; 1795 mcp->flags = 0; 1796 rval = qla2x00_mailbox_command(vha, mcp); 1797 1798 if (rval != QLA_SUCCESS) { 1799 /*EMPTY*/ 1800 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval); 1801 } else { 1802 /*EMPTY*/ 1803 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c, 1804 "Done %s.\n", __func__); 1805 } 1806 1807 return rval; 1808 } 1809 1810 /* 1811 * qla2x00_send_sns 1812 * Send SNS command. 1813 * 1814 * Input: 1815 * ha = adapter block pointer. 1816 * sns = pointer for command. 1817 * cmd_size = command size. 1818 * buf_size = response/command size. 1819 * TARGET_QUEUE_LOCK must be released. 1820 * ADAPTER_STATE_LOCK must be released. 1821 * 1822 * Returns: 1823 * qla2x00 local function return status code. 1824 * 1825 * Context: 1826 * Kernel context. 1827 */ 1828 int 1829 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address, 1830 uint16_t cmd_size, size_t buf_size) 1831 { 1832 int rval; 1833 mbx_cmd_t mc; 1834 mbx_cmd_t *mcp = &mc; 1835 1836 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d, 1837 "Entered %s.\n", __func__); 1838 1839 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e, 1840 "Retry cnt=%d ratov=%d total tov=%d.\n", 1841 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov); 1842 1843 mcp->mb[0] = MBC_SEND_SNS_COMMAND; 1844 mcp->mb[1] = cmd_size; 1845 mcp->mb[2] = MSW(sns_phys_address); 1846 mcp->mb[3] = LSW(sns_phys_address); 1847 mcp->mb[6] = MSW(MSD(sns_phys_address)); 1848 mcp->mb[7] = LSW(MSD(sns_phys_address)); 1849 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1850 mcp->in_mb = MBX_0|MBX_1; 1851 mcp->buf_size = buf_size; 1852 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN; 1853 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2); 1854 rval = qla2x00_mailbox_command(vha, mcp); 1855 1856 if (rval != QLA_SUCCESS) { 1857 /*EMPTY*/ 1858 ql_dbg(ql_dbg_mbx, vha, 0x105f, 1859 "Failed=%x mb[0]=%x mb[1]=%x.\n", 1860 rval, mcp->mb[0], mcp->mb[1]); 1861 } else { 1862 /*EMPTY*/ 1863 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060, 1864 "Done %s.\n", __func__); 1865 } 1866 1867 return rval; 1868 } 1869 1870 int 1871 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 1872 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 1873 { 1874 int rval; 1875 1876 struct logio_entry_24xx *lg; 1877 dma_addr_t lg_dma; 1878 uint32_t iop[2]; 1879 struct qla_hw_data *ha = vha->hw; 1880 struct req_que *req; 1881 1882 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061, 1883 "Entered %s.\n", __func__); 1884 1885 if (ha->flags.cpu_affinity_enabled) 1886 req = ha->req_q_map[0]; 1887 else 1888 req = vha->req; 1889 1890 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 1891 if (lg == NULL) { 1892 ql_log(ql_log_warn, vha, 0x1062, 1893 "Failed to allocate login IOCB.\n"); 1894 return QLA_MEMORY_ALLOC_FAILED; 1895 } 1896 memset(lg, 0, sizeof(struct logio_entry_24xx)); 1897 1898 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 1899 lg->entry_count = 1; 1900 lg->handle = MAKE_HANDLE(req->id, lg->handle); 1901 lg->nport_handle = cpu_to_le16(loop_id); 1902 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI); 1903 if (opt & BIT_0) 1904 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI); 1905 if (opt & BIT_1) 1906 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI); 1907 lg->port_id[0] = al_pa; 1908 lg->port_id[1] = area; 1909 lg->port_id[2] = domain; 1910 lg->vp_index = vha->vp_idx; 1911 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 1912 (ha->r_a_tov / 10 * 2) + 2); 1913 if (rval != QLA_SUCCESS) { 1914 ql_dbg(ql_dbg_mbx, vha, 0x1063, 1915 "Failed to issue login IOCB (%x).\n", rval); 1916 } else if (lg->entry_status != 0) { 1917 ql_dbg(ql_dbg_mbx, vha, 0x1064, 1918 "Failed to complete IOCB -- error status (%x).\n", 1919 lg->entry_status); 1920 rval = QLA_FUNCTION_FAILED; 1921 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 1922 iop[0] = le32_to_cpu(lg->io_parameter[0]); 1923 iop[1] = le32_to_cpu(lg->io_parameter[1]); 1924 1925 ql_dbg(ql_dbg_mbx, vha, 0x1065, 1926 "Failed to complete IOCB -- completion status (%x) " 1927 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 1928 iop[0], iop[1]); 1929 1930 switch (iop[0]) { 1931 case LSC_SCODE_PORTID_USED: 1932 mb[0] = MBS_PORT_ID_USED; 1933 mb[1] = LSW(iop[1]); 1934 break; 1935 case LSC_SCODE_NPORT_USED: 1936 mb[0] = MBS_LOOP_ID_USED; 1937 break; 1938 case LSC_SCODE_NOLINK: 1939 case LSC_SCODE_NOIOCB: 1940 case LSC_SCODE_NOXCB: 1941 case LSC_SCODE_CMD_FAILED: 1942 case LSC_SCODE_NOFABRIC: 1943 case LSC_SCODE_FW_NOT_READY: 1944 case LSC_SCODE_NOT_LOGGED_IN: 1945 case LSC_SCODE_NOPCB: 1946 case LSC_SCODE_ELS_REJECT: 1947 case LSC_SCODE_CMD_PARAM_ERR: 1948 case LSC_SCODE_NONPORT: 1949 case LSC_SCODE_LOGGED_IN: 1950 case LSC_SCODE_NOFLOGI_ACC: 1951 default: 1952 mb[0] = MBS_COMMAND_ERROR; 1953 break; 1954 } 1955 } else { 1956 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066, 1957 "Done %s.\n", __func__); 1958 1959 iop[0] = le32_to_cpu(lg->io_parameter[0]); 1960 1961 mb[0] = MBS_COMMAND_COMPLETE; 1962 mb[1] = 0; 1963 if (iop[0] & BIT_4) { 1964 if (iop[0] & BIT_8) 1965 mb[1] |= BIT_1; 1966 } else 1967 mb[1] = BIT_0; 1968 1969 /* Passback COS information. */ 1970 mb[10] = 0; 1971 if (lg->io_parameter[7] || lg->io_parameter[8]) 1972 mb[10] |= BIT_0; /* Class 2. */ 1973 if (lg->io_parameter[9] || lg->io_parameter[10]) 1974 mb[10] |= BIT_1; /* Class 3. */ 1975 if (lg->io_parameter[0] & cpu_to_le32(BIT_7)) 1976 mb[10] |= BIT_7; /* Confirmed Completion 1977 * Allowed 1978 */ 1979 } 1980 1981 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 1982 1983 return rval; 1984 } 1985 1986 /* 1987 * qla2x00_login_fabric 1988 * Issue login fabric port mailbox command. 1989 * 1990 * Input: 1991 * ha = adapter block pointer. 1992 * loop_id = device loop ID. 1993 * domain = device domain. 1994 * area = device area. 1995 * al_pa = device AL_PA. 1996 * status = pointer for return status. 1997 * opt = command options. 1998 * TARGET_QUEUE_LOCK must be released. 1999 * ADAPTER_STATE_LOCK must be released. 2000 * 2001 * Returns: 2002 * qla2x00 local function return status code. 2003 * 2004 * Context: 2005 * Kernel context. 2006 */ 2007 int 2008 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2009 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 2010 { 2011 int rval; 2012 mbx_cmd_t mc; 2013 mbx_cmd_t *mcp = &mc; 2014 struct qla_hw_data *ha = vha->hw; 2015 2016 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067, 2017 "Entered %s.\n", __func__); 2018 2019 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT; 2020 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2021 if (HAS_EXTENDED_IDS(ha)) { 2022 mcp->mb[1] = loop_id; 2023 mcp->mb[10] = opt; 2024 mcp->out_mb |= MBX_10; 2025 } else { 2026 mcp->mb[1] = (loop_id << 8) | opt; 2027 } 2028 mcp->mb[2] = domain; 2029 mcp->mb[3] = area << 8 | al_pa; 2030 2031 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0; 2032 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2033 mcp->flags = 0; 2034 rval = qla2x00_mailbox_command(vha, mcp); 2035 2036 /* Return mailbox statuses. */ 2037 if (mb != NULL) { 2038 mb[0] = mcp->mb[0]; 2039 mb[1] = mcp->mb[1]; 2040 mb[2] = mcp->mb[2]; 2041 mb[6] = mcp->mb[6]; 2042 mb[7] = mcp->mb[7]; 2043 /* COS retrieved from Get-Port-Database mailbox command. */ 2044 mb[10] = 0; 2045 } 2046 2047 if (rval != QLA_SUCCESS) { 2048 /* RLU tmp code: need to change main mailbox_command function to 2049 * return ok even when the mailbox completion value is not 2050 * SUCCESS. The caller needs to be responsible to interpret 2051 * the return values of this mailbox command if we're not 2052 * to change too much of the existing code. 2053 */ 2054 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 || 2055 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 || 2056 mcp->mb[0] == 0x4006) 2057 rval = QLA_SUCCESS; 2058 2059 /*EMPTY*/ 2060 ql_dbg(ql_dbg_mbx, vha, 0x1068, 2061 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 2062 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 2063 } else { 2064 /*EMPTY*/ 2065 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069, 2066 "Done %s.\n", __func__); 2067 } 2068 2069 return rval; 2070 } 2071 2072 /* 2073 * qla2x00_login_local_device 2074 * Issue login loop port mailbox command. 2075 * 2076 * Input: 2077 * ha = adapter block pointer. 2078 * loop_id = device loop ID. 2079 * opt = command options. 2080 * 2081 * Returns: 2082 * Return status code. 2083 * 2084 * Context: 2085 * Kernel context. 2086 * 2087 */ 2088 int 2089 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport, 2090 uint16_t *mb_ret, uint8_t opt) 2091 { 2092 int rval; 2093 mbx_cmd_t mc; 2094 mbx_cmd_t *mcp = &mc; 2095 struct qla_hw_data *ha = vha->hw; 2096 2097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a, 2098 "Entered %s.\n", __func__); 2099 2100 if (IS_FWI2_CAPABLE(ha)) 2101 return qla24xx_login_fabric(vha, fcport->loop_id, 2102 fcport->d_id.b.domain, fcport->d_id.b.area, 2103 fcport->d_id.b.al_pa, mb_ret, opt); 2104 2105 mcp->mb[0] = MBC_LOGIN_LOOP_PORT; 2106 if (HAS_EXTENDED_IDS(ha)) 2107 mcp->mb[1] = fcport->loop_id; 2108 else 2109 mcp->mb[1] = fcport->loop_id << 8; 2110 mcp->mb[2] = opt; 2111 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2112 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0; 2113 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2114 mcp->flags = 0; 2115 rval = qla2x00_mailbox_command(vha, mcp); 2116 2117 /* Return mailbox statuses. */ 2118 if (mb_ret != NULL) { 2119 mb_ret[0] = mcp->mb[0]; 2120 mb_ret[1] = mcp->mb[1]; 2121 mb_ret[6] = mcp->mb[6]; 2122 mb_ret[7] = mcp->mb[7]; 2123 } 2124 2125 if (rval != QLA_SUCCESS) { 2126 /* AV tmp code: need to change main mailbox_command function to 2127 * return ok even when the mailbox completion value is not 2128 * SUCCESS. The caller needs to be responsible to interpret 2129 * the return values of this mailbox command if we're not 2130 * to change too much of the existing code. 2131 */ 2132 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006) 2133 rval = QLA_SUCCESS; 2134 2135 ql_dbg(ql_dbg_mbx, vha, 0x106b, 2136 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n", 2137 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]); 2138 } else { 2139 /*EMPTY*/ 2140 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c, 2141 "Done %s.\n", __func__); 2142 } 2143 2144 return (rval); 2145 } 2146 2147 int 2148 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2149 uint8_t area, uint8_t al_pa) 2150 { 2151 int rval; 2152 struct logio_entry_24xx *lg; 2153 dma_addr_t lg_dma; 2154 struct qla_hw_data *ha = vha->hw; 2155 struct req_que *req; 2156 2157 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d, 2158 "Entered %s.\n", __func__); 2159 2160 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2161 if (lg == NULL) { 2162 ql_log(ql_log_warn, vha, 0x106e, 2163 "Failed to allocate logout IOCB.\n"); 2164 return QLA_MEMORY_ALLOC_FAILED; 2165 } 2166 memset(lg, 0, sizeof(struct logio_entry_24xx)); 2167 2168 if (ql2xmaxqueues > 1) 2169 req = ha->req_q_map[0]; 2170 else 2171 req = vha->req; 2172 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2173 lg->entry_count = 1; 2174 lg->handle = MAKE_HANDLE(req->id, lg->handle); 2175 lg->nport_handle = cpu_to_le16(loop_id); 2176 lg->control_flags = 2177 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO| 2178 LCF_FREE_NPORT); 2179 lg->port_id[0] = al_pa; 2180 lg->port_id[1] = area; 2181 lg->port_id[2] = domain; 2182 lg->vp_index = vha->vp_idx; 2183 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2184 (ha->r_a_tov / 10 * 2) + 2); 2185 if (rval != QLA_SUCCESS) { 2186 ql_dbg(ql_dbg_mbx, vha, 0x106f, 2187 "Failed to issue logout IOCB (%x).\n", rval); 2188 } else if (lg->entry_status != 0) { 2189 ql_dbg(ql_dbg_mbx, vha, 0x1070, 2190 "Failed to complete IOCB -- error status (%x).\n", 2191 lg->entry_status); 2192 rval = QLA_FUNCTION_FAILED; 2193 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 2194 ql_dbg(ql_dbg_mbx, vha, 0x1071, 2195 "Failed to complete IOCB -- completion status (%x) " 2196 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2197 le32_to_cpu(lg->io_parameter[0]), 2198 le32_to_cpu(lg->io_parameter[1])); 2199 } else { 2200 /*EMPTY*/ 2201 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072, 2202 "Done %s.\n", __func__); 2203 } 2204 2205 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2206 2207 return rval; 2208 } 2209 2210 /* 2211 * qla2x00_fabric_logout 2212 * Issue logout fabric port mailbox command. 2213 * 2214 * Input: 2215 * ha = adapter block pointer. 2216 * loop_id = device loop ID. 2217 * TARGET_QUEUE_LOCK must be released. 2218 * ADAPTER_STATE_LOCK must be released. 2219 * 2220 * Returns: 2221 * qla2x00 local function return status code. 2222 * 2223 * Context: 2224 * Kernel context. 2225 */ 2226 int 2227 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2228 uint8_t area, uint8_t al_pa) 2229 { 2230 int rval; 2231 mbx_cmd_t mc; 2232 mbx_cmd_t *mcp = &mc; 2233 2234 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073, 2235 "Entered %s.\n", __func__); 2236 2237 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT; 2238 mcp->out_mb = MBX_1|MBX_0; 2239 if (HAS_EXTENDED_IDS(vha->hw)) { 2240 mcp->mb[1] = loop_id; 2241 mcp->mb[10] = 0; 2242 mcp->out_mb |= MBX_10; 2243 } else { 2244 mcp->mb[1] = loop_id << 8; 2245 } 2246 2247 mcp->in_mb = MBX_1|MBX_0; 2248 mcp->tov = MBX_TOV_SECONDS; 2249 mcp->flags = 0; 2250 rval = qla2x00_mailbox_command(vha, mcp); 2251 2252 if (rval != QLA_SUCCESS) { 2253 /*EMPTY*/ 2254 ql_dbg(ql_dbg_mbx, vha, 0x1074, 2255 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]); 2256 } else { 2257 /*EMPTY*/ 2258 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075, 2259 "Done %s.\n", __func__); 2260 } 2261 2262 return rval; 2263 } 2264 2265 /* 2266 * qla2x00_full_login_lip 2267 * Issue full login LIP mailbox command. 2268 * 2269 * Input: 2270 * ha = adapter block pointer. 2271 * TARGET_QUEUE_LOCK must be released. 2272 * ADAPTER_STATE_LOCK must be released. 2273 * 2274 * Returns: 2275 * qla2x00 local function return status code. 2276 * 2277 * Context: 2278 * Kernel context. 2279 */ 2280 int 2281 qla2x00_full_login_lip(scsi_qla_host_t *vha) 2282 { 2283 int rval; 2284 mbx_cmd_t mc; 2285 mbx_cmd_t *mcp = &mc; 2286 2287 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076, 2288 "Entered %s.\n", __func__); 2289 2290 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2291 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0; 2292 mcp->mb[2] = 0; 2293 mcp->mb[3] = 0; 2294 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2295 mcp->in_mb = MBX_0; 2296 mcp->tov = MBX_TOV_SECONDS; 2297 mcp->flags = 0; 2298 rval = qla2x00_mailbox_command(vha, mcp); 2299 2300 if (rval != QLA_SUCCESS) { 2301 /*EMPTY*/ 2302 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval); 2303 } else { 2304 /*EMPTY*/ 2305 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078, 2306 "Done %s.\n", __func__); 2307 } 2308 2309 return rval; 2310 } 2311 2312 /* 2313 * qla2x00_get_id_list 2314 * 2315 * Input: 2316 * ha = adapter block pointer. 2317 * 2318 * Returns: 2319 * qla2x00 local function return status code. 2320 * 2321 * Context: 2322 * Kernel context. 2323 */ 2324 int 2325 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma, 2326 uint16_t *entries) 2327 { 2328 int rval; 2329 mbx_cmd_t mc; 2330 mbx_cmd_t *mcp = &mc; 2331 2332 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079, 2333 "Entered %s.\n", __func__); 2334 2335 if (id_list == NULL) 2336 return QLA_FUNCTION_FAILED; 2337 2338 mcp->mb[0] = MBC_GET_ID_LIST; 2339 mcp->out_mb = MBX_0; 2340 if (IS_FWI2_CAPABLE(vha->hw)) { 2341 mcp->mb[2] = MSW(id_list_dma); 2342 mcp->mb[3] = LSW(id_list_dma); 2343 mcp->mb[6] = MSW(MSD(id_list_dma)); 2344 mcp->mb[7] = LSW(MSD(id_list_dma)); 2345 mcp->mb[8] = 0; 2346 mcp->mb[9] = vha->vp_idx; 2347 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2; 2348 } else { 2349 mcp->mb[1] = MSW(id_list_dma); 2350 mcp->mb[2] = LSW(id_list_dma); 2351 mcp->mb[3] = MSW(MSD(id_list_dma)); 2352 mcp->mb[6] = LSW(MSD(id_list_dma)); 2353 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1; 2354 } 2355 mcp->in_mb = MBX_1|MBX_0; 2356 mcp->tov = MBX_TOV_SECONDS; 2357 mcp->flags = 0; 2358 rval = qla2x00_mailbox_command(vha, mcp); 2359 2360 if (rval != QLA_SUCCESS) { 2361 /*EMPTY*/ 2362 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval); 2363 } else { 2364 *entries = mcp->mb[1]; 2365 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b, 2366 "Done %s.\n", __func__); 2367 } 2368 2369 return rval; 2370 } 2371 2372 /* 2373 * qla2x00_get_resource_cnts 2374 * Get current firmware resource counts. 2375 * 2376 * Input: 2377 * ha = adapter block pointer. 2378 * 2379 * Returns: 2380 * qla2x00 local function return status code. 2381 * 2382 * Context: 2383 * Kernel context. 2384 */ 2385 int 2386 qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt, 2387 uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt, 2388 uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs) 2389 { 2390 int rval; 2391 mbx_cmd_t mc; 2392 mbx_cmd_t *mcp = &mc; 2393 2394 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c, 2395 "Entered %s.\n", __func__); 2396 2397 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS; 2398 mcp->out_mb = MBX_0; 2399 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2400 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw)) 2401 mcp->in_mb |= MBX_12; 2402 mcp->tov = MBX_TOV_SECONDS; 2403 mcp->flags = 0; 2404 rval = qla2x00_mailbox_command(vha, mcp); 2405 2406 if (rval != QLA_SUCCESS) { 2407 /*EMPTY*/ 2408 ql_dbg(ql_dbg_mbx, vha, 0x107d, 2409 "Failed mb[0]=%x.\n", mcp->mb[0]); 2410 } else { 2411 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e, 2412 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x " 2413 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2], 2414 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10], 2415 mcp->mb[11], mcp->mb[12]); 2416 2417 if (cur_xchg_cnt) 2418 *cur_xchg_cnt = mcp->mb[3]; 2419 if (orig_xchg_cnt) 2420 *orig_xchg_cnt = mcp->mb[6]; 2421 if (cur_iocb_cnt) 2422 *cur_iocb_cnt = mcp->mb[7]; 2423 if (orig_iocb_cnt) 2424 *orig_iocb_cnt = mcp->mb[10]; 2425 if (vha->hw->flags.npiv_supported && max_npiv_vports) 2426 *max_npiv_vports = mcp->mb[11]; 2427 if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || 2428 IS_QLA27XX(vha->hw)) && max_fcfs) 2429 *max_fcfs = mcp->mb[12]; 2430 } 2431 2432 return (rval); 2433 } 2434 2435 /* 2436 * qla2x00_get_fcal_position_map 2437 * Get FCAL (LILP) position map using mailbox command 2438 * 2439 * Input: 2440 * ha = adapter state pointer. 2441 * pos_map = buffer pointer (can be NULL). 2442 * 2443 * Returns: 2444 * qla2x00 local function return status code. 2445 * 2446 * Context: 2447 * Kernel context. 2448 */ 2449 int 2450 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map) 2451 { 2452 int rval; 2453 mbx_cmd_t mc; 2454 mbx_cmd_t *mcp = &mc; 2455 char *pmap; 2456 dma_addr_t pmap_dma; 2457 struct qla_hw_data *ha = vha->hw; 2458 2459 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f, 2460 "Entered %s.\n", __func__); 2461 2462 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma); 2463 if (pmap == NULL) { 2464 ql_log(ql_log_warn, vha, 0x1080, 2465 "Memory alloc failed.\n"); 2466 return QLA_MEMORY_ALLOC_FAILED; 2467 } 2468 memset(pmap, 0, FCAL_MAP_SIZE); 2469 2470 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP; 2471 mcp->mb[2] = MSW(pmap_dma); 2472 mcp->mb[3] = LSW(pmap_dma); 2473 mcp->mb[6] = MSW(MSD(pmap_dma)); 2474 mcp->mb[7] = LSW(MSD(pmap_dma)); 2475 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2476 mcp->in_mb = MBX_1|MBX_0; 2477 mcp->buf_size = FCAL_MAP_SIZE; 2478 mcp->flags = MBX_DMA_IN; 2479 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2480 rval = qla2x00_mailbox_command(vha, mcp); 2481 2482 if (rval == QLA_SUCCESS) { 2483 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081, 2484 "mb0/mb1=%x/%X FC/AL position map size (%x).\n", 2485 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]); 2486 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d, 2487 pmap, pmap[0] + 1); 2488 2489 if (pos_map) 2490 memcpy(pos_map, pmap, FCAL_MAP_SIZE); 2491 } 2492 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma); 2493 2494 if (rval != QLA_SUCCESS) { 2495 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval); 2496 } else { 2497 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083, 2498 "Done %s.\n", __func__); 2499 } 2500 2501 return rval; 2502 } 2503 2504 /* 2505 * qla2x00_get_link_status 2506 * 2507 * Input: 2508 * ha = adapter block pointer. 2509 * loop_id = device loop ID. 2510 * ret_buf = pointer to link status return buffer. 2511 * 2512 * Returns: 2513 * 0 = success. 2514 * BIT_0 = mem alloc error. 2515 * BIT_1 = mailbox error. 2516 */ 2517 int 2518 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id, 2519 struct link_statistics *stats, dma_addr_t stats_dma) 2520 { 2521 int rval; 2522 mbx_cmd_t mc; 2523 mbx_cmd_t *mcp = &mc; 2524 uint32_t *siter, *diter, dwords; 2525 struct qla_hw_data *ha = vha->hw; 2526 2527 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084, 2528 "Entered %s.\n", __func__); 2529 2530 mcp->mb[0] = MBC_GET_LINK_STATUS; 2531 mcp->mb[2] = MSW(stats_dma); 2532 mcp->mb[3] = LSW(stats_dma); 2533 mcp->mb[6] = MSW(MSD(stats_dma)); 2534 mcp->mb[7] = LSW(MSD(stats_dma)); 2535 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2536 mcp->in_mb = MBX_0; 2537 if (IS_FWI2_CAPABLE(ha)) { 2538 mcp->mb[1] = loop_id; 2539 mcp->mb[4] = 0; 2540 mcp->mb[10] = 0; 2541 mcp->out_mb |= MBX_10|MBX_4|MBX_1; 2542 mcp->in_mb |= MBX_1; 2543 } else if (HAS_EXTENDED_IDS(ha)) { 2544 mcp->mb[1] = loop_id; 2545 mcp->mb[10] = 0; 2546 mcp->out_mb |= MBX_10|MBX_1; 2547 } else { 2548 mcp->mb[1] = loop_id << 8; 2549 mcp->out_mb |= MBX_1; 2550 } 2551 mcp->tov = MBX_TOV_SECONDS; 2552 mcp->flags = IOCTL_CMD; 2553 rval = qla2x00_mailbox_command(vha, mcp); 2554 2555 if (rval == QLA_SUCCESS) { 2556 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2557 ql_dbg(ql_dbg_mbx, vha, 0x1085, 2558 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2559 rval = QLA_FUNCTION_FAILED; 2560 } else { 2561 /* Copy over data -- firmware data is LE. */ 2562 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086, 2563 "Done %s.\n", __func__); 2564 dwords = offsetof(struct link_statistics, unused1) / 4; 2565 siter = diter = &stats->link_fail_cnt; 2566 while (dwords--) 2567 *diter++ = le32_to_cpu(*siter++); 2568 } 2569 } else { 2570 /* Failed. */ 2571 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval); 2572 } 2573 2574 return rval; 2575 } 2576 2577 int 2578 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats, 2579 dma_addr_t stats_dma) 2580 { 2581 int rval; 2582 mbx_cmd_t mc; 2583 mbx_cmd_t *mcp = &mc; 2584 uint32_t *siter, *diter, dwords; 2585 2586 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088, 2587 "Entered %s.\n", __func__); 2588 2589 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS; 2590 mcp->mb[2] = MSW(stats_dma); 2591 mcp->mb[3] = LSW(stats_dma); 2592 mcp->mb[6] = MSW(MSD(stats_dma)); 2593 mcp->mb[7] = LSW(MSD(stats_dma)); 2594 mcp->mb[8] = sizeof(struct link_statistics) / 4; 2595 mcp->mb[9] = vha->vp_idx; 2596 mcp->mb[10] = 0; 2597 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2598 mcp->in_mb = MBX_2|MBX_1|MBX_0; 2599 mcp->tov = MBX_TOV_SECONDS; 2600 mcp->flags = IOCTL_CMD; 2601 rval = qla2x00_mailbox_command(vha, mcp); 2602 2603 if (rval == QLA_SUCCESS) { 2604 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2605 ql_dbg(ql_dbg_mbx, vha, 0x1089, 2606 "Failed mb[0]=%x.\n", mcp->mb[0]); 2607 rval = QLA_FUNCTION_FAILED; 2608 } else { 2609 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a, 2610 "Done %s.\n", __func__); 2611 /* Copy over data -- firmware data is LE. */ 2612 dwords = sizeof(struct link_statistics) / 4; 2613 siter = diter = &stats->link_fail_cnt; 2614 while (dwords--) 2615 *diter++ = le32_to_cpu(*siter++); 2616 } 2617 } else { 2618 /* Failed. */ 2619 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval); 2620 } 2621 2622 return rval; 2623 } 2624 2625 int 2626 qla24xx_abort_command(srb_t *sp) 2627 { 2628 int rval; 2629 unsigned long flags = 0; 2630 2631 struct abort_entry_24xx *abt; 2632 dma_addr_t abt_dma; 2633 uint32_t handle; 2634 fc_port_t *fcport = sp->fcport; 2635 struct scsi_qla_host *vha = fcport->vha; 2636 struct qla_hw_data *ha = vha->hw; 2637 struct req_que *req = vha->req; 2638 2639 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c, 2640 "Entered %s.\n", __func__); 2641 2642 if (ql2xasynctmfenable) 2643 return qla24xx_async_abort_command(sp); 2644 2645 spin_lock_irqsave(&ha->hardware_lock, flags); 2646 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 2647 if (req->outstanding_cmds[handle] == sp) 2648 break; 2649 } 2650 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2651 if (handle == req->num_outstanding_cmds) { 2652 /* Command not found. */ 2653 return QLA_FUNCTION_FAILED; 2654 } 2655 2656 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma); 2657 if (abt == NULL) { 2658 ql_log(ql_log_warn, vha, 0x108d, 2659 "Failed to allocate abort IOCB.\n"); 2660 return QLA_MEMORY_ALLOC_FAILED; 2661 } 2662 memset(abt, 0, sizeof(struct abort_entry_24xx)); 2663 2664 abt->entry_type = ABORT_IOCB_TYPE; 2665 abt->entry_count = 1; 2666 abt->handle = MAKE_HANDLE(req->id, abt->handle); 2667 abt->nport_handle = cpu_to_le16(fcport->loop_id); 2668 abt->handle_to_abort = MAKE_HANDLE(req->id, handle); 2669 abt->port_id[0] = fcport->d_id.b.al_pa; 2670 abt->port_id[1] = fcport->d_id.b.area; 2671 abt->port_id[2] = fcport->d_id.b.domain; 2672 abt->vp_index = fcport->vha->vp_idx; 2673 2674 abt->req_que_no = cpu_to_le16(req->id); 2675 2676 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0); 2677 if (rval != QLA_SUCCESS) { 2678 ql_dbg(ql_dbg_mbx, vha, 0x108e, 2679 "Failed to issue IOCB (%x).\n", rval); 2680 } else if (abt->entry_status != 0) { 2681 ql_dbg(ql_dbg_mbx, vha, 0x108f, 2682 "Failed to complete IOCB -- error status (%x).\n", 2683 abt->entry_status); 2684 rval = QLA_FUNCTION_FAILED; 2685 } else if (abt->nport_handle != cpu_to_le16(0)) { 2686 ql_dbg(ql_dbg_mbx, vha, 0x1090, 2687 "Failed to complete IOCB -- completion status (%x).\n", 2688 le16_to_cpu(abt->nport_handle)); 2689 if (abt->nport_handle == CS_IOCB_ERROR) 2690 rval = QLA_FUNCTION_PARAMETER_ERROR; 2691 else 2692 rval = QLA_FUNCTION_FAILED; 2693 } else { 2694 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091, 2695 "Done %s.\n", __func__); 2696 } 2697 2698 dma_pool_free(ha->s_dma_pool, abt, abt_dma); 2699 2700 return rval; 2701 } 2702 2703 struct tsk_mgmt_cmd { 2704 union { 2705 struct tsk_mgmt_entry tsk; 2706 struct sts_entry_24xx sts; 2707 } p; 2708 }; 2709 2710 static int 2711 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport, 2712 uint64_t l, int tag) 2713 { 2714 int rval, rval2; 2715 struct tsk_mgmt_cmd *tsk; 2716 struct sts_entry_24xx *sts; 2717 dma_addr_t tsk_dma; 2718 scsi_qla_host_t *vha; 2719 struct qla_hw_data *ha; 2720 struct req_que *req; 2721 struct rsp_que *rsp; 2722 2723 vha = fcport->vha; 2724 ha = vha->hw; 2725 req = vha->req; 2726 2727 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092, 2728 "Entered %s.\n", __func__); 2729 2730 if (ha->flags.cpu_affinity_enabled) 2731 rsp = ha->rsp_q_map[tag + 1]; 2732 else 2733 rsp = req->rsp; 2734 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma); 2735 if (tsk == NULL) { 2736 ql_log(ql_log_warn, vha, 0x1093, 2737 "Failed to allocate task management IOCB.\n"); 2738 return QLA_MEMORY_ALLOC_FAILED; 2739 } 2740 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd)); 2741 2742 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE; 2743 tsk->p.tsk.entry_count = 1; 2744 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle); 2745 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id); 2746 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2); 2747 tsk->p.tsk.control_flags = cpu_to_le32(type); 2748 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa; 2749 tsk->p.tsk.port_id[1] = fcport->d_id.b.area; 2750 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain; 2751 tsk->p.tsk.vp_index = fcport->vha->vp_idx; 2752 if (type == TCF_LUN_RESET) { 2753 int_to_scsilun(l, &tsk->p.tsk.lun); 2754 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun, 2755 sizeof(tsk->p.tsk.lun)); 2756 } 2757 2758 sts = &tsk->p.sts; 2759 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0); 2760 if (rval != QLA_SUCCESS) { 2761 ql_dbg(ql_dbg_mbx, vha, 0x1094, 2762 "Failed to issue %s reset IOCB (%x).\n", name, rval); 2763 } else if (sts->entry_status != 0) { 2764 ql_dbg(ql_dbg_mbx, vha, 0x1095, 2765 "Failed to complete IOCB -- error status (%x).\n", 2766 sts->entry_status); 2767 rval = QLA_FUNCTION_FAILED; 2768 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) { 2769 ql_dbg(ql_dbg_mbx, vha, 0x1096, 2770 "Failed to complete IOCB -- completion status (%x).\n", 2771 le16_to_cpu(sts->comp_status)); 2772 rval = QLA_FUNCTION_FAILED; 2773 } else if (le16_to_cpu(sts->scsi_status) & 2774 SS_RESPONSE_INFO_LEN_VALID) { 2775 if (le32_to_cpu(sts->rsp_data_len) < 4) { 2776 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097, 2777 "Ignoring inconsistent data length -- not enough " 2778 "response info (%d).\n", 2779 le32_to_cpu(sts->rsp_data_len)); 2780 } else if (sts->data[3]) { 2781 ql_dbg(ql_dbg_mbx, vha, 0x1098, 2782 "Failed to complete IOCB -- response (%x).\n", 2783 sts->data[3]); 2784 rval = QLA_FUNCTION_FAILED; 2785 } 2786 } 2787 2788 /* Issue marker IOCB. */ 2789 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 2790 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID); 2791 if (rval2 != QLA_SUCCESS) { 2792 ql_dbg(ql_dbg_mbx, vha, 0x1099, 2793 "Failed to issue marker IOCB (%x).\n", rval2); 2794 } else { 2795 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a, 2796 "Done %s.\n", __func__); 2797 } 2798 2799 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma); 2800 2801 return rval; 2802 } 2803 2804 int 2805 qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag) 2806 { 2807 struct qla_hw_data *ha = fcport->vha->hw; 2808 2809 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 2810 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag); 2811 2812 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag); 2813 } 2814 2815 int 2816 qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 2817 { 2818 struct qla_hw_data *ha = fcport->vha->hw; 2819 2820 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 2821 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag); 2822 2823 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag); 2824 } 2825 2826 int 2827 qla2x00_system_error(scsi_qla_host_t *vha) 2828 { 2829 int rval; 2830 mbx_cmd_t mc; 2831 mbx_cmd_t *mcp = &mc; 2832 struct qla_hw_data *ha = vha->hw; 2833 2834 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha)) 2835 return QLA_FUNCTION_FAILED; 2836 2837 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b, 2838 "Entered %s.\n", __func__); 2839 2840 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR; 2841 mcp->out_mb = MBX_0; 2842 mcp->in_mb = MBX_0; 2843 mcp->tov = 5; 2844 mcp->flags = 0; 2845 rval = qla2x00_mailbox_command(vha, mcp); 2846 2847 if (rval != QLA_SUCCESS) { 2848 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval); 2849 } else { 2850 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d, 2851 "Done %s.\n", __func__); 2852 } 2853 2854 return rval; 2855 } 2856 2857 int 2858 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data) 2859 { 2860 int rval; 2861 mbx_cmd_t mc; 2862 mbx_cmd_t *mcp = &mc; 2863 2864 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 2865 !IS_QLA27XX(vha->hw)) 2866 return QLA_FUNCTION_FAILED; 2867 2868 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182, 2869 "Entered %s.\n", __func__); 2870 2871 mcp->mb[0] = MBC_WRITE_SERDES; 2872 mcp->mb[1] = addr; 2873 if (IS_QLA2031(vha->hw)) 2874 mcp->mb[2] = data & 0xff; 2875 else 2876 mcp->mb[2] = data; 2877 2878 mcp->mb[3] = 0; 2879 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2880 mcp->in_mb = MBX_0; 2881 mcp->tov = MBX_TOV_SECONDS; 2882 mcp->flags = 0; 2883 rval = qla2x00_mailbox_command(vha, mcp); 2884 2885 if (rval != QLA_SUCCESS) { 2886 ql_dbg(ql_dbg_mbx, vha, 0x1183, 2887 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2888 } else { 2889 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184, 2890 "Done %s.\n", __func__); 2891 } 2892 2893 return rval; 2894 } 2895 2896 int 2897 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data) 2898 { 2899 int rval; 2900 mbx_cmd_t mc; 2901 mbx_cmd_t *mcp = &mc; 2902 2903 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 2904 !IS_QLA27XX(vha->hw)) 2905 return QLA_FUNCTION_FAILED; 2906 2907 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185, 2908 "Entered %s.\n", __func__); 2909 2910 mcp->mb[0] = MBC_READ_SERDES; 2911 mcp->mb[1] = addr; 2912 mcp->mb[3] = 0; 2913 mcp->out_mb = MBX_3|MBX_1|MBX_0; 2914 mcp->in_mb = MBX_1|MBX_0; 2915 mcp->tov = MBX_TOV_SECONDS; 2916 mcp->flags = 0; 2917 rval = qla2x00_mailbox_command(vha, mcp); 2918 2919 if (IS_QLA2031(vha->hw)) 2920 *data = mcp->mb[1] & 0xff; 2921 else 2922 *data = mcp->mb[1]; 2923 2924 if (rval != QLA_SUCCESS) { 2925 ql_dbg(ql_dbg_mbx, vha, 0x1186, 2926 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2927 } else { 2928 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187, 2929 "Done %s.\n", __func__); 2930 } 2931 2932 return rval; 2933 } 2934 2935 int 2936 qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) 2937 { 2938 int rval; 2939 mbx_cmd_t mc; 2940 mbx_cmd_t *mcp = &mc; 2941 2942 if (!IS_QLA8044(vha->hw)) 2943 return QLA_FUNCTION_FAILED; 2944 2945 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1186, 2946 "Entered %s.\n", __func__); 2947 2948 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 2949 mcp->mb[1] = HCS_WRITE_SERDES; 2950 mcp->mb[3] = LSW(addr); 2951 mcp->mb[4] = MSW(addr); 2952 mcp->mb[5] = LSW(data); 2953 mcp->mb[6] = MSW(data); 2954 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0; 2955 mcp->in_mb = MBX_0; 2956 mcp->tov = MBX_TOV_SECONDS; 2957 mcp->flags = 0; 2958 rval = qla2x00_mailbox_command(vha, mcp); 2959 2960 if (rval != QLA_SUCCESS) { 2961 ql_dbg(ql_dbg_mbx, vha, 0x1187, 2962 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2963 } else { 2964 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188, 2965 "Done %s.\n", __func__); 2966 } 2967 2968 return rval; 2969 } 2970 2971 int 2972 qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) 2973 { 2974 int rval; 2975 mbx_cmd_t mc; 2976 mbx_cmd_t *mcp = &mc; 2977 2978 if (!IS_QLA8044(vha->hw)) 2979 return QLA_FUNCTION_FAILED; 2980 2981 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189, 2982 "Entered %s.\n", __func__); 2983 2984 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 2985 mcp->mb[1] = HCS_READ_SERDES; 2986 mcp->mb[3] = LSW(addr); 2987 mcp->mb[4] = MSW(addr); 2988 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0; 2989 mcp->in_mb = MBX_2|MBX_1|MBX_0; 2990 mcp->tov = MBX_TOV_SECONDS; 2991 mcp->flags = 0; 2992 rval = qla2x00_mailbox_command(vha, mcp); 2993 2994 *data = mcp->mb[2] << 16 | mcp->mb[1]; 2995 2996 if (rval != QLA_SUCCESS) { 2997 ql_dbg(ql_dbg_mbx, vha, 0x118a, 2998 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2999 } else { 3000 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b, 3001 "Done %s.\n", __func__); 3002 } 3003 3004 return rval; 3005 } 3006 3007 /** 3008 * qla2x00_set_serdes_params() - 3009 * @ha: HA context 3010 * 3011 * Returns 3012 */ 3013 int 3014 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g, 3015 uint16_t sw_em_2g, uint16_t sw_em_4g) 3016 { 3017 int rval; 3018 mbx_cmd_t mc; 3019 mbx_cmd_t *mcp = &mc; 3020 3021 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e, 3022 "Entered %s.\n", __func__); 3023 3024 mcp->mb[0] = MBC_SERDES_PARAMS; 3025 mcp->mb[1] = BIT_0; 3026 mcp->mb[2] = sw_em_1g | BIT_15; 3027 mcp->mb[3] = sw_em_2g | BIT_15; 3028 mcp->mb[4] = sw_em_4g | BIT_15; 3029 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3030 mcp->in_mb = MBX_0; 3031 mcp->tov = MBX_TOV_SECONDS; 3032 mcp->flags = 0; 3033 rval = qla2x00_mailbox_command(vha, mcp); 3034 3035 if (rval != QLA_SUCCESS) { 3036 /*EMPTY*/ 3037 ql_dbg(ql_dbg_mbx, vha, 0x109f, 3038 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3039 } else { 3040 /*EMPTY*/ 3041 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0, 3042 "Done %s.\n", __func__); 3043 } 3044 3045 return rval; 3046 } 3047 3048 int 3049 qla2x00_stop_firmware(scsi_qla_host_t *vha) 3050 { 3051 int rval; 3052 mbx_cmd_t mc; 3053 mbx_cmd_t *mcp = &mc; 3054 3055 if (!IS_FWI2_CAPABLE(vha->hw)) 3056 return QLA_FUNCTION_FAILED; 3057 3058 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1, 3059 "Entered %s.\n", __func__); 3060 3061 mcp->mb[0] = MBC_STOP_FIRMWARE; 3062 mcp->mb[1] = 0; 3063 mcp->out_mb = MBX_1|MBX_0; 3064 mcp->in_mb = MBX_0; 3065 mcp->tov = 5; 3066 mcp->flags = 0; 3067 rval = qla2x00_mailbox_command(vha, mcp); 3068 3069 if (rval != QLA_SUCCESS) { 3070 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval); 3071 if (mcp->mb[0] == MBS_INVALID_COMMAND) 3072 rval = QLA_INVALID_COMMAND; 3073 } else { 3074 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3, 3075 "Done %s.\n", __func__); 3076 } 3077 3078 return rval; 3079 } 3080 3081 int 3082 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma, 3083 uint16_t buffers) 3084 { 3085 int rval; 3086 mbx_cmd_t mc; 3087 mbx_cmd_t *mcp = &mc; 3088 3089 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4, 3090 "Entered %s.\n", __func__); 3091 3092 if (!IS_FWI2_CAPABLE(vha->hw)) 3093 return QLA_FUNCTION_FAILED; 3094 3095 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3096 return QLA_FUNCTION_FAILED; 3097 3098 mcp->mb[0] = MBC_TRACE_CONTROL; 3099 mcp->mb[1] = TC_EFT_ENABLE; 3100 mcp->mb[2] = LSW(eft_dma); 3101 mcp->mb[3] = MSW(eft_dma); 3102 mcp->mb[4] = LSW(MSD(eft_dma)); 3103 mcp->mb[5] = MSW(MSD(eft_dma)); 3104 mcp->mb[6] = buffers; 3105 mcp->mb[7] = TC_AEN_DISABLE; 3106 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3107 mcp->in_mb = MBX_1|MBX_0; 3108 mcp->tov = MBX_TOV_SECONDS; 3109 mcp->flags = 0; 3110 rval = qla2x00_mailbox_command(vha, mcp); 3111 if (rval != QLA_SUCCESS) { 3112 ql_dbg(ql_dbg_mbx, vha, 0x10a5, 3113 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3114 rval, mcp->mb[0], mcp->mb[1]); 3115 } else { 3116 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6, 3117 "Done %s.\n", __func__); 3118 } 3119 3120 return rval; 3121 } 3122 3123 int 3124 qla2x00_disable_eft_trace(scsi_qla_host_t *vha) 3125 { 3126 int rval; 3127 mbx_cmd_t mc; 3128 mbx_cmd_t *mcp = &mc; 3129 3130 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7, 3131 "Entered %s.\n", __func__); 3132 3133 if (!IS_FWI2_CAPABLE(vha->hw)) 3134 return QLA_FUNCTION_FAILED; 3135 3136 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3137 return QLA_FUNCTION_FAILED; 3138 3139 mcp->mb[0] = MBC_TRACE_CONTROL; 3140 mcp->mb[1] = TC_EFT_DISABLE; 3141 mcp->out_mb = MBX_1|MBX_0; 3142 mcp->in_mb = MBX_1|MBX_0; 3143 mcp->tov = MBX_TOV_SECONDS; 3144 mcp->flags = 0; 3145 rval = qla2x00_mailbox_command(vha, mcp); 3146 if (rval != QLA_SUCCESS) { 3147 ql_dbg(ql_dbg_mbx, vha, 0x10a8, 3148 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3149 rval, mcp->mb[0], mcp->mb[1]); 3150 } else { 3151 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9, 3152 "Done %s.\n", __func__); 3153 } 3154 3155 return rval; 3156 } 3157 3158 int 3159 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma, 3160 uint16_t buffers, uint16_t *mb, uint32_t *dwords) 3161 { 3162 int rval; 3163 mbx_cmd_t mc; 3164 mbx_cmd_t *mcp = &mc; 3165 3166 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa, 3167 "Entered %s.\n", __func__); 3168 3169 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) && 3170 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw)) 3171 return QLA_FUNCTION_FAILED; 3172 3173 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3174 return QLA_FUNCTION_FAILED; 3175 3176 mcp->mb[0] = MBC_TRACE_CONTROL; 3177 mcp->mb[1] = TC_FCE_ENABLE; 3178 mcp->mb[2] = LSW(fce_dma); 3179 mcp->mb[3] = MSW(fce_dma); 3180 mcp->mb[4] = LSW(MSD(fce_dma)); 3181 mcp->mb[5] = MSW(MSD(fce_dma)); 3182 mcp->mb[6] = buffers; 3183 mcp->mb[7] = TC_AEN_DISABLE; 3184 mcp->mb[8] = 0; 3185 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE; 3186 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE; 3187 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3188 MBX_1|MBX_0; 3189 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3190 mcp->tov = MBX_TOV_SECONDS; 3191 mcp->flags = 0; 3192 rval = qla2x00_mailbox_command(vha, mcp); 3193 if (rval != QLA_SUCCESS) { 3194 ql_dbg(ql_dbg_mbx, vha, 0x10ab, 3195 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3196 rval, mcp->mb[0], mcp->mb[1]); 3197 } else { 3198 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac, 3199 "Done %s.\n", __func__); 3200 3201 if (mb) 3202 memcpy(mb, mcp->mb, 8 * sizeof(*mb)); 3203 if (dwords) 3204 *dwords = buffers; 3205 } 3206 3207 return rval; 3208 } 3209 3210 int 3211 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd) 3212 { 3213 int rval; 3214 mbx_cmd_t mc; 3215 mbx_cmd_t *mcp = &mc; 3216 3217 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad, 3218 "Entered %s.\n", __func__); 3219 3220 if (!IS_FWI2_CAPABLE(vha->hw)) 3221 return QLA_FUNCTION_FAILED; 3222 3223 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3224 return QLA_FUNCTION_FAILED; 3225 3226 mcp->mb[0] = MBC_TRACE_CONTROL; 3227 mcp->mb[1] = TC_FCE_DISABLE; 3228 mcp->mb[2] = TC_FCE_DISABLE_TRACE; 3229 mcp->out_mb = MBX_2|MBX_1|MBX_0; 3230 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3231 MBX_1|MBX_0; 3232 mcp->tov = MBX_TOV_SECONDS; 3233 mcp->flags = 0; 3234 rval = qla2x00_mailbox_command(vha, mcp); 3235 if (rval != QLA_SUCCESS) { 3236 ql_dbg(ql_dbg_mbx, vha, 0x10ae, 3237 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3238 rval, mcp->mb[0], mcp->mb[1]); 3239 } else { 3240 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af, 3241 "Done %s.\n", __func__); 3242 3243 if (wr) 3244 *wr = (uint64_t) mcp->mb[5] << 48 | 3245 (uint64_t) mcp->mb[4] << 32 | 3246 (uint64_t) mcp->mb[3] << 16 | 3247 (uint64_t) mcp->mb[2]; 3248 if (rd) 3249 *rd = (uint64_t) mcp->mb[9] << 48 | 3250 (uint64_t) mcp->mb[8] << 32 | 3251 (uint64_t) mcp->mb[7] << 16 | 3252 (uint64_t) mcp->mb[6]; 3253 } 3254 3255 return rval; 3256 } 3257 3258 int 3259 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3260 uint16_t *port_speed, uint16_t *mb) 3261 { 3262 int rval; 3263 mbx_cmd_t mc; 3264 mbx_cmd_t *mcp = &mc; 3265 3266 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0, 3267 "Entered %s.\n", __func__); 3268 3269 if (!IS_IIDMA_CAPABLE(vha->hw)) 3270 return QLA_FUNCTION_FAILED; 3271 3272 mcp->mb[0] = MBC_PORT_PARAMS; 3273 mcp->mb[1] = loop_id; 3274 mcp->mb[2] = mcp->mb[3] = 0; 3275 mcp->mb[9] = vha->vp_idx; 3276 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3277 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3278 mcp->tov = MBX_TOV_SECONDS; 3279 mcp->flags = 0; 3280 rval = qla2x00_mailbox_command(vha, mcp); 3281 3282 /* Return mailbox statuses. */ 3283 if (mb != NULL) { 3284 mb[0] = mcp->mb[0]; 3285 mb[1] = mcp->mb[1]; 3286 mb[3] = mcp->mb[3]; 3287 } 3288 3289 if (rval != QLA_SUCCESS) { 3290 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval); 3291 } else { 3292 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2, 3293 "Done %s.\n", __func__); 3294 if (port_speed) 3295 *port_speed = mcp->mb[3]; 3296 } 3297 3298 return rval; 3299 } 3300 3301 int 3302 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3303 uint16_t port_speed, uint16_t *mb) 3304 { 3305 int rval; 3306 mbx_cmd_t mc; 3307 mbx_cmd_t *mcp = &mc; 3308 3309 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3, 3310 "Entered %s.\n", __func__); 3311 3312 if (!IS_IIDMA_CAPABLE(vha->hw)) 3313 return QLA_FUNCTION_FAILED; 3314 3315 mcp->mb[0] = MBC_PORT_PARAMS; 3316 mcp->mb[1] = loop_id; 3317 mcp->mb[2] = BIT_0; 3318 if (IS_CNA_CAPABLE(vha->hw)) 3319 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); 3320 else 3321 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); 3322 mcp->mb[9] = vha->vp_idx; 3323 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3324 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3325 mcp->tov = MBX_TOV_SECONDS; 3326 mcp->flags = 0; 3327 rval = qla2x00_mailbox_command(vha, mcp); 3328 3329 /* Return mailbox statuses. */ 3330 if (mb != NULL) { 3331 mb[0] = mcp->mb[0]; 3332 mb[1] = mcp->mb[1]; 3333 mb[3] = mcp->mb[3]; 3334 } 3335 3336 if (rval != QLA_SUCCESS) { 3337 ql_dbg(ql_dbg_mbx, vha, 0x10b4, 3338 "Failed=%x.\n", rval); 3339 } else { 3340 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5, 3341 "Done %s.\n", __func__); 3342 } 3343 3344 return rval; 3345 } 3346 3347 void 3348 qla24xx_report_id_acquisition(scsi_qla_host_t *vha, 3349 struct vp_rpt_id_entry_24xx *rptid_entry) 3350 { 3351 uint8_t vp_idx; 3352 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx); 3353 struct qla_hw_data *ha = vha->hw; 3354 scsi_qla_host_t *vp; 3355 unsigned long flags; 3356 int found; 3357 3358 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6, 3359 "Entered %s.\n", __func__); 3360 3361 if (rptid_entry->entry_status != 0) 3362 return; 3363 3364 if (rptid_entry->format == 0) { 3365 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7, 3366 "Format 0 : Number of VPs setup %d, number of " 3367 "VPs acquired %d.\n", 3368 MSB(le16_to_cpu(rptid_entry->vp_count)), 3369 LSB(le16_to_cpu(rptid_entry->vp_count))); 3370 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8, 3371 "Primary port id %02x%02x%02x.\n", 3372 rptid_entry->port_id[2], rptid_entry->port_id[1], 3373 rptid_entry->port_id[0]); 3374 } else if (rptid_entry->format == 1) { 3375 vp_idx = LSB(stat); 3376 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9, 3377 "Format 1: VP[%d] enabled - status %d - with " 3378 "port id %02x%02x%02x.\n", vp_idx, MSB(stat), 3379 rptid_entry->port_id[2], rptid_entry->port_id[1], 3380 rptid_entry->port_id[0]); 3381 3382 /* FA-WWN is only for physical port */ 3383 if (!vp_idx) { 3384 void *wwpn = ha->init_cb->port_name; 3385 3386 if (!MSB(stat)) { 3387 if (rptid_entry->vp_idx_map[1] & BIT_6) 3388 wwpn = rptid_entry->reserved_4 + 8; 3389 } 3390 memcpy(vha->port_name, wwpn, WWN_SIZE); 3391 fc_host_port_name(vha->host) = 3392 wwn_to_u64(vha->port_name); 3393 ql_dbg(ql_dbg_mbx, vha, 0x1018, 3394 "FA-WWN portname %016llx (%x)\n", 3395 fc_host_port_name(vha->host), MSB(stat)); 3396 } 3397 3398 vp = vha; 3399 if (vp_idx == 0) 3400 goto reg_needed; 3401 3402 if (MSB(stat) != 0 && MSB(stat) != 2) { 3403 ql_dbg(ql_dbg_mbx, vha, 0x10ba, 3404 "Could not acquire ID for VP[%d].\n", vp_idx); 3405 return; 3406 } 3407 3408 found = 0; 3409 spin_lock_irqsave(&ha->vport_slock, flags); 3410 list_for_each_entry(vp, &ha->vp_list, list) { 3411 if (vp_idx == vp->vp_idx) { 3412 found = 1; 3413 break; 3414 } 3415 } 3416 spin_unlock_irqrestore(&ha->vport_slock, flags); 3417 3418 if (!found) 3419 return; 3420 3421 vp->d_id.b.domain = rptid_entry->port_id[2]; 3422 vp->d_id.b.area = rptid_entry->port_id[1]; 3423 vp->d_id.b.al_pa = rptid_entry->port_id[0]; 3424 3425 /* 3426 * Cannot configure here as we are still sitting on the 3427 * response queue. Handle it in dpc context. 3428 */ 3429 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags); 3430 3431 reg_needed: 3432 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags); 3433 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags); 3434 set_bit(VP_DPC_NEEDED, &vha->dpc_flags); 3435 qla2xxx_wake_dpc(vha); 3436 } 3437 } 3438 3439 /* 3440 * qla24xx_modify_vp_config 3441 * Change VP configuration for vha 3442 * 3443 * Input: 3444 * vha = adapter block pointer. 3445 * 3446 * Returns: 3447 * qla2xxx local function return status code. 3448 * 3449 * Context: 3450 * Kernel context. 3451 */ 3452 int 3453 qla24xx_modify_vp_config(scsi_qla_host_t *vha) 3454 { 3455 int rval; 3456 struct vp_config_entry_24xx *vpmod; 3457 dma_addr_t vpmod_dma; 3458 struct qla_hw_data *ha = vha->hw; 3459 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3460 3461 /* This can be called by the parent */ 3462 3463 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb, 3464 "Entered %s.\n", __func__); 3465 3466 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma); 3467 if (!vpmod) { 3468 ql_log(ql_log_warn, vha, 0x10bc, 3469 "Failed to allocate modify VP IOCB.\n"); 3470 return QLA_MEMORY_ALLOC_FAILED; 3471 } 3472 3473 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx)); 3474 vpmod->entry_type = VP_CONFIG_IOCB_TYPE; 3475 vpmod->entry_count = 1; 3476 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS; 3477 vpmod->vp_count = 1; 3478 vpmod->vp_index1 = vha->vp_idx; 3479 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; 3480 3481 qlt_modify_vp_config(vha, vpmod); 3482 3483 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE); 3484 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE); 3485 vpmod->entry_count = 1; 3486 3487 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0); 3488 if (rval != QLA_SUCCESS) { 3489 ql_dbg(ql_dbg_mbx, vha, 0x10bd, 3490 "Failed to issue VP config IOCB (%x).\n", rval); 3491 } else if (vpmod->comp_status != 0) { 3492 ql_dbg(ql_dbg_mbx, vha, 0x10be, 3493 "Failed to complete IOCB -- error status (%x).\n", 3494 vpmod->comp_status); 3495 rval = QLA_FUNCTION_FAILED; 3496 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) { 3497 ql_dbg(ql_dbg_mbx, vha, 0x10bf, 3498 "Failed to complete IOCB -- completion status (%x).\n", 3499 le16_to_cpu(vpmod->comp_status)); 3500 rval = QLA_FUNCTION_FAILED; 3501 } else { 3502 /* EMPTY */ 3503 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0, 3504 "Done %s.\n", __func__); 3505 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING); 3506 } 3507 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma); 3508 3509 return rval; 3510 } 3511 3512 /* 3513 * qla24xx_control_vp 3514 * Enable a virtual port for given host 3515 * 3516 * Input: 3517 * ha = adapter block pointer. 3518 * vhba = virtual adapter (unused) 3519 * index = index number for enabled VP 3520 * 3521 * Returns: 3522 * qla2xxx local function return status code. 3523 * 3524 * Context: 3525 * Kernel context. 3526 */ 3527 int 3528 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd) 3529 { 3530 int rval; 3531 int map, pos; 3532 struct vp_ctrl_entry_24xx *vce; 3533 dma_addr_t vce_dma; 3534 struct qla_hw_data *ha = vha->hw; 3535 int vp_index = vha->vp_idx; 3536 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3537 3538 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1, 3539 "Entered %s enabling index %d.\n", __func__, vp_index); 3540 3541 if (vp_index == 0 || vp_index >= ha->max_npiv_vports) 3542 return QLA_PARAMETER_ERROR; 3543 3544 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma); 3545 if (!vce) { 3546 ql_log(ql_log_warn, vha, 0x10c2, 3547 "Failed to allocate VP control IOCB.\n"); 3548 return QLA_MEMORY_ALLOC_FAILED; 3549 } 3550 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx)); 3551 3552 vce->entry_type = VP_CTRL_IOCB_TYPE; 3553 vce->entry_count = 1; 3554 vce->command = cpu_to_le16(cmd); 3555 vce->vp_count = cpu_to_le16(1); 3556 3557 /* index map in firmware starts with 1; decrement index 3558 * this is ok as we never use index 0 3559 */ 3560 map = (vp_index - 1) / 8; 3561 pos = (vp_index - 1) & 7; 3562 mutex_lock(&ha->vport_lock); 3563 vce->vp_idx_map[map] |= 1 << pos; 3564 mutex_unlock(&ha->vport_lock); 3565 3566 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0); 3567 if (rval != QLA_SUCCESS) { 3568 ql_dbg(ql_dbg_mbx, vha, 0x10c3, 3569 "Failed to issue VP control IOCB (%x).\n", rval); 3570 } else if (vce->entry_status != 0) { 3571 ql_dbg(ql_dbg_mbx, vha, 0x10c4, 3572 "Failed to complete IOCB -- error status (%x).\n", 3573 vce->entry_status); 3574 rval = QLA_FUNCTION_FAILED; 3575 } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) { 3576 ql_dbg(ql_dbg_mbx, vha, 0x10c5, 3577 "Failed to complet IOCB -- completion status (%x).\n", 3578 le16_to_cpu(vce->comp_status)); 3579 rval = QLA_FUNCTION_FAILED; 3580 } else { 3581 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6, 3582 "Done %s.\n", __func__); 3583 } 3584 3585 dma_pool_free(ha->s_dma_pool, vce, vce_dma); 3586 3587 return rval; 3588 } 3589 3590 /* 3591 * qla2x00_send_change_request 3592 * Receive or disable RSCN request from fabric controller 3593 * 3594 * Input: 3595 * ha = adapter block pointer 3596 * format = registration format: 3597 * 0 - Reserved 3598 * 1 - Fabric detected registration 3599 * 2 - N_port detected registration 3600 * 3 - Full registration 3601 * FF - clear registration 3602 * vp_idx = Virtual port index 3603 * 3604 * Returns: 3605 * qla2x00 local function return status code. 3606 * 3607 * Context: 3608 * Kernel Context 3609 */ 3610 3611 int 3612 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format, 3613 uint16_t vp_idx) 3614 { 3615 int rval; 3616 mbx_cmd_t mc; 3617 mbx_cmd_t *mcp = &mc; 3618 3619 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7, 3620 "Entered %s.\n", __func__); 3621 3622 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST; 3623 mcp->mb[1] = format; 3624 mcp->mb[9] = vp_idx; 3625 mcp->out_mb = MBX_9|MBX_1|MBX_0; 3626 mcp->in_mb = MBX_0|MBX_1; 3627 mcp->tov = MBX_TOV_SECONDS; 3628 mcp->flags = 0; 3629 rval = qla2x00_mailbox_command(vha, mcp); 3630 3631 if (rval == QLA_SUCCESS) { 3632 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 3633 rval = BIT_1; 3634 } 3635 } else 3636 rval = BIT_1; 3637 3638 return rval; 3639 } 3640 3641 int 3642 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 3643 uint32_t size) 3644 { 3645 int rval; 3646 mbx_cmd_t mc; 3647 mbx_cmd_t *mcp = &mc; 3648 3649 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009, 3650 "Entered %s.\n", __func__); 3651 3652 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) { 3653 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 3654 mcp->mb[8] = MSW(addr); 3655 mcp->out_mb = MBX_8|MBX_0; 3656 } else { 3657 mcp->mb[0] = MBC_DUMP_RISC_RAM; 3658 mcp->out_mb = MBX_0; 3659 } 3660 mcp->mb[1] = LSW(addr); 3661 mcp->mb[2] = MSW(req_dma); 3662 mcp->mb[3] = LSW(req_dma); 3663 mcp->mb[6] = MSW(MSD(req_dma)); 3664 mcp->mb[7] = LSW(MSD(req_dma)); 3665 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 3666 if (IS_FWI2_CAPABLE(vha->hw)) { 3667 mcp->mb[4] = MSW(size); 3668 mcp->mb[5] = LSW(size); 3669 mcp->out_mb |= MBX_5|MBX_4; 3670 } else { 3671 mcp->mb[4] = LSW(size); 3672 mcp->out_mb |= MBX_4; 3673 } 3674 3675 mcp->in_mb = MBX_0; 3676 mcp->tov = MBX_TOV_SECONDS; 3677 mcp->flags = 0; 3678 rval = qla2x00_mailbox_command(vha, mcp); 3679 3680 if (rval != QLA_SUCCESS) { 3681 ql_dbg(ql_dbg_mbx, vha, 0x1008, 3682 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3683 } else { 3684 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007, 3685 "Done %s.\n", __func__); 3686 } 3687 3688 return rval; 3689 } 3690 /* 84XX Support **************************************************************/ 3691 3692 struct cs84xx_mgmt_cmd { 3693 union { 3694 struct verify_chip_entry_84xx req; 3695 struct verify_chip_rsp_84xx rsp; 3696 } p; 3697 }; 3698 3699 int 3700 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status) 3701 { 3702 int rval, retry; 3703 struct cs84xx_mgmt_cmd *mn; 3704 dma_addr_t mn_dma; 3705 uint16_t options; 3706 unsigned long flags; 3707 struct qla_hw_data *ha = vha->hw; 3708 3709 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8, 3710 "Entered %s.\n", __func__); 3711 3712 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma); 3713 if (mn == NULL) { 3714 return QLA_MEMORY_ALLOC_FAILED; 3715 } 3716 3717 /* Force Update? */ 3718 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0; 3719 /* Diagnostic firmware? */ 3720 /* options |= MENLO_DIAG_FW; */ 3721 /* We update the firmware with only one data sequence. */ 3722 options |= VCO_END_OF_DATA; 3723 3724 do { 3725 retry = 0; 3726 memset(mn, 0, sizeof(*mn)); 3727 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE; 3728 mn->p.req.entry_count = 1; 3729 mn->p.req.options = cpu_to_le16(options); 3730 3731 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c, 3732 "Dump of Verify Request.\n"); 3733 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e, 3734 (uint8_t *)mn, sizeof(*mn)); 3735 3736 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120); 3737 if (rval != QLA_SUCCESS) { 3738 ql_dbg(ql_dbg_mbx, vha, 0x10cb, 3739 "Failed to issue verify IOCB (%x).\n", rval); 3740 goto verify_done; 3741 } 3742 3743 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110, 3744 "Dump of Verify Response.\n"); 3745 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118, 3746 (uint8_t *)mn, sizeof(*mn)); 3747 3748 status[0] = le16_to_cpu(mn->p.rsp.comp_status); 3749 status[1] = status[0] == CS_VCS_CHIP_FAILURE ? 3750 le16_to_cpu(mn->p.rsp.failure_code) : 0; 3751 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce, 3752 "cs=%x fc=%x.\n", status[0], status[1]); 3753 3754 if (status[0] != CS_COMPLETE) { 3755 rval = QLA_FUNCTION_FAILED; 3756 if (!(options & VCO_DONT_UPDATE_FW)) { 3757 ql_dbg(ql_dbg_mbx, vha, 0x10cf, 3758 "Firmware update failed. Retrying " 3759 "without update firmware.\n"); 3760 options |= VCO_DONT_UPDATE_FW; 3761 options &= ~VCO_FORCE_UPDATE; 3762 retry = 1; 3763 } 3764 } else { 3765 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0, 3766 "Firmware updated to %x.\n", 3767 le32_to_cpu(mn->p.rsp.fw_ver)); 3768 3769 /* NOTE: we only update OP firmware. */ 3770 spin_lock_irqsave(&ha->cs84xx->access_lock, flags); 3771 ha->cs84xx->op_fw_version = 3772 le32_to_cpu(mn->p.rsp.fw_ver); 3773 spin_unlock_irqrestore(&ha->cs84xx->access_lock, 3774 flags); 3775 } 3776 } while (retry); 3777 3778 verify_done: 3779 dma_pool_free(ha->s_dma_pool, mn, mn_dma); 3780 3781 if (rval != QLA_SUCCESS) { 3782 ql_dbg(ql_dbg_mbx, vha, 0x10d1, 3783 "Failed=%x.\n", rval); 3784 } else { 3785 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2, 3786 "Done %s.\n", __func__); 3787 } 3788 3789 return rval; 3790 } 3791 3792 int 3793 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req) 3794 { 3795 int rval; 3796 unsigned long flags; 3797 mbx_cmd_t mc; 3798 mbx_cmd_t *mcp = &mc; 3799 struct qla_hw_data *ha = vha->hw; 3800 3801 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3, 3802 "Entered %s.\n", __func__); 3803 3804 if (IS_SHADOW_REG_CAPABLE(ha)) 3805 req->options |= BIT_13; 3806 3807 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 3808 mcp->mb[1] = req->options; 3809 mcp->mb[2] = MSW(LSD(req->dma)); 3810 mcp->mb[3] = LSW(LSD(req->dma)); 3811 mcp->mb[6] = MSW(MSD(req->dma)); 3812 mcp->mb[7] = LSW(MSD(req->dma)); 3813 mcp->mb[5] = req->length; 3814 if (req->rsp) 3815 mcp->mb[10] = req->rsp->id; 3816 mcp->mb[12] = req->qos; 3817 mcp->mb[11] = req->vp_idx; 3818 mcp->mb[13] = req->rid; 3819 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3820 mcp->mb[15] = 0; 3821 3822 mcp->mb[4] = req->id; 3823 /* que in ptr index */ 3824 mcp->mb[8] = 0; 3825 /* que out ptr index */ 3826 mcp->mb[9] = *req->out_ptr = 0; 3827 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7| 3828 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3829 mcp->in_mb = MBX_0; 3830 mcp->flags = MBX_DMA_OUT; 3831 mcp->tov = MBX_TOV_SECONDS * 2; 3832 3833 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3834 mcp->in_mb |= MBX_1; 3835 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3836 mcp->out_mb |= MBX_15; 3837 /* debug q create issue in SR-IOV */ 3838 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 3839 } 3840 3841 spin_lock_irqsave(&ha->hardware_lock, flags); 3842 if (!(req->options & BIT_0)) { 3843 WRT_REG_DWORD(req->req_q_in, 0); 3844 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 3845 WRT_REG_DWORD(req->req_q_out, 0); 3846 } 3847 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3848 3849 rval = qla2x00_mailbox_command(vha, mcp); 3850 if (rval != QLA_SUCCESS) { 3851 ql_dbg(ql_dbg_mbx, vha, 0x10d4, 3852 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3853 } else { 3854 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5, 3855 "Done %s.\n", __func__); 3856 } 3857 3858 return rval; 3859 } 3860 3861 int 3862 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp) 3863 { 3864 int rval; 3865 unsigned long flags; 3866 mbx_cmd_t mc; 3867 mbx_cmd_t *mcp = &mc; 3868 struct qla_hw_data *ha = vha->hw; 3869 3870 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6, 3871 "Entered %s.\n", __func__); 3872 3873 if (IS_SHADOW_REG_CAPABLE(ha)) 3874 rsp->options |= BIT_13; 3875 3876 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 3877 mcp->mb[1] = rsp->options; 3878 mcp->mb[2] = MSW(LSD(rsp->dma)); 3879 mcp->mb[3] = LSW(LSD(rsp->dma)); 3880 mcp->mb[6] = MSW(MSD(rsp->dma)); 3881 mcp->mb[7] = LSW(MSD(rsp->dma)); 3882 mcp->mb[5] = rsp->length; 3883 mcp->mb[14] = rsp->msix->entry; 3884 mcp->mb[13] = rsp->rid; 3885 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3886 mcp->mb[15] = 0; 3887 3888 mcp->mb[4] = rsp->id; 3889 /* que in ptr index */ 3890 mcp->mb[8] = *rsp->in_ptr = 0; 3891 /* que out ptr index */ 3892 mcp->mb[9] = 0; 3893 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7 3894 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3895 mcp->in_mb = MBX_0; 3896 mcp->flags = MBX_DMA_OUT; 3897 mcp->tov = MBX_TOV_SECONDS * 2; 3898 3899 if (IS_QLA81XX(ha)) { 3900 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 3901 mcp->in_mb |= MBX_1; 3902 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3903 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10; 3904 mcp->in_mb |= MBX_1; 3905 /* debug q create issue in SR-IOV */ 3906 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 3907 } 3908 3909 spin_lock_irqsave(&ha->hardware_lock, flags); 3910 if (!(rsp->options & BIT_0)) { 3911 WRT_REG_DWORD(rsp->rsp_q_out, 0); 3912 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 3913 WRT_REG_DWORD(rsp->rsp_q_in, 0); 3914 } 3915 3916 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3917 3918 rval = qla2x00_mailbox_command(vha, mcp); 3919 if (rval != QLA_SUCCESS) { 3920 ql_dbg(ql_dbg_mbx, vha, 0x10d7, 3921 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3922 } else { 3923 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8, 3924 "Done %s.\n", __func__); 3925 } 3926 3927 return rval; 3928 } 3929 3930 int 3931 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb) 3932 { 3933 int rval; 3934 mbx_cmd_t mc; 3935 mbx_cmd_t *mcp = &mc; 3936 3937 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9, 3938 "Entered %s.\n", __func__); 3939 3940 mcp->mb[0] = MBC_IDC_ACK; 3941 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3942 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3943 mcp->in_mb = MBX_0; 3944 mcp->tov = MBX_TOV_SECONDS; 3945 mcp->flags = 0; 3946 rval = qla2x00_mailbox_command(vha, mcp); 3947 3948 if (rval != QLA_SUCCESS) { 3949 ql_dbg(ql_dbg_mbx, vha, 0x10da, 3950 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3951 } else { 3952 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db, 3953 "Done %s.\n", __func__); 3954 } 3955 3956 return rval; 3957 } 3958 3959 int 3960 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size) 3961 { 3962 int rval; 3963 mbx_cmd_t mc; 3964 mbx_cmd_t *mcp = &mc; 3965 3966 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc, 3967 "Entered %s.\n", __func__); 3968 3969 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 3970 !IS_QLA27XX(vha->hw)) 3971 return QLA_FUNCTION_FAILED; 3972 3973 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 3974 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE; 3975 mcp->out_mb = MBX_1|MBX_0; 3976 mcp->in_mb = MBX_1|MBX_0; 3977 mcp->tov = MBX_TOV_SECONDS; 3978 mcp->flags = 0; 3979 rval = qla2x00_mailbox_command(vha, mcp); 3980 3981 if (rval != QLA_SUCCESS) { 3982 ql_dbg(ql_dbg_mbx, vha, 0x10dd, 3983 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3984 rval, mcp->mb[0], mcp->mb[1]); 3985 } else { 3986 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de, 3987 "Done %s.\n", __func__); 3988 *sector_size = mcp->mb[1]; 3989 } 3990 3991 return rval; 3992 } 3993 3994 int 3995 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable) 3996 { 3997 int rval; 3998 mbx_cmd_t mc; 3999 mbx_cmd_t *mcp = &mc; 4000 4001 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4002 !IS_QLA27XX(vha->hw)) 4003 return QLA_FUNCTION_FAILED; 4004 4005 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df, 4006 "Entered %s.\n", __func__); 4007 4008 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4009 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE : 4010 FAC_OPT_CMD_WRITE_PROTECT; 4011 mcp->out_mb = MBX_1|MBX_0; 4012 mcp->in_mb = MBX_1|MBX_0; 4013 mcp->tov = MBX_TOV_SECONDS; 4014 mcp->flags = 0; 4015 rval = qla2x00_mailbox_command(vha, mcp); 4016 4017 if (rval != QLA_SUCCESS) { 4018 ql_dbg(ql_dbg_mbx, vha, 0x10e0, 4019 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4020 rval, mcp->mb[0], mcp->mb[1]); 4021 } else { 4022 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1, 4023 "Done %s.\n", __func__); 4024 } 4025 4026 return rval; 4027 } 4028 4029 int 4030 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish) 4031 { 4032 int rval; 4033 mbx_cmd_t mc; 4034 mbx_cmd_t *mcp = &mc; 4035 4036 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4037 !IS_QLA27XX(vha->hw)) 4038 return QLA_FUNCTION_FAILED; 4039 4040 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2, 4041 "Entered %s.\n", __func__); 4042 4043 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4044 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR; 4045 mcp->mb[2] = LSW(start); 4046 mcp->mb[3] = MSW(start); 4047 mcp->mb[4] = LSW(finish); 4048 mcp->mb[5] = MSW(finish); 4049 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4050 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4051 mcp->tov = MBX_TOV_SECONDS; 4052 mcp->flags = 0; 4053 rval = qla2x00_mailbox_command(vha, mcp); 4054 4055 if (rval != QLA_SUCCESS) { 4056 ql_dbg(ql_dbg_mbx, vha, 0x10e3, 4057 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4058 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4059 } else { 4060 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4, 4061 "Done %s.\n", __func__); 4062 } 4063 4064 return rval; 4065 } 4066 4067 int 4068 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha) 4069 { 4070 int rval = 0; 4071 mbx_cmd_t mc; 4072 mbx_cmd_t *mcp = &mc; 4073 4074 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5, 4075 "Entered %s.\n", __func__); 4076 4077 mcp->mb[0] = MBC_RESTART_MPI_FW; 4078 mcp->out_mb = MBX_0; 4079 mcp->in_mb = MBX_0|MBX_1; 4080 mcp->tov = MBX_TOV_SECONDS; 4081 mcp->flags = 0; 4082 rval = qla2x00_mailbox_command(vha, mcp); 4083 4084 if (rval != QLA_SUCCESS) { 4085 ql_dbg(ql_dbg_mbx, vha, 0x10e6, 4086 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4087 rval, mcp->mb[0], mcp->mb[1]); 4088 } else { 4089 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7, 4090 "Done %s.\n", __func__); 4091 } 4092 4093 return rval; 4094 } 4095 4096 int 4097 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4098 { 4099 int rval; 4100 mbx_cmd_t mc; 4101 mbx_cmd_t *mcp = &mc; 4102 int i; 4103 int len; 4104 uint16_t *str; 4105 struct qla_hw_data *ha = vha->hw; 4106 4107 if (!IS_P3P_TYPE(ha)) 4108 return QLA_FUNCTION_FAILED; 4109 4110 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b, 4111 "Entered %s.\n", __func__); 4112 4113 str = (void *)version; 4114 len = strlen(version); 4115 4116 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4117 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8; 4118 mcp->out_mb = MBX_1|MBX_0; 4119 for (i = 4; i < 16 && len; i++, str++, len -= 2) { 4120 mcp->mb[i] = cpu_to_le16p(str); 4121 mcp->out_mb |= 1<<i; 4122 } 4123 for (; i < 16; i++) { 4124 mcp->mb[i] = 0; 4125 mcp->out_mb |= 1<<i; 4126 } 4127 mcp->in_mb = MBX_1|MBX_0; 4128 mcp->tov = MBX_TOV_SECONDS; 4129 mcp->flags = 0; 4130 rval = qla2x00_mailbox_command(vha, mcp); 4131 4132 if (rval != QLA_SUCCESS) { 4133 ql_dbg(ql_dbg_mbx, vha, 0x117c, 4134 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4135 } else { 4136 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d, 4137 "Done %s.\n", __func__); 4138 } 4139 4140 return rval; 4141 } 4142 4143 int 4144 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4145 { 4146 int rval; 4147 mbx_cmd_t mc; 4148 mbx_cmd_t *mcp = &mc; 4149 int len; 4150 uint16_t dwlen; 4151 uint8_t *str; 4152 dma_addr_t str_dma; 4153 struct qla_hw_data *ha = vha->hw; 4154 4155 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) || 4156 IS_P3P_TYPE(ha)) 4157 return QLA_FUNCTION_FAILED; 4158 4159 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e, 4160 "Entered %s.\n", __func__); 4161 4162 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma); 4163 if (!str) { 4164 ql_log(ql_log_warn, vha, 0x117f, 4165 "Failed to allocate driver version param.\n"); 4166 return QLA_MEMORY_ALLOC_FAILED; 4167 } 4168 4169 memcpy(str, "\x7\x3\x11\x0", 4); 4170 dwlen = str[0]; 4171 len = dwlen * 4 - 4; 4172 memset(str + 4, 0, len); 4173 if (len > strlen(version)) 4174 len = strlen(version); 4175 memcpy(str + 4, version, len); 4176 4177 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4178 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen; 4179 mcp->mb[2] = MSW(LSD(str_dma)); 4180 mcp->mb[3] = LSW(LSD(str_dma)); 4181 mcp->mb[6] = MSW(MSD(str_dma)); 4182 mcp->mb[7] = LSW(MSD(str_dma)); 4183 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4184 mcp->in_mb = MBX_1|MBX_0; 4185 mcp->tov = MBX_TOV_SECONDS; 4186 mcp->flags = 0; 4187 rval = qla2x00_mailbox_command(vha, mcp); 4188 4189 if (rval != QLA_SUCCESS) { 4190 ql_dbg(ql_dbg_mbx, vha, 0x1180, 4191 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4192 } else { 4193 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181, 4194 "Done %s.\n", __func__); 4195 } 4196 4197 dma_pool_free(ha->s_dma_pool, str, str_dma); 4198 4199 return rval; 4200 } 4201 4202 static int 4203 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp) 4204 { 4205 int rval; 4206 mbx_cmd_t mc; 4207 mbx_cmd_t *mcp = &mc; 4208 4209 if (!IS_FWI2_CAPABLE(vha->hw)) 4210 return QLA_FUNCTION_FAILED; 4211 4212 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159, 4213 "Entered %s.\n", __func__); 4214 4215 mcp->mb[0] = MBC_GET_RNID_PARAMS; 4216 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8; 4217 mcp->out_mb = MBX_1|MBX_0; 4218 mcp->in_mb = MBX_1|MBX_0; 4219 mcp->tov = MBX_TOV_SECONDS; 4220 mcp->flags = 0; 4221 rval = qla2x00_mailbox_command(vha, mcp); 4222 *temp = mcp->mb[1]; 4223 4224 if (rval != QLA_SUCCESS) { 4225 ql_dbg(ql_dbg_mbx, vha, 0x115a, 4226 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4227 } else { 4228 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b, 4229 "Done %s.\n", __func__); 4230 } 4231 4232 return rval; 4233 } 4234 4235 int 4236 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4237 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4238 { 4239 int rval; 4240 mbx_cmd_t mc; 4241 mbx_cmd_t *mcp = &mc; 4242 struct qla_hw_data *ha = vha->hw; 4243 4244 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8, 4245 "Entered %s.\n", __func__); 4246 4247 if (!IS_FWI2_CAPABLE(ha)) 4248 return QLA_FUNCTION_FAILED; 4249 4250 if (len == 1) 4251 opt |= BIT_0; 4252 4253 mcp->mb[0] = MBC_READ_SFP; 4254 mcp->mb[1] = dev; 4255 mcp->mb[2] = MSW(sfp_dma); 4256 mcp->mb[3] = LSW(sfp_dma); 4257 mcp->mb[6] = MSW(MSD(sfp_dma)); 4258 mcp->mb[7] = LSW(MSD(sfp_dma)); 4259 mcp->mb[8] = len; 4260 mcp->mb[9] = off; 4261 mcp->mb[10] = opt; 4262 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4263 mcp->in_mb = MBX_1|MBX_0; 4264 mcp->tov = MBX_TOV_SECONDS; 4265 mcp->flags = 0; 4266 rval = qla2x00_mailbox_command(vha, mcp); 4267 4268 if (opt & BIT_0) 4269 *sfp = mcp->mb[1]; 4270 4271 if (rval != QLA_SUCCESS) { 4272 ql_dbg(ql_dbg_mbx, vha, 0x10e9, 4273 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4274 } else { 4275 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea, 4276 "Done %s.\n", __func__); 4277 } 4278 4279 return rval; 4280 } 4281 4282 int 4283 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 4284 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 4285 { 4286 int rval; 4287 mbx_cmd_t mc; 4288 mbx_cmd_t *mcp = &mc; 4289 struct qla_hw_data *ha = vha->hw; 4290 4291 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb, 4292 "Entered %s.\n", __func__); 4293 4294 if (!IS_FWI2_CAPABLE(ha)) 4295 return QLA_FUNCTION_FAILED; 4296 4297 if (len == 1) 4298 opt |= BIT_0; 4299 4300 if (opt & BIT_0) 4301 len = *sfp; 4302 4303 mcp->mb[0] = MBC_WRITE_SFP; 4304 mcp->mb[1] = dev; 4305 mcp->mb[2] = MSW(sfp_dma); 4306 mcp->mb[3] = LSW(sfp_dma); 4307 mcp->mb[6] = MSW(MSD(sfp_dma)); 4308 mcp->mb[7] = LSW(MSD(sfp_dma)); 4309 mcp->mb[8] = len; 4310 mcp->mb[9] = off; 4311 mcp->mb[10] = opt; 4312 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4313 mcp->in_mb = MBX_1|MBX_0; 4314 mcp->tov = MBX_TOV_SECONDS; 4315 mcp->flags = 0; 4316 rval = qla2x00_mailbox_command(vha, mcp); 4317 4318 if (rval != QLA_SUCCESS) { 4319 ql_dbg(ql_dbg_mbx, vha, 0x10ec, 4320 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4321 } else { 4322 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed, 4323 "Done %s.\n", __func__); 4324 } 4325 4326 return rval; 4327 } 4328 4329 int 4330 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma, 4331 uint16_t size_in_bytes, uint16_t *actual_size) 4332 { 4333 int rval; 4334 mbx_cmd_t mc; 4335 mbx_cmd_t *mcp = &mc; 4336 4337 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee, 4338 "Entered %s.\n", __func__); 4339 4340 if (!IS_CNA_CAPABLE(vha->hw)) 4341 return QLA_FUNCTION_FAILED; 4342 4343 mcp->mb[0] = MBC_GET_XGMAC_STATS; 4344 mcp->mb[2] = MSW(stats_dma); 4345 mcp->mb[3] = LSW(stats_dma); 4346 mcp->mb[6] = MSW(MSD(stats_dma)); 4347 mcp->mb[7] = LSW(MSD(stats_dma)); 4348 mcp->mb[8] = size_in_bytes >> 2; 4349 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 4350 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4351 mcp->tov = MBX_TOV_SECONDS; 4352 mcp->flags = 0; 4353 rval = qla2x00_mailbox_command(vha, mcp); 4354 4355 if (rval != QLA_SUCCESS) { 4356 ql_dbg(ql_dbg_mbx, vha, 0x10ef, 4357 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4358 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4359 } else { 4360 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0, 4361 "Done %s.\n", __func__); 4362 4363 4364 *actual_size = mcp->mb[2] << 2; 4365 } 4366 4367 return rval; 4368 } 4369 4370 int 4371 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma, 4372 uint16_t size) 4373 { 4374 int rval; 4375 mbx_cmd_t mc; 4376 mbx_cmd_t *mcp = &mc; 4377 4378 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1, 4379 "Entered %s.\n", __func__); 4380 4381 if (!IS_CNA_CAPABLE(vha->hw)) 4382 return QLA_FUNCTION_FAILED; 4383 4384 mcp->mb[0] = MBC_GET_DCBX_PARAMS; 4385 mcp->mb[1] = 0; 4386 mcp->mb[2] = MSW(tlv_dma); 4387 mcp->mb[3] = LSW(tlv_dma); 4388 mcp->mb[6] = MSW(MSD(tlv_dma)); 4389 mcp->mb[7] = LSW(MSD(tlv_dma)); 4390 mcp->mb[8] = size; 4391 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4392 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4393 mcp->tov = MBX_TOV_SECONDS; 4394 mcp->flags = 0; 4395 rval = qla2x00_mailbox_command(vha, mcp); 4396 4397 if (rval != QLA_SUCCESS) { 4398 ql_dbg(ql_dbg_mbx, vha, 0x10f2, 4399 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4400 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4401 } else { 4402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3, 4403 "Done %s.\n", __func__); 4404 } 4405 4406 return rval; 4407 } 4408 4409 int 4410 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data) 4411 { 4412 int rval; 4413 mbx_cmd_t mc; 4414 mbx_cmd_t *mcp = &mc; 4415 4416 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4, 4417 "Entered %s.\n", __func__); 4418 4419 if (!IS_FWI2_CAPABLE(vha->hw)) 4420 return QLA_FUNCTION_FAILED; 4421 4422 mcp->mb[0] = MBC_READ_RAM_EXTENDED; 4423 mcp->mb[1] = LSW(risc_addr); 4424 mcp->mb[8] = MSW(risc_addr); 4425 mcp->out_mb = MBX_8|MBX_1|MBX_0; 4426 mcp->in_mb = MBX_3|MBX_2|MBX_0; 4427 mcp->tov = 30; 4428 mcp->flags = 0; 4429 rval = qla2x00_mailbox_command(vha, mcp); 4430 if (rval != QLA_SUCCESS) { 4431 ql_dbg(ql_dbg_mbx, vha, 0x10f5, 4432 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4433 } else { 4434 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6, 4435 "Done %s.\n", __func__); 4436 *data = mcp->mb[3] << 16 | mcp->mb[2]; 4437 } 4438 4439 return rval; 4440 } 4441 4442 int 4443 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4444 uint16_t *mresp) 4445 { 4446 int rval; 4447 mbx_cmd_t mc; 4448 mbx_cmd_t *mcp = &mc; 4449 4450 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7, 4451 "Entered %s.\n", __func__); 4452 4453 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4454 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK; 4455 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing 4456 4457 /* transfer count */ 4458 mcp->mb[10] = LSW(mreq->transfer_size); 4459 mcp->mb[11] = MSW(mreq->transfer_size); 4460 4461 /* send data address */ 4462 mcp->mb[14] = LSW(mreq->send_dma); 4463 mcp->mb[15] = MSW(mreq->send_dma); 4464 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4465 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4466 4467 /* receive data address */ 4468 mcp->mb[16] = LSW(mreq->rcv_dma); 4469 mcp->mb[17] = MSW(mreq->rcv_dma); 4470 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4471 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4472 4473 /* Iteration count */ 4474 mcp->mb[18] = LSW(mreq->iteration_count); 4475 mcp->mb[19] = MSW(mreq->iteration_count); 4476 4477 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| 4478 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4479 if (IS_CNA_CAPABLE(vha->hw)) 4480 mcp->out_mb |= MBX_2; 4481 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; 4482 4483 mcp->buf_size = mreq->transfer_size; 4484 mcp->tov = MBX_TOV_SECONDS; 4485 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4486 4487 rval = qla2x00_mailbox_command(vha, mcp); 4488 4489 if (rval != QLA_SUCCESS) { 4490 ql_dbg(ql_dbg_mbx, vha, 0x10f8, 4491 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x " 4492 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], 4493 mcp->mb[3], mcp->mb[18], mcp->mb[19]); 4494 } else { 4495 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9, 4496 "Done %s.\n", __func__); 4497 } 4498 4499 /* Copy mailbox information */ 4500 memcpy( mresp, mcp->mb, 64); 4501 return rval; 4502 } 4503 4504 int 4505 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 4506 uint16_t *mresp) 4507 { 4508 int rval; 4509 mbx_cmd_t mc; 4510 mbx_cmd_t *mcp = &mc; 4511 struct qla_hw_data *ha = vha->hw; 4512 4513 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa, 4514 "Entered %s.\n", __func__); 4515 4516 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4517 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; 4518 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */ 4519 if (IS_CNA_CAPABLE(ha)) { 4520 mcp->mb[1] |= BIT_15; 4521 mcp->mb[2] = vha->fcoe_fcf_idx; 4522 } 4523 mcp->mb[16] = LSW(mreq->rcv_dma); 4524 mcp->mb[17] = MSW(mreq->rcv_dma); 4525 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 4526 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 4527 4528 mcp->mb[10] = LSW(mreq->transfer_size); 4529 4530 mcp->mb[14] = LSW(mreq->send_dma); 4531 mcp->mb[15] = MSW(mreq->send_dma); 4532 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 4533 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 4534 4535 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| 4536 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 4537 if (IS_CNA_CAPABLE(ha)) 4538 mcp->out_mb |= MBX_2; 4539 4540 mcp->in_mb = MBX_0; 4541 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || 4542 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4543 mcp->in_mb |= MBX_1; 4544 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 4545 mcp->in_mb |= MBX_3; 4546 4547 mcp->tov = MBX_TOV_SECONDS; 4548 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4549 mcp->buf_size = mreq->transfer_size; 4550 4551 rval = qla2x00_mailbox_command(vha, mcp); 4552 4553 if (rval != QLA_SUCCESS) { 4554 ql_dbg(ql_dbg_mbx, vha, 0x10fb, 4555 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4556 rval, mcp->mb[0], mcp->mb[1]); 4557 } else { 4558 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc, 4559 "Done %s.\n", __func__); 4560 } 4561 4562 /* Copy mailbox information */ 4563 memcpy(mresp, mcp->mb, 64); 4564 return rval; 4565 } 4566 4567 int 4568 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic) 4569 { 4570 int rval; 4571 mbx_cmd_t mc; 4572 mbx_cmd_t *mcp = &mc; 4573 4574 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd, 4575 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic); 4576 4577 mcp->mb[0] = MBC_ISP84XX_RESET; 4578 mcp->mb[1] = enable_diagnostic; 4579 mcp->out_mb = MBX_1|MBX_0; 4580 mcp->in_mb = MBX_1|MBX_0; 4581 mcp->tov = MBX_TOV_SECONDS; 4582 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4583 rval = qla2x00_mailbox_command(vha, mcp); 4584 4585 if (rval != QLA_SUCCESS) 4586 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval); 4587 else 4588 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff, 4589 "Done %s.\n", __func__); 4590 4591 return rval; 4592 } 4593 4594 int 4595 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data) 4596 { 4597 int rval; 4598 mbx_cmd_t mc; 4599 mbx_cmd_t *mcp = &mc; 4600 4601 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100, 4602 "Entered %s.\n", __func__); 4603 4604 if (!IS_FWI2_CAPABLE(vha->hw)) 4605 return QLA_FUNCTION_FAILED; 4606 4607 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED; 4608 mcp->mb[1] = LSW(risc_addr); 4609 mcp->mb[2] = LSW(data); 4610 mcp->mb[3] = MSW(data); 4611 mcp->mb[8] = MSW(risc_addr); 4612 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0; 4613 mcp->in_mb = MBX_0; 4614 mcp->tov = 30; 4615 mcp->flags = 0; 4616 rval = qla2x00_mailbox_command(vha, mcp); 4617 if (rval != QLA_SUCCESS) { 4618 ql_dbg(ql_dbg_mbx, vha, 0x1101, 4619 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4620 } else { 4621 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102, 4622 "Done %s.\n", __func__); 4623 } 4624 4625 return rval; 4626 } 4627 4628 int 4629 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb) 4630 { 4631 int rval; 4632 uint32_t stat, timer; 4633 uint16_t mb0 = 0; 4634 struct qla_hw_data *ha = vha->hw; 4635 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 4636 4637 rval = QLA_SUCCESS; 4638 4639 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103, 4640 "Entered %s.\n", __func__); 4641 4642 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 4643 4644 /* Write the MBC data to the registers */ 4645 WRT_REG_WORD(®->mailbox0, MBC_WRITE_MPI_REGISTER); 4646 WRT_REG_WORD(®->mailbox1, mb[0]); 4647 WRT_REG_WORD(®->mailbox2, mb[1]); 4648 WRT_REG_WORD(®->mailbox3, mb[2]); 4649 WRT_REG_WORD(®->mailbox4, mb[3]); 4650 4651 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 4652 4653 /* Poll for MBC interrupt */ 4654 for (timer = 6000000; timer; timer--) { 4655 /* Check for pending interrupts. */ 4656 stat = RD_REG_DWORD(®->host_status); 4657 if (stat & HSRX_RISC_INT) { 4658 stat &= 0xff; 4659 4660 if (stat == 0x1 || stat == 0x2 || 4661 stat == 0x10 || stat == 0x11) { 4662 set_bit(MBX_INTERRUPT, 4663 &ha->mbx_cmd_flags); 4664 mb0 = RD_REG_WORD(®->mailbox0); 4665 WRT_REG_DWORD(®->hccr, 4666 HCCRX_CLR_RISC_INT); 4667 RD_REG_DWORD(®->hccr); 4668 break; 4669 } 4670 } 4671 udelay(5); 4672 } 4673 4674 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) 4675 rval = mb0 & MBS_MASK; 4676 else 4677 rval = QLA_FUNCTION_FAILED; 4678 4679 if (rval != QLA_SUCCESS) { 4680 ql_dbg(ql_dbg_mbx, vha, 0x1104, 4681 "Failed=%x mb[0]=%x.\n", rval, mb[0]); 4682 } else { 4683 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105, 4684 "Done %s.\n", __func__); 4685 } 4686 4687 return rval; 4688 } 4689 4690 int 4691 qla2x00_get_data_rate(scsi_qla_host_t *vha) 4692 { 4693 int rval; 4694 mbx_cmd_t mc; 4695 mbx_cmd_t *mcp = &mc; 4696 struct qla_hw_data *ha = vha->hw; 4697 4698 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106, 4699 "Entered %s.\n", __func__); 4700 4701 if (!IS_FWI2_CAPABLE(ha)) 4702 return QLA_FUNCTION_FAILED; 4703 4704 mcp->mb[0] = MBC_DATA_RATE; 4705 mcp->mb[1] = 0; 4706 mcp->out_mb = MBX_1|MBX_0; 4707 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4708 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4709 mcp->in_mb |= MBX_3; 4710 mcp->tov = MBX_TOV_SECONDS; 4711 mcp->flags = 0; 4712 rval = qla2x00_mailbox_command(vha, mcp); 4713 if (rval != QLA_SUCCESS) { 4714 ql_dbg(ql_dbg_mbx, vha, 0x1107, 4715 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4716 } else { 4717 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108, 4718 "Done %s.\n", __func__); 4719 if (mcp->mb[1] != 0x7) 4720 ha->link_data_rate = mcp->mb[1]; 4721 } 4722 4723 return rval; 4724 } 4725 4726 int 4727 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb) 4728 { 4729 int rval; 4730 mbx_cmd_t mc; 4731 mbx_cmd_t *mcp = &mc; 4732 struct qla_hw_data *ha = vha->hw; 4733 4734 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109, 4735 "Entered %s.\n", __func__); 4736 4737 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) && 4738 !IS_QLA27XX(ha)) 4739 return QLA_FUNCTION_FAILED; 4740 mcp->mb[0] = MBC_GET_PORT_CONFIG; 4741 mcp->out_mb = MBX_0; 4742 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4743 mcp->tov = MBX_TOV_SECONDS; 4744 mcp->flags = 0; 4745 4746 rval = qla2x00_mailbox_command(vha, mcp); 4747 4748 if (rval != QLA_SUCCESS) { 4749 ql_dbg(ql_dbg_mbx, vha, 0x110a, 4750 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4751 } else { 4752 /* Copy all bits to preserve original value */ 4753 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4); 4754 4755 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b, 4756 "Done %s.\n", __func__); 4757 } 4758 return rval; 4759 } 4760 4761 int 4762 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb) 4763 { 4764 int rval; 4765 mbx_cmd_t mc; 4766 mbx_cmd_t *mcp = &mc; 4767 4768 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c, 4769 "Entered %s.\n", __func__); 4770 4771 mcp->mb[0] = MBC_SET_PORT_CONFIG; 4772 /* Copy all bits to preserve original setting */ 4773 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4); 4774 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4775 mcp->in_mb = MBX_0; 4776 mcp->tov = MBX_TOV_SECONDS; 4777 mcp->flags = 0; 4778 rval = qla2x00_mailbox_command(vha, mcp); 4779 4780 if (rval != QLA_SUCCESS) { 4781 ql_dbg(ql_dbg_mbx, vha, 0x110d, 4782 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4783 } else 4784 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e, 4785 "Done %s.\n", __func__); 4786 4787 return rval; 4788 } 4789 4790 4791 int 4792 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority, 4793 uint16_t *mb) 4794 { 4795 int rval; 4796 mbx_cmd_t mc; 4797 mbx_cmd_t *mcp = &mc; 4798 struct qla_hw_data *ha = vha->hw; 4799 4800 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f, 4801 "Entered %s.\n", __func__); 4802 4803 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 4804 return QLA_FUNCTION_FAILED; 4805 4806 mcp->mb[0] = MBC_PORT_PARAMS; 4807 mcp->mb[1] = loop_id; 4808 if (ha->flags.fcp_prio_enabled) 4809 mcp->mb[2] = BIT_1; 4810 else 4811 mcp->mb[2] = BIT_2; 4812 mcp->mb[4] = priority & 0xf; 4813 mcp->mb[9] = vha->vp_idx; 4814 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4815 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 4816 mcp->tov = 30; 4817 mcp->flags = 0; 4818 rval = qla2x00_mailbox_command(vha, mcp); 4819 if (mb != NULL) { 4820 mb[0] = mcp->mb[0]; 4821 mb[1] = mcp->mb[1]; 4822 mb[3] = mcp->mb[3]; 4823 mb[4] = mcp->mb[4]; 4824 } 4825 4826 if (rval != QLA_SUCCESS) { 4827 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval); 4828 } else { 4829 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc, 4830 "Done %s.\n", __func__); 4831 } 4832 4833 return rval; 4834 } 4835 4836 int 4837 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp) 4838 { 4839 int rval = QLA_FUNCTION_FAILED; 4840 struct qla_hw_data *ha = vha->hw; 4841 uint8_t byte; 4842 4843 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) { 4844 ql_dbg(ql_dbg_mbx, vha, 0x1150, 4845 "Thermal not supported by this card.\n"); 4846 return rval; 4847 } 4848 4849 if (IS_QLA25XX(ha)) { 4850 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 4851 ha->pdev->subsystem_device == 0x0175) { 4852 rval = qla2x00_read_sfp(vha, 0, &byte, 4853 0x98, 0x1, 1, BIT_13|BIT_0); 4854 *temp = byte; 4855 return rval; 4856 } 4857 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 4858 ha->pdev->subsystem_device == 0x338e) { 4859 rval = qla2x00_read_sfp(vha, 0, &byte, 4860 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0); 4861 *temp = byte; 4862 return rval; 4863 } 4864 ql_dbg(ql_dbg_mbx, vha, 0x10c9, 4865 "Thermal not supported by this card.\n"); 4866 return rval; 4867 } 4868 4869 if (IS_QLA82XX(ha)) { 4870 *temp = qla82xx_read_temperature(vha); 4871 rval = QLA_SUCCESS; 4872 return rval; 4873 } else if (IS_QLA8044(ha)) { 4874 *temp = qla8044_read_temperature(vha); 4875 rval = QLA_SUCCESS; 4876 return rval; 4877 } 4878 4879 rval = qla2x00_read_asic_temperature(vha, temp); 4880 return rval; 4881 } 4882 4883 int 4884 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha) 4885 { 4886 int rval; 4887 struct qla_hw_data *ha = vha->hw; 4888 mbx_cmd_t mc; 4889 mbx_cmd_t *mcp = &mc; 4890 4891 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017, 4892 "Entered %s.\n", __func__); 4893 4894 if (!IS_FWI2_CAPABLE(ha)) 4895 return QLA_FUNCTION_FAILED; 4896 4897 memset(mcp, 0, sizeof(mbx_cmd_t)); 4898 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 4899 mcp->mb[1] = 1; 4900 4901 mcp->out_mb = MBX_1|MBX_0; 4902 mcp->in_mb = MBX_0; 4903 mcp->tov = 30; 4904 mcp->flags = 0; 4905 4906 rval = qla2x00_mailbox_command(vha, mcp); 4907 if (rval != QLA_SUCCESS) { 4908 ql_dbg(ql_dbg_mbx, vha, 0x1016, 4909 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4910 } else { 4911 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e, 4912 "Done %s.\n", __func__); 4913 } 4914 4915 return rval; 4916 } 4917 4918 int 4919 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha) 4920 { 4921 int rval; 4922 struct qla_hw_data *ha = vha->hw; 4923 mbx_cmd_t mc; 4924 mbx_cmd_t *mcp = &mc; 4925 4926 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d, 4927 "Entered %s.\n", __func__); 4928 4929 if (!IS_P3P_TYPE(ha)) 4930 return QLA_FUNCTION_FAILED; 4931 4932 memset(mcp, 0, sizeof(mbx_cmd_t)); 4933 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 4934 mcp->mb[1] = 0; 4935 4936 mcp->out_mb = MBX_1|MBX_0; 4937 mcp->in_mb = MBX_0; 4938 mcp->tov = 30; 4939 mcp->flags = 0; 4940 4941 rval = qla2x00_mailbox_command(vha, mcp); 4942 if (rval != QLA_SUCCESS) { 4943 ql_dbg(ql_dbg_mbx, vha, 0x100c, 4944 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4945 } else { 4946 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b, 4947 "Done %s.\n", __func__); 4948 } 4949 4950 return rval; 4951 } 4952 4953 int 4954 qla82xx_md_get_template_size(scsi_qla_host_t *vha) 4955 { 4956 struct qla_hw_data *ha = vha->hw; 4957 mbx_cmd_t mc; 4958 mbx_cmd_t *mcp = &mc; 4959 int rval = QLA_FUNCTION_FAILED; 4960 4961 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f, 4962 "Entered %s.\n", __func__); 4963 4964 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4965 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4966 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4967 mcp->mb[2] = LSW(RQST_TMPLT_SIZE); 4968 mcp->mb[3] = MSW(RQST_TMPLT_SIZE); 4969 4970 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 4971 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| 4972 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4973 4974 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4975 mcp->tov = MBX_TOV_SECONDS; 4976 rval = qla2x00_mailbox_command(vha, mcp); 4977 4978 /* Always copy back return mailbox values. */ 4979 if (rval != QLA_SUCCESS) { 4980 ql_dbg(ql_dbg_mbx, vha, 0x1120, 4981 "mailbox command FAILED=0x%x, subcode=%x.\n", 4982 (mcp->mb[1] << 16) | mcp->mb[0], 4983 (mcp->mb[3] << 16) | mcp->mb[2]); 4984 } else { 4985 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121, 4986 "Done %s.\n", __func__); 4987 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]); 4988 if (!ha->md_template_size) { 4989 ql_dbg(ql_dbg_mbx, vha, 0x1122, 4990 "Null template size obtained.\n"); 4991 rval = QLA_FUNCTION_FAILED; 4992 } 4993 } 4994 return rval; 4995 } 4996 4997 int 4998 qla82xx_md_get_template(scsi_qla_host_t *vha) 4999 { 5000 struct qla_hw_data *ha = vha->hw; 5001 mbx_cmd_t mc; 5002 mbx_cmd_t *mcp = &mc; 5003 int rval = QLA_FUNCTION_FAILED; 5004 5005 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123, 5006 "Entered %s.\n", __func__); 5007 5008 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5009 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5010 if (!ha->md_tmplt_hdr) { 5011 ql_log(ql_log_warn, vha, 0x1124, 5012 "Unable to allocate memory for Minidump template.\n"); 5013 return rval; 5014 } 5015 5016 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5017 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5018 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5019 mcp->mb[2] = LSW(RQST_TMPLT); 5020 mcp->mb[3] = MSW(RQST_TMPLT); 5021 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma)); 5022 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma)); 5023 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma)); 5024 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma)); 5025 mcp->mb[8] = LSW(ha->md_template_size); 5026 mcp->mb[9] = MSW(ha->md_template_size); 5027 5028 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5029 mcp->tov = MBX_TOV_SECONDS; 5030 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5031 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5032 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5033 rval = qla2x00_mailbox_command(vha, mcp); 5034 5035 if (rval != QLA_SUCCESS) { 5036 ql_dbg(ql_dbg_mbx, vha, 0x1125, 5037 "mailbox command FAILED=0x%x, subcode=%x.\n", 5038 ((mcp->mb[1] << 16) | mcp->mb[0]), 5039 ((mcp->mb[3] << 16) | mcp->mb[2])); 5040 } else 5041 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126, 5042 "Done %s.\n", __func__); 5043 return rval; 5044 } 5045 5046 int 5047 qla8044_md_get_template(scsi_qla_host_t *vha) 5048 { 5049 struct qla_hw_data *ha = vha->hw; 5050 mbx_cmd_t mc; 5051 mbx_cmd_t *mcp = &mc; 5052 int rval = QLA_FUNCTION_FAILED; 5053 int offset = 0, size = MINIDUMP_SIZE_36K; 5054 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f, 5055 "Entered %s.\n", __func__); 5056 5057 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5058 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5059 if (!ha->md_tmplt_hdr) { 5060 ql_log(ql_log_warn, vha, 0xb11b, 5061 "Unable to allocate memory for Minidump template.\n"); 5062 return rval; 5063 } 5064 5065 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5066 while (offset < ha->md_template_size) { 5067 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5068 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5069 mcp->mb[2] = LSW(RQST_TMPLT); 5070 mcp->mb[3] = MSW(RQST_TMPLT); 5071 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5072 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5073 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5074 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5075 mcp->mb[8] = LSW(size); 5076 mcp->mb[9] = MSW(size); 5077 mcp->mb[10] = offset & 0x0000FFFF; 5078 mcp->mb[11] = offset & 0xFFFF0000; 5079 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5080 mcp->tov = MBX_TOV_SECONDS; 5081 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5082 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5083 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5084 rval = qla2x00_mailbox_command(vha, mcp); 5085 5086 if (rval != QLA_SUCCESS) { 5087 ql_dbg(ql_dbg_mbx, vha, 0xb11c, 5088 "mailbox command FAILED=0x%x, subcode=%x.\n", 5089 ((mcp->mb[1] << 16) | mcp->mb[0]), 5090 ((mcp->mb[3] << 16) | mcp->mb[2])); 5091 return rval; 5092 } else 5093 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d, 5094 "Done %s.\n", __func__); 5095 offset = offset + size; 5096 } 5097 return rval; 5098 } 5099 5100 int 5101 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5102 { 5103 int rval; 5104 struct qla_hw_data *ha = vha->hw; 5105 mbx_cmd_t mc; 5106 mbx_cmd_t *mcp = &mc; 5107 5108 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5109 return QLA_FUNCTION_FAILED; 5110 5111 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133, 5112 "Entered %s.\n", __func__); 5113 5114 memset(mcp, 0, sizeof(mbx_cmd_t)); 5115 mcp->mb[0] = MBC_SET_LED_CONFIG; 5116 mcp->mb[1] = led_cfg[0]; 5117 mcp->mb[2] = led_cfg[1]; 5118 if (IS_QLA8031(ha)) { 5119 mcp->mb[3] = led_cfg[2]; 5120 mcp->mb[4] = led_cfg[3]; 5121 mcp->mb[5] = led_cfg[4]; 5122 mcp->mb[6] = led_cfg[5]; 5123 } 5124 5125 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5126 if (IS_QLA8031(ha)) 5127 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5128 mcp->in_mb = MBX_0; 5129 mcp->tov = 30; 5130 mcp->flags = 0; 5131 5132 rval = qla2x00_mailbox_command(vha, mcp); 5133 if (rval != QLA_SUCCESS) { 5134 ql_dbg(ql_dbg_mbx, vha, 0x1134, 5135 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5136 } else { 5137 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135, 5138 "Done %s.\n", __func__); 5139 } 5140 5141 return rval; 5142 } 5143 5144 int 5145 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5146 { 5147 int rval; 5148 struct qla_hw_data *ha = vha->hw; 5149 mbx_cmd_t mc; 5150 mbx_cmd_t *mcp = &mc; 5151 5152 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5153 return QLA_FUNCTION_FAILED; 5154 5155 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136, 5156 "Entered %s.\n", __func__); 5157 5158 memset(mcp, 0, sizeof(mbx_cmd_t)); 5159 mcp->mb[0] = MBC_GET_LED_CONFIG; 5160 5161 mcp->out_mb = MBX_0; 5162 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5163 if (IS_QLA8031(ha)) 5164 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 5165 mcp->tov = 30; 5166 mcp->flags = 0; 5167 5168 rval = qla2x00_mailbox_command(vha, mcp); 5169 if (rval != QLA_SUCCESS) { 5170 ql_dbg(ql_dbg_mbx, vha, 0x1137, 5171 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5172 } else { 5173 led_cfg[0] = mcp->mb[1]; 5174 led_cfg[1] = mcp->mb[2]; 5175 if (IS_QLA8031(ha)) { 5176 led_cfg[2] = mcp->mb[3]; 5177 led_cfg[3] = mcp->mb[4]; 5178 led_cfg[4] = mcp->mb[5]; 5179 led_cfg[5] = mcp->mb[6]; 5180 } 5181 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138, 5182 "Done %s.\n", __func__); 5183 } 5184 5185 return rval; 5186 } 5187 5188 int 5189 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable) 5190 { 5191 int rval; 5192 struct qla_hw_data *ha = vha->hw; 5193 mbx_cmd_t mc; 5194 mbx_cmd_t *mcp = &mc; 5195 5196 if (!IS_P3P_TYPE(ha)) 5197 return QLA_FUNCTION_FAILED; 5198 5199 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127, 5200 "Entered %s.\n", __func__); 5201 5202 memset(mcp, 0, sizeof(mbx_cmd_t)); 5203 mcp->mb[0] = MBC_SET_LED_CONFIG; 5204 if (enable) 5205 mcp->mb[7] = 0xE; 5206 else 5207 mcp->mb[7] = 0xD; 5208 5209 mcp->out_mb = MBX_7|MBX_0; 5210 mcp->in_mb = MBX_0; 5211 mcp->tov = MBX_TOV_SECONDS; 5212 mcp->flags = 0; 5213 5214 rval = qla2x00_mailbox_command(vha, mcp); 5215 if (rval != QLA_SUCCESS) { 5216 ql_dbg(ql_dbg_mbx, vha, 0x1128, 5217 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5218 } else { 5219 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129, 5220 "Done %s.\n", __func__); 5221 } 5222 5223 return rval; 5224 } 5225 5226 int 5227 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data) 5228 { 5229 int rval; 5230 struct qla_hw_data *ha = vha->hw; 5231 mbx_cmd_t mc; 5232 mbx_cmd_t *mcp = &mc; 5233 5234 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5235 return QLA_FUNCTION_FAILED; 5236 5237 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130, 5238 "Entered %s.\n", __func__); 5239 5240 mcp->mb[0] = MBC_WRITE_REMOTE_REG; 5241 mcp->mb[1] = LSW(reg); 5242 mcp->mb[2] = MSW(reg); 5243 mcp->mb[3] = LSW(data); 5244 mcp->mb[4] = MSW(data); 5245 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5246 5247 mcp->in_mb = MBX_1|MBX_0; 5248 mcp->tov = MBX_TOV_SECONDS; 5249 mcp->flags = 0; 5250 rval = qla2x00_mailbox_command(vha, mcp); 5251 5252 if (rval != QLA_SUCCESS) { 5253 ql_dbg(ql_dbg_mbx, vha, 0x1131, 5254 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5255 } else { 5256 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132, 5257 "Done %s.\n", __func__); 5258 } 5259 5260 return rval; 5261 } 5262 5263 int 5264 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport) 5265 { 5266 int rval; 5267 struct qla_hw_data *ha = vha->hw; 5268 mbx_cmd_t mc; 5269 mbx_cmd_t *mcp = &mc; 5270 5271 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 5272 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b, 5273 "Implicit LOGO Unsupported.\n"); 5274 return QLA_FUNCTION_FAILED; 5275 } 5276 5277 5278 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c, 5279 "Entering %s.\n", __func__); 5280 5281 /* Perform Implicit LOGO. */ 5282 mcp->mb[0] = MBC_PORT_LOGOUT; 5283 mcp->mb[1] = fcport->loop_id; 5284 mcp->mb[10] = BIT_15; 5285 mcp->out_mb = MBX_10|MBX_1|MBX_0; 5286 mcp->in_mb = MBX_0; 5287 mcp->tov = MBX_TOV_SECONDS; 5288 mcp->flags = 0; 5289 rval = qla2x00_mailbox_command(vha, mcp); 5290 if (rval != QLA_SUCCESS) 5291 ql_dbg(ql_dbg_mbx, vha, 0x113d, 5292 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5293 else 5294 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e, 5295 "Done %s.\n", __func__); 5296 5297 return rval; 5298 } 5299 5300 int 5301 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data) 5302 { 5303 int rval; 5304 mbx_cmd_t mc; 5305 mbx_cmd_t *mcp = &mc; 5306 struct qla_hw_data *ha = vha->hw; 5307 unsigned long retry_max_time = jiffies + (2 * HZ); 5308 5309 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5310 return QLA_FUNCTION_FAILED; 5311 5312 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__); 5313 5314 retry_rd_reg: 5315 mcp->mb[0] = MBC_READ_REMOTE_REG; 5316 mcp->mb[1] = LSW(reg); 5317 mcp->mb[2] = MSW(reg); 5318 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5319 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5320 mcp->tov = MBX_TOV_SECONDS; 5321 mcp->flags = 0; 5322 rval = qla2x00_mailbox_command(vha, mcp); 5323 5324 if (rval != QLA_SUCCESS) { 5325 ql_dbg(ql_dbg_mbx, vha, 0x114c, 5326 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5327 rval, mcp->mb[0], mcp->mb[1]); 5328 } else { 5329 *data = (mcp->mb[3] | (mcp->mb[4] << 16)); 5330 if (*data == QLA8XXX_BAD_VALUE) { 5331 /* 5332 * During soft-reset CAMRAM register reads might 5333 * return 0xbad0bad0. So retry for MAX of 2 sec 5334 * while reading camram registers. 5335 */ 5336 if (time_after(jiffies, retry_max_time)) { 5337 ql_dbg(ql_dbg_mbx, vha, 0x1141, 5338 "Failure to read CAMRAM register. " 5339 "data=0x%x.\n", *data); 5340 return QLA_FUNCTION_FAILED; 5341 } 5342 msleep(100); 5343 goto retry_rd_reg; 5344 } 5345 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__); 5346 } 5347 5348 return rval; 5349 } 5350 5351 int 5352 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha) 5353 { 5354 int rval; 5355 mbx_cmd_t mc; 5356 mbx_cmd_t *mcp = &mc; 5357 struct qla_hw_data *ha = vha->hw; 5358 5359 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 5360 return QLA_FUNCTION_FAILED; 5361 5362 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__); 5363 5364 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE; 5365 mcp->out_mb = MBX_0; 5366 mcp->in_mb = MBX_1|MBX_0; 5367 mcp->tov = MBX_TOV_SECONDS; 5368 mcp->flags = 0; 5369 rval = qla2x00_mailbox_command(vha, mcp); 5370 5371 if (rval != QLA_SUCCESS) { 5372 ql_dbg(ql_dbg_mbx, vha, 0x1144, 5373 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5374 rval, mcp->mb[0], mcp->mb[1]); 5375 ha->isp_ops->fw_dump(vha, 0); 5376 } else { 5377 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__); 5378 } 5379 5380 return rval; 5381 } 5382 5383 int 5384 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options, 5385 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size) 5386 { 5387 int rval; 5388 mbx_cmd_t mc; 5389 mbx_cmd_t *mcp = &mc; 5390 uint8_t subcode = (uint8_t)options; 5391 struct qla_hw_data *ha = vha->hw; 5392 5393 if (!IS_QLA8031(ha)) 5394 return QLA_FUNCTION_FAILED; 5395 5396 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__); 5397 5398 mcp->mb[0] = MBC_SET_ACCESS_CONTROL; 5399 mcp->mb[1] = options; 5400 mcp->out_mb = MBX_1|MBX_0; 5401 if (subcode & BIT_2) { 5402 mcp->mb[2] = LSW(start_addr); 5403 mcp->mb[3] = MSW(start_addr); 5404 mcp->mb[4] = LSW(end_addr); 5405 mcp->mb[5] = MSW(end_addr); 5406 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2; 5407 } 5408 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5409 if (!(subcode & (BIT_2 | BIT_5))) 5410 mcp->in_mb |= MBX_4|MBX_3; 5411 mcp->tov = MBX_TOV_SECONDS; 5412 mcp->flags = 0; 5413 rval = qla2x00_mailbox_command(vha, mcp); 5414 5415 if (rval != QLA_SUCCESS) { 5416 ql_dbg(ql_dbg_mbx, vha, 0x1147, 5417 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n", 5418 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], 5419 mcp->mb[4]); 5420 ha->isp_ops->fw_dump(vha, 0); 5421 } else { 5422 if (subcode & BIT_5) 5423 *sector_size = mcp->mb[1]; 5424 else if (subcode & (BIT_6 | BIT_7)) { 5425 ql_dbg(ql_dbg_mbx, vha, 0x1148, 5426 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5427 } else if (subcode & (BIT_3 | BIT_4)) { 5428 ql_dbg(ql_dbg_mbx, vha, 0x1149, 5429 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 5430 } 5431 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__); 5432 } 5433 5434 return rval; 5435 } 5436 5437 int 5438 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 5439 uint32_t size) 5440 { 5441 int rval; 5442 mbx_cmd_t mc; 5443 mbx_cmd_t *mcp = &mc; 5444 5445 if (!IS_MCTP_CAPABLE(vha->hw)) 5446 return QLA_FUNCTION_FAILED; 5447 5448 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f, 5449 "Entered %s.\n", __func__); 5450 5451 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 5452 mcp->mb[1] = LSW(addr); 5453 mcp->mb[2] = MSW(req_dma); 5454 mcp->mb[3] = LSW(req_dma); 5455 mcp->mb[4] = MSW(size); 5456 mcp->mb[5] = LSW(size); 5457 mcp->mb[6] = MSW(MSD(req_dma)); 5458 mcp->mb[7] = LSW(MSD(req_dma)); 5459 mcp->mb[8] = MSW(addr); 5460 /* Setting RAM ID to valid */ 5461 mcp->mb[10] |= BIT_7; 5462 /* For MCTP RAM ID is 0x40 */ 5463 mcp->mb[10] |= 0x40; 5464 5465 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1| 5466 MBX_0; 5467 5468 mcp->in_mb = MBX_0; 5469 mcp->tov = MBX_TOV_SECONDS; 5470 mcp->flags = 0; 5471 rval = qla2x00_mailbox_command(vha, mcp); 5472 5473 if (rval != QLA_SUCCESS) { 5474 ql_dbg(ql_dbg_mbx, vha, 0x114e, 5475 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5476 } else { 5477 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d, 5478 "Done %s.\n", __func__); 5479 } 5480 5481 return rval; 5482 } 5483