1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2011 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/delay.h> 10 #include <linux/gfp.h> 11 12 13 /* 14 * qla2x00_mailbox_command 15 * Issue mailbox command and waits for completion. 16 * 17 * Input: 18 * ha = adapter block pointer. 19 * mcp = driver internal mbx struct pointer. 20 * 21 * Output: 22 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data. 23 * 24 * Returns: 25 * 0 : QLA_SUCCESS = cmd performed success 26 * 1 : QLA_FUNCTION_FAILED (error encountered) 27 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered) 28 * 29 * Context: 30 * Kernel context. 31 */ 32 static int 33 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) 34 { 35 int rval; 36 unsigned long flags = 0; 37 device_reg_t __iomem *reg; 38 uint8_t abort_active; 39 uint8_t io_lock_on; 40 uint16_t command = 0; 41 uint16_t *iptr; 42 uint16_t __iomem *optr; 43 uint32_t cnt; 44 uint32_t mboxes; 45 unsigned long wait_time; 46 struct qla_hw_data *ha = vha->hw; 47 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 48 49 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__); 50 51 if (ha->pdev->error_state > pci_channel_io_frozen) { 52 ql_log(ql_log_warn, vha, 0x1001, 53 "error_state is greater than pci_channel_io_frozen, " 54 "exiting.\n"); 55 return QLA_FUNCTION_TIMEOUT; 56 } 57 58 if (vha->device_flags & DFLG_DEV_FAILED) { 59 ql_log(ql_log_warn, vha, 0x1002, 60 "Device in failed state, exiting.\n"); 61 return QLA_FUNCTION_TIMEOUT; 62 } 63 64 reg = ha->iobase; 65 io_lock_on = base_vha->flags.init_done; 66 67 rval = QLA_SUCCESS; 68 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 69 70 71 if (ha->flags.pci_channel_io_perm_failure) { 72 ql_log(ql_log_warn, vha, 0x1003, 73 "Perm failure on EEH timeout MBX, exiting.\n"); 74 return QLA_FUNCTION_TIMEOUT; 75 } 76 77 if (ha->flags.isp82xx_fw_hung) { 78 /* Setting Link-Down error */ 79 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 80 ql_log(ql_log_warn, vha, 0x1004, 81 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 82 return QLA_FUNCTION_TIMEOUT; 83 } 84 85 /* 86 * Wait for active mailbox commands to finish by waiting at most tov 87 * seconds. This is to serialize actual issuing of mailbox cmds during 88 * non ISP abort time. 89 */ 90 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) { 91 /* Timeout occurred. Return error. */ 92 ql_log(ql_log_warn, vha, 0x1005, 93 "Cmd access timeout, cmd=0x%x, Exiting.\n", 94 mcp->mb[0]); 95 return QLA_FUNCTION_TIMEOUT; 96 } 97 98 ha->flags.mbox_busy = 1; 99 /* Save mailbox command for debug */ 100 ha->mcp = mcp; 101 102 ql_dbg(ql_dbg_mbx, vha, 0x1006, 103 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); 104 105 spin_lock_irqsave(&ha->hardware_lock, flags); 106 107 /* Load mailbox registers. */ 108 if (IS_QLA82XX(ha)) 109 optr = (uint16_t __iomem *)®->isp82.mailbox_in[0]; 110 else if (IS_FWI2_CAPABLE(ha) && !IS_QLA82XX(ha)) 111 optr = (uint16_t __iomem *)®->isp24.mailbox0; 112 else 113 optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); 114 115 iptr = mcp->mb; 116 command = mcp->mb[0]; 117 mboxes = mcp->out_mb; 118 119 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 120 if (IS_QLA2200(ha) && cnt == 8) 121 optr = 122 (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 8); 123 if (mboxes & BIT_0) 124 WRT_REG_WORD(optr, *iptr); 125 126 mboxes >>= 1; 127 optr++; 128 iptr++; 129 } 130 131 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111, 132 "Loaded MBX registers (displayed in bytes) =.\n"); 133 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1112, 134 (uint8_t *)mcp->mb, 16); 135 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1113, 136 ".\n"); 137 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1114, 138 ((uint8_t *)mcp->mb + 0x10), 16); 139 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1115, 140 ".\n"); 141 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1116, 142 ((uint8_t *)mcp->mb + 0x20), 8); 143 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117, 144 "I/O Address = %p.\n", optr); 145 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x100e); 146 147 /* Issue set host interrupt command to send cmd out. */ 148 ha->flags.mbox_int = 0; 149 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 150 151 /* Unlock mbx registers and wait for interrupt */ 152 ql_dbg(ql_dbg_mbx, vha, 0x100f, 153 "Going to unlock irq & waiting for interrupts. " 154 "jiffies=%lx.\n", jiffies); 155 156 /* Wait for mbx cmd completion until timeout */ 157 158 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { 159 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 160 161 if (IS_QLA82XX(ha)) { 162 if (RD_REG_DWORD(®->isp82.hint) & 163 HINT_MBX_INT_PENDING) { 164 spin_unlock_irqrestore(&ha->hardware_lock, 165 flags); 166 ha->flags.mbox_busy = 0; 167 ql_dbg(ql_dbg_mbx, vha, 0x1010, 168 "Pending mailbox timeout, exiting.\n"); 169 rval = QLA_FUNCTION_TIMEOUT; 170 goto premature_exit; 171 } 172 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 173 } else if (IS_FWI2_CAPABLE(ha)) 174 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 175 else 176 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 177 spin_unlock_irqrestore(&ha->hardware_lock, flags); 178 179 wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ); 180 181 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 182 183 } else { 184 ql_dbg(ql_dbg_mbx, vha, 0x1011, 185 "Cmd=%x Polling Mode.\n", command); 186 187 if (IS_QLA82XX(ha)) { 188 if (RD_REG_DWORD(®->isp82.hint) & 189 HINT_MBX_INT_PENDING) { 190 spin_unlock_irqrestore(&ha->hardware_lock, 191 flags); 192 ha->flags.mbox_busy = 0; 193 ql_dbg(ql_dbg_mbx, vha, 0x1012, 194 "Pending mailbox timeout, exiting.\n"); 195 rval = QLA_FUNCTION_TIMEOUT; 196 goto premature_exit; 197 } 198 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); 199 } else if (IS_FWI2_CAPABLE(ha)) 200 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); 201 else 202 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); 203 spin_unlock_irqrestore(&ha->hardware_lock, flags); 204 205 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */ 206 while (!ha->flags.mbox_int) { 207 if (time_after(jiffies, wait_time)) 208 break; 209 210 /* Check for pending interrupts. */ 211 qla2x00_poll(ha->rsp_q_map[0]); 212 213 if (!ha->flags.mbox_int && 214 !(IS_QLA2200(ha) && 215 command == MBC_LOAD_RISC_RAM_EXTENDED)) 216 msleep(10); 217 } /* while */ 218 ql_dbg(ql_dbg_mbx, vha, 0x1013, 219 "Waited %d sec.\n", 220 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ)); 221 } 222 223 /* Check whether we timed out */ 224 if (ha->flags.mbox_int) { 225 uint16_t *iptr2; 226 227 ql_dbg(ql_dbg_mbx, vha, 0x1014, 228 "Cmd=%x completed.\n", command); 229 230 /* Got interrupt. Clear the flag. */ 231 ha->flags.mbox_int = 0; 232 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 233 234 if (ha->flags.isp82xx_fw_hung) { 235 ha->flags.mbox_busy = 0; 236 /* Setting Link-Down error */ 237 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 238 ha->mcp = NULL; 239 rval = QLA_FUNCTION_FAILED; 240 ql_log(ql_log_warn, vha, 0x1015, 241 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 242 goto premature_exit; 243 } 244 245 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) 246 rval = QLA_FUNCTION_FAILED; 247 248 /* Load return mailbox registers. */ 249 iptr2 = mcp->mb; 250 iptr = (uint16_t *)&ha->mailbox_out[0]; 251 mboxes = mcp->in_mb; 252 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 253 if (mboxes & BIT_0) 254 *iptr2 = *iptr; 255 256 mboxes >>= 1; 257 iptr2++; 258 iptr++; 259 } 260 } else { 261 262 uint16_t mb0; 263 uint32_t ictrl; 264 265 if (IS_FWI2_CAPABLE(ha)) { 266 mb0 = RD_REG_WORD(®->isp24.mailbox0); 267 ictrl = RD_REG_DWORD(®->isp24.ictrl); 268 } else { 269 mb0 = RD_MAILBOX_REG(ha, ®->isp, 0); 270 ictrl = RD_REG_WORD(®->isp.ictrl); 271 } 272 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119, 273 "MBX Command timeout for cmd %x.\n", command); 274 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111a, 275 "iocontrol=%x jiffies=%lx.\n", ictrl, jiffies); 276 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111b, 277 "mb[0] = 0x%x.\n", mb0); 278 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019); 279 280 /* 281 * Attempt to capture a firmware dump for further analysis 282 * of the current firmware state 283 */ 284 ha->isp_ops->fw_dump(vha, 0); 285 286 rval = QLA_FUNCTION_TIMEOUT; 287 } 288 289 ha->flags.mbox_busy = 0; 290 291 /* Clean up */ 292 ha->mcp = NULL; 293 294 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) { 295 ql_dbg(ql_dbg_mbx, vha, 0x101a, 296 "Checking for additional resp interrupt.\n"); 297 298 /* polling mode for non isp_abort commands. */ 299 qla2x00_poll(ha->rsp_q_map[0]); 300 } 301 302 if (rval == QLA_FUNCTION_TIMEOUT && 303 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) { 304 if (!io_lock_on || (mcp->flags & IOCTL_CMD) || 305 ha->flags.eeh_busy) { 306 /* not in dpc. schedule it for dpc to take over. */ 307 ql_dbg(ql_dbg_mbx, vha, 0x101b, 308 "Timeout, schedule isp_abort_needed.\n"); 309 310 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 311 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 312 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 313 if (IS_QLA82XX(ha)) { 314 ql_dbg(ql_dbg_mbx, vha, 0x112a, 315 "disabling pause transmit on port " 316 "0 & 1.\n"); 317 qla82xx_wr_32(ha, 318 QLA82XX_CRB_NIU + 0x98, 319 CRB_NIU_XG_PAUSE_CTL_P0| 320 CRB_NIU_XG_PAUSE_CTL_P1); 321 } 322 ql_log(ql_log_info, base_vha, 0x101c, 323 "Mailbox cmd timeout occured, cmd=0x%x, " 324 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP " 325 "abort.\n", command, mcp->mb[0], 326 ha->flags.eeh_busy); 327 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 328 qla2xxx_wake_dpc(vha); 329 } 330 } else if (!abort_active) { 331 /* call abort directly since we are in the DPC thread */ 332 ql_dbg(ql_dbg_mbx, vha, 0x101d, 333 "Timeout, calling abort_isp.\n"); 334 335 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 336 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 337 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 338 if (IS_QLA82XX(ha)) { 339 ql_dbg(ql_dbg_mbx, vha, 0x112b, 340 "disabling pause transmit on port " 341 "0 & 1.\n"); 342 qla82xx_wr_32(ha, 343 QLA82XX_CRB_NIU + 0x98, 344 CRB_NIU_XG_PAUSE_CTL_P0| 345 CRB_NIU_XG_PAUSE_CTL_P1); 346 } 347 ql_log(ql_log_info, base_vha, 0x101e, 348 "Mailbox cmd timeout occured, cmd=0x%x, " 349 "mb[0]=0x%x. Scheduling ISP abort ", 350 command, mcp->mb[0]); 351 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 352 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 353 /* Allow next mbx cmd to come in. */ 354 complete(&ha->mbx_cmd_comp); 355 if (ha->isp_ops->abort_isp(vha)) { 356 /* Failed. retry later. */ 357 set_bit(ISP_ABORT_NEEDED, 358 &vha->dpc_flags); 359 } 360 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 361 ql_dbg(ql_dbg_mbx, vha, 0x101f, 362 "Finished abort_isp.\n"); 363 goto mbx_done; 364 } 365 } 366 } 367 368 premature_exit: 369 /* Allow next mbx cmd to come in. */ 370 complete(&ha->mbx_cmd_comp); 371 372 mbx_done: 373 if (rval) { 374 ql_dbg(ql_dbg_mbx, base_vha, 0x1020, 375 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n", 376 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command); 377 } else { 378 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__); 379 } 380 381 return rval; 382 } 383 384 int 385 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr, 386 uint32_t risc_code_size) 387 { 388 int rval; 389 struct qla_hw_data *ha = vha->hw; 390 mbx_cmd_t mc; 391 mbx_cmd_t *mcp = &mc; 392 393 ql_dbg(ql_dbg_mbx, vha, 0x1022, "Entered %s.\n", __func__); 394 395 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) { 396 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; 397 mcp->mb[8] = MSW(risc_addr); 398 mcp->out_mb = MBX_8|MBX_0; 399 } else { 400 mcp->mb[0] = MBC_LOAD_RISC_RAM; 401 mcp->out_mb = MBX_0; 402 } 403 mcp->mb[1] = LSW(risc_addr); 404 mcp->mb[2] = MSW(req_dma); 405 mcp->mb[3] = LSW(req_dma); 406 mcp->mb[6] = MSW(MSD(req_dma)); 407 mcp->mb[7] = LSW(MSD(req_dma)); 408 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 409 if (IS_FWI2_CAPABLE(ha)) { 410 mcp->mb[4] = MSW(risc_code_size); 411 mcp->mb[5] = LSW(risc_code_size); 412 mcp->out_mb |= MBX_5|MBX_4; 413 } else { 414 mcp->mb[4] = LSW(risc_code_size); 415 mcp->out_mb |= MBX_4; 416 } 417 418 mcp->in_mb = MBX_0; 419 mcp->tov = MBX_TOV_SECONDS; 420 mcp->flags = 0; 421 rval = qla2x00_mailbox_command(vha, mcp); 422 423 if (rval != QLA_SUCCESS) { 424 ql_dbg(ql_dbg_mbx, vha, 0x1023, 425 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 426 } else { 427 ql_dbg(ql_dbg_mbx, vha, 0x1024, "Done %s.\n", __func__); 428 } 429 430 return rval; 431 } 432 433 #define EXTENDED_BB_CREDITS BIT_0 434 /* 435 * qla2x00_execute_fw 436 * Start adapter firmware. 437 * 438 * Input: 439 * ha = adapter block pointer. 440 * TARGET_QUEUE_LOCK must be released. 441 * ADAPTER_STATE_LOCK must be released. 442 * 443 * Returns: 444 * qla2x00 local function return status code. 445 * 446 * Context: 447 * Kernel context. 448 */ 449 int 450 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr) 451 { 452 int rval; 453 struct qla_hw_data *ha = vha->hw; 454 mbx_cmd_t mc; 455 mbx_cmd_t *mcp = &mc; 456 457 ql_dbg(ql_dbg_mbx, vha, 0x1025, "Entered %s.\n", __func__); 458 459 mcp->mb[0] = MBC_EXECUTE_FIRMWARE; 460 mcp->out_mb = MBX_0; 461 mcp->in_mb = MBX_0; 462 if (IS_FWI2_CAPABLE(ha)) { 463 mcp->mb[1] = MSW(risc_addr); 464 mcp->mb[2] = LSW(risc_addr); 465 mcp->mb[3] = 0; 466 if (IS_QLA81XX(ha) || IS_QLA83XX(ha)) { 467 struct nvram_81xx *nv = ha->nvram; 468 mcp->mb[4] = (nv->enhanced_features & 469 EXTENDED_BB_CREDITS); 470 } else 471 mcp->mb[4] = 0; 472 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1; 473 mcp->in_mb |= MBX_1; 474 } else { 475 mcp->mb[1] = LSW(risc_addr); 476 mcp->out_mb |= MBX_1; 477 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 478 mcp->mb[2] = 0; 479 mcp->out_mb |= MBX_2; 480 } 481 } 482 483 mcp->tov = MBX_TOV_SECONDS; 484 mcp->flags = 0; 485 rval = qla2x00_mailbox_command(vha, mcp); 486 487 if (rval != QLA_SUCCESS) { 488 ql_dbg(ql_dbg_mbx, vha, 0x1026, 489 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 490 } else { 491 if (IS_FWI2_CAPABLE(ha)) { 492 ql_dbg(ql_dbg_mbx, vha, 0x1027, 493 "Done exchanges=%x.\n", mcp->mb[1]); 494 } else { 495 ql_dbg(ql_dbg_mbx, vha, 0x1028, "Done %s.\n", __func__); 496 } 497 } 498 499 return rval; 500 } 501 502 /* 503 * qla2x00_get_fw_version 504 * Get firmware version. 505 * 506 * Input: 507 * ha: adapter state pointer. 508 * major: pointer for major number. 509 * minor: pointer for minor number. 510 * subminor: pointer for subminor number. 511 * 512 * Returns: 513 * qla2x00 local function return status code. 514 * 515 * Context: 516 * Kernel context. 517 */ 518 int 519 qla2x00_get_fw_version(scsi_qla_host_t *vha) 520 { 521 int rval; 522 mbx_cmd_t mc; 523 mbx_cmd_t *mcp = &mc; 524 struct qla_hw_data *ha = vha->hw; 525 526 ql_dbg(ql_dbg_mbx, vha, 0x1029, "Entered %s.\n", __func__); 527 528 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION; 529 mcp->out_mb = MBX_0; 530 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 531 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha)) 532 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8; 533 if (IS_QLA83XX(vha->hw)) 534 mcp->in_mb |= MBX_17|MBX_16|MBX_15; 535 mcp->flags = 0; 536 mcp->tov = MBX_TOV_SECONDS; 537 rval = qla2x00_mailbox_command(vha, mcp); 538 if (rval != QLA_SUCCESS) 539 goto failed; 540 541 /* Return mailbox data. */ 542 ha->fw_major_version = mcp->mb[1]; 543 ha->fw_minor_version = mcp->mb[2]; 544 ha->fw_subminor_version = mcp->mb[3]; 545 ha->fw_attributes = mcp->mb[6]; 546 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw)) 547 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */ 548 else 549 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4]; 550 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw)) { 551 ha->mpi_version[0] = mcp->mb[10] & 0xff; 552 ha->mpi_version[1] = mcp->mb[11] >> 8; 553 ha->mpi_version[2] = mcp->mb[11] & 0xff; 554 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13]; 555 ha->phy_version[0] = mcp->mb[8] & 0xff; 556 ha->phy_version[1] = mcp->mb[9] >> 8; 557 ha->phy_version[2] = mcp->mb[9] & 0xff; 558 } 559 if (IS_QLA83XX(ha)) { 560 if (mcp->mb[6] & BIT_15) { 561 ha->fw_attributes_h = mcp->mb[15]; 562 ha->fw_attributes_ext[0] = mcp->mb[16]; 563 ha->fw_attributes_ext[1] = mcp->mb[17]; 564 ql_dbg(ql_dbg_mbx, vha, 0x1139, 565 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n", 566 __func__, mcp->mb[15], mcp->mb[6]); 567 } else 568 ql_dbg(ql_dbg_mbx, vha, 0x112f, 569 "%s: FwAttributes [Upper] invalid, MB6:%04x\n", 570 __func__, mcp->mb[6]); 571 } 572 573 failed: 574 if (rval != QLA_SUCCESS) { 575 /*EMPTY*/ 576 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval); 577 } else { 578 /*EMPTY*/ 579 ql_dbg(ql_dbg_mbx, vha, 0x102b, "Done %s.\n", __func__); 580 } 581 return rval; 582 } 583 584 /* 585 * qla2x00_get_fw_options 586 * Set firmware options. 587 * 588 * Input: 589 * ha = adapter block pointer. 590 * fwopt = pointer for firmware options. 591 * 592 * Returns: 593 * qla2x00 local function return status code. 594 * 595 * Context: 596 * Kernel context. 597 */ 598 int 599 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 600 { 601 int rval; 602 mbx_cmd_t mc; 603 mbx_cmd_t *mcp = &mc; 604 605 ql_dbg(ql_dbg_mbx, vha, 0x102c, "Entered %s.\n", __func__); 606 607 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION; 608 mcp->out_mb = MBX_0; 609 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 610 mcp->tov = MBX_TOV_SECONDS; 611 mcp->flags = 0; 612 rval = qla2x00_mailbox_command(vha, mcp); 613 614 if (rval != QLA_SUCCESS) { 615 /*EMPTY*/ 616 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval); 617 } else { 618 fwopts[0] = mcp->mb[0]; 619 fwopts[1] = mcp->mb[1]; 620 fwopts[2] = mcp->mb[2]; 621 fwopts[3] = mcp->mb[3]; 622 623 ql_dbg(ql_dbg_mbx, vha, 0x102e, "Done %s.\n", __func__); 624 } 625 626 return rval; 627 } 628 629 630 /* 631 * qla2x00_set_fw_options 632 * Set firmware options. 633 * 634 * Input: 635 * ha = adapter block pointer. 636 * fwopt = pointer for firmware options. 637 * 638 * Returns: 639 * qla2x00 local function return status code. 640 * 641 * Context: 642 * Kernel context. 643 */ 644 int 645 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 646 { 647 int rval; 648 mbx_cmd_t mc; 649 mbx_cmd_t *mcp = &mc; 650 651 ql_dbg(ql_dbg_mbx, vha, 0x102f, "Entered %s.\n", __func__); 652 653 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION; 654 mcp->mb[1] = fwopts[1]; 655 mcp->mb[2] = fwopts[2]; 656 mcp->mb[3] = fwopts[3]; 657 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 658 mcp->in_mb = MBX_0; 659 if (IS_FWI2_CAPABLE(vha->hw)) { 660 mcp->in_mb |= MBX_1; 661 } else { 662 mcp->mb[10] = fwopts[10]; 663 mcp->mb[11] = fwopts[11]; 664 mcp->mb[12] = 0; /* Undocumented, but used */ 665 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 666 } 667 mcp->tov = MBX_TOV_SECONDS; 668 mcp->flags = 0; 669 rval = qla2x00_mailbox_command(vha, mcp); 670 671 fwopts[0] = mcp->mb[0]; 672 673 if (rval != QLA_SUCCESS) { 674 /*EMPTY*/ 675 ql_dbg(ql_dbg_mbx, vha, 0x1030, 676 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]); 677 } else { 678 /*EMPTY*/ 679 ql_dbg(ql_dbg_mbx, vha, 0x1031, "Done %s.\n", __func__); 680 } 681 682 return rval; 683 } 684 685 /* 686 * qla2x00_mbx_reg_test 687 * Mailbox register wrap test. 688 * 689 * Input: 690 * ha = adapter block pointer. 691 * TARGET_QUEUE_LOCK must be released. 692 * ADAPTER_STATE_LOCK must be released. 693 * 694 * Returns: 695 * qla2x00 local function return status code. 696 * 697 * Context: 698 * Kernel context. 699 */ 700 int 701 qla2x00_mbx_reg_test(scsi_qla_host_t *vha) 702 { 703 int rval; 704 mbx_cmd_t mc; 705 mbx_cmd_t *mcp = &mc; 706 707 ql_dbg(ql_dbg_mbx, vha, 0x1032, "Entered %s.\n", __func__); 708 709 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; 710 mcp->mb[1] = 0xAAAA; 711 mcp->mb[2] = 0x5555; 712 mcp->mb[3] = 0xAA55; 713 mcp->mb[4] = 0x55AA; 714 mcp->mb[5] = 0xA5A5; 715 mcp->mb[6] = 0x5A5A; 716 mcp->mb[7] = 0x2525; 717 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 718 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 719 mcp->tov = MBX_TOV_SECONDS; 720 mcp->flags = 0; 721 rval = qla2x00_mailbox_command(vha, mcp); 722 723 if (rval == QLA_SUCCESS) { 724 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 || 725 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA) 726 rval = QLA_FUNCTION_FAILED; 727 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A || 728 mcp->mb[7] != 0x2525) 729 rval = QLA_FUNCTION_FAILED; 730 } 731 732 if (rval != QLA_SUCCESS) { 733 /*EMPTY*/ 734 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval); 735 } else { 736 /*EMPTY*/ 737 ql_dbg(ql_dbg_mbx, vha, 0x1034, "Done %s.\n", __func__); 738 } 739 740 return rval; 741 } 742 743 /* 744 * qla2x00_verify_checksum 745 * Verify firmware checksum. 746 * 747 * Input: 748 * ha = adapter block pointer. 749 * TARGET_QUEUE_LOCK must be released. 750 * ADAPTER_STATE_LOCK must be released. 751 * 752 * Returns: 753 * qla2x00 local function return status code. 754 * 755 * Context: 756 * Kernel context. 757 */ 758 int 759 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr) 760 { 761 int rval; 762 mbx_cmd_t mc; 763 mbx_cmd_t *mcp = &mc; 764 765 ql_dbg(ql_dbg_mbx, vha, 0x1035, "Entered %s.\n", __func__); 766 767 mcp->mb[0] = MBC_VERIFY_CHECKSUM; 768 mcp->out_mb = MBX_0; 769 mcp->in_mb = MBX_0; 770 if (IS_FWI2_CAPABLE(vha->hw)) { 771 mcp->mb[1] = MSW(risc_addr); 772 mcp->mb[2] = LSW(risc_addr); 773 mcp->out_mb |= MBX_2|MBX_1; 774 mcp->in_mb |= MBX_2|MBX_1; 775 } else { 776 mcp->mb[1] = LSW(risc_addr); 777 mcp->out_mb |= MBX_1; 778 mcp->in_mb |= MBX_1; 779 } 780 781 mcp->tov = MBX_TOV_SECONDS; 782 mcp->flags = 0; 783 rval = qla2x00_mailbox_command(vha, mcp); 784 785 if (rval != QLA_SUCCESS) { 786 ql_dbg(ql_dbg_mbx, vha, 0x1036, 787 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ? 788 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]); 789 } else { 790 ql_dbg(ql_dbg_mbx, vha, 0x1037, "Done %s.\n", __func__); 791 } 792 793 return rval; 794 } 795 796 /* 797 * qla2x00_issue_iocb 798 * Issue IOCB using mailbox command 799 * 800 * Input: 801 * ha = adapter state pointer. 802 * buffer = buffer pointer. 803 * phys_addr = physical address of buffer. 804 * size = size of buffer. 805 * TARGET_QUEUE_LOCK must be released. 806 * ADAPTER_STATE_LOCK must be released. 807 * 808 * Returns: 809 * qla2x00 local function return status code. 810 * 811 * Context: 812 * Kernel context. 813 */ 814 int 815 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer, 816 dma_addr_t phys_addr, size_t size, uint32_t tov) 817 { 818 int rval; 819 mbx_cmd_t mc; 820 mbx_cmd_t *mcp = &mc; 821 822 ql_dbg(ql_dbg_mbx, vha, 0x1038, "Entered %s.\n", __func__); 823 824 mcp->mb[0] = MBC_IOCB_COMMAND_A64; 825 mcp->mb[1] = 0; 826 mcp->mb[2] = MSW(phys_addr); 827 mcp->mb[3] = LSW(phys_addr); 828 mcp->mb[6] = MSW(MSD(phys_addr)); 829 mcp->mb[7] = LSW(MSD(phys_addr)); 830 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 831 mcp->in_mb = MBX_2|MBX_0; 832 mcp->tov = tov; 833 mcp->flags = 0; 834 rval = qla2x00_mailbox_command(vha, mcp); 835 836 if (rval != QLA_SUCCESS) { 837 /*EMPTY*/ 838 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval); 839 } else { 840 sts_entry_t *sts_entry = (sts_entry_t *) buffer; 841 842 /* Mask reserved bits. */ 843 sts_entry->entry_status &= 844 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK; 845 ql_dbg(ql_dbg_mbx, vha, 0x103a, "Done %s.\n", __func__); 846 } 847 848 return rval; 849 } 850 851 int 852 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr, 853 size_t size) 854 { 855 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size, 856 MBX_TOV_SECONDS); 857 } 858 859 /* 860 * qla2x00_abort_command 861 * Abort command aborts a specified IOCB. 862 * 863 * Input: 864 * ha = adapter block pointer. 865 * sp = SB structure pointer. 866 * 867 * Returns: 868 * qla2x00 local function return status code. 869 * 870 * Context: 871 * Kernel context. 872 */ 873 int 874 qla2x00_abort_command(srb_t *sp) 875 { 876 unsigned long flags = 0; 877 int rval; 878 uint32_t handle = 0; 879 mbx_cmd_t mc; 880 mbx_cmd_t *mcp = &mc; 881 fc_port_t *fcport = sp->fcport; 882 scsi_qla_host_t *vha = fcport->vha; 883 struct qla_hw_data *ha = vha->hw; 884 struct req_que *req = vha->req; 885 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 886 887 ql_dbg(ql_dbg_mbx, vha, 0x103b, "Entered %s.\n", __func__); 888 889 spin_lock_irqsave(&ha->hardware_lock, flags); 890 for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) { 891 if (req->outstanding_cmds[handle] == sp) 892 break; 893 } 894 spin_unlock_irqrestore(&ha->hardware_lock, flags); 895 896 if (handle == MAX_OUTSTANDING_COMMANDS) { 897 /* command not found */ 898 return QLA_FUNCTION_FAILED; 899 } 900 901 mcp->mb[0] = MBC_ABORT_COMMAND; 902 if (HAS_EXTENDED_IDS(ha)) 903 mcp->mb[1] = fcport->loop_id; 904 else 905 mcp->mb[1] = fcport->loop_id << 8; 906 mcp->mb[2] = (uint16_t)handle; 907 mcp->mb[3] = (uint16_t)(handle >> 16); 908 mcp->mb[6] = (uint16_t)cmd->device->lun; 909 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 910 mcp->in_mb = MBX_0; 911 mcp->tov = MBX_TOV_SECONDS; 912 mcp->flags = 0; 913 rval = qla2x00_mailbox_command(vha, mcp); 914 915 if (rval != QLA_SUCCESS) { 916 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval); 917 } else { 918 ql_dbg(ql_dbg_mbx, vha, 0x103d, "Done %s.\n", __func__); 919 } 920 921 return rval; 922 } 923 924 int 925 qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag) 926 { 927 int rval, rval2; 928 mbx_cmd_t mc; 929 mbx_cmd_t *mcp = &mc; 930 scsi_qla_host_t *vha; 931 struct req_que *req; 932 struct rsp_que *rsp; 933 934 l = l; 935 vha = fcport->vha; 936 937 ql_dbg(ql_dbg_mbx, vha, 0x103e, "Entered %s.\n", __func__); 938 939 req = vha->hw->req_q_map[0]; 940 rsp = req->rsp; 941 mcp->mb[0] = MBC_ABORT_TARGET; 942 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0; 943 if (HAS_EXTENDED_IDS(vha->hw)) { 944 mcp->mb[1] = fcport->loop_id; 945 mcp->mb[10] = 0; 946 mcp->out_mb |= MBX_10; 947 } else { 948 mcp->mb[1] = fcport->loop_id << 8; 949 } 950 mcp->mb[2] = vha->hw->loop_reset_delay; 951 mcp->mb[9] = vha->vp_idx; 952 953 mcp->in_mb = MBX_0; 954 mcp->tov = MBX_TOV_SECONDS; 955 mcp->flags = 0; 956 rval = qla2x00_mailbox_command(vha, mcp); 957 if (rval != QLA_SUCCESS) { 958 ql_dbg(ql_dbg_mbx, vha, 0x103f, "Failed=%x.\n", rval); 959 } 960 961 /* Issue marker IOCB. */ 962 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0, 963 MK_SYNC_ID); 964 if (rval2 != QLA_SUCCESS) { 965 ql_dbg(ql_dbg_mbx, vha, 0x1040, 966 "Failed to issue marker IOCB (%x).\n", rval2); 967 } else { 968 ql_dbg(ql_dbg_mbx, vha, 0x1041, "Done %s.\n", __func__); 969 } 970 971 return rval; 972 } 973 974 int 975 qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag) 976 { 977 int rval, rval2; 978 mbx_cmd_t mc; 979 mbx_cmd_t *mcp = &mc; 980 scsi_qla_host_t *vha; 981 struct req_que *req; 982 struct rsp_que *rsp; 983 984 vha = fcport->vha; 985 986 ql_dbg(ql_dbg_mbx, vha, 0x1042, "Entered %s.\n", __func__); 987 988 req = vha->hw->req_q_map[0]; 989 rsp = req->rsp; 990 mcp->mb[0] = MBC_LUN_RESET; 991 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 992 if (HAS_EXTENDED_IDS(vha->hw)) 993 mcp->mb[1] = fcport->loop_id; 994 else 995 mcp->mb[1] = fcport->loop_id << 8; 996 mcp->mb[2] = l; 997 mcp->mb[3] = 0; 998 mcp->mb[9] = vha->vp_idx; 999 1000 mcp->in_mb = MBX_0; 1001 mcp->tov = MBX_TOV_SECONDS; 1002 mcp->flags = 0; 1003 rval = qla2x00_mailbox_command(vha, mcp); 1004 if (rval != QLA_SUCCESS) { 1005 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval); 1006 } 1007 1008 /* Issue marker IOCB. */ 1009 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 1010 MK_SYNC_ID_LUN); 1011 if (rval2 != QLA_SUCCESS) { 1012 ql_dbg(ql_dbg_mbx, vha, 0x1044, 1013 "Failed to issue marker IOCB (%x).\n", rval2); 1014 } else { 1015 ql_dbg(ql_dbg_mbx, vha, 0x1045, "Done %s.\n", __func__); 1016 } 1017 1018 return rval; 1019 } 1020 1021 /* 1022 * qla2x00_get_adapter_id 1023 * Get adapter ID and topology. 1024 * 1025 * Input: 1026 * ha = adapter block pointer. 1027 * id = pointer for loop ID. 1028 * al_pa = pointer for AL_PA. 1029 * area = pointer for area. 1030 * domain = pointer for domain. 1031 * top = pointer for topology. 1032 * TARGET_QUEUE_LOCK must be released. 1033 * ADAPTER_STATE_LOCK must be released. 1034 * 1035 * Returns: 1036 * qla2x00 local function return status code. 1037 * 1038 * Context: 1039 * Kernel context. 1040 */ 1041 int 1042 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa, 1043 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap) 1044 { 1045 int rval; 1046 mbx_cmd_t mc; 1047 mbx_cmd_t *mcp = &mc; 1048 1049 ql_dbg(ql_dbg_mbx, vha, 0x1046, "Entered %s.\n", __func__); 1050 1051 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID; 1052 mcp->mb[9] = vha->vp_idx; 1053 mcp->out_mb = MBX_9|MBX_0; 1054 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1055 if (IS_CNA_CAPABLE(vha->hw)) 1056 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; 1057 mcp->tov = MBX_TOV_SECONDS; 1058 mcp->flags = 0; 1059 rval = qla2x00_mailbox_command(vha, mcp); 1060 if (mcp->mb[0] == MBS_COMMAND_ERROR) 1061 rval = QLA_COMMAND_ERROR; 1062 else if (mcp->mb[0] == MBS_INVALID_COMMAND) 1063 rval = QLA_INVALID_COMMAND; 1064 1065 /* Return data. */ 1066 *id = mcp->mb[1]; 1067 *al_pa = LSB(mcp->mb[2]); 1068 *area = MSB(mcp->mb[2]); 1069 *domain = LSB(mcp->mb[3]); 1070 *top = mcp->mb[6]; 1071 *sw_cap = mcp->mb[7]; 1072 1073 if (rval != QLA_SUCCESS) { 1074 /*EMPTY*/ 1075 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval); 1076 } else { 1077 ql_dbg(ql_dbg_mbx, vha, 0x1048, "Done %s.\n", __func__); 1078 1079 if (IS_CNA_CAPABLE(vha->hw)) { 1080 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; 1081 vha->fcoe_fcf_idx = mcp->mb[10]; 1082 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; 1083 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff; 1084 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8; 1085 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff; 1086 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8; 1087 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff; 1088 } 1089 } 1090 1091 return rval; 1092 } 1093 1094 /* 1095 * qla2x00_get_retry_cnt 1096 * Get current firmware login retry count and delay. 1097 * 1098 * Input: 1099 * ha = adapter block pointer. 1100 * retry_cnt = pointer to login retry count. 1101 * tov = pointer to login timeout value. 1102 * 1103 * Returns: 1104 * qla2x00 local function return status code. 1105 * 1106 * Context: 1107 * Kernel context. 1108 */ 1109 int 1110 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov, 1111 uint16_t *r_a_tov) 1112 { 1113 int rval; 1114 uint16_t ratov; 1115 mbx_cmd_t mc; 1116 mbx_cmd_t *mcp = &mc; 1117 1118 ql_dbg(ql_dbg_mbx, vha, 0x1049, "Entered %s.\n", __func__); 1119 1120 mcp->mb[0] = MBC_GET_RETRY_COUNT; 1121 mcp->out_mb = MBX_0; 1122 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1123 mcp->tov = MBX_TOV_SECONDS; 1124 mcp->flags = 0; 1125 rval = qla2x00_mailbox_command(vha, mcp); 1126 1127 if (rval != QLA_SUCCESS) { 1128 /*EMPTY*/ 1129 ql_dbg(ql_dbg_mbx, vha, 0x104a, 1130 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 1131 } else { 1132 /* Convert returned data and check our values. */ 1133 *r_a_tov = mcp->mb[3] / 2; 1134 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */ 1135 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) { 1136 /* Update to the larger values */ 1137 *retry_cnt = (uint8_t)mcp->mb[1]; 1138 *tov = ratov; 1139 } 1140 1141 ql_dbg(ql_dbg_mbx, vha, 0x104b, 1142 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov); 1143 } 1144 1145 return rval; 1146 } 1147 1148 /* 1149 * qla2x00_init_firmware 1150 * Initialize adapter firmware. 1151 * 1152 * Input: 1153 * ha = adapter block pointer. 1154 * dptr = Initialization control block pointer. 1155 * size = size of initialization control block. 1156 * TARGET_QUEUE_LOCK must be released. 1157 * ADAPTER_STATE_LOCK must be released. 1158 * 1159 * Returns: 1160 * qla2x00 local function return status code. 1161 * 1162 * Context: 1163 * Kernel context. 1164 */ 1165 int 1166 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size) 1167 { 1168 int rval; 1169 mbx_cmd_t mc; 1170 mbx_cmd_t *mcp = &mc; 1171 struct qla_hw_data *ha = vha->hw; 1172 1173 ql_dbg(ql_dbg_mbx, vha, 0x104c, "Entered %s.\n", __func__); 1174 1175 if (IS_QLA82XX(ha) && ql2xdbwr) 1176 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, 1177 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16))); 1178 1179 if (ha->flags.npiv_supported) 1180 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE; 1181 else 1182 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; 1183 1184 mcp->mb[1] = 0; 1185 mcp->mb[2] = MSW(ha->init_cb_dma); 1186 mcp->mb[3] = LSW(ha->init_cb_dma); 1187 mcp->mb[6] = MSW(MSD(ha->init_cb_dma)); 1188 mcp->mb[7] = LSW(MSD(ha->init_cb_dma)); 1189 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1190 if ((IS_QLA81XX(ha) || IS_QLA83XX(ha)) && ha->ex_init_cb->ex_version) { 1191 mcp->mb[1] = BIT_0; 1192 mcp->mb[10] = MSW(ha->ex_init_cb_dma); 1193 mcp->mb[11] = LSW(ha->ex_init_cb_dma); 1194 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma)); 1195 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma)); 1196 mcp->mb[14] = sizeof(*ha->ex_init_cb); 1197 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10; 1198 } 1199 /* 1 and 2 should normally be captured. */ 1200 mcp->in_mb = MBX_2|MBX_1|MBX_0; 1201 if (IS_QLA83XX(ha)) 1202 /* mb3 is additional info about the installed SFP. */ 1203 mcp->in_mb |= MBX_3; 1204 mcp->buf_size = size; 1205 mcp->flags = MBX_DMA_OUT; 1206 mcp->tov = MBX_TOV_SECONDS; 1207 rval = qla2x00_mailbox_command(vha, mcp); 1208 1209 if (rval != QLA_SUCCESS) { 1210 /*EMPTY*/ 1211 ql_dbg(ql_dbg_mbx, vha, 0x104d, 1212 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n", 1213 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]); 1214 } else { 1215 /*EMPTY*/ 1216 ql_dbg(ql_dbg_mbx, vha, 0x104e, "Done %s.\n", __func__); 1217 } 1218 1219 return rval; 1220 } 1221 1222 /* 1223 * qla2x00_get_port_database 1224 * Issue normal/enhanced get port database mailbox command 1225 * and copy device name as necessary. 1226 * 1227 * Input: 1228 * ha = adapter state pointer. 1229 * dev = structure pointer. 1230 * opt = enhanced cmd option byte. 1231 * 1232 * Returns: 1233 * qla2x00 local function return status code. 1234 * 1235 * Context: 1236 * Kernel context. 1237 */ 1238 int 1239 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt) 1240 { 1241 int rval; 1242 mbx_cmd_t mc; 1243 mbx_cmd_t *mcp = &mc; 1244 port_database_t *pd; 1245 struct port_database_24xx *pd24; 1246 dma_addr_t pd_dma; 1247 struct qla_hw_data *ha = vha->hw; 1248 1249 ql_dbg(ql_dbg_mbx, vha, 0x104f, "Entered %s.\n", __func__); 1250 1251 pd24 = NULL; 1252 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1253 if (pd == NULL) { 1254 ql_log(ql_log_warn, vha, 0x1050, 1255 "Failed to allocate port database structure.\n"); 1256 return QLA_MEMORY_ALLOC_FAILED; 1257 } 1258 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE)); 1259 1260 mcp->mb[0] = MBC_GET_PORT_DATABASE; 1261 if (opt != 0 && !IS_FWI2_CAPABLE(ha)) 1262 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE; 1263 mcp->mb[2] = MSW(pd_dma); 1264 mcp->mb[3] = LSW(pd_dma); 1265 mcp->mb[6] = MSW(MSD(pd_dma)); 1266 mcp->mb[7] = LSW(MSD(pd_dma)); 1267 mcp->mb[9] = vha->vp_idx; 1268 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 1269 mcp->in_mb = MBX_0; 1270 if (IS_FWI2_CAPABLE(ha)) { 1271 mcp->mb[1] = fcport->loop_id; 1272 mcp->mb[10] = opt; 1273 mcp->out_mb |= MBX_10|MBX_1; 1274 mcp->in_mb |= MBX_1; 1275 } else if (HAS_EXTENDED_IDS(ha)) { 1276 mcp->mb[1] = fcport->loop_id; 1277 mcp->mb[10] = opt; 1278 mcp->out_mb |= MBX_10|MBX_1; 1279 } else { 1280 mcp->mb[1] = fcport->loop_id << 8 | opt; 1281 mcp->out_mb |= MBX_1; 1282 } 1283 mcp->buf_size = IS_FWI2_CAPABLE(ha) ? 1284 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE; 1285 mcp->flags = MBX_DMA_IN; 1286 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1287 rval = qla2x00_mailbox_command(vha, mcp); 1288 if (rval != QLA_SUCCESS) 1289 goto gpd_error_out; 1290 1291 if (IS_FWI2_CAPABLE(ha)) { 1292 uint64_t zero = 0; 1293 pd24 = (struct port_database_24xx *) pd; 1294 1295 /* Check for logged in state. */ 1296 if (pd24->current_login_state != PDS_PRLI_COMPLETE && 1297 pd24->last_login_state != PDS_PRLI_COMPLETE) { 1298 ql_dbg(ql_dbg_mbx, vha, 0x1051, 1299 "Unable to verify login-state (%x/%x) for " 1300 "loop_id %x.\n", pd24->current_login_state, 1301 pd24->last_login_state, fcport->loop_id); 1302 rval = QLA_FUNCTION_FAILED; 1303 goto gpd_error_out; 1304 } 1305 1306 if (fcport->loop_id == FC_NO_LOOP_ID || 1307 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1308 memcmp(fcport->port_name, pd24->port_name, 8))) { 1309 /* We lost the device mid way. */ 1310 rval = QLA_NOT_LOGGED_IN; 1311 goto gpd_error_out; 1312 } 1313 1314 /* Names are little-endian. */ 1315 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE); 1316 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE); 1317 1318 /* Get port_id of device. */ 1319 fcport->d_id.b.domain = pd24->port_id[0]; 1320 fcport->d_id.b.area = pd24->port_id[1]; 1321 fcport->d_id.b.al_pa = pd24->port_id[2]; 1322 fcport->d_id.b.rsvd_1 = 0; 1323 1324 /* If not target must be initiator or unknown type. */ 1325 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0) 1326 fcport->port_type = FCT_INITIATOR; 1327 else 1328 fcport->port_type = FCT_TARGET; 1329 } else { 1330 uint64_t zero = 0; 1331 1332 /* Check for logged in state. */ 1333 if (pd->master_state != PD_STATE_PORT_LOGGED_IN && 1334 pd->slave_state != PD_STATE_PORT_LOGGED_IN) { 1335 ql_dbg(ql_dbg_mbx, vha, 0x100a, 1336 "Unable to verify login-state (%x/%x) - " 1337 "portid=%02x%02x%02x.\n", pd->master_state, 1338 pd->slave_state, fcport->d_id.b.domain, 1339 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1340 rval = QLA_FUNCTION_FAILED; 1341 goto gpd_error_out; 1342 } 1343 1344 if (fcport->loop_id == FC_NO_LOOP_ID || 1345 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1346 memcmp(fcport->port_name, pd->port_name, 8))) { 1347 /* We lost the device mid way. */ 1348 rval = QLA_NOT_LOGGED_IN; 1349 goto gpd_error_out; 1350 } 1351 1352 /* Names are little-endian. */ 1353 memcpy(fcport->node_name, pd->node_name, WWN_SIZE); 1354 memcpy(fcport->port_name, pd->port_name, WWN_SIZE); 1355 1356 /* Get port_id of device. */ 1357 fcport->d_id.b.domain = pd->port_id[0]; 1358 fcport->d_id.b.area = pd->port_id[3]; 1359 fcport->d_id.b.al_pa = pd->port_id[2]; 1360 fcport->d_id.b.rsvd_1 = 0; 1361 1362 /* If not target must be initiator or unknown type. */ 1363 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 1364 fcport->port_type = FCT_INITIATOR; 1365 else 1366 fcport->port_type = FCT_TARGET; 1367 1368 /* Passback COS information. */ 1369 fcport->supported_classes = (pd->options & BIT_4) ? 1370 FC_COS_CLASS2: FC_COS_CLASS3; 1371 } 1372 1373 gpd_error_out: 1374 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1375 1376 if (rval != QLA_SUCCESS) { 1377 ql_dbg(ql_dbg_mbx, vha, 0x1052, 1378 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval, 1379 mcp->mb[0], mcp->mb[1]); 1380 } else { 1381 ql_dbg(ql_dbg_mbx, vha, 0x1053, "Done %s.\n", __func__); 1382 } 1383 1384 return rval; 1385 } 1386 1387 /* 1388 * qla2x00_get_firmware_state 1389 * Get adapter firmware state. 1390 * 1391 * Input: 1392 * ha = adapter block pointer. 1393 * dptr = pointer for firmware state. 1394 * TARGET_QUEUE_LOCK must be released. 1395 * ADAPTER_STATE_LOCK must be released. 1396 * 1397 * Returns: 1398 * qla2x00 local function return status code. 1399 * 1400 * Context: 1401 * Kernel context. 1402 */ 1403 int 1404 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states) 1405 { 1406 int rval; 1407 mbx_cmd_t mc; 1408 mbx_cmd_t *mcp = &mc; 1409 1410 ql_dbg(ql_dbg_mbx, vha, 0x1054, "Entered %s.\n", __func__); 1411 1412 mcp->mb[0] = MBC_GET_FIRMWARE_STATE; 1413 mcp->out_mb = MBX_0; 1414 if (IS_FWI2_CAPABLE(vha->hw)) 1415 mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1416 else 1417 mcp->in_mb = MBX_1|MBX_0; 1418 mcp->tov = MBX_TOV_SECONDS; 1419 mcp->flags = 0; 1420 rval = qla2x00_mailbox_command(vha, mcp); 1421 1422 /* Return firmware states. */ 1423 states[0] = mcp->mb[1]; 1424 if (IS_FWI2_CAPABLE(vha->hw)) { 1425 states[1] = mcp->mb[2]; 1426 states[2] = mcp->mb[3]; 1427 states[3] = mcp->mb[4]; 1428 states[4] = mcp->mb[5]; 1429 } 1430 1431 if (rval != QLA_SUCCESS) { 1432 /*EMPTY*/ 1433 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval); 1434 } else { 1435 /*EMPTY*/ 1436 ql_dbg(ql_dbg_mbx, vha, 0x1056, "Done %s.\n", __func__); 1437 } 1438 1439 return rval; 1440 } 1441 1442 /* 1443 * qla2x00_get_port_name 1444 * Issue get port name mailbox command. 1445 * Returned name is in big endian format. 1446 * 1447 * Input: 1448 * ha = adapter block pointer. 1449 * loop_id = loop ID of device. 1450 * name = pointer for name. 1451 * TARGET_QUEUE_LOCK must be released. 1452 * ADAPTER_STATE_LOCK must be released. 1453 * 1454 * Returns: 1455 * qla2x00 local function return status code. 1456 * 1457 * Context: 1458 * Kernel context. 1459 */ 1460 int 1461 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name, 1462 uint8_t opt) 1463 { 1464 int rval; 1465 mbx_cmd_t mc; 1466 mbx_cmd_t *mcp = &mc; 1467 1468 ql_dbg(ql_dbg_mbx, vha, 0x1057, "Entered %s.\n", __func__); 1469 1470 mcp->mb[0] = MBC_GET_PORT_NAME; 1471 mcp->mb[9] = vha->vp_idx; 1472 mcp->out_mb = MBX_9|MBX_1|MBX_0; 1473 if (HAS_EXTENDED_IDS(vha->hw)) { 1474 mcp->mb[1] = loop_id; 1475 mcp->mb[10] = opt; 1476 mcp->out_mb |= MBX_10; 1477 } else { 1478 mcp->mb[1] = loop_id << 8 | opt; 1479 } 1480 1481 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1482 mcp->tov = MBX_TOV_SECONDS; 1483 mcp->flags = 0; 1484 rval = qla2x00_mailbox_command(vha, mcp); 1485 1486 if (rval != QLA_SUCCESS) { 1487 /*EMPTY*/ 1488 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval); 1489 } else { 1490 if (name != NULL) { 1491 /* This function returns name in big endian. */ 1492 name[0] = MSB(mcp->mb[2]); 1493 name[1] = LSB(mcp->mb[2]); 1494 name[2] = MSB(mcp->mb[3]); 1495 name[3] = LSB(mcp->mb[3]); 1496 name[4] = MSB(mcp->mb[6]); 1497 name[5] = LSB(mcp->mb[6]); 1498 name[6] = MSB(mcp->mb[7]); 1499 name[7] = LSB(mcp->mb[7]); 1500 } 1501 1502 ql_dbg(ql_dbg_mbx, vha, 0x1059, "Done %s.\n", __func__); 1503 } 1504 1505 return rval; 1506 } 1507 1508 /* 1509 * qla2x00_lip_reset 1510 * Issue LIP reset mailbox command. 1511 * 1512 * Input: 1513 * ha = adapter block pointer. 1514 * TARGET_QUEUE_LOCK must be released. 1515 * ADAPTER_STATE_LOCK must be released. 1516 * 1517 * Returns: 1518 * qla2x00 local function return status code. 1519 * 1520 * Context: 1521 * Kernel context. 1522 */ 1523 int 1524 qla2x00_lip_reset(scsi_qla_host_t *vha) 1525 { 1526 int rval; 1527 mbx_cmd_t mc; 1528 mbx_cmd_t *mcp = &mc; 1529 1530 ql_dbg(ql_dbg_mbx, vha, 0x105a, "Entered %s.\n", __func__); 1531 1532 if (IS_CNA_CAPABLE(vha->hw)) { 1533 /* Logout across all FCFs. */ 1534 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1535 mcp->mb[1] = BIT_1; 1536 mcp->mb[2] = 0; 1537 mcp->out_mb = MBX_2|MBX_1|MBX_0; 1538 } else if (IS_FWI2_CAPABLE(vha->hw)) { 1539 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1540 mcp->mb[1] = BIT_6; 1541 mcp->mb[2] = 0; 1542 mcp->mb[3] = vha->hw->loop_reset_delay; 1543 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1544 } else { 1545 mcp->mb[0] = MBC_LIP_RESET; 1546 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1547 if (HAS_EXTENDED_IDS(vha->hw)) { 1548 mcp->mb[1] = 0x00ff; 1549 mcp->mb[10] = 0; 1550 mcp->out_mb |= MBX_10; 1551 } else { 1552 mcp->mb[1] = 0xff00; 1553 } 1554 mcp->mb[2] = vha->hw->loop_reset_delay; 1555 mcp->mb[3] = 0; 1556 } 1557 mcp->in_mb = MBX_0; 1558 mcp->tov = MBX_TOV_SECONDS; 1559 mcp->flags = 0; 1560 rval = qla2x00_mailbox_command(vha, mcp); 1561 1562 if (rval != QLA_SUCCESS) { 1563 /*EMPTY*/ 1564 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval); 1565 } else { 1566 /*EMPTY*/ 1567 ql_dbg(ql_dbg_mbx, vha, 0x105c, "Done %s.\n", __func__); 1568 } 1569 1570 return rval; 1571 } 1572 1573 /* 1574 * qla2x00_send_sns 1575 * Send SNS command. 1576 * 1577 * Input: 1578 * ha = adapter block pointer. 1579 * sns = pointer for command. 1580 * cmd_size = command size. 1581 * buf_size = response/command size. 1582 * TARGET_QUEUE_LOCK must be released. 1583 * ADAPTER_STATE_LOCK must be released. 1584 * 1585 * Returns: 1586 * qla2x00 local function return status code. 1587 * 1588 * Context: 1589 * Kernel context. 1590 */ 1591 int 1592 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address, 1593 uint16_t cmd_size, size_t buf_size) 1594 { 1595 int rval; 1596 mbx_cmd_t mc; 1597 mbx_cmd_t *mcp = &mc; 1598 1599 ql_dbg(ql_dbg_mbx, vha, 0x105d, "Entered %s.\n", __func__); 1600 1601 ql_dbg(ql_dbg_mbx, vha, 0x105e, 1602 "Retry cnt=%d ratov=%d total tov=%d.\n", 1603 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov); 1604 1605 mcp->mb[0] = MBC_SEND_SNS_COMMAND; 1606 mcp->mb[1] = cmd_size; 1607 mcp->mb[2] = MSW(sns_phys_address); 1608 mcp->mb[3] = LSW(sns_phys_address); 1609 mcp->mb[6] = MSW(MSD(sns_phys_address)); 1610 mcp->mb[7] = LSW(MSD(sns_phys_address)); 1611 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1612 mcp->in_mb = MBX_0|MBX_1; 1613 mcp->buf_size = buf_size; 1614 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN; 1615 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2); 1616 rval = qla2x00_mailbox_command(vha, mcp); 1617 1618 if (rval != QLA_SUCCESS) { 1619 /*EMPTY*/ 1620 ql_dbg(ql_dbg_mbx, vha, 0x105f, 1621 "Failed=%x mb[0]=%x mb[1]=%x.\n", 1622 rval, mcp->mb[0], mcp->mb[1]); 1623 } else { 1624 /*EMPTY*/ 1625 ql_dbg(ql_dbg_mbx, vha, 0x1060, "Done %s.\n", __func__); 1626 } 1627 1628 return rval; 1629 } 1630 1631 int 1632 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 1633 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 1634 { 1635 int rval; 1636 1637 struct logio_entry_24xx *lg; 1638 dma_addr_t lg_dma; 1639 uint32_t iop[2]; 1640 struct qla_hw_data *ha = vha->hw; 1641 struct req_que *req; 1642 struct rsp_que *rsp; 1643 1644 ql_dbg(ql_dbg_mbx, vha, 0x1061, "Entered %s.\n", __func__); 1645 1646 if (ha->flags.cpu_affinity_enabled) 1647 req = ha->req_q_map[0]; 1648 else 1649 req = vha->req; 1650 rsp = req->rsp; 1651 1652 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 1653 if (lg == NULL) { 1654 ql_log(ql_log_warn, vha, 0x1062, 1655 "Failed to allocate login IOCB.\n"); 1656 return QLA_MEMORY_ALLOC_FAILED; 1657 } 1658 memset(lg, 0, sizeof(struct logio_entry_24xx)); 1659 1660 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 1661 lg->entry_count = 1; 1662 lg->handle = MAKE_HANDLE(req->id, lg->handle); 1663 lg->nport_handle = cpu_to_le16(loop_id); 1664 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI); 1665 if (opt & BIT_0) 1666 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI); 1667 if (opt & BIT_1) 1668 lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI); 1669 lg->port_id[0] = al_pa; 1670 lg->port_id[1] = area; 1671 lg->port_id[2] = domain; 1672 lg->vp_index = vha->vp_idx; 1673 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 1674 (ha->r_a_tov / 10 * 2) + 2); 1675 if (rval != QLA_SUCCESS) { 1676 ql_dbg(ql_dbg_mbx, vha, 0x1063, 1677 "Failed to issue login IOCB (%x).\n", rval); 1678 } else if (lg->entry_status != 0) { 1679 ql_dbg(ql_dbg_mbx, vha, 0x1064, 1680 "Failed to complete IOCB -- error status (%x).\n", 1681 lg->entry_status); 1682 rval = QLA_FUNCTION_FAILED; 1683 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 1684 iop[0] = le32_to_cpu(lg->io_parameter[0]); 1685 iop[1] = le32_to_cpu(lg->io_parameter[1]); 1686 1687 ql_dbg(ql_dbg_mbx, vha, 0x1065, 1688 "Failed to complete IOCB -- completion status (%x) " 1689 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 1690 iop[0], iop[1]); 1691 1692 switch (iop[0]) { 1693 case LSC_SCODE_PORTID_USED: 1694 mb[0] = MBS_PORT_ID_USED; 1695 mb[1] = LSW(iop[1]); 1696 break; 1697 case LSC_SCODE_NPORT_USED: 1698 mb[0] = MBS_LOOP_ID_USED; 1699 break; 1700 case LSC_SCODE_NOLINK: 1701 case LSC_SCODE_NOIOCB: 1702 case LSC_SCODE_NOXCB: 1703 case LSC_SCODE_CMD_FAILED: 1704 case LSC_SCODE_NOFABRIC: 1705 case LSC_SCODE_FW_NOT_READY: 1706 case LSC_SCODE_NOT_LOGGED_IN: 1707 case LSC_SCODE_NOPCB: 1708 case LSC_SCODE_ELS_REJECT: 1709 case LSC_SCODE_CMD_PARAM_ERR: 1710 case LSC_SCODE_NONPORT: 1711 case LSC_SCODE_LOGGED_IN: 1712 case LSC_SCODE_NOFLOGI_ACC: 1713 default: 1714 mb[0] = MBS_COMMAND_ERROR; 1715 break; 1716 } 1717 } else { 1718 ql_dbg(ql_dbg_mbx, vha, 0x1066, "Done %s.\n", __func__); 1719 1720 iop[0] = le32_to_cpu(lg->io_parameter[0]); 1721 1722 mb[0] = MBS_COMMAND_COMPLETE; 1723 mb[1] = 0; 1724 if (iop[0] & BIT_4) { 1725 if (iop[0] & BIT_8) 1726 mb[1] |= BIT_1; 1727 } else 1728 mb[1] = BIT_0; 1729 1730 /* Passback COS information. */ 1731 mb[10] = 0; 1732 if (lg->io_parameter[7] || lg->io_parameter[8]) 1733 mb[10] |= BIT_0; /* Class 2. */ 1734 if (lg->io_parameter[9] || lg->io_parameter[10]) 1735 mb[10] |= BIT_1; /* Class 3. */ 1736 } 1737 1738 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 1739 1740 return rval; 1741 } 1742 1743 /* 1744 * qla2x00_login_fabric 1745 * Issue login fabric port mailbox command. 1746 * 1747 * Input: 1748 * ha = adapter block pointer. 1749 * loop_id = device loop ID. 1750 * domain = device domain. 1751 * area = device area. 1752 * al_pa = device AL_PA. 1753 * status = pointer for return status. 1754 * opt = command options. 1755 * TARGET_QUEUE_LOCK must be released. 1756 * ADAPTER_STATE_LOCK must be released. 1757 * 1758 * Returns: 1759 * qla2x00 local function return status code. 1760 * 1761 * Context: 1762 * Kernel context. 1763 */ 1764 int 1765 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 1766 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 1767 { 1768 int rval; 1769 mbx_cmd_t mc; 1770 mbx_cmd_t *mcp = &mc; 1771 struct qla_hw_data *ha = vha->hw; 1772 1773 ql_dbg(ql_dbg_mbx, vha, 0x1067, "Entered %s.\n", __func__); 1774 1775 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT; 1776 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1777 if (HAS_EXTENDED_IDS(ha)) { 1778 mcp->mb[1] = loop_id; 1779 mcp->mb[10] = opt; 1780 mcp->out_mb |= MBX_10; 1781 } else { 1782 mcp->mb[1] = (loop_id << 8) | opt; 1783 } 1784 mcp->mb[2] = domain; 1785 mcp->mb[3] = area << 8 | al_pa; 1786 1787 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0; 1788 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1789 mcp->flags = 0; 1790 rval = qla2x00_mailbox_command(vha, mcp); 1791 1792 /* Return mailbox statuses. */ 1793 if (mb != NULL) { 1794 mb[0] = mcp->mb[0]; 1795 mb[1] = mcp->mb[1]; 1796 mb[2] = mcp->mb[2]; 1797 mb[6] = mcp->mb[6]; 1798 mb[7] = mcp->mb[7]; 1799 /* COS retrieved from Get-Port-Database mailbox command. */ 1800 mb[10] = 0; 1801 } 1802 1803 if (rval != QLA_SUCCESS) { 1804 /* RLU tmp code: need to change main mailbox_command function to 1805 * return ok even when the mailbox completion value is not 1806 * SUCCESS. The caller needs to be responsible to interpret 1807 * the return values of this mailbox command if we're not 1808 * to change too much of the existing code. 1809 */ 1810 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 || 1811 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 || 1812 mcp->mb[0] == 0x4006) 1813 rval = QLA_SUCCESS; 1814 1815 /*EMPTY*/ 1816 ql_dbg(ql_dbg_mbx, vha, 0x1068, 1817 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 1818 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 1819 } else { 1820 /*EMPTY*/ 1821 ql_dbg(ql_dbg_mbx, vha, 0x1069, "Done %s.\n", __func__); 1822 } 1823 1824 return rval; 1825 } 1826 1827 /* 1828 * qla2x00_login_local_device 1829 * Issue login loop port mailbox command. 1830 * 1831 * Input: 1832 * ha = adapter block pointer. 1833 * loop_id = device loop ID. 1834 * opt = command options. 1835 * 1836 * Returns: 1837 * Return status code. 1838 * 1839 * Context: 1840 * Kernel context. 1841 * 1842 */ 1843 int 1844 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport, 1845 uint16_t *mb_ret, uint8_t opt) 1846 { 1847 int rval; 1848 mbx_cmd_t mc; 1849 mbx_cmd_t *mcp = &mc; 1850 struct qla_hw_data *ha = vha->hw; 1851 1852 ql_dbg(ql_dbg_mbx, vha, 0x106a, "Entered %s.\n", __func__); 1853 1854 if (IS_FWI2_CAPABLE(ha)) 1855 return qla24xx_login_fabric(vha, fcport->loop_id, 1856 fcport->d_id.b.domain, fcport->d_id.b.area, 1857 fcport->d_id.b.al_pa, mb_ret, opt); 1858 1859 mcp->mb[0] = MBC_LOGIN_LOOP_PORT; 1860 if (HAS_EXTENDED_IDS(ha)) 1861 mcp->mb[1] = fcport->loop_id; 1862 else 1863 mcp->mb[1] = fcport->loop_id << 8; 1864 mcp->mb[2] = opt; 1865 mcp->out_mb = MBX_2|MBX_1|MBX_0; 1866 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0; 1867 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1868 mcp->flags = 0; 1869 rval = qla2x00_mailbox_command(vha, mcp); 1870 1871 /* Return mailbox statuses. */ 1872 if (mb_ret != NULL) { 1873 mb_ret[0] = mcp->mb[0]; 1874 mb_ret[1] = mcp->mb[1]; 1875 mb_ret[6] = mcp->mb[6]; 1876 mb_ret[7] = mcp->mb[7]; 1877 } 1878 1879 if (rval != QLA_SUCCESS) { 1880 /* AV tmp code: need to change main mailbox_command function to 1881 * return ok even when the mailbox completion value is not 1882 * SUCCESS. The caller needs to be responsible to interpret 1883 * the return values of this mailbox command if we're not 1884 * to change too much of the existing code. 1885 */ 1886 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006) 1887 rval = QLA_SUCCESS; 1888 1889 ql_dbg(ql_dbg_mbx, vha, 0x106b, 1890 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n", 1891 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]); 1892 } else { 1893 /*EMPTY*/ 1894 ql_dbg(ql_dbg_mbx, vha, 0x106c, "Done %s.\n", __func__); 1895 } 1896 1897 return (rval); 1898 } 1899 1900 int 1901 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 1902 uint8_t area, uint8_t al_pa) 1903 { 1904 int rval; 1905 struct logio_entry_24xx *lg; 1906 dma_addr_t lg_dma; 1907 struct qla_hw_data *ha = vha->hw; 1908 struct req_que *req; 1909 struct rsp_que *rsp; 1910 1911 ql_dbg(ql_dbg_mbx, vha, 0x106d, "Entered %s.\n", __func__); 1912 1913 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 1914 if (lg == NULL) { 1915 ql_log(ql_log_warn, vha, 0x106e, 1916 "Failed to allocate logout IOCB.\n"); 1917 return QLA_MEMORY_ALLOC_FAILED; 1918 } 1919 memset(lg, 0, sizeof(struct logio_entry_24xx)); 1920 1921 if (ql2xmaxqueues > 1) 1922 req = ha->req_q_map[0]; 1923 else 1924 req = vha->req; 1925 rsp = req->rsp; 1926 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 1927 lg->entry_count = 1; 1928 lg->handle = MAKE_HANDLE(req->id, lg->handle); 1929 lg->nport_handle = cpu_to_le16(loop_id); 1930 lg->control_flags = 1931 __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO| 1932 LCF_FREE_NPORT); 1933 lg->port_id[0] = al_pa; 1934 lg->port_id[1] = area; 1935 lg->port_id[2] = domain; 1936 lg->vp_index = vha->vp_idx; 1937 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 1938 (ha->r_a_tov / 10 * 2) + 2); 1939 if (rval != QLA_SUCCESS) { 1940 ql_dbg(ql_dbg_mbx, vha, 0x106f, 1941 "Failed to issue logout IOCB (%x).\n", rval); 1942 } else if (lg->entry_status != 0) { 1943 ql_dbg(ql_dbg_mbx, vha, 0x1070, 1944 "Failed to complete IOCB -- error status (%x).\n", 1945 lg->entry_status); 1946 rval = QLA_FUNCTION_FAILED; 1947 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 1948 ql_dbg(ql_dbg_mbx, vha, 0x1071, 1949 "Failed to complete IOCB -- completion status (%x) " 1950 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 1951 le32_to_cpu(lg->io_parameter[0]), 1952 le32_to_cpu(lg->io_parameter[1])); 1953 } else { 1954 /*EMPTY*/ 1955 ql_dbg(ql_dbg_mbx, vha, 0x1072, "Done %s.\n", __func__); 1956 } 1957 1958 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 1959 1960 return rval; 1961 } 1962 1963 /* 1964 * qla2x00_fabric_logout 1965 * Issue logout fabric port mailbox command. 1966 * 1967 * Input: 1968 * ha = adapter block pointer. 1969 * loop_id = device loop ID. 1970 * TARGET_QUEUE_LOCK must be released. 1971 * ADAPTER_STATE_LOCK must be released. 1972 * 1973 * Returns: 1974 * qla2x00 local function return status code. 1975 * 1976 * Context: 1977 * Kernel context. 1978 */ 1979 int 1980 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 1981 uint8_t area, uint8_t al_pa) 1982 { 1983 int rval; 1984 mbx_cmd_t mc; 1985 mbx_cmd_t *mcp = &mc; 1986 1987 ql_dbg(ql_dbg_mbx, vha, 0x1073, "Entered %s.\n", __func__); 1988 1989 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT; 1990 mcp->out_mb = MBX_1|MBX_0; 1991 if (HAS_EXTENDED_IDS(vha->hw)) { 1992 mcp->mb[1] = loop_id; 1993 mcp->mb[10] = 0; 1994 mcp->out_mb |= MBX_10; 1995 } else { 1996 mcp->mb[1] = loop_id << 8; 1997 } 1998 1999 mcp->in_mb = MBX_1|MBX_0; 2000 mcp->tov = MBX_TOV_SECONDS; 2001 mcp->flags = 0; 2002 rval = qla2x00_mailbox_command(vha, mcp); 2003 2004 if (rval != QLA_SUCCESS) { 2005 /*EMPTY*/ 2006 ql_dbg(ql_dbg_mbx, vha, 0x1074, 2007 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]); 2008 } else { 2009 /*EMPTY*/ 2010 ql_dbg(ql_dbg_mbx, vha, 0x1075, "Done %s.\n", __func__); 2011 } 2012 2013 return rval; 2014 } 2015 2016 /* 2017 * qla2x00_full_login_lip 2018 * Issue full login LIP mailbox command. 2019 * 2020 * Input: 2021 * ha = adapter block pointer. 2022 * TARGET_QUEUE_LOCK must be released. 2023 * ADAPTER_STATE_LOCK must be released. 2024 * 2025 * Returns: 2026 * qla2x00 local function return status code. 2027 * 2028 * Context: 2029 * Kernel context. 2030 */ 2031 int 2032 qla2x00_full_login_lip(scsi_qla_host_t *vha) 2033 { 2034 int rval; 2035 mbx_cmd_t mc; 2036 mbx_cmd_t *mcp = &mc; 2037 2038 ql_dbg(ql_dbg_mbx, vha, 0x1076, "Entered %s.\n", __func__); 2039 2040 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2041 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0; 2042 mcp->mb[2] = 0; 2043 mcp->mb[3] = 0; 2044 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2045 mcp->in_mb = MBX_0; 2046 mcp->tov = MBX_TOV_SECONDS; 2047 mcp->flags = 0; 2048 rval = qla2x00_mailbox_command(vha, mcp); 2049 2050 if (rval != QLA_SUCCESS) { 2051 /*EMPTY*/ 2052 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval); 2053 } else { 2054 /*EMPTY*/ 2055 ql_dbg(ql_dbg_mbx, vha, 0x1078, "Done %s.\n", __func__); 2056 } 2057 2058 return rval; 2059 } 2060 2061 /* 2062 * qla2x00_get_id_list 2063 * 2064 * Input: 2065 * ha = adapter block pointer. 2066 * 2067 * Returns: 2068 * qla2x00 local function return status code. 2069 * 2070 * Context: 2071 * Kernel context. 2072 */ 2073 int 2074 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma, 2075 uint16_t *entries) 2076 { 2077 int rval; 2078 mbx_cmd_t mc; 2079 mbx_cmd_t *mcp = &mc; 2080 2081 ql_dbg(ql_dbg_mbx, vha, 0x1079, "Entered %s.\n", __func__); 2082 2083 if (id_list == NULL) 2084 return QLA_FUNCTION_FAILED; 2085 2086 mcp->mb[0] = MBC_GET_ID_LIST; 2087 mcp->out_mb = MBX_0; 2088 if (IS_FWI2_CAPABLE(vha->hw)) { 2089 mcp->mb[2] = MSW(id_list_dma); 2090 mcp->mb[3] = LSW(id_list_dma); 2091 mcp->mb[6] = MSW(MSD(id_list_dma)); 2092 mcp->mb[7] = LSW(MSD(id_list_dma)); 2093 mcp->mb[8] = 0; 2094 mcp->mb[9] = vha->vp_idx; 2095 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2; 2096 } else { 2097 mcp->mb[1] = MSW(id_list_dma); 2098 mcp->mb[2] = LSW(id_list_dma); 2099 mcp->mb[3] = MSW(MSD(id_list_dma)); 2100 mcp->mb[6] = LSW(MSD(id_list_dma)); 2101 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1; 2102 } 2103 mcp->in_mb = MBX_1|MBX_0; 2104 mcp->tov = MBX_TOV_SECONDS; 2105 mcp->flags = 0; 2106 rval = qla2x00_mailbox_command(vha, mcp); 2107 2108 if (rval != QLA_SUCCESS) { 2109 /*EMPTY*/ 2110 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval); 2111 } else { 2112 *entries = mcp->mb[1]; 2113 ql_dbg(ql_dbg_mbx, vha, 0x107b, "Done %s.\n", __func__); 2114 } 2115 2116 return rval; 2117 } 2118 2119 /* 2120 * qla2x00_get_resource_cnts 2121 * Get current firmware resource counts. 2122 * 2123 * Input: 2124 * ha = adapter block pointer. 2125 * 2126 * Returns: 2127 * qla2x00 local function return status code. 2128 * 2129 * Context: 2130 * Kernel context. 2131 */ 2132 int 2133 qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt, 2134 uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt, 2135 uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs) 2136 { 2137 int rval; 2138 mbx_cmd_t mc; 2139 mbx_cmd_t *mcp = &mc; 2140 2141 ql_dbg(ql_dbg_mbx, vha, 0x107c, "Entered %s.\n", __func__); 2142 2143 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS; 2144 mcp->out_mb = MBX_0; 2145 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2146 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) 2147 mcp->in_mb |= MBX_12; 2148 mcp->tov = MBX_TOV_SECONDS; 2149 mcp->flags = 0; 2150 rval = qla2x00_mailbox_command(vha, mcp); 2151 2152 if (rval != QLA_SUCCESS) { 2153 /*EMPTY*/ 2154 ql_dbg(ql_dbg_mbx, vha, 0x107d, 2155 "Failed mb[0]=%x.\n", mcp->mb[0]); 2156 } else { 2157 ql_dbg(ql_dbg_mbx, vha, 0x107e, 2158 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x " 2159 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2], 2160 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10], 2161 mcp->mb[11], mcp->mb[12]); 2162 2163 if (cur_xchg_cnt) 2164 *cur_xchg_cnt = mcp->mb[3]; 2165 if (orig_xchg_cnt) 2166 *orig_xchg_cnt = mcp->mb[6]; 2167 if (cur_iocb_cnt) 2168 *cur_iocb_cnt = mcp->mb[7]; 2169 if (orig_iocb_cnt) 2170 *orig_iocb_cnt = mcp->mb[10]; 2171 if (vha->hw->flags.npiv_supported && max_npiv_vports) 2172 *max_npiv_vports = mcp->mb[11]; 2173 if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs) 2174 *max_fcfs = mcp->mb[12]; 2175 } 2176 2177 return (rval); 2178 } 2179 2180 /* 2181 * qla2x00_get_fcal_position_map 2182 * Get FCAL (LILP) position map using mailbox command 2183 * 2184 * Input: 2185 * ha = adapter state pointer. 2186 * pos_map = buffer pointer (can be NULL). 2187 * 2188 * Returns: 2189 * qla2x00 local function return status code. 2190 * 2191 * Context: 2192 * Kernel context. 2193 */ 2194 int 2195 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map) 2196 { 2197 int rval; 2198 mbx_cmd_t mc; 2199 mbx_cmd_t *mcp = &mc; 2200 char *pmap; 2201 dma_addr_t pmap_dma; 2202 struct qla_hw_data *ha = vha->hw; 2203 2204 ql_dbg(ql_dbg_mbx, vha, 0x107f, "Entered %s.\n", __func__); 2205 2206 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma); 2207 if (pmap == NULL) { 2208 ql_log(ql_log_warn, vha, 0x1080, 2209 "Memory alloc failed.\n"); 2210 return QLA_MEMORY_ALLOC_FAILED; 2211 } 2212 memset(pmap, 0, FCAL_MAP_SIZE); 2213 2214 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP; 2215 mcp->mb[2] = MSW(pmap_dma); 2216 mcp->mb[3] = LSW(pmap_dma); 2217 mcp->mb[6] = MSW(MSD(pmap_dma)); 2218 mcp->mb[7] = LSW(MSD(pmap_dma)); 2219 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2220 mcp->in_mb = MBX_1|MBX_0; 2221 mcp->buf_size = FCAL_MAP_SIZE; 2222 mcp->flags = MBX_DMA_IN; 2223 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2224 rval = qla2x00_mailbox_command(vha, mcp); 2225 2226 if (rval == QLA_SUCCESS) { 2227 ql_dbg(ql_dbg_mbx, vha, 0x1081, 2228 "mb0/mb1=%x/%X FC/AL position map size (%x).\n", 2229 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]); 2230 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d, 2231 pmap, pmap[0] + 1); 2232 2233 if (pos_map) 2234 memcpy(pos_map, pmap, FCAL_MAP_SIZE); 2235 } 2236 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma); 2237 2238 if (rval != QLA_SUCCESS) { 2239 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval); 2240 } else { 2241 ql_dbg(ql_dbg_mbx, vha, 0x1083, "Done %s.\n", __func__); 2242 } 2243 2244 return rval; 2245 } 2246 2247 /* 2248 * qla2x00_get_link_status 2249 * 2250 * Input: 2251 * ha = adapter block pointer. 2252 * loop_id = device loop ID. 2253 * ret_buf = pointer to link status return buffer. 2254 * 2255 * Returns: 2256 * 0 = success. 2257 * BIT_0 = mem alloc error. 2258 * BIT_1 = mailbox error. 2259 */ 2260 int 2261 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id, 2262 struct link_statistics *stats, dma_addr_t stats_dma) 2263 { 2264 int rval; 2265 mbx_cmd_t mc; 2266 mbx_cmd_t *mcp = &mc; 2267 uint32_t *siter, *diter, dwords; 2268 struct qla_hw_data *ha = vha->hw; 2269 2270 ql_dbg(ql_dbg_mbx, vha, 0x1084, "Entered %s.\n", __func__); 2271 2272 mcp->mb[0] = MBC_GET_LINK_STATUS; 2273 mcp->mb[2] = MSW(stats_dma); 2274 mcp->mb[3] = LSW(stats_dma); 2275 mcp->mb[6] = MSW(MSD(stats_dma)); 2276 mcp->mb[7] = LSW(MSD(stats_dma)); 2277 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2278 mcp->in_mb = MBX_0; 2279 if (IS_FWI2_CAPABLE(ha)) { 2280 mcp->mb[1] = loop_id; 2281 mcp->mb[4] = 0; 2282 mcp->mb[10] = 0; 2283 mcp->out_mb |= MBX_10|MBX_4|MBX_1; 2284 mcp->in_mb |= MBX_1; 2285 } else if (HAS_EXTENDED_IDS(ha)) { 2286 mcp->mb[1] = loop_id; 2287 mcp->mb[10] = 0; 2288 mcp->out_mb |= MBX_10|MBX_1; 2289 } else { 2290 mcp->mb[1] = loop_id << 8; 2291 mcp->out_mb |= MBX_1; 2292 } 2293 mcp->tov = MBX_TOV_SECONDS; 2294 mcp->flags = IOCTL_CMD; 2295 rval = qla2x00_mailbox_command(vha, mcp); 2296 2297 if (rval == QLA_SUCCESS) { 2298 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2299 ql_dbg(ql_dbg_mbx, vha, 0x1085, 2300 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2301 rval = QLA_FUNCTION_FAILED; 2302 } else { 2303 /* Copy over data -- firmware data is LE. */ 2304 ql_dbg(ql_dbg_mbx, vha, 0x1086, "Done %s.\n", __func__); 2305 dwords = offsetof(struct link_statistics, unused1) / 4; 2306 siter = diter = &stats->link_fail_cnt; 2307 while (dwords--) 2308 *diter++ = le32_to_cpu(*siter++); 2309 } 2310 } else { 2311 /* Failed. */ 2312 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval); 2313 } 2314 2315 return rval; 2316 } 2317 2318 int 2319 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats, 2320 dma_addr_t stats_dma) 2321 { 2322 int rval; 2323 mbx_cmd_t mc; 2324 mbx_cmd_t *mcp = &mc; 2325 uint32_t *siter, *diter, dwords; 2326 2327 ql_dbg(ql_dbg_mbx, vha, 0x1088, "Entered %s.\n", __func__); 2328 2329 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS; 2330 mcp->mb[2] = MSW(stats_dma); 2331 mcp->mb[3] = LSW(stats_dma); 2332 mcp->mb[6] = MSW(MSD(stats_dma)); 2333 mcp->mb[7] = LSW(MSD(stats_dma)); 2334 mcp->mb[8] = sizeof(struct link_statistics) / 4; 2335 mcp->mb[9] = vha->vp_idx; 2336 mcp->mb[10] = 0; 2337 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2338 mcp->in_mb = MBX_2|MBX_1|MBX_0; 2339 mcp->tov = MBX_TOV_SECONDS; 2340 mcp->flags = IOCTL_CMD; 2341 rval = qla2x00_mailbox_command(vha, mcp); 2342 2343 if (rval == QLA_SUCCESS) { 2344 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 2345 ql_dbg(ql_dbg_mbx, vha, 0x1089, 2346 "Failed mb[0]=%x.\n", mcp->mb[0]); 2347 rval = QLA_FUNCTION_FAILED; 2348 } else { 2349 ql_dbg(ql_dbg_mbx, vha, 0x108a, "Done %s.\n", __func__); 2350 /* Copy over data -- firmware data is LE. */ 2351 dwords = sizeof(struct link_statistics) / 4; 2352 siter = diter = &stats->link_fail_cnt; 2353 while (dwords--) 2354 *diter++ = le32_to_cpu(*siter++); 2355 } 2356 } else { 2357 /* Failed. */ 2358 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval); 2359 } 2360 2361 return rval; 2362 } 2363 2364 int 2365 qla24xx_abort_command(srb_t *sp) 2366 { 2367 int rval; 2368 unsigned long flags = 0; 2369 2370 struct abort_entry_24xx *abt; 2371 dma_addr_t abt_dma; 2372 uint32_t handle; 2373 fc_port_t *fcport = sp->fcport; 2374 struct scsi_qla_host *vha = fcport->vha; 2375 struct qla_hw_data *ha = vha->hw; 2376 struct req_que *req = vha->req; 2377 2378 ql_dbg(ql_dbg_mbx, vha, 0x108c, "Entered %s.\n", __func__); 2379 2380 spin_lock_irqsave(&ha->hardware_lock, flags); 2381 for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) { 2382 if (req->outstanding_cmds[handle] == sp) 2383 break; 2384 } 2385 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2386 if (handle == MAX_OUTSTANDING_COMMANDS) { 2387 /* Command not found. */ 2388 return QLA_FUNCTION_FAILED; 2389 } 2390 2391 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma); 2392 if (abt == NULL) { 2393 ql_log(ql_log_warn, vha, 0x108d, 2394 "Failed to allocate abort IOCB.\n"); 2395 return QLA_MEMORY_ALLOC_FAILED; 2396 } 2397 memset(abt, 0, sizeof(struct abort_entry_24xx)); 2398 2399 abt->entry_type = ABORT_IOCB_TYPE; 2400 abt->entry_count = 1; 2401 abt->handle = MAKE_HANDLE(req->id, abt->handle); 2402 abt->nport_handle = cpu_to_le16(fcport->loop_id); 2403 abt->handle_to_abort = MAKE_HANDLE(req->id, handle); 2404 abt->port_id[0] = fcport->d_id.b.al_pa; 2405 abt->port_id[1] = fcport->d_id.b.area; 2406 abt->port_id[2] = fcport->d_id.b.domain; 2407 abt->vp_index = fcport->vp_idx; 2408 2409 abt->req_que_no = cpu_to_le16(req->id); 2410 2411 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0); 2412 if (rval != QLA_SUCCESS) { 2413 ql_dbg(ql_dbg_mbx, vha, 0x108e, 2414 "Failed to issue IOCB (%x).\n", rval); 2415 } else if (abt->entry_status != 0) { 2416 ql_dbg(ql_dbg_mbx, vha, 0x108f, 2417 "Failed to complete IOCB -- error status (%x).\n", 2418 abt->entry_status); 2419 rval = QLA_FUNCTION_FAILED; 2420 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) { 2421 ql_dbg(ql_dbg_mbx, vha, 0x1090, 2422 "Failed to complete IOCB -- completion status (%x).\n", 2423 le16_to_cpu(abt->nport_handle)); 2424 rval = QLA_FUNCTION_FAILED; 2425 } else { 2426 ql_dbg(ql_dbg_mbx, vha, 0x1091, "Done %s.\n", __func__); 2427 } 2428 2429 dma_pool_free(ha->s_dma_pool, abt, abt_dma); 2430 2431 return rval; 2432 } 2433 2434 struct tsk_mgmt_cmd { 2435 union { 2436 struct tsk_mgmt_entry tsk; 2437 struct sts_entry_24xx sts; 2438 } p; 2439 }; 2440 2441 static int 2442 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport, 2443 unsigned int l, int tag) 2444 { 2445 int rval, rval2; 2446 struct tsk_mgmt_cmd *tsk; 2447 struct sts_entry_24xx *sts; 2448 dma_addr_t tsk_dma; 2449 scsi_qla_host_t *vha; 2450 struct qla_hw_data *ha; 2451 struct req_que *req; 2452 struct rsp_que *rsp; 2453 2454 vha = fcport->vha; 2455 ha = vha->hw; 2456 req = vha->req; 2457 2458 ql_dbg(ql_dbg_mbx, vha, 0x1092, "Entered %s.\n", __func__); 2459 2460 if (ha->flags.cpu_affinity_enabled) 2461 rsp = ha->rsp_q_map[tag + 1]; 2462 else 2463 rsp = req->rsp; 2464 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma); 2465 if (tsk == NULL) { 2466 ql_log(ql_log_warn, vha, 0x1093, 2467 "Failed to allocate task management IOCB.\n"); 2468 return QLA_MEMORY_ALLOC_FAILED; 2469 } 2470 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd)); 2471 2472 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE; 2473 tsk->p.tsk.entry_count = 1; 2474 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle); 2475 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id); 2476 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2); 2477 tsk->p.tsk.control_flags = cpu_to_le32(type); 2478 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa; 2479 tsk->p.tsk.port_id[1] = fcport->d_id.b.area; 2480 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain; 2481 tsk->p.tsk.vp_index = fcport->vp_idx; 2482 if (type == TCF_LUN_RESET) { 2483 int_to_scsilun(l, &tsk->p.tsk.lun); 2484 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun, 2485 sizeof(tsk->p.tsk.lun)); 2486 } 2487 2488 sts = &tsk->p.sts; 2489 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0); 2490 if (rval != QLA_SUCCESS) { 2491 ql_dbg(ql_dbg_mbx, vha, 0x1094, 2492 "Failed to issue %s reset IOCB (%x).\n", name, rval); 2493 } else if (sts->entry_status != 0) { 2494 ql_dbg(ql_dbg_mbx, vha, 0x1095, 2495 "Failed to complete IOCB -- error status (%x).\n", 2496 sts->entry_status); 2497 rval = QLA_FUNCTION_FAILED; 2498 } else if (sts->comp_status != 2499 __constant_cpu_to_le16(CS_COMPLETE)) { 2500 ql_dbg(ql_dbg_mbx, vha, 0x1096, 2501 "Failed to complete IOCB -- completion status (%x).\n", 2502 le16_to_cpu(sts->comp_status)); 2503 rval = QLA_FUNCTION_FAILED; 2504 } else if (le16_to_cpu(sts->scsi_status) & 2505 SS_RESPONSE_INFO_LEN_VALID) { 2506 if (le32_to_cpu(sts->rsp_data_len) < 4) { 2507 ql_dbg(ql_dbg_mbx, vha, 0x1097, 2508 "Ignoring inconsistent data length -- not enough " 2509 "response info (%d).\n", 2510 le32_to_cpu(sts->rsp_data_len)); 2511 } else if (sts->data[3]) { 2512 ql_dbg(ql_dbg_mbx, vha, 0x1098, 2513 "Failed to complete IOCB -- response (%x).\n", 2514 sts->data[3]); 2515 rval = QLA_FUNCTION_FAILED; 2516 } 2517 } 2518 2519 /* Issue marker IOCB. */ 2520 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l, 2521 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID); 2522 if (rval2 != QLA_SUCCESS) { 2523 ql_dbg(ql_dbg_mbx, vha, 0x1099, 2524 "Failed to issue marker IOCB (%x).\n", rval2); 2525 } else { 2526 ql_dbg(ql_dbg_mbx, vha, 0x109a, "Done %s.\n", __func__); 2527 } 2528 2529 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma); 2530 2531 return rval; 2532 } 2533 2534 int 2535 qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag) 2536 { 2537 struct qla_hw_data *ha = fcport->vha->hw; 2538 2539 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 2540 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag); 2541 2542 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag); 2543 } 2544 2545 int 2546 qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag) 2547 { 2548 struct qla_hw_data *ha = fcport->vha->hw; 2549 2550 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 2551 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag); 2552 2553 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag); 2554 } 2555 2556 int 2557 qla2x00_system_error(scsi_qla_host_t *vha) 2558 { 2559 int rval; 2560 mbx_cmd_t mc; 2561 mbx_cmd_t *mcp = &mc; 2562 struct qla_hw_data *ha = vha->hw; 2563 2564 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha)) 2565 return QLA_FUNCTION_FAILED; 2566 2567 ql_dbg(ql_dbg_mbx, vha, 0x109b, "Entered %s.\n", __func__); 2568 2569 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR; 2570 mcp->out_mb = MBX_0; 2571 mcp->in_mb = MBX_0; 2572 mcp->tov = 5; 2573 mcp->flags = 0; 2574 rval = qla2x00_mailbox_command(vha, mcp); 2575 2576 if (rval != QLA_SUCCESS) { 2577 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval); 2578 } else { 2579 ql_dbg(ql_dbg_mbx, vha, 0x109d, "Done %s.\n", __func__); 2580 } 2581 2582 return rval; 2583 } 2584 2585 /** 2586 * qla2x00_set_serdes_params() - 2587 * @ha: HA context 2588 * 2589 * Returns 2590 */ 2591 int 2592 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g, 2593 uint16_t sw_em_2g, uint16_t sw_em_4g) 2594 { 2595 int rval; 2596 mbx_cmd_t mc; 2597 mbx_cmd_t *mcp = &mc; 2598 2599 ql_dbg(ql_dbg_mbx, vha, 0x109e, "Entered %s.\n", __func__); 2600 2601 mcp->mb[0] = MBC_SERDES_PARAMS; 2602 mcp->mb[1] = BIT_0; 2603 mcp->mb[2] = sw_em_1g | BIT_15; 2604 mcp->mb[3] = sw_em_2g | BIT_15; 2605 mcp->mb[4] = sw_em_4g | BIT_15; 2606 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 2607 mcp->in_mb = MBX_0; 2608 mcp->tov = MBX_TOV_SECONDS; 2609 mcp->flags = 0; 2610 rval = qla2x00_mailbox_command(vha, mcp); 2611 2612 if (rval != QLA_SUCCESS) { 2613 /*EMPTY*/ 2614 ql_dbg(ql_dbg_mbx, vha, 0x109f, 2615 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 2616 } else { 2617 /*EMPTY*/ 2618 ql_dbg(ql_dbg_mbx, vha, 0x10a0, "Done %s.\n", __func__); 2619 } 2620 2621 return rval; 2622 } 2623 2624 int 2625 qla2x00_stop_firmware(scsi_qla_host_t *vha) 2626 { 2627 int rval; 2628 mbx_cmd_t mc; 2629 mbx_cmd_t *mcp = &mc; 2630 2631 if (!IS_FWI2_CAPABLE(vha->hw)) 2632 return QLA_FUNCTION_FAILED; 2633 2634 ql_dbg(ql_dbg_mbx, vha, 0x10a1, "Entered %s.\n", __func__); 2635 2636 mcp->mb[0] = MBC_STOP_FIRMWARE; 2637 mcp->mb[1] = 0; 2638 mcp->out_mb = MBX_1|MBX_0; 2639 mcp->in_mb = MBX_0; 2640 mcp->tov = 5; 2641 mcp->flags = 0; 2642 rval = qla2x00_mailbox_command(vha, mcp); 2643 2644 if (rval != QLA_SUCCESS) { 2645 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval); 2646 if (mcp->mb[0] == MBS_INVALID_COMMAND) 2647 rval = QLA_INVALID_COMMAND; 2648 } else { 2649 ql_dbg(ql_dbg_mbx, vha, 0x10a3, "Done %s.\n", __func__); 2650 } 2651 2652 return rval; 2653 } 2654 2655 int 2656 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma, 2657 uint16_t buffers) 2658 { 2659 int rval; 2660 mbx_cmd_t mc; 2661 mbx_cmd_t *mcp = &mc; 2662 2663 ql_dbg(ql_dbg_mbx, vha, 0x10a4, "Entered %s.\n", __func__); 2664 2665 if (!IS_FWI2_CAPABLE(vha->hw)) 2666 return QLA_FUNCTION_FAILED; 2667 2668 if (unlikely(pci_channel_offline(vha->hw->pdev))) 2669 return QLA_FUNCTION_FAILED; 2670 2671 mcp->mb[0] = MBC_TRACE_CONTROL; 2672 mcp->mb[1] = TC_EFT_ENABLE; 2673 mcp->mb[2] = LSW(eft_dma); 2674 mcp->mb[3] = MSW(eft_dma); 2675 mcp->mb[4] = LSW(MSD(eft_dma)); 2676 mcp->mb[5] = MSW(MSD(eft_dma)); 2677 mcp->mb[6] = buffers; 2678 mcp->mb[7] = TC_AEN_DISABLE; 2679 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 2680 mcp->in_mb = MBX_1|MBX_0; 2681 mcp->tov = MBX_TOV_SECONDS; 2682 mcp->flags = 0; 2683 rval = qla2x00_mailbox_command(vha, mcp); 2684 if (rval != QLA_SUCCESS) { 2685 ql_dbg(ql_dbg_mbx, vha, 0x10a5, 2686 "Failed=%x mb[0]=%x mb[1]=%x.\n", 2687 rval, mcp->mb[0], mcp->mb[1]); 2688 } else { 2689 ql_dbg(ql_dbg_mbx, vha, 0x10a6, "Done %s.\n", __func__); 2690 } 2691 2692 return rval; 2693 } 2694 2695 int 2696 qla2x00_disable_eft_trace(scsi_qla_host_t *vha) 2697 { 2698 int rval; 2699 mbx_cmd_t mc; 2700 mbx_cmd_t *mcp = &mc; 2701 2702 ql_dbg(ql_dbg_mbx, vha, 0x10a7, "Entered %s.\n", __func__); 2703 2704 if (!IS_FWI2_CAPABLE(vha->hw)) 2705 return QLA_FUNCTION_FAILED; 2706 2707 if (unlikely(pci_channel_offline(vha->hw->pdev))) 2708 return QLA_FUNCTION_FAILED; 2709 2710 mcp->mb[0] = MBC_TRACE_CONTROL; 2711 mcp->mb[1] = TC_EFT_DISABLE; 2712 mcp->out_mb = MBX_1|MBX_0; 2713 mcp->in_mb = MBX_1|MBX_0; 2714 mcp->tov = MBX_TOV_SECONDS; 2715 mcp->flags = 0; 2716 rval = qla2x00_mailbox_command(vha, mcp); 2717 if (rval != QLA_SUCCESS) { 2718 ql_dbg(ql_dbg_mbx, vha, 0x10a8, 2719 "Failed=%x mb[0]=%x mb[1]=%x.\n", 2720 rval, mcp->mb[0], mcp->mb[1]); 2721 } else { 2722 ql_dbg(ql_dbg_mbx, vha, 0x10a9, "Done %s.\n", __func__); 2723 } 2724 2725 return rval; 2726 } 2727 2728 int 2729 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma, 2730 uint16_t buffers, uint16_t *mb, uint32_t *dwords) 2731 { 2732 int rval; 2733 mbx_cmd_t mc; 2734 mbx_cmd_t *mcp = &mc; 2735 2736 ql_dbg(ql_dbg_mbx, vha, 0x10aa, "Entered %s.\n", __func__); 2737 2738 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) && 2739 !IS_QLA83XX(vha->hw)) 2740 return QLA_FUNCTION_FAILED; 2741 2742 if (unlikely(pci_channel_offline(vha->hw->pdev))) 2743 return QLA_FUNCTION_FAILED; 2744 2745 mcp->mb[0] = MBC_TRACE_CONTROL; 2746 mcp->mb[1] = TC_FCE_ENABLE; 2747 mcp->mb[2] = LSW(fce_dma); 2748 mcp->mb[3] = MSW(fce_dma); 2749 mcp->mb[4] = LSW(MSD(fce_dma)); 2750 mcp->mb[5] = MSW(MSD(fce_dma)); 2751 mcp->mb[6] = buffers; 2752 mcp->mb[7] = TC_AEN_DISABLE; 2753 mcp->mb[8] = 0; 2754 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE; 2755 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE; 2756 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 2757 MBX_1|MBX_0; 2758 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 2759 mcp->tov = MBX_TOV_SECONDS; 2760 mcp->flags = 0; 2761 rval = qla2x00_mailbox_command(vha, mcp); 2762 if (rval != QLA_SUCCESS) { 2763 ql_dbg(ql_dbg_mbx, vha, 0x10ab, 2764 "Failed=%x mb[0]=%x mb[1]=%x.\n", 2765 rval, mcp->mb[0], mcp->mb[1]); 2766 } else { 2767 ql_dbg(ql_dbg_mbx, vha, 0x10ac, "Done %s.\n", __func__); 2768 2769 if (mb) 2770 memcpy(mb, mcp->mb, 8 * sizeof(*mb)); 2771 if (dwords) 2772 *dwords = buffers; 2773 } 2774 2775 return rval; 2776 } 2777 2778 int 2779 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd) 2780 { 2781 int rval; 2782 mbx_cmd_t mc; 2783 mbx_cmd_t *mcp = &mc; 2784 2785 ql_dbg(ql_dbg_mbx, vha, 0x10ad, "Entered %s.\n", __func__); 2786 2787 if (!IS_FWI2_CAPABLE(vha->hw)) 2788 return QLA_FUNCTION_FAILED; 2789 2790 if (unlikely(pci_channel_offline(vha->hw->pdev))) 2791 return QLA_FUNCTION_FAILED; 2792 2793 mcp->mb[0] = MBC_TRACE_CONTROL; 2794 mcp->mb[1] = TC_FCE_DISABLE; 2795 mcp->mb[2] = TC_FCE_DISABLE_TRACE; 2796 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2797 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 2798 MBX_1|MBX_0; 2799 mcp->tov = MBX_TOV_SECONDS; 2800 mcp->flags = 0; 2801 rval = qla2x00_mailbox_command(vha, mcp); 2802 if (rval != QLA_SUCCESS) { 2803 ql_dbg(ql_dbg_mbx, vha, 0x10ae, 2804 "Failed=%x mb[0]=%x mb[1]=%x.\n", 2805 rval, mcp->mb[0], mcp->mb[1]); 2806 } else { 2807 ql_dbg(ql_dbg_mbx, vha, 0x10af, "Done %s.\n", __func__); 2808 2809 if (wr) 2810 *wr = (uint64_t) mcp->mb[5] << 48 | 2811 (uint64_t) mcp->mb[4] << 32 | 2812 (uint64_t) mcp->mb[3] << 16 | 2813 (uint64_t) mcp->mb[2]; 2814 if (rd) 2815 *rd = (uint64_t) mcp->mb[9] << 48 | 2816 (uint64_t) mcp->mb[8] << 32 | 2817 (uint64_t) mcp->mb[7] << 16 | 2818 (uint64_t) mcp->mb[6]; 2819 } 2820 2821 return rval; 2822 } 2823 2824 int 2825 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 2826 uint16_t *port_speed, uint16_t *mb) 2827 { 2828 int rval; 2829 mbx_cmd_t mc; 2830 mbx_cmd_t *mcp = &mc; 2831 2832 ql_dbg(ql_dbg_mbx, vha, 0x10b0, "Entered %s.\n", __func__); 2833 2834 if (!IS_IIDMA_CAPABLE(vha->hw)) 2835 return QLA_FUNCTION_FAILED; 2836 2837 mcp->mb[0] = MBC_PORT_PARAMS; 2838 mcp->mb[1] = loop_id; 2839 mcp->mb[2] = mcp->mb[3] = 0; 2840 mcp->mb[9] = vha->vp_idx; 2841 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 2842 mcp->in_mb = MBX_3|MBX_1|MBX_0; 2843 mcp->tov = MBX_TOV_SECONDS; 2844 mcp->flags = 0; 2845 rval = qla2x00_mailbox_command(vha, mcp); 2846 2847 /* Return mailbox statuses. */ 2848 if (mb != NULL) { 2849 mb[0] = mcp->mb[0]; 2850 mb[1] = mcp->mb[1]; 2851 mb[3] = mcp->mb[3]; 2852 } 2853 2854 if (rval != QLA_SUCCESS) { 2855 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval); 2856 } else { 2857 ql_dbg(ql_dbg_mbx, vha, 0x10b2, "Done %s.\n", __func__); 2858 if (port_speed) 2859 *port_speed = mcp->mb[3]; 2860 } 2861 2862 return rval; 2863 } 2864 2865 int 2866 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 2867 uint16_t port_speed, uint16_t *mb) 2868 { 2869 int rval; 2870 mbx_cmd_t mc; 2871 mbx_cmd_t *mcp = &mc; 2872 2873 ql_dbg(ql_dbg_mbx, vha, 0x10b3, "Entered %s.\n", __func__); 2874 2875 if (!IS_IIDMA_CAPABLE(vha->hw)) 2876 return QLA_FUNCTION_FAILED; 2877 2878 mcp->mb[0] = MBC_PORT_PARAMS; 2879 mcp->mb[1] = loop_id; 2880 mcp->mb[2] = BIT_0; 2881 if (IS_CNA_CAPABLE(vha->hw)) 2882 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); 2883 else 2884 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); 2885 mcp->mb[9] = vha->vp_idx; 2886 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 2887 mcp->in_mb = MBX_3|MBX_1|MBX_0; 2888 mcp->tov = MBX_TOV_SECONDS; 2889 mcp->flags = 0; 2890 rval = qla2x00_mailbox_command(vha, mcp); 2891 2892 /* Return mailbox statuses. */ 2893 if (mb != NULL) { 2894 mb[0] = mcp->mb[0]; 2895 mb[1] = mcp->mb[1]; 2896 mb[3] = mcp->mb[3]; 2897 } 2898 2899 if (rval != QLA_SUCCESS) { 2900 ql_dbg(ql_dbg_mbx, vha, 0x10b4, "Failed=%x.\n", rval); 2901 } else { 2902 ql_dbg(ql_dbg_mbx, vha, 0x10b5, "Done %s.\n", __func__); 2903 } 2904 2905 return rval; 2906 } 2907 2908 void 2909 qla24xx_report_id_acquisition(scsi_qla_host_t *vha, 2910 struct vp_rpt_id_entry_24xx *rptid_entry) 2911 { 2912 uint8_t vp_idx; 2913 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx); 2914 struct qla_hw_data *ha = vha->hw; 2915 scsi_qla_host_t *vp; 2916 unsigned long flags; 2917 2918 ql_dbg(ql_dbg_mbx, vha, 0x10b6, "Entered %s.\n", __func__); 2919 2920 if (rptid_entry->entry_status != 0) 2921 return; 2922 2923 if (rptid_entry->format == 0) { 2924 ql_dbg(ql_dbg_mbx, vha, 0x10b7, 2925 "Format 0 : Number of VPs setup %d, number of " 2926 "VPs acquired %d.\n", 2927 MSB(le16_to_cpu(rptid_entry->vp_count)), 2928 LSB(le16_to_cpu(rptid_entry->vp_count))); 2929 ql_dbg(ql_dbg_mbx, vha, 0x10b8, 2930 "Primary port id %02x%02x%02x.\n", 2931 rptid_entry->port_id[2], rptid_entry->port_id[1], 2932 rptid_entry->port_id[0]); 2933 } else if (rptid_entry->format == 1) { 2934 vp_idx = LSB(stat); 2935 ql_dbg(ql_dbg_mbx, vha, 0x10b9, 2936 "Format 1: VP[%d] enabled - status %d - with " 2937 "port id %02x%02x%02x.\n", vp_idx, MSB(stat), 2938 rptid_entry->port_id[2], rptid_entry->port_id[1], 2939 rptid_entry->port_id[0]); 2940 2941 vp = vha; 2942 if (vp_idx == 0 && (MSB(stat) != 1)) 2943 goto reg_needed; 2944 2945 if (MSB(stat) != 0) { 2946 ql_dbg(ql_dbg_mbx, vha, 0x10ba, 2947 "Could not acquire ID for VP[%d].\n", vp_idx); 2948 return; 2949 } 2950 2951 spin_lock_irqsave(&ha->vport_slock, flags); 2952 list_for_each_entry(vp, &ha->vp_list, list) 2953 if (vp_idx == vp->vp_idx) 2954 break; 2955 spin_unlock_irqrestore(&ha->vport_slock, flags); 2956 2957 if (!vp) 2958 return; 2959 2960 vp->d_id.b.domain = rptid_entry->port_id[2]; 2961 vp->d_id.b.area = rptid_entry->port_id[1]; 2962 vp->d_id.b.al_pa = rptid_entry->port_id[0]; 2963 2964 /* 2965 * Cannot configure here as we are still sitting on the 2966 * response queue. Handle it in dpc context. 2967 */ 2968 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags); 2969 2970 reg_needed: 2971 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags); 2972 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags); 2973 set_bit(VP_DPC_NEEDED, &vha->dpc_flags); 2974 qla2xxx_wake_dpc(vha); 2975 } 2976 } 2977 2978 /* 2979 * qla24xx_modify_vp_config 2980 * Change VP configuration for vha 2981 * 2982 * Input: 2983 * vha = adapter block pointer. 2984 * 2985 * Returns: 2986 * qla2xxx local function return status code. 2987 * 2988 * Context: 2989 * Kernel context. 2990 */ 2991 int 2992 qla24xx_modify_vp_config(scsi_qla_host_t *vha) 2993 { 2994 int rval; 2995 struct vp_config_entry_24xx *vpmod; 2996 dma_addr_t vpmod_dma; 2997 struct qla_hw_data *ha = vha->hw; 2998 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2999 3000 /* This can be called by the parent */ 3001 3002 ql_dbg(ql_dbg_mbx, vha, 0x10bb, "Entered %s.\n", __func__); 3003 3004 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma); 3005 if (!vpmod) { 3006 ql_log(ql_log_warn, vha, 0x10bc, 3007 "Failed to allocate modify VP IOCB.\n"); 3008 return QLA_MEMORY_ALLOC_FAILED; 3009 } 3010 3011 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx)); 3012 vpmod->entry_type = VP_CONFIG_IOCB_TYPE; 3013 vpmod->entry_count = 1; 3014 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS; 3015 vpmod->vp_count = 1; 3016 vpmod->vp_index1 = vha->vp_idx; 3017 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; 3018 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE); 3019 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE); 3020 vpmod->entry_count = 1; 3021 3022 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0); 3023 if (rval != QLA_SUCCESS) { 3024 ql_dbg(ql_dbg_mbx, vha, 0x10bd, 3025 "Failed to issue VP config IOCB (%x).\n", rval); 3026 } else if (vpmod->comp_status != 0) { 3027 ql_dbg(ql_dbg_mbx, vha, 0x10be, 3028 "Failed to complete IOCB -- error status (%x).\n", 3029 vpmod->comp_status); 3030 rval = QLA_FUNCTION_FAILED; 3031 } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 3032 ql_dbg(ql_dbg_mbx, vha, 0x10bf, 3033 "Failed to complete IOCB -- completion status (%x).\n", 3034 le16_to_cpu(vpmod->comp_status)); 3035 rval = QLA_FUNCTION_FAILED; 3036 } else { 3037 /* EMPTY */ 3038 ql_dbg(ql_dbg_mbx, vha, 0x10c0, "Done %s.\n", __func__); 3039 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING); 3040 } 3041 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma); 3042 3043 return rval; 3044 } 3045 3046 /* 3047 * qla24xx_control_vp 3048 * Enable a virtual port for given host 3049 * 3050 * Input: 3051 * ha = adapter block pointer. 3052 * vhba = virtual adapter (unused) 3053 * index = index number for enabled VP 3054 * 3055 * Returns: 3056 * qla2xxx local function return status code. 3057 * 3058 * Context: 3059 * Kernel context. 3060 */ 3061 int 3062 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd) 3063 { 3064 int rval; 3065 int map, pos; 3066 struct vp_ctrl_entry_24xx *vce; 3067 dma_addr_t vce_dma; 3068 struct qla_hw_data *ha = vha->hw; 3069 int vp_index = vha->vp_idx; 3070 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3071 3072 ql_dbg(ql_dbg_mbx, vha, 0x10c1, 3073 "Entered %s enabling index %d.\n", __func__, vp_index); 3074 3075 if (vp_index == 0 || vp_index >= ha->max_npiv_vports) 3076 return QLA_PARAMETER_ERROR; 3077 3078 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma); 3079 if (!vce) { 3080 ql_log(ql_log_warn, vha, 0x10c2, 3081 "Failed to allocate VP control IOCB.\n"); 3082 return QLA_MEMORY_ALLOC_FAILED; 3083 } 3084 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx)); 3085 3086 vce->entry_type = VP_CTRL_IOCB_TYPE; 3087 vce->entry_count = 1; 3088 vce->command = cpu_to_le16(cmd); 3089 vce->vp_count = __constant_cpu_to_le16(1); 3090 3091 /* index map in firmware starts with 1; decrement index 3092 * this is ok as we never use index 0 3093 */ 3094 map = (vp_index - 1) / 8; 3095 pos = (vp_index - 1) & 7; 3096 mutex_lock(&ha->vport_lock); 3097 vce->vp_idx_map[map] |= 1 << pos; 3098 mutex_unlock(&ha->vport_lock); 3099 3100 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0); 3101 if (rval != QLA_SUCCESS) { 3102 ql_dbg(ql_dbg_mbx, vha, 0x10c3, 3103 "Failed to issue VP control IOCB (%x).\n", rval); 3104 } else if (vce->entry_status != 0) { 3105 ql_dbg(ql_dbg_mbx, vha, 0x10c4, 3106 "Failed to complete IOCB -- error status (%x).\n", 3107 vce->entry_status); 3108 rval = QLA_FUNCTION_FAILED; 3109 } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) { 3110 ql_dbg(ql_dbg_mbx, vha, 0x10c5, 3111 "Failed to complet IOCB -- completion status (%x).\n", 3112 le16_to_cpu(vce->comp_status)); 3113 rval = QLA_FUNCTION_FAILED; 3114 } else { 3115 ql_dbg(ql_dbg_mbx, vha, 0x10c6, "Done %s.\n", __func__); 3116 } 3117 3118 dma_pool_free(ha->s_dma_pool, vce, vce_dma); 3119 3120 return rval; 3121 } 3122 3123 /* 3124 * qla2x00_send_change_request 3125 * Receive or disable RSCN request from fabric controller 3126 * 3127 * Input: 3128 * ha = adapter block pointer 3129 * format = registration format: 3130 * 0 - Reserved 3131 * 1 - Fabric detected registration 3132 * 2 - N_port detected registration 3133 * 3 - Full registration 3134 * FF - clear registration 3135 * vp_idx = Virtual port index 3136 * 3137 * Returns: 3138 * qla2x00 local function return status code. 3139 * 3140 * Context: 3141 * Kernel Context 3142 */ 3143 3144 int 3145 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format, 3146 uint16_t vp_idx) 3147 { 3148 int rval; 3149 mbx_cmd_t mc; 3150 mbx_cmd_t *mcp = &mc; 3151 3152 ql_dbg(ql_dbg_mbx, vha, 0x10c7, "Entered %s.\n", __func__); 3153 3154 /* 3155 * This command is implicitly executed by firmware during login for the 3156 * physical hosts 3157 */ 3158 if (vp_idx == 0) 3159 return QLA_FUNCTION_FAILED; 3160 3161 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST; 3162 mcp->mb[1] = format; 3163 mcp->mb[9] = vp_idx; 3164 mcp->out_mb = MBX_9|MBX_1|MBX_0; 3165 mcp->in_mb = MBX_0|MBX_1; 3166 mcp->tov = MBX_TOV_SECONDS; 3167 mcp->flags = 0; 3168 rval = qla2x00_mailbox_command(vha, mcp); 3169 3170 if (rval == QLA_SUCCESS) { 3171 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 3172 rval = BIT_1; 3173 } 3174 } else 3175 rval = BIT_1; 3176 3177 return rval; 3178 } 3179 3180 int 3181 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 3182 uint32_t size) 3183 { 3184 int rval; 3185 mbx_cmd_t mc; 3186 mbx_cmd_t *mcp = &mc; 3187 3188 ql_dbg(ql_dbg_mbx, vha, 0x1009, "Entered %s.\n", __func__); 3189 3190 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) { 3191 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 3192 mcp->mb[8] = MSW(addr); 3193 mcp->out_mb = MBX_8|MBX_0; 3194 } else { 3195 mcp->mb[0] = MBC_DUMP_RISC_RAM; 3196 mcp->out_mb = MBX_0; 3197 } 3198 mcp->mb[1] = LSW(addr); 3199 mcp->mb[2] = MSW(req_dma); 3200 mcp->mb[3] = LSW(req_dma); 3201 mcp->mb[6] = MSW(MSD(req_dma)); 3202 mcp->mb[7] = LSW(MSD(req_dma)); 3203 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 3204 if (IS_FWI2_CAPABLE(vha->hw)) { 3205 mcp->mb[4] = MSW(size); 3206 mcp->mb[5] = LSW(size); 3207 mcp->out_mb |= MBX_5|MBX_4; 3208 } else { 3209 mcp->mb[4] = LSW(size); 3210 mcp->out_mb |= MBX_4; 3211 } 3212 3213 mcp->in_mb = MBX_0; 3214 mcp->tov = MBX_TOV_SECONDS; 3215 mcp->flags = 0; 3216 rval = qla2x00_mailbox_command(vha, mcp); 3217 3218 if (rval != QLA_SUCCESS) { 3219 ql_dbg(ql_dbg_mbx, vha, 0x1008, 3220 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3221 } else { 3222 ql_dbg(ql_dbg_mbx, vha, 0x1007, "Done %s.\n", __func__); 3223 } 3224 3225 return rval; 3226 } 3227 3228 /* 84XX Support **************************************************************/ 3229 3230 struct cs84xx_mgmt_cmd { 3231 union { 3232 struct verify_chip_entry_84xx req; 3233 struct verify_chip_rsp_84xx rsp; 3234 } p; 3235 }; 3236 3237 int 3238 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status) 3239 { 3240 int rval, retry; 3241 struct cs84xx_mgmt_cmd *mn; 3242 dma_addr_t mn_dma; 3243 uint16_t options; 3244 unsigned long flags; 3245 struct qla_hw_data *ha = vha->hw; 3246 3247 ql_dbg(ql_dbg_mbx, vha, 0x10c8, "Entered %s.\n", __func__); 3248 3249 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma); 3250 if (mn == NULL) { 3251 return QLA_MEMORY_ALLOC_FAILED; 3252 } 3253 3254 /* Force Update? */ 3255 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0; 3256 /* Diagnostic firmware? */ 3257 /* options |= MENLO_DIAG_FW; */ 3258 /* We update the firmware with only one data sequence. */ 3259 options |= VCO_END_OF_DATA; 3260 3261 do { 3262 retry = 0; 3263 memset(mn, 0, sizeof(*mn)); 3264 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE; 3265 mn->p.req.entry_count = 1; 3266 mn->p.req.options = cpu_to_le16(options); 3267 3268 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c, 3269 "Dump of Verify Request.\n"); 3270 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e, 3271 (uint8_t *)mn, sizeof(*mn)); 3272 3273 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120); 3274 if (rval != QLA_SUCCESS) { 3275 ql_dbg(ql_dbg_mbx, vha, 0x10cb, 3276 "Failed to issue verify IOCB (%x).\n", rval); 3277 goto verify_done; 3278 } 3279 3280 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110, 3281 "Dump of Verify Response.\n"); 3282 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118, 3283 (uint8_t *)mn, sizeof(*mn)); 3284 3285 status[0] = le16_to_cpu(mn->p.rsp.comp_status); 3286 status[1] = status[0] == CS_VCS_CHIP_FAILURE ? 3287 le16_to_cpu(mn->p.rsp.failure_code) : 0; 3288 ql_dbg(ql_dbg_mbx, vha, 0x10ce, 3289 "cs=%x fc=%x.\n", status[0], status[1]); 3290 3291 if (status[0] != CS_COMPLETE) { 3292 rval = QLA_FUNCTION_FAILED; 3293 if (!(options & VCO_DONT_UPDATE_FW)) { 3294 ql_dbg(ql_dbg_mbx, vha, 0x10cf, 3295 "Firmware update failed. Retrying " 3296 "without update firmware.\n"); 3297 options |= VCO_DONT_UPDATE_FW; 3298 options &= ~VCO_FORCE_UPDATE; 3299 retry = 1; 3300 } 3301 } else { 3302 ql_dbg(ql_dbg_mbx, vha, 0x10d0, 3303 "Firmware updated to %x.\n", 3304 le32_to_cpu(mn->p.rsp.fw_ver)); 3305 3306 /* NOTE: we only update OP firmware. */ 3307 spin_lock_irqsave(&ha->cs84xx->access_lock, flags); 3308 ha->cs84xx->op_fw_version = 3309 le32_to_cpu(mn->p.rsp.fw_ver); 3310 spin_unlock_irqrestore(&ha->cs84xx->access_lock, 3311 flags); 3312 } 3313 } while (retry); 3314 3315 verify_done: 3316 dma_pool_free(ha->s_dma_pool, mn, mn_dma); 3317 3318 if (rval != QLA_SUCCESS) { 3319 ql_dbg(ql_dbg_mbx, vha, 0x10d1, "Failed=%x.\n", rval); 3320 } else { 3321 ql_dbg(ql_dbg_mbx, vha, 0x10d2, "Done %s.\n", __func__); 3322 } 3323 3324 return rval; 3325 } 3326 3327 int 3328 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req) 3329 { 3330 int rval; 3331 unsigned long flags; 3332 mbx_cmd_t mc; 3333 mbx_cmd_t *mcp = &mc; 3334 struct device_reg_25xxmq __iomem *reg; 3335 struct qla_hw_data *ha = vha->hw; 3336 3337 ql_dbg(ql_dbg_mbx, vha, 0x10d3, "Entered %s.\n", __func__); 3338 3339 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 3340 mcp->mb[1] = req->options; 3341 mcp->mb[2] = MSW(LSD(req->dma)); 3342 mcp->mb[3] = LSW(LSD(req->dma)); 3343 mcp->mb[6] = MSW(MSD(req->dma)); 3344 mcp->mb[7] = LSW(MSD(req->dma)); 3345 mcp->mb[5] = req->length; 3346 if (req->rsp) 3347 mcp->mb[10] = req->rsp->id; 3348 mcp->mb[12] = req->qos; 3349 mcp->mb[11] = req->vp_idx; 3350 mcp->mb[13] = req->rid; 3351 if (IS_QLA83XX(ha)) 3352 mcp->mb[15] = 0; 3353 3354 reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) + 3355 QLA_QUE_PAGE * req->id); 3356 3357 mcp->mb[4] = req->id; 3358 /* que in ptr index */ 3359 mcp->mb[8] = 0; 3360 /* que out ptr index */ 3361 mcp->mb[9] = 0; 3362 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7| 3363 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3364 mcp->in_mb = MBX_0; 3365 mcp->flags = MBX_DMA_OUT; 3366 mcp->tov = MBX_TOV_SECONDS * 2; 3367 3368 if (IS_QLA81XX(ha) || IS_QLA83XX(ha)) 3369 mcp->in_mb |= MBX_1; 3370 if (IS_QLA83XX(ha)) { 3371 mcp->out_mb |= MBX_15; 3372 /* debug q create issue in SR-IOV */ 3373 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 3374 } 3375 3376 spin_lock_irqsave(&ha->hardware_lock, flags); 3377 if (!(req->options & BIT_0)) { 3378 WRT_REG_DWORD(®->req_q_in, 0); 3379 if (!IS_QLA83XX(ha)) 3380 WRT_REG_DWORD(®->req_q_out, 0); 3381 } 3382 req->req_q_in = ®->req_q_in; 3383 req->req_q_out = ®->req_q_out; 3384 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3385 3386 rval = qla2x00_mailbox_command(vha, mcp); 3387 if (rval != QLA_SUCCESS) { 3388 ql_dbg(ql_dbg_mbx, vha, 0x10d4, 3389 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3390 } else { 3391 ql_dbg(ql_dbg_mbx, vha, 0x10d5, "Done %s.\n", __func__); 3392 } 3393 3394 return rval; 3395 } 3396 3397 int 3398 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp) 3399 { 3400 int rval; 3401 unsigned long flags; 3402 mbx_cmd_t mc; 3403 mbx_cmd_t *mcp = &mc; 3404 struct device_reg_25xxmq __iomem *reg; 3405 struct qla_hw_data *ha = vha->hw; 3406 3407 ql_dbg(ql_dbg_mbx, vha, 0x10d6, "Entered %s.\n", __func__); 3408 3409 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 3410 mcp->mb[1] = rsp->options; 3411 mcp->mb[2] = MSW(LSD(rsp->dma)); 3412 mcp->mb[3] = LSW(LSD(rsp->dma)); 3413 mcp->mb[6] = MSW(MSD(rsp->dma)); 3414 mcp->mb[7] = LSW(MSD(rsp->dma)); 3415 mcp->mb[5] = rsp->length; 3416 mcp->mb[14] = rsp->msix->entry; 3417 mcp->mb[13] = rsp->rid; 3418 if (IS_QLA83XX(ha)) 3419 mcp->mb[15] = 0; 3420 3421 reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) + 3422 QLA_QUE_PAGE * rsp->id); 3423 3424 mcp->mb[4] = rsp->id; 3425 /* que in ptr index */ 3426 mcp->mb[8] = 0; 3427 /* que out ptr index */ 3428 mcp->mb[9] = 0; 3429 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7 3430 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3431 mcp->in_mb = MBX_0; 3432 mcp->flags = MBX_DMA_OUT; 3433 mcp->tov = MBX_TOV_SECONDS * 2; 3434 3435 if (IS_QLA81XX(ha)) { 3436 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 3437 mcp->in_mb |= MBX_1; 3438 } else if (IS_QLA83XX(ha)) { 3439 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10; 3440 mcp->in_mb |= MBX_1; 3441 /* debug q create issue in SR-IOV */ 3442 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 3443 } 3444 3445 spin_lock_irqsave(&ha->hardware_lock, flags); 3446 if (!(rsp->options & BIT_0)) { 3447 WRT_REG_DWORD(®->rsp_q_out, 0); 3448 if (!IS_QLA83XX(ha)) 3449 WRT_REG_DWORD(®->rsp_q_in, 0); 3450 } 3451 3452 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3453 3454 rval = qla2x00_mailbox_command(vha, mcp); 3455 if (rval != QLA_SUCCESS) { 3456 ql_dbg(ql_dbg_mbx, vha, 0x10d7, 3457 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3458 } else { 3459 ql_dbg(ql_dbg_mbx, vha, 0x10d8, "Done %s.\n", __func__); 3460 } 3461 3462 return rval; 3463 } 3464 3465 int 3466 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb) 3467 { 3468 int rval; 3469 mbx_cmd_t mc; 3470 mbx_cmd_t *mcp = &mc; 3471 3472 ql_dbg(ql_dbg_mbx, vha, 0x10d9, "Entered %s.\n", __func__); 3473 3474 mcp->mb[0] = MBC_IDC_ACK; 3475 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 3476 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3477 mcp->in_mb = MBX_0; 3478 mcp->tov = MBX_TOV_SECONDS; 3479 mcp->flags = 0; 3480 rval = qla2x00_mailbox_command(vha, mcp); 3481 3482 if (rval != QLA_SUCCESS) { 3483 ql_dbg(ql_dbg_mbx, vha, 0x10da, 3484 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3485 } else { 3486 ql_dbg(ql_dbg_mbx, vha, 0x10db, "Done %s.\n", __func__); 3487 } 3488 3489 return rval; 3490 } 3491 3492 int 3493 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size) 3494 { 3495 int rval; 3496 mbx_cmd_t mc; 3497 mbx_cmd_t *mcp = &mc; 3498 3499 ql_dbg(ql_dbg_mbx, vha, 0x10dc, "Entered %s.\n", __func__); 3500 3501 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw)) 3502 return QLA_FUNCTION_FAILED; 3503 3504 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 3505 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE; 3506 mcp->out_mb = MBX_1|MBX_0; 3507 mcp->in_mb = MBX_1|MBX_0; 3508 mcp->tov = MBX_TOV_SECONDS; 3509 mcp->flags = 0; 3510 rval = qla2x00_mailbox_command(vha, mcp); 3511 3512 if (rval != QLA_SUCCESS) { 3513 ql_dbg(ql_dbg_mbx, vha, 0x10dd, 3514 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3515 rval, mcp->mb[0], mcp->mb[1]); 3516 } else { 3517 ql_dbg(ql_dbg_mbx, vha, 0x10de, "Done %s.\n", __func__); 3518 *sector_size = mcp->mb[1]; 3519 } 3520 3521 return rval; 3522 } 3523 3524 int 3525 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable) 3526 { 3527 int rval; 3528 mbx_cmd_t mc; 3529 mbx_cmd_t *mcp = &mc; 3530 3531 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw)) 3532 return QLA_FUNCTION_FAILED; 3533 3534 ql_dbg(ql_dbg_mbx, vha, 0x10df, "Entered %s.\n", __func__); 3535 3536 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 3537 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE : 3538 FAC_OPT_CMD_WRITE_PROTECT; 3539 mcp->out_mb = MBX_1|MBX_0; 3540 mcp->in_mb = MBX_1|MBX_0; 3541 mcp->tov = MBX_TOV_SECONDS; 3542 mcp->flags = 0; 3543 rval = qla2x00_mailbox_command(vha, mcp); 3544 3545 if (rval != QLA_SUCCESS) { 3546 ql_dbg(ql_dbg_mbx, vha, 0x10e0, 3547 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3548 rval, mcp->mb[0], mcp->mb[1]); 3549 } else { 3550 ql_dbg(ql_dbg_mbx, vha, 0x10e1, "Done %s.\n", __func__); 3551 } 3552 3553 return rval; 3554 } 3555 3556 int 3557 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish) 3558 { 3559 int rval; 3560 mbx_cmd_t mc; 3561 mbx_cmd_t *mcp = &mc; 3562 3563 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw)) 3564 return QLA_FUNCTION_FAILED; 3565 3566 ql_dbg(ql_dbg_mbx, vha, 0x10e2, "Entered %s.\n", __func__); 3567 3568 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 3569 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR; 3570 mcp->mb[2] = LSW(start); 3571 mcp->mb[3] = MSW(start); 3572 mcp->mb[4] = LSW(finish); 3573 mcp->mb[5] = MSW(finish); 3574 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3575 mcp->in_mb = MBX_2|MBX_1|MBX_0; 3576 mcp->tov = MBX_TOV_SECONDS; 3577 mcp->flags = 0; 3578 rval = qla2x00_mailbox_command(vha, mcp); 3579 3580 if (rval != QLA_SUCCESS) { 3581 ql_dbg(ql_dbg_mbx, vha, 0x10e3, 3582 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 3583 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 3584 } else { 3585 ql_dbg(ql_dbg_mbx, vha, 0x10e4, "Done %s.\n", __func__); 3586 } 3587 3588 return rval; 3589 } 3590 3591 int 3592 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha) 3593 { 3594 int rval = 0; 3595 mbx_cmd_t mc; 3596 mbx_cmd_t *mcp = &mc; 3597 3598 ql_dbg(ql_dbg_mbx, vha, 0x10e5, "Entered %s.\n", __func__); 3599 3600 mcp->mb[0] = MBC_RESTART_MPI_FW; 3601 mcp->out_mb = MBX_0; 3602 mcp->in_mb = MBX_0|MBX_1; 3603 mcp->tov = MBX_TOV_SECONDS; 3604 mcp->flags = 0; 3605 rval = qla2x00_mailbox_command(vha, mcp); 3606 3607 if (rval != QLA_SUCCESS) { 3608 ql_dbg(ql_dbg_mbx, vha, 0x10e6, 3609 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3610 rval, mcp->mb[0], mcp->mb[1]); 3611 } else { 3612 ql_dbg(ql_dbg_mbx, vha, 0x10e7, "Done %s.\n", __func__); 3613 } 3614 3615 return rval; 3616 } 3617 3618 int 3619 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 3620 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 3621 { 3622 int rval; 3623 mbx_cmd_t mc; 3624 mbx_cmd_t *mcp = &mc; 3625 struct qla_hw_data *ha = vha->hw; 3626 3627 ql_dbg(ql_dbg_mbx, vha, 0x10e8, "Entered %s.\n", __func__); 3628 3629 if (!IS_FWI2_CAPABLE(ha)) 3630 return QLA_FUNCTION_FAILED; 3631 3632 if (len == 1) 3633 opt |= BIT_0; 3634 3635 mcp->mb[0] = MBC_READ_SFP; 3636 mcp->mb[1] = dev; 3637 mcp->mb[2] = MSW(sfp_dma); 3638 mcp->mb[3] = LSW(sfp_dma); 3639 mcp->mb[6] = MSW(MSD(sfp_dma)); 3640 mcp->mb[7] = LSW(MSD(sfp_dma)); 3641 mcp->mb[8] = len; 3642 mcp->mb[9] = off; 3643 mcp->mb[10] = opt; 3644 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 3645 mcp->in_mb = MBX_1|MBX_0; 3646 mcp->tov = MBX_TOV_SECONDS; 3647 mcp->flags = 0; 3648 rval = qla2x00_mailbox_command(vha, mcp); 3649 3650 if (opt & BIT_0) 3651 *sfp = mcp->mb[1]; 3652 3653 if (rval != QLA_SUCCESS) { 3654 ql_dbg(ql_dbg_mbx, vha, 0x10e9, 3655 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3656 } else { 3657 ql_dbg(ql_dbg_mbx, vha, 0x10ea, "Done %s.\n", __func__); 3658 } 3659 3660 return rval; 3661 } 3662 3663 int 3664 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 3665 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 3666 { 3667 int rval; 3668 mbx_cmd_t mc; 3669 mbx_cmd_t *mcp = &mc; 3670 struct qla_hw_data *ha = vha->hw; 3671 3672 ql_dbg(ql_dbg_mbx, vha, 0x10eb, "Entered %s.\n", __func__); 3673 3674 if (!IS_FWI2_CAPABLE(ha)) 3675 return QLA_FUNCTION_FAILED; 3676 3677 if (len == 1) 3678 opt |= BIT_0; 3679 3680 if (opt & BIT_0) 3681 len = *sfp; 3682 3683 mcp->mb[0] = MBC_WRITE_SFP; 3684 mcp->mb[1] = dev; 3685 mcp->mb[2] = MSW(sfp_dma); 3686 mcp->mb[3] = LSW(sfp_dma); 3687 mcp->mb[6] = MSW(MSD(sfp_dma)); 3688 mcp->mb[7] = LSW(MSD(sfp_dma)); 3689 mcp->mb[8] = len; 3690 mcp->mb[9] = off; 3691 mcp->mb[10] = opt; 3692 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 3693 mcp->in_mb = MBX_1|MBX_0; 3694 mcp->tov = MBX_TOV_SECONDS; 3695 mcp->flags = 0; 3696 rval = qla2x00_mailbox_command(vha, mcp); 3697 3698 if (rval != QLA_SUCCESS) { 3699 ql_dbg(ql_dbg_mbx, vha, 0x10ec, 3700 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3701 } else { 3702 ql_dbg(ql_dbg_mbx, vha, 0x10ed, "Done %s.\n", __func__); 3703 } 3704 3705 return rval; 3706 } 3707 3708 int 3709 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma, 3710 uint16_t size_in_bytes, uint16_t *actual_size) 3711 { 3712 int rval; 3713 mbx_cmd_t mc; 3714 mbx_cmd_t *mcp = &mc; 3715 3716 ql_dbg(ql_dbg_mbx, vha, 0x10ee, "Entered %s.\n", __func__); 3717 3718 if (!IS_CNA_CAPABLE(vha->hw)) 3719 return QLA_FUNCTION_FAILED; 3720 3721 mcp->mb[0] = MBC_GET_XGMAC_STATS; 3722 mcp->mb[2] = MSW(stats_dma); 3723 mcp->mb[3] = LSW(stats_dma); 3724 mcp->mb[6] = MSW(MSD(stats_dma)); 3725 mcp->mb[7] = LSW(MSD(stats_dma)); 3726 mcp->mb[8] = size_in_bytes >> 2; 3727 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 3728 mcp->in_mb = MBX_2|MBX_1|MBX_0; 3729 mcp->tov = MBX_TOV_SECONDS; 3730 mcp->flags = 0; 3731 rval = qla2x00_mailbox_command(vha, mcp); 3732 3733 if (rval != QLA_SUCCESS) { 3734 ql_dbg(ql_dbg_mbx, vha, 0x10ef, 3735 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 3736 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 3737 } else { 3738 ql_dbg(ql_dbg_mbx, vha, 0x10f0, "Done %s.\n", __func__); 3739 3740 3741 *actual_size = mcp->mb[2] << 2; 3742 } 3743 3744 return rval; 3745 } 3746 3747 int 3748 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma, 3749 uint16_t size) 3750 { 3751 int rval; 3752 mbx_cmd_t mc; 3753 mbx_cmd_t *mcp = &mc; 3754 3755 ql_dbg(ql_dbg_mbx, vha, 0x10f1, "Entered %s.\n", __func__); 3756 3757 if (!IS_CNA_CAPABLE(vha->hw)) 3758 return QLA_FUNCTION_FAILED; 3759 3760 mcp->mb[0] = MBC_GET_DCBX_PARAMS; 3761 mcp->mb[1] = 0; 3762 mcp->mb[2] = MSW(tlv_dma); 3763 mcp->mb[3] = LSW(tlv_dma); 3764 mcp->mb[6] = MSW(MSD(tlv_dma)); 3765 mcp->mb[7] = LSW(MSD(tlv_dma)); 3766 mcp->mb[8] = size; 3767 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 3768 mcp->in_mb = MBX_2|MBX_1|MBX_0; 3769 mcp->tov = MBX_TOV_SECONDS; 3770 mcp->flags = 0; 3771 rval = qla2x00_mailbox_command(vha, mcp); 3772 3773 if (rval != QLA_SUCCESS) { 3774 ql_dbg(ql_dbg_mbx, vha, 0x10f2, 3775 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 3776 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 3777 } else { 3778 ql_dbg(ql_dbg_mbx, vha, 0x10f3, "Done %s.\n", __func__); 3779 } 3780 3781 return rval; 3782 } 3783 3784 int 3785 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data) 3786 { 3787 int rval; 3788 mbx_cmd_t mc; 3789 mbx_cmd_t *mcp = &mc; 3790 3791 ql_dbg(ql_dbg_mbx, vha, 0x10f4, "Entered %s.\n", __func__); 3792 3793 if (!IS_FWI2_CAPABLE(vha->hw)) 3794 return QLA_FUNCTION_FAILED; 3795 3796 mcp->mb[0] = MBC_READ_RAM_EXTENDED; 3797 mcp->mb[1] = LSW(risc_addr); 3798 mcp->mb[8] = MSW(risc_addr); 3799 mcp->out_mb = MBX_8|MBX_1|MBX_0; 3800 mcp->in_mb = MBX_3|MBX_2|MBX_0; 3801 mcp->tov = 30; 3802 mcp->flags = 0; 3803 rval = qla2x00_mailbox_command(vha, mcp); 3804 if (rval != QLA_SUCCESS) { 3805 ql_dbg(ql_dbg_mbx, vha, 0x10f5, 3806 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3807 } else { 3808 ql_dbg(ql_dbg_mbx, vha, 0x10f6, "Done %s.\n", __func__); 3809 *data = mcp->mb[3] << 16 | mcp->mb[2]; 3810 } 3811 3812 return rval; 3813 } 3814 3815 int 3816 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 3817 uint16_t *mresp) 3818 { 3819 int rval; 3820 mbx_cmd_t mc; 3821 mbx_cmd_t *mcp = &mc; 3822 uint32_t iter_cnt = 0x1; 3823 3824 ql_dbg(ql_dbg_mbx, vha, 0x10f7, "Entered %s.\n", __func__); 3825 3826 memset(mcp->mb, 0 , sizeof(mcp->mb)); 3827 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK; 3828 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing 3829 3830 /* transfer count */ 3831 mcp->mb[10] = LSW(mreq->transfer_size); 3832 mcp->mb[11] = MSW(mreq->transfer_size); 3833 3834 /* send data address */ 3835 mcp->mb[14] = LSW(mreq->send_dma); 3836 mcp->mb[15] = MSW(mreq->send_dma); 3837 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 3838 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 3839 3840 /* receive data address */ 3841 mcp->mb[16] = LSW(mreq->rcv_dma); 3842 mcp->mb[17] = MSW(mreq->rcv_dma); 3843 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 3844 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 3845 3846 /* Iteration count */ 3847 mcp->mb[18] = LSW(iter_cnt); 3848 mcp->mb[19] = MSW(iter_cnt); 3849 3850 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| 3851 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 3852 if (IS_CNA_CAPABLE(vha->hw)) 3853 mcp->out_mb |= MBX_2; 3854 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; 3855 3856 mcp->buf_size = mreq->transfer_size; 3857 mcp->tov = MBX_TOV_SECONDS; 3858 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 3859 3860 rval = qla2x00_mailbox_command(vha, mcp); 3861 3862 if (rval != QLA_SUCCESS) { 3863 ql_dbg(ql_dbg_mbx, vha, 0x10f8, 3864 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x " 3865 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], 3866 mcp->mb[3], mcp->mb[18], mcp->mb[19]); 3867 } else { 3868 ql_dbg(ql_dbg_mbx, vha, 0x10f9, "Done %s.\n", __func__); 3869 } 3870 3871 /* Copy mailbox information */ 3872 memcpy( mresp, mcp->mb, 64); 3873 return rval; 3874 } 3875 3876 int 3877 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 3878 uint16_t *mresp) 3879 { 3880 int rval; 3881 mbx_cmd_t mc; 3882 mbx_cmd_t *mcp = &mc; 3883 struct qla_hw_data *ha = vha->hw; 3884 3885 ql_dbg(ql_dbg_mbx, vha, 0x10fa, "Entered %s.\n", __func__); 3886 3887 memset(mcp->mb, 0 , sizeof(mcp->mb)); 3888 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; 3889 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */ 3890 if (IS_CNA_CAPABLE(ha)) { 3891 mcp->mb[1] |= BIT_15; 3892 mcp->mb[2] = vha->fcoe_fcf_idx; 3893 } 3894 mcp->mb[16] = LSW(mreq->rcv_dma); 3895 mcp->mb[17] = MSW(mreq->rcv_dma); 3896 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 3897 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 3898 3899 mcp->mb[10] = LSW(mreq->transfer_size); 3900 3901 mcp->mb[14] = LSW(mreq->send_dma); 3902 mcp->mb[15] = MSW(mreq->send_dma); 3903 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 3904 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 3905 3906 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| 3907 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 3908 if (IS_CNA_CAPABLE(ha)) 3909 mcp->out_mb |= MBX_2; 3910 3911 mcp->in_mb = MBX_0; 3912 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || 3913 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 3914 mcp->in_mb |= MBX_1; 3915 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) 3916 mcp->in_mb |= MBX_3; 3917 3918 mcp->tov = MBX_TOV_SECONDS; 3919 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 3920 mcp->buf_size = mreq->transfer_size; 3921 3922 rval = qla2x00_mailbox_command(vha, mcp); 3923 3924 if (rval != QLA_SUCCESS) { 3925 ql_dbg(ql_dbg_mbx, vha, 0x10fb, 3926 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3927 rval, mcp->mb[0], mcp->mb[1]); 3928 } else { 3929 ql_dbg(ql_dbg_mbx, vha, 0x10fc, "Done %s.\n", __func__); 3930 } 3931 3932 /* Copy mailbox information */ 3933 memcpy(mresp, mcp->mb, 64); 3934 return rval; 3935 } 3936 3937 int 3938 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic) 3939 { 3940 int rval; 3941 mbx_cmd_t mc; 3942 mbx_cmd_t *mcp = &mc; 3943 3944 ql_dbg(ql_dbg_mbx, vha, 0x10fd, 3945 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic); 3946 3947 mcp->mb[0] = MBC_ISP84XX_RESET; 3948 mcp->mb[1] = enable_diagnostic; 3949 mcp->out_mb = MBX_1|MBX_0; 3950 mcp->in_mb = MBX_1|MBX_0; 3951 mcp->tov = MBX_TOV_SECONDS; 3952 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 3953 rval = qla2x00_mailbox_command(vha, mcp); 3954 3955 if (rval != QLA_SUCCESS) 3956 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval); 3957 else 3958 ql_dbg(ql_dbg_mbx, vha, 0x10ff, "Done %s.\n", __func__); 3959 3960 return rval; 3961 } 3962 3963 int 3964 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data) 3965 { 3966 int rval; 3967 mbx_cmd_t mc; 3968 mbx_cmd_t *mcp = &mc; 3969 3970 ql_dbg(ql_dbg_mbx, vha, 0x1100, "Entered %s.\n", __func__); 3971 3972 if (!IS_FWI2_CAPABLE(vha->hw)) 3973 return QLA_FUNCTION_FAILED; 3974 3975 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED; 3976 mcp->mb[1] = LSW(risc_addr); 3977 mcp->mb[2] = LSW(data); 3978 mcp->mb[3] = MSW(data); 3979 mcp->mb[8] = MSW(risc_addr); 3980 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0; 3981 mcp->in_mb = MBX_0; 3982 mcp->tov = 30; 3983 mcp->flags = 0; 3984 rval = qla2x00_mailbox_command(vha, mcp); 3985 if (rval != QLA_SUCCESS) { 3986 ql_dbg(ql_dbg_mbx, vha, 0x1101, 3987 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3988 } else { 3989 ql_dbg(ql_dbg_mbx, vha, 0x1102, "Done %s.\n", __func__); 3990 } 3991 3992 return rval; 3993 } 3994 3995 int 3996 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb) 3997 { 3998 int rval; 3999 uint32_t stat, timer; 4000 uint16_t mb0 = 0; 4001 struct qla_hw_data *ha = vha->hw; 4002 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 4003 4004 rval = QLA_SUCCESS; 4005 4006 ql_dbg(ql_dbg_mbx, vha, 0x1103, "Entered %s.\n", __func__); 4007 4008 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 4009 4010 /* Write the MBC data to the registers */ 4011 WRT_REG_WORD(®->mailbox0, MBC_WRITE_MPI_REGISTER); 4012 WRT_REG_WORD(®->mailbox1, mb[0]); 4013 WRT_REG_WORD(®->mailbox2, mb[1]); 4014 WRT_REG_WORD(®->mailbox3, mb[2]); 4015 WRT_REG_WORD(®->mailbox4, mb[3]); 4016 4017 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 4018 4019 /* Poll for MBC interrupt */ 4020 for (timer = 6000000; timer; timer--) { 4021 /* Check for pending interrupts. */ 4022 stat = RD_REG_DWORD(®->host_status); 4023 if (stat & HSRX_RISC_INT) { 4024 stat &= 0xff; 4025 4026 if (stat == 0x1 || stat == 0x2 || 4027 stat == 0x10 || stat == 0x11) { 4028 set_bit(MBX_INTERRUPT, 4029 &ha->mbx_cmd_flags); 4030 mb0 = RD_REG_WORD(®->mailbox0); 4031 WRT_REG_DWORD(®->hccr, 4032 HCCRX_CLR_RISC_INT); 4033 RD_REG_DWORD(®->hccr); 4034 break; 4035 } 4036 } 4037 udelay(5); 4038 } 4039 4040 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) 4041 rval = mb0 & MBS_MASK; 4042 else 4043 rval = QLA_FUNCTION_FAILED; 4044 4045 if (rval != QLA_SUCCESS) { 4046 ql_dbg(ql_dbg_mbx, vha, 0x1104, 4047 "Failed=%x mb[0]=%x.\n", rval, mb[0]); 4048 } else { 4049 ql_dbg(ql_dbg_mbx, vha, 0x1105, "Done %s.\n", __func__); 4050 } 4051 4052 return rval; 4053 } 4054 4055 int 4056 qla2x00_get_data_rate(scsi_qla_host_t *vha) 4057 { 4058 int rval; 4059 mbx_cmd_t mc; 4060 mbx_cmd_t *mcp = &mc; 4061 struct qla_hw_data *ha = vha->hw; 4062 4063 ql_dbg(ql_dbg_mbx, vha, 0x1106, "Entered %s.\n", __func__); 4064 4065 if (!IS_FWI2_CAPABLE(ha)) 4066 return QLA_FUNCTION_FAILED; 4067 4068 mcp->mb[0] = MBC_DATA_RATE; 4069 mcp->mb[1] = 0; 4070 mcp->out_mb = MBX_1|MBX_0; 4071 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4072 if (IS_QLA83XX(ha)) 4073 mcp->in_mb |= MBX_3; 4074 mcp->tov = MBX_TOV_SECONDS; 4075 mcp->flags = 0; 4076 rval = qla2x00_mailbox_command(vha, mcp); 4077 if (rval != QLA_SUCCESS) { 4078 ql_dbg(ql_dbg_mbx, vha, 0x1107, 4079 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4080 } else { 4081 ql_dbg(ql_dbg_mbx, vha, 0x1108, "Done %s.\n", __func__); 4082 if (mcp->mb[1] != 0x7) 4083 ha->link_data_rate = mcp->mb[1]; 4084 } 4085 4086 return rval; 4087 } 4088 4089 int 4090 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb) 4091 { 4092 int rval; 4093 mbx_cmd_t mc; 4094 mbx_cmd_t *mcp = &mc; 4095 struct qla_hw_data *ha = vha->hw; 4096 4097 ql_dbg(ql_dbg_mbx, vha, 0x1109, "Entered %s.\n", __func__); 4098 4099 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha)) 4100 return QLA_FUNCTION_FAILED; 4101 mcp->mb[0] = MBC_GET_PORT_CONFIG; 4102 mcp->out_mb = MBX_0; 4103 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4104 mcp->tov = MBX_TOV_SECONDS; 4105 mcp->flags = 0; 4106 4107 rval = qla2x00_mailbox_command(vha, mcp); 4108 4109 if (rval != QLA_SUCCESS) { 4110 ql_dbg(ql_dbg_mbx, vha, 0x110a, 4111 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4112 } else { 4113 /* Copy all bits to preserve original value */ 4114 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4); 4115 4116 ql_dbg(ql_dbg_mbx, vha, 0x110b, "Done %s.\n", __func__); 4117 } 4118 return rval; 4119 } 4120 4121 int 4122 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb) 4123 { 4124 int rval; 4125 mbx_cmd_t mc; 4126 mbx_cmd_t *mcp = &mc; 4127 4128 ql_dbg(ql_dbg_mbx, vha, 0x110c, "Entered %s.\n", __func__); 4129 4130 mcp->mb[0] = MBC_SET_PORT_CONFIG; 4131 /* Copy all bits to preserve original setting */ 4132 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4); 4133 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4134 mcp->in_mb = MBX_0; 4135 mcp->tov = MBX_TOV_SECONDS; 4136 mcp->flags = 0; 4137 rval = qla2x00_mailbox_command(vha, mcp); 4138 4139 if (rval != QLA_SUCCESS) { 4140 ql_dbg(ql_dbg_mbx, vha, 0x110d, 4141 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4142 } else 4143 ql_dbg(ql_dbg_mbx, vha, 0x110e, "Done %s.\n", __func__); 4144 4145 return rval; 4146 } 4147 4148 4149 int 4150 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority, 4151 uint16_t *mb) 4152 { 4153 int rval; 4154 mbx_cmd_t mc; 4155 mbx_cmd_t *mcp = &mc; 4156 struct qla_hw_data *ha = vha->hw; 4157 4158 ql_dbg(ql_dbg_mbx, vha, 0x110f, "Entered %s.\n", __func__); 4159 4160 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 4161 return QLA_FUNCTION_FAILED; 4162 4163 mcp->mb[0] = MBC_PORT_PARAMS; 4164 mcp->mb[1] = loop_id; 4165 if (ha->flags.fcp_prio_enabled) 4166 mcp->mb[2] = BIT_1; 4167 else 4168 mcp->mb[2] = BIT_2; 4169 mcp->mb[4] = priority & 0xf; 4170 mcp->mb[9] = vha->vp_idx; 4171 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4172 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 4173 mcp->tov = 30; 4174 mcp->flags = 0; 4175 rval = qla2x00_mailbox_command(vha, mcp); 4176 if (mb != NULL) { 4177 mb[0] = mcp->mb[0]; 4178 mb[1] = mcp->mb[1]; 4179 mb[3] = mcp->mb[3]; 4180 mb[4] = mcp->mb[4]; 4181 } 4182 4183 if (rval != QLA_SUCCESS) { 4184 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval); 4185 } else { 4186 ql_dbg(ql_dbg_mbx, vha, 0x10cc, "Done %s.\n", __func__); 4187 } 4188 4189 return rval; 4190 } 4191 4192 int 4193 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp, uint16_t *frac) 4194 { 4195 int rval; 4196 uint8_t byte; 4197 struct qla_hw_data *ha = vha->hw; 4198 4199 ql_dbg(ql_dbg_mbx, vha, 0x10ca, "Entered %s.\n", __func__); 4200 4201 /* Integer part */ 4202 rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x01, 1, BIT_13|BIT_0); 4203 if (rval != QLA_SUCCESS) { 4204 ql_dbg(ql_dbg_mbx, vha, 0x10c9, "Failed=%x.\n", rval); 4205 ha->flags.thermal_supported = 0; 4206 goto fail; 4207 } 4208 *temp = byte; 4209 4210 /* Fraction part */ 4211 rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x10, 1, BIT_13|BIT_0); 4212 if (rval != QLA_SUCCESS) { 4213 ql_dbg(ql_dbg_mbx, vha, 0x1019, "Failed=%x.\n", rval); 4214 ha->flags.thermal_supported = 0; 4215 goto fail; 4216 } 4217 *frac = (byte >> 6) * 25; 4218 4219 ql_dbg(ql_dbg_mbx, vha, 0x1018, "Done %s.\n", __func__); 4220 fail: 4221 return rval; 4222 } 4223 4224 int 4225 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha) 4226 { 4227 int rval; 4228 struct qla_hw_data *ha = vha->hw; 4229 mbx_cmd_t mc; 4230 mbx_cmd_t *mcp = &mc; 4231 4232 ql_dbg(ql_dbg_mbx, vha, 0x1017, "Entered %s.\n", __func__); 4233 4234 if (!IS_FWI2_CAPABLE(ha)) 4235 return QLA_FUNCTION_FAILED; 4236 4237 memset(mcp, 0, sizeof(mbx_cmd_t)); 4238 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 4239 mcp->mb[1] = 1; 4240 4241 mcp->out_mb = MBX_1|MBX_0; 4242 mcp->in_mb = MBX_0; 4243 mcp->tov = 30; 4244 mcp->flags = 0; 4245 4246 rval = qla2x00_mailbox_command(vha, mcp); 4247 if (rval != QLA_SUCCESS) { 4248 ql_dbg(ql_dbg_mbx, vha, 0x1016, 4249 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4250 } else { 4251 ql_dbg(ql_dbg_mbx, vha, 0x100e, "Done %s.\n", __func__); 4252 } 4253 4254 return rval; 4255 } 4256 4257 int 4258 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha) 4259 { 4260 int rval; 4261 struct qla_hw_data *ha = vha->hw; 4262 mbx_cmd_t mc; 4263 mbx_cmd_t *mcp = &mc; 4264 4265 ql_dbg(ql_dbg_mbx, vha, 0x100d, "Entered %s.\n", __func__); 4266 4267 if (!IS_QLA82XX(ha)) 4268 return QLA_FUNCTION_FAILED; 4269 4270 memset(mcp, 0, sizeof(mbx_cmd_t)); 4271 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 4272 mcp->mb[1] = 0; 4273 4274 mcp->out_mb = MBX_1|MBX_0; 4275 mcp->in_mb = MBX_0; 4276 mcp->tov = 30; 4277 mcp->flags = 0; 4278 4279 rval = qla2x00_mailbox_command(vha, mcp); 4280 if (rval != QLA_SUCCESS) { 4281 ql_dbg(ql_dbg_mbx, vha, 0x100c, 4282 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4283 } else { 4284 ql_dbg(ql_dbg_mbx, vha, 0x100b, "Done %s.\n", __func__); 4285 } 4286 4287 return rval; 4288 } 4289 4290 int 4291 qla82xx_md_get_template_size(scsi_qla_host_t *vha) 4292 { 4293 struct qla_hw_data *ha = vha->hw; 4294 mbx_cmd_t mc; 4295 mbx_cmd_t *mcp = &mc; 4296 int rval = QLA_FUNCTION_FAILED; 4297 4298 ql_dbg(ql_dbg_mbx, vha, 0x111f, "Entered %s.\n", __func__); 4299 4300 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4301 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4302 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4303 mcp->mb[2] = LSW(RQST_TMPLT_SIZE); 4304 mcp->mb[3] = MSW(RQST_TMPLT_SIZE); 4305 4306 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 4307 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| 4308 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4309 4310 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4311 mcp->tov = MBX_TOV_SECONDS; 4312 rval = qla2x00_mailbox_command(vha, mcp); 4313 4314 /* Always copy back return mailbox values. */ 4315 if (rval != QLA_SUCCESS) { 4316 ql_dbg(ql_dbg_mbx, vha, 0x1120, 4317 "mailbox command FAILED=0x%x, subcode=%x.\n", 4318 (mcp->mb[1] << 16) | mcp->mb[0], 4319 (mcp->mb[3] << 16) | mcp->mb[2]); 4320 } else { 4321 ql_dbg(ql_dbg_mbx, vha, 0x1121, "Done %s.\n", __func__); 4322 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]); 4323 if (!ha->md_template_size) { 4324 ql_dbg(ql_dbg_mbx, vha, 0x1122, 4325 "Null template size obtained.\n"); 4326 rval = QLA_FUNCTION_FAILED; 4327 } 4328 } 4329 return rval; 4330 } 4331 4332 int 4333 qla82xx_md_get_template(scsi_qla_host_t *vha) 4334 { 4335 struct qla_hw_data *ha = vha->hw; 4336 mbx_cmd_t mc; 4337 mbx_cmd_t *mcp = &mc; 4338 int rval = QLA_FUNCTION_FAILED; 4339 4340 ql_dbg(ql_dbg_mbx, vha, 0x1123, "Entered %s.\n", __func__); 4341 4342 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 4343 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 4344 if (!ha->md_tmplt_hdr) { 4345 ql_log(ql_log_warn, vha, 0x1124, 4346 "Unable to allocate memory for Minidump template.\n"); 4347 return rval; 4348 } 4349 4350 memset(mcp->mb, 0 , sizeof(mcp->mb)); 4351 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4352 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 4353 mcp->mb[2] = LSW(RQST_TMPLT); 4354 mcp->mb[3] = MSW(RQST_TMPLT); 4355 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma)); 4356 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma)); 4357 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma)); 4358 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma)); 4359 mcp->mb[8] = LSW(ha->md_template_size); 4360 mcp->mb[9] = MSW(ha->md_template_size); 4361 4362 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 4363 mcp->tov = MBX_TOV_SECONDS; 4364 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 4365 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4366 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 4367 rval = qla2x00_mailbox_command(vha, mcp); 4368 4369 if (rval != QLA_SUCCESS) { 4370 ql_dbg(ql_dbg_mbx, vha, 0x1125, 4371 "mailbox command FAILED=0x%x, subcode=%x.\n", 4372 ((mcp->mb[1] << 16) | mcp->mb[0]), 4373 ((mcp->mb[3] << 16) | mcp->mb[2])); 4374 } else 4375 ql_dbg(ql_dbg_mbx, vha, 0x1126, "Done %s.\n", __func__); 4376 return rval; 4377 } 4378 4379 int 4380 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 4381 { 4382 int rval; 4383 struct qla_hw_data *ha = vha->hw; 4384 mbx_cmd_t mc; 4385 mbx_cmd_t *mcp = &mc; 4386 4387 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 4388 return QLA_FUNCTION_FAILED; 4389 4390 ql_dbg(ql_dbg_mbx, vha, 0x1133, "Entered %s.\n", __func__); 4391 4392 memset(mcp, 0, sizeof(mbx_cmd_t)); 4393 mcp->mb[0] = MBC_SET_LED_CONFIG; 4394 mcp->mb[1] = led_cfg[0]; 4395 mcp->mb[2] = led_cfg[1]; 4396 if (IS_QLA8031(ha)) { 4397 mcp->mb[3] = led_cfg[2]; 4398 mcp->mb[4] = led_cfg[3]; 4399 mcp->mb[5] = led_cfg[4]; 4400 mcp->mb[6] = led_cfg[5]; 4401 } 4402 4403 mcp->out_mb = MBX_2|MBX_1|MBX_0; 4404 if (IS_QLA8031(ha)) 4405 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 4406 mcp->in_mb = MBX_0; 4407 mcp->tov = 30; 4408 mcp->flags = 0; 4409 4410 rval = qla2x00_mailbox_command(vha, mcp); 4411 if (rval != QLA_SUCCESS) { 4412 ql_dbg(ql_dbg_mbx, vha, 0x1134, 4413 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4414 } else { 4415 ql_dbg(ql_dbg_mbx, vha, 0x1135, "Done %s.\n", __func__); 4416 } 4417 4418 return rval; 4419 } 4420 4421 int 4422 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 4423 { 4424 int rval; 4425 struct qla_hw_data *ha = vha->hw; 4426 mbx_cmd_t mc; 4427 mbx_cmd_t *mcp = &mc; 4428 4429 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 4430 return QLA_FUNCTION_FAILED; 4431 4432 ql_dbg(ql_dbg_mbx, vha, 0x1136, "Entered %s.\n", __func__); 4433 4434 memset(mcp, 0, sizeof(mbx_cmd_t)); 4435 mcp->mb[0] = MBC_GET_LED_CONFIG; 4436 4437 mcp->out_mb = MBX_0; 4438 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4439 if (IS_QLA8031(ha)) 4440 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 4441 mcp->tov = 30; 4442 mcp->flags = 0; 4443 4444 rval = qla2x00_mailbox_command(vha, mcp); 4445 if (rval != QLA_SUCCESS) { 4446 ql_dbg(ql_dbg_mbx, vha, 0x1137, 4447 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4448 } else { 4449 led_cfg[0] = mcp->mb[1]; 4450 led_cfg[1] = mcp->mb[2]; 4451 if (IS_QLA8031(ha)) { 4452 led_cfg[2] = mcp->mb[3]; 4453 led_cfg[3] = mcp->mb[4]; 4454 led_cfg[4] = mcp->mb[5]; 4455 led_cfg[5] = mcp->mb[6]; 4456 } 4457 ql_dbg(ql_dbg_mbx, vha, 0x1138, "Done %s.\n", __func__); 4458 } 4459 4460 return rval; 4461 } 4462 4463 int 4464 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable) 4465 { 4466 int rval; 4467 struct qla_hw_data *ha = vha->hw; 4468 mbx_cmd_t mc; 4469 mbx_cmd_t *mcp = &mc; 4470 4471 if (!IS_QLA82XX(ha)) 4472 return QLA_FUNCTION_FAILED; 4473 4474 ql_dbg(ql_dbg_mbx, vha, 0x1127, 4475 "Entered %s.\n", __func__); 4476 4477 memset(mcp, 0, sizeof(mbx_cmd_t)); 4478 mcp->mb[0] = MBC_SET_LED_CONFIG; 4479 if (enable) 4480 mcp->mb[7] = 0xE; 4481 else 4482 mcp->mb[7] = 0xD; 4483 4484 mcp->out_mb = MBX_7|MBX_0; 4485 mcp->in_mb = MBX_0; 4486 mcp->tov = MBX_TOV_SECONDS; 4487 mcp->flags = 0; 4488 4489 rval = qla2x00_mailbox_command(vha, mcp); 4490 if (rval != QLA_SUCCESS) { 4491 ql_dbg(ql_dbg_mbx, vha, 0x1128, 4492 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4493 } else { 4494 ql_dbg(ql_dbg_mbx, vha, 0x1129, 4495 "Done %s.\n", __func__); 4496 } 4497 4498 return rval; 4499 } 4500 4501 int 4502 qla83xx_write_remote_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data) 4503 { 4504 int rval; 4505 struct qla_hw_data *ha = vha->hw; 4506 mbx_cmd_t mc; 4507 mbx_cmd_t *mcp = &mc; 4508 4509 if (!IS_QLA83XX(ha)) 4510 return QLA_FUNCTION_FAILED; 4511 4512 ql_dbg(ql_dbg_mbx, vha, 0x1130, "Entered %s.\n", __func__); 4513 4514 mcp->mb[0] = MBC_WRITE_REMOTE_REG; 4515 mcp->mb[1] = LSW(reg); 4516 mcp->mb[2] = MSW(reg); 4517 mcp->mb[3] = LSW(data); 4518 mcp->mb[4] = MSW(data); 4519 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4520 4521 mcp->in_mb = MBX_1|MBX_0; 4522 mcp->tov = MBX_TOV_SECONDS; 4523 mcp->flags = 0; 4524 rval = qla2x00_mailbox_command(vha, mcp); 4525 4526 if (rval != QLA_SUCCESS) { 4527 ql_dbg(ql_dbg_mbx, vha, 0x1131, 4528 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4529 } else { 4530 ql_dbg(ql_dbg_mbx, vha, 0x1132, 4531 "Done %s.\n", __func__); 4532 } 4533 4534 return rval; 4535 } 4536 4537 int 4538 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport) 4539 { 4540 int rval; 4541 struct qla_hw_data *ha = vha->hw; 4542 mbx_cmd_t mc; 4543 mbx_cmd_t *mcp = &mc; 4544 4545 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4546 ql_dbg(ql_dbg_mbx, vha, 0x113b, 4547 "Implicit LOGO Unsupported.\n"); 4548 return QLA_FUNCTION_FAILED; 4549 } 4550 4551 4552 ql_dbg(ql_dbg_mbx, vha, 0x113c, "Done %s.\n", __func__); 4553 4554 /* Perform Implicit LOGO. */ 4555 mcp->mb[0] = MBC_PORT_LOGOUT; 4556 mcp->mb[1] = fcport->loop_id; 4557 mcp->mb[10] = BIT_15; 4558 mcp->out_mb = MBX_10|MBX_1|MBX_0; 4559 mcp->in_mb = MBX_0; 4560 mcp->tov = MBX_TOV_SECONDS; 4561 mcp->flags = 0; 4562 rval = qla2x00_mailbox_command(vha, mcp); 4563 if (rval != QLA_SUCCESS) 4564 ql_dbg(ql_dbg_mbx, vha, 0x113d, 4565 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4566 else 4567 ql_dbg(ql_dbg_mbx, vha, 0x113e, "Done %s.\n", __func__); 4568 4569 return rval; 4570 } 4571 4572