1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_target.h" 9 10 #include <linux/delay.h> 11 #include <linux/gfp.h> 12 13 static struct mb_cmd_name { 14 uint16_t cmd; 15 const char *str; 16 } mb_str[] = { 17 {MBC_GET_PORT_DATABASE, "GPDB"}, 18 {MBC_GET_ID_LIST, "GIDList"}, 19 {MBC_GET_LINK_PRIV_STATS, "Stats"}, 20 {MBC_GET_RESOURCE_COUNTS, "ResCnt"}, 21 }; 22 23 static const char *mb_to_str(uint16_t cmd) 24 { 25 int i; 26 struct mb_cmd_name *e; 27 28 for (i = 0; i < ARRAY_SIZE(mb_str); i++) { 29 e = mb_str + i; 30 if (cmd == e->cmd) 31 return e->str; 32 } 33 return "unknown"; 34 } 35 36 static struct rom_cmd { 37 uint16_t cmd; 38 } rom_cmds[] = { 39 { MBC_LOAD_RAM }, 40 { MBC_EXECUTE_FIRMWARE }, 41 { MBC_READ_RAM_WORD }, 42 { MBC_MAILBOX_REGISTER_TEST }, 43 { MBC_VERIFY_CHECKSUM }, 44 { MBC_GET_FIRMWARE_VERSION }, 45 { MBC_LOAD_RISC_RAM }, 46 { MBC_DUMP_RISC_RAM }, 47 { MBC_LOAD_RISC_RAM_EXTENDED }, 48 { MBC_DUMP_RISC_RAM_EXTENDED }, 49 { MBC_WRITE_RAM_WORD_EXTENDED }, 50 { MBC_READ_RAM_EXTENDED }, 51 { MBC_GET_RESOURCE_COUNTS }, 52 { MBC_SET_FIRMWARE_OPTION }, 53 { MBC_MID_INITIALIZE_FIRMWARE }, 54 { MBC_GET_FIRMWARE_STATE }, 55 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT }, 56 { MBC_GET_RETRY_COUNT }, 57 { MBC_TRACE_CONTROL }, 58 { MBC_INITIALIZE_MULTIQ }, 59 { MBC_IOCB_COMMAND_A64 }, 60 { MBC_GET_ADAPTER_LOOP_ID }, 61 { MBC_READ_SFP }, 62 { MBC_SET_RNID_PARAMS }, 63 { MBC_GET_RNID_PARAMS }, 64 { MBC_GET_SET_ZIO_THRESHOLD }, 65 }; 66 67 static int is_rom_cmd(uint16_t cmd) 68 { 69 int i; 70 struct rom_cmd *wc; 71 72 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) { 73 wc = rom_cmds + i; 74 if (wc->cmd == cmd) 75 return 1; 76 } 77 78 return 0; 79 } 80 81 /* 82 * qla2x00_mailbox_command 83 * Issue mailbox command and waits for completion. 84 * 85 * Input: 86 * ha = adapter block pointer. 87 * mcp = driver internal mbx struct pointer. 88 * 89 * Output: 90 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data. 91 * 92 * Returns: 93 * 0 : QLA_SUCCESS = cmd performed success 94 * 1 : QLA_FUNCTION_FAILED (error encountered) 95 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered) 96 * 97 * Context: 98 * Kernel context. 99 */ 100 static int 101 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) 102 { 103 int rval, i; 104 unsigned long flags = 0; 105 device_reg_t *reg; 106 uint8_t abort_active; 107 uint8_t io_lock_on; 108 uint16_t command = 0; 109 uint16_t *iptr; 110 __le16 __iomem *optr; 111 uint32_t cnt; 112 uint32_t mboxes; 113 unsigned long wait_time; 114 struct qla_hw_data *ha = vha->hw; 115 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 116 u32 chip_reset; 117 118 119 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__); 120 121 if (ha->pdev->error_state == pci_channel_io_perm_failure) { 122 ql_log(ql_log_warn, vha, 0x1001, 123 "PCI channel failed permanently, exiting.\n"); 124 return QLA_FUNCTION_TIMEOUT; 125 } 126 127 if (vha->device_flags & DFLG_DEV_FAILED) { 128 ql_log(ql_log_warn, vha, 0x1002, 129 "Device in failed state, exiting.\n"); 130 return QLA_FUNCTION_TIMEOUT; 131 } 132 133 /* if PCI error, then avoid mbx processing.*/ 134 if (test_bit(PFLG_DISCONNECTED, &base_vha->dpc_flags) && 135 test_bit(UNLOADING, &base_vha->dpc_flags)) { 136 ql_log(ql_log_warn, vha, 0xd04e, 137 "PCI error, exiting.\n"); 138 return QLA_FUNCTION_TIMEOUT; 139 } 140 141 reg = ha->iobase; 142 io_lock_on = base_vha->flags.init_done; 143 144 rval = QLA_SUCCESS; 145 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 146 chip_reset = ha->chip_reset; 147 148 if (ha->flags.pci_channel_io_perm_failure) { 149 ql_log(ql_log_warn, vha, 0x1003, 150 "Perm failure on EEH timeout MBX, exiting.\n"); 151 return QLA_FUNCTION_TIMEOUT; 152 } 153 154 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 155 /* Setting Link-Down error */ 156 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 157 ql_log(ql_log_warn, vha, 0x1004, 158 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 159 return QLA_FUNCTION_TIMEOUT; 160 } 161 162 /* check if ISP abort is active and return cmd with timeout */ 163 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 164 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 165 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) && 166 !is_rom_cmd(mcp->mb[0])) { 167 ql_log(ql_log_info, vha, 0x1005, 168 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n", 169 mcp->mb[0]); 170 return QLA_FUNCTION_TIMEOUT; 171 } 172 173 atomic_inc(&ha->num_pend_mbx_stage1); 174 /* 175 * Wait for active mailbox commands to finish by waiting at most tov 176 * seconds. This is to serialize actual issuing of mailbox cmds during 177 * non ISP abort time. 178 */ 179 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) { 180 /* Timeout occurred. Return error. */ 181 ql_log(ql_log_warn, vha, 0xd035, 182 "Cmd access timeout, cmd=0x%x, Exiting.\n", 183 mcp->mb[0]); 184 atomic_dec(&ha->num_pend_mbx_stage1); 185 return QLA_FUNCTION_TIMEOUT; 186 } 187 atomic_dec(&ha->num_pend_mbx_stage1); 188 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset) { 189 rval = QLA_ABORTED; 190 goto premature_exit; 191 } 192 193 194 /* Save mailbox command for debug */ 195 ha->mcp = mcp; 196 197 ql_dbg(ql_dbg_mbx, vha, 0x1006, 198 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]); 199 200 spin_lock_irqsave(&ha->hardware_lock, flags); 201 202 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset || 203 ha->flags.mbox_busy) { 204 rval = QLA_ABORTED; 205 spin_unlock_irqrestore(&ha->hardware_lock, flags); 206 goto premature_exit; 207 } 208 ha->flags.mbox_busy = 1; 209 210 /* Load mailbox registers. */ 211 if (IS_P3P_TYPE(ha)) 212 optr = ®->isp82.mailbox_in[0]; 213 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) 214 optr = ®->isp24.mailbox0; 215 else 216 optr = MAILBOX_REG(ha, ®->isp, 0); 217 218 iptr = mcp->mb; 219 command = mcp->mb[0]; 220 mboxes = mcp->out_mb; 221 222 ql_dbg(ql_dbg_mbx, vha, 0x1111, 223 "Mailbox registers (OUT):\n"); 224 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 225 if (IS_QLA2200(ha) && cnt == 8) 226 optr = MAILBOX_REG(ha, ®->isp, 8); 227 if (mboxes & BIT_0) { 228 ql_dbg(ql_dbg_mbx, vha, 0x1112, 229 "mbox[%d]<-0x%04x\n", cnt, *iptr); 230 wrt_reg_word(optr, *iptr); 231 } 232 233 mboxes >>= 1; 234 optr++; 235 iptr++; 236 } 237 238 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117, 239 "I/O Address = %p.\n", optr); 240 241 /* Issue set host interrupt command to send cmd out. */ 242 ha->flags.mbox_int = 0; 243 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 244 245 /* Unlock mbx registers and wait for interrupt */ 246 ql_dbg(ql_dbg_mbx, vha, 0x100f, 247 "Going to unlock irq & waiting for interrupts. " 248 "jiffies=%lx.\n", jiffies); 249 250 /* Wait for mbx cmd completion until timeout */ 251 atomic_inc(&ha->num_pend_mbx_stage2); 252 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { 253 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 254 255 if (IS_P3P_TYPE(ha)) 256 wrt_reg_dword(®->isp82.hint, HINT_MBX_INT_PENDING); 257 else if (IS_FWI2_CAPABLE(ha)) 258 wrt_reg_dword(®->isp24.hccr, HCCRX_SET_HOST_INT); 259 else 260 wrt_reg_word(®->isp.hccr, HCCR_SET_HOST_INT); 261 spin_unlock_irqrestore(&ha->hardware_lock, flags); 262 263 wait_time = jiffies; 264 atomic_inc(&ha->num_pend_mbx_stage3); 265 if (!wait_for_completion_timeout(&ha->mbx_intr_comp, 266 mcp->tov * HZ)) { 267 if (chip_reset != ha->chip_reset) { 268 spin_lock_irqsave(&ha->hardware_lock, flags); 269 ha->flags.mbox_busy = 0; 270 spin_unlock_irqrestore(&ha->hardware_lock, 271 flags); 272 atomic_dec(&ha->num_pend_mbx_stage2); 273 atomic_dec(&ha->num_pend_mbx_stage3); 274 rval = QLA_ABORTED; 275 goto premature_exit; 276 } 277 ql_dbg(ql_dbg_mbx, vha, 0x117a, 278 "cmd=%x Timeout.\n", command); 279 spin_lock_irqsave(&ha->hardware_lock, flags); 280 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 281 spin_unlock_irqrestore(&ha->hardware_lock, flags); 282 283 } else if (ha->flags.purge_mbox || 284 chip_reset != ha->chip_reset) { 285 spin_lock_irqsave(&ha->hardware_lock, flags); 286 ha->flags.mbox_busy = 0; 287 spin_unlock_irqrestore(&ha->hardware_lock, flags); 288 atomic_dec(&ha->num_pend_mbx_stage2); 289 atomic_dec(&ha->num_pend_mbx_stage3); 290 rval = QLA_ABORTED; 291 goto premature_exit; 292 } 293 atomic_dec(&ha->num_pend_mbx_stage3); 294 295 if (time_after(jiffies, wait_time + 5 * HZ)) 296 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n", 297 command, jiffies_to_msecs(jiffies - wait_time)); 298 } else { 299 ql_dbg(ql_dbg_mbx, vha, 0x1011, 300 "Cmd=%x Polling Mode.\n", command); 301 302 if (IS_P3P_TYPE(ha)) { 303 if (rd_reg_dword(®->isp82.hint) & 304 HINT_MBX_INT_PENDING) { 305 ha->flags.mbox_busy = 0; 306 spin_unlock_irqrestore(&ha->hardware_lock, 307 flags); 308 atomic_dec(&ha->num_pend_mbx_stage2); 309 ql_dbg(ql_dbg_mbx, vha, 0x1012, 310 "Pending mailbox timeout, exiting.\n"); 311 rval = QLA_FUNCTION_TIMEOUT; 312 goto premature_exit; 313 } 314 wrt_reg_dword(®->isp82.hint, HINT_MBX_INT_PENDING); 315 } else if (IS_FWI2_CAPABLE(ha)) 316 wrt_reg_dword(®->isp24.hccr, HCCRX_SET_HOST_INT); 317 else 318 wrt_reg_word(®->isp.hccr, HCCR_SET_HOST_INT); 319 spin_unlock_irqrestore(&ha->hardware_lock, flags); 320 321 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */ 322 while (!ha->flags.mbox_int) { 323 if (ha->flags.purge_mbox || 324 chip_reset != ha->chip_reset) { 325 spin_lock_irqsave(&ha->hardware_lock, flags); 326 ha->flags.mbox_busy = 0; 327 spin_unlock_irqrestore(&ha->hardware_lock, 328 flags); 329 atomic_dec(&ha->num_pend_mbx_stage2); 330 rval = QLA_ABORTED; 331 goto premature_exit; 332 } 333 334 if (time_after(jiffies, wait_time)) 335 break; 336 337 /* 338 * Check if it's UNLOADING, cause we cannot poll in 339 * this case, or else a NULL pointer dereference 340 * is triggered. 341 */ 342 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) 343 return QLA_FUNCTION_TIMEOUT; 344 345 /* Check for pending interrupts. */ 346 qla2x00_poll(ha->rsp_q_map[0]); 347 348 if (!ha->flags.mbox_int && 349 !(IS_QLA2200(ha) && 350 command == MBC_LOAD_RISC_RAM_EXTENDED)) 351 msleep(10); 352 } /* while */ 353 ql_dbg(ql_dbg_mbx, vha, 0x1013, 354 "Waited %d sec.\n", 355 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ)); 356 } 357 atomic_dec(&ha->num_pend_mbx_stage2); 358 359 /* Check whether we timed out */ 360 if (ha->flags.mbox_int) { 361 uint16_t *iptr2; 362 363 ql_dbg(ql_dbg_mbx, vha, 0x1014, 364 "Cmd=%x completed.\n", command); 365 366 /* Got interrupt. Clear the flag. */ 367 ha->flags.mbox_int = 0; 368 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 369 370 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) { 371 spin_lock_irqsave(&ha->hardware_lock, flags); 372 ha->flags.mbox_busy = 0; 373 spin_unlock_irqrestore(&ha->hardware_lock, flags); 374 375 /* Setting Link-Down error */ 376 mcp->mb[0] = MBS_LINK_DOWN_ERROR; 377 ha->mcp = NULL; 378 rval = QLA_FUNCTION_FAILED; 379 ql_log(ql_log_warn, vha, 0xd048, 380 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung); 381 goto premature_exit; 382 } 383 384 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) { 385 ql_dbg(ql_dbg_mbx, vha, 0x11ff, 386 "mb_out[0] = %#x <> %#x\n", ha->mailbox_out[0], 387 MBS_COMMAND_COMPLETE); 388 rval = QLA_FUNCTION_FAILED; 389 } 390 391 /* Load return mailbox registers. */ 392 iptr2 = mcp->mb; 393 iptr = (uint16_t *)&ha->mailbox_out[0]; 394 mboxes = mcp->in_mb; 395 396 ql_dbg(ql_dbg_mbx, vha, 0x1113, 397 "Mailbox registers (IN):\n"); 398 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 399 if (mboxes & BIT_0) { 400 *iptr2 = *iptr; 401 ql_dbg(ql_dbg_mbx, vha, 0x1114, 402 "mbox[%d]->0x%04x\n", cnt, *iptr2); 403 } 404 405 mboxes >>= 1; 406 iptr2++; 407 iptr++; 408 } 409 } else { 410 411 uint16_t mb[8]; 412 uint32_t ictrl, host_status, hccr; 413 uint16_t w; 414 415 if (IS_FWI2_CAPABLE(ha)) { 416 mb[0] = rd_reg_word(®->isp24.mailbox0); 417 mb[1] = rd_reg_word(®->isp24.mailbox1); 418 mb[2] = rd_reg_word(®->isp24.mailbox2); 419 mb[3] = rd_reg_word(®->isp24.mailbox3); 420 mb[7] = rd_reg_word(®->isp24.mailbox7); 421 ictrl = rd_reg_dword(®->isp24.ictrl); 422 host_status = rd_reg_dword(®->isp24.host_status); 423 hccr = rd_reg_dword(®->isp24.hccr); 424 425 ql_log(ql_log_warn, vha, 0xd04c, 426 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx " 427 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n", 428 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3], 429 mb[7], host_status, hccr); 430 431 } else { 432 mb[0] = RD_MAILBOX_REG(ha, ®->isp, 0); 433 ictrl = rd_reg_word(®->isp.ictrl); 434 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119, 435 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx " 436 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]); 437 } 438 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019); 439 440 /* Capture FW dump only, if PCI device active */ 441 if (!pci_channel_offline(vha->hw->pdev)) { 442 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 443 if (w == 0xffff || ictrl == 0xffffffff || 444 (chip_reset != ha->chip_reset)) { 445 /* This is special case if there is unload 446 * of driver happening and if PCI device go 447 * into bad state due to PCI error condition 448 * then only PCI ERR flag would be set. 449 * we will do premature exit for above case. 450 */ 451 spin_lock_irqsave(&ha->hardware_lock, flags); 452 ha->flags.mbox_busy = 0; 453 spin_unlock_irqrestore(&ha->hardware_lock, 454 flags); 455 rval = QLA_FUNCTION_TIMEOUT; 456 goto premature_exit; 457 } 458 459 /* Attempt to capture firmware dump for further 460 * anallysis of the current formware state. we do not 461 * need to do this if we are intentionally generating 462 * a dump 463 */ 464 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) 465 qla2xxx_dump_fw(vha); 466 rval = QLA_FUNCTION_TIMEOUT; 467 } 468 } 469 spin_lock_irqsave(&ha->hardware_lock, flags); 470 ha->flags.mbox_busy = 0; 471 spin_unlock_irqrestore(&ha->hardware_lock, flags); 472 473 /* Clean up */ 474 ha->mcp = NULL; 475 476 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) { 477 ql_dbg(ql_dbg_mbx, vha, 0x101a, 478 "Checking for additional resp interrupt.\n"); 479 480 /* polling mode for non isp_abort commands. */ 481 qla2x00_poll(ha->rsp_q_map[0]); 482 } 483 484 if (rval == QLA_FUNCTION_TIMEOUT && 485 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) { 486 if (!io_lock_on || (mcp->flags & IOCTL_CMD) || 487 ha->flags.eeh_busy) { 488 /* not in dpc. schedule it for dpc to take over. */ 489 ql_dbg(ql_dbg_mbx, vha, 0x101b, 490 "Timeout, schedule isp_abort_needed.\n"); 491 492 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 493 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 494 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 495 if (IS_QLA82XX(ha)) { 496 ql_dbg(ql_dbg_mbx, vha, 0x112a, 497 "disabling pause transmit on port " 498 "0 & 1.\n"); 499 qla82xx_wr_32(ha, 500 QLA82XX_CRB_NIU + 0x98, 501 CRB_NIU_XG_PAUSE_CTL_P0| 502 CRB_NIU_XG_PAUSE_CTL_P1); 503 } 504 ql_log(ql_log_info, base_vha, 0x101c, 505 "Mailbox cmd timeout occurred, cmd=0x%x, " 506 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP " 507 "abort.\n", command, mcp->mb[0], 508 ha->flags.eeh_busy); 509 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 510 qla2xxx_wake_dpc(vha); 511 } 512 } else if (current == ha->dpc_thread) { 513 /* call abort directly since we are in the DPC thread */ 514 ql_dbg(ql_dbg_mbx, vha, 0x101d, 515 "Timeout, calling abort_isp.\n"); 516 517 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) && 518 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 519 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 520 if (IS_QLA82XX(ha)) { 521 ql_dbg(ql_dbg_mbx, vha, 0x112b, 522 "disabling pause transmit on port " 523 "0 & 1.\n"); 524 qla82xx_wr_32(ha, 525 QLA82XX_CRB_NIU + 0x98, 526 CRB_NIU_XG_PAUSE_CTL_P0| 527 CRB_NIU_XG_PAUSE_CTL_P1); 528 } 529 ql_log(ql_log_info, base_vha, 0x101e, 530 "Mailbox cmd timeout occurred, cmd=0x%x, " 531 "mb[0]=0x%x. Scheduling ISP abort ", 532 command, mcp->mb[0]); 533 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 534 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 535 /* Allow next mbx cmd to come in. */ 536 complete(&ha->mbx_cmd_comp); 537 if (ha->isp_ops->abort_isp(vha)) { 538 /* Failed. retry later. */ 539 set_bit(ISP_ABORT_NEEDED, 540 &vha->dpc_flags); 541 } 542 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags); 543 ql_dbg(ql_dbg_mbx, vha, 0x101f, 544 "Finished abort_isp.\n"); 545 goto mbx_done; 546 } 547 } 548 } 549 550 premature_exit: 551 /* Allow next mbx cmd to come in. */ 552 complete(&ha->mbx_cmd_comp); 553 554 mbx_done: 555 if (rval == QLA_ABORTED) { 556 ql_log(ql_log_info, vha, 0xd035, 557 "Chip Reset in progress. Purging Mbox cmd=0x%x.\n", 558 mcp->mb[0]); 559 } else if (rval) { 560 if (ql2xextended_error_logging & (ql_dbg_disc|ql_dbg_mbx)) { 561 pr_warn("%s [%s]-%04x:%ld: **** Failed=%x", QL_MSGHDR, 562 dev_name(&ha->pdev->dev), 0x1020+0x800, 563 vha->host_no, rval); 564 mboxes = mcp->in_mb; 565 cnt = 4; 566 for (i = 0; i < ha->mbx_count && cnt; i++, mboxes >>= 1) 567 if (mboxes & BIT_0) { 568 printk(" mb[%u]=%x", i, mcp->mb[i]); 569 cnt--; 570 } 571 pr_warn(" cmd=%x ****\n", command); 572 } 573 if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) { 574 ql_dbg(ql_dbg_mbx, vha, 0x1198, 575 "host_status=%#x intr_ctrl=%#x intr_status=%#x\n", 576 rd_reg_dword(®->isp24.host_status), 577 rd_reg_dword(®->isp24.ictrl), 578 rd_reg_dword(®->isp24.istatus)); 579 } else { 580 ql_dbg(ql_dbg_mbx, vha, 0x1206, 581 "ctrl_status=%#x ictrl=%#x istatus=%#x\n", 582 rd_reg_word(®->isp.ctrl_status), 583 rd_reg_word(®->isp.ictrl), 584 rd_reg_word(®->isp.istatus)); 585 } 586 } else { 587 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__); 588 } 589 590 return rval; 591 } 592 593 int 594 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr, 595 uint32_t risc_code_size) 596 { 597 int rval; 598 struct qla_hw_data *ha = vha->hw; 599 mbx_cmd_t mc; 600 mbx_cmd_t *mcp = &mc; 601 602 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022, 603 "Entered %s.\n", __func__); 604 605 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) { 606 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; 607 mcp->mb[8] = MSW(risc_addr); 608 mcp->out_mb = MBX_8|MBX_0; 609 } else { 610 mcp->mb[0] = MBC_LOAD_RISC_RAM; 611 mcp->out_mb = MBX_0; 612 } 613 mcp->mb[1] = LSW(risc_addr); 614 mcp->mb[2] = MSW(req_dma); 615 mcp->mb[3] = LSW(req_dma); 616 mcp->mb[6] = MSW(MSD(req_dma)); 617 mcp->mb[7] = LSW(MSD(req_dma)); 618 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 619 if (IS_FWI2_CAPABLE(ha)) { 620 mcp->mb[4] = MSW(risc_code_size); 621 mcp->mb[5] = LSW(risc_code_size); 622 mcp->out_mb |= MBX_5|MBX_4; 623 } else { 624 mcp->mb[4] = LSW(risc_code_size); 625 mcp->out_mb |= MBX_4; 626 } 627 628 mcp->in_mb = MBX_1|MBX_0; 629 mcp->tov = MBX_TOV_SECONDS; 630 mcp->flags = 0; 631 rval = qla2x00_mailbox_command(vha, mcp); 632 633 if (rval != QLA_SUCCESS) { 634 ql_dbg(ql_dbg_mbx, vha, 0x1023, 635 "Failed=%x mb[0]=%x mb[1]=%x.\n", 636 rval, mcp->mb[0], mcp->mb[1]); 637 } else { 638 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024, 639 "Done %s.\n", __func__); 640 } 641 642 return rval; 643 } 644 645 #define NVME_ENABLE_FLAG BIT_3 646 647 /* 648 * qla2x00_execute_fw 649 * Start adapter firmware. 650 * 651 * Input: 652 * ha = adapter block pointer. 653 * TARGET_QUEUE_LOCK must be released. 654 * ADAPTER_STATE_LOCK must be released. 655 * 656 * Returns: 657 * qla2x00 local function return status code. 658 * 659 * Context: 660 * Kernel context. 661 */ 662 int 663 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr) 664 { 665 int rval; 666 struct qla_hw_data *ha = vha->hw; 667 mbx_cmd_t mc; 668 mbx_cmd_t *mcp = &mc; 669 u8 semaphore = 0; 670 #define EXE_FW_FORCE_SEMAPHORE BIT_7 671 u8 retry = 3; 672 673 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025, 674 "Entered %s.\n", __func__); 675 676 again: 677 mcp->mb[0] = MBC_EXECUTE_FIRMWARE; 678 mcp->out_mb = MBX_0; 679 mcp->in_mb = MBX_0; 680 if (IS_FWI2_CAPABLE(ha)) { 681 mcp->mb[1] = MSW(risc_addr); 682 mcp->mb[2] = LSW(risc_addr); 683 mcp->mb[3] = 0; 684 mcp->mb[4] = 0; 685 mcp->mb[11] = 0; 686 687 /* Enable BPM? */ 688 if (ha->flags.lr_detected) { 689 mcp->mb[4] = BIT_0; 690 if (IS_BPM_RANGE_CAPABLE(ha)) 691 mcp->mb[4] |= 692 ha->lr_distance << LR_DIST_FW_POS; 693 } 694 695 if (ql2xnvmeenable && (IS_QLA27XX(ha) || IS_QLA28XX(ha))) 696 mcp->mb[4] |= NVME_ENABLE_FLAG; 697 698 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 699 struct nvram_81xx *nv = ha->nvram; 700 /* set minimum speed if specified in nvram */ 701 if (nv->min_supported_speed >= 2 && 702 nv->min_supported_speed <= 5) { 703 mcp->mb[4] |= BIT_4; 704 mcp->mb[11] |= nv->min_supported_speed & 0xF; 705 mcp->out_mb |= MBX_11; 706 mcp->in_mb |= BIT_5; 707 vha->min_supported_speed = 708 nv->min_supported_speed; 709 } 710 } 711 712 if (ha->flags.exlogins_enabled) 713 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN; 714 715 if (ha->flags.exchoffld_enabled) 716 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD; 717 718 if (semaphore) 719 mcp->mb[11] |= EXE_FW_FORCE_SEMAPHORE; 720 721 mcp->out_mb |= MBX_4 | MBX_3 | MBX_2 | MBX_1 | MBX_11; 722 mcp->in_mb |= MBX_3 | MBX_2 | MBX_1; 723 } else { 724 mcp->mb[1] = LSW(risc_addr); 725 mcp->out_mb |= MBX_1; 726 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 727 mcp->mb[2] = 0; 728 mcp->out_mb |= MBX_2; 729 } 730 } 731 732 mcp->tov = MBX_TOV_SECONDS; 733 mcp->flags = 0; 734 rval = qla2x00_mailbox_command(vha, mcp); 735 736 if (rval != QLA_SUCCESS) { 737 if (IS_QLA28XX(ha) && rval == QLA_COMMAND_ERROR && 738 mcp->mb[1] == 0x27 && retry) { 739 semaphore = 1; 740 retry--; 741 ql_dbg(ql_dbg_async, vha, 0x1026, 742 "Exe FW: force semaphore.\n"); 743 goto again; 744 } 745 746 ql_dbg(ql_dbg_mbx, vha, 0x1026, 747 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 748 return rval; 749 } 750 751 if (!IS_FWI2_CAPABLE(ha)) 752 goto done; 753 754 ha->fw_ability_mask = mcp->mb[3] << 16 | mcp->mb[2]; 755 ql_dbg(ql_dbg_mbx, vha, 0x119a, 756 "fw_ability_mask=%x.\n", ha->fw_ability_mask); 757 ql_dbg(ql_dbg_mbx, vha, 0x1027, "exchanges=%x.\n", mcp->mb[1]); 758 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 759 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1); 760 ql_dbg(ql_dbg_mbx, vha, 0x119b, "max_supported_speed=%s.\n", 761 ha->max_supported_speed == 0 ? "16Gps" : 762 ha->max_supported_speed == 1 ? "32Gps" : 763 ha->max_supported_speed == 2 ? "64Gps" : "unknown"); 764 if (vha->min_supported_speed) { 765 ha->min_supported_speed = mcp->mb[5] & 766 (BIT_0 | BIT_1 | BIT_2); 767 ql_dbg(ql_dbg_mbx, vha, 0x119c, 768 "min_supported_speed=%s.\n", 769 ha->min_supported_speed == 6 ? "64Gps" : 770 ha->min_supported_speed == 5 ? "32Gps" : 771 ha->min_supported_speed == 4 ? "16Gps" : 772 ha->min_supported_speed == 3 ? "8Gps" : 773 ha->min_supported_speed == 2 ? "4Gps" : "unknown"); 774 } 775 } 776 777 done: 778 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028, 779 "Done %s.\n", __func__); 780 781 return rval; 782 } 783 784 /* 785 * qla_get_exlogin_status 786 * Get extended login status 787 * uses the memory offload control/status Mailbox 788 * 789 * Input: 790 * ha: adapter state pointer. 791 * fwopt: firmware options 792 * 793 * Returns: 794 * qla2x00 local function status 795 * 796 * Context: 797 * Kernel context. 798 */ 799 #define FETCH_XLOGINS_STAT 0x8 800 int 801 qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz, 802 uint16_t *ex_logins_cnt) 803 { 804 int rval; 805 mbx_cmd_t mc; 806 mbx_cmd_t *mcp = &mc; 807 808 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f, 809 "Entered %s\n", __func__); 810 811 memset(mcp->mb, 0 , sizeof(mcp->mb)); 812 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 813 mcp->mb[1] = FETCH_XLOGINS_STAT; 814 mcp->out_mb = MBX_1|MBX_0; 815 mcp->in_mb = MBX_10|MBX_4|MBX_0; 816 mcp->tov = MBX_TOV_SECONDS; 817 mcp->flags = 0; 818 819 rval = qla2x00_mailbox_command(vha, mcp); 820 if (rval != QLA_SUCCESS) { 821 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval); 822 } else { 823 *buf_sz = mcp->mb[4]; 824 *ex_logins_cnt = mcp->mb[10]; 825 826 ql_log(ql_log_info, vha, 0x1190, 827 "buffer size 0x%x, exchange login count=%d\n", 828 mcp->mb[4], mcp->mb[10]); 829 830 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116, 831 "Done %s.\n", __func__); 832 } 833 834 return rval; 835 } 836 837 /* 838 * qla_set_exlogin_mem_cfg 839 * set extended login memory configuration 840 * Mbx needs to be issues before init_cb is set 841 * 842 * Input: 843 * ha: adapter state pointer. 844 * buffer: buffer pointer 845 * phys_addr: physical address of buffer 846 * size: size of buffer 847 * TARGET_QUEUE_LOCK must be released 848 * ADAPTER_STATE_LOCK must be release 849 * 850 * Returns: 851 * qla2x00 local funxtion status code. 852 * 853 * Context: 854 * Kernel context. 855 */ 856 #define CONFIG_XLOGINS_MEM 0x3 857 int 858 qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr) 859 { 860 int rval; 861 mbx_cmd_t mc; 862 mbx_cmd_t *mcp = &mc; 863 struct qla_hw_data *ha = vha->hw; 864 865 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a, 866 "Entered %s.\n", __func__); 867 868 memset(mcp->mb, 0 , sizeof(mcp->mb)); 869 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 870 mcp->mb[1] = CONFIG_XLOGINS_MEM; 871 mcp->mb[2] = MSW(phys_addr); 872 mcp->mb[3] = LSW(phys_addr); 873 mcp->mb[6] = MSW(MSD(phys_addr)); 874 mcp->mb[7] = LSW(MSD(phys_addr)); 875 mcp->mb[8] = MSW(ha->exlogin_size); 876 mcp->mb[9] = LSW(ha->exlogin_size); 877 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 878 mcp->in_mb = MBX_11|MBX_0; 879 mcp->tov = MBX_TOV_SECONDS; 880 mcp->flags = 0; 881 rval = qla2x00_mailbox_command(vha, mcp); 882 if (rval != QLA_SUCCESS) { 883 /*EMPTY*/ 884 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval); 885 } else { 886 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c, 887 "Done %s.\n", __func__); 888 } 889 890 return rval; 891 } 892 893 /* 894 * qla_get_exchoffld_status 895 * Get exchange offload status 896 * uses the memory offload control/status Mailbox 897 * 898 * Input: 899 * ha: adapter state pointer. 900 * fwopt: firmware options 901 * 902 * Returns: 903 * qla2x00 local function status 904 * 905 * Context: 906 * Kernel context. 907 */ 908 #define FETCH_XCHOFFLD_STAT 0x2 909 int 910 qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz, 911 uint16_t *ex_logins_cnt) 912 { 913 int rval; 914 mbx_cmd_t mc; 915 mbx_cmd_t *mcp = &mc; 916 917 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019, 918 "Entered %s\n", __func__); 919 920 memset(mcp->mb, 0 , sizeof(mcp->mb)); 921 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 922 mcp->mb[1] = FETCH_XCHOFFLD_STAT; 923 mcp->out_mb = MBX_1|MBX_0; 924 mcp->in_mb = MBX_10|MBX_4|MBX_0; 925 mcp->tov = MBX_TOV_SECONDS; 926 mcp->flags = 0; 927 928 rval = qla2x00_mailbox_command(vha, mcp); 929 if (rval != QLA_SUCCESS) { 930 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval); 931 } else { 932 *buf_sz = mcp->mb[4]; 933 *ex_logins_cnt = mcp->mb[10]; 934 935 ql_log(ql_log_info, vha, 0x118e, 936 "buffer size 0x%x, exchange offload count=%d\n", 937 mcp->mb[4], mcp->mb[10]); 938 939 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156, 940 "Done %s.\n", __func__); 941 } 942 943 return rval; 944 } 945 946 /* 947 * qla_set_exchoffld_mem_cfg 948 * Set exchange offload memory configuration 949 * Mbx needs to be issues before init_cb is set 950 * 951 * Input: 952 * ha: adapter state pointer. 953 * buffer: buffer pointer 954 * phys_addr: physical address of buffer 955 * size: size of buffer 956 * TARGET_QUEUE_LOCK must be released 957 * ADAPTER_STATE_LOCK must be release 958 * 959 * Returns: 960 * qla2x00 local funxtion status code. 961 * 962 * Context: 963 * Kernel context. 964 */ 965 #define CONFIG_XCHOFFLD_MEM 0x3 966 int 967 qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha) 968 { 969 int rval; 970 mbx_cmd_t mc; 971 mbx_cmd_t *mcp = &mc; 972 struct qla_hw_data *ha = vha->hw; 973 974 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157, 975 "Entered %s.\n", __func__); 976 977 memset(mcp->mb, 0 , sizeof(mcp->mb)); 978 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT; 979 mcp->mb[1] = CONFIG_XCHOFFLD_MEM; 980 mcp->mb[2] = MSW(ha->exchoffld_buf_dma); 981 mcp->mb[3] = LSW(ha->exchoffld_buf_dma); 982 mcp->mb[6] = MSW(MSD(ha->exchoffld_buf_dma)); 983 mcp->mb[7] = LSW(MSD(ha->exchoffld_buf_dma)); 984 mcp->mb[8] = MSW(ha->exchoffld_size); 985 mcp->mb[9] = LSW(ha->exchoffld_size); 986 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 987 mcp->in_mb = MBX_11|MBX_0; 988 mcp->tov = MBX_TOV_SECONDS; 989 mcp->flags = 0; 990 rval = qla2x00_mailbox_command(vha, mcp); 991 if (rval != QLA_SUCCESS) { 992 /*EMPTY*/ 993 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval); 994 } else { 995 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192, 996 "Done %s.\n", __func__); 997 } 998 999 return rval; 1000 } 1001 1002 /* 1003 * qla2x00_get_fw_version 1004 * Get firmware version. 1005 * 1006 * Input: 1007 * ha: adapter state pointer. 1008 * major: pointer for major number. 1009 * minor: pointer for minor number. 1010 * subminor: pointer for subminor number. 1011 * 1012 * Returns: 1013 * qla2x00 local function return status code. 1014 * 1015 * Context: 1016 * Kernel context. 1017 */ 1018 int 1019 qla2x00_get_fw_version(scsi_qla_host_t *vha) 1020 { 1021 int rval; 1022 mbx_cmd_t mc; 1023 mbx_cmd_t *mcp = &mc; 1024 struct qla_hw_data *ha = vha->hw; 1025 1026 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029, 1027 "Entered %s.\n", __func__); 1028 1029 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION; 1030 mcp->out_mb = MBX_0; 1031 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1032 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha)) 1033 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8; 1034 if (IS_FWI2_CAPABLE(ha)) 1035 mcp->in_mb |= MBX_17|MBX_16|MBX_15; 1036 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1037 mcp->in_mb |= 1038 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18| 1039 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7; 1040 1041 mcp->flags = 0; 1042 mcp->tov = MBX_TOV_SECONDS; 1043 rval = qla2x00_mailbox_command(vha, mcp); 1044 if (rval != QLA_SUCCESS) 1045 goto failed; 1046 1047 /* Return mailbox data. */ 1048 ha->fw_major_version = mcp->mb[1]; 1049 ha->fw_minor_version = mcp->mb[2]; 1050 ha->fw_subminor_version = mcp->mb[3]; 1051 ha->fw_attributes = mcp->mb[6]; 1052 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw)) 1053 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */ 1054 else 1055 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4]; 1056 1057 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) { 1058 ha->mpi_version[0] = mcp->mb[10] & 0xff; 1059 ha->mpi_version[1] = mcp->mb[11] >> 8; 1060 ha->mpi_version[2] = mcp->mb[11] & 0xff; 1061 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13]; 1062 ha->phy_version[0] = mcp->mb[8] & 0xff; 1063 ha->phy_version[1] = mcp->mb[9] >> 8; 1064 ha->phy_version[2] = mcp->mb[9] & 0xff; 1065 } 1066 1067 if (IS_FWI2_CAPABLE(ha)) { 1068 ha->fw_attributes_h = mcp->mb[15]; 1069 ha->fw_attributes_ext[0] = mcp->mb[16]; 1070 ha->fw_attributes_ext[1] = mcp->mb[17]; 1071 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139, 1072 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n", 1073 __func__, mcp->mb[15], mcp->mb[6]); 1074 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f, 1075 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n", 1076 __func__, mcp->mb[17], mcp->mb[16]); 1077 1078 if (ha->fw_attributes_h & 0x4) 1079 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d, 1080 "%s: Firmware supports Extended Login 0x%x\n", 1081 __func__, ha->fw_attributes_h); 1082 1083 if (ha->fw_attributes_h & 0x8) 1084 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191, 1085 "%s: Firmware supports Exchange Offload 0x%x\n", 1086 __func__, ha->fw_attributes_h); 1087 1088 /* 1089 * FW supports nvme and driver load parameter requested nvme. 1090 * BIT 26 of fw_attributes indicates NVMe support. 1091 */ 1092 if ((ha->fw_attributes_h & 1093 (FW_ATTR_H_NVME | FW_ATTR_H_NVME_UPDATED)) && 1094 ql2xnvmeenable) { 1095 if (ha->fw_attributes_h & FW_ATTR_H_NVME_FBURST) 1096 vha->flags.nvme_first_burst = 1; 1097 1098 vha->flags.nvme_enabled = 1; 1099 ql_log(ql_log_info, vha, 0xd302, 1100 "%s: FC-NVMe is Enabled (0x%x)\n", 1101 __func__, ha->fw_attributes_h); 1102 } 1103 } 1104 1105 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 1106 ha->serdes_version[0] = mcp->mb[7] & 0xff; 1107 ha->serdes_version[1] = mcp->mb[8] >> 8; 1108 ha->serdes_version[2] = mcp->mb[8] & 0xff; 1109 ha->mpi_version[0] = mcp->mb[10] & 0xff; 1110 ha->mpi_version[1] = mcp->mb[11] >> 8; 1111 ha->mpi_version[2] = mcp->mb[11] & 0xff; 1112 ha->pep_version[0] = mcp->mb[13] & 0xff; 1113 ha->pep_version[1] = mcp->mb[14] >> 8; 1114 ha->pep_version[2] = mcp->mb[14] & 0xff; 1115 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18]; 1116 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20]; 1117 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22]; 1118 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24]; 1119 if (IS_QLA28XX(ha)) { 1120 if (mcp->mb[16] & BIT_10) 1121 ha->flags.secure_fw = 1; 1122 1123 ql_log(ql_log_info, vha, 0xffff, 1124 "Secure Flash Update in FW: %s\n", 1125 (ha->flags.secure_fw) ? "Supported" : 1126 "Not Supported"); 1127 } 1128 1129 if (ha->flags.scm_supported_a && 1130 (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_SCM_SUPPORTED)) { 1131 ha->flags.scm_supported_f = 1; 1132 memset(ha->sf_init_cb, 0, sizeof(struct init_sf_cb)); 1133 ha->sf_init_cb->flags |= BIT_13; 1134 } 1135 ql_log(ql_log_info, vha, 0x11a3, "SCM in FW: %s\n", 1136 (ha->flags.scm_supported_f) ? "Supported" : 1137 "Not Supported"); 1138 } 1139 1140 failed: 1141 if (rval != QLA_SUCCESS) { 1142 /*EMPTY*/ 1143 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval); 1144 } else { 1145 /*EMPTY*/ 1146 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b, 1147 "Done %s.\n", __func__); 1148 } 1149 return rval; 1150 } 1151 1152 /* 1153 * qla2x00_get_fw_options 1154 * Set firmware options. 1155 * 1156 * Input: 1157 * ha = adapter block pointer. 1158 * fwopt = pointer for firmware options. 1159 * 1160 * Returns: 1161 * qla2x00 local function return status code. 1162 * 1163 * Context: 1164 * Kernel context. 1165 */ 1166 int 1167 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 1168 { 1169 int rval; 1170 mbx_cmd_t mc; 1171 mbx_cmd_t *mcp = &mc; 1172 1173 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c, 1174 "Entered %s.\n", __func__); 1175 1176 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION; 1177 mcp->out_mb = MBX_0; 1178 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1179 mcp->tov = MBX_TOV_SECONDS; 1180 mcp->flags = 0; 1181 rval = qla2x00_mailbox_command(vha, mcp); 1182 1183 if (rval != QLA_SUCCESS) { 1184 /*EMPTY*/ 1185 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval); 1186 } else { 1187 fwopts[0] = mcp->mb[0]; 1188 fwopts[1] = mcp->mb[1]; 1189 fwopts[2] = mcp->mb[2]; 1190 fwopts[3] = mcp->mb[3]; 1191 1192 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e, 1193 "Done %s.\n", __func__); 1194 } 1195 1196 return rval; 1197 } 1198 1199 1200 /* 1201 * qla2x00_set_fw_options 1202 * Set firmware options. 1203 * 1204 * Input: 1205 * ha = adapter block pointer. 1206 * fwopt = pointer for firmware options. 1207 * 1208 * Returns: 1209 * qla2x00 local function return status code. 1210 * 1211 * Context: 1212 * Kernel context. 1213 */ 1214 int 1215 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts) 1216 { 1217 int rval; 1218 mbx_cmd_t mc; 1219 mbx_cmd_t *mcp = &mc; 1220 1221 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f, 1222 "Entered %s.\n", __func__); 1223 1224 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION; 1225 mcp->mb[1] = fwopts[1]; 1226 mcp->mb[2] = fwopts[2]; 1227 mcp->mb[3] = fwopts[3]; 1228 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1229 mcp->in_mb = MBX_0; 1230 if (IS_FWI2_CAPABLE(vha->hw)) { 1231 mcp->in_mb |= MBX_1; 1232 mcp->mb[10] = fwopts[10]; 1233 mcp->out_mb |= MBX_10; 1234 } else { 1235 mcp->mb[10] = fwopts[10]; 1236 mcp->mb[11] = fwopts[11]; 1237 mcp->mb[12] = 0; /* Undocumented, but used */ 1238 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 1239 } 1240 mcp->tov = MBX_TOV_SECONDS; 1241 mcp->flags = 0; 1242 rval = qla2x00_mailbox_command(vha, mcp); 1243 1244 fwopts[0] = mcp->mb[0]; 1245 1246 if (rval != QLA_SUCCESS) { 1247 /*EMPTY*/ 1248 ql_dbg(ql_dbg_mbx, vha, 0x1030, 1249 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]); 1250 } else { 1251 /*EMPTY*/ 1252 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031, 1253 "Done %s.\n", __func__); 1254 } 1255 1256 return rval; 1257 } 1258 1259 /* 1260 * qla2x00_mbx_reg_test 1261 * Mailbox register wrap test. 1262 * 1263 * Input: 1264 * ha = adapter block pointer. 1265 * TARGET_QUEUE_LOCK must be released. 1266 * ADAPTER_STATE_LOCK must be released. 1267 * 1268 * Returns: 1269 * qla2x00 local function return status code. 1270 * 1271 * Context: 1272 * Kernel context. 1273 */ 1274 int 1275 qla2x00_mbx_reg_test(scsi_qla_host_t *vha) 1276 { 1277 int rval; 1278 mbx_cmd_t mc; 1279 mbx_cmd_t *mcp = &mc; 1280 1281 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032, 1282 "Entered %s.\n", __func__); 1283 1284 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST; 1285 mcp->mb[1] = 0xAAAA; 1286 mcp->mb[2] = 0x5555; 1287 mcp->mb[3] = 0xAA55; 1288 mcp->mb[4] = 0x55AA; 1289 mcp->mb[5] = 0xA5A5; 1290 mcp->mb[6] = 0x5A5A; 1291 mcp->mb[7] = 0x2525; 1292 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1293 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 1294 mcp->tov = MBX_TOV_SECONDS; 1295 mcp->flags = 0; 1296 rval = qla2x00_mailbox_command(vha, mcp); 1297 1298 if (rval == QLA_SUCCESS) { 1299 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 || 1300 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA) 1301 rval = QLA_FUNCTION_FAILED; 1302 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A || 1303 mcp->mb[7] != 0x2525) 1304 rval = QLA_FUNCTION_FAILED; 1305 } 1306 1307 if (rval != QLA_SUCCESS) { 1308 /*EMPTY*/ 1309 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval); 1310 } else { 1311 /*EMPTY*/ 1312 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034, 1313 "Done %s.\n", __func__); 1314 } 1315 1316 return rval; 1317 } 1318 1319 /* 1320 * qla2x00_verify_checksum 1321 * Verify firmware checksum. 1322 * 1323 * Input: 1324 * ha = adapter block pointer. 1325 * TARGET_QUEUE_LOCK must be released. 1326 * ADAPTER_STATE_LOCK must be released. 1327 * 1328 * Returns: 1329 * qla2x00 local function return status code. 1330 * 1331 * Context: 1332 * Kernel context. 1333 */ 1334 int 1335 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr) 1336 { 1337 int rval; 1338 mbx_cmd_t mc; 1339 mbx_cmd_t *mcp = &mc; 1340 1341 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035, 1342 "Entered %s.\n", __func__); 1343 1344 mcp->mb[0] = MBC_VERIFY_CHECKSUM; 1345 mcp->out_mb = MBX_0; 1346 mcp->in_mb = MBX_0; 1347 if (IS_FWI2_CAPABLE(vha->hw)) { 1348 mcp->mb[1] = MSW(risc_addr); 1349 mcp->mb[2] = LSW(risc_addr); 1350 mcp->out_mb |= MBX_2|MBX_1; 1351 mcp->in_mb |= MBX_2|MBX_1; 1352 } else { 1353 mcp->mb[1] = LSW(risc_addr); 1354 mcp->out_mb |= MBX_1; 1355 mcp->in_mb |= MBX_1; 1356 } 1357 1358 mcp->tov = MBX_TOV_SECONDS; 1359 mcp->flags = 0; 1360 rval = qla2x00_mailbox_command(vha, mcp); 1361 1362 if (rval != QLA_SUCCESS) { 1363 ql_dbg(ql_dbg_mbx, vha, 0x1036, 1364 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ? 1365 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]); 1366 } else { 1367 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037, 1368 "Done %s.\n", __func__); 1369 } 1370 1371 return rval; 1372 } 1373 1374 /* 1375 * qla2x00_issue_iocb 1376 * Issue IOCB using mailbox command 1377 * 1378 * Input: 1379 * ha = adapter state pointer. 1380 * buffer = buffer pointer. 1381 * phys_addr = physical address of buffer. 1382 * size = size of buffer. 1383 * TARGET_QUEUE_LOCK must be released. 1384 * ADAPTER_STATE_LOCK must be released. 1385 * 1386 * Returns: 1387 * qla2x00 local function return status code. 1388 * 1389 * Context: 1390 * Kernel context. 1391 */ 1392 int 1393 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer, 1394 dma_addr_t phys_addr, size_t size, uint32_t tov) 1395 { 1396 int rval; 1397 mbx_cmd_t mc; 1398 mbx_cmd_t *mcp = &mc; 1399 1400 if (!vha->hw->flags.fw_started) 1401 return QLA_INVALID_COMMAND; 1402 1403 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038, 1404 "Entered %s.\n", __func__); 1405 1406 mcp->mb[0] = MBC_IOCB_COMMAND_A64; 1407 mcp->mb[1] = 0; 1408 mcp->mb[2] = MSW(LSD(phys_addr)); 1409 mcp->mb[3] = LSW(LSD(phys_addr)); 1410 mcp->mb[6] = MSW(MSD(phys_addr)); 1411 mcp->mb[7] = LSW(MSD(phys_addr)); 1412 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1413 mcp->in_mb = MBX_1|MBX_0; 1414 mcp->tov = tov; 1415 mcp->flags = 0; 1416 rval = qla2x00_mailbox_command(vha, mcp); 1417 1418 if (rval != QLA_SUCCESS) { 1419 /*EMPTY*/ 1420 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval); 1421 } else { 1422 sts_entry_t *sts_entry = buffer; 1423 1424 /* Mask reserved bits. */ 1425 sts_entry->entry_status &= 1426 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK; 1427 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a, 1428 "Done %s (status=%x).\n", __func__, 1429 sts_entry->entry_status); 1430 } 1431 1432 return rval; 1433 } 1434 1435 int 1436 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr, 1437 size_t size) 1438 { 1439 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size, 1440 MBX_TOV_SECONDS); 1441 } 1442 1443 /* 1444 * qla2x00_abort_command 1445 * Abort command aborts a specified IOCB. 1446 * 1447 * Input: 1448 * ha = adapter block pointer. 1449 * sp = SB structure pointer. 1450 * 1451 * Returns: 1452 * qla2x00 local function return status code. 1453 * 1454 * Context: 1455 * Kernel context. 1456 */ 1457 int 1458 qla2x00_abort_command(srb_t *sp) 1459 { 1460 unsigned long flags = 0; 1461 int rval; 1462 uint32_t handle = 0; 1463 mbx_cmd_t mc; 1464 mbx_cmd_t *mcp = &mc; 1465 fc_port_t *fcport = sp->fcport; 1466 scsi_qla_host_t *vha = fcport->vha; 1467 struct qla_hw_data *ha = vha->hw; 1468 struct req_que *req; 1469 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1470 1471 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b, 1472 "Entered %s.\n", __func__); 1473 1474 if (sp->qpair) 1475 req = sp->qpair->req; 1476 else 1477 req = vha->req; 1478 1479 spin_lock_irqsave(&ha->hardware_lock, flags); 1480 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 1481 if (req->outstanding_cmds[handle] == sp) 1482 break; 1483 } 1484 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1485 1486 if (handle == req->num_outstanding_cmds) { 1487 /* command not found */ 1488 return QLA_FUNCTION_FAILED; 1489 } 1490 1491 mcp->mb[0] = MBC_ABORT_COMMAND; 1492 if (HAS_EXTENDED_IDS(ha)) 1493 mcp->mb[1] = fcport->loop_id; 1494 else 1495 mcp->mb[1] = fcport->loop_id << 8; 1496 mcp->mb[2] = (uint16_t)handle; 1497 mcp->mb[3] = (uint16_t)(handle >> 16); 1498 mcp->mb[6] = (uint16_t)cmd->device->lun; 1499 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1500 mcp->in_mb = MBX_0; 1501 mcp->tov = MBX_TOV_SECONDS; 1502 mcp->flags = 0; 1503 rval = qla2x00_mailbox_command(vha, mcp); 1504 1505 if (rval != QLA_SUCCESS) { 1506 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval); 1507 } else { 1508 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d, 1509 "Done %s.\n", __func__); 1510 } 1511 1512 return rval; 1513 } 1514 1515 int 1516 qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag) 1517 { 1518 int rval, rval2; 1519 mbx_cmd_t mc; 1520 mbx_cmd_t *mcp = &mc; 1521 scsi_qla_host_t *vha; 1522 1523 vha = fcport->vha; 1524 1525 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e, 1526 "Entered %s.\n", __func__); 1527 1528 mcp->mb[0] = MBC_ABORT_TARGET; 1529 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0; 1530 if (HAS_EXTENDED_IDS(vha->hw)) { 1531 mcp->mb[1] = fcport->loop_id; 1532 mcp->mb[10] = 0; 1533 mcp->out_mb |= MBX_10; 1534 } else { 1535 mcp->mb[1] = fcport->loop_id << 8; 1536 } 1537 mcp->mb[2] = vha->hw->loop_reset_delay; 1538 mcp->mb[9] = vha->vp_idx; 1539 1540 mcp->in_mb = MBX_0; 1541 mcp->tov = MBX_TOV_SECONDS; 1542 mcp->flags = 0; 1543 rval = qla2x00_mailbox_command(vha, mcp); 1544 if (rval != QLA_SUCCESS) { 1545 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f, 1546 "Failed=%x.\n", rval); 1547 } 1548 1549 /* Issue marker IOCB. */ 1550 rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, 0, 1551 MK_SYNC_ID); 1552 if (rval2 != QLA_SUCCESS) { 1553 ql_dbg(ql_dbg_mbx, vha, 0x1040, 1554 "Failed to issue marker IOCB (%x).\n", rval2); 1555 } else { 1556 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041, 1557 "Done %s.\n", __func__); 1558 } 1559 1560 return rval; 1561 } 1562 1563 int 1564 qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 1565 { 1566 int rval, rval2; 1567 mbx_cmd_t mc; 1568 mbx_cmd_t *mcp = &mc; 1569 scsi_qla_host_t *vha; 1570 1571 vha = fcport->vha; 1572 1573 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042, 1574 "Entered %s.\n", __func__); 1575 1576 mcp->mb[0] = MBC_LUN_RESET; 1577 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 1578 if (HAS_EXTENDED_IDS(vha->hw)) 1579 mcp->mb[1] = fcport->loop_id; 1580 else 1581 mcp->mb[1] = fcport->loop_id << 8; 1582 mcp->mb[2] = (u32)l; 1583 mcp->mb[3] = 0; 1584 mcp->mb[9] = vha->vp_idx; 1585 1586 mcp->in_mb = MBX_0; 1587 mcp->tov = MBX_TOV_SECONDS; 1588 mcp->flags = 0; 1589 rval = qla2x00_mailbox_command(vha, mcp); 1590 if (rval != QLA_SUCCESS) { 1591 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval); 1592 } 1593 1594 /* Issue marker IOCB. */ 1595 rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, l, 1596 MK_SYNC_ID_LUN); 1597 if (rval2 != QLA_SUCCESS) { 1598 ql_dbg(ql_dbg_mbx, vha, 0x1044, 1599 "Failed to issue marker IOCB (%x).\n", rval2); 1600 } else { 1601 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045, 1602 "Done %s.\n", __func__); 1603 } 1604 1605 return rval; 1606 } 1607 1608 /* 1609 * qla2x00_get_adapter_id 1610 * Get adapter ID and topology. 1611 * 1612 * Input: 1613 * ha = adapter block pointer. 1614 * id = pointer for loop ID. 1615 * al_pa = pointer for AL_PA. 1616 * area = pointer for area. 1617 * domain = pointer for domain. 1618 * top = pointer for topology. 1619 * TARGET_QUEUE_LOCK must be released. 1620 * ADAPTER_STATE_LOCK must be released. 1621 * 1622 * Returns: 1623 * qla2x00 local function return status code. 1624 * 1625 * Context: 1626 * Kernel context. 1627 */ 1628 int 1629 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa, 1630 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap) 1631 { 1632 int rval; 1633 mbx_cmd_t mc; 1634 mbx_cmd_t *mcp = &mc; 1635 1636 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046, 1637 "Entered %s.\n", __func__); 1638 1639 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID; 1640 mcp->mb[9] = vha->vp_idx; 1641 mcp->out_mb = MBX_9|MBX_0; 1642 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1643 if (IS_CNA_CAPABLE(vha->hw)) 1644 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; 1645 if (IS_FWI2_CAPABLE(vha->hw)) 1646 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16; 1647 if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw)) { 1648 mcp->in_mb |= MBX_15; 1649 mcp->out_mb |= MBX_7|MBX_21|MBX_22|MBX_23; 1650 } 1651 1652 mcp->tov = MBX_TOV_SECONDS; 1653 mcp->flags = 0; 1654 rval = qla2x00_mailbox_command(vha, mcp); 1655 if (mcp->mb[0] == MBS_COMMAND_ERROR) 1656 rval = QLA_COMMAND_ERROR; 1657 else if (mcp->mb[0] == MBS_INVALID_COMMAND) 1658 rval = QLA_INVALID_COMMAND; 1659 1660 /* Return data. */ 1661 *id = mcp->mb[1]; 1662 *al_pa = LSB(mcp->mb[2]); 1663 *area = MSB(mcp->mb[2]); 1664 *domain = LSB(mcp->mb[3]); 1665 *top = mcp->mb[6]; 1666 *sw_cap = mcp->mb[7]; 1667 1668 if (rval != QLA_SUCCESS) { 1669 /*EMPTY*/ 1670 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval); 1671 } else { 1672 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048, 1673 "Done %s.\n", __func__); 1674 1675 if (IS_CNA_CAPABLE(vha->hw)) { 1676 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; 1677 vha->fcoe_fcf_idx = mcp->mb[10]; 1678 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; 1679 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff; 1680 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8; 1681 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff; 1682 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8; 1683 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff; 1684 } 1685 /* If FA-WWN supported */ 1686 if (IS_FAWWN_CAPABLE(vha->hw)) { 1687 if (mcp->mb[7] & BIT_14) { 1688 vha->port_name[0] = MSB(mcp->mb[16]); 1689 vha->port_name[1] = LSB(mcp->mb[16]); 1690 vha->port_name[2] = MSB(mcp->mb[17]); 1691 vha->port_name[3] = LSB(mcp->mb[17]); 1692 vha->port_name[4] = MSB(mcp->mb[18]); 1693 vha->port_name[5] = LSB(mcp->mb[18]); 1694 vha->port_name[6] = MSB(mcp->mb[19]); 1695 vha->port_name[7] = LSB(mcp->mb[19]); 1696 fc_host_port_name(vha->host) = 1697 wwn_to_u64(vha->port_name); 1698 ql_dbg(ql_dbg_mbx, vha, 0x10ca, 1699 "FA-WWN acquired %016llx\n", 1700 wwn_to_u64(vha->port_name)); 1701 } 1702 } 1703 1704 if (IS_QLA27XX(vha->hw) || IS_QLA28XX(vha->hw)) { 1705 vha->bbcr = mcp->mb[15]; 1706 if (mcp->mb[7] & SCM_EDC_ACC_RECEIVED) { 1707 ql_log(ql_log_info, vha, 0x11a4, 1708 "SCM: EDC ELS completed, flags 0x%x\n", 1709 mcp->mb[21]); 1710 } 1711 if (mcp->mb[7] & SCM_RDF_ACC_RECEIVED) { 1712 vha->hw->flags.scm_enabled = 1; 1713 vha->scm_fabric_connection_flags |= 1714 SCM_FLAG_RDF_COMPLETED; 1715 ql_log(ql_log_info, vha, 0x11a5, 1716 "SCM: RDF ELS completed, flags 0x%x\n", 1717 mcp->mb[23]); 1718 } 1719 } 1720 } 1721 1722 return rval; 1723 } 1724 1725 /* 1726 * qla2x00_get_retry_cnt 1727 * Get current firmware login retry count and delay. 1728 * 1729 * Input: 1730 * ha = adapter block pointer. 1731 * retry_cnt = pointer to login retry count. 1732 * tov = pointer to login timeout value. 1733 * 1734 * Returns: 1735 * qla2x00 local function return status code. 1736 * 1737 * Context: 1738 * Kernel context. 1739 */ 1740 int 1741 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov, 1742 uint16_t *r_a_tov) 1743 { 1744 int rval; 1745 uint16_t ratov; 1746 mbx_cmd_t mc; 1747 mbx_cmd_t *mcp = &mc; 1748 1749 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049, 1750 "Entered %s.\n", __func__); 1751 1752 mcp->mb[0] = MBC_GET_RETRY_COUNT; 1753 mcp->out_mb = MBX_0; 1754 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 1755 mcp->tov = MBX_TOV_SECONDS; 1756 mcp->flags = 0; 1757 rval = qla2x00_mailbox_command(vha, mcp); 1758 1759 if (rval != QLA_SUCCESS) { 1760 /*EMPTY*/ 1761 ql_dbg(ql_dbg_mbx, vha, 0x104a, 1762 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 1763 } else { 1764 /* Convert returned data and check our values. */ 1765 *r_a_tov = mcp->mb[3] / 2; 1766 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */ 1767 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) { 1768 /* Update to the larger values */ 1769 *retry_cnt = (uint8_t)mcp->mb[1]; 1770 *tov = ratov; 1771 } 1772 1773 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b, 1774 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov); 1775 } 1776 1777 return rval; 1778 } 1779 1780 /* 1781 * qla2x00_init_firmware 1782 * Initialize adapter firmware. 1783 * 1784 * Input: 1785 * ha = adapter block pointer. 1786 * dptr = Initialization control block pointer. 1787 * size = size of initialization control block. 1788 * TARGET_QUEUE_LOCK must be released. 1789 * ADAPTER_STATE_LOCK must be released. 1790 * 1791 * Returns: 1792 * qla2x00 local function return status code. 1793 * 1794 * Context: 1795 * Kernel context. 1796 */ 1797 int 1798 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size) 1799 { 1800 int rval; 1801 mbx_cmd_t mc; 1802 mbx_cmd_t *mcp = &mc; 1803 struct qla_hw_data *ha = vha->hw; 1804 1805 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c, 1806 "Entered %s.\n", __func__); 1807 1808 if (IS_P3P_TYPE(ha) && ql2xdbwr) 1809 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr, 1810 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16))); 1811 1812 if (ha->flags.npiv_supported) 1813 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE; 1814 else 1815 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE; 1816 1817 mcp->mb[1] = 0; 1818 mcp->mb[2] = MSW(ha->init_cb_dma); 1819 mcp->mb[3] = LSW(ha->init_cb_dma); 1820 mcp->mb[6] = MSW(MSD(ha->init_cb_dma)); 1821 mcp->mb[7] = LSW(MSD(ha->init_cb_dma)); 1822 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 1823 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) { 1824 mcp->mb[1] = BIT_0; 1825 mcp->mb[10] = MSW(ha->ex_init_cb_dma); 1826 mcp->mb[11] = LSW(ha->ex_init_cb_dma); 1827 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma)); 1828 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma)); 1829 mcp->mb[14] = sizeof(*ha->ex_init_cb); 1830 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10; 1831 } 1832 1833 if (ha->flags.scm_supported_f) { 1834 mcp->mb[1] |= BIT_1; 1835 mcp->mb[16] = MSW(ha->sf_init_cb_dma); 1836 mcp->mb[17] = LSW(ha->sf_init_cb_dma); 1837 mcp->mb[18] = MSW(MSD(ha->sf_init_cb_dma)); 1838 mcp->mb[19] = LSW(MSD(ha->sf_init_cb_dma)); 1839 mcp->mb[15] = sizeof(*ha->sf_init_cb); 1840 mcp->out_mb |= MBX_19|MBX_18|MBX_17|MBX_16|MBX_15; 1841 } 1842 1843 /* 1 and 2 should normally be captured. */ 1844 mcp->in_mb = MBX_2|MBX_1|MBX_0; 1845 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1846 /* mb3 is additional info about the installed SFP. */ 1847 mcp->in_mb |= MBX_3; 1848 mcp->buf_size = size; 1849 mcp->flags = MBX_DMA_OUT; 1850 mcp->tov = MBX_TOV_SECONDS; 1851 rval = qla2x00_mailbox_command(vha, mcp); 1852 1853 if (rval != QLA_SUCCESS) { 1854 /*EMPTY*/ 1855 ql_dbg(ql_dbg_mbx, vha, 0x104d, 1856 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x.\n", 1857 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]); 1858 if (ha->init_cb) { 1859 ql_dbg(ql_dbg_mbx, vha, 0x104d, "init_cb:\n"); 1860 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 1861 0x0104d, ha->init_cb, sizeof(*ha->init_cb)); 1862 } 1863 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) { 1864 ql_dbg(ql_dbg_mbx, vha, 0x104d, "ex_init_cb:\n"); 1865 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 1866 0x0104d, ha->ex_init_cb, sizeof(*ha->ex_init_cb)); 1867 } 1868 } else { 1869 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 1870 if (mcp->mb[2] == 6 || mcp->mb[3] == 2) 1871 ql_dbg(ql_dbg_mbx, vha, 0x119d, 1872 "Invalid SFP/Validation Failed\n"); 1873 } 1874 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e, 1875 "Done %s.\n", __func__); 1876 } 1877 1878 return rval; 1879 } 1880 1881 1882 /* 1883 * qla2x00_get_port_database 1884 * Issue normal/enhanced get port database mailbox command 1885 * and copy device name as necessary. 1886 * 1887 * Input: 1888 * ha = adapter state pointer. 1889 * dev = structure pointer. 1890 * opt = enhanced cmd option byte. 1891 * 1892 * Returns: 1893 * qla2x00 local function return status code. 1894 * 1895 * Context: 1896 * Kernel context. 1897 */ 1898 int 1899 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt) 1900 { 1901 int rval; 1902 mbx_cmd_t mc; 1903 mbx_cmd_t *mcp = &mc; 1904 port_database_t *pd; 1905 struct port_database_24xx *pd24; 1906 dma_addr_t pd_dma; 1907 struct qla_hw_data *ha = vha->hw; 1908 1909 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f, 1910 "Entered %s.\n", __func__); 1911 1912 pd24 = NULL; 1913 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1914 if (pd == NULL) { 1915 ql_log(ql_log_warn, vha, 0x1050, 1916 "Failed to allocate port database structure.\n"); 1917 fcport->query = 0; 1918 return QLA_MEMORY_ALLOC_FAILED; 1919 } 1920 1921 mcp->mb[0] = MBC_GET_PORT_DATABASE; 1922 if (opt != 0 && !IS_FWI2_CAPABLE(ha)) 1923 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE; 1924 mcp->mb[2] = MSW(pd_dma); 1925 mcp->mb[3] = LSW(pd_dma); 1926 mcp->mb[6] = MSW(MSD(pd_dma)); 1927 mcp->mb[7] = LSW(MSD(pd_dma)); 1928 mcp->mb[9] = vha->vp_idx; 1929 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 1930 mcp->in_mb = MBX_0; 1931 if (IS_FWI2_CAPABLE(ha)) { 1932 mcp->mb[1] = fcport->loop_id; 1933 mcp->mb[10] = opt; 1934 mcp->out_mb |= MBX_10|MBX_1; 1935 mcp->in_mb |= MBX_1; 1936 } else if (HAS_EXTENDED_IDS(ha)) { 1937 mcp->mb[1] = fcport->loop_id; 1938 mcp->mb[10] = opt; 1939 mcp->out_mb |= MBX_10|MBX_1; 1940 } else { 1941 mcp->mb[1] = fcport->loop_id << 8 | opt; 1942 mcp->out_mb |= MBX_1; 1943 } 1944 mcp->buf_size = IS_FWI2_CAPABLE(ha) ? 1945 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE; 1946 mcp->flags = MBX_DMA_IN; 1947 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1948 rval = qla2x00_mailbox_command(vha, mcp); 1949 if (rval != QLA_SUCCESS) 1950 goto gpd_error_out; 1951 1952 if (IS_FWI2_CAPABLE(ha)) { 1953 uint64_t zero = 0; 1954 u8 current_login_state, last_login_state; 1955 1956 pd24 = (struct port_database_24xx *) pd; 1957 1958 /* Check for logged in state. */ 1959 if (NVME_TARGET(ha, fcport)) { 1960 current_login_state = pd24->current_login_state >> 4; 1961 last_login_state = pd24->last_login_state >> 4; 1962 } else { 1963 current_login_state = pd24->current_login_state & 0xf; 1964 last_login_state = pd24->last_login_state & 0xf; 1965 } 1966 fcport->current_login_state = pd24->current_login_state; 1967 fcport->last_login_state = pd24->last_login_state; 1968 1969 /* Check for logged in state. */ 1970 if (current_login_state != PDS_PRLI_COMPLETE && 1971 last_login_state != PDS_PRLI_COMPLETE) { 1972 ql_dbg(ql_dbg_mbx, vha, 0x119a, 1973 "Unable to verify login-state (%x/%x) for loop_id %x.\n", 1974 current_login_state, last_login_state, 1975 fcport->loop_id); 1976 rval = QLA_FUNCTION_FAILED; 1977 1978 if (!fcport->query) 1979 goto gpd_error_out; 1980 } 1981 1982 if (fcport->loop_id == FC_NO_LOOP_ID || 1983 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 1984 memcmp(fcport->port_name, pd24->port_name, 8))) { 1985 /* We lost the device mid way. */ 1986 rval = QLA_NOT_LOGGED_IN; 1987 goto gpd_error_out; 1988 } 1989 1990 /* Names are little-endian. */ 1991 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE); 1992 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE); 1993 1994 /* Get port_id of device. */ 1995 fcport->d_id.b.domain = pd24->port_id[0]; 1996 fcport->d_id.b.area = pd24->port_id[1]; 1997 fcport->d_id.b.al_pa = pd24->port_id[2]; 1998 fcport->d_id.b.rsvd_1 = 0; 1999 2000 /* If not target must be initiator or unknown type. */ 2001 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0) 2002 fcport->port_type = FCT_INITIATOR; 2003 else 2004 fcport->port_type = FCT_TARGET; 2005 2006 /* Passback COS information. */ 2007 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ? 2008 FC_COS_CLASS2 : FC_COS_CLASS3; 2009 2010 if (pd24->prli_svc_param_word_3[0] & BIT_7) 2011 fcport->flags |= FCF_CONF_COMP_SUPPORTED; 2012 } else { 2013 uint64_t zero = 0; 2014 2015 /* Check for logged in state. */ 2016 if (pd->master_state != PD_STATE_PORT_LOGGED_IN && 2017 pd->slave_state != PD_STATE_PORT_LOGGED_IN) { 2018 ql_dbg(ql_dbg_mbx, vha, 0x100a, 2019 "Unable to verify login-state (%x/%x) - " 2020 "portid=%02x%02x%02x.\n", pd->master_state, 2021 pd->slave_state, fcport->d_id.b.domain, 2022 fcport->d_id.b.area, fcport->d_id.b.al_pa); 2023 rval = QLA_FUNCTION_FAILED; 2024 goto gpd_error_out; 2025 } 2026 2027 if (fcport->loop_id == FC_NO_LOOP_ID || 2028 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 2029 memcmp(fcport->port_name, pd->port_name, 8))) { 2030 /* We lost the device mid way. */ 2031 rval = QLA_NOT_LOGGED_IN; 2032 goto gpd_error_out; 2033 } 2034 2035 /* Names are little-endian. */ 2036 memcpy(fcport->node_name, pd->node_name, WWN_SIZE); 2037 memcpy(fcport->port_name, pd->port_name, WWN_SIZE); 2038 2039 /* Get port_id of device. */ 2040 fcport->d_id.b.domain = pd->port_id[0]; 2041 fcport->d_id.b.area = pd->port_id[3]; 2042 fcport->d_id.b.al_pa = pd->port_id[2]; 2043 fcport->d_id.b.rsvd_1 = 0; 2044 2045 /* If not target must be initiator or unknown type. */ 2046 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 2047 fcport->port_type = FCT_INITIATOR; 2048 else 2049 fcport->port_type = FCT_TARGET; 2050 2051 /* Passback COS information. */ 2052 fcport->supported_classes = (pd->options & BIT_4) ? 2053 FC_COS_CLASS2 : FC_COS_CLASS3; 2054 } 2055 2056 gpd_error_out: 2057 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 2058 fcport->query = 0; 2059 2060 if (rval != QLA_SUCCESS) { 2061 ql_dbg(ql_dbg_mbx, vha, 0x1052, 2062 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval, 2063 mcp->mb[0], mcp->mb[1]); 2064 } else { 2065 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053, 2066 "Done %s.\n", __func__); 2067 } 2068 2069 return rval; 2070 } 2071 2072 int 2073 qla24xx_get_port_database(scsi_qla_host_t *vha, u16 nport_handle, 2074 struct port_database_24xx *pdb) 2075 { 2076 mbx_cmd_t mc; 2077 mbx_cmd_t *mcp = &mc; 2078 dma_addr_t pdb_dma; 2079 int rval; 2080 2081 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1115, 2082 "Entered %s.\n", __func__); 2083 2084 memset(pdb, 0, sizeof(*pdb)); 2085 2086 pdb_dma = dma_map_single(&vha->hw->pdev->dev, pdb, 2087 sizeof(*pdb), DMA_FROM_DEVICE); 2088 if (!pdb_dma) { 2089 ql_log(ql_log_warn, vha, 0x1116, "Failed to map dma buffer.\n"); 2090 return QLA_MEMORY_ALLOC_FAILED; 2091 } 2092 2093 mcp->mb[0] = MBC_GET_PORT_DATABASE; 2094 mcp->mb[1] = nport_handle; 2095 mcp->mb[2] = MSW(LSD(pdb_dma)); 2096 mcp->mb[3] = LSW(LSD(pdb_dma)); 2097 mcp->mb[6] = MSW(MSD(pdb_dma)); 2098 mcp->mb[7] = LSW(MSD(pdb_dma)); 2099 mcp->mb[9] = 0; 2100 mcp->mb[10] = 0; 2101 mcp->out_mb = MBX_10|MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2102 mcp->in_mb = MBX_1|MBX_0; 2103 mcp->buf_size = sizeof(*pdb); 2104 mcp->flags = MBX_DMA_IN; 2105 mcp->tov = vha->hw->login_timeout * 2; 2106 rval = qla2x00_mailbox_command(vha, mcp); 2107 2108 if (rval != QLA_SUCCESS) { 2109 ql_dbg(ql_dbg_mbx, vha, 0x111a, 2110 "Failed=%x mb[0]=%x mb[1]=%x.\n", 2111 rval, mcp->mb[0], mcp->mb[1]); 2112 } else { 2113 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111b, 2114 "Done %s.\n", __func__); 2115 } 2116 2117 dma_unmap_single(&vha->hw->pdev->dev, pdb_dma, 2118 sizeof(*pdb), DMA_FROM_DEVICE); 2119 2120 return rval; 2121 } 2122 2123 /* 2124 * qla2x00_get_firmware_state 2125 * Get adapter firmware state. 2126 * 2127 * Input: 2128 * ha = adapter block pointer. 2129 * dptr = pointer for firmware state. 2130 * TARGET_QUEUE_LOCK must be released. 2131 * ADAPTER_STATE_LOCK must be released. 2132 * 2133 * Returns: 2134 * qla2x00 local function return status code. 2135 * 2136 * Context: 2137 * Kernel context. 2138 */ 2139 int 2140 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states) 2141 { 2142 int rval; 2143 mbx_cmd_t mc; 2144 mbx_cmd_t *mcp = &mc; 2145 struct qla_hw_data *ha = vha->hw; 2146 2147 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054, 2148 "Entered %s.\n", __func__); 2149 2150 mcp->mb[0] = MBC_GET_FIRMWARE_STATE; 2151 mcp->out_mb = MBX_0; 2152 if (IS_FWI2_CAPABLE(vha->hw)) 2153 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 2154 else 2155 mcp->in_mb = MBX_1|MBX_0; 2156 mcp->tov = MBX_TOV_SECONDS; 2157 mcp->flags = 0; 2158 rval = qla2x00_mailbox_command(vha, mcp); 2159 2160 /* Return firmware states. */ 2161 states[0] = mcp->mb[1]; 2162 if (IS_FWI2_CAPABLE(vha->hw)) { 2163 states[1] = mcp->mb[2]; 2164 states[2] = mcp->mb[3]; /* SFP info */ 2165 states[3] = mcp->mb[4]; 2166 states[4] = mcp->mb[5]; 2167 states[5] = mcp->mb[6]; /* DPORT status */ 2168 } 2169 2170 if (rval != QLA_SUCCESS) { 2171 /*EMPTY*/ 2172 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval); 2173 } else { 2174 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 2175 if (mcp->mb[2] == 6 || mcp->mb[3] == 2) 2176 ql_dbg(ql_dbg_mbx, vha, 0x119e, 2177 "Invalid SFP/Validation Failed\n"); 2178 } 2179 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056, 2180 "Done %s.\n", __func__); 2181 } 2182 2183 return rval; 2184 } 2185 2186 /* 2187 * qla2x00_get_port_name 2188 * Issue get port name mailbox command. 2189 * Returned name is in big endian format. 2190 * 2191 * Input: 2192 * ha = adapter block pointer. 2193 * loop_id = loop ID of device. 2194 * name = pointer for name. 2195 * TARGET_QUEUE_LOCK must be released. 2196 * ADAPTER_STATE_LOCK must be released. 2197 * 2198 * Returns: 2199 * qla2x00 local function return status code. 2200 * 2201 * Context: 2202 * Kernel context. 2203 */ 2204 int 2205 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name, 2206 uint8_t opt) 2207 { 2208 int rval; 2209 mbx_cmd_t mc; 2210 mbx_cmd_t *mcp = &mc; 2211 2212 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057, 2213 "Entered %s.\n", __func__); 2214 2215 mcp->mb[0] = MBC_GET_PORT_NAME; 2216 mcp->mb[9] = vha->vp_idx; 2217 mcp->out_mb = MBX_9|MBX_1|MBX_0; 2218 if (HAS_EXTENDED_IDS(vha->hw)) { 2219 mcp->mb[1] = loop_id; 2220 mcp->mb[10] = opt; 2221 mcp->out_mb |= MBX_10; 2222 } else { 2223 mcp->mb[1] = loop_id << 8 | opt; 2224 } 2225 2226 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2227 mcp->tov = MBX_TOV_SECONDS; 2228 mcp->flags = 0; 2229 rval = qla2x00_mailbox_command(vha, mcp); 2230 2231 if (rval != QLA_SUCCESS) { 2232 /*EMPTY*/ 2233 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval); 2234 } else { 2235 if (name != NULL) { 2236 /* This function returns name in big endian. */ 2237 name[0] = MSB(mcp->mb[2]); 2238 name[1] = LSB(mcp->mb[2]); 2239 name[2] = MSB(mcp->mb[3]); 2240 name[3] = LSB(mcp->mb[3]); 2241 name[4] = MSB(mcp->mb[6]); 2242 name[5] = LSB(mcp->mb[6]); 2243 name[6] = MSB(mcp->mb[7]); 2244 name[7] = LSB(mcp->mb[7]); 2245 } 2246 2247 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059, 2248 "Done %s.\n", __func__); 2249 } 2250 2251 return rval; 2252 } 2253 2254 /* 2255 * qla24xx_link_initialization 2256 * Issue link initialization mailbox command. 2257 * 2258 * Input: 2259 * ha = adapter block pointer. 2260 * TARGET_QUEUE_LOCK must be released. 2261 * ADAPTER_STATE_LOCK must be released. 2262 * 2263 * Returns: 2264 * qla2x00 local function return status code. 2265 * 2266 * Context: 2267 * Kernel context. 2268 */ 2269 int 2270 qla24xx_link_initialize(scsi_qla_host_t *vha) 2271 { 2272 int rval; 2273 mbx_cmd_t mc; 2274 mbx_cmd_t *mcp = &mc; 2275 2276 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152, 2277 "Entered %s.\n", __func__); 2278 2279 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw)) 2280 return QLA_FUNCTION_FAILED; 2281 2282 mcp->mb[0] = MBC_LINK_INITIALIZATION; 2283 mcp->mb[1] = BIT_4; 2284 if (vha->hw->operating_mode == LOOP) 2285 mcp->mb[1] |= BIT_6; 2286 else 2287 mcp->mb[1] |= BIT_5; 2288 mcp->mb[2] = 0; 2289 mcp->mb[3] = 0; 2290 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2291 mcp->in_mb = MBX_0; 2292 mcp->tov = MBX_TOV_SECONDS; 2293 mcp->flags = 0; 2294 rval = qla2x00_mailbox_command(vha, mcp); 2295 2296 if (rval != QLA_SUCCESS) { 2297 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval); 2298 } else { 2299 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154, 2300 "Done %s.\n", __func__); 2301 } 2302 2303 return rval; 2304 } 2305 2306 /* 2307 * qla2x00_lip_reset 2308 * Issue LIP reset mailbox command. 2309 * 2310 * Input: 2311 * ha = adapter block pointer. 2312 * TARGET_QUEUE_LOCK must be released. 2313 * ADAPTER_STATE_LOCK must be released. 2314 * 2315 * Returns: 2316 * qla2x00 local function return status code. 2317 * 2318 * Context: 2319 * Kernel context. 2320 */ 2321 int 2322 qla2x00_lip_reset(scsi_qla_host_t *vha) 2323 { 2324 int rval; 2325 mbx_cmd_t mc; 2326 mbx_cmd_t *mcp = &mc; 2327 2328 ql_dbg(ql_dbg_disc, vha, 0x105a, 2329 "Entered %s.\n", __func__); 2330 2331 if (IS_CNA_CAPABLE(vha->hw)) { 2332 /* Logout across all FCFs. */ 2333 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2334 mcp->mb[1] = BIT_1; 2335 mcp->mb[2] = 0; 2336 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2337 } else if (IS_FWI2_CAPABLE(vha->hw)) { 2338 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2339 mcp->mb[1] = BIT_4; 2340 mcp->mb[2] = 0; 2341 mcp->mb[3] = vha->hw->loop_reset_delay; 2342 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2343 } else { 2344 mcp->mb[0] = MBC_LIP_RESET; 2345 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2346 if (HAS_EXTENDED_IDS(vha->hw)) { 2347 mcp->mb[1] = 0x00ff; 2348 mcp->mb[10] = 0; 2349 mcp->out_mb |= MBX_10; 2350 } else { 2351 mcp->mb[1] = 0xff00; 2352 } 2353 mcp->mb[2] = vha->hw->loop_reset_delay; 2354 mcp->mb[3] = 0; 2355 } 2356 mcp->in_mb = MBX_0; 2357 mcp->tov = MBX_TOV_SECONDS; 2358 mcp->flags = 0; 2359 rval = qla2x00_mailbox_command(vha, mcp); 2360 2361 if (rval != QLA_SUCCESS) { 2362 /*EMPTY*/ 2363 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval); 2364 } else { 2365 /*EMPTY*/ 2366 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c, 2367 "Done %s.\n", __func__); 2368 } 2369 2370 return rval; 2371 } 2372 2373 /* 2374 * qla2x00_send_sns 2375 * Send SNS command. 2376 * 2377 * Input: 2378 * ha = adapter block pointer. 2379 * sns = pointer for command. 2380 * cmd_size = command size. 2381 * buf_size = response/command size. 2382 * TARGET_QUEUE_LOCK must be released. 2383 * ADAPTER_STATE_LOCK must be released. 2384 * 2385 * Returns: 2386 * qla2x00 local function return status code. 2387 * 2388 * Context: 2389 * Kernel context. 2390 */ 2391 int 2392 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address, 2393 uint16_t cmd_size, size_t buf_size) 2394 { 2395 int rval; 2396 mbx_cmd_t mc; 2397 mbx_cmd_t *mcp = &mc; 2398 2399 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d, 2400 "Entered %s.\n", __func__); 2401 2402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e, 2403 "Retry cnt=%d ratov=%d total tov=%d.\n", 2404 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov); 2405 2406 mcp->mb[0] = MBC_SEND_SNS_COMMAND; 2407 mcp->mb[1] = cmd_size; 2408 mcp->mb[2] = MSW(sns_phys_address); 2409 mcp->mb[3] = LSW(sns_phys_address); 2410 mcp->mb[6] = MSW(MSD(sns_phys_address)); 2411 mcp->mb[7] = LSW(MSD(sns_phys_address)); 2412 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2413 mcp->in_mb = MBX_0|MBX_1; 2414 mcp->buf_size = buf_size; 2415 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN; 2416 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2); 2417 rval = qla2x00_mailbox_command(vha, mcp); 2418 2419 if (rval != QLA_SUCCESS) { 2420 /*EMPTY*/ 2421 ql_dbg(ql_dbg_mbx, vha, 0x105f, 2422 "Failed=%x mb[0]=%x mb[1]=%x.\n", 2423 rval, mcp->mb[0], mcp->mb[1]); 2424 } else { 2425 /*EMPTY*/ 2426 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060, 2427 "Done %s.\n", __func__); 2428 } 2429 2430 return rval; 2431 } 2432 2433 int 2434 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2435 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 2436 { 2437 int rval; 2438 2439 struct logio_entry_24xx *lg; 2440 dma_addr_t lg_dma; 2441 uint32_t iop[2]; 2442 struct qla_hw_data *ha = vha->hw; 2443 struct req_que *req; 2444 2445 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061, 2446 "Entered %s.\n", __func__); 2447 2448 if (vha->vp_idx && vha->qpair) 2449 req = vha->qpair->req; 2450 else 2451 req = ha->req_q_map[0]; 2452 2453 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2454 if (lg == NULL) { 2455 ql_log(ql_log_warn, vha, 0x1062, 2456 "Failed to allocate login IOCB.\n"); 2457 return QLA_MEMORY_ALLOC_FAILED; 2458 } 2459 2460 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2461 lg->entry_count = 1; 2462 lg->handle = make_handle(req->id, lg->handle); 2463 lg->nport_handle = cpu_to_le16(loop_id); 2464 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI); 2465 if (opt & BIT_0) 2466 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI); 2467 if (opt & BIT_1) 2468 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI); 2469 lg->port_id[0] = al_pa; 2470 lg->port_id[1] = area; 2471 lg->port_id[2] = domain; 2472 lg->vp_index = vha->vp_idx; 2473 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2474 (ha->r_a_tov / 10 * 2) + 2); 2475 if (rval != QLA_SUCCESS) { 2476 ql_dbg(ql_dbg_mbx, vha, 0x1063, 2477 "Failed to issue login IOCB (%x).\n", rval); 2478 } else if (lg->entry_status != 0) { 2479 ql_dbg(ql_dbg_mbx, vha, 0x1064, 2480 "Failed to complete IOCB -- error status (%x).\n", 2481 lg->entry_status); 2482 rval = QLA_FUNCTION_FAILED; 2483 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 2484 iop[0] = le32_to_cpu(lg->io_parameter[0]); 2485 iop[1] = le32_to_cpu(lg->io_parameter[1]); 2486 2487 ql_dbg(ql_dbg_mbx, vha, 0x1065, 2488 "Failed to complete IOCB -- completion status (%x) " 2489 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2490 iop[0], iop[1]); 2491 2492 switch (iop[0]) { 2493 case LSC_SCODE_PORTID_USED: 2494 mb[0] = MBS_PORT_ID_USED; 2495 mb[1] = LSW(iop[1]); 2496 break; 2497 case LSC_SCODE_NPORT_USED: 2498 mb[0] = MBS_LOOP_ID_USED; 2499 break; 2500 case LSC_SCODE_NOLINK: 2501 case LSC_SCODE_NOIOCB: 2502 case LSC_SCODE_NOXCB: 2503 case LSC_SCODE_CMD_FAILED: 2504 case LSC_SCODE_NOFABRIC: 2505 case LSC_SCODE_FW_NOT_READY: 2506 case LSC_SCODE_NOT_LOGGED_IN: 2507 case LSC_SCODE_NOPCB: 2508 case LSC_SCODE_ELS_REJECT: 2509 case LSC_SCODE_CMD_PARAM_ERR: 2510 case LSC_SCODE_NONPORT: 2511 case LSC_SCODE_LOGGED_IN: 2512 case LSC_SCODE_NOFLOGI_ACC: 2513 default: 2514 mb[0] = MBS_COMMAND_ERROR; 2515 break; 2516 } 2517 } else { 2518 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066, 2519 "Done %s.\n", __func__); 2520 2521 iop[0] = le32_to_cpu(lg->io_parameter[0]); 2522 2523 mb[0] = MBS_COMMAND_COMPLETE; 2524 mb[1] = 0; 2525 if (iop[0] & BIT_4) { 2526 if (iop[0] & BIT_8) 2527 mb[1] |= BIT_1; 2528 } else 2529 mb[1] = BIT_0; 2530 2531 /* Passback COS information. */ 2532 mb[10] = 0; 2533 if (lg->io_parameter[7] || lg->io_parameter[8]) 2534 mb[10] |= BIT_0; /* Class 2. */ 2535 if (lg->io_parameter[9] || lg->io_parameter[10]) 2536 mb[10] |= BIT_1; /* Class 3. */ 2537 if (lg->io_parameter[0] & cpu_to_le32(BIT_7)) 2538 mb[10] |= BIT_7; /* Confirmed Completion 2539 * Allowed 2540 */ 2541 } 2542 2543 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2544 2545 return rval; 2546 } 2547 2548 /* 2549 * qla2x00_login_fabric 2550 * Issue login fabric port mailbox command. 2551 * 2552 * Input: 2553 * ha = adapter block pointer. 2554 * loop_id = device loop ID. 2555 * domain = device domain. 2556 * area = device area. 2557 * al_pa = device AL_PA. 2558 * status = pointer for return status. 2559 * opt = command options. 2560 * TARGET_QUEUE_LOCK must be released. 2561 * ADAPTER_STATE_LOCK must be released. 2562 * 2563 * Returns: 2564 * qla2x00 local function return status code. 2565 * 2566 * Context: 2567 * Kernel context. 2568 */ 2569 int 2570 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2571 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt) 2572 { 2573 int rval; 2574 mbx_cmd_t mc; 2575 mbx_cmd_t *mcp = &mc; 2576 struct qla_hw_data *ha = vha->hw; 2577 2578 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067, 2579 "Entered %s.\n", __func__); 2580 2581 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT; 2582 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2583 if (HAS_EXTENDED_IDS(ha)) { 2584 mcp->mb[1] = loop_id; 2585 mcp->mb[10] = opt; 2586 mcp->out_mb |= MBX_10; 2587 } else { 2588 mcp->mb[1] = (loop_id << 8) | opt; 2589 } 2590 mcp->mb[2] = domain; 2591 mcp->mb[3] = area << 8 | al_pa; 2592 2593 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0; 2594 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2595 mcp->flags = 0; 2596 rval = qla2x00_mailbox_command(vha, mcp); 2597 2598 /* Return mailbox statuses. */ 2599 if (mb != NULL) { 2600 mb[0] = mcp->mb[0]; 2601 mb[1] = mcp->mb[1]; 2602 mb[2] = mcp->mb[2]; 2603 mb[6] = mcp->mb[6]; 2604 mb[7] = mcp->mb[7]; 2605 /* COS retrieved from Get-Port-Database mailbox command. */ 2606 mb[10] = 0; 2607 } 2608 2609 if (rval != QLA_SUCCESS) { 2610 /* RLU tmp code: need to change main mailbox_command function to 2611 * return ok even when the mailbox completion value is not 2612 * SUCCESS. The caller needs to be responsible to interpret 2613 * the return values of this mailbox command if we're not 2614 * to change too much of the existing code. 2615 */ 2616 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 || 2617 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 || 2618 mcp->mb[0] == 0x4006) 2619 rval = QLA_SUCCESS; 2620 2621 /*EMPTY*/ 2622 ql_dbg(ql_dbg_mbx, vha, 0x1068, 2623 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 2624 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 2625 } else { 2626 /*EMPTY*/ 2627 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069, 2628 "Done %s.\n", __func__); 2629 } 2630 2631 return rval; 2632 } 2633 2634 /* 2635 * qla2x00_login_local_device 2636 * Issue login loop port mailbox command. 2637 * 2638 * Input: 2639 * ha = adapter block pointer. 2640 * loop_id = device loop ID. 2641 * opt = command options. 2642 * 2643 * Returns: 2644 * Return status code. 2645 * 2646 * Context: 2647 * Kernel context. 2648 * 2649 */ 2650 int 2651 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport, 2652 uint16_t *mb_ret, uint8_t opt) 2653 { 2654 int rval; 2655 mbx_cmd_t mc; 2656 mbx_cmd_t *mcp = &mc; 2657 struct qla_hw_data *ha = vha->hw; 2658 2659 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a, 2660 "Entered %s.\n", __func__); 2661 2662 if (IS_FWI2_CAPABLE(ha)) 2663 return qla24xx_login_fabric(vha, fcport->loop_id, 2664 fcport->d_id.b.domain, fcport->d_id.b.area, 2665 fcport->d_id.b.al_pa, mb_ret, opt); 2666 2667 mcp->mb[0] = MBC_LOGIN_LOOP_PORT; 2668 if (HAS_EXTENDED_IDS(ha)) 2669 mcp->mb[1] = fcport->loop_id; 2670 else 2671 mcp->mb[1] = fcport->loop_id << 8; 2672 mcp->mb[2] = opt; 2673 mcp->out_mb = MBX_2|MBX_1|MBX_0; 2674 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0; 2675 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 2676 mcp->flags = 0; 2677 rval = qla2x00_mailbox_command(vha, mcp); 2678 2679 /* Return mailbox statuses. */ 2680 if (mb_ret != NULL) { 2681 mb_ret[0] = mcp->mb[0]; 2682 mb_ret[1] = mcp->mb[1]; 2683 mb_ret[6] = mcp->mb[6]; 2684 mb_ret[7] = mcp->mb[7]; 2685 } 2686 2687 if (rval != QLA_SUCCESS) { 2688 /* AV tmp code: need to change main mailbox_command function to 2689 * return ok even when the mailbox completion value is not 2690 * SUCCESS. The caller needs to be responsible to interpret 2691 * the return values of this mailbox command if we're not 2692 * to change too much of the existing code. 2693 */ 2694 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006) 2695 rval = QLA_SUCCESS; 2696 2697 ql_dbg(ql_dbg_mbx, vha, 0x106b, 2698 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n", 2699 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]); 2700 } else { 2701 /*EMPTY*/ 2702 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c, 2703 "Done %s.\n", __func__); 2704 } 2705 2706 return (rval); 2707 } 2708 2709 int 2710 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2711 uint8_t area, uint8_t al_pa) 2712 { 2713 int rval; 2714 struct logio_entry_24xx *lg; 2715 dma_addr_t lg_dma; 2716 struct qla_hw_data *ha = vha->hw; 2717 struct req_que *req; 2718 2719 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d, 2720 "Entered %s.\n", __func__); 2721 2722 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma); 2723 if (lg == NULL) { 2724 ql_log(ql_log_warn, vha, 0x106e, 2725 "Failed to allocate logout IOCB.\n"); 2726 return QLA_MEMORY_ALLOC_FAILED; 2727 } 2728 2729 req = vha->req; 2730 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE; 2731 lg->entry_count = 1; 2732 lg->handle = make_handle(req->id, lg->handle); 2733 lg->nport_handle = cpu_to_le16(loop_id); 2734 lg->control_flags = 2735 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO| 2736 LCF_FREE_NPORT); 2737 lg->port_id[0] = al_pa; 2738 lg->port_id[1] = area; 2739 lg->port_id[2] = domain; 2740 lg->vp_index = vha->vp_idx; 2741 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0, 2742 (ha->r_a_tov / 10 * 2) + 2); 2743 if (rval != QLA_SUCCESS) { 2744 ql_dbg(ql_dbg_mbx, vha, 0x106f, 2745 "Failed to issue logout IOCB (%x).\n", rval); 2746 } else if (lg->entry_status != 0) { 2747 ql_dbg(ql_dbg_mbx, vha, 0x1070, 2748 "Failed to complete IOCB -- error status (%x).\n", 2749 lg->entry_status); 2750 rval = QLA_FUNCTION_FAILED; 2751 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) { 2752 ql_dbg(ql_dbg_mbx, vha, 0x1071, 2753 "Failed to complete IOCB -- completion status (%x) " 2754 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status), 2755 le32_to_cpu(lg->io_parameter[0]), 2756 le32_to_cpu(lg->io_parameter[1])); 2757 } else { 2758 /*EMPTY*/ 2759 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072, 2760 "Done %s.\n", __func__); 2761 } 2762 2763 dma_pool_free(ha->s_dma_pool, lg, lg_dma); 2764 2765 return rval; 2766 } 2767 2768 /* 2769 * qla2x00_fabric_logout 2770 * Issue logout fabric port mailbox command. 2771 * 2772 * Input: 2773 * ha = adapter block pointer. 2774 * loop_id = device loop ID. 2775 * TARGET_QUEUE_LOCK must be released. 2776 * ADAPTER_STATE_LOCK must be released. 2777 * 2778 * Returns: 2779 * qla2x00 local function return status code. 2780 * 2781 * Context: 2782 * Kernel context. 2783 */ 2784 int 2785 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain, 2786 uint8_t area, uint8_t al_pa) 2787 { 2788 int rval; 2789 mbx_cmd_t mc; 2790 mbx_cmd_t *mcp = &mc; 2791 2792 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073, 2793 "Entered %s.\n", __func__); 2794 2795 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT; 2796 mcp->out_mb = MBX_1|MBX_0; 2797 if (HAS_EXTENDED_IDS(vha->hw)) { 2798 mcp->mb[1] = loop_id; 2799 mcp->mb[10] = 0; 2800 mcp->out_mb |= MBX_10; 2801 } else { 2802 mcp->mb[1] = loop_id << 8; 2803 } 2804 2805 mcp->in_mb = MBX_1|MBX_0; 2806 mcp->tov = MBX_TOV_SECONDS; 2807 mcp->flags = 0; 2808 rval = qla2x00_mailbox_command(vha, mcp); 2809 2810 if (rval != QLA_SUCCESS) { 2811 /*EMPTY*/ 2812 ql_dbg(ql_dbg_mbx, vha, 0x1074, 2813 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]); 2814 } else { 2815 /*EMPTY*/ 2816 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075, 2817 "Done %s.\n", __func__); 2818 } 2819 2820 return rval; 2821 } 2822 2823 /* 2824 * qla2x00_full_login_lip 2825 * Issue full login LIP mailbox command. 2826 * 2827 * Input: 2828 * ha = adapter block pointer. 2829 * TARGET_QUEUE_LOCK must be released. 2830 * ADAPTER_STATE_LOCK must be released. 2831 * 2832 * Returns: 2833 * qla2x00 local function return status code. 2834 * 2835 * Context: 2836 * Kernel context. 2837 */ 2838 int 2839 qla2x00_full_login_lip(scsi_qla_host_t *vha) 2840 { 2841 int rval; 2842 mbx_cmd_t mc; 2843 mbx_cmd_t *mcp = &mc; 2844 2845 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076, 2846 "Entered %s.\n", __func__); 2847 2848 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 2849 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_4 : 0; 2850 mcp->mb[2] = 0; 2851 mcp->mb[3] = 0; 2852 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 2853 mcp->in_mb = MBX_0; 2854 mcp->tov = MBX_TOV_SECONDS; 2855 mcp->flags = 0; 2856 rval = qla2x00_mailbox_command(vha, mcp); 2857 2858 if (rval != QLA_SUCCESS) { 2859 /*EMPTY*/ 2860 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval); 2861 } else { 2862 /*EMPTY*/ 2863 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078, 2864 "Done %s.\n", __func__); 2865 } 2866 2867 return rval; 2868 } 2869 2870 /* 2871 * qla2x00_get_id_list 2872 * 2873 * Input: 2874 * ha = adapter block pointer. 2875 * 2876 * Returns: 2877 * qla2x00 local function return status code. 2878 * 2879 * Context: 2880 * Kernel context. 2881 */ 2882 int 2883 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma, 2884 uint16_t *entries) 2885 { 2886 int rval; 2887 mbx_cmd_t mc; 2888 mbx_cmd_t *mcp = &mc; 2889 2890 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079, 2891 "Entered %s.\n", __func__); 2892 2893 if (id_list == NULL) 2894 return QLA_FUNCTION_FAILED; 2895 2896 mcp->mb[0] = MBC_GET_ID_LIST; 2897 mcp->out_mb = MBX_0; 2898 if (IS_FWI2_CAPABLE(vha->hw)) { 2899 mcp->mb[2] = MSW(id_list_dma); 2900 mcp->mb[3] = LSW(id_list_dma); 2901 mcp->mb[6] = MSW(MSD(id_list_dma)); 2902 mcp->mb[7] = LSW(MSD(id_list_dma)); 2903 mcp->mb[8] = 0; 2904 mcp->mb[9] = vha->vp_idx; 2905 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2; 2906 } else { 2907 mcp->mb[1] = MSW(id_list_dma); 2908 mcp->mb[2] = LSW(id_list_dma); 2909 mcp->mb[3] = MSW(MSD(id_list_dma)); 2910 mcp->mb[6] = LSW(MSD(id_list_dma)); 2911 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1; 2912 } 2913 mcp->in_mb = MBX_1|MBX_0; 2914 mcp->tov = MBX_TOV_SECONDS; 2915 mcp->flags = 0; 2916 rval = qla2x00_mailbox_command(vha, mcp); 2917 2918 if (rval != QLA_SUCCESS) { 2919 /*EMPTY*/ 2920 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval); 2921 } else { 2922 *entries = mcp->mb[1]; 2923 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b, 2924 "Done %s.\n", __func__); 2925 } 2926 2927 return rval; 2928 } 2929 2930 /* 2931 * qla2x00_get_resource_cnts 2932 * Get current firmware resource counts. 2933 * 2934 * Input: 2935 * ha = adapter block pointer. 2936 * 2937 * Returns: 2938 * qla2x00 local function return status code. 2939 * 2940 * Context: 2941 * Kernel context. 2942 */ 2943 int 2944 qla2x00_get_resource_cnts(scsi_qla_host_t *vha) 2945 { 2946 struct qla_hw_data *ha = vha->hw; 2947 int rval; 2948 mbx_cmd_t mc; 2949 mbx_cmd_t *mcp = &mc; 2950 2951 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c, 2952 "Entered %s.\n", __func__); 2953 2954 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS; 2955 mcp->out_mb = MBX_0; 2956 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 2957 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || 2958 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2959 mcp->in_mb |= MBX_12; 2960 mcp->tov = MBX_TOV_SECONDS; 2961 mcp->flags = 0; 2962 rval = qla2x00_mailbox_command(vha, mcp); 2963 2964 if (rval != QLA_SUCCESS) { 2965 /*EMPTY*/ 2966 ql_dbg(ql_dbg_mbx, vha, 0x107d, 2967 "Failed mb[0]=%x.\n", mcp->mb[0]); 2968 } else { 2969 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e, 2970 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x " 2971 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2], 2972 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10], 2973 mcp->mb[11], mcp->mb[12]); 2974 2975 ha->orig_fw_tgt_xcb_count = mcp->mb[1]; 2976 ha->cur_fw_tgt_xcb_count = mcp->mb[2]; 2977 ha->cur_fw_xcb_count = mcp->mb[3]; 2978 ha->orig_fw_xcb_count = mcp->mb[6]; 2979 ha->cur_fw_iocb_count = mcp->mb[7]; 2980 ha->orig_fw_iocb_count = mcp->mb[10]; 2981 if (ha->flags.npiv_supported) 2982 ha->max_npiv_vports = mcp->mb[11]; 2983 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 2984 IS_QLA28XX(ha)) 2985 ha->fw_max_fcf_count = mcp->mb[12]; 2986 } 2987 2988 return (rval); 2989 } 2990 2991 /* 2992 * qla2x00_get_fcal_position_map 2993 * Get FCAL (LILP) position map using mailbox command 2994 * 2995 * Input: 2996 * ha = adapter state pointer. 2997 * pos_map = buffer pointer (can be NULL). 2998 * 2999 * Returns: 3000 * qla2x00 local function return status code. 3001 * 3002 * Context: 3003 * Kernel context. 3004 */ 3005 int 3006 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map) 3007 { 3008 int rval; 3009 mbx_cmd_t mc; 3010 mbx_cmd_t *mcp = &mc; 3011 char *pmap; 3012 dma_addr_t pmap_dma; 3013 struct qla_hw_data *ha = vha->hw; 3014 3015 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f, 3016 "Entered %s.\n", __func__); 3017 3018 pmap = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma); 3019 if (pmap == NULL) { 3020 ql_log(ql_log_warn, vha, 0x1080, 3021 "Memory alloc failed.\n"); 3022 return QLA_MEMORY_ALLOC_FAILED; 3023 } 3024 3025 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP; 3026 mcp->mb[2] = MSW(pmap_dma); 3027 mcp->mb[3] = LSW(pmap_dma); 3028 mcp->mb[6] = MSW(MSD(pmap_dma)); 3029 mcp->mb[7] = LSW(MSD(pmap_dma)); 3030 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 3031 mcp->in_mb = MBX_1|MBX_0; 3032 mcp->buf_size = FCAL_MAP_SIZE; 3033 mcp->flags = MBX_DMA_IN; 3034 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 3035 rval = qla2x00_mailbox_command(vha, mcp); 3036 3037 if (rval == QLA_SUCCESS) { 3038 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081, 3039 "mb0/mb1=%x/%X FC/AL position map size (%x).\n", 3040 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]); 3041 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d, 3042 pmap, pmap[0] + 1); 3043 3044 if (pos_map) 3045 memcpy(pos_map, pmap, FCAL_MAP_SIZE); 3046 } 3047 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma); 3048 3049 if (rval != QLA_SUCCESS) { 3050 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval); 3051 } else { 3052 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083, 3053 "Done %s.\n", __func__); 3054 } 3055 3056 return rval; 3057 } 3058 3059 /* 3060 * qla2x00_get_link_status 3061 * 3062 * Input: 3063 * ha = adapter block pointer. 3064 * loop_id = device loop ID. 3065 * ret_buf = pointer to link status return buffer. 3066 * 3067 * Returns: 3068 * 0 = success. 3069 * BIT_0 = mem alloc error. 3070 * BIT_1 = mailbox error. 3071 */ 3072 int 3073 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id, 3074 struct link_statistics *stats, dma_addr_t stats_dma) 3075 { 3076 int rval; 3077 mbx_cmd_t mc; 3078 mbx_cmd_t *mcp = &mc; 3079 uint32_t *iter = (uint32_t *)stats; 3080 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter); 3081 struct qla_hw_data *ha = vha->hw; 3082 3083 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084, 3084 "Entered %s.\n", __func__); 3085 3086 mcp->mb[0] = MBC_GET_LINK_STATUS; 3087 mcp->mb[2] = MSW(LSD(stats_dma)); 3088 mcp->mb[3] = LSW(LSD(stats_dma)); 3089 mcp->mb[6] = MSW(MSD(stats_dma)); 3090 mcp->mb[7] = LSW(MSD(stats_dma)); 3091 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 3092 mcp->in_mb = MBX_0; 3093 if (IS_FWI2_CAPABLE(ha)) { 3094 mcp->mb[1] = loop_id; 3095 mcp->mb[4] = 0; 3096 mcp->mb[10] = 0; 3097 mcp->out_mb |= MBX_10|MBX_4|MBX_1; 3098 mcp->in_mb |= MBX_1; 3099 } else if (HAS_EXTENDED_IDS(ha)) { 3100 mcp->mb[1] = loop_id; 3101 mcp->mb[10] = 0; 3102 mcp->out_mb |= MBX_10|MBX_1; 3103 } else { 3104 mcp->mb[1] = loop_id << 8; 3105 mcp->out_mb |= MBX_1; 3106 } 3107 mcp->tov = MBX_TOV_SECONDS; 3108 mcp->flags = IOCTL_CMD; 3109 rval = qla2x00_mailbox_command(vha, mcp); 3110 3111 if (rval == QLA_SUCCESS) { 3112 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 3113 ql_dbg(ql_dbg_mbx, vha, 0x1085, 3114 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3115 rval = QLA_FUNCTION_FAILED; 3116 } else { 3117 /* Re-endianize - firmware data is le32. */ 3118 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086, 3119 "Done %s.\n", __func__); 3120 for ( ; dwords--; iter++) 3121 le32_to_cpus(iter); 3122 } 3123 } else { 3124 /* Failed. */ 3125 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval); 3126 } 3127 3128 return rval; 3129 } 3130 3131 int 3132 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats, 3133 dma_addr_t stats_dma, uint16_t options) 3134 { 3135 int rval; 3136 mbx_cmd_t mc; 3137 mbx_cmd_t *mcp = &mc; 3138 uint32_t *iter = (uint32_t *)stats; 3139 ushort dwords = sizeof(*stats)/sizeof(*iter); 3140 3141 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088, 3142 "Entered %s.\n", __func__); 3143 3144 memset(&mc, 0, sizeof(mc)); 3145 mc.mb[0] = MBC_GET_LINK_PRIV_STATS; 3146 mc.mb[2] = MSW(LSD(stats_dma)); 3147 mc.mb[3] = LSW(LSD(stats_dma)); 3148 mc.mb[6] = MSW(MSD(stats_dma)); 3149 mc.mb[7] = LSW(MSD(stats_dma)); 3150 mc.mb[8] = dwords; 3151 mc.mb[9] = vha->vp_idx; 3152 mc.mb[10] = options; 3153 3154 rval = qla24xx_send_mb_cmd(vha, &mc); 3155 3156 if (rval == QLA_SUCCESS) { 3157 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 3158 ql_dbg(ql_dbg_mbx, vha, 0x1089, 3159 "Failed mb[0]=%x.\n", mcp->mb[0]); 3160 rval = QLA_FUNCTION_FAILED; 3161 } else { 3162 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a, 3163 "Done %s.\n", __func__); 3164 /* Re-endianize - firmware data is le32. */ 3165 for ( ; dwords--; iter++) 3166 le32_to_cpus(iter); 3167 } 3168 } else { 3169 /* Failed. */ 3170 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval); 3171 } 3172 3173 return rval; 3174 } 3175 3176 int 3177 qla24xx_abort_command(srb_t *sp) 3178 { 3179 int rval; 3180 unsigned long flags = 0; 3181 3182 struct abort_entry_24xx *abt; 3183 dma_addr_t abt_dma; 3184 uint32_t handle; 3185 fc_port_t *fcport = sp->fcport; 3186 struct scsi_qla_host *vha = fcport->vha; 3187 struct qla_hw_data *ha = vha->hw; 3188 struct req_que *req = vha->req; 3189 struct qla_qpair *qpair = sp->qpair; 3190 3191 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c, 3192 "Entered %s.\n", __func__); 3193 3194 if (sp->qpair) 3195 req = sp->qpair->req; 3196 else 3197 return QLA_FUNCTION_FAILED; 3198 3199 if (ql2xasynctmfenable) 3200 return qla24xx_async_abort_command(sp); 3201 3202 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 3203 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 3204 if (req->outstanding_cmds[handle] == sp) 3205 break; 3206 } 3207 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 3208 if (handle == req->num_outstanding_cmds) { 3209 /* Command not found. */ 3210 return QLA_FUNCTION_FAILED; 3211 } 3212 3213 abt = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma); 3214 if (abt == NULL) { 3215 ql_log(ql_log_warn, vha, 0x108d, 3216 "Failed to allocate abort IOCB.\n"); 3217 return QLA_MEMORY_ALLOC_FAILED; 3218 } 3219 3220 abt->entry_type = ABORT_IOCB_TYPE; 3221 abt->entry_count = 1; 3222 abt->handle = make_handle(req->id, abt->handle); 3223 abt->nport_handle = cpu_to_le16(fcport->loop_id); 3224 abt->handle_to_abort = make_handle(req->id, handle); 3225 abt->port_id[0] = fcport->d_id.b.al_pa; 3226 abt->port_id[1] = fcport->d_id.b.area; 3227 abt->port_id[2] = fcport->d_id.b.domain; 3228 abt->vp_index = fcport->vha->vp_idx; 3229 3230 abt->req_que_no = cpu_to_le16(req->id); 3231 3232 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0); 3233 if (rval != QLA_SUCCESS) { 3234 ql_dbg(ql_dbg_mbx, vha, 0x108e, 3235 "Failed to issue IOCB (%x).\n", rval); 3236 } else if (abt->entry_status != 0) { 3237 ql_dbg(ql_dbg_mbx, vha, 0x108f, 3238 "Failed to complete IOCB -- error status (%x).\n", 3239 abt->entry_status); 3240 rval = QLA_FUNCTION_FAILED; 3241 } else if (abt->nport_handle != cpu_to_le16(0)) { 3242 ql_dbg(ql_dbg_mbx, vha, 0x1090, 3243 "Failed to complete IOCB -- completion status (%x).\n", 3244 le16_to_cpu(abt->nport_handle)); 3245 if (abt->nport_handle == cpu_to_le16(CS_IOCB_ERROR)) 3246 rval = QLA_FUNCTION_PARAMETER_ERROR; 3247 else 3248 rval = QLA_FUNCTION_FAILED; 3249 } else { 3250 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091, 3251 "Done %s.\n", __func__); 3252 } 3253 3254 dma_pool_free(ha->s_dma_pool, abt, abt_dma); 3255 3256 return rval; 3257 } 3258 3259 struct tsk_mgmt_cmd { 3260 union { 3261 struct tsk_mgmt_entry tsk; 3262 struct sts_entry_24xx sts; 3263 } p; 3264 }; 3265 3266 static int 3267 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport, 3268 uint64_t l, int tag) 3269 { 3270 int rval, rval2; 3271 struct tsk_mgmt_cmd *tsk; 3272 struct sts_entry_24xx *sts; 3273 dma_addr_t tsk_dma; 3274 scsi_qla_host_t *vha; 3275 struct qla_hw_data *ha; 3276 struct req_que *req; 3277 struct qla_qpair *qpair; 3278 3279 vha = fcport->vha; 3280 ha = vha->hw; 3281 req = vha->req; 3282 3283 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092, 3284 "Entered %s.\n", __func__); 3285 3286 if (vha->vp_idx && vha->qpair) { 3287 /* NPIV port */ 3288 qpair = vha->qpair; 3289 req = qpair->req; 3290 } 3291 3292 tsk = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma); 3293 if (tsk == NULL) { 3294 ql_log(ql_log_warn, vha, 0x1093, 3295 "Failed to allocate task management IOCB.\n"); 3296 return QLA_MEMORY_ALLOC_FAILED; 3297 } 3298 3299 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE; 3300 tsk->p.tsk.entry_count = 1; 3301 tsk->p.tsk.handle = make_handle(req->id, tsk->p.tsk.handle); 3302 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id); 3303 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2); 3304 tsk->p.tsk.control_flags = cpu_to_le32(type); 3305 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa; 3306 tsk->p.tsk.port_id[1] = fcport->d_id.b.area; 3307 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain; 3308 tsk->p.tsk.vp_index = fcport->vha->vp_idx; 3309 if (type == TCF_LUN_RESET) { 3310 int_to_scsilun(l, &tsk->p.tsk.lun); 3311 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun, 3312 sizeof(tsk->p.tsk.lun)); 3313 } 3314 3315 sts = &tsk->p.sts; 3316 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0); 3317 if (rval != QLA_SUCCESS) { 3318 ql_dbg(ql_dbg_mbx, vha, 0x1094, 3319 "Failed to issue %s reset IOCB (%x).\n", name, rval); 3320 } else if (sts->entry_status != 0) { 3321 ql_dbg(ql_dbg_mbx, vha, 0x1095, 3322 "Failed to complete IOCB -- error status (%x).\n", 3323 sts->entry_status); 3324 rval = QLA_FUNCTION_FAILED; 3325 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) { 3326 ql_dbg(ql_dbg_mbx, vha, 0x1096, 3327 "Failed to complete IOCB -- completion status (%x).\n", 3328 le16_to_cpu(sts->comp_status)); 3329 rval = QLA_FUNCTION_FAILED; 3330 } else if (le16_to_cpu(sts->scsi_status) & 3331 SS_RESPONSE_INFO_LEN_VALID) { 3332 if (le32_to_cpu(sts->rsp_data_len) < 4) { 3333 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097, 3334 "Ignoring inconsistent data length -- not enough " 3335 "response info (%d).\n", 3336 le32_to_cpu(sts->rsp_data_len)); 3337 } else if (sts->data[3]) { 3338 ql_dbg(ql_dbg_mbx, vha, 0x1098, 3339 "Failed to complete IOCB -- response (%x).\n", 3340 sts->data[3]); 3341 rval = QLA_FUNCTION_FAILED; 3342 } 3343 } 3344 3345 /* Issue marker IOCB. */ 3346 rval2 = qla2x00_marker(vha, ha->base_qpair, fcport->loop_id, l, 3347 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID); 3348 if (rval2 != QLA_SUCCESS) { 3349 ql_dbg(ql_dbg_mbx, vha, 0x1099, 3350 "Failed to issue marker IOCB (%x).\n", rval2); 3351 } else { 3352 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a, 3353 "Done %s.\n", __func__); 3354 } 3355 3356 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma); 3357 3358 return rval; 3359 } 3360 3361 int 3362 qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag) 3363 { 3364 struct qla_hw_data *ha = fcport->vha->hw; 3365 3366 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 3367 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag); 3368 3369 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag); 3370 } 3371 3372 int 3373 qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag) 3374 { 3375 struct qla_hw_data *ha = fcport->vha->hw; 3376 3377 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha)) 3378 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag); 3379 3380 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag); 3381 } 3382 3383 int 3384 qla2x00_system_error(scsi_qla_host_t *vha) 3385 { 3386 int rval; 3387 mbx_cmd_t mc; 3388 mbx_cmd_t *mcp = &mc; 3389 struct qla_hw_data *ha = vha->hw; 3390 3391 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha)) 3392 return QLA_FUNCTION_FAILED; 3393 3394 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b, 3395 "Entered %s.\n", __func__); 3396 3397 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR; 3398 mcp->out_mb = MBX_0; 3399 mcp->in_mb = MBX_0; 3400 mcp->tov = 5; 3401 mcp->flags = 0; 3402 rval = qla2x00_mailbox_command(vha, mcp); 3403 3404 if (rval != QLA_SUCCESS) { 3405 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval); 3406 } else { 3407 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d, 3408 "Done %s.\n", __func__); 3409 } 3410 3411 return rval; 3412 } 3413 3414 int 3415 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data) 3416 { 3417 int rval; 3418 mbx_cmd_t mc; 3419 mbx_cmd_t *mcp = &mc; 3420 3421 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 3422 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw)) 3423 return QLA_FUNCTION_FAILED; 3424 3425 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182, 3426 "Entered %s.\n", __func__); 3427 3428 mcp->mb[0] = MBC_WRITE_SERDES; 3429 mcp->mb[1] = addr; 3430 if (IS_QLA2031(vha->hw)) 3431 mcp->mb[2] = data & 0xff; 3432 else 3433 mcp->mb[2] = data; 3434 3435 mcp->mb[3] = 0; 3436 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 3437 mcp->in_mb = MBX_0; 3438 mcp->tov = MBX_TOV_SECONDS; 3439 mcp->flags = 0; 3440 rval = qla2x00_mailbox_command(vha, mcp); 3441 3442 if (rval != QLA_SUCCESS) { 3443 ql_dbg(ql_dbg_mbx, vha, 0x1183, 3444 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3445 } else { 3446 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184, 3447 "Done %s.\n", __func__); 3448 } 3449 3450 return rval; 3451 } 3452 3453 int 3454 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data) 3455 { 3456 int rval; 3457 mbx_cmd_t mc; 3458 mbx_cmd_t *mcp = &mc; 3459 3460 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) && 3461 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw)) 3462 return QLA_FUNCTION_FAILED; 3463 3464 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185, 3465 "Entered %s.\n", __func__); 3466 3467 mcp->mb[0] = MBC_READ_SERDES; 3468 mcp->mb[1] = addr; 3469 mcp->mb[3] = 0; 3470 mcp->out_mb = MBX_3|MBX_1|MBX_0; 3471 mcp->in_mb = MBX_1|MBX_0; 3472 mcp->tov = MBX_TOV_SECONDS; 3473 mcp->flags = 0; 3474 rval = qla2x00_mailbox_command(vha, mcp); 3475 3476 if (IS_QLA2031(vha->hw)) 3477 *data = mcp->mb[1] & 0xff; 3478 else 3479 *data = mcp->mb[1]; 3480 3481 if (rval != QLA_SUCCESS) { 3482 ql_dbg(ql_dbg_mbx, vha, 0x1186, 3483 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3484 } else { 3485 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187, 3486 "Done %s.\n", __func__); 3487 } 3488 3489 return rval; 3490 } 3491 3492 int 3493 qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) 3494 { 3495 int rval; 3496 mbx_cmd_t mc; 3497 mbx_cmd_t *mcp = &mc; 3498 3499 if (!IS_QLA8044(vha->hw)) 3500 return QLA_FUNCTION_FAILED; 3501 3502 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x11a0, 3503 "Entered %s.\n", __func__); 3504 3505 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 3506 mcp->mb[1] = HCS_WRITE_SERDES; 3507 mcp->mb[3] = LSW(addr); 3508 mcp->mb[4] = MSW(addr); 3509 mcp->mb[5] = LSW(data); 3510 mcp->mb[6] = MSW(data); 3511 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0; 3512 mcp->in_mb = MBX_0; 3513 mcp->tov = MBX_TOV_SECONDS; 3514 mcp->flags = 0; 3515 rval = qla2x00_mailbox_command(vha, mcp); 3516 3517 if (rval != QLA_SUCCESS) { 3518 ql_dbg(ql_dbg_mbx, vha, 0x11a1, 3519 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3520 } else { 3521 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188, 3522 "Done %s.\n", __func__); 3523 } 3524 3525 return rval; 3526 } 3527 3528 int 3529 qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) 3530 { 3531 int rval; 3532 mbx_cmd_t mc; 3533 mbx_cmd_t *mcp = &mc; 3534 3535 if (!IS_QLA8044(vha->hw)) 3536 return QLA_FUNCTION_FAILED; 3537 3538 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189, 3539 "Entered %s.\n", __func__); 3540 3541 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG; 3542 mcp->mb[1] = HCS_READ_SERDES; 3543 mcp->mb[3] = LSW(addr); 3544 mcp->mb[4] = MSW(addr); 3545 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0; 3546 mcp->in_mb = MBX_2|MBX_1|MBX_0; 3547 mcp->tov = MBX_TOV_SECONDS; 3548 mcp->flags = 0; 3549 rval = qla2x00_mailbox_command(vha, mcp); 3550 3551 *data = mcp->mb[2] << 16 | mcp->mb[1]; 3552 3553 if (rval != QLA_SUCCESS) { 3554 ql_dbg(ql_dbg_mbx, vha, 0x118a, 3555 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3556 } else { 3557 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b, 3558 "Done %s.\n", __func__); 3559 } 3560 3561 return rval; 3562 } 3563 3564 /** 3565 * qla2x00_set_serdes_params() - 3566 * @vha: HA context 3567 * @sw_em_1g: serial link options 3568 * @sw_em_2g: serial link options 3569 * @sw_em_4g: serial link options 3570 * 3571 * Returns 3572 */ 3573 int 3574 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g, 3575 uint16_t sw_em_2g, uint16_t sw_em_4g) 3576 { 3577 int rval; 3578 mbx_cmd_t mc; 3579 mbx_cmd_t *mcp = &mc; 3580 3581 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e, 3582 "Entered %s.\n", __func__); 3583 3584 mcp->mb[0] = MBC_SERDES_PARAMS; 3585 mcp->mb[1] = BIT_0; 3586 mcp->mb[2] = sw_em_1g | BIT_15; 3587 mcp->mb[3] = sw_em_2g | BIT_15; 3588 mcp->mb[4] = sw_em_4g | BIT_15; 3589 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3590 mcp->in_mb = MBX_0; 3591 mcp->tov = MBX_TOV_SECONDS; 3592 mcp->flags = 0; 3593 rval = qla2x00_mailbox_command(vha, mcp); 3594 3595 if (rval != QLA_SUCCESS) { 3596 /*EMPTY*/ 3597 ql_dbg(ql_dbg_mbx, vha, 0x109f, 3598 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 3599 } else { 3600 /*EMPTY*/ 3601 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0, 3602 "Done %s.\n", __func__); 3603 } 3604 3605 return rval; 3606 } 3607 3608 int 3609 qla2x00_stop_firmware(scsi_qla_host_t *vha) 3610 { 3611 int rval; 3612 mbx_cmd_t mc; 3613 mbx_cmd_t *mcp = &mc; 3614 3615 if (!IS_FWI2_CAPABLE(vha->hw)) 3616 return QLA_FUNCTION_FAILED; 3617 3618 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1, 3619 "Entered %s.\n", __func__); 3620 3621 mcp->mb[0] = MBC_STOP_FIRMWARE; 3622 mcp->mb[1] = 0; 3623 mcp->out_mb = MBX_1|MBX_0; 3624 mcp->in_mb = MBX_0; 3625 mcp->tov = 5; 3626 mcp->flags = 0; 3627 rval = qla2x00_mailbox_command(vha, mcp); 3628 3629 if (rval != QLA_SUCCESS) { 3630 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval); 3631 if (mcp->mb[0] == MBS_INVALID_COMMAND) 3632 rval = QLA_INVALID_COMMAND; 3633 } else { 3634 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3, 3635 "Done %s.\n", __func__); 3636 } 3637 3638 return rval; 3639 } 3640 3641 int 3642 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma, 3643 uint16_t buffers) 3644 { 3645 int rval; 3646 mbx_cmd_t mc; 3647 mbx_cmd_t *mcp = &mc; 3648 3649 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4, 3650 "Entered %s.\n", __func__); 3651 3652 if (!IS_FWI2_CAPABLE(vha->hw)) 3653 return QLA_FUNCTION_FAILED; 3654 3655 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3656 return QLA_FUNCTION_FAILED; 3657 3658 mcp->mb[0] = MBC_TRACE_CONTROL; 3659 mcp->mb[1] = TC_EFT_ENABLE; 3660 mcp->mb[2] = LSW(eft_dma); 3661 mcp->mb[3] = MSW(eft_dma); 3662 mcp->mb[4] = LSW(MSD(eft_dma)); 3663 mcp->mb[5] = MSW(MSD(eft_dma)); 3664 mcp->mb[6] = buffers; 3665 mcp->mb[7] = TC_AEN_DISABLE; 3666 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3667 mcp->in_mb = MBX_1|MBX_0; 3668 mcp->tov = MBX_TOV_SECONDS; 3669 mcp->flags = 0; 3670 rval = qla2x00_mailbox_command(vha, mcp); 3671 if (rval != QLA_SUCCESS) { 3672 ql_dbg(ql_dbg_mbx, vha, 0x10a5, 3673 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3674 rval, mcp->mb[0], mcp->mb[1]); 3675 } else { 3676 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6, 3677 "Done %s.\n", __func__); 3678 } 3679 3680 return rval; 3681 } 3682 3683 int 3684 qla2x00_disable_eft_trace(scsi_qla_host_t *vha) 3685 { 3686 int rval; 3687 mbx_cmd_t mc; 3688 mbx_cmd_t *mcp = &mc; 3689 3690 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7, 3691 "Entered %s.\n", __func__); 3692 3693 if (!IS_FWI2_CAPABLE(vha->hw)) 3694 return QLA_FUNCTION_FAILED; 3695 3696 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3697 return QLA_FUNCTION_FAILED; 3698 3699 mcp->mb[0] = MBC_TRACE_CONTROL; 3700 mcp->mb[1] = TC_EFT_DISABLE; 3701 mcp->out_mb = MBX_1|MBX_0; 3702 mcp->in_mb = MBX_1|MBX_0; 3703 mcp->tov = MBX_TOV_SECONDS; 3704 mcp->flags = 0; 3705 rval = qla2x00_mailbox_command(vha, mcp); 3706 if (rval != QLA_SUCCESS) { 3707 ql_dbg(ql_dbg_mbx, vha, 0x10a8, 3708 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3709 rval, mcp->mb[0], mcp->mb[1]); 3710 } else { 3711 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9, 3712 "Done %s.\n", __func__); 3713 } 3714 3715 return rval; 3716 } 3717 3718 int 3719 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma, 3720 uint16_t buffers, uint16_t *mb, uint32_t *dwords) 3721 { 3722 int rval; 3723 mbx_cmd_t mc; 3724 mbx_cmd_t *mcp = &mc; 3725 3726 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa, 3727 "Entered %s.\n", __func__); 3728 3729 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) && 3730 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) && 3731 !IS_QLA28XX(vha->hw)) 3732 return QLA_FUNCTION_FAILED; 3733 3734 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3735 return QLA_FUNCTION_FAILED; 3736 3737 mcp->mb[0] = MBC_TRACE_CONTROL; 3738 mcp->mb[1] = TC_FCE_ENABLE; 3739 mcp->mb[2] = LSW(fce_dma); 3740 mcp->mb[3] = MSW(fce_dma); 3741 mcp->mb[4] = LSW(MSD(fce_dma)); 3742 mcp->mb[5] = MSW(MSD(fce_dma)); 3743 mcp->mb[6] = buffers; 3744 mcp->mb[7] = TC_AEN_DISABLE; 3745 mcp->mb[8] = 0; 3746 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE; 3747 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE; 3748 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3749 MBX_1|MBX_0; 3750 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 3751 mcp->tov = MBX_TOV_SECONDS; 3752 mcp->flags = 0; 3753 rval = qla2x00_mailbox_command(vha, mcp); 3754 if (rval != QLA_SUCCESS) { 3755 ql_dbg(ql_dbg_mbx, vha, 0x10ab, 3756 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3757 rval, mcp->mb[0], mcp->mb[1]); 3758 } else { 3759 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac, 3760 "Done %s.\n", __func__); 3761 3762 if (mb) 3763 memcpy(mb, mcp->mb, 8 * sizeof(*mb)); 3764 if (dwords) 3765 *dwords = buffers; 3766 } 3767 3768 return rval; 3769 } 3770 3771 int 3772 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd) 3773 { 3774 int rval; 3775 mbx_cmd_t mc; 3776 mbx_cmd_t *mcp = &mc; 3777 3778 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad, 3779 "Entered %s.\n", __func__); 3780 3781 if (!IS_FWI2_CAPABLE(vha->hw)) 3782 return QLA_FUNCTION_FAILED; 3783 3784 if (unlikely(pci_channel_offline(vha->hw->pdev))) 3785 return QLA_FUNCTION_FAILED; 3786 3787 mcp->mb[0] = MBC_TRACE_CONTROL; 3788 mcp->mb[1] = TC_FCE_DISABLE; 3789 mcp->mb[2] = TC_FCE_DISABLE_TRACE; 3790 mcp->out_mb = MBX_2|MBX_1|MBX_0; 3791 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2| 3792 MBX_1|MBX_0; 3793 mcp->tov = MBX_TOV_SECONDS; 3794 mcp->flags = 0; 3795 rval = qla2x00_mailbox_command(vha, mcp); 3796 if (rval != QLA_SUCCESS) { 3797 ql_dbg(ql_dbg_mbx, vha, 0x10ae, 3798 "Failed=%x mb[0]=%x mb[1]=%x.\n", 3799 rval, mcp->mb[0], mcp->mb[1]); 3800 } else { 3801 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af, 3802 "Done %s.\n", __func__); 3803 3804 if (wr) 3805 *wr = (uint64_t) mcp->mb[5] << 48 | 3806 (uint64_t) mcp->mb[4] << 32 | 3807 (uint64_t) mcp->mb[3] << 16 | 3808 (uint64_t) mcp->mb[2]; 3809 if (rd) 3810 *rd = (uint64_t) mcp->mb[9] << 48 | 3811 (uint64_t) mcp->mb[8] << 32 | 3812 (uint64_t) mcp->mb[7] << 16 | 3813 (uint64_t) mcp->mb[6]; 3814 } 3815 3816 return rval; 3817 } 3818 3819 int 3820 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3821 uint16_t *port_speed, uint16_t *mb) 3822 { 3823 int rval; 3824 mbx_cmd_t mc; 3825 mbx_cmd_t *mcp = &mc; 3826 3827 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0, 3828 "Entered %s.\n", __func__); 3829 3830 if (!IS_IIDMA_CAPABLE(vha->hw)) 3831 return QLA_FUNCTION_FAILED; 3832 3833 mcp->mb[0] = MBC_PORT_PARAMS; 3834 mcp->mb[1] = loop_id; 3835 mcp->mb[2] = mcp->mb[3] = 0; 3836 mcp->mb[9] = vha->vp_idx; 3837 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3838 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3839 mcp->tov = MBX_TOV_SECONDS; 3840 mcp->flags = 0; 3841 rval = qla2x00_mailbox_command(vha, mcp); 3842 3843 /* Return mailbox statuses. */ 3844 if (mb) { 3845 mb[0] = mcp->mb[0]; 3846 mb[1] = mcp->mb[1]; 3847 mb[3] = mcp->mb[3]; 3848 } 3849 3850 if (rval != QLA_SUCCESS) { 3851 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval); 3852 } else { 3853 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2, 3854 "Done %s.\n", __func__); 3855 if (port_speed) 3856 *port_speed = mcp->mb[3]; 3857 } 3858 3859 return rval; 3860 } 3861 3862 int 3863 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, 3864 uint16_t port_speed, uint16_t *mb) 3865 { 3866 int rval; 3867 mbx_cmd_t mc; 3868 mbx_cmd_t *mcp = &mc; 3869 3870 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3, 3871 "Entered %s.\n", __func__); 3872 3873 if (!IS_IIDMA_CAPABLE(vha->hw)) 3874 return QLA_FUNCTION_FAILED; 3875 3876 mcp->mb[0] = MBC_PORT_PARAMS; 3877 mcp->mb[1] = loop_id; 3878 mcp->mb[2] = BIT_0; 3879 mcp->mb[3] = port_speed & 0x3F; 3880 mcp->mb[9] = vha->vp_idx; 3881 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0; 3882 mcp->in_mb = MBX_3|MBX_1|MBX_0; 3883 mcp->tov = MBX_TOV_SECONDS; 3884 mcp->flags = 0; 3885 rval = qla2x00_mailbox_command(vha, mcp); 3886 3887 /* Return mailbox statuses. */ 3888 if (mb) { 3889 mb[0] = mcp->mb[0]; 3890 mb[1] = mcp->mb[1]; 3891 mb[3] = mcp->mb[3]; 3892 } 3893 3894 if (rval != QLA_SUCCESS) { 3895 ql_dbg(ql_dbg_mbx, vha, 0x10b4, 3896 "Failed=%x.\n", rval); 3897 } else { 3898 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5, 3899 "Done %s.\n", __func__); 3900 } 3901 3902 return rval; 3903 } 3904 3905 void 3906 qla24xx_report_id_acquisition(scsi_qla_host_t *vha, 3907 struct vp_rpt_id_entry_24xx *rptid_entry) 3908 { 3909 struct qla_hw_data *ha = vha->hw; 3910 scsi_qla_host_t *vp = NULL; 3911 unsigned long flags; 3912 int found; 3913 port_id_t id; 3914 struct fc_port *fcport; 3915 3916 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6, 3917 "Entered %s.\n", __func__); 3918 3919 if (rptid_entry->entry_status != 0) 3920 return; 3921 3922 id.b.domain = rptid_entry->port_id[2]; 3923 id.b.area = rptid_entry->port_id[1]; 3924 id.b.al_pa = rptid_entry->port_id[0]; 3925 id.b.rsvd_1 = 0; 3926 ha->flags.n2n_ae = 0; 3927 3928 if (rptid_entry->format == 0) { 3929 /* loop */ 3930 ql_dbg(ql_dbg_async, vha, 0x10b7, 3931 "Format 0 : Number of VPs setup %d, number of " 3932 "VPs acquired %d.\n", rptid_entry->vp_setup, 3933 rptid_entry->vp_acquired); 3934 ql_dbg(ql_dbg_async, vha, 0x10b8, 3935 "Primary port id %02x%02x%02x.\n", 3936 rptid_entry->port_id[2], rptid_entry->port_id[1], 3937 rptid_entry->port_id[0]); 3938 ha->current_topology = ISP_CFG_NL; 3939 qlt_update_host_map(vha, id); 3940 3941 } else if (rptid_entry->format == 1) { 3942 /* fabric */ 3943 ql_dbg(ql_dbg_async, vha, 0x10b9, 3944 "Format 1: VP[%d] enabled - status %d - with " 3945 "port id %02x%02x%02x.\n", rptid_entry->vp_idx, 3946 rptid_entry->vp_status, 3947 rptid_entry->port_id[2], rptid_entry->port_id[1], 3948 rptid_entry->port_id[0]); 3949 ql_dbg(ql_dbg_async, vha, 0x5075, 3950 "Format 1: Remote WWPN %8phC.\n", 3951 rptid_entry->u.f1.port_name); 3952 3953 ql_dbg(ql_dbg_async, vha, 0x5075, 3954 "Format 1: WWPN %8phC.\n", 3955 vha->port_name); 3956 3957 switch (rptid_entry->u.f1.flags & TOPO_MASK) { 3958 case TOPO_N2N: 3959 ha->current_topology = ISP_CFG_N; 3960 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 3961 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3962 fcport->scan_state = QLA_FCPORT_SCAN; 3963 fcport->n2n_flag = 0; 3964 } 3965 id.b24 = 0; 3966 if (wwn_to_u64(vha->port_name) > 3967 wwn_to_u64(rptid_entry->u.f1.port_name)) { 3968 vha->d_id.b24 = 0; 3969 vha->d_id.b.al_pa = 1; 3970 ha->flags.n2n_bigger = 1; 3971 3972 id.b.al_pa = 2; 3973 ql_dbg(ql_dbg_async, vha, 0x5075, 3974 "Format 1: assign local id %x remote id %x\n", 3975 vha->d_id.b24, id.b24); 3976 } else { 3977 ql_dbg(ql_dbg_async, vha, 0x5075, 3978 "Format 1: Remote login - Waiting for WWPN %8phC.\n", 3979 rptid_entry->u.f1.port_name); 3980 ha->flags.n2n_bigger = 0; 3981 } 3982 3983 fcport = qla2x00_find_fcport_by_wwpn(vha, 3984 rptid_entry->u.f1.port_name, 1); 3985 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 3986 3987 3988 if (fcport) { 3989 fcport->plogi_nack_done_deadline = jiffies + HZ; 3990 fcport->dm_login_expire = jiffies + 2*HZ; 3991 fcport->scan_state = QLA_FCPORT_FOUND; 3992 fcport->n2n_flag = 1; 3993 fcport->keep_nport_handle = 1; 3994 fcport->fc4_type = FS_FC4TYPE_FCP; 3995 if (vha->flags.nvme_enabled) 3996 fcport->fc4_type |= FS_FC4TYPE_NVME; 3997 3998 if (wwn_to_u64(vha->port_name) > 3999 wwn_to_u64(fcport->port_name)) { 4000 fcport->d_id = id; 4001 } 4002 4003 switch (fcport->disc_state) { 4004 case DSC_DELETED: 4005 set_bit(RELOGIN_NEEDED, 4006 &vha->dpc_flags); 4007 break; 4008 case DSC_DELETE_PEND: 4009 break; 4010 default: 4011 qlt_schedule_sess_for_deletion(fcport); 4012 break; 4013 } 4014 } else { 4015 qla24xx_post_newsess_work(vha, &id, 4016 rptid_entry->u.f1.port_name, 4017 rptid_entry->u.f1.node_name, 4018 NULL, 4019 FS_FCP_IS_N2N); 4020 } 4021 4022 /* if our portname is higher then initiate N2N login */ 4023 4024 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags); 4025 return; 4026 break; 4027 case TOPO_FL: 4028 ha->current_topology = ISP_CFG_FL; 4029 break; 4030 case TOPO_F: 4031 ha->current_topology = ISP_CFG_F; 4032 break; 4033 default: 4034 break; 4035 } 4036 4037 ha->flags.gpsc_supported = 1; 4038 ha->current_topology = ISP_CFG_F; 4039 /* buffer to buffer credit flag */ 4040 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0; 4041 4042 if (rptid_entry->vp_idx == 0) { 4043 if (rptid_entry->vp_status == VP_STAT_COMPL) { 4044 /* FA-WWN is only for physical port */ 4045 if (qla_ini_mode_enabled(vha) && 4046 ha->flags.fawwpn_enabled && 4047 (rptid_entry->u.f1.flags & 4048 BIT_6)) { 4049 memcpy(vha->port_name, 4050 rptid_entry->u.f1.port_name, 4051 WWN_SIZE); 4052 } 4053 4054 qlt_update_host_map(vha, id); 4055 } 4056 4057 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags); 4058 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags); 4059 } else { 4060 if (rptid_entry->vp_status != VP_STAT_COMPL && 4061 rptid_entry->vp_status != VP_STAT_ID_CHG) { 4062 ql_dbg(ql_dbg_mbx, vha, 0x10ba, 4063 "Could not acquire ID for VP[%d].\n", 4064 rptid_entry->vp_idx); 4065 return; 4066 } 4067 4068 found = 0; 4069 spin_lock_irqsave(&ha->vport_slock, flags); 4070 list_for_each_entry(vp, &ha->vp_list, list) { 4071 if (rptid_entry->vp_idx == vp->vp_idx) { 4072 found = 1; 4073 break; 4074 } 4075 } 4076 spin_unlock_irqrestore(&ha->vport_slock, flags); 4077 4078 if (!found) 4079 return; 4080 4081 qlt_update_host_map(vp, id); 4082 4083 /* 4084 * Cannot configure here as we are still sitting on the 4085 * response queue. Handle it in dpc context. 4086 */ 4087 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags); 4088 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags); 4089 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags); 4090 } 4091 set_bit(VP_DPC_NEEDED, &vha->dpc_flags); 4092 qla2xxx_wake_dpc(vha); 4093 } else if (rptid_entry->format == 2) { 4094 ql_dbg(ql_dbg_async, vha, 0x505f, 4095 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n", 4096 rptid_entry->port_id[2], rptid_entry->port_id[1], 4097 rptid_entry->port_id[0]); 4098 4099 ql_dbg(ql_dbg_async, vha, 0x5075, 4100 "N2N: Remote WWPN %8phC.\n", 4101 rptid_entry->u.f2.port_name); 4102 4103 /* N2N. direct connect */ 4104 ha->current_topology = ISP_CFG_N; 4105 ha->flags.rida_fmt2 = 1; 4106 vha->d_id.b.domain = rptid_entry->port_id[2]; 4107 vha->d_id.b.area = rptid_entry->port_id[1]; 4108 vha->d_id.b.al_pa = rptid_entry->port_id[0]; 4109 4110 ha->flags.n2n_ae = 1; 4111 spin_lock_irqsave(&ha->vport_slock, flags); 4112 qlt_update_vp_map(vha, SET_AL_PA); 4113 spin_unlock_irqrestore(&ha->vport_slock, flags); 4114 4115 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4116 fcport->scan_state = QLA_FCPORT_SCAN; 4117 fcport->n2n_flag = 0; 4118 } 4119 4120 fcport = qla2x00_find_fcport_by_wwpn(vha, 4121 rptid_entry->u.f2.port_name, 1); 4122 4123 if (fcport) { 4124 fcport->login_retry = vha->hw->login_retry_count; 4125 fcport->plogi_nack_done_deadline = jiffies + HZ; 4126 fcport->scan_state = QLA_FCPORT_FOUND; 4127 fcport->keep_nport_handle = 1; 4128 fcport->n2n_flag = 1; 4129 fcport->d_id.b.domain = 4130 rptid_entry->u.f2.remote_nport_id[2]; 4131 fcport->d_id.b.area = 4132 rptid_entry->u.f2.remote_nport_id[1]; 4133 fcport->d_id.b.al_pa = 4134 rptid_entry->u.f2.remote_nport_id[0]; 4135 } 4136 } 4137 } 4138 4139 /* 4140 * qla24xx_modify_vp_config 4141 * Change VP configuration for vha 4142 * 4143 * Input: 4144 * vha = adapter block pointer. 4145 * 4146 * Returns: 4147 * qla2xxx local function return status code. 4148 * 4149 * Context: 4150 * Kernel context. 4151 */ 4152 int 4153 qla24xx_modify_vp_config(scsi_qla_host_t *vha) 4154 { 4155 int rval; 4156 struct vp_config_entry_24xx *vpmod; 4157 dma_addr_t vpmod_dma; 4158 struct qla_hw_data *ha = vha->hw; 4159 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 4160 4161 /* This can be called by the parent */ 4162 4163 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb, 4164 "Entered %s.\n", __func__); 4165 4166 vpmod = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma); 4167 if (!vpmod) { 4168 ql_log(ql_log_warn, vha, 0x10bc, 4169 "Failed to allocate modify VP IOCB.\n"); 4170 return QLA_MEMORY_ALLOC_FAILED; 4171 } 4172 4173 vpmod->entry_type = VP_CONFIG_IOCB_TYPE; 4174 vpmod->entry_count = 1; 4175 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS; 4176 vpmod->vp_count = 1; 4177 vpmod->vp_index1 = vha->vp_idx; 4178 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; 4179 4180 qlt_modify_vp_config(vha, vpmod); 4181 4182 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE); 4183 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE); 4184 vpmod->entry_count = 1; 4185 4186 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0); 4187 if (rval != QLA_SUCCESS) { 4188 ql_dbg(ql_dbg_mbx, vha, 0x10bd, 4189 "Failed to issue VP config IOCB (%x).\n", rval); 4190 } else if (vpmod->comp_status != 0) { 4191 ql_dbg(ql_dbg_mbx, vha, 0x10be, 4192 "Failed to complete IOCB -- error status (%x).\n", 4193 vpmod->comp_status); 4194 rval = QLA_FUNCTION_FAILED; 4195 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) { 4196 ql_dbg(ql_dbg_mbx, vha, 0x10bf, 4197 "Failed to complete IOCB -- completion status (%x).\n", 4198 le16_to_cpu(vpmod->comp_status)); 4199 rval = QLA_FUNCTION_FAILED; 4200 } else { 4201 /* EMPTY */ 4202 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0, 4203 "Done %s.\n", __func__); 4204 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING); 4205 } 4206 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma); 4207 4208 return rval; 4209 } 4210 4211 /* 4212 * qla2x00_send_change_request 4213 * Receive or disable RSCN request from fabric controller 4214 * 4215 * Input: 4216 * ha = adapter block pointer 4217 * format = registration format: 4218 * 0 - Reserved 4219 * 1 - Fabric detected registration 4220 * 2 - N_port detected registration 4221 * 3 - Full registration 4222 * FF - clear registration 4223 * vp_idx = Virtual port index 4224 * 4225 * Returns: 4226 * qla2x00 local function return status code. 4227 * 4228 * Context: 4229 * Kernel Context 4230 */ 4231 4232 int 4233 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format, 4234 uint16_t vp_idx) 4235 { 4236 int rval; 4237 mbx_cmd_t mc; 4238 mbx_cmd_t *mcp = &mc; 4239 4240 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7, 4241 "Entered %s.\n", __func__); 4242 4243 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST; 4244 mcp->mb[1] = format; 4245 mcp->mb[9] = vp_idx; 4246 mcp->out_mb = MBX_9|MBX_1|MBX_0; 4247 mcp->in_mb = MBX_0|MBX_1; 4248 mcp->tov = MBX_TOV_SECONDS; 4249 mcp->flags = 0; 4250 rval = qla2x00_mailbox_command(vha, mcp); 4251 4252 if (rval == QLA_SUCCESS) { 4253 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) { 4254 rval = BIT_1; 4255 } 4256 } else 4257 rval = BIT_1; 4258 4259 return rval; 4260 } 4261 4262 int 4263 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 4264 uint32_t size) 4265 { 4266 int rval; 4267 mbx_cmd_t mc; 4268 mbx_cmd_t *mcp = &mc; 4269 4270 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009, 4271 "Entered %s.\n", __func__); 4272 4273 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) { 4274 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 4275 mcp->mb[8] = MSW(addr); 4276 mcp->out_mb = MBX_8|MBX_0; 4277 } else { 4278 mcp->mb[0] = MBC_DUMP_RISC_RAM; 4279 mcp->out_mb = MBX_0; 4280 } 4281 mcp->mb[1] = LSW(addr); 4282 mcp->mb[2] = MSW(req_dma); 4283 mcp->mb[3] = LSW(req_dma); 4284 mcp->mb[6] = MSW(MSD(req_dma)); 4285 mcp->mb[7] = LSW(MSD(req_dma)); 4286 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 4287 if (IS_FWI2_CAPABLE(vha->hw)) { 4288 mcp->mb[4] = MSW(size); 4289 mcp->mb[5] = LSW(size); 4290 mcp->out_mb |= MBX_5|MBX_4; 4291 } else { 4292 mcp->mb[4] = LSW(size); 4293 mcp->out_mb |= MBX_4; 4294 } 4295 4296 mcp->in_mb = MBX_0; 4297 mcp->tov = MBX_TOV_SECONDS; 4298 mcp->flags = 0; 4299 rval = qla2x00_mailbox_command(vha, mcp); 4300 4301 if (rval != QLA_SUCCESS) { 4302 ql_dbg(ql_dbg_mbx, vha, 0x1008, 4303 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4304 } else { 4305 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007, 4306 "Done %s.\n", __func__); 4307 } 4308 4309 return rval; 4310 } 4311 /* 84XX Support **************************************************************/ 4312 4313 struct cs84xx_mgmt_cmd { 4314 union { 4315 struct verify_chip_entry_84xx req; 4316 struct verify_chip_rsp_84xx rsp; 4317 } p; 4318 }; 4319 4320 int 4321 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status) 4322 { 4323 int rval, retry; 4324 struct cs84xx_mgmt_cmd *mn; 4325 dma_addr_t mn_dma; 4326 uint16_t options; 4327 unsigned long flags; 4328 struct qla_hw_data *ha = vha->hw; 4329 4330 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8, 4331 "Entered %s.\n", __func__); 4332 4333 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma); 4334 if (mn == NULL) { 4335 return QLA_MEMORY_ALLOC_FAILED; 4336 } 4337 4338 /* Force Update? */ 4339 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0; 4340 /* Diagnostic firmware? */ 4341 /* options |= MENLO_DIAG_FW; */ 4342 /* We update the firmware with only one data sequence. */ 4343 options |= VCO_END_OF_DATA; 4344 4345 do { 4346 retry = 0; 4347 memset(mn, 0, sizeof(*mn)); 4348 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE; 4349 mn->p.req.entry_count = 1; 4350 mn->p.req.options = cpu_to_le16(options); 4351 4352 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c, 4353 "Dump of Verify Request.\n"); 4354 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e, 4355 mn, sizeof(*mn)); 4356 4357 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120); 4358 if (rval != QLA_SUCCESS) { 4359 ql_dbg(ql_dbg_mbx, vha, 0x10cb, 4360 "Failed to issue verify IOCB (%x).\n", rval); 4361 goto verify_done; 4362 } 4363 4364 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110, 4365 "Dump of Verify Response.\n"); 4366 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118, 4367 mn, sizeof(*mn)); 4368 4369 status[0] = le16_to_cpu(mn->p.rsp.comp_status); 4370 status[1] = status[0] == CS_VCS_CHIP_FAILURE ? 4371 le16_to_cpu(mn->p.rsp.failure_code) : 0; 4372 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce, 4373 "cs=%x fc=%x.\n", status[0], status[1]); 4374 4375 if (status[0] != CS_COMPLETE) { 4376 rval = QLA_FUNCTION_FAILED; 4377 if (!(options & VCO_DONT_UPDATE_FW)) { 4378 ql_dbg(ql_dbg_mbx, vha, 0x10cf, 4379 "Firmware update failed. Retrying " 4380 "without update firmware.\n"); 4381 options |= VCO_DONT_UPDATE_FW; 4382 options &= ~VCO_FORCE_UPDATE; 4383 retry = 1; 4384 } 4385 } else { 4386 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0, 4387 "Firmware updated to %x.\n", 4388 le32_to_cpu(mn->p.rsp.fw_ver)); 4389 4390 /* NOTE: we only update OP firmware. */ 4391 spin_lock_irqsave(&ha->cs84xx->access_lock, flags); 4392 ha->cs84xx->op_fw_version = 4393 le32_to_cpu(mn->p.rsp.fw_ver); 4394 spin_unlock_irqrestore(&ha->cs84xx->access_lock, 4395 flags); 4396 } 4397 } while (retry); 4398 4399 verify_done: 4400 dma_pool_free(ha->s_dma_pool, mn, mn_dma); 4401 4402 if (rval != QLA_SUCCESS) { 4403 ql_dbg(ql_dbg_mbx, vha, 0x10d1, 4404 "Failed=%x.\n", rval); 4405 } else { 4406 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2, 4407 "Done %s.\n", __func__); 4408 } 4409 4410 return rval; 4411 } 4412 4413 int 4414 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req) 4415 { 4416 int rval; 4417 unsigned long flags; 4418 mbx_cmd_t mc; 4419 mbx_cmd_t *mcp = &mc; 4420 struct qla_hw_data *ha = vha->hw; 4421 4422 if (!ha->flags.fw_started) 4423 return QLA_SUCCESS; 4424 4425 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3, 4426 "Entered %s.\n", __func__); 4427 4428 if (IS_SHADOW_REG_CAPABLE(ha)) 4429 req->options |= BIT_13; 4430 4431 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 4432 mcp->mb[1] = req->options; 4433 mcp->mb[2] = MSW(LSD(req->dma)); 4434 mcp->mb[3] = LSW(LSD(req->dma)); 4435 mcp->mb[6] = MSW(MSD(req->dma)); 4436 mcp->mb[7] = LSW(MSD(req->dma)); 4437 mcp->mb[5] = req->length; 4438 if (req->rsp) 4439 mcp->mb[10] = req->rsp->id; 4440 mcp->mb[12] = req->qos; 4441 mcp->mb[11] = req->vp_idx; 4442 mcp->mb[13] = req->rid; 4443 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4444 mcp->mb[15] = 0; 4445 4446 mcp->mb[4] = req->id; 4447 /* que in ptr index */ 4448 mcp->mb[8] = 0; 4449 /* que out ptr index */ 4450 mcp->mb[9] = *req->out_ptr = 0; 4451 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7| 4452 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4453 mcp->in_mb = MBX_0; 4454 mcp->flags = MBX_DMA_OUT; 4455 mcp->tov = MBX_TOV_SECONDS * 2; 4456 4457 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 4458 IS_QLA28XX(ha)) 4459 mcp->in_mb |= MBX_1; 4460 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4461 mcp->out_mb |= MBX_15; 4462 /* debug q create issue in SR-IOV */ 4463 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 4464 } 4465 4466 spin_lock_irqsave(&ha->hardware_lock, flags); 4467 if (!(req->options & BIT_0)) { 4468 wrt_reg_dword(req->req_q_in, 0); 4469 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 4470 wrt_reg_dword(req->req_q_out, 0); 4471 } 4472 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4473 4474 rval = qla2x00_mailbox_command(vha, mcp); 4475 if (rval != QLA_SUCCESS) { 4476 ql_dbg(ql_dbg_mbx, vha, 0x10d4, 4477 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4478 } else { 4479 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5, 4480 "Done %s.\n", __func__); 4481 } 4482 4483 return rval; 4484 } 4485 4486 int 4487 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp) 4488 { 4489 int rval; 4490 unsigned long flags; 4491 mbx_cmd_t mc; 4492 mbx_cmd_t *mcp = &mc; 4493 struct qla_hw_data *ha = vha->hw; 4494 4495 if (!ha->flags.fw_started) 4496 return QLA_SUCCESS; 4497 4498 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6, 4499 "Entered %s.\n", __func__); 4500 4501 if (IS_SHADOW_REG_CAPABLE(ha)) 4502 rsp->options |= BIT_13; 4503 4504 mcp->mb[0] = MBC_INITIALIZE_MULTIQ; 4505 mcp->mb[1] = rsp->options; 4506 mcp->mb[2] = MSW(LSD(rsp->dma)); 4507 mcp->mb[3] = LSW(LSD(rsp->dma)); 4508 mcp->mb[6] = MSW(MSD(rsp->dma)); 4509 mcp->mb[7] = LSW(MSD(rsp->dma)); 4510 mcp->mb[5] = rsp->length; 4511 mcp->mb[14] = rsp->msix->entry; 4512 mcp->mb[13] = rsp->rid; 4513 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4514 mcp->mb[15] = 0; 4515 4516 mcp->mb[4] = rsp->id; 4517 /* que in ptr index */ 4518 mcp->mb[8] = *rsp->in_ptr = 0; 4519 /* que out ptr index */ 4520 mcp->mb[9] = 0; 4521 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7 4522 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4523 mcp->in_mb = MBX_0; 4524 mcp->flags = MBX_DMA_OUT; 4525 mcp->tov = MBX_TOV_SECONDS * 2; 4526 4527 if (IS_QLA81XX(ha)) { 4528 mcp->out_mb |= MBX_12|MBX_11|MBX_10; 4529 mcp->in_mb |= MBX_1; 4530 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4531 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10; 4532 mcp->in_mb |= MBX_1; 4533 /* debug q create issue in SR-IOV */ 4534 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7; 4535 } 4536 4537 spin_lock_irqsave(&ha->hardware_lock, flags); 4538 if (!(rsp->options & BIT_0)) { 4539 wrt_reg_dword(rsp->rsp_q_out, 0); 4540 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 4541 wrt_reg_dword(rsp->rsp_q_in, 0); 4542 } 4543 4544 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4545 4546 rval = qla2x00_mailbox_command(vha, mcp); 4547 if (rval != QLA_SUCCESS) { 4548 ql_dbg(ql_dbg_mbx, vha, 0x10d7, 4549 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4550 } else { 4551 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8, 4552 "Done %s.\n", __func__); 4553 } 4554 4555 return rval; 4556 } 4557 4558 int 4559 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb) 4560 { 4561 int rval; 4562 mbx_cmd_t mc; 4563 mbx_cmd_t *mcp = &mc; 4564 4565 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9, 4566 "Entered %s.\n", __func__); 4567 4568 mcp->mb[0] = MBC_IDC_ACK; 4569 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4570 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4571 mcp->in_mb = MBX_0; 4572 mcp->tov = MBX_TOV_SECONDS; 4573 mcp->flags = 0; 4574 rval = qla2x00_mailbox_command(vha, mcp); 4575 4576 if (rval != QLA_SUCCESS) { 4577 ql_dbg(ql_dbg_mbx, vha, 0x10da, 4578 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 4579 } else { 4580 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db, 4581 "Done %s.\n", __func__); 4582 } 4583 4584 return rval; 4585 } 4586 4587 int 4588 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size) 4589 { 4590 int rval; 4591 mbx_cmd_t mc; 4592 mbx_cmd_t *mcp = &mc; 4593 4594 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc, 4595 "Entered %s.\n", __func__); 4596 4597 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4598 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw)) 4599 return QLA_FUNCTION_FAILED; 4600 4601 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4602 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE; 4603 mcp->out_mb = MBX_1|MBX_0; 4604 mcp->in_mb = MBX_1|MBX_0; 4605 mcp->tov = MBX_TOV_SECONDS; 4606 mcp->flags = 0; 4607 rval = qla2x00_mailbox_command(vha, mcp); 4608 4609 if (rval != QLA_SUCCESS) { 4610 ql_dbg(ql_dbg_mbx, vha, 0x10dd, 4611 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4612 rval, mcp->mb[0], mcp->mb[1]); 4613 } else { 4614 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de, 4615 "Done %s.\n", __func__); 4616 *sector_size = mcp->mb[1]; 4617 } 4618 4619 return rval; 4620 } 4621 4622 int 4623 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable) 4624 { 4625 int rval; 4626 mbx_cmd_t mc; 4627 mbx_cmd_t *mcp = &mc; 4628 4629 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4630 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw)) 4631 return QLA_FUNCTION_FAILED; 4632 4633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df, 4634 "Entered %s.\n", __func__); 4635 4636 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4637 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE : 4638 FAC_OPT_CMD_WRITE_PROTECT; 4639 mcp->out_mb = MBX_1|MBX_0; 4640 mcp->in_mb = MBX_1|MBX_0; 4641 mcp->tov = MBX_TOV_SECONDS; 4642 mcp->flags = 0; 4643 rval = qla2x00_mailbox_command(vha, mcp); 4644 4645 if (rval != QLA_SUCCESS) { 4646 ql_dbg(ql_dbg_mbx, vha, 0x10e0, 4647 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4648 rval, mcp->mb[0], mcp->mb[1]); 4649 } else { 4650 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1, 4651 "Done %s.\n", __func__); 4652 } 4653 4654 return rval; 4655 } 4656 4657 int 4658 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish) 4659 { 4660 int rval; 4661 mbx_cmd_t mc; 4662 mbx_cmd_t *mcp = &mc; 4663 4664 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) && 4665 !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw)) 4666 return QLA_FUNCTION_FAILED; 4667 4668 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2, 4669 "Entered %s.\n", __func__); 4670 4671 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4672 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR; 4673 mcp->mb[2] = LSW(start); 4674 mcp->mb[3] = MSW(start); 4675 mcp->mb[4] = LSW(finish); 4676 mcp->mb[5] = MSW(finish); 4677 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4678 mcp->in_mb = MBX_2|MBX_1|MBX_0; 4679 mcp->tov = MBX_TOV_SECONDS; 4680 mcp->flags = 0; 4681 rval = qla2x00_mailbox_command(vha, mcp); 4682 4683 if (rval != QLA_SUCCESS) { 4684 ql_dbg(ql_dbg_mbx, vha, 0x10e3, 4685 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4686 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4687 } else { 4688 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4, 4689 "Done %s.\n", __func__); 4690 } 4691 4692 return rval; 4693 } 4694 4695 int 4696 qla81xx_fac_semaphore_access(scsi_qla_host_t *vha, int lock) 4697 { 4698 int rval = QLA_SUCCESS; 4699 mbx_cmd_t mc; 4700 mbx_cmd_t *mcp = &mc; 4701 struct qla_hw_data *ha = vha->hw; 4702 4703 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 4704 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 4705 return rval; 4706 4707 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2, 4708 "Entered %s.\n", __func__); 4709 4710 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL; 4711 mcp->mb[1] = (lock ? FAC_OPT_CMD_LOCK_SEMAPHORE : 4712 FAC_OPT_CMD_UNLOCK_SEMAPHORE); 4713 mcp->out_mb = MBX_1|MBX_0; 4714 mcp->in_mb = MBX_1|MBX_0; 4715 mcp->tov = MBX_TOV_SECONDS; 4716 mcp->flags = 0; 4717 rval = qla2x00_mailbox_command(vha, mcp); 4718 4719 if (rval != QLA_SUCCESS) { 4720 ql_dbg(ql_dbg_mbx, vha, 0x10e3, 4721 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 4722 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 4723 } else { 4724 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4, 4725 "Done %s.\n", __func__); 4726 } 4727 4728 return rval; 4729 } 4730 4731 int 4732 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha) 4733 { 4734 int rval = 0; 4735 mbx_cmd_t mc; 4736 mbx_cmd_t *mcp = &mc; 4737 4738 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5, 4739 "Entered %s.\n", __func__); 4740 4741 mcp->mb[0] = MBC_RESTART_MPI_FW; 4742 mcp->out_mb = MBX_0; 4743 mcp->in_mb = MBX_0|MBX_1; 4744 mcp->tov = MBX_TOV_SECONDS; 4745 mcp->flags = 0; 4746 rval = qla2x00_mailbox_command(vha, mcp); 4747 4748 if (rval != QLA_SUCCESS) { 4749 ql_dbg(ql_dbg_mbx, vha, 0x10e6, 4750 "Failed=%x mb[0]=%x mb[1]=%x.\n", 4751 rval, mcp->mb[0], mcp->mb[1]); 4752 } else { 4753 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7, 4754 "Done %s.\n", __func__); 4755 } 4756 4757 return rval; 4758 } 4759 4760 int 4761 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4762 { 4763 int rval; 4764 mbx_cmd_t mc; 4765 mbx_cmd_t *mcp = &mc; 4766 int i; 4767 int len; 4768 __le16 *str; 4769 struct qla_hw_data *ha = vha->hw; 4770 4771 if (!IS_P3P_TYPE(ha)) 4772 return QLA_FUNCTION_FAILED; 4773 4774 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b, 4775 "Entered %s.\n", __func__); 4776 4777 str = (__force __le16 *)version; 4778 len = strlen(version); 4779 4780 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4781 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8; 4782 mcp->out_mb = MBX_1|MBX_0; 4783 for (i = 4; i < 16 && len; i++, str++, len -= 2) { 4784 mcp->mb[i] = le16_to_cpup(str); 4785 mcp->out_mb |= 1<<i; 4786 } 4787 for (; i < 16; i++) { 4788 mcp->mb[i] = 0; 4789 mcp->out_mb |= 1<<i; 4790 } 4791 mcp->in_mb = MBX_1|MBX_0; 4792 mcp->tov = MBX_TOV_SECONDS; 4793 mcp->flags = 0; 4794 rval = qla2x00_mailbox_command(vha, mcp); 4795 4796 if (rval != QLA_SUCCESS) { 4797 ql_dbg(ql_dbg_mbx, vha, 0x117c, 4798 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4799 } else { 4800 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d, 4801 "Done %s.\n", __func__); 4802 } 4803 4804 return rval; 4805 } 4806 4807 int 4808 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version) 4809 { 4810 int rval; 4811 mbx_cmd_t mc; 4812 mbx_cmd_t *mcp = &mc; 4813 int len; 4814 uint16_t dwlen; 4815 uint8_t *str; 4816 dma_addr_t str_dma; 4817 struct qla_hw_data *ha = vha->hw; 4818 4819 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) || 4820 IS_P3P_TYPE(ha)) 4821 return QLA_FUNCTION_FAILED; 4822 4823 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e, 4824 "Entered %s.\n", __func__); 4825 4826 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma); 4827 if (!str) { 4828 ql_log(ql_log_warn, vha, 0x117f, 4829 "Failed to allocate driver version param.\n"); 4830 return QLA_MEMORY_ALLOC_FAILED; 4831 } 4832 4833 memcpy(str, "\x7\x3\x11\x0", 4); 4834 dwlen = str[0]; 4835 len = dwlen * 4 - 4; 4836 memset(str + 4, 0, len); 4837 if (len > strlen(version)) 4838 len = strlen(version); 4839 memcpy(str + 4, version, len); 4840 4841 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4842 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen; 4843 mcp->mb[2] = MSW(LSD(str_dma)); 4844 mcp->mb[3] = LSW(LSD(str_dma)); 4845 mcp->mb[6] = MSW(MSD(str_dma)); 4846 mcp->mb[7] = LSW(MSD(str_dma)); 4847 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4848 mcp->in_mb = MBX_1|MBX_0; 4849 mcp->tov = MBX_TOV_SECONDS; 4850 mcp->flags = 0; 4851 rval = qla2x00_mailbox_command(vha, mcp); 4852 4853 if (rval != QLA_SUCCESS) { 4854 ql_dbg(ql_dbg_mbx, vha, 0x1180, 4855 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4856 } else { 4857 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181, 4858 "Done %s.\n", __func__); 4859 } 4860 4861 dma_pool_free(ha->s_dma_pool, str, str_dma); 4862 4863 return rval; 4864 } 4865 4866 int 4867 qla24xx_get_port_login_templ(scsi_qla_host_t *vha, dma_addr_t buf_dma, 4868 void *buf, uint16_t bufsiz) 4869 { 4870 int rval, i; 4871 mbx_cmd_t mc; 4872 mbx_cmd_t *mcp = &mc; 4873 uint32_t *bp; 4874 4875 if (!IS_FWI2_CAPABLE(vha->hw)) 4876 return QLA_FUNCTION_FAILED; 4877 4878 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159, 4879 "Entered %s.\n", __func__); 4880 4881 mcp->mb[0] = MBC_GET_RNID_PARAMS; 4882 mcp->mb[1] = RNID_TYPE_PORT_LOGIN << 8; 4883 mcp->mb[2] = MSW(buf_dma); 4884 mcp->mb[3] = LSW(buf_dma); 4885 mcp->mb[6] = MSW(MSD(buf_dma)); 4886 mcp->mb[7] = LSW(MSD(buf_dma)); 4887 mcp->mb[8] = bufsiz/4; 4888 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 4889 mcp->in_mb = MBX_1|MBX_0; 4890 mcp->tov = MBX_TOV_SECONDS; 4891 mcp->flags = 0; 4892 rval = qla2x00_mailbox_command(vha, mcp); 4893 4894 if (rval != QLA_SUCCESS) { 4895 ql_dbg(ql_dbg_mbx, vha, 0x115a, 4896 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 4897 } else { 4898 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b, 4899 "Done %s.\n", __func__); 4900 bp = (uint32_t *) buf; 4901 for (i = 0; i < (bufsiz-4)/4; i++, bp++) 4902 *bp = le32_to_cpu((__force __le32)*bp); 4903 } 4904 4905 return rval; 4906 } 4907 4908 #define PUREX_CMD_COUNT 2 4909 int 4910 qla25xx_set_els_cmds_supported(scsi_qla_host_t *vha) 4911 { 4912 int rval; 4913 mbx_cmd_t mc; 4914 mbx_cmd_t *mcp = &mc; 4915 uint8_t *els_cmd_map; 4916 dma_addr_t els_cmd_map_dma; 4917 uint8_t cmd_opcode[PUREX_CMD_COUNT]; 4918 uint8_t i, index, purex_bit; 4919 struct qla_hw_data *ha = vha->hw; 4920 4921 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha) && 4922 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 4923 return QLA_SUCCESS; 4924 4925 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1197, 4926 "Entered %s.\n", __func__); 4927 4928 els_cmd_map = dma_alloc_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE, 4929 &els_cmd_map_dma, GFP_KERNEL); 4930 if (!els_cmd_map) { 4931 ql_log(ql_log_warn, vha, 0x7101, 4932 "Failed to allocate RDP els command param.\n"); 4933 return QLA_MEMORY_ALLOC_FAILED; 4934 } 4935 4936 memset(els_cmd_map, 0, ELS_CMD_MAP_SIZE); 4937 4938 /* List of Purex ELS */ 4939 cmd_opcode[0] = ELS_FPIN; 4940 cmd_opcode[1] = ELS_RDP; 4941 4942 for (i = 0; i < PUREX_CMD_COUNT; i++) { 4943 index = cmd_opcode[i] / 8; 4944 purex_bit = cmd_opcode[i] % 8; 4945 els_cmd_map[index] |= 1 << purex_bit; 4946 } 4947 4948 mcp->mb[0] = MBC_SET_RNID_PARAMS; 4949 mcp->mb[1] = RNID_TYPE_ELS_CMD << 8; 4950 mcp->mb[2] = MSW(LSD(els_cmd_map_dma)); 4951 mcp->mb[3] = LSW(LSD(els_cmd_map_dma)); 4952 mcp->mb[6] = MSW(MSD(els_cmd_map_dma)); 4953 mcp->mb[7] = LSW(MSD(els_cmd_map_dma)); 4954 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4955 mcp->in_mb = MBX_1|MBX_0; 4956 mcp->tov = MBX_TOV_SECONDS; 4957 mcp->flags = MBX_DMA_OUT; 4958 mcp->buf_size = ELS_CMD_MAP_SIZE; 4959 rval = qla2x00_mailbox_command(vha, mcp); 4960 4961 if (rval != QLA_SUCCESS) { 4962 ql_dbg(ql_dbg_mbx, vha, 0x118d, 4963 "Failed=%x (%x,%x).\n", rval, mcp->mb[0], mcp->mb[1]); 4964 } else { 4965 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c, 4966 "Done %s.\n", __func__); 4967 } 4968 4969 dma_free_coherent(&ha->pdev->dev, DMA_POOL_SIZE, 4970 els_cmd_map, els_cmd_map_dma); 4971 4972 return rval; 4973 } 4974 4975 int 4976 qla24xx_get_buffer_credits(scsi_qla_host_t *vha, struct buffer_credit_24xx *bbc, 4977 dma_addr_t bbc_dma) 4978 { 4979 mbx_cmd_t mc; 4980 mbx_cmd_t *mcp = &mc; 4981 int rval; 4982 4983 if (!IS_FWI2_CAPABLE(vha->hw)) 4984 return QLA_FUNCTION_FAILED; 4985 4986 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118e, 4987 "Entered %s.\n", __func__); 4988 4989 mcp->mb[0] = MBC_GET_RNID_PARAMS; 4990 mcp->mb[1] = RNID_BUFFER_CREDITS << 8; 4991 mcp->mb[2] = MSW(LSD(bbc_dma)); 4992 mcp->mb[3] = LSW(LSD(bbc_dma)); 4993 mcp->mb[6] = MSW(MSD(bbc_dma)); 4994 mcp->mb[7] = LSW(MSD(bbc_dma)); 4995 mcp->mb[8] = sizeof(*bbc) / sizeof(*bbc->parameter); 4996 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 4997 mcp->in_mb = MBX_1|MBX_0; 4998 mcp->buf_size = sizeof(*bbc); 4999 mcp->flags = MBX_DMA_IN; 5000 mcp->tov = MBX_TOV_SECONDS; 5001 rval = qla2x00_mailbox_command(vha, mcp); 5002 5003 if (rval != QLA_SUCCESS) { 5004 ql_dbg(ql_dbg_mbx, vha, 0x118f, 5005 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 5006 } else { 5007 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1190, 5008 "Done %s.\n", __func__); 5009 } 5010 5011 return rval; 5012 } 5013 5014 static int 5015 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp) 5016 { 5017 int rval; 5018 mbx_cmd_t mc; 5019 mbx_cmd_t *mcp = &mc; 5020 5021 if (!IS_FWI2_CAPABLE(vha->hw)) 5022 return QLA_FUNCTION_FAILED; 5023 5024 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159, 5025 "Entered %s.\n", __func__); 5026 5027 mcp->mb[0] = MBC_GET_RNID_PARAMS; 5028 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8; 5029 mcp->out_mb = MBX_1|MBX_0; 5030 mcp->in_mb = MBX_1|MBX_0; 5031 mcp->tov = MBX_TOV_SECONDS; 5032 mcp->flags = 0; 5033 rval = qla2x00_mailbox_command(vha, mcp); 5034 *temp = mcp->mb[1]; 5035 5036 if (rval != QLA_SUCCESS) { 5037 ql_dbg(ql_dbg_mbx, vha, 0x115a, 5038 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]); 5039 } else { 5040 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b, 5041 "Done %s.\n", __func__); 5042 } 5043 5044 return rval; 5045 } 5046 5047 int 5048 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 5049 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 5050 { 5051 int rval; 5052 mbx_cmd_t mc; 5053 mbx_cmd_t *mcp = &mc; 5054 struct qla_hw_data *ha = vha->hw; 5055 5056 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8, 5057 "Entered %s.\n", __func__); 5058 5059 if (!IS_FWI2_CAPABLE(ha)) 5060 return QLA_FUNCTION_FAILED; 5061 5062 if (len == 1) 5063 opt |= BIT_0; 5064 5065 mcp->mb[0] = MBC_READ_SFP; 5066 mcp->mb[1] = dev; 5067 mcp->mb[2] = MSW(LSD(sfp_dma)); 5068 mcp->mb[3] = LSW(LSD(sfp_dma)); 5069 mcp->mb[6] = MSW(MSD(sfp_dma)); 5070 mcp->mb[7] = LSW(MSD(sfp_dma)); 5071 mcp->mb[8] = len; 5072 mcp->mb[9] = off; 5073 mcp->mb[10] = opt; 5074 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 5075 mcp->in_mb = MBX_1|MBX_0; 5076 mcp->tov = MBX_TOV_SECONDS; 5077 mcp->flags = 0; 5078 rval = qla2x00_mailbox_command(vha, mcp); 5079 5080 if (opt & BIT_0) 5081 *sfp = mcp->mb[1]; 5082 5083 if (rval != QLA_SUCCESS) { 5084 ql_dbg(ql_dbg_mbx, vha, 0x10e9, 5085 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5086 if (mcp->mb[0] == MBS_COMMAND_ERROR && mcp->mb[1] == 0x22) { 5087 /* sfp is not there */ 5088 rval = QLA_INTERFACE_ERROR; 5089 } 5090 } else { 5091 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea, 5092 "Done %s.\n", __func__); 5093 } 5094 5095 return rval; 5096 } 5097 5098 int 5099 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp, 5100 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt) 5101 { 5102 int rval; 5103 mbx_cmd_t mc; 5104 mbx_cmd_t *mcp = &mc; 5105 struct qla_hw_data *ha = vha->hw; 5106 5107 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb, 5108 "Entered %s.\n", __func__); 5109 5110 if (!IS_FWI2_CAPABLE(ha)) 5111 return QLA_FUNCTION_FAILED; 5112 5113 if (len == 1) 5114 opt |= BIT_0; 5115 5116 if (opt & BIT_0) 5117 len = *sfp; 5118 5119 mcp->mb[0] = MBC_WRITE_SFP; 5120 mcp->mb[1] = dev; 5121 mcp->mb[2] = MSW(LSD(sfp_dma)); 5122 mcp->mb[3] = LSW(LSD(sfp_dma)); 5123 mcp->mb[6] = MSW(MSD(sfp_dma)); 5124 mcp->mb[7] = LSW(MSD(sfp_dma)); 5125 mcp->mb[8] = len; 5126 mcp->mb[9] = off; 5127 mcp->mb[10] = opt; 5128 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 5129 mcp->in_mb = MBX_1|MBX_0; 5130 mcp->tov = MBX_TOV_SECONDS; 5131 mcp->flags = 0; 5132 rval = qla2x00_mailbox_command(vha, mcp); 5133 5134 if (rval != QLA_SUCCESS) { 5135 ql_dbg(ql_dbg_mbx, vha, 0x10ec, 5136 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5137 } else { 5138 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed, 5139 "Done %s.\n", __func__); 5140 } 5141 5142 return rval; 5143 } 5144 5145 int 5146 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma, 5147 uint16_t size_in_bytes, uint16_t *actual_size) 5148 { 5149 int rval; 5150 mbx_cmd_t mc; 5151 mbx_cmd_t *mcp = &mc; 5152 5153 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee, 5154 "Entered %s.\n", __func__); 5155 5156 if (!IS_CNA_CAPABLE(vha->hw)) 5157 return QLA_FUNCTION_FAILED; 5158 5159 mcp->mb[0] = MBC_GET_XGMAC_STATS; 5160 mcp->mb[2] = MSW(stats_dma); 5161 mcp->mb[3] = LSW(stats_dma); 5162 mcp->mb[6] = MSW(MSD(stats_dma)); 5163 mcp->mb[7] = LSW(MSD(stats_dma)); 5164 mcp->mb[8] = size_in_bytes >> 2; 5165 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 5166 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5167 mcp->tov = MBX_TOV_SECONDS; 5168 mcp->flags = 0; 5169 rval = qla2x00_mailbox_command(vha, mcp); 5170 5171 if (rval != QLA_SUCCESS) { 5172 ql_dbg(ql_dbg_mbx, vha, 0x10ef, 5173 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 5174 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 5175 } else { 5176 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0, 5177 "Done %s.\n", __func__); 5178 5179 5180 *actual_size = mcp->mb[2] << 2; 5181 } 5182 5183 return rval; 5184 } 5185 5186 int 5187 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma, 5188 uint16_t size) 5189 { 5190 int rval; 5191 mbx_cmd_t mc; 5192 mbx_cmd_t *mcp = &mc; 5193 5194 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1, 5195 "Entered %s.\n", __func__); 5196 5197 if (!IS_CNA_CAPABLE(vha->hw)) 5198 return QLA_FUNCTION_FAILED; 5199 5200 mcp->mb[0] = MBC_GET_DCBX_PARAMS; 5201 mcp->mb[1] = 0; 5202 mcp->mb[2] = MSW(tlv_dma); 5203 mcp->mb[3] = LSW(tlv_dma); 5204 mcp->mb[6] = MSW(MSD(tlv_dma)); 5205 mcp->mb[7] = LSW(MSD(tlv_dma)); 5206 mcp->mb[8] = size; 5207 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 5208 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5209 mcp->tov = MBX_TOV_SECONDS; 5210 mcp->flags = 0; 5211 rval = qla2x00_mailbox_command(vha, mcp); 5212 5213 if (rval != QLA_SUCCESS) { 5214 ql_dbg(ql_dbg_mbx, vha, 0x10f2, 5215 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n", 5216 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]); 5217 } else { 5218 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3, 5219 "Done %s.\n", __func__); 5220 } 5221 5222 return rval; 5223 } 5224 5225 int 5226 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data) 5227 { 5228 int rval; 5229 mbx_cmd_t mc; 5230 mbx_cmd_t *mcp = &mc; 5231 5232 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4, 5233 "Entered %s.\n", __func__); 5234 5235 if (!IS_FWI2_CAPABLE(vha->hw)) 5236 return QLA_FUNCTION_FAILED; 5237 5238 mcp->mb[0] = MBC_READ_RAM_EXTENDED; 5239 mcp->mb[1] = LSW(risc_addr); 5240 mcp->mb[8] = MSW(risc_addr); 5241 mcp->out_mb = MBX_8|MBX_1|MBX_0; 5242 mcp->in_mb = MBX_3|MBX_2|MBX_0; 5243 mcp->tov = 30; 5244 mcp->flags = 0; 5245 rval = qla2x00_mailbox_command(vha, mcp); 5246 if (rval != QLA_SUCCESS) { 5247 ql_dbg(ql_dbg_mbx, vha, 0x10f5, 5248 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5249 } else { 5250 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6, 5251 "Done %s.\n", __func__); 5252 *data = mcp->mb[3] << 16 | mcp->mb[2]; 5253 } 5254 5255 return rval; 5256 } 5257 5258 int 5259 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 5260 uint16_t *mresp) 5261 { 5262 int rval; 5263 mbx_cmd_t mc; 5264 mbx_cmd_t *mcp = &mc; 5265 5266 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7, 5267 "Entered %s.\n", __func__); 5268 5269 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5270 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK; 5271 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing 5272 5273 /* transfer count */ 5274 mcp->mb[10] = LSW(mreq->transfer_size); 5275 mcp->mb[11] = MSW(mreq->transfer_size); 5276 5277 /* send data address */ 5278 mcp->mb[14] = LSW(mreq->send_dma); 5279 mcp->mb[15] = MSW(mreq->send_dma); 5280 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 5281 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 5282 5283 /* receive data address */ 5284 mcp->mb[16] = LSW(mreq->rcv_dma); 5285 mcp->mb[17] = MSW(mreq->rcv_dma); 5286 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 5287 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 5288 5289 /* Iteration count */ 5290 mcp->mb[18] = LSW(mreq->iteration_count); 5291 mcp->mb[19] = MSW(mreq->iteration_count); 5292 5293 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| 5294 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 5295 if (IS_CNA_CAPABLE(vha->hw)) 5296 mcp->out_mb |= MBX_2; 5297 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; 5298 5299 mcp->buf_size = mreq->transfer_size; 5300 mcp->tov = MBX_TOV_SECONDS; 5301 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5302 5303 rval = qla2x00_mailbox_command(vha, mcp); 5304 5305 if (rval != QLA_SUCCESS) { 5306 ql_dbg(ql_dbg_mbx, vha, 0x10f8, 5307 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x " 5308 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], 5309 mcp->mb[3], mcp->mb[18], mcp->mb[19]); 5310 } else { 5311 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9, 5312 "Done %s.\n", __func__); 5313 } 5314 5315 /* Copy mailbox information */ 5316 memcpy( mresp, mcp->mb, 64); 5317 return rval; 5318 } 5319 5320 int 5321 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, 5322 uint16_t *mresp) 5323 { 5324 int rval; 5325 mbx_cmd_t mc; 5326 mbx_cmd_t *mcp = &mc; 5327 struct qla_hw_data *ha = vha->hw; 5328 5329 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa, 5330 "Entered %s.\n", __func__); 5331 5332 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5333 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; 5334 /* BIT_6 specifies 64bit address */ 5335 mcp->mb[1] = mreq->options | BIT_15 | BIT_6; 5336 if (IS_CNA_CAPABLE(ha)) { 5337 mcp->mb[2] = vha->fcoe_fcf_idx; 5338 } 5339 mcp->mb[16] = LSW(mreq->rcv_dma); 5340 mcp->mb[17] = MSW(mreq->rcv_dma); 5341 mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); 5342 mcp->mb[7] = MSW(MSD(mreq->rcv_dma)); 5343 5344 mcp->mb[10] = LSW(mreq->transfer_size); 5345 5346 mcp->mb[14] = LSW(mreq->send_dma); 5347 mcp->mb[15] = MSW(mreq->send_dma); 5348 mcp->mb[20] = LSW(MSD(mreq->send_dma)); 5349 mcp->mb[21] = MSW(MSD(mreq->send_dma)); 5350 5351 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| 5352 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; 5353 if (IS_CNA_CAPABLE(ha)) 5354 mcp->out_mb |= MBX_2; 5355 5356 mcp->in_mb = MBX_0; 5357 if (IS_CNA_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || 5358 IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5359 mcp->in_mb |= MBX_1; 5360 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 5361 IS_QLA28XX(ha)) 5362 mcp->in_mb |= MBX_3; 5363 5364 mcp->tov = MBX_TOV_SECONDS; 5365 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5366 mcp->buf_size = mreq->transfer_size; 5367 5368 rval = qla2x00_mailbox_command(vha, mcp); 5369 5370 if (rval != QLA_SUCCESS) { 5371 ql_dbg(ql_dbg_mbx, vha, 0x10fb, 5372 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5373 rval, mcp->mb[0], mcp->mb[1]); 5374 } else { 5375 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc, 5376 "Done %s.\n", __func__); 5377 } 5378 5379 /* Copy mailbox information */ 5380 memcpy(mresp, mcp->mb, 64); 5381 return rval; 5382 } 5383 5384 int 5385 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic) 5386 { 5387 int rval; 5388 mbx_cmd_t mc; 5389 mbx_cmd_t *mcp = &mc; 5390 5391 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd, 5392 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic); 5393 5394 mcp->mb[0] = MBC_ISP84XX_RESET; 5395 mcp->mb[1] = enable_diagnostic; 5396 mcp->out_mb = MBX_1|MBX_0; 5397 mcp->in_mb = MBX_1|MBX_0; 5398 mcp->tov = MBX_TOV_SECONDS; 5399 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5400 rval = qla2x00_mailbox_command(vha, mcp); 5401 5402 if (rval != QLA_SUCCESS) 5403 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval); 5404 else 5405 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff, 5406 "Done %s.\n", __func__); 5407 5408 return rval; 5409 } 5410 5411 int 5412 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data) 5413 { 5414 int rval; 5415 mbx_cmd_t mc; 5416 mbx_cmd_t *mcp = &mc; 5417 5418 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100, 5419 "Entered %s.\n", __func__); 5420 5421 if (!IS_FWI2_CAPABLE(vha->hw)) 5422 return QLA_FUNCTION_FAILED; 5423 5424 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED; 5425 mcp->mb[1] = LSW(risc_addr); 5426 mcp->mb[2] = LSW(data); 5427 mcp->mb[3] = MSW(data); 5428 mcp->mb[8] = MSW(risc_addr); 5429 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0; 5430 mcp->in_mb = MBX_1|MBX_0; 5431 mcp->tov = 30; 5432 mcp->flags = 0; 5433 rval = qla2x00_mailbox_command(vha, mcp); 5434 if (rval != QLA_SUCCESS) { 5435 ql_dbg(ql_dbg_mbx, vha, 0x1101, 5436 "Failed=%x mb[0]=%x mb[1]=%x.\n", 5437 rval, mcp->mb[0], mcp->mb[1]); 5438 } else { 5439 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102, 5440 "Done %s.\n", __func__); 5441 } 5442 5443 return rval; 5444 } 5445 5446 int 5447 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb) 5448 { 5449 int rval; 5450 uint32_t stat, timer; 5451 uint16_t mb0 = 0; 5452 struct qla_hw_data *ha = vha->hw; 5453 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 5454 5455 rval = QLA_SUCCESS; 5456 5457 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103, 5458 "Entered %s.\n", __func__); 5459 5460 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 5461 5462 /* Write the MBC data to the registers */ 5463 wrt_reg_word(®->mailbox0, MBC_WRITE_MPI_REGISTER); 5464 wrt_reg_word(®->mailbox1, mb[0]); 5465 wrt_reg_word(®->mailbox2, mb[1]); 5466 wrt_reg_word(®->mailbox3, mb[2]); 5467 wrt_reg_word(®->mailbox4, mb[3]); 5468 5469 wrt_reg_dword(®->hccr, HCCRX_SET_HOST_INT); 5470 5471 /* Poll for MBC interrupt */ 5472 for (timer = 6000000; timer; timer--) { 5473 /* Check for pending interrupts. */ 5474 stat = rd_reg_dword(®->host_status); 5475 if (stat & HSRX_RISC_INT) { 5476 stat &= 0xff; 5477 5478 if (stat == 0x1 || stat == 0x2 || 5479 stat == 0x10 || stat == 0x11) { 5480 set_bit(MBX_INTERRUPT, 5481 &ha->mbx_cmd_flags); 5482 mb0 = rd_reg_word(®->mailbox0); 5483 wrt_reg_dword(®->hccr, 5484 HCCRX_CLR_RISC_INT); 5485 rd_reg_dword(®->hccr); 5486 break; 5487 } 5488 } 5489 udelay(5); 5490 } 5491 5492 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) 5493 rval = mb0 & MBS_MASK; 5494 else 5495 rval = QLA_FUNCTION_FAILED; 5496 5497 if (rval != QLA_SUCCESS) { 5498 ql_dbg(ql_dbg_mbx, vha, 0x1104, 5499 "Failed=%x mb[0]=%x.\n", rval, mb[0]); 5500 } else { 5501 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105, 5502 "Done %s.\n", __func__); 5503 } 5504 5505 return rval; 5506 } 5507 5508 /* Set the specified data rate */ 5509 int 5510 qla2x00_set_data_rate(scsi_qla_host_t *vha, uint16_t mode) 5511 { 5512 int rval; 5513 mbx_cmd_t mc; 5514 mbx_cmd_t *mcp = &mc; 5515 struct qla_hw_data *ha = vha->hw; 5516 uint16_t val; 5517 5518 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106, 5519 "Entered %s speed:0x%x mode:0x%x.\n", __func__, ha->set_data_rate, 5520 mode); 5521 5522 if (!IS_FWI2_CAPABLE(ha)) 5523 return QLA_FUNCTION_FAILED; 5524 5525 memset(mcp, 0, sizeof(*mcp)); 5526 switch (ha->set_data_rate) { 5527 case PORT_SPEED_AUTO: 5528 case PORT_SPEED_4GB: 5529 case PORT_SPEED_8GB: 5530 case PORT_SPEED_16GB: 5531 case PORT_SPEED_32GB: 5532 val = ha->set_data_rate; 5533 break; 5534 default: 5535 ql_log(ql_log_warn, vha, 0x1199, 5536 "Unrecognized speed setting:%d. Setting Autoneg\n", 5537 ha->set_data_rate); 5538 val = ha->set_data_rate = PORT_SPEED_AUTO; 5539 break; 5540 } 5541 5542 mcp->mb[0] = MBC_DATA_RATE; 5543 mcp->mb[1] = mode; 5544 mcp->mb[2] = val; 5545 5546 mcp->out_mb = MBX_2|MBX_1|MBX_0; 5547 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5548 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5549 mcp->in_mb |= MBX_4|MBX_3; 5550 mcp->tov = MBX_TOV_SECONDS; 5551 mcp->flags = 0; 5552 rval = qla2x00_mailbox_command(vha, mcp); 5553 if (rval != QLA_SUCCESS) { 5554 ql_dbg(ql_dbg_mbx, vha, 0x1107, 5555 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5556 } else { 5557 if (mcp->mb[1] != 0x7) 5558 ql_dbg(ql_dbg_mbx, vha, 0x1179, 5559 "Speed set:0x%x\n", mcp->mb[1]); 5560 5561 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108, 5562 "Done %s.\n", __func__); 5563 } 5564 5565 return rval; 5566 } 5567 5568 int 5569 qla2x00_get_data_rate(scsi_qla_host_t *vha) 5570 { 5571 int rval; 5572 mbx_cmd_t mc; 5573 mbx_cmd_t *mcp = &mc; 5574 struct qla_hw_data *ha = vha->hw; 5575 5576 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106, 5577 "Entered %s.\n", __func__); 5578 5579 if (!IS_FWI2_CAPABLE(ha)) 5580 return QLA_FUNCTION_FAILED; 5581 5582 mcp->mb[0] = MBC_DATA_RATE; 5583 mcp->mb[1] = QLA_GET_DATA_RATE; 5584 mcp->out_mb = MBX_1|MBX_0; 5585 mcp->in_mb = MBX_2|MBX_1|MBX_0; 5586 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5587 mcp->in_mb |= MBX_3; 5588 mcp->tov = MBX_TOV_SECONDS; 5589 mcp->flags = 0; 5590 rval = qla2x00_mailbox_command(vha, mcp); 5591 if (rval != QLA_SUCCESS) { 5592 ql_dbg(ql_dbg_mbx, vha, 0x1107, 5593 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5594 } else { 5595 if (mcp->mb[1] != 0x7) 5596 ha->link_data_rate = mcp->mb[1]; 5597 5598 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 5599 if (mcp->mb[4] & BIT_0) 5600 ql_log(ql_log_info, vha, 0x11a2, 5601 "FEC=enabled (data rate).\n"); 5602 } 5603 5604 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108, 5605 "Done %s.\n", __func__); 5606 if (mcp->mb[1] != 0x7) 5607 ha->link_data_rate = mcp->mb[1]; 5608 } 5609 5610 return rval; 5611 } 5612 5613 int 5614 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb) 5615 { 5616 int rval; 5617 mbx_cmd_t mc; 5618 mbx_cmd_t *mcp = &mc; 5619 struct qla_hw_data *ha = vha->hw; 5620 5621 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109, 5622 "Entered %s.\n", __func__); 5623 5624 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) && 5625 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 5626 return QLA_FUNCTION_FAILED; 5627 mcp->mb[0] = MBC_GET_PORT_CONFIG; 5628 mcp->out_mb = MBX_0; 5629 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5630 mcp->tov = MBX_TOV_SECONDS; 5631 mcp->flags = 0; 5632 5633 rval = qla2x00_mailbox_command(vha, mcp); 5634 5635 if (rval != QLA_SUCCESS) { 5636 ql_dbg(ql_dbg_mbx, vha, 0x110a, 5637 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5638 } else { 5639 /* Copy all bits to preserve original value */ 5640 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4); 5641 5642 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b, 5643 "Done %s.\n", __func__); 5644 } 5645 return rval; 5646 } 5647 5648 int 5649 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb) 5650 { 5651 int rval; 5652 mbx_cmd_t mc; 5653 mbx_cmd_t *mcp = &mc; 5654 5655 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c, 5656 "Entered %s.\n", __func__); 5657 5658 mcp->mb[0] = MBC_SET_PORT_CONFIG; 5659 /* Copy all bits to preserve original setting */ 5660 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4); 5661 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5662 mcp->in_mb = MBX_0; 5663 mcp->tov = MBX_TOV_SECONDS; 5664 mcp->flags = 0; 5665 rval = qla2x00_mailbox_command(vha, mcp); 5666 5667 if (rval != QLA_SUCCESS) { 5668 ql_dbg(ql_dbg_mbx, vha, 0x110d, 5669 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5670 } else 5671 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e, 5672 "Done %s.\n", __func__); 5673 5674 return rval; 5675 } 5676 5677 5678 int 5679 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority, 5680 uint16_t *mb) 5681 { 5682 int rval; 5683 mbx_cmd_t mc; 5684 mbx_cmd_t *mcp = &mc; 5685 struct qla_hw_data *ha = vha->hw; 5686 5687 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f, 5688 "Entered %s.\n", __func__); 5689 5690 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 5691 return QLA_FUNCTION_FAILED; 5692 5693 mcp->mb[0] = MBC_PORT_PARAMS; 5694 mcp->mb[1] = loop_id; 5695 if (ha->flags.fcp_prio_enabled) 5696 mcp->mb[2] = BIT_1; 5697 else 5698 mcp->mb[2] = BIT_2; 5699 mcp->mb[4] = priority & 0xf; 5700 mcp->mb[9] = vha->vp_idx; 5701 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5702 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 5703 mcp->tov = 30; 5704 mcp->flags = 0; 5705 rval = qla2x00_mailbox_command(vha, mcp); 5706 if (mb != NULL) { 5707 mb[0] = mcp->mb[0]; 5708 mb[1] = mcp->mb[1]; 5709 mb[3] = mcp->mb[3]; 5710 mb[4] = mcp->mb[4]; 5711 } 5712 5713 if (rval != QLA_SUCCESS) { 5714 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval); 5715 } else { 5716 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc, 5717 "Done %s.\n", __func__); 5718 } 5719 5720 return rval; 5721 } 5722 5723 int 5724 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp) 5725 { 5726 int rval = QLA_FUNCTION_FAILED; 5727 struct qla_hw_data *ha = vha->hw; 5728 uint8_t byte; 5729 5730 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) { 5731 ql_dbg(ql_dbg_mbx, vha, 0x1150, 5732 "Thermal not supported by this card.\n"); 5733 return rval; 5734 } 5735 5736 if (IS_QLA25XX(ha)) { 5737 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 5738 ha->pdev->subsystem_device == 0x0175) { 5739 rval = qla2x00_read_sfp(vha, 0, &byte, 5740 0x98, 0x1, 1, BIT_13|BIT_0); 5741 *temp = byte; 5742 return rval; 5743 } 5744 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && 5745 ha->pdev->subsystem_device == 0x338e) { 5746 rval = qla2x00_read_sfp(vha, 0, &byte, 5747 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0); 5748 *temp = byte; 5749 return rval; 5750 } 5751 ql_dbg(ql_dbg_mbx, vha, 0x10c9, 5752 "Thermal not supported by this card.\n"); 5753 return rval; 5754 } 5755 5756 if (IS_QLA82XX(ha)) { 5757 *temp = qla82xx_read_temperature(vha); 5758 rval = QLA_SUCCESS; 5759 return rval; 5760 } else if (IS_QLA8044(ha)) { 5761 *temp = qla8044_read_temperature(vha); 5762 rval = QLA_SUCCESS; 5763 return rval; 5764 } 5765 5766 rval = qla2x00_read_asic_temperature(vha, temp); 5767 return rval; 5768 } 5769 5770 int 5771 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha) 5772 { 5773 int rval; 5774 struct qla_hw_data *ha = vha->hw; 5775 mbx_cmd_t mc; 5776 mbx_cmd_t *mcp = &mc; 5777 5778 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017, 5779 "Entered %s.\n", __func__); 5780 5781 if (!IS_FWI2_CAPABLE(ha)) 5782 return QLA_FUNCTION_FAILED; 5783 5784 memset(mcp, 0, sizeof(mbx_cmd_t)); 5785 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 5786 mcp->mb[1] = 1; 5787 5788 mcp->out_mb = MBX_1|MBX_0; 5789 mcp->in_mb = MBX_0; 5790 mcp->tov = 30; 5791 mcp->flags = 0; 5792 5793 rval = qla2x00_mailbox_command(vha, mcp); 5794 if (rval != QLA_SUCCESS) { 5795 ql_dbg(ql_dbg_mbx, vha, 0x1016, 5796 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5797 } else { 5798 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e, 5799 "Done %s.\n", __func__); 5800 } 5801 5802 return rval; 5803 } 5804 5805 int 5806 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha) 5807 { 5808 int rval; 5809 struct qla_hw_data *ha = vha->hw; 5810 mbx_cmd_t mc; 5811 mbx_cmd_t *mcp = &mc; 5812 5813 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d, 5814 "Entered %s.\n", __func__); 5815 5816 if (!IS_P3P_TYPE(ha)) 5817 return QLA_FUNCTION_FAILED; 5818 5819 memset(mcp, 0, sizeof(mbx_cmd_t)); 5820 mcp->mb[0] = MBC_TOGGLE_INTERRUPT; 5821 mcp->mb[1] = 0; 5822 5823 mcp->out_mb = MBX_1|MBX_0; 5824 mcp->in_mb = MBX_0; 5825 mcp->tov = 30; 5826 mcp->flags = 0; 5827 5828 rval = qla2x00_mailbox_command(vha, mcp); 5829 if (rval != QLA_SUCCESS) { 5830 ql_dbg(ql_dbg_mbx, vha, 0x100c, 5831 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 5832 } else { 5833 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b, 5834 "Done %s.\n", __func__); 5835 } 5836 5837 return rval; 5838 } 5839 5840 int 5841 qla82xx_md_get_template_size(scsi_qla_host_t *vha) 5842 { 5843 struct qla_hw_data *ha = vha->hw; 5844 mbx_cmd_t mc; 5845 mbx_cmd_t *mcp = &mc; 5846 int rval = QLA_FUNCTION_FAILED; 5847 5848 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f, 5849 "Entered %s.\n", __func__); 5850 5851 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5852 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5853 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5854 mcp->mb[2] = LSW(RQST_TMPLT_SIZE); 5855 mcp->mb[3] = MSW(RQST_TMPLT_SIZE); 5856 5857 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5858 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8| 5859 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5860 5861 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5862 mcp->tov = MBX_TOV_SECONDS; 5863 rval = qla2x00_mailbox_command(vha, mcp); 5864 5865 /* Always copy back return mailbox values. */ 5866 if (rval != QLA_SUCCESS) { 5867 ql_dbg(ql_dbg_mbx, vha, 0x1120, 5868 "mailbox command FAILED=0x%x, subcode=%x.\n", 5869 (mcp->mb[1] << 16) | mcp->mb[0], 5870 (mcp->mb[3] << 16) | mcp->mb[2]); 5871 } else { 5872 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121, 5873 "Done %s.\n", __func__); 5874 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]); 5875 if (!ha->md_template_size) { 5876 ql_dbg(ql_dbg_mbx, vha, 0x1122, 5877 "Null template size obtained.\n"); 5878 rval = QLA_FUNCTION_FAILED; 5879 } 5880 } 5881 return rval; 5882 } 5883 5884 int 5885 qla82xx_md_get_template(scsi_qla_host_t *vha) 5886 { 5887 struct qla_hw_data *ha = vha->hw; 5888 mbx_cmd_t mc; 5889 mbx_cmd_t *mcp = &mc; 5890 int rval = QLA_FUNCTION_FAILED; 5891 5892 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123, 5893 "Entered %s.\n", __func__); 5894 5895 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5896 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5897 if (!ha->md_tmplt_hdr) { 5898 ql_log(ql_log_warn, vha, 0x1124, 5899 "Unable to allocate memory for Minidump template.\n"); 5900 return rval; 5901 } 5902 5903 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5904 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5905 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5906 mcp->mb[2] = LSW(RQST_TMPLT); 5907 mcp->mb[3] = MSW(RQST_TMPLT); 5908 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma)); 5909 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma)); 5910 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma)); 5911 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma)); 5912 mcp->mb[8] = LSW(ha->md_template_size); 5913 mcp->mb[9] = MSW(ha->md_template_size); 5914 5915 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5916 mcp->tov = MBX_TOV_SECONDS; 5917 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5918 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5919 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5920 rval = qla2x00_mailbox_command(vha, mcp); 5921 5922 if (rval != QLA_SUCCESS) { 5923 ql_dbg(ql_dbg_mbx, vha, 0x1125, 5924 "mailbox command FAILED=0x%x, subcode=%x.\n", 5925 ((mcp->mb[1] << 16) | mcp->mb[0]), 5926 ((mcp->mb[3] << 16) | mcp->mb[2])); 5927 } else 5928 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126, 5929 "Done %s.\n", __func__); 5930 return rval; 5931 } 5932 5933 int 5934 qla8044_md_get_template(scsi_qla_host_t *vha) 5935 { 5936 struct qla_hw_data *ha = vha->hw; 5937 mbx_cmd_t mc; 5938 mbx_cmd_t *mcp = &mc; 5939 int rval = QLA_FUNCTION_FAILED; 5940 int offset = 0, size = MINIDUMP_SIZE_36K; 5941 5942 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f, 5943 "Entered %s.\n", __func__); 5944 5945 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev, 5946 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL); 5947 if (!ha->md_tmplt_hdr) { 5948 ql_log(ql_log_warn, vha, 0xb11b, 5949 "Unable to allocate memory for Minidump template.\n"); 5950 return rval; 5951 } 5952 5953 memset(mcp->mb, 0 , sizeof(mcp->mb)); 5954 while (offset < ha->md_template_size) { 5955 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5956 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE); 5957 mcp->mb[2] = LSW(RQST_TMPLT); 5958 mcp->mb[3] = MSW(RQST_TMPLT); 5959 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5960 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset)); 5961 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5962 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset)); 5963 mcp->mb[8] = LSW(size); 5964 mcp->mb[9] = MSW(size); 5965 mcp->mb[10] = offset & 0x0000FFFF; 5966 mcp->mb[11] = offset & 0xFFFF0000; 5967 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD; 5968 mcp->tov = MBX_TOV_SECONDS; 5969 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8| 5970 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 5971 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 5972 rval = qla2x00_mailbox_command(vha, mcp); 5973 5974 if (rval != QLA_SUCCESS) { 5975 ql_dbg(ql_dbg_mbx, vha, 0xb11c, 5976 "mailbox command FAILED=0x%x, subcode=%x.\n", 5977 ((mcp->mb[1] << 16) | mcp->mb[0]), 5978 ((mcp->mb[3] << 16) | mcp->mb[2])); 5979 return rval; 5980 } else 5981 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d, 5982 "Done %s.\n", __func__); 5983 offset = offset + size; 5984 } 5985 return rval; 5986 } 5987 5988 int 5989 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 5990 { 5991 int rval; 5992 struct qla_hw_data *ha = vha->hw; 5993 mbx_cmd_t mc; 5994 mbx_cmd_t *mcp = &mc; 5995 5996 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 5997 return QLA_FUNCTION_FAILED; 5998 5999 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133, 6000 "Entered %s.\n", __func__); 6001 6002 memset(mcp, 0, sizeof(mbx_cmd_t)); 6003 mcp->mb[0] = MBC_SET_LED_CONFIG; 6004 mcp->mb[1] = led_cfg[0]; 6005 mcp->mb[2] = led_cfg[1]; 6006 if (IS_QLA8031(ha)) { 6007 mcp->mb[3] = led_cfg[2]; 6008 mcp->mb[4] = led_cfg[3]; 6009 mcp->mb[5] = led_cfg[4]; 6010 mcp->mb[6] = led_cfg[5]; 6011 } 6012 6013 mcp->out_mb = MBX_2|MBX_1|MBX_0; 6014 if (IS_QLA8031(ha)) 6015 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 6016 mcp->in_mb = MBX_0; 6017 mcp->tov = 30; 6018 mcp->flags = 0; 6019 6020 rval = qla2x00_mailbox_command(vha, mcp); 6021 if (rval != QLA_SUCCESS) { 6022 ql_dbg(ql_dbg_mbx, vha, 0x1134, 6023 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 6024 } else { 6025 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135, 6026 "Done %s.\n", __func__); 6027 } 6028 6029 return rval; 6030 } 6031 6032 int 6033 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg) 6034 { 6035 int rval; 6036 struct qla_hw_data *ha = vha->hw; 6037 mbx_cmd_t mc; 6038 mbx_cmd_t *mcp = &mc; 6039 6040 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha)) 6041 return QLA_FUNCTION_FAILED; 6042 6043 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136, 6044 "Entered %s.\n", __func__); 6045 6046 memset(mcp, 0, sizeof(mbx_cmd_t)); 6047 mcp->mb[0] = MBC_GET_LED_CONFIG; 6048 6049 mcp->out_mb = MBX_0; 6050 mcp->in_mb = MBX_2|MBX_1|MBX_0; 6051 if (IS_QLA8031(ha)) 6052 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3; 6053 mcp->tov = 30; 6054 mcp->flags = 0; 6055 6056 rval = qla2x00_mailbox_command(vha, mcp); 6057 if (rval != QLA_SUCCESS) { 6058 ql_dbg(ql_dbg_mbx, vha, 0x1137, 6059 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 6060 } else { 6061 led_cfg[0] = mcp->mb[1]; 6062 led_cfg[1] = mcp->mb[2]; 6063 if (IS_QLA8031(ha)) { 6064 led_cfg[2] = mcp->mb[3]; 6065 led_cfg[3] = mcp->mb[4]; 6066 led_cfg[4] = mcp->mb[5]; 6067 led_cfg[5] = mcp->mb[6]; 6068 } 6069 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138, 6070 "Done %s.\n", __func__); 6071 } 6072 6073 return rval; 6074 } 6075 6076 int 6077 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable) 6078 { 6079 int rval; 6080 struct qla_hw_data *ha = vha->hw; 6081 mbx_cmd_t mc; 6082 mbx_cmd_t *mcp = &mc; 6083 6084 if (!IS_P3P_TYPE(ha)) 6085 return QLA_FUNCTION_FAILED; 6086 6087 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127, 6088 "Entered %s.\n", __func__); 6089 6090 memset(mcp, 0, sizeof(mbx_cmd_t)); 6091 mcp->mb[0] = MBC_SET_LED_CONFIG; 6092 if (enable) 6093 mcp->mb[7] = 0xE; 6094 else 6095 mcp->mb[7] = 0xD; 6096 6097 mcp->out_mb = MBX_7|MBX_0; 6098 mcp->in_mb = MBX_0; 6099 mcp->tov = MBX_TOV_SECONDS; 6100 mcp->flags = 0; 6101 6102 rval = qla2x00_mailbox_command(vha, mcp); 6103 if (rval != QLA_SUCCESS) { 6104 ql_dbg(ql_dbg_mbx, vha, 0x1128, 6105 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 6106 } else { 6107 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129, 6108 "Done %s.\n", __func__); 6109 } 6110 6111 return rval; 6112 } 6113 6114 int 6115 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data) 6116 { 6117 int rval; 6118 struct qla_hw_data *ha = vha->hw; 6119 mbx_cmd_t mc; 6120 mbx_cmd_t *mcp = &mc; 6121 6122 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 6123 return QLA_FUNCTION_FAILED; 6124 6125 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130, 6126 "Entered %s.\n", __func__); 6127 6128 mcp->mb[0] = MBC_WRITE_REMOTE_REG; 6129 mcp->mb[1] = LSW(reg); 6130 mcp->mb[2] = MSW(reg); 6131 mcp->mb[3] = LSW(data); 6132 mcp->mb[4] = MSW(data); 6133 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 6134 6135 mcp->in_mb = MBX_1|MBX_0; 6136 mcp->tov = MBX_TOV_SECONDS; 6137 mcp->flags = 0; 6138 rval = qla2x00_mailbox_command(vha, mcp); 6139 6140 if (rval != QLA_SUCCESS) { 6141 ql_dbg(ql_dbg_mbx, vha, 0x1131, 6142 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 6143 } else { 6144 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132, 6145 "Done %s.\n", __func__); 6146 } 6147 6148 return rval; 6149 } 6150 6151 int 6152 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport) 6153 { 6154 int rval; 6155 struct qla_hw_data *ha = vha->hw; 6156 mbx_cmd_t mc; 6157 mbx_cmd_t *mcp = &mc; 6158 6159 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 6160 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b, 6161 "Implicit LOGO Unsupported.\n"); 6162 return QLA_FUNCTION_FAILED; 6163 } 6164 6165 6166 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c, 6167 "Entering %s.\n", __func__); 6168 6169 /* Perform Implicit LOGO. */ 6170 mcp->mb[0] = MBC_PORT_LOGOUT; 6171 mcp->mb[1] = fcport->loop_id; 6172 mcp->mb[10] = BIT_15; 6173 mcp->out_mb = MBX_10|MBX_1|MBX_0; 6174 mcp->in_mb = MBX_0; 6175 mcp->tov = MBX_TOV_SECONDS; 6176 mcp->flags = 0; 6177 rval = qla2x00_mailbox_command(vha, mcp); 6178 if (rval != QLA_SUCCESS) 6179 ql_dbg(ql_dbg_mbx, vha, 0x113d, 6180 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 6181 else 6182 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e, 6183 "Done %s.\n", __func__); 6184 6185 return rval; 6186 } 6187 6188 int 6189 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data) 6190 { 6191 int rval; 6192 mbx_cmd_t mc; 6193 mbx_cmd_t *mcp = &mc; 6194 struct qla_hw_data *ha = vha->hw; 6195 unsigned long retry_max_time = jiffies + (2 * HZ); 6196 6197 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 6198 return QLA_FUNCTION_FAILED; 6199 6200 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__); 6201 6202 retry_rd_reg: 6203 mcp->mb[0] = MBC_READ_REMOTE_REG; 6204 mcp->mb[1] = LSW(reg); 6205 mcp->mb[2] = MSW(reg); 6206 mcp->out_mb = MBX_2|MBX_1|MBX_0; 6207 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0; 6208 mcp->tov = MBX_TOV_SECONDS; 6209 mcp->flags = 0; 6210 rval = qla2x00_mailbox_command(vha, mcp); 6211 6212 if (rval != QLA_SUCCESS) { 6213 ql_dbg(ql_dbg_mbx, vha, 0x114c, 6214 "Failed=%x mb[0]=%x mb[1]=%x.\n", 6215 rval, mcp->mb[0], mcp->mb[1]); 6216 } else { 6217 *data = (mcp->mb[3] | (mcp->mb[4] << 16)); 6218 if (*data == QLA8XXX_BAD_VALUE) { 6219 /* 6220 * During soft-reset CAMRAM register reads might 6221 * return 0xbad0bad0. So retry for MAX of 2 sec 6222 * while reading camram registers. 6223 */ 6224 if (time_after(jiffies, retry_max_time)) { 6225 ql_dbg(ql_dbg_mbx, vha, 0x1141, 6226 "Failure to read CAMRAM register. " 6227 "data=0x%x.\n", *data); 6228 return QLA_FUNCTION_FAILED; 6229 } 6230 msleep(100); 6231 goto retry_rd_reg; 6232 } 6233 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__); 6234 } 6235 6236 return rval; 6237 } 6238 6239 int 6240 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha) 6241 { 6242 int rval; 6243 mbx_cmd_t mc; 6244 mbx_cmd_t *mcp = &mc; 6245 struct qla_hw_data *ha = vha->hw; 6246 6247 if (!IS_QLA83XX(ha)) 6248 return QLA_FUNCTION_FAILED; 6249 6250 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__); 6251 6252 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE; 6253 mcp->out_mb = MBX_0; 6254 mcp->in_mb = MBX_1|MBX_0; 6255 mcp->tov = MBX_TOV_SECONDS; 6256 mcp->flags = 0; 6257 rval = qla2x00_mailbox_command(vha, mcp); 6258 6259 if (rval != QLA_SUCCESS) { 6260 ql_dbg(ql_dbg_mbx, vha, 0x1144, 6261 "Failed=%x mb[0]=%x mb[1]=%x.\n", 6262 rval, mcp->mb[0], mcp->mb[1]); 6263 qla2xxx_dump_fw(vha); 6264 } else { 6265 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__); 6266 } 6267 6268 return rval; 6269 } 6270 6271 int 6272 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options, 6273 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size) 6274 { 6275 int rval; 6276 mbx_cmd_t mc; 6277 mbx_cmd_t *mcp = &mc; 6278 uint8_t subcode = (uint8_t)options; 6279 struct qla_hw_data *ha = vha->hw; 6280 6281 if (!IS_QLA8031(ha)) 6282 return QLA_FUNCTION_FAILED; 6283 6284 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__); 6285 6286 mcp->mb[0] = MBC_SET_ACCESS_CONTROL; 6287 mcp->mb[1] = options; 6288 mcp->out_mb = MBX_1|MBX_0; 6289 if (subcode & BIT_2) { 6290 mcp->mb[2] = LSW(start_addr); 6291 mcp->mb[3] = MSW(start_addr); 6292 mcp->mb[4] = LSW(end_addr); 6293 mcp->mb[5] = MSW(end_addr); 6294 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2; 6295 } 6296 mcp->in_mb = MBX_2|MBX_1|MBX_0; 6297 if (!(subcode & (BIT_2 | BIT_5))) 6298 mcp->in_mb |= MBX_4|MBX_3; 6299 mcp->tov = MBX_TOV_SECONDS; 6300 mcp->flags = 0; 6301 rval = qla2x00_mailbox_command(vha, mcp); 6302 6303 if (rval != QLA_SUCCESS) { 6304 ql_dbg(ql_dbg_mbx, vha, 0x1147, 6305 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n", 6306 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], 6307 mcp->mb[4]); 6308 qla2xxx_dump_fw(vha); 6309 } else { 6310 if (subcode & BIT_5) 6311 *sector_size = mcp->mb[1]; 6312 else if (subcode & (BIT_6 | BIT_7)) { 6313 ql_dbg(ql_dbg_mbx, vha, 0x1148, 6314 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 6315 } else if (subcode & (BIT_3 | BIT_4)) { 6316 ql_dbg(ql_dbg_mbx, vha, 0x1149, 6317 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]); 6318 } 6319 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__); 6320 } 6321 6322 return rval; 6323 } 6324 6325 int 6326 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr, 6327 uint32_t size) 6328 { 6329 int rval; 6330 mbx_cmd_t mc; 6331 mbx_cmd_t *mcp = &mc; 6332 6333 if (!IS_MCTP_CAPABLE(vha->hw)) 6334 return QLA_FUNCTION_FAILED; 6335 6336 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f, 6337 "Entered %s.\n", __func__); 6338 6339 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED; 6340 mcp->mb[1] = LSW(addr); 6341 mcp->mb[2] = MSW(req_dma); 6342 mcp->mb[3] = LSW(req_dma); 6343 mcp->mb[4] = MSW(size); 6344 mcp->mb[5] = LSW(size); 6345 mcp->mb[6] = MSW(MSD(req_dma)); 6346 mcp->mb[7] = LSW(MSD(req_dma)); 6347 mcp->mb[8] = MSW(addr); 6348 /* Setting RAM ID to valid */ 6349 /* For MCTP RAM ID is 0x40 */ 6350 mcp->mb[10] = BIT_7 | 0x40; 6351 6352 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1| 6353 MBX_0; 6354 6355 mcp->in_mb = MBX_0; 6356 mcp->tov = MBX_TOV_SECONDS; 6357 mcp->flags = 0; 6358 rval = qla2x00_mailbox_command(vha, mcp); 6359 6360 if (rval != QLA_SUCCESS) { 6361 ql_dbg(ql_dbg_mbx, vha, 0x114e, 6362 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 6363 } else { 6364 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d, 6365 "Done %s.\n", __func__); 6366 } 6367 6368 return rval; 6369 } 6370 6371 int 6372 qla26xx_dport_diagnostics(scsi_qla_host_t *vha, 6373 void *dd_buf, uint size, uint options) 6374 { 6375 int rval; 6376 mbx_cmd_t mc; 6377 mbx_cmd_t *mcp = &mc; 6378 dma_addr_t dd_dma; 6379 6380 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) && 6381 !IS_QLA28XX(vha->hw)) 6382 return QLA_FUNCTION_FAILED; 6383 6384 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f, 6385 "Entered %s.\n", __func__); 6386 6387 dd_dma = dma_map_single(&vha->hw->pdev->dev, 6388 dd_buf, size, DMA_FROM_DEVICE); 6389 if (dma_mapping_error(&vha->hw->pdev->dev, dd_dma)) { 6390 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n"); 6391 return QLA_MEMORY_ALLOC_FAILED; 6392 } 6393 6394 memset(dd_buf, 0, size); 6395 6396 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS; 6397 mcp->mb[1] = options; 6398 mcp->mb[2] = MSW(LSD(dd_dma)); 6399 mcp->mb[3] = LSW(LSD(dd_dma)); 6400 mcp->mb[6] = MSW(MSD(dd_dma)); 6401 mcp->mb[7] = LSW(MSD(dd_dma)); 6402 mcp->mb[8] = size; 6403 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; 6404 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0; 6405 mcp->buf_size = size; 6406 mcp->flags = MBX_DMA_IN; 6407 mcp->tov = MBX_TOV_SECONDS * 4; 6408 rval = qla2x00_mailbox_command(vha, mcp); 6409 6410 if (rval != QLA_SUCCESS) { 6411 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval); 6412 } else { 6413 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196, 6414 "Done %s.\n", __func__); 6415 } 6416 6417 dma_unmap_single(&vha->hw->pdev->dev, dd_dma, 6418 size, DMA_FROM_DEVICE); 6419 6420 return rval; 6421 } 6422 6423 static void qla2x00_async_mb_sp_done(srb_t *sp, int res) 6424 { 6425 sp->u.iocb_cmd.u.mbx.rc = res; 6426 6427 complete(&sp->u.iocb_cmd.u.mbx.comp); 6428 /* don't free sp here. Let the caller do the free */ 6429 } 6430 6431 /* 6432 * This mailbox uses the iocb interface to send MB command. 6433 * This allows non-critial (non chip setup) command to go 6434 * out in parrallel. 6435 */ 6436 int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp) 6437 { 6438 int rval = QLA_FUNCTION_FAILED; 6439 srb_t *sp; 6440 struct srb_iocb *c; 6441 6442 if (!vha->hw->flags.fw_started) 6443 goto done; 6444 6445 sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL); 6446 if (!sp) 6447 goto done; 6448 6449 sp->type = SRB_MB_IOCB; 6450 sp->name = mb_to_str(mcp->mb[0]); 6451 6452 c = &sp->u.iocb_cmd; 6453 c->timeout = qla2x00_async_iocb_timeout; 6454 init_completion(&c->u.mbx.comp); 6455 6456 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 6457 6458 memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG); 6459 6460 sp->done = qla2x00_async_mb_sp_done; 6461 6462 rval = qla2x00_start_sp(sp); 6463 if (rval != QLA_SUCCESS) { 6464 ql_dbg(ql_dbg_mbx, vha, 0x1018, 6465 "%s: %s Failed submission. %x.\n", 6466 __func__, sp->name, rval); 6467 goto done_free_sp; 6468 } 6469 6470 ql_dbg(ql_dbg_mbx, vha, 0x113f, "MB:%s hndl %x submitted\n", 6471 sp->name, sp->handle); 6472 6473 wait_for_completion(&c->u.mbx.comp); 6474 memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG); 6475 6476 rval = c->u.mbx.rc; 6477 switch (rval) { 6478 case QLA_FUNCTION_TIMEOUT: 6479 ql_dbg(ql_dbg_mbx, vha, 0x1140, "%s: %s Timeout. %x.\n", 6480 __func__, sp->name, rval); 6481 break; 6482 case QLA_SUCCESS: 6483 ql_dbg(ql_dbg_mbx, vha, 0x119d, "%s: %s done.\n", 6484 __func__, sp->name); 6485 break; 6486 default: 6487 ql_dbg(ql_dbg_mbx, vha, 0x119e, "%s: %s Failed. %x.\n", 6488 __func__, sp->name, rval); 6489 break; 6490 } 6491 6492 done_free_sp: 6493 sp->free(sp); 6494 done: 6495 return rval; 6496 } 6497 6498 /* 6499 * qla24xx_gpdb_wait 6500 * NOTE: Do not call this routine from DPC thread 6501 */ 6502 int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 6503 { 6504 int rval = QLA_FUNCTION_FAILED; 6505 dma_addr_t pd_dma; 6506 struct port_database_24xx *pd; 6507 struct qla_hw_data *ha = vha->hw; 6508 mbx_cmd_t mc; 6509 6510 if (!vha->hw->flags.fw_started) 6511 goto done; 6512 6513 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 6514 if (pd == NULL) { 6515 ql_log(ql_log_warn, vha, 0xd047, 6516 "Failed to allocate port database structure.\n"); 6517 goto done_free_sp; 6518 } 6519 6520 memset(&mc, 0, sizeof(mc)); 6521 mc.mb[0] = MBC_GET_PORT_DATABASE; 6522 mc.mb[1] = fcport->loop_id; 6523 mc.mb[2] = MSW(pd_dma); 6524 mc.mb[3] = LSW(pd_dma); 6525 mc.mb[6] = MSW(MSD(pd_dma)); 6526 mc.mb[7] = LSW(MSD(pd_dma)); 6527 mc.mb[9] = vha->vp_idx; 6528 mc.mb[10] = opt; 6529 6530 rval = qla24xx_send_mb_cmd(vha, &mc); 6531 if (rval != QLA_SUCCESS) { 6532 ql_dbg(ql_dbg_mbx, vha, 0x1193, 6533 "%s: %8phC fail\n", __func__, fcport->port_name); 6534 goto done_free_sp; 6535 } 6536 6537 rval = __qla24xx_parse_gpdb(vha, fcport, pd); 6538 6539 ql_dbg(ql_dbg_mbx, vha, 0x1197, "%s: %8phC done\n", 6540 __func__, fcport->port_name); 6541 6542 done_free_sp: 6543 if (pd) 6544 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 6545 done: 6546 return rval; 6547 } 6548 6549 int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, 6550 struct port_database_24xx *pd) 6551 { 6552 int rval = QLA_SUCCESS; 6553 uint64_t zero = 0; 6554 u8 current_login_state, last_login_state; 6555 6556 if (NVME_TARGET(vha->hw, fcport)) { 6557 current_login_state = pd->current_login_state >> 4; 6558 last_login_state = pd->last_login_state >> 4; 6559 } else { 6560 current_login_state = pd->current_login_state & 0xf; 6561 last_login_state = pd->last_login_state & 0xf; 6562 } 6563 6564 /* Check for logged in state. */ 6565 if (current_login_state != PDS_PRLI_COMPLETE) { 6566 ql_dbg(ql_dbg_mbx, vha, 0x119a, 6567 "Unable to verify login-state (%x/%x) for loop_id %x.\n", 6568 current_login_state, last_login_state, fcport->loop_id); 6569 rval = QLA_FUNCTION_FAILED; 6570 goto gpd_error_out; 6571 } 6572 6573 if (fcport->loop_id == FC_NO_LOOP_ID || 6574 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) && 6575 memcmp(fcport->port_name, pd->port_name, 8))) { 6576 /* We lost the device mid way. */ 6577 rval = QLA_NOT_LOGGED_IN; 6578 goto gpd_error_out; 6579 } 6580 6581 /* Names are little-endian. */ 6582 memcpy(fcport->node_name, pd->node_name, WWN_SIZE); 6583 memcpy(fcport->port_name, pd->port_name, WWN_SIZE); 6584 6585 /* Get port_id of device. */ 6586 fcport->d_id.b.domain = pd->port_id[0]; 6587 fcport->d_id.b.area = pd->port_id[1]; 6588 fcport->d_id.b.al_pa = pd->port_id[2]; 6589 fcport->d_id.b.rsvd_1 = 0; 6590 6591 if (NVME_TARGET(vha->hw, fcport)) { 6592 fcport->port_type = FCT_NVME; 6593 if ((pd->prli_svc_param_word_3[0] & BIT_5) == 0) 6594 fcport->port_type |= FCT_NVME_INITIATOR; 6595 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 6596 fcport->port_type |= FCT_NVME_TARGET; 6597 if ((pd->prli_svc_param_word_3[0] & BIT_3) == 0) 6598 fcport->port_type |= FCT_NVME_DISCOVERY; 6599 } else { 6600 /* If not target must be initiator or unknown type. */ 6601 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0) 6602 fcport->port_type = FCT_INITIATOR; 6603 else 6604 fcport->port_type = FCT_TARGET; 6605 } 6606 /* Passback COS information. */ 6607 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ? 6608 FC_COS_CLASS2 : FC_COS_CLASS3; 6609 6610 if (pd->prli_svc_param_word_3[0] & BIT_7) { 6611 fcport->flags |= FCF_CONF_COMP_SUPPORTED; 6612 fcport->conf_compl_supported = 1; 6613 } 6614 6615 gpd_error_out: 6616 return rval; 6617 } 6618 6619 /* 6620 * qla24xx_gidlist__wait 6621 * NOTE: don't call this routine from DPC thread. 6622 */ 6623 int qla24xx_gidlist_wait(struct scsi_qla_host *vha, 6624 void *id_list, dma_addr_t id_list_dma, uint16_t *entries) 6625 { 6626 int rval = QLA_FUNCTION_FAILED; 6627 mbx_cmd_t mc; 6628 6629 if (!vha->hw->flags.fw_started) 6630 goto done; 6631 6632 memset(&mc, 0, sizeof(mc)); 6633 mc.mb[0] = MBC_GET_ID_LIST; 6634 mc.mb[2] = MSW(id_list_dma); 6635 mc.mb[3] = LSW(id_list_dma); 6636 mc.mb[6] = MSW(MSD(id_list_dma)); 6637 mc.mb[7] = LSW(MSD(id_list_dma)); 6638 mc.mb[8] = 0; 6639 mc.mb[9] = vha->vp_idx; 6640 6641 rval = qla24xx_send_mb_cmd(vha, &mc); 6642 if (rval != QLA_SUCCESS) { 6643 ql_dbg(ql_dbg_mbx, vha, 0x119b, 6644 "%s: fail\n", __func__); 6645 } else { 6646 *entries = mc.mb[1]; 6647 ql_dbg(ql_dbg_mbx, vha, 0x119c, 6648 "%s: done\n", __func__); 6649 } 6650 done: 6651 return rval; 6652 } 6653 6654 int qla27xx_set_zio_threshold(scsi_qla_host_t *vha, uint16_t value) 6655 { 6656 int rval; 6657 mbx_cmd_t mc; 6658 mbx_cmd_t *mcp = &mc; 6659 6660 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1200, 6661 "Entered %s\n", __func__); 6662 6663 memset(mcp->mb, 0 , sizeof(mcp->mb)); 6664 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD; 6665 mcp->mb[1] = 1; 6666 mcp->mb[2] = value; 6667 mcp->out_mb = MBX_2 | MBX_1 | MBX_0; 6668 mcp->in_mb = MBX_2 | MBX_0; 6669 mcp->tov = MBX_TOV_SECONDS; 6670 mcp->flags = 0; 6671 6672 rval = qla2x00_mailbox_command(vha, mcp); 6673 6674 ql_dbg(ql_dbg_mbx, vha, 0x1201, "%s %x\n", 6675 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval); 6676 6677 return rval; 6678 } 6679 6680 int qla27xx_get_zio_threshold(scsi_qla_host_t *vha, uint16_t *value) 6681 { 6682 int rval; 6683 mbx_cmd_t mc; 6684 mbx_cmd_t *mcp = &mc; 6685 6686 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1203, 6687 "Entered %s\n", __func__); 6688 6689 memset(mcp->mb, 0, sizeof(mcp->mb)); 6690 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD; 6691 mcp->mb[1] = 0; 6692 mcp->out_mb = MBX_1 | MBX_0; 6693 mcp->in_mb = MBX_2 | MBX_0; 6694 mcp->tov = MBX_TOV_SECONDS; 6695 mcp->flags = 0; 6696 6697 rval = qla2x00_mailbox_command(vha, mcp); 6698 if (rval == QLA_SUCCESS) 6699 *value = mc.mb[2]; 6700 6701 ql_dbg(ql_dbg_mbx, vha, 0x1205, "%s %x\n", 6702 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval); 6703 6704 return rval; 6705 } 6706 6707 int 6708 qla2x00_read_sfp_dev(struct scsi_qla_host *vha, char *buf, int count) 6709 { 6710 struct qla_hw_data *ha = vha->hw; 6711 uint16_t iter, addr, offset; 6712 dma_addr_t phys_addr; 6713 int rval, c; 6714 u8 *sfp_data; 6715 6716 memset(ha->sfp_data, 0, SFP_DEV_SIZE); 6717 addr = 0xa0; 6718 phys_addr = ha->sfp_data_dma; 6719 sfp_data = ha->sfp_data; 6720 offset = c = 0; 6721 6722 for (iter = 0; iter < SFP_DEV_SIZE / SFP_BLOCK_SIZE; iter++) { 6723 if (iter == 4) { 6724 /* Skip to next device address. */ 6725 addr = 0xa2; 6726 offset = 0; 6727 } 6728 6729 rval = qla2x00_read_sfp(vha, phys_addr, sfp_data, 6730 addr, offset, SFP_BLOCK_SIZE, BIT_1); 6731 if (rval != QLA_SUCCESS) { 6732 ql_log(ql_log_warn, vha, 0x706d, 6733 "Unable to read SFP data (%x/%x/%x).\n", rval, 6734 addr, offset); 6735 6736 return rval; 6737 } 6738 6739 if (buf && (c < count)) { 6740 u16 sz; 6741 6742 if ((count - c) >= SFP_BLOCK_SIZE) 6743 sz = SFP_BLOCK_SIZE; 6744 else 6745 sz = count - c; 6746 6747 memcpy(buf, sfp_data, sz); 6748 buf += SFP_BLOCK_SIZE; 6749 c += sz; 6750 } 6751 phys_addr += SFP_BLOCK_SIZE; 6752 sfp_data += SFP_BLOCK_SIZE; 6753 offset += SFP_BLOCK_SIZE; 6754 } 6755 6756 return rval; 6757 } 6758 6759 int qla24xx_res_count_wait(struct scsi_qla_host *vha, 6760 uint16_t *out_mb, int out_mb_sz) 6761 { 6762 int rval = QLA_FUNCTION_FAILED; 6763 mbx_cmd_t mc; 6764 6765 if (!vha->hw->flags.fw_started) 6766 goto done; 6767 6768 memset(&mc, 0, sizeof(mc)); 6769 mc.mb[0] = MBC_GET_RESOURCE_COUNTS; 6770 6771 rval = qla24xx_send_mb_cmd(vha, &mc); 6772 if (rval != QLA_SUCCESS) { 6773 ql_dbg(ql_dbg_mbx, vha, 0xffff, 6774 "%s: fail\n", __func__); 6775 } else { 6776 if (out_mb_sz <= SIZEOF_IOCB_MB_REG) 6777 memcpy(out_mb, mc.mb, out_mb_sz); 6778 else 6779 memcpy(out_mb, mc.mb, SIZEOF_IOCB_MB_REG); 6780 6781 ql_dbg(ql_dbg_mbx, vha, 0xffff, 6782 "%s: done\n", __func__); 6783 } 6784 done: 6785 return rval; 6786 } 6787 6788 int qla28xx_secure_flash_update(scsi_qla_host_t *vha, uint16_t opts, 6789 uint16_t region, uint32_t len, dma_addr_t sfub_dma_addr, 6790 uint32_t sfub_len) 6791 { 6792 int rval; 6793 mbx_cmd_t mc; 6794 mbx_cmd_t *mcp = &mc; 6795 6796 mcp->mb[0] = MBC_SECURE_FLASH_UPDATE; 6797 mcp->mb[1] = opts; 6798 mcp->mb[2] = region; 6799 mcp->mb[3] = MSW(len); 6800 mcp->mb[4] = LSW(len); 6801 mcp->mb[5] = MSW(sfub_dma_addr); 6802 mcp->mb[6] = LSW(sfub_dma_addr); 6803 mcp->mb[7] = MSW(MSD(sfub_dma_addr)); 6804 mcp->mb[8] = LSW(MSD(sfub_dma_addr)); 6805 mcp->mb[9] = sfub_len; 6806 mcp->out_mb = 6807 MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 6808 mcp->in_mb = MBX_2|MBX_1|MBX_0; 6809 mcp->tov = MBX_TOV_SECONDS; 6810 mcp->flags = 0; 6811 rval = qla2x00_mailbox_command(vha, mcp); 6812 6813 if (rval != QLA_SUCCESS) { 6814 ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s(%ld): failed rval 0x%x, %x %x %x", 6815 __func__, vha->host_no, rval, mcp->mb[0], mcp->mb[1], 6816 mcp->mb[2]); 6817 } 6818 6819 return rval; 6820 } 6821 6822 int qla2xxx_write_remote_register(scsi_qla_host_t *vha, uint32_t addr, 6823 uint32_t data) 6824 { 6825 int rval; 6826 mbx_cmd_t mc; 6827 mbx_cmd_t *mcp = &mc; 6828 6829 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8, 6830 "Entered %s.\n", __func__); 6831 6832 mcp->mb[0] = MBC_WRITE_REMOTE_REG; 6833 mcp->mb[1] = LSW(addr); 6834 mcp->mb[2] = MSW(addr); 6835 mcp->mb[3] = LSW(data); 6836 mcp->mb[4] = MSW(data); 6837 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 6838 mcp->in_mb = MBX_1|MBX_0; 6839 mcp->tov = MBX_TOV_SECONDS; 6840 mcp->flags = 0; 6841 rval = qla2x00_mailbox_command(vha, mcp); 6842 6843 if (rval != QLA_SUCCESS) { 6844 ql_dbg(ql_dbg_mbx, vha, 0x10e9, 6845 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 6846 } else { 6847 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea, 6848 "Done %s.\n", __func__); 6849 } 6850 6851 return rval; 6852 } 6853 6854 int qla2xxx_read_remote_register(scsi_qla_host_t *vha, uint32_t addr, 6855 uint32_t *data) 6856 { 6857 int rval; 6858 mbx_cmd_t mc; 6859 mbx_cmd_t *mcp = &mc; 6860 6861 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8, 6862 "Entered %s.\n", __func__); 6863 6864 mcp->mb[0] = MBC_READ_REMOTE_REG; 6865 mcp->mb[1] = LSW(addr); 6866 mcp->mb[2] = MSW(addr); 6867 mcp->out_mb = MBX_2|MBX_1|MBX_0; 6868 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0; 6869 mcp->tov = MBX_TOV_SECONDS; 6870 mcp->flags = 0; 6871 rval = qla2x00_mailbox_command(vha, mcp); 6872 6873 *data = (uint32_t)((((uint32_t)mcp->mb[4]) << 16) | mcp->mb[3]); 6874 6875 if (rval != QLA_SUCCESS) { 6876 ql_dbg(ql_dbg_mbx, vha, 0x10e9, 6877 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]); 6878 } else { 6879 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea, 6880 "Done %s.\n", __func__); 6881 } 6882 6883 return rval; 6884 } 6885 6886 int 6887 ql26xx_led_config(scsi_qla_host_t *vha, uint16_t options, uint16_t *led) 6888 { 6889 struct qla_hw_data *ha = vha->hw; 6890 mbx_cmd_t mc; 6891 mbx_cmd_t *mcp = &mc; 6892 int rval; 6893 6894 if (!IS_QLA2031(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 6895 return QLA_FUNCTION_FAILED; 6896 6897 ql_dbg(ql_dbg_mbx, vha, 0x7070, "Entered %s (options=%x).\n", 6898 __func__, options); 6899 6900 mcp->mb[0] = MBC_SET_GET_FC_LED_CONFIG; 6901 mcp->mb[1] = options; 6902 mcp->out_mb = MBX_1|MBX_0; 6903 mcp->in_mb = MBX_1|MBX_0; 6904 if (options & BIT_0) { 6905 if (options & BIT_1) { 6906 mcp->mb[2] = led[2]; 6907 mcp->out_mb |= MBX_2; 6908 } 6909 if (options & BIT_2) { 6910 mcp->mb[3] = led[0]; 6911 mcp->out_mb |= MBX_3; 6912 } 6913 if (options & BIT_3) { 6914 mcp->mb[4] = led[1]; 6915 mcp->out_mb |= MBX_4; 6916 } 6917 } else { 6918 mcp->in_mb |= MBX_4|MBX_3|MBX_2; 6919 } 6920 mcp->tov = MBX_TOV_SECONDS; 6921 mcp->flags = 0; 6922 rval = qla2x00_mailbox_command(vha, mcp); 6923 if (rval) { 6924 ql_dbg(ql_dbg_mbx, vha, 0x7071, "Failed %s %x (mb=%x,%x)\n", 6925 __func__, rval, mcp->mb[0], mcp->mb[1]); 6926 return rval; 6927 } 6928 6929 if (options & BIT_0) { 6930 ha->beacon_blink_led = 0; 6931 ql_dbg(ql_dbg_mbx, vha, 0x7072, "Done %s\n", __func__); 6932 } else { 6933 led[2] = mcp->mb[2]; 6934 led[0] = mcp->mb[3]; 6935 led[1] = mcp->mb[4]; 6936 ql_dbg(ql_dbg_mbx, vha, 0x7073, "Done %s (led=%x,%x,%x)\n", 6937 __func__, led[0], led[1], led[2]); 6938 } 6939 6940 return rval; 6941 } 6942