1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_gbl.h" 9 10 #include <linux/delay.h> 11 #include <linux/slab.h> 12 #include <linux/vmalloc.h> 13 14 #include "qla_devtbl.h" 15 16 #ifdef CONFIG_SPARC 17 #include <asm/prom.h> 18 #endif 19 20 #include <target/target_core_base.h> 21 #include "qla_target.h" 22 23 /* 24 * QLogic ISP2x00 Hardware Support Function Prototypes. 25 */ 26 static int qla2x00_isp_firmware(scsi_qla_host_t *); 27 static int qla2x00_setup_chip(scsi_qla_host_t *); 28 static int qla2x00_fw_ready(scsi_qla_host_t *); 29 static int qla2x00_configure_hba(scsi_qla_host_t *); 30 static int qla2x00_configure_loop(scsi_qla_host_t *); 31 static int qla2x00_configure_local_loop(scsi_qla_host_t *); 32 static int qla2x00_configure_fabric(scsi_qla_host_t *); 33 static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *); 34 static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *, 35 uint16_t *); 36 37 static int qla2x00_restart_isp(scsi_qla_host_t *); 38 39 static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *); 40 static int qla84xx_init_chip(scsi_qla_host_t *); 41 static int qla25xx_init_queues(struct qla_hw_data *); 42 43 /* SRB Extensions ---------------------------------------------------------- */ 44 45 void 46 qla2x00_sp_timeout(unsigned long __data) 47 { 48 srb_t *sp = (srb_t *)__data; 49 struct srb_iocb *iocb; 50 fc_port_t *fcport = sp->fcport; 51 struct qla_hw_data *ha = fcport->vha->hw; 52 struct req_que *req; 53 unsigned long flags; 54 55 spin_lock_irqsave(&ha->hardware_lock, flags); 56 req = ha->req_q_map[0]; 57 req->outstanding_cmds[sp->handle] = NULL; 58 iocb = &sp->u.iocb_cmd; 59 iocb->timeout(sp); 60 sp->free(fcport->vha, sp); 61 spin_unlock_irqrestore(&ha->hardware_lock, flags); 62 } 63 64 void 65 qla2x00_sp_free(void *data, void *ptr) 66 { 67 srb_t *sp = (srb_t *)ptr; 68 struct srb_iocb *iocb = &sp->u.iocb_cmd; 69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data; 70 71 del_timer(&iocb->timer); 72 qla2x00_rel_sp(vha, sp); 73 } 74 75 /* Asynchronous Login/Logout Routines -------------------------------------- */ 76 77 unsigned long 78 qla2x00_get_async_timeout(struct scsi_qla_host *vha) 79 { 80 unsigned long tmo; 81 struct qla_hw_data *ha = vha->hw; 82 83 /* Firmware should use switch negotiated r_a_tov for timeout. */ 84 tmo = ha->r_a_tov / 10 * 2; 85 if (IS_QLAFX00(ha)) { 86 tmo = FX00_DEF_RATOV * 2; 87 } else if (!IS_FWI2_CAPABLE(ha)) { 88 /* 89 * Except for earlier ISPs where the timeout is seeded from the 90 * initialization control block. 91 */ 92 tmo = ha->login_timeout; 93 } 94 return tmo; 95 } 96 97 static void 98 qla2x00_async_iocb_timeout(void *data) 99 { 100 srb_t *sp = (srb_t *)data; 101 fc_port_t *fcport = sp->fcport; 102 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n", 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area, 106 fcport->d_id.b.al_pa); 107 108 fcport->flags &= ~FCF_ASYNC_SENT; 109 if (sp->type == SRB_LOGIN_CMD) { 110 struct srb_iocb *lio = &sp->u.iocb_cmd; 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL); 112 /* Retry as needed. */ 113 lio->u.logio.data[0] = MBS_COMMAND_ERROR; 114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ? 115 QLA_LOGIO_LOGIN_RETRIED : 0; 116 qla2x00_post_async_login_done_work(fcport->vha, fcport, 117 lio->u.logio.data); 118 } 119 } 120 121 static void 122 qla2x00_async_login_sp_done(void *data, void *ptr, int res) 123 { 124 srb_t *sp = (srb_t *)ptr; 125 struct srb_iocb *lio = &sp->u.iocb_cmd; 126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data; 127 128 if (!test_bit(UNLOADING, &vha->dpc_flags)) 129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport, 130 lio->u.logio.data); 131 sp->free(sp->fcport->vha, sp); 132 } 133 134 int 135 qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport, 136 uint16_t *data) 137 { 138 srb_t *sp; 139 struct srb_iocb *lio; 140 int rval; 141 142 rval = QLA_FUNCTION_FAILED; 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 144 if (!sp) 145 goto done; 146 147 sp->type = SRB_LOGIN_CMD; 148 sp->name = "login"; 149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 150 151 lio = &sp->u.iocb_cmd; 152 lio->timeout = qla2x00_async_iocb_timeout; 153 sp->done = qla2x00_async_login_sp_done; 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI; 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED; 157 rval = qla2x00_start_sp(sp); 158 if (rval != QLA_SUCCESS) 159 goto done_free_sp; 160 161 ql_dbg(ql_dbg_disc, vha, 0x2072, 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x " 163 "retries=%d.\n", sp->handle, fcport->loop_id, 164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa, 165 fcport->login_retry); 166 return rval; 167 168 done_free_sp: 169 sp->free(fcport->vha, sp); 170 done: 171 return rval; 172 } 173 174 static void 175 qla2x00_async_logout_sp_done(void *data, void *ptr, int res) 176 { 177 srb_t *sp = (srb_t *)ptr; 178 struct srb_iocb *lio = &sp->u.iocb_cmd; 179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data; 180 181 if (!test_bit(UNLOADING, &vha->dpc_flags)) 182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport, 183 lio->u.logio.data); 184 sp->free(sp->fcport->vha, sp); 185 } 186 187 int 188 qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport) 189 { 190 srb_t *sp; 191 struct srb_iocb *lio; 192 int rval; 193 194 rval = QLA_FUNCTION_FAILED; 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 196 if (!sp) 197 goto done; 198 199 sp->type = SRB_LOGOUT_CMD; 200 sp->name = "logout"; 201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 202 203 lio = &sp->u.iocb_cmd; 204 lio->timeout = qla2x00_async_iocb_timeout; 205 sp->done = qla2x00_async_logout_sp_done; 206 rval = qla2x00_start_sp(sp); 207 if (rval != QLA_SUCCESS) 208 goto done_free_sp; 209 210 ql_dbg(ql_dbg_disc, vha, 0x2070, 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 212 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 213 fcport->d_id.b.area, fcport->d_id.b.al_pa); 214 return rval; 215 216 done_free_sp: 217 sp->free(fcport->vha, sp); 218 done: 219 return rval; 220 } 221 222 static void 223 qla2x00_async_adisc_sp_done(void *data, void *ptr, int res) 224 { 225 srb_t *sp = (srb_t *)ptr; 226 struct srb_iocb *lio = &sp->u.iocb_cmd; 227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data; 228 229 if (!test_bit(UNLOADING, &vha->dpc_flags)) 230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport, 231 lio->u.logio.data); 232 sp->free(sp->fcport->vha, sp); 233 } 234 235 int 236 qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport, 237 uint16_t *data) 238 { 239 srb_t *sp; 240 struct srb_iocb *lio; 241 int rval; 242 243 rval = QLA_FUNCTION_FAILED; 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 245 if (!sp) 246 goto done; 247 248 sp->type = SRB_ADISC_CMD; 249 sp->name = "adisc"; 250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 251 252 lio = &sp->u.iocb_cmd; 253 lio->timeout = qla2x00_async_iocb_timeout; 254 sp->done = qla2x00_async_adisc_sp_done; 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED; 257 rval = qla2x00_start_sp(sp); 258 if (rval != QLA_SUCCESS) 259 goto done_free_sp; 260 261 ql_dbg(ql_dbg_disc, vha, 0x206f, 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n", 263 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 264 fcport->d_id.b.area, fcport->d_id.b.al_pa); 265 return rval; 266 267 done_free_sp: 268 sp->free(fcport->vha, sp); 269 done: 270 return rval; 271 } 272 273 static void 274 qla2x00_async_tm_cmd_done(void *data, void *ptr, int res) 275 { 276 srb_t *sp = (srb_t *)ptr; 277 struct srb_iocb *iocb = &sp->u.iocb_cmd; 278 struct scsi_qla_host *vha = (scsi_qla_host_t *)data; 279 uint32_t flags; 280 uint16_t lun; 281 int rval; 282 283 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 284 flags = iocb->u.tmf.flags; 285 lun = (uint16_t)iocb->u.tmf.lun; 286 287 /* Issue Marker IOCB */ 288 rval = qla2x00_marker(vha, vha->hw->req_q_map[0], 289 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun, 290 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID); 291 292 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) { 293 ql_dbg(ql_dbg_taskm, vha, 0x8030, 294 "TM IOCB failed (%x).\n", rval); 295 } 296 } 297 sp->free(sp->fcport->vha, sp); 298 } 299 300 int 301 qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun, 302 uint32_t tag) 303 { 304 struct scsi_qla_host *vha = fcport->vha; 305 srb_t *sp; 306 struct srb_iocb *tcf; 307 int rval; 308 309 rval = QLA_FUNCTION_FAILED; 310 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 311 if (!sp) 312 goto done; 313 314 sp->type = SRB_TM_CMD; 315 sp->name = "tmf"; 316 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 317 318 tcf = &sp->u.iocb_cmd; 319 tcf->u.tmf.flags = tm_flags; 320 tcf->u.tmf.lun = lun; 321 tcf->u.tmf.data = tag; 322 tcf->timeout = qla2x00_async_iocb_timeout; 323 sp->done = qla2x00_async_tm_cmd_done; 324 325 rval = qla2x00_start_sp(sp); 326 if (rval != QLA_SUCCESS) 327 goto done_free_sp; 328 329 ql_dbg(ql_dbg_taskm, vha, 0x802f, 330 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 331 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 332 fcport->d_id.b.area, fcport->d_id.b.al_pa); 333 return rval; 334 335 done_free_sp: 336 sp->free(fcport->vha, sp); 337 done: 338 return rval; 339 } 340 341 void 342 qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport, 343 uint16_t *data) 344 { 345 int rval; 346 347 switch (data[0]) { 348 case MBS_COMMAND_COMPLETE: 349 /* 350 * Driver must validate login state - If PRLI not complete, 351 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI 352 * requests. 353 */ 354 rval = qla2x00_get_port_database(vha, fcport, 0); 355 if (rval == QLA_NOT_LOGGED_IN) { 356 fcport->flags &= ~FCF_ASYNC_SENT; 357 fcport->flags |= FCF_LOGIN_NEEDED; 358 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 359 break; 360 } 361 362 if (rval != QLA_SUCCESS) { 363 qla2x00_post_async_logout_work(vha, fcport, NULL); 364 qla2x00_post_async_login_work(vha, fcport, NULL); 365 break; 366 } 367 if (fcport->flags & FCF_FCP2_DEVICE) { 368 qla2x00_post_async_adisc_work(vha, fcport, data); 369 break; 370 } 371 qla2x00_update_fcport(vha, fcport); 372 break; 373 case MBS_COMMAND_ERROR: 374 fcport->flags &= ~FCF_ASYNC_SENT; 375 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 376 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 377 else 378 qla2x00_mark_device_lost(vha, fcport, 1, 0); 379 break; 380 case MBS_PORT_ID_USED: 381 fcport->loop_id = data[1]; 382 qla2x00_post_async_logout_work(vha, fcport, NULL); 383 qla2x00_post_async_login_work(vha, fcport, NULL); 384 break; 385 case MBS_LOOP_ID_USED: 386 fcport->loop_id++; 387 rval = qla2x00_find_new_loop_id(vha, fcport); 388 if (rval != QLA_SUCCESS) { 389 fcport->flags &= ~FCF_ASYNC_SENT; 390 qla2x00_mark_device_lost(vha, fcport, 1, 0); 391 break; 392 } 393 qla2x00_post_async_login_work(vha, fcport, NULL); 394 break; 395 } 396 return; 397 } 398 399 void 400 qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport, 401 uint16_t *data) 402 { 403 qla2x00_mark_device_lost(vha, fcport, 1, 0); 404 return; 405 } 406 407 void 408 qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport, 409 uint16_t *data) 410 { 411 if (data[0] == MBS_COMMAND_COMPLETE) { 412 qla2x00_update_fcport(vha, fcport); 413 414 return; 415 } 416 417 /* Retry login. */ 418 fcport->flags &= ~FCF_ASYNC_SENT; 419 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 420 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 421 else 422 qla2x00_mark_device_lost(vha, fcport, 1, 0); 423 424 return; 425 } 426 427 /****************************************************************************/ 428 /* QLogic ISP2x00 Hardware Support Functions. */ 429 /****************************************************************************/ 430 431 static int 432 qla83xx_nic_core_fw_load(scsi_qla_host_t *vha) 433 { 434 int rval = QLA_SUCCESS; 435 struct qla_hw_data *ha = vha->hw; 436 uint32_t idc_major_ver, idc_minor_ver; 437 uint16_t config[4]; 438 439 qla83xx_idc_lock(vha, 0); 440 441 /* SV: TODO: Assign initialization timeout from 442 * flash-info / other param 443 */ 444 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT; 445 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT; 446 447 /* Set our fcoe function presence */ 448 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) { 449 ql_dbg(ql_dbg_p3p, vha, 0xb077, 450 "Error while setting DRV-Presence.\n"); 451 rval = QLA_FUNCTION_FAILED; 452 goto exit; 453 } 454 455 /* Decide the reset ownership */ 456 qla83xx_reset_ownership(vha); 457 458 /* 459 * On first protocol driver load: 460 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery 461 * register. 462 * Others: Check compatibility with current IDC Major version. 463 */ 464 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver); 465 if (ha->flags.nic_core_reset_owner) { 466 /* Set IDC Major version */ 467 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION; 468 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver); 469 470 /* Clearing IDC-Lock-Recovery register */ 471 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0); 472 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) { 473 /* 474 * Clear further IDC participation if we are not compatible with 475 * the current IDC Major Version. 476 */ 477 ql_log(ql_log_warn, vha, 0xb07d, 478 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n", 479 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION); 480 __qla83xx_clear_drv_presence(vha); 481 rval = QLA_FUNCTION_FAILED; 482 goto exit; 483 } 484 /* Each function sets its supported Minor version. */ 485 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver); 486 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2)); 487 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver); 488 489 if (ha->flags.nic_core_reset_owner) { 490 memset(config, 0, sizeof(config)); 491 if (!qla81xx_get_port_config(vha, config)) 492 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 493 QLA8XXX_DEV_READY); 494 } 495 496 rval = qla83xx_idc_state_handler(vha); 497 498 exit: 499 qla83xx_idc_unlock(vha, 0); 500 501 return rval; 502 } 503 504 /* 505 * qla2x00_initialize_adapter 506 * Initialize board. 507 * 508 * Input: 509 * ha = adapter block pointer. 510 * 511 * Returns: 512 * 0 = success 513 */ 514 int 515 qla2x00_initialize_adapter(scsi_qla_host_t *vha) 516 { 517 int rval; 518 struct qla_hw_data *ha = vha->hw; 519 struct req_que *req = ha->req_q_map[0]; 520 521 /* Clear adapter flags. */ 522 vha->flags.online = 0; 523 ha->flags.chip_reset_done = 0; 524 vha->flags.reset_active = 0; 525 ha->flags.pci_channel_io_perm_failure = 0; 526 ha->flags.eeh_busy = 0; 527 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64(); 528 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 529 atomic_set(&vha->loop_state, LOOP_DOWN); 530 vha->device_flags = DFLG_NO_CABLE; 531 vha->dpc_flags = 0; 532 vha->flags.management_server_logged_in = 0; 533 vha->marker_needed = 0; 534 ha->isp_abort_cnt = 0; 535 ha->beacon_blink_led = 0; 536 537 set_bit(0, ha->req_qid_map); 538 set_bit(0, ha->rsp_qid_map); 539 540 ql_dbg(ql_dbg_init, vha, 0x0040, 541 "Configuring PCI space...\n"); 542 rval = ha->isp_ops->pci_config(vha); 543 if (rval) { 544 ql_log(ql_log_warn, vha, 0x0044, 545 "Unable to configure PCI space.\n"); 546 return (rval); 547 } 548 549 ha->isp_ops->reset_chip(vha); 550 551 rval = qla2xxx_get_flash_info(vha); 552 if (rval) { 553 ql_log(ql_log_fatal, vha, 0x004f, 554 "Unable to validate FLASH data.\n"); 555 return rval; 556 } 557 558 if (IS_QLA8044(ha)) { 559 qla8044_read_reset_template(vha); 560 561 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0. 562 * If DONRESET_BIT0 is set, drivers should not set dev_state 563 * to NEED_RESET. But if NEED_RESET is set, drivers should 564 * should honor the reset. */ 565 if (ql2xdontresethba == 1) 566 qla8044_set_idc_dontreset(vha); 567 } 568 569 ha->isp_ops->get_flash_version(vha, req->ring); 570 ql_dbg(ql_dbg_init, vha, 0x0061, 571 "Configure NVRAM parameters...\n"); 572 573 ha->isp_ops->nvram_config(vha); 574 575 if (ha->flags.disable_serdes) { 576 /* Mask HBA via NVRAM settings? */ 577 ql_log(ql_log_info, vha, 0x0077, 578 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name); 579 return QLA_FUNCTION_FAILED; 580 } 581 582 ql_dbg(ql_dbg_init, vha, 0x0078, 583 "Verifying loaded RISC code...\n"); 584 585 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) { 586 rval = ha->isp_ops->chip_diag(vha); 587 if (rval) 588 return (rval); 589 rval = qla2x00_setup_chip(vha); 590 if (rval) 591 return (rval); 592 } 593 594 if (IS_QLA84XX(ha)) { 595 ha->cs84xx = qla84xx_get_chip(vha); 596 if (!ha->cs84xx) { 597 ql_log(ql_log_warn, vha, 0x00d0, 598 "Unable to configure ISP84XX.\n"); 599 return QLA_FUNCTION_FAILED; 600 } 601 } 602 603 if (qla_ini_mode_enabled(vha)) 604 rval = qla2x00_init_rings(vha); 605 606 ha->flags.chip_reset_done = 1; 607 608 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) { 609 /* Issue verify 84xx FW IOCB to complete 84xx initialization */ 610 rval = qla84xx_init_chip(vha); 611 if (rval != QLA_SUCCESS) { 612 ql_log(ql_log_warn, vha, 0x00d4, 613 "Unable to initialize ISP84XX.\n"); 614 qla84xx_put_chip(vha); 615 } 616 } 617 618 /* Load the NIC Core f/w if we are the first protocol driver. */ 619 if (IS_QLA8031(ha)) { 620 rval = qla83xx_nic_core_fw_load(vha); 621 if (rval) 622 ql_log(ql_log_warn, vha, 0x0124, 623 "Error in initializing NIC Core f/w.\n"); 624 } 625 626 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)) 627 qla24xx_read_fcp_prio_cfg(vha); 628 629 if (IS_P3P_TYPE(ha)) 630 qla82xx_set_driver_version(vha, QLA2XXX_VERSION); 631 else 632 qla25xx_set_driver_version(vha, QLA2XXX_VERSION); 633 634 return (rval); 635 } 636 637 /** 638 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers. 639 * @ha: HA context 640 * 641 * Returns 0 on success. 642 */ 643 int 644 qla2100_pci_config(scsi_qla_host_t *vha) 645 { 646 uint16_t w; 647 unsigned long flags; 648 struct qla_hw_data *ha = vha->hw; 649 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 650 651 pci_set_master(ha->pdev); 652 pci_try_set_mwi(ha->pdev); 653 654 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 655 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 656 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 657 658 pci_disable_rom(ha->pdev); 659 660 /* Get PCI bus information. */ 661 spin_lock_irqsave(&ha->hardware_lock, flags); 662 ha->pci_attr = RD_REG_WORD(®->ctrl_status); 663 spin_unlock_irqrestore(&ha->hardware_lock, flags); 664 665 return QLA_SUCCESS; 666 } 667 668 /** 669 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers. 670 * @ha: HA context 671 * 672 * Returns 0 on success. 673 */ 674 int 675 qla2300_pci_config(scsi_qla_host_t *vha) 676 { 677 uint16_t w; 678 unsigned long flags = 0; 679 uint32_t cnt; 680 struct qla_hw_data *ha = vha->hw; 681 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 682 683 pci_set_master(ha->pdev); 684 pci_try_set_mwi(ha->pdev); 685 686 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 687 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 688 689 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 690 w &= ~PCI_COMMAND_INTX_DISABLE; 691 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 692 693 /* 694 * If this is a 2300 card and not 2312, reset the 695 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately, 696 * the 2310 also reports itself as a 2300 so we need to get the 697 * fb revision level -- a 6 indicates it really is a 2300 and 698 * not a 2310. 699 */ 700 if (IS_QLA2300(ha)) { 701 spin_lock_irqsave(&ha->hardware_lock, flags); 702 703 /* Pause RISC. */ 704 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 705 for (cnt = 0; cnt < 30000; cnt++) { 706 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) 707 break; 708 709 udelay(10); 710 } 711 712 /* Select FPM registers. */ 713 WRT_REG_WORD(®->ctrl_status, 0x20); 714 RD_REG_WORD(®->ctrl_status); 715 716 /* Get the fb rev level */ 717 ha->fb_rev = RD_FB_CMD_REG(ha, reg); 718 719 if (ha->fb_rev == FPM_2300) 720 pci_clear_mwi(ha->pdev); 721 722 /* Deselect FPM registers. */ 723 WRT_REG_WORD(®->ctrl_status, 0x0); 724 RD_REG_WORD(®->ctrl_status); 725 726 /* Release RISC module. */ 727 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 728 for (cnt = 0; cnt < 30000; cnt++) { 729 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0) 730 break; 731 732 udelay(10); 733 } 734 735 spin_unlock_irqrestore(&ha->hardware_lock, flags); 736 } 737 738 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 739 740 pci_disable_rom(ha->pdev); 741 742 /* Get PCI bus information. */ 743 spin_lock_irqsave(&ha->hardware_lock, flags); 744 ha->pci_attr = RD_REG_WORD(®->ctrl_status); 745 spin_unlock_irqrestore(&ha->hardware_lock, flags); 746 747 return QLA_SUCCESS; 748 } 749 750 /** 751 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers. 752 * @ha: HA context 753 * 754 * Returns 0 on success. 755 */ 756 int 757 qla24xx_pci_config(scsi_qla_host_t *vha) 758 { 759 uint16_t w; 760 unsigned long flags = 0; 761 struct qla_hw_data *ha = vha->hw; 762 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 763 764 pci_set_master(ha->pdev); 765 pci_try_set_mwi(ha->pdev); 766 767 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 768 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 769 w &= ~PCI_COMMAND_INTX_DISABLE; 770 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 771 772 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 773 774 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ 775 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) 776 pcix_set_mmrbc(ha->pdev, 2048); 777 778 /* PCIe -- adjust Maximum Read Request Size (2048). */ 779 if (pci_is_pcie(ha->pdev)) 780 pcie_set_readrq(ha->pdev, 4096); 781 782 pci_disable_rom(ha->pdev); 783 784 ha->chip_revision = ha->pdev->revision; 785 786 /* Get PCI bus information. */ 787 spin_lock_irqsave(&ha->hardware_lock, flags); 788 ha->pci_attr = RD_REG_DWORD(®->ctrl_status); 789 spin_unlock_irqrestore(&ha->hardware_lock, flags); 790 791 return QLA_SUCCESS; 792 } 793 794 /** 795 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. 796 * @ha: HA context 797 * 798 * Returns 0 on success. 799 */ 800 int 801 qla25xx_pci_config(scsi_qla_host_t *vha) 802 { 803 uint16_t w; 804 struct qla_hw_data *ha = vha->hw; 805 806 pci_set_master(ha->pdev); 807 pci_try_set_mwi(ha->pdev); 808 809 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 810 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 811 w &= ~PCI_COMMAND_INTX_DISABLE; 812 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 813 814 /* PCIe -- adjust Maximum Read Request Size (2048). */ 815 if (pci_is_pcie(ha->pdev)) 816 pcie_set_readrq(ha->pdev, 4096); 817 818 pci_disable_rom(ha->pdev); 819 820 ha->chip_revision = ha->pdev->revision; 821 822 return QLA_SUCCESS; 823 } 824 825 /** 826 * qla2x00_isp_firmware() - Choose firmware image. 827 * @ha: HA context 828 * 829 * Returns 0 on success. 830 */ 831 static int 832 qla2x00_isp_firmware(scsi_qla_host_t *vha) 833 { 834 int rval; 835 uint16_t loop_id, topo, sw_cap; 836 uint8_t domain, area, al_pa; 837 struct qla_hw_data *ha = vha->hw; 838 839 /* Assume loading risc code */ 840 rval = QLA_FUNCTION_FAILED; 841 842 if (ha->flags.disable_risc_code_load) { 843 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n"); 844 845 /* Verify checksum of loaded RISC code. */ 846 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address); 847 if (rval == QLA_SUCCESS) { 848 /* And, verify we are not in ROM code. */ 849 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa, 850 &area, &domain, &topo, &sw_cap); 851 } 852 } 853 854 if (rval) 855 ql_dbg(ql_dbg_init, vha, 0x007a, 856 "**** Load RISC code ****.\n"); 857 858 return (rval); 859 } 860 861 /** 862 * qla2x00_reset_chip() - Reset ISP chip. 863 * @ha: HA context 864 * 865 * Returns 0 on success. 866 */ 867 void 868 qla2x00_reset_chip(scsi_qla_host_t *vha) 869 { 870 unsigned long flags = 0; 871 struct qla_hw_data *ha = vha->hw; 872 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 873 uint32_t cnt; 874 uint16_t cmd; 875 876 if (unlikely(pci_channel_offline(ha->pdev))) 877 return; 878 879 ha->isp_ops->disable_intrs(ha); 880 881 spin_lock_irqsave(&ha->hardware_lock, flags); 882 883 /* Turn off master enable */ 884 cmd = 0; 885 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd); 886 cmd &= ~PCI_COMMAND_MASTER; 887 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 888 889 if (!IS_QLA2100(ha)) { 890 /* Pause RISC. */ 891 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 892 if (IS_QLA2200(ha) || IS_QLA2300(ha)) { 893 for (cnt = 0; cnt < 30000; cnt++) { 894 if ((RD_REG_WORD(®->hccr) & 895 HCCR_RISC_PAUSE) != 0) 896 break; 897 udelay(100); 898 } 899 } else { 900 RD_REG_WORD(®->hccr); /* PCI Posting. */ 901 udelay(10); 902 } 903 904 /* Select FPM registers. */ 905 WRT_REG_WORD(®->ctrl_status, 0x20); 906 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 907 908 /* FPM Soft Reset. */ 909 WRT_REG_WORD(®->fpm_diag_config, 0x100); 910 RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ 911 912 /* Toggle Fpm Reset. */ 913 if (!IS_QLA2200(ha)) { 914 WRT_REG_WORD(®->fpm_diag_config, 0x0); 915 RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ 916 } 917 918 /* Select frame buffer registers. */ 919 WRT_REG_WORD(®->ctrl_status, 0x10); 920 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 921 922 /* Reset frame buffer FIFOs. */ 923 if (IS_QLA2200(ha)) { 924 WRT_FB_CMD_REG(ha, reg, 0xa000); 925 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ 926 } else { 927 WRT_FB_CMD_REG(ha, reg, 0x00fc); 928 929 /* Read back fb_cmd until zero or 3 seconds max */ 930 for (cnt = 0; cnt < 3000; cnt++) { 931 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) 932 break; 933 udelay(100); 934 } 935 } 936 937 /* Select RISC module registers. */ 938 WRT_REG_WORD(®->ctrl_status, 0); 939 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 940 941 /* Reset RISC processor. */ 942 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 943 RD_REG_WORD(®->hccr); /* PCI Posting. */ 944 945 /* Release RISC processor. */ 946 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 947 RD_REG_WORD(®->hccr); /* PCI Posting. */ 948 } 949 950 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 951 WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT); 952 953 /* Reset ISP chip. */ 954 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 955 956 /* Wait for RISC to recover from reset. */ 957 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 958 /* 959 * It is necessary to for a delay here since the card doesn't 960 * respond to PCI reads during a reset. On some architectures 961 * this will result in an MCA. 962 */ 963 udelay(20); 964 for (cnt = 30000; cnt; cnt--) { 965 if ((RD_REG_WORD(®->ctrl_status) & 966 CSR_ISP_SOFT_RESET) == 0) 967 break; 968 udelay(100); 969 } 970 } else 971 udelay(10); 972 973 /* Reset RISC processor. */ 974 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 975 976 WRT_REG_WORD(®->semaphore, 0); 977 978 /* Release RISC processor. */ 979 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 980 RD_REG_WORD(®->hccr); /* PCI Posting. */ 981 982 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 983 for (cnt = 0; cnt < 30000; cnt++) { 984 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) 985 break; 986 987 udelay(100); 988 } 989 } else 990 udelay(100); 991 992 /* Turn on master enable */ 993 cmd |= PCI_COMMAND_MASTER; 994 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 995 996 /* Disable RISC pause on FPM parity error. */ 997 if (!IS_QLA2100(ha)) { 998 WRT_REG_WORD(®->hccr, HCCR_DISABLE_PARITY_PAUSE); 999 RD_REG_WORD(®->hccr); /* PCI Posting. */ 1000 } 1001 1002 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1003 } 1004 1005 /** 1006 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC. 1007 * 1008 * Returns 0 on success. 1009 */ 1010 static int 1011 qla81xx_reset_mpi(scsi_qla_host_t *vha) 1012 { 1013 uint16_t mb[4] = {0x1010, 0, 1, 0}; 1014 1015 if (!IS_QLA81XX(vha->hw)) 1016 return QLA_SUCCESS; 1017 1018 return qla81xx_write_mpi_register(vha, mb); 1019 } 1020 1021 /** 1022 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. 1023 * @ha: HA context 1024 * 1025 * Returns 0 on success. 1026 */ 1027 static inline void 1028 qla24xx_reset_risc(scsi_qla_host_t *vha) 1029 { 1030 unsigned long flags = 0; 1031 struct qla_hw_data *ha = vha->hw; 1032 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1033 uint32_t cnt, d2; 1034 uint16_t wd; 1035 static int abts_cnt; /* ISP abort retry counts */ 1036 1037 spin_lock_irqsave(&ha->hardware_lock, flags); 1038 1039 /* Reset RISC. */ 1040 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 1041 for (cnt = 0; cnt < 30000; cnt++) { 1042 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 1043 break; 1044 1045 udelay(10); 1046 } 1047 1048 WRT_REG_DWORD(®->ctrl_status, 1049 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 1050 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 1051 1052 udelay(100); 1053 /* Wait for firmware to complete NVRAM accesses. */ 1054 d2 = (uint32_t) RD_REG_WORD(®->mailbox0); 1055 for (cnt = 10000 ; cnt && d2; cnt--) { 1056 udelay(5); 1057 d2 = (uint32_t) RD_REG_WORD(®->mailbox0); 1058 barrier(); 1059 } 1060 1061 /* Wait for soft-reset to complete. */ 1062 d2 = RD_REG_DWORD(®->ctrl_status); 1063 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) { 1064 udelay(5); 1065 d2 = RD_REG_DWORD(®->ctrl_status); 1066 barrier(); 1067 } 1068 1069 /* If required, do an MPI FW reset now */ 1070 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) { 1071 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) { 1072 if (++abts_cnt < 5) { 1073 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 1074 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags); 1075 } else { 1076 /* 1077 * We exhausted the ISP abort retries. We have to 1078 * set the board offline. 1079 */ 1080 abts_cnt = 0; 1081 vha->flags.online = 0; 1082 } 1083 } 1084 } 1085 1086 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); 1087 RD_REG_DWORD(®->hccr); 1088 1089 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); 1090 RD_REG_DWORD(®->hccr); 1091 1092 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 1093 RD_REG_DWORD(®->hccr); 1094 1095 d2 = (uint32_t) RD_REG_WORD(®->mailbox0); 1096 for (cnt = 6000000 ; cnt && d2; cnt--) { 1097 udelay(5); 1098 d2 = (uint32_t) RD_REG_WORD(®->mailbox0); 1099 barrier(); 1100 } 1101 1102 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1103 1104 if (IS_NOPOLLING_TYPE(ha)) 1105 ha->isp_ops->enable_intrs(ha); 1106 } 1107 1108 static void 1109 qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) 1110 { 1111 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 1112 1113 WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 1114 *data = RD_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET); 1115 1116 } 1117 1118 static void 1119 qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) 1120 { 1121 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 1122 1123 WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 1124 WRT_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET, data); 1125 } 1126 1127 static void 1128 qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) 1129 { 1130 struct qla_hw_data *ha = vha->hw; 1131 uint32_t wd32 = 0; 1132 uint delta_msec = 100; 1133 uint elapsed_msec = 0; 1134 uint timeout_msec; 1135 ulong n; 1136 1137 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha)) 1138 return; 1139 1140 attempt: 1141 timeout_msec = TIMEOUT_SEMAPHORE; 1142 n = timeout_msec / delta_msec; 1143 while (n--) { 1144 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET); 1145 qla25xx_read_risc_sema_reg(vha, &wd32); 1146 if (wd32 & RISC_SEMAPHORE) 1147 break; 1148 msleep(delta_msec); 1149 elapsed_msec += delta_msec; 1150 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 1151 goto force; 1152 } 1153 1154 if (!(wd32 & RISC_SEMAPHORE)) 1155 goto force; 1156 1157 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 1158 goto acquired; 1159 1160 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR); 1161 timeout_msec = TIMEOUT_SEMAPHORE_FORCE; 1162 n = timeout_msec / delta_msec; 1163 while (n--) { 1164 qla25xx_read_risc_sema_reg(vha, &wd32); 1165 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 1166 break; 1167 msleep(delta_msec); 1168 elapsed_msec += delta_msec; 1169 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 1170 goto force; 1171 } 1172 1173 if (wd32 & RISC_SEMAPHORE_FORCE) 1174 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR); 1175 1176 goto attempt; 1177 1178 force: 1179 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET); 1180 1181 acquired: 1182 return; 1183 } 1184 1185 /** 1186 * qla24xx_reset_chip() - Reset ISP24xx chip. 1187 * @ha: HA context 1188 * 1189 * Returns 0 on success. 1190 */ 1191 void 1192 qla24xx_reset_chip(scsi_qla_host_t *vha) 1193 { 1194 struct qla_hw_data *ha = vha->hw; 1195 1196 if (pci_channel_offline(ha->pdev) && 1197 ha->flags.pci_channel_io_perm_failure) { 1198 return; 1199 } 1200 1201 ha->isp_ops->disable_intrs(ha); 1202 1203 qla25xx_manipulate_risc_semaphore(vha); 1204 1205 /* Perform RISC reset. */ 1206 qla24xx_reset_risc(vha); 1207 } 1208 1209 /** 1210 * qla2x00_chip_diag() - Test chip for proper operation. 1211 * @ha: HA context 1212 * 1213 * Returns 0 on success. 1214 */ 1215 int 1216 qla2x00_chip_diag(scsi_qla_host_t *vha) 1217 { 1218 int rval; 1219 struct qla_hw_data *ha = vha->hw; 1220 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1221 unsigned long flags = 0; 1222 uint16_t data; 1223 uint32_t cnt; 1224 uint16_t mb[5]; 1225 struct req_que *req = ha->req_q_map[0]; 1226 1227 /* Assume a failed state */ 1228 rval = QLA_FUNCTION_FAILED; 1229 1230 ql_dbg(ql_dbg_init, vha, 0x007b, 1231 "Testing device at %lx.\n", (u_long)®->flash_address); 1232 1233 spin_lock_irqsave(&ha->hardware_lock, flags); 1234 1235 /* Reset ISP chip. */ 1236 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 1237 1238 /* 1239 * We need to have a delay here since the card will not respond while 1240 * in reset causing an MCA on some architectures. 1241 */ 1242 udelay(20); 1243 data = qla2x00_debounce_register(®->ctrl_status); 1244 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) { 1245 udelay(5); 1246 data = RD_REG_WORD(®->ctrl_status); 1247 barrier(); 1248 } 1249 1250 if (!cnt) 1251 goto chip_diag_failed; 1252 1253 ql_dbg(ql_dbg_init, vha, 0x007c, 1254 "Reset register cleared by chip reset.\n"); 1255 1256 /* Reset RISC processor. */ 1257 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 1258 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 1259 1260 /* Workaround for QLA2312 PCI parity error */ 1261 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 1262 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); 1263 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) { 1264 udelay(5); 1265 data = RD_MAILBOX_REG(ha, reg, 0); 1266 barrier(); 1267 } 1268 } else 1269 udelay(10); 1270 1271 if (!cnt) 1272 goto chip_diag_failed; 1273 1274 /* Check product ID of chip */ 1275 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n"); 1276 1277 mb[1] = RD_MAILBOX_REG(ha, reg, 1); 1278 mb[2] = RD_MAILBOX_REG(ha, reg, 2); 1279 mb[3] = RD_MAILBOX_REG(ha, reg, 3); 1280 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); 1281 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) || 1282 mb[3] != PROD_ID_3) { 1283 ql_log(ql_log_warn, vha, 0x0062, 1284 "Wrong product ID = 0x%x,0x%x,0x%x.\n", 1285 mb[1], mb[2], mb[3]); 1286 1287 goto chip_diag_failed; 1288 } 1289 ha->product_id[0] = mb[1]; 1290 ha->product_id[1] = mb[2]; 1291 ha->product_id[2] = mb[3]; 1292 ha->product_id[3] = mb[4]; 1293 1294 /* Adjust fw RISC transfer size */ 1295 if (req->length > 1024) 1296 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; 1297 else 1298 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1299 req->length; 1300 1301 if (IS_QLA2200(ha) && 1302 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { 1303 /* Limit firmware transfer size with a 2200A */ 1304 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n"); 1305 1306 ha->device_type |= DT_ISP2200A; 1307 ha->fw_transfer_size = 128; 1308 } 1309 1310 /* Wrap Incoming Mailboxes Test. */ 1311 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1312 1313 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n"); 1314 rval = qla2x00_mbx_reg_test(vha); 1315 if (rval) 1316 ql_log(ql_log_warn, vha, 0x0080, 1317 "Failed mailbox send register test.\n"); 1318 else 1319 /* Flag a successful rval */ 1320 rval = QLA_SUCCESS; 1321 spin_lock_irqsave(&ha->hardware_lock, flags); 1322 1323 chip_diag_failed: 1324 if (rval) 1325 ql_log(ql_log_info, vha, 0x0081, 1326 "Chip diagnostics **** FAILED ****.\n"); 1327 1328 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1329 1330 return (rval); 1331 } 1332 1333 /** 1334 * qla24xx_chip_diag() - Test ISP24xx for proper operation. 1335 * @ha: HA context 1336 * 1337 * Returns 0 on success. 1338 */ 1339 int 1340 qla24xx_chip_diag(scsi_qla_host_t *vha) 1341 { 1342 int rval; 1343 struct qla_hw_data *ha = vha->hw; 1344 struct req_que *req = ha->req_q_map[0]; 1345 1346 if (IS_P3P_TYPE(ha)) 1347 return QLA_SUCCESS; 1348 1349 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; 1350 1351 rval = qla2x00_mbx_reg_test(vha); 1352 if (rval) { 1353 ql_log(ql_log_warn, vha, 0x0082, 1354 "Failed mailbox send register test.\n"); 1355 } else { 1356 /* Flag a successful rval */ 1357 rval = QLA_SUCCESS; 1358 } 1359 1360 return rval; 1361 } 1362 1363 void 1364 qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) 1365 { 1366 int rval; 1367 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, 1368 eft_size, fce_size, mq_size; 1369 dma_addr_t tc_dma; 1370 void *tc; 1371 struct qla_hw_data *ha = vha->hw; 1372 struct req_que *req = ha->req_q_map[0]; 1373 struct rsp_que *rsp = ha->rsp_q_map[0]; 1374 1375 if (ha->fw_dump) { 1376 ql_dbg(ql_dbg_init, vha, 0x00bd, 1377 "Firmware dump already allocated.\n"); 1378 return; 1379 } 1380 1381 ha->fw_dumped = 0; 1382 fixed_size = mem_size = eft_size = fce_size = mq_size = 0; 1383 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 1384 fixed_size = sizeof(struct qla2100_fw_dump); 1385 } else if (IS_QLA23XX(ha)) { 1386 fixed_size = offsetof(struct qla2300_fw_dump, data_ram); 1387 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 1388 sizeof(uint16_t); 1389 } else if (IS_FWI2_CAPABLE(ha)) { 1390 if (IS_QLA83XX(ha)) 1391 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem); 1392 else if (IS_QLA81XX(ha)) 1393 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); 1394 else if (IS_QLA25XX(ha)) 1395 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); 1396 else 1397 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); 1398 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 1399 sizeof(uint32_t); 1400 if (ha->mqenable) { 1401 if (!IS_QLA83XX(ha)) 1402 mq_size = sizeof(struct qla2xxx_mq_chain); 1403 /* 1404 * Allocate maximum buffer size for all queues. 1405 * Resizing must be done at end-of-dump processing. 1406 */ 1407 mq_size += ha->max_req_queues * 1408 (req->length * sizeof(request_t)); 1409 mq_size += ha->max_rsp_queues * 1410 (rsp->length * sizeof(response_t)); 1411 } 1412 if (ha->tgt.atio_ring) 1413 mq_size += ha->tgt.atio_q_length * sizeof(request_t); 1414 /* Allocate memory for Fibre Channel Event Buffer. */ 1415 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha)) 1416 goto try_eft; 1417 1418 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, 1419 GFP_KERNEL); 1420 if (!tc) { 1421 ql_log(ql_log_warn, vha, 0x00be, 1422 "Unable to allocate (%d KB) for FCE.\n", 1423 FCE_SIZE / 1024); 1424 goto try_eft; 1425 } 1426 1427 memset(tc, 0, FCE_SIZE); 1428 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS, 1429 ha->fce_mb, &ha->fce_bufs); 1430 if (rval) { 1431 ql_log(ql_log_warn, vha, 0x00bf, 1432 "Unable to initialize FCE (%d).\n", rval); 1433 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc, 1434 tc_dma); 1435 ha->flags.fce_enabled = 0; 1436 goto try_eft; 1437 } 1438 ql_dbg(ql_dbg_init, vha, 0x00c0, 1439 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024); 1440 1441 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE; 1442 ha->flags.fce_enabled = 1; 1443 ha->fce_dma = tc_dma; 1444 ha->fce = tc; 1445 try_eft: 1446 /* Allocate memory for Extended Trace Buffer. */ 1447 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma, 1448 GFP_KERNEL); 1449 if (!tc) { 1450 ql_log(ql_log_warn, vha, 0x00c1, 1451 "Unable to allocate (%d KB) for EFT.\n", 1452 EFT_SIZE / 1024); 1453 goto cont_alloc; 1454 } 1455 1456 memset(tc, 0, EFT_SIZE); 1457 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS); 1458 if (rval) { 1459 ql_log(ql_log_warn, vha, 0x00c2, 1460 "Unable to initialize EFT (%d).\n", rval); 1461 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc, 1462 tc_dma); 1463 goto cont_alloc; 1464 } 1465 ql_dbg(ql_dbg_init, vha, 0x00c3, 1466 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024); 1467 1468 eft_size = EFT_SIZE; 1469 ha->eft_dma = tc_dma; 1470 ha->eft = tc; 1471 } 1472 cont_alloc: 1473 req_q_size = req->length * sizeof(request_t); 1474 rsp_q_size = rsp->length * sizeof(response_t); 1475 1476 dump_size = offsetof(struct qla2xxx_fw_dump, isp); 1477 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size; 1478 ha->chain_offset = dump_size; 1479 dump_size += mq_size + fce_size; 1480 1481 ha->fw_dump = vmalloc(dump_size); 1482 if (!ha->fw_dump) { 1483 ql_log(ql_log_warn, vha, 0x00c4, 1484 "Unable to allocate (%d KB) for firmware dump.\n", 1485 dump_size / 1024); 1486 1487 if (ha->fce) { 1488 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, 1489 ha->fce_dma); 1490 ha->fce = NULL; 1491 ha->fce_dma = 0; 1492 } 1493 1494 if (ha->eft) { 1495 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft, 1496 ha->eft_dma); 1497 ha->eft = NULL; 1498 ha->eft_dma = 0; 1499 } 1500 return; 1501 } 1502 ql_dbg(ql_dbg_init, vha, 0x00c5, 1503 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024); 1504 1505 ha->fw_dump_len = dump_size; 1506 ha->fw_dump->signature[0] = 'Q'; 1507 ha->fw_dump->signature[1] = 'L'; 1508 ha->fw_dump->signature[2] = 'G'; 1509 ha->fw_dump->signature[3] = 'C'; 1510 ha->fw_dump->version = __constant_htonl(1); 1511 1512 ha->fw_dump->fixed_size = htonl(fixed_size); 1513 ha->fw_dump->mem_size = htonl(mem_size); 1514 ha->fw_dump->req_q_size = htonl(req_q_size); 1515 ha->fw_dump->rsp_q_size = htonl(rsp_q_size); 1516 1517 ha->fw_dump->eft_size = htonl(eft_size); 1518 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma)); 1519 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma)); 1520 1521 ha->fw_dump->header_size = 1522 htonl(offsetof(struct qla2xxx_fw_dump, isp)); 1523 } 1524 1525 static int 1526 qla81xx_mpi_sync(scsi_qla_host_t *vha) 1527 { 1528 #define MPS_MASK 0xe0 1529 int rval; 1530 uint16_t dc; 1531 uint32_t dw; 1532 1533 if (!IS_QLA81XX(vha->hw)) 1534 return QLA_SUCCESS; 1535 1536 rval = qla2x00_write_ram_word(vha, 0x7c00, 1); 1537 if (rval != QLA_SUCCESS) { 1538 ql_log(ql_log_warn, vha, 0x0105, 1539 "Unable to acquire semaphore.\n"); 1540 goto done; 1541 } 1542 1543 pci_read_config_word(vha->hw->pdev, 0x54, &dc); 1544 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw); 1545 if (rval != QLA_SUCCESS) { 1546 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n"); 1547 goto done_release; 1548 } 1549 1550 dc &= MPS_MASK; 1551 if (dc == (dw & MPS_MASK)) 1552 goto done_release; 1553 1554 dw &= ~MPS_MASK; 1555 dw |= dc; 1556 rval = qla2x00_write_ram_word(vha, 0x7a15, dw); 1557 if (rval != QLA_SUCCESS) { 1558 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n"); 1559 } 1560 1561 done_release: 1562 rval = qla2x00_write_ram_word(vha, 0x7c00, 0); 1563 if (rval != QLA_SUCCESS) { 1564 ql_log(ql_log_warn, vha, 0x006d, 1565 "Unable to release semaphore.\n"); 1566 } 1567 1568 done: 1569 return rval; 1570 } 1571 1572 int 1573 qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req) 1574 { 1575 /* Don't try to reallocate the array */ 1576 if (req->outstanding_cmds) 1577 return QLA_SUCCESS; 1578 1579 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase && 1580 (ql2xmultique_tag || ql2xmaxqueues > 1))) 1581 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS; 1582 else { 1583 if (ha->fw_xcb_count <= ha->fw_iocb_count) 1584 req->num_outstanding_cmds = ha->fw_xcb_count; 1585 else 1586 req->num_outstanding_cmds = ha->fw_iocb_count; 1587 } 1588 1589 req->outstanding_cmds = kzalloc(sizeof(srb_t *) * 1590 req->num_outstanding_cmds, GFP_KERNEL); 1591 1592 if (!req->outstanding_cmds) { 1593 /* 1594 * Try to allocate a minimal size just so we can get through 1595 * initialization. 1596 */ 1597 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS; 1598 req->outstanding_cmds = kzalloc(sizeof(srb_t *) * 1599 req->num_outstanding_cmds, GFP_KERNEL); 1600 1601 if (!req->outstanding_cmds) { 1602 ql_log(ql_log_fatal, NULL, 0x0126, 1603 "Failed to allocate memory for " 1604 "outstanding_cmds for req_que %p.\n", req); 1605 req->num_outstanding_cmds = 0; 1606 return QLA_FUNCTION_FAILED; 1607 } 1608 } 1609 1610 return QLA_SUCCESS; 1611 } 1612 1613 /** 1614 * qla2x00_setup_chip() - Load and start RISC firmware. 1615 * @ha: HA context 1616 * 1617 * Returns 0 on success. 1618 */ 1619 static int 1620 qla2x00_setup_chip(scsi_qla_host_t *vha) 1621 { 1622 int rval; 1623 uint32_t srisc_address = 0; 1624 struct qla_hw_data *ha = vha->hw; 1625 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1626 unsigned long flags; 1627 uint16_t fw_major_version; 1628 1629 if (IS_P3P_TYPE(ha)) { 1630 rval = ha->isp_ops->load_risc(vha, &srisc_address); 1631 if (rval == QLA_SUCCESS) { 1632 qla2x00_stop_firmware(vha); 1633 goto enable_82xx_npiv; 1634 } else 1635 goto failed; 1636 } 1637 1638 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 1639 /* Disable SRAM, Instruction RAM and GP RAM parity. */ 1640 spin_lock_irqsave(&ha->hardware_lock, flags); 1641 WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); 1642 RD_REG_WORD(®->hccr); 1643 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1644 } 1645 1646 qla81xx_mpi_sync(vha); 1647 1648 /* Load firmware sequences */ 1649 rval = ha->isp_ops->load_risc(vha, &srisc_address); 1650 if (rval == QLA_SUCCESS) { 1651 ql_dbg(ql_dbg_init, vha, 0x00c9, 1652 "Verifying Checksum of loaded RISC code.\n"); 1653 1654 rval = qla2x00_verify_checksum(vha, srisc_address); 1655 if (rval == QLA_SUCCESS) { 1656 /* Start firmware execution. */ 1657 ql_dbg(ql_dbg_init, vha, 0x00ca, 1658 "Starting firmware.\n"); 1659 1660 rval = qla2x00_execute_fw(vha, srisc_address); 1661 /* Retrieve firmware information. */ 1662 if (rval == QLA_SUCCESS) { 1663 enable_82xx_npiv: 1664 fw_major_version = ha->fw_major_version; 1665 if (IS_P3P_TYPE(ha)) 1666 qla82xx_check_md_needed(vha); 1667 else 1668 rval = qla2x00_get_fw_version(vha); 1669 if (rval != QLA_SUCCESS) 1670 goto failed; 1671 ha->flags.npiv_supported = 0; 1672 if (IS_QLA2XXX_MIDTYPE(ha) && 1673 (ha->fw_attributes & BIT_2)) { 1674 ha->flags.npiv_supported = 1; 1675 if ((!ha->max_npiv_vports) || 1676 ((ha->max_npiv_vports + 1) % 1677 MIN_MULTI_ID_FABRIC)) 1678 ha->max_npiv_vports = 1679 MIN_MULTI_ID_FABRIC - 1; 1680 } 1681 qla2x00_get_resource_cnts(vha, NULL, 1682 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count, 1683 &ha->max_npiv_vports, NULL); 1684 1685 /* 1686 * Allocate the array of outstanding commands 1687 * now that we know the firmware resources. 1688 */ 1689 rval = qla2x00_alloc_outstanding_cmds(ha, 1690 vha->req); 1691 if (rval != QLA_SUCCESS) 1692 goto failed; 1693 1694 if (!fw_major_version && ql2xallocfwdump 1695 && !(IS_P3P_TYPE(ha))) 1696 qla2x00_alloc_fw_dump(vha); 1697 } 1698 } else { 1699 ql_log(ql_log_fatal, vha, 0x00cd, 1700 "ISP Firmware failed checksum.\n"); 1701 goto failed; 1702 } 1703 } else 1704 goto failed; 1705 1706 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 1707 /* Enable proper parity. */ 1708 spin_lock_irqsave(&ha->hardware_lock, flags); 1709 if (IS_QLA2300(ha)) 1710 /* SRAM parity */ 1711 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1); 1712 else 1713 /* SRAM, Instruction RAM and GP RAM parity */ 1714 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7); 1715 RD_REG_WORD(®->hccr); 1716 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1717 } 1718 1719 if (IS_QLA83XX(ha)) 1720 goto skip_fac_check; 1721 1722 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { 1723 uint32_t size; 1724 1725 rval = qla81xx_fac_get_sector_size(vha, &size); 1726 if (rval == QLA_SUCCESS) { 1727 ha->flags.fac_supported = 1; 1728 ha->fdt_block_size = size << 2; 1729 } else { 1730 ql_log(ql_log_warn, vha, 0x00ce, 1731 "Unsupported FAC firmware (%d.%02d.%02d).\n", 1732 ha->fw_major_version, ha->fw_minor_version, 1733 ha->fw_subminor_version); 1734 skip_fac_check: 1735 if (IS_QLA83XX(ha)) { 1736 ha->flags.fac_supported = 0; 1737 rval = QLA_SUCCESS; 1738 } 1739 } 1740 } 1741 failed: 1742 if (rval) { 1743 ql_log(ql_log_fatal, vha, 0x00cf, 1744 "Setup chip ****FAILED****.\n"); 1745 } 1746 1747 return (rval); 1748 } 1749 1750 /** 1751 * qla2x00_init_response_q_entries() - Initializes response queue entries. 1752 * @ha: HA context 1753 * 1754 * Beginning of request ring has initialization control block already built 1755 * by nvram config routine. 1756 * 1757 * Returns 0 on success. 1758 */ 1759 void 1760 qla2x00_init_response_q_entries(struct rsp_que *rsp) 1761 { 1762 uint16_t cnt; 1763 response_t *pkt; 1764 1765 rsp->ring_ptr = rsp->ring; 1766 rsp->ring_index = 0; 1767 rsp->status_srb = NULL; 1768 pkt = rsp->ring_ptr; 1769 for (cnt = 0; cnt < rsp->length; cnt++) { 1770 pkt->signature = RESPONSE_PROCESSED; 1771 pkt++; 1772 } 1773 } 1774 1775 /** 1776 * qla2x00_update_fw_options() - Read and process firmware options. 1777 * @ha: HA context 1778 * 1779 * Returns 0 on success. 1780 */ 1781 void 1782 qla2x00_update_fw_options(scsi_qla_host_t *vha) 1783 { 1784 uint16_t swing, emphasis, tx_sens, rx_sens; 1785 struct qla_hw_data *ha = vha->hw; 1786 1787 memset(ha->fw_options, 0, sizeof(ha->fw_options)); 1788 qla2x00_get_fw_options(vha, ha->fw_options); 1789 1790 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 1791 return; 1792 1793 /* Serial Link options. */ 1794 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115, 1795 "Serial link options.\n"); 1796 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109, 1797 (uint8_t *)&ha->fw_seriallink_options, 1798 sizeof(ha->fw_seriallink_options)); 1799 1800 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1801 if (ha->fw_seriallink_options[3] & BIT_2) { 1802 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING; 1803 1804 /* 1G settings */ 1805 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); 1806 emphasis = (ha->fw_seriallink_options[2] & 1807 (BIT_4 | BIT_3)) >> 3; 1808 tx_sens = ha->fw_seriallink_options[0] & 1809 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 1810 rx_sens = (ha->fw_seriallink_options[0] & 1811 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 1812 ha->fw_options[10] = (emphasis << 14) | (swing << 8); 1813 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 1814 if (rx_sens == 0x0) 1815 rx_sens = 0x3; 1816 ha->fw_options[10] |= (tx_sens << 4) | rx_sens; 1817 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 1818 ha->fw_options[10] |= BIT_5 | 1819 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 1820 (tx_sens & (BIT_1 | BIT_0)); 1821 1822 /* 2G settings */ 1823 swing = (ha->fw_seriallink_options[2] & 1824 (BIT_7 | BIT_6 | BIT_5)) >> 5; 1825 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); 1826 tx_sens = ha->fw_seriallink_options[1] & 1827 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 1828 rx_sens = (ha->fw_seriallink_options[1] & 1829 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 1830 ha->fw_options[11] = (emphasis << 14) | (swing << 8); 1831 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 1832 if (rx_sens == 0x0) 1833 rx_sens = 0x3; 1834 ha->fw_options[11] |= (tx_sens << 4) | rx_sens; 1835 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 1836 ha->fw_options[11] |= BIT_5 | 1837 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 1838 (tx_sens & (BIT_1 | BIT_0)); 1839 } 1840 1841 /* FCP2 options. */ 1842 /* Return command IOCBs without waiting for an ABTS to complete. */ 1843 ha->fw_options[3] |= BIT_13; 1844 1845 /* LED scheme. */ 1846 if (ha->flags.enable_led_scheme) 1847 ha->fw_options[2] |= BIT_12; 1848 1849 /* Detect ISP6312. */ 1850 if (IS_QLA6312(ha)) 1851 ha->fw_options[2] |= BIT_13; 1852 1853 /* Update firmware options. */ 1854 qla2x00_set_fw_options(vha, ha->fw_options); 1855 } 1856 1857 void 1858 qla24xx_update_fw_options(scsi_qla_host_t *vha) 1859 { 1860 int rval; 1861 struct qla_hw_data *ha = vha->hw; 1862 1863 if (IS_P3P_TYPE(ha)) 1864 return; 1865 1866 /* Update Serial Link options. */ 1867 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) 1868 return; 1869 1870 rval = qla2x00_set_serdes_params(vha, 1871 le16_to_cpu(ha->fw_seriallink_options24[1]), 1872 le16_to_cpu(ha->fw_seriallink_options24[2]), 1873 le16_to_cpu(ha->fw_seriallink_options24[3])); 1874 if (rval != QLA_SUCCESS) { 1875 ql_log(ql_log_warn, vha, 0x0104, 1876 "Unable to update Serial Link options (%x).\n", rval); 1877 } 1878 } 1879 1880 void 1881 qla2x00_config_rings(struct scsi_qla_host *vha) 1882 { 1883 struct qla_hw_data *ha = vha->hw; 1884 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1885 struct req_que *req = ha->req_q_map[0]; 1886 struct rsp_que *rsp = ha->rsp_q_map[0]; 1887 1888 /* Setup ring parameters in initialization control block. */ 1889 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0); 1890 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0); 1891 ha->init_cb->request_q_length = cpu_to_le16(req->length); 1892 ha->init_cb->response_q_length = cpu_to_le16(rsp->length); 1893 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1894 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1895 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1896 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1897 1898 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0); 1899 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0); 1900 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0); 1901 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0); 1902 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ 1903 } 1904 1905 void 1906 qla24xx_config_rings(struct scsi_qla_host *vha) 1907 { 1908 struct qla_hw_data *ha = vha->hw; 1909 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0); 1910 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; 1911 struct qla_msix_entry *msix; 1912 struct init_cb_24xx *icb; 1913 uint16_t rid = 0; 1914 struct req_que *req = ha->req_q_map[0]; 1915 struct rsp_que *rsp = ha->rsp_q_map[0]; 1916 1917 /* Setup ring parameters in initialization control block. */ 1918 icb = (struct init_cb_24xx *)ha->init_cb; 1919 icb->request_q_outpointer = __constant_cpu_to_le16(0); 1920 icb->response_q_inpointer = __constant_cpu_to_le16(0); 1921 icb->request_q_length = cpu_to_le16(req->length); 1922 icb->response_q_length = cpu_to_le16(rsp->length); 1923 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 1924 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 1925 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1926 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1927 1928 /* Setup ATIO queue dma pointers for target mode */ 1929 icb->atio_q_inpointer = __constant_cpu_to_le16(0); 1930 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length); 1931 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma)); 1932 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma)); 1933 1934 if (ha->mqenable || IS_QLA83XX(ha)) { 1935 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS); 1936 icb->rid = __constant_cpu_to_le16(rid); 1937 if (ha->flags.msix_enabled) { 1938 msix = &ha->msix_entries[1]; 1939 ql_dbg(ql_dbg_init, vha, 0x00fd, 1940 "Registering vector 0x%x for base que.\n", 1941 msix->entry); 1942 icb->msix = cpu_to_le16(msix->entry); 1943 } 1944 /* Use alternate PCI bus number */ 1945 if (MSB(rid)) 1946 icb->firmware_options_2 |= 1947 __constant_cpu_to_le32(BIT_19); 1948 /* Use alternate PCI devfn */ 1949 if (LSB(rid)) 1950 icb->firmware_options_2 |= 1951 __constant_cpu_to_le32(BIT_18); 1952 1953 /* Use Disable MSIX Handshake mode for capable adapters */ 1954 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) && 1955 (ha->flags.msix_enabled)) { 1956 icb->firmware_options_2 &= 1957 __constant_cpu_to_le32(~BIT_22); 1958 ha->flags.disable_msix_handshake = 1; 1959 ql_dbg(ql_dbg_init, vha, 0x00fe, 1960 "MSIX Handshake Disable Mode turned on.\n"); 1961 } else { 1962 icb->firmware_options_2 |= 1963 __constant_cpu_to_le32(BIT_22); 1964 } 1965 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23); 1966 1967 WRT_REG_DWORD(®->isp25mq.req_q_in, 0); 1968 WRT_REG_DWORD(®->isp25mq.req_q_out, 0); 1969 WRT_REG_DWORD(®->isp25mq.rsp_q_in, 0); 1970 WRT_REG_DWORD(®->isp25mq.rsp_q_out, 0); 1971 } else { 1972 WRT_REG_DWORD(®->isp24.req_q_in, 0); 1973 WRT_REG_DWORD(®->isp24.req_q_out, 0); 1974 WRT_REG_DWORD(®->isp24.rsp_q_in, 0); 1975 WRT_REG_DWORD(®->isp24.rsp_q_out, 0); 1976 } 1977 qlt_24xx_config_rings(vha); 1978 1979 /* PCI posting */ 1980 RD_REG_DWORD(&ioreg->hccr); 1981 } 1982 1983 /** 1984 * qla2x00_init_rings() - Initializes firmware. 1985 * @ha: HA context 1986 * 1987 * Beginning of request ring has initialization control block already built 1988 * by nvram config routine. 1989 * 1990 * Returns 0 on success. 1991 */ 1992 int 1993 qla2x00_init_rings(scsi_qla_host_t *vha) 1994 { 1995 int rval; 1996 unsigned long flags = 0; 1997 int cnt, que; 1998 struct qla_hw_data *ha = vha->hw; 1999 struct req_que *req; 2000 struct rsp_que *rsp; 2001 struct mid_init_cb_24xx *mid_init_cb = 2002 (struct mid_init_cb_24xx *) ha->init_cb; 2003 2004 spin_lock_irqsave(&ha->hardware_lock, flags); 2005 2006 /* Clear outstanding commands array. */ 2007 for (que = 0; que < ha->max_req_queues; que++) { 2008 req = ha->req_q_map[que]; 2009 if (!req) 2010 continue; 2011 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) 2012 req->outstanding_cmds[cnt] = NULL; 2013 2014 req->current_outstanding_cmd = 1; 2015 2016 /* Initialize firmware. */ 2017 req->ring_ptr = req->ring; 2018 req->ring_index = 0; 2019 req->cnt = req->length; 2020 } 2021 2022 for (que = 0; que < ha->max_rsp_queues; que++) { 2023 rsp = ha->rsp_q_map[que]; 2024 if (!rsp) 2025 continue; 2026 /* Initialize response queue entries */ 2027 if (IS_QLAFX00(ha)) 2028 qlafx00_init_response_q_entries(rsp); 2029 else 2030 qla2x00_init_response_q_entries(rsp); 2031 } 2032 2033 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring; 2034 ha->tgt.atio_ring_index = 0; 2035 /* Initialize ATIO queue entries */ 2036 qlt_init_atio_q_entries(vha); 2037 2038 ha->isp_ops->config_rings(vha); 2039 2040 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2041 2042 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n"); 2043 2044 if (IS_QLAFX00(ha)) { 2045 rval = qlafx00_init_firmware(vha, ha->init_cb_size); 2046 goto next_check; 2047 } 2048 2049 /* Update any ISP specific firmware options before initialization. */ 2050 ha->isp_ops->update_fw_options(vha); 2051 2052 if (ha->flags.npiv_supported) { 2053 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha)) 2054 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; 2055 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); 2056 } 2057 2058 if (IS_FWI2_CAPABLE(ha)) { 2059 mid_init_cb->options = __constant_cpu_to_le16(BIT_1); 2060 mid_init_cb->init_cb.execution_throttle = 2061 cpu_to_le16(ha->fw_xcb_count); 2062 } 2063 2064 rval = qla2x00_init_firmware(vha, ha->init_cb_size); 2065 next_check: 2066 if (rval) { 2067 ql_log(ql_log_fatal, vha, 0x00d2, 2068 "Init Firmware **** FAILED ****.\n"); 2069 } else { 2070 ql_dbg(ql_dbg_init, vha, 0x00d3, 2071 "Init Firmware -- success.\n"); 2072 } 2073 2074 return (rval); 2075 } 2076 2077 /** 2078 * qla2x00_fw_ready() - Waits for firmware ready. 2079 * @ha: HA context 2080 * 2081 * Returns 0 on success. 2082 */ 2083 static int 2084 qla2x00_fw_ready(scsi_qla_host_t *vha) 2085 { 2086 int rval; 2087 unsigned long wtime, mtime, cs84xx_time; 2088 uint16_t min_wait; /* Minimum wait time if loop is down */ 2089 uint16_t wait_time; /* Wait time if loop is coming ready */ 2090 uint16_t state[5]; 2091 struct qla_hw_data *ha = vha->hw; 2092 2093 if (IS_QLAFX00(vha->hw)) 2094 return qlafx00_fw_ready(vha); 2095 2096 rval = QLA_SUCCESS; 2097 2098 /* 20 seconds for loop down. */ 2099 min_wait = 20; 2100 2101 /* 2102 * Firmware should take at most one RATOV to login, plus 5 seconds for 2103 * our own processing. 2104 */ 2105 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) { 2106 wait_time = min_wait; 2107 } 2108 2109 /* Min wait time if loop down */ 2110 mtime = jiffies + (min_wait * HZ); 2111 2112 /* wait time before firmware ready */ 2113 wtime = jiffies + (wait_time * HZ); 2114 2115 /* Wait for ISP to finish LIP */ 2116 if (!vha->flags.init_done) 2117 ql_log(ql_log_info, vha, 0x801e, 2118 "Waiting for LIP to complete.\n"); 2119 2120 do { 2121 memset(state, -1, sizeof(state)); 2122 rval = qla2x00_get_firmware_state(vha, state); 2123 if (rval == QLA_SUCCESS) { 2124 if (state[0] < FSTATE_LOSS_OF_SYNC) { 2125 vha->device_flags &= ~DFLG_NO_CABLE; 2126 } 2127 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) { 2128 ql_dbg(ql_dbg_taskm, vha, 0x801f, 2129 "fw_state=%x 84xx=%x.\n", state[0], 2130 state[2]); 2131 if ((state[2] & FSTATE_LOGGED_IN) && 2132 (state[2] & FSTATE_WAITING_FOR_VERIFY)) { 2133 ql_dbg(ql_dbg_taskm, vha, 0x8028, 2134 "Sending verify iocb.\n"); 2135 2136 cs84xx_time = jiffies; 2137 rval = qla84xx_init_chip(vha); 2138 if (rval != QLA_SUCCESS) { 2139 ql_log(ql_log_warn, 2140 vha, 0x8007, 2141 "Init chip failed.\n"); 2142 break; 2143 } 2144 2145 /* Add time taken to initialize. */ 2146 cs84xx_time = jiffies - cs84xx_time; 2147 wtime += cs84xx_time; 2148 mtime += cs84xx_time; 2149 ql_dbg(ql_dbg_taskm, vha, 0x8008, 2150 "Increasing wait time by %ld. " 2151 "New time %ld.\n", cs84xx_time, 2152 wtime); 2153 } 2154 } else if (state[0] == FSTATE_READY) { 2155 ql_dbg(ql_dbg_taskm, vha, 0x8037, 2156 "F/W Ready - OK.\n"); 2157 2158 qla2x00_get_retry_cnt(vha, &ha->retry_count, 2159 &ha->login_timeout, &ha->r_a_tov); 2160 2161 rval = QLA_SUCCESS; 2162 break; 2163 } 2164 2165 rval = QLA_FUNCTION_FAILED; 2166 2167 if (atomic_read(&vha->loop_down_timer) && 2168 state[0] != FSTATE_READY) { 2169 /* Loop down. Timeout on min_wait for states 2170 * other than Wait for Login. 2171 */ 2172 if (time_after_eq(jiffies, mtime)) { 2173 ql_log(ql_log_info, vha, 0x8038, 2174 "Cable is unplugged...\n"); 2175 2176 vha->device_flags |= DFLG_NO_CABLE; 2177 break; 2178 } 2179 } 2180 } else { 2181 /* Mailbox cmd failed. Timeout on min_wait. */ 2182 if (time_after_eq(jiffies, mtime) || 2183 ha->flags.isp82xx_fw_hung) 2184 break; 2185 } 2186 2187 if (time_after_eq(jiffies, wtime)) 2188 break; 2189 2190 /* Delay for a while */ 2191 msleep(500); 2192 } while (1); 2193 2194 ql_dbg(ql_dbg_taskm, vha, 0x803a, 2195 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0], 2196 state[1], state[2], state[3], state[4], jiffies); 2197 2198 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) { 2199 ql_log(ql_log_warn, vha, 0x803b, 2200 "Firmware ready **** FAILED ****.\n"); 2201 } 2202 2203 return (rval); 2204 } 2205 2206 /* 2207 * qla2x00_configure_hba 2208 * Setup adapter context. 2209 * 2210 * Input: 2211 * ha = adapter state pointer. 2212 * 2213 * Returns: 2214 * 0 = success 2215 * 2216 * Context: 2217 * Kernel context. 2218 */ 2219 static int 2220 qla2x00_configure_hba(scsi_qla_host_t *vha) 2221 { 2222 int rval; 2223 uint16_t loop_id; 2224 uint16_t topo; 2225 uint16_t sw_cap; 2226 uint8_t al_pa; 2227 uint8_t area; 2228 uint8_t domain; 2229 char connect_type[22]; 2230 struct qla_hw_data *ha = vha->hw; 2231 unsigned long flags; 2232 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 2233 2234 /* Get host addresses. */ 2235 rval = qla2x00_get_adapter_id(vha, 2236 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); 2237 if (rval != QLA_SUCCESS) { 2238 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || 2239 IS_CNA_CAPABLE(ha) || 2240 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { 2241 ql_dbg(ql_dbg_disc, vha, 0x2008, 2242 "Loop is in a transition state.\n"); 2243 } else { 2244 ql_log(ql_log_warn, vha, 0x2009, 2245 "Unable to get host loop ID.\n"); 2246 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) && 2247 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) { 2248 ql_log(ql_log_warn, vha, 0x1151, 2249 "Doing link init.\n"); 2250 if (qla24xx_link_initialize(vha) == QLA_SUCCESS) 2251 return rval; 2252 } 2253 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2254 } 2255 return (rval); 2256 } 2257 2258 if (topo == 4) { 2259 ql_log(ql_log_info, vha, 0x200a, 2260 "Cannot get topology - retrying.\n"); 2261 return (QLA_FUNCTION_FAILED); 2262 } 2263 2264 vha->loop_id = loop_id; 2265 2266 /* initialize */ 2267 ha->min_external_loopid = SNS_FIRST_LOOP_ID; 2268 ha->operating_mode = LOOP; 2269 ha->switch_cap = 0; 2270 2271 switch (topo) { 2272 case 0: 2273 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n"); 2274 ha->current_topology = ISP_CFG_NL; 2275 strcpy(connect_type, "(Loop)"); 2276 break; 2277 2278 case 1: 2279 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n"); 2280 ha->switch_cap = sw_cap; 2281 ha->current_topology = ISP_CFG_FL; 2282 strcpy(connect_type, "(FL_Port)"); 2283 break; 2284 2285 case 2: 2286 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n"); 2287 ha->operating_mode = P2P; 2288 ha->current_topology = ISP_CFG_N; 2289 strcpy(connect_type, "(N_Port-to-N_Port)"); 2290 break; 2291 2292 case 3: 2293 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n"); 2294 ha->switch_cap = sw_cap; 2295 ha->operating_mode = P2P; 2296 ha->current_topology = ISP_CFG_F; 2297 strcpy(connect_type, "(F_Port)"); 2298 break; 2299 2300 default: 2301 ql_dbg(ql_dbg_disc, vha, 0x200f, 2302 "HBA in unknown topology %x, using NL.\n", topo); 2303 ha->current_topology = ISP_CFG_NL; 2304 strcpy(connect_type, "(Loop)"); 2305 break; 2306 } 2307 2308 /* Save Host port and loop ID. */ 2309 /* byte order - Big Endian */ 2310 vha->d_id.b.domain = domain; 2311 vha->d_id.b.area = area; 2312 vha->d_id.b.al_pa = al_pa; 2313 2314 spin_lock_irqsave(&ha->vport_slock, flags); 2315 qlt_update_vp_map(vha, SET_AL_PA); 2316 spin_unlock_irqrestore(&ha->vport_slock, flags); 2317 2318 if (!vha->flags.init_done) 2319 ql_log(ql_log_info, vha, 0x2010, 2320 "Topology - %s, Host Loop address 0x%x.\n", 2321 connect_type, vha->loop_id); 2322 2323 return(rval); 2324 } 2325 2326 inline void 2327 qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, 2328 char *def) 2329 { 2330 char *st, *en; 2331 uint16_t index; 2332 struct qla_hw_data *ha = vha->hw; 2333 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 2334 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha); 2335 2336 if (memcmp(model, BINZERO, len) != 0) { 2337 strncpy(ha->model_number, model, len); 2338 st = en = ha->model_number; 2339 en += len - 1; 2340 while (en > st) { 2341 if (*en != 0x20 && *en != 0x00) 2342 break; 2343 *en-- = '\0'; 2344 } 2345 2346 index = (ha->pdev->subsystem_device & 0xff); 2347 if (use_tbl && 2348 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 2349 index < QLA_MODEL_NAMES) 2350 strncpy(ha->model_desc, 2351 qla2x00_model_name[index * 2 + 1], 2352 sizeof(ha->model_desc) - 1); 2353 } else { 2354 index = (ha->pdev->subsystem_device & 0xff); 2355 if (use_tbl && 2356 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 2357 index < QLA_MODEL_NAMES) { 2358 strcpy(ha->model_number, 2359 qla2x00_model_name[index * 2]); 2360 strncpy(ha->model_desc, 2361 qla2x00_model_name[index * 2 + 1], 2362 sizeof(ha->model_desc) - 1); 2363 } else { 2364 strcpy(ha->model_number, def); 2365 } 2366 } 2367 if (IS_FWI2_CAPABLE(ha)) 2368 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc, 2369 sizeof(ha->model_desc)); 2370 } 2371 2372 /* On sparc systems, obtain port and node WWN from firmware 2373 * properties. 2374 */ 2375 static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv) 2376 { 2377 #ifdef CONFIG_SPARC 2378 struct qla_hw_data *ha = vha->hw; 2379 struct pci_dev *pdev = ha->pdev; 2380 struct device_node *dp = pci_device_to_OF_node(pdev); 2381 const u8 *val; 2382 int len; 2383 2384 val = of_get_property(dp, "port-wwn", &len); 2385 if (val && len >= WWN_SIZE) 2386 memcpy(nv->port_name, val, WWN_SIZE); 2387 2388 val = of_get_property(dp, "node-wwn", &len); 2389 if (val && len >= WWN_SIZE) 2390 memcpy(nv->node_name, val, WWN_SIZE); 2391 #endif 2392 } 2393 2394 /* 2395 * NVRAM configuration for ISP 2xxx 2396 * 2397 * Input: 2398 * ha = adapter block pointer. 2399 * 2400 * Output: 2401 * initialization control block in response_ring 2402 * host adapters parameters in host adapter block 2403 * 2404 * Returns: 2405 * 0 = success. 2406 */ 2407 int 2408 qla2x00_nvram_config(scsi_qla_host_t *vha) 2409 { 2410 int rval; 2411 uint8_t chksum = 0; 2412 uint16_t cnt; 2413 uint8_t *dptr1, *dptr2; 2414 struct qla_hw_data *ha = vha->hw; 2415 init_cb_t *icb = ha->init_cb; 2416 nvram_t *nv = ha->nvram; 2417 uint8_t *ptr = ha->nvram; 2418 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2419 2420 rval = QLA_SUCCESS; 2421 2422 /* Determine NVRAM starting address. */ 2423 ha->nvram_size = sizeof(nvram_t); 2424 ha->nvram_base = 0; 2425 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) 2426 if ((RD_REG_WORD(®->ctrl_status) >> 14) == 1) 2427 ha->nvram_base = 0x80; 2428 2429 /* Get NVRAM data and calculate checksum. */ 2430 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size); 2431 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) 2432 chksum += *ptr++; 2433 2434 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f, 2435 "Contents of NVRAM.\n"); 2436 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110, 2437 (uint8_t *)nv, ha->nvram_size); 2438 2439 /* Bad NVRAM data, set defaults parameters. */ 2440 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || 2441 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) { 2442 /* Reset NVRAM data. */ 2443 ql_log(ql_log_warn, vha, 0x0064, 2444 "Inconsistent NVRAM " 2445 "detected: checksum=0x%x id=%c version=0x%x.\n", 2446 chksum, nv->id[0], nv->nvram_version); 2447 ql_log(ql_log_warn, vha, 0x0065, 2448 "Falling back to " 2449 "functioning (yet invalid -- WWPN) defaults.\n"); 2450 2451 /* 2452 * Set default initialization control block. 2453 */ 2454 memset(nv, 0, ha->nvram_size); 2455 nv->parameter_block_version = ICB_VERSION; 2456 2457 if (IS_QLA23XX(ha)) { 2458 nv->firmware_options[0] = BIT_2 | BIT_1; 2459 nv->firmware_options[1] = BIT_7 | BIT_5; 2460 nv->add_firmware_options[0] = BIT_5; 2461 nv->add_firmware_options[1] = BIT_5 | BIT_4; 2462 nv->frame_payload_size = __constant_cpu_to_le16(2048); 2463 nv->special_options[1] = BIT_7; 2464 } else if (IS_QLA2200(ha)) { 2465 nv->firmware_options[0] = BIT_2 | BIT_1; 2466 nv->firmware_options[1] = BIT_7 | BIT_5; 2467 nv->add_firmware_options[0] = BIT_5; 2468 nv->add_firmware_options[1] = BIT_5 | BIT_4; 2469 nv->frame_payload_size = __constant_cpu_to_le16(1024); 2470 } else if (IS_QLA2100(ha)) { 2471 nv->firmware_options[0] = BIT_3 | BIT_1; 2472 nv->firmware_options[1] = BIT_5; 2473 nv->frame_payload_size = __constant_cpu_to_le16(1024); 2474 } 2475 2476 nv->max_iocb_allocation = __constant_cpu_to_le16(256); 2477 nv->execution_throttle = __constant_cpu_to_le16(16); 2478 nv->retry_count = 8; 2479 nv->retry_delay = 1; 2480 2481 nv->port_name[0] = 33; 2482 nv->port_name[3] = 224; 2483 nv->port_name[4] = 139; 2484 2485 qla2xxx_nvram_wwn_from_ofw(vha, nv); 2486 2487 nv->login_timeout = 4; 2488 2489 /* 2490 * Set default host adapter parameters 2491 */ 2492 nv->host_p[1] = BIT_2; 2493 nv->reset_delay = 5; 2494 nv->port_down_retry_count = 8; 2495 nv->max_luns_per_target = __constant_cpu_to_le16(8); 2496 nv->link_down_timeout = 60; 2497 2498 rval = 1; 2499 } 2500 2501 #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) 2502 /* 2503 * The SN2 does not provide BIOS emulation which means you can't change 2504 * potentially bogus BIOS settings. Force the use of default settings 2505 * for link rate and frame size. Hope that the rest of the settings 2506 * are valid. 2507 */ 2508 if (ia64_platform_is("sn2")) { 2509 nv->frame_payload_size = __constant_cpu_to_le16(2048); 2510 if (IS_QLA23XX(ha)) 2511 nv->special_options[1] = BIT_7; 2512 } 2513 #endif 2514 2515 /* Reset Initialization control block */ 2516 memset(icb, 0, ha->init_cb_size); 2517 2518 /* 2519 * Setup driver NVRAM options. 2520 */ 2521 nv->firmware_options[0] |= (BIT_6 | BIT_1); 2522 nv->firmware_options[0] &= ~(BIT_5 | BIT_4); 2523 nv->firmware_options[1] |= (BIT_5 | BIT_0); 2524 nv->firmware_options[1] &= ~BIT_4; 2525 2526 if (IS_QLA23XX(ha)) { 2527 nv->firmware_options[0] |= BIT_2; 2528 nv->firmware_options[0] &= ~BIT_3; 2529 nv->special_options[0] &= ~BIT_6; 2530 nv->add_firmware_options[1] |= BIT_5 | BIT_4; 2531 2532 if (IS_QLA2300(ha)) { 2533 if (ha->fb_rev == FPM_2310) { 2534 strcpy(ha->model_number, "QLA2310"); 2535 } else { 2536 strcpy(ha->model_number, "QLA2300"); 2537 } 2538 } else { 2539 qla2x00_set_model_info(vha, nv->model_number, 2540 sizeof(nv->model_number), "QLA23xx"); 2541 } 2542 } else if (IS_QLA2200(ha)) { 2543 nv->firmware_options[0] |= BIT_2; 2544 /* 2545 * 'Point-to-point preferred, else loop' is not a safe 2546 * connection mode setting. 2547 */ 2548 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == 2549 (BIT_5 | BIT_4)) { 2550 /* Force 'loop preferred, else point-to-point'. */ 2551 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); 2552 nv->add_firmware_options[0] |= BIT_5; 2553 } 2554 strcpy(ha->model_number, "QLA22xx"); 2555 } else /*if (IS_QLA2100(ha))*/ { 2556 strcpy(ha->model_number, "QLA2100"); 2557 } 2558 2559 /* 2560 * Copy over NVRAM RISC parameter block to initialization control block. 2561 */ 2562 dptr1 = (uint8_t *)icb; 2563 dptr2 = (uint8_t *)&nv->parameter_block_version; 2564 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version; 2565 while (cnt--) 2566 *dptr1++ = *dptr2++; 2567 2568 /* Copy 2nd half. */ 2569 dptr1 = (uint8_t *)icb->add_firmware_options; 2570 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options; 2571 while (cnt--) 2572 *dptr1++ = *dptr2++; 2573 2574 /* Use alternate WWN? */ 2575 if (nv->host_p[1] & BIT_7) { 2576 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 2577 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 2578 } 2579 2580 /* Prepare nodename */ 2581 if ((icb->firmware_options[1] & BIT_6) == 0) { 2582 /* 2583 * Firmware will apply the following mask if the nodename was 2584 * not provided. 2585 */ 2586 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 2587 icb->node_name[0] &= 0xF0; 2588 } 2589 2590 /* 2591 * Set host adapter parameters. 2592 */ 2593 2594 /* 2595 * BIT_7 in the host-parameters section allows for modification to 2596 * internal driver logging. 2597 */ 2598 if (nv->host_p[0] & BIT_7) 2599 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 2600 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); 2601 /* Always load RISC code on non ISP2[12]00 chips. */ 2602 if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) 2603 ha->flags.disable_risc_code_load = 0; 2604 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0); 2605 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); 2606 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); 2607 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; 2608 ha->flags.disable_serdes = 0; 2609 2610 ha->operating_mode = 2611 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; 2612 2613 memcpy(ha->fw_seriallink_options, nv->seriallink_options, 2614 sizeof(ha->fw_seriallink_options)); 2615 2616 /* save HBA serial number */ 2617 ha->serial0 = icb->port_name[5]; 2618 ha->serial1 = icb->port_name[6]; 2619 ha->serial2 = icb->port_name[7]; 2620 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 2621 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 2622 2623 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); 2624 2625 ha->retry_count = nv->retry_count; 2626 2627 /* Set minimum login_timeout to 4 seconds. */ 2628 if (nv->login_timeout != ql2xlogintimeout) 2629 nv->login_timeout = ql2xlogintimeout; 2630 if (nv->login_timeout < 4) 2631 nv->login_timeout = 4; 2632 ha->login_timeout = nv->login_timeout; 2633 icb->login_timeout = nv->login_timeout; 2634 2635 /* Set minimum RATOV to 100 tenths of a second. */ 2636 ha->r_a_tov = 100; 2637 2638 ha->loop_reset_delay = nv->reset_delay; 2639 2640 /* Link Down Timeout = 0: 2641 * 2642 * When Port Down timer expires we will start returning 2643 * I/O's to OS with "DID_NO_CONNECT". 2644 * 2645 * Link Down Timeout != 0: 2646 * 2647 * The driver waits for the link to come up after link down 2648 * before returning I/Os to OS with "DID_NO_CONNECT". 2649 */ 2650 if (nv->link_down_timeout == 0) { 2651 ha->loop_down_abort_time = 2652 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 2653 } else { 2654 ha->link_down_timeout = nv->link_down_timeout; 2655 ha->loop_down_abort_time = 2656 (LOOP_DOWN_TIME - ha->link_down_timeout); 2657 } 2658 2659 /* 2660 * Need enough time to try and get the port back. 2661 */ 2662 ha->port_down_retry_count = nv->port_down_retry_count; 2663 if (qlport_down_retry) 2664 ha->port_down_retry_count = qlport_down_retry; 2665 /* Set login_retry_count */ 2666 ha->login_retry_count = nv->retry_count; 2667 if (ha->port_down_retry_count == nv->port_down_retry_count && 2668 ha->port_down_retry_count > 3) 2669 ha->login_retry_count = ha->port_down_retry_count; 2670 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 2671 ha->login_retry_count = ha->port_down_retry_count; 2672 if (ql2xloginretrycount) 2673 ha->login_retry_count = ql2xloginretrycount; 2674 2675 icb->lun_enables = __constant_cpu_to_le16(0); 2676 icb->command_resource_count = 0; 2677 icb->immediate_notify_resource_count = 0; 2678 icb->timeout = __constant_cpu_to_le16(0); 2679 2680 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 2681 /* Enable RIO */ 2682 icb->firmware_options[0] &= ~BIT_3; 2683 icb->add_firmware_options[0] &= 2684 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 2685 icb->add_firmware_options[0] |= BIT_2; 2686 icb->response_accumulation_timer = 3; 2687 icb->interrupt_delay_timer = 5; 2688 2689 vha->flags.process_response_queue = 1; 2690 } else { 2691 /* Enable ZIO. */ 2692 if (!vha->flags.init_done) { 2693 ha->zio_mode = icb->add_firmware_options[0] & 2694 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 2695 ha->zio_timer = icb->interrupt_delay_timer ? 2696 icb->interrupt_delay_timer: 2; 2697 } 2698 icb->add_firmware_options[0] &= 2699 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 2700 vha->flags.process_response_queue = 0; 2701 if (ha->zio_mode != QLA_ZIO_DISABLED) { 2702 ha->zio_mode = QLA_ZIO_MODE_6; 2703 2704 ql_log(ql_log_info, vha, 0x0068, 2705 "ZIO mode %d enabled; timer delay (%d us).\n", 2706 ha->zio_mode, ha->zio_timer * 100); 2707 2708 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode; 2709 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer; 2710 vha->flags.process_response_queue = 1; 2711 } 2712 } 2713 2714 if (rval) { 2715 ql_log(ql_log_warn, vha, 0x0069, 2716 "NVRAM configuration failed.\n"); 2717 } 2718 return (rval); 2719 } 2720 2721 static void 2722 qla2x00_rport_del(void *data) 2723 { 2724 fc_port_t *fcport = data; 2725 struct fc_rport *rport; 2726 scsi_qla_host_t *vha = fcport->vha; 2727 unsigned long flags; 2728 2729 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 2730 rport = fcport->drport ? fcport->drport: fcport->rport; 2731 fcport->drport = NULL; 2732 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 2733 if (rport) { 2734 fc_remote_port_delete(rport); 2735 /* 2736 * Release the target mode FC NEXUS in qla_target.c code 2737 * if target mod is enabled. 2738 */ 2739 qlt_fc_port_deleted(vha, fcport); 2740 } 2741 } 2742 2743 /** 2744 * qla2x00_alloc_fcport() - Allocate a generic fcport. 2745 * @ha: HA context 2746 * @flags: allocation flags 2747 * 2748 * Returns a pointer to the allocated fcport, or NULL, if none available. 2749 */ 2750 fc_port_t * 2751 qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags) 2752 { 2753 fc_port_t *fcport; 2754 2755 fcport = kzalloc(sizeof(fc_port_t), flags); 2756 if (!fcport) 2757 return NULL; 2758 2759 /* Setup fcport template structure. */ 2760 fcport->vha = vha; 2761 fcport->port_type = FCT_UNKNOWN; 2762 fcport->loop_id = FC_NO_LOOP_ID; 2763 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED); 2764 fcport->supported_classes = FC_COS_UNSPECIFIED; 2765 2766 return fcport; 2767 } 2768 2769 /* 2770 * qla2x00_configure_loop 2771 * Updates Fibre Channel Device Database with what is actually on loop. 2772 * 2773 * Input: 2774 * ha = adapter block pointer. 2775 * 2776 * Returns: 2777 * 0 = success. 2778 * 1 = error. 2779 * 2 = database was full and device was not configured. 2780 */ 2781 static int 2782 qla2x00_configure_loop(scsi_qla_host_t *vha) 2783 { 2784 int rval; 2785 unsigned long flags, save_flags; 2786 struct qla_hw_data *ha = vha->hw; 2787 rval = QLA_SUCCESS; 2788 2789 /* Get Initiator ID */ 2790 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) { 2791 rval = qla2x00_configure_hba(vha); 2792 if (rval != QLA_SUCCESS) { 2793 ql_dbg(ql_dbg_disc, vha, 0x2013, 2794 "Unable to configure HBA.\n"); 2795 return (rval); 2796 } 2797 } 2798 2799 save_flags = flags = vha->dpc_flags; 2800 ql_dbg(ql_dbg_disc, vha, 0x2014, 2801 "Configure loop -- dpc flags = 0x%lx.\n", flags); 2802 2803 /* 2804 * If we have both an RSCN and PORT UPDATE pending then handle them 2805 * both at the same time. 2806 */ 2807 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2808 clear_bit(RSCN_UPDATE, &vha->dpc_flags); 2809 2810 qla2x00_get_data_rate(vha); 2811 2812 /* Determine what we need to do */ 2813 if (ha->current_topology == ISP_CFG_FL && 2814 (test_bit(LOCAL_LOOP_UPDATE, &flags))) { 2815 2816 set_bit(RSCN_UPDATE, &flags); 2817 2818 } else if (ha->current_topology == ISP_CFG_F && 2819 (test_bit(LOCAL_LOOP_UPDATE, &flags))) { 2820 2821 set_bit(RSCN_UPDATE, &flags); 2822 clear_bit(LOCAL_LOOP_UPDATE, &flags); 2823 2824 } else if (ha->current_topology == ISP_CFG_N) { 2825 clear_bit(RSCN_UPDATE, &flags); 2826 2827 } else if (!vha->flags.online || 2828 (test_bit(ABORT_ISP_ACTIVE, &flags))) { 2829 2830 set_bit(RSCN_UPDATE, &flags); 2831 set_bit(LOCAL_LOOP_UPDATE, &flags); 2832 } 2833 2834 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) { 2835 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 2836 ql_dbg(ql_dbg_disc, vha, 0x2015, 2837 "Loop resync needed, failing.\n"); 2838 rval = QLA_FUNCTION_FAILED; 2839 } else 2840 rval = qla2x00_configure_local_loop(vha); 2841 } 2842 2843 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) { 2844 if (LOOP_TRANSITION(vha)) { 2845 ql_dbg(ql_dbg_disc, vha, 0x201e, 2846 "Needs RSCN update and loop transition.\n"); 2847 rval = QLA_FUNCTION_FAILED; 2848 } 2849 else 2850 rval = qla2x00_configure_fabric(vha); 2851 } 2852 2853 if (rval == QLA_SUCCESS) { 2854 if (atomic_read(&vha->loop_down_timer) || 2855 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 2856 rval = QLA_FUNCTION_FAILED; 2857 } else { 2858 atomic_set(&vha->loop_state, LOOP_READY); 2859 ql_dbg(ql_dbg_disc, vha, 0x2069, 2860 "LOOP READY.\n"); 2861 } 2862 } 2863 2864 if (rval) { 2865 ql_dbg(ql_dbg_disc, vha, 0x206a, 2866 "%s *** FAILED ***.\n", __func__); 2867 } else { 2868 ql_dbg(ql_dbg_disc, vha, 0x206b, 2869 "%s: exiting normally.\n", __func__); 2870 } 2871 2872 /* Restore state if a resync event occurred during processing */ 2873 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 2874 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags)) 2875 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2876 if (test_bit(RSCN_UPDATE, &save_flags)) { 2877 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2878 } 2879 } 2880 2881 return (rval); 2882 } 2883 2884 2885 2886 /* 2887 * qla2x00_configure_local_loop 2888 * Updates Fibre Channel Device Database with local loop devices. 2889 * 2890 * Input: 2891 * ha = adapter block pointer. 2892 * 2893 * Returns: 2894 * 0 = success. 2895 */ 2896 static int 2897 qla2x00_configure_local_loop(scsi_qla_host_t *vha) 2898 { 2899 int rval, rval2; 2900 int found_devs; 2901 int found; 2902 fc_port_t *fcport, *new_fcport; 2903 2904 uint16_t index; 2905 uint16_t entries; 2906 char *id_iter; 2907 uint16_t loop_id; 2908 uint8_t domain, area, al_pa; 2909 struct qla_hw_data *ha = vha->hw; 2910 2911 found_devs = 0; 2912 new_fcport = NULL; 2913 entries = MAX_FIBRE_DEVICES_LOOP; 2914 2915 /* Get list of logged in devices. */ 2916 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha)); 2917 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma, 2918 &entries); 2919 if (rval != QLA_SUCCESS) 2920 goto cleanup_allocation; 2921 2922 ql_dbg(ql_dbg_disc, vha, 0x2017, 2923 "Entries in ID list (%d).\n", entries); 2924 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075, 2925 (uint8_t *)ha->gid_list, 2926 entries * sizeof(struct gid_list_info)); 2927 2928 /* Allocate temporary fcport for any new fcports discovered. */ 2929 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 2930 if (new_fcport == NULL) { 2931 ql_log(ql_log_warn, vha, 0x2018, 2932 "Memory allocation failed for fcport.\n"); 2933 rval = QLA_MEMORY_ALLOC_FAILED; 2934 goto cleanup_allocation; 2935 } 2936 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 2937 2938 /* 2939 * Mark local devices that were present with FCF_DEVICE_LOST for now. 2940 */ 2941 list_for_each_entry(fcport, &vha->vp_fcports, list) { 2942 if (atomic_read(&fcport->state) == FCS_ONLINE && 2943 fcport->port_type != FCT_BROADCAST && 2944 (fcport->flags & FCF_FABRIC_DEVICE) == 0) { 2945 2946 ql_dbg(ql_dbg_disc, vha, 0x2019, 2947 "Marking port lost loop_id=0x%04x.\n", 2948 fcport->loop_id); 2949 2950 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 2951 } 2952 } 2953 2954 /* Add devices to port list. */ 2955 id_iter = (char *)ha->gid_list; 2956 for (index = 0; index < entries; index++) { 2957 domain = ((struct gid_list_info *)id_iter)->domain; 2958 area = ((struct gid_list_info *)id_iter)->area; 2959 al_pa = ((struct gid_list_info *)id_iter)->al_pa; 2960 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 2961 loop_id = (uint16_t) 2962 ((struct gid_list_info *)id_iter)->loop_id_2100; 2963 else 2964 loop_id = le16_to_cpu( 2965 ((struct gid_list_info *)id_iter)->loop_id); 2966 id_iter += ha->gid_list_info_size; 2967 2968 /* Bypass reserved domain fields. */ 2969 if ((domain & 0xf0) == 0xf0) 2970 continue; 2971 2972 /* Bypass if not same domain and area of adapter. */ 2973 if (area && domain && 2974 (area != vha->d_id.b.area || domain != vha->d_id.b.domain)) 2975 continue; 2976 2977 /* Bypass invalid local loop ID. */ 2978 if (loop_id > LAST_LOCAL_LOOP_ID) 2979 continue; 2980 2981 memset(new_fcport, 0, sizeof(fc_port_t)); 2982 2983 /* Fill in member data. */ 2984 new_fcport->d_id.b.domain = domain; 2985 new_fcport->d_id.b.area = area; 2986 new_fcport->d_id.b.al_pa = al_pa; 2987 new_fcport->loop_id = loop_id; 2988 rval2 = qla2x00_get_port_database(vha, new_fcport, 0); 2989 if (rval2 != QLA_SUCCESS) { 2990 ql_dbg(ql_dbg_disc, vha, 0x201a, 2991 "Failed to retrieve fcport information " 2992 "-- get_port_database=%x, loop_id=0x%04x.\n", 2993 rval2, new_fcport->loop_id); 2994 ql_dbg(ql_dbg_disc, vha, 0x201b, 2995 "Scheduling resync.\n"); 2996 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2997 continue; 2998 } 2999 3000 /* Check for matching device in port list. */ 3001 found = 0; 3002 fcport = NULL; 3003 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3004 if (memcmp(new_fcport->port_name, fcport->port_name, 3005 WWN_SIZE)) 3006 continue; 3007 3008 fcport->flags &= ~FCF_FABRIC_DEVICE; 3009 fcport->loop_id = new_fcport->loop_id; 3010 fcport->port_type = new_fcport->port_type; 3011 fcport->d_id.b24 = new_fcport->d_id.b24; 3012 memcpy(fcport->node_name, new_fcport->node_name, 3013 WWN_SIZE); 3014 3015 found++; 3016 break; 3017 } 3018 3019 if (!found) { 3020 /* New device, add to fcports list. */ 3021 list_add_tail(&new_fcport->list, &vha->vp_fcports); 3022 3023 /* Allocate a new replacement fcport. */ 3024 fcport = new_fcport; 3025 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 3026 if (new_fcport == NULL) { 3027 ql_log(ql_log_warn, vha, 0x201c, 3028 "Failed to allocate memory for fcport.\n"); 3029 rval = QLA_MEMORY_ALLOC_FAILED; 3030 goto cleanup_allocation; 3031 } 3032 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 3033 } 3034 3035 /* Base iIDMA settings on HBA port speed. */ 3036 fcport->fp_speed = ha->link_data_rate; 3037 3038 qla2x00_update_fcport(vha, fcport); 3039 3040 found_devs++; 3041 } 3042 3043 cleanup_allocation: 3044 kfree(new_fcport); 3045 3046 if (rval != QLA_SUCCESS) { 3047 ql_dbg(ql_dbg_disc, vha, 0x201d, 3048 "Configure local loop error exit: rval=%x.\n", rval); 3049 } 3050 3051 return (rval); 3052 } 3053 3054 static void 3055 qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 3056 { 3057 int rval; 3058 uint16_t mb[4]; 3059 struct qla_hw_data *ha = vha->hw; 3060 3061 if (!IS_IIDMA_CAPABLE(ha)) 3062 return; 3063 3064 if (atomic_read(&fcport->state) != FCS_ONLINE) 3065 return; 3066 3067 if (fcport->fp_speed == PORT_SPEED_UNKNOWN || 3068 fcport->fp_speed > ha->link_data_rate) 3069 return; 3070 3071 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed, 3072 mb); 3073 if (rval != QLA_SUCCESS) { 3074 ql_dbg(ql_dbg_disc, vha, 0x2004, 3075 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n", 3076 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]); 3077 } else { 3078 ql_dbg(ql_dbg_disc, vha, 0x2005, 3079 "iIDMA adjusted to %s GB/s on %8phN.\n", 3080 qla2x00_get_link_speed_str(ha, fcport->fp_speed), 3081 fcport->port_name); 3082 } 3083 } 3084 3085 static void 3086 qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport) 3087 { 3088 struct fc_rport_identifiers rport_ids; 3089 struct fc_rport *rport; 3090 unsigned long flags; 3091 3092 qla2x00_rport_del(fcport); 3093 3094 rport_ids.node_name = wwn_to_u64(fcport->node_name); 3095 rport_ids.port_name = wwn_to_u64(fcport->port_name); 3096 rport_ids.port_id = fcport->d_id.b.domain << 16 | 3097 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa; 3098 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; 3099 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids); 3100 if (!rport) { 3101 ql_log(ql_log_warn, vha, 0x2006, 3102 "Unable to allocate fc remote port.\n"); 3103 return; 3104 } 3105 /* 3106 * Create target mode FC NEXUS in qla_target.c if target mode is 3107 * enabled.. 3108 */ 3109 qlt_fc_port_added(vha, fcport); 3110 3111 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 3112 *((fc_port_t **)rport->dd_data) = fcport; 3113 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 3114 3115 rport->supported_classes = fcport->supported_classes; 3116 3117 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; 3118 if (fcport->port_type == FCT_INITIATOR) 3119 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR; 3120 if (fcport->port_type == FCT_TARGET) 3121 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET; 3122 fc_remote_port_rolechg(rport, rport_ids.roles); 3123 } 3124 3125 /* 3126 * qla2x00_update_fcport 3127 * Updates device on list. 3128 * 3129 * Input: 3130 * ha = adapter block pointer. 3131 * fcport = port structure pointer. 3132 * 3133 * Return: 3134 * 0 - Success 3135 * BIT_0 - error 3136 * 3137 * Context: 3138 * Kernel context. 3139 */ 3140 void 3141 qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 3142 { 3143 fcport->vha = vha; 3144 3145 if (IS_QLAFX00(vha->hw)) { 3146 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 3147 qla2x00_reg_remote_port(vha, fcport); 3148 return; 3149 } 3150 fcport->login_retry = 0; 3151 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 3152 3153 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 3154 qla2x00_iidma_fcport(vha, fcport); 3155 qla24xx_update_fcport_fcp_prio(vha, fcport); 3156 qla2x00_reg_remote_port(vha, fcport); 3157 } 3158 3159 /* 3160 * qla2x00_configure_fabric 3161 * Setup SNS devices with loop ID's. 3162 * 3163 * Input: 3164 * ha = adapter block pointer. 3165 * 3166 * Returns: 3167 * 0 = success. 3168 * BIT_0 = error 3169 */ 3170 static int 3171 qla2x00_configure_fabric(scsi_qla_host_t *vha) 3172 { 3173 int rval; 3174 fc_port_t *fcport, *fcptemp; 3175 uint16_t next_loopid; 3176 uint16_t mb[MAILBOX_REGISTER_COUNT]; 3177 uint16_t loop_id; 3178 LIST_HEAD(new_fcports); 3179 struct qla_hw_data *ha = vha->hw; 3180 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3181 3182 /* If FL port exists, then SNS is present */ 3183 if (IS_FWI2_CAPABLE(ha)) 3184 loop_id = NPH_F_PORT; 3185 else 3186 loop_id = SNS_FL_PORT; 3187 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1); 3188 if (rval != QLA_SUCCESS) { 3189 ql_dbg(ql_dbg_disc, vha, 0x201f, 3190 "MBX_GET_PORT_NAME failed, No FL Port.\n"); 3191 3192 vha->device_flags &= ~SWITCH_FOUND; 3193 return (QLA_SUCCESS); 3194 } 3195 vha->device_flags |= SWITCH_FOUND; 3196 3197 do { 3198 /* FDMI support. */ 3199 if (ql2xfdmienable && 3200 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags)) 3201 qla2x00_fdmi_register(vha); 3202 3203 /* Ensure we are logged into the SNS. */ 3204 if (IS_FWI2_CAPABLE(ha)) 3205 loop_id = NPH_SNS; 3206 else 3207 loop_id = SIMPLE_NAME_SERVER; 3208 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff, 3209 0xfc, mb, BIT_1|BIT_0); 3210 if (rval != QLA_SUCCESS) { 3211 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 3212 return rval; 3213 } 3214 if (mb[0] != MBS_COMMAND_COMPLETE) { 3215 ql_dbg(ql_dbg_disc, vha, 0x2042, 3216 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x " 3217 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1], 3218 mb[2], mb[6], mb[7]); 3219 return (QLA_SUCCESS); 3220 } 3221 3222 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) { 3223 if (qla2x00_rft_id(vha)) { 3224 /* EMPTY */ 3225 ql_dbg(ql_dbg_disc, vha, 0x2045, 3226 "Register FC-4 TYPE failed.\n"); 3227 } 3228 if (qla2x00_rff_id(vha)) { 3229 /* EMPTY */ 3230 ql_dbg(ql_dbg_disc, vha, 0x2049, 3231 "Register FC-4 Features failed.\n"); 3232 } 3233 if (qla2x00_rnn_id(vha)) { 3234 /* EMPTY */ 3235 ql_dbg(ql_dbg_disc, vha, 0x204f, 3236 "Register Node Name failed.\n"); 3237 } else if (qla2x00_rsnn_nn(vha)) { 3238 /* EMPTY */ 3239 ql_dbg(ql_dbg_disc, vha, 0x2053, 3240 "Register Symobilic Node Name failed.\n"); 3241 } 3242 } 3243 3244 #define QLA_FCPORT_SCAN 1 3245 #define QLA_FCPORT_FOUND 2 3246 3247 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3248 fcport->scan_state = QLA_FCPORT_SCAN; 3249 } 3250 3251 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports); 3252 if (rval != QLA_SUCCESS) 3253 break; 3254 3255 /* 3256 * Logout all previous fabric devices marked lost, except 3257 * FCP2 devices. 3258 */ 3259 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3260 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 3261 break; 3262 3263 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) 3264 continue; 3265 3266 if (fcport->scan_state == QLA_FCPORT_SCAN && 3267 atomic_read(&fcport->state) == FCS_ONLINE) { 3268 qla2x00_mark_device_lost(vha, fcport, 3269 ql2xplogiabsentdevice, 0); 3270 if (fcport->loop_id != FC_NO_LOOP_ID && 3271 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 3272 fcport->port_type != FCT_INITIATOR && 3273 fcport->port_type != FCT_BROADCAST) { 3274 ha->isp_ops->fabric_logout(vha, 3275 fcport->loop_id, 3276 fcport->d_id.b.domain, 3277 fcport->d_id.b.area, 3278 fcport->d_id.b.al_pa); 3279 fcport->loop_id = FC_NO_LOOP_ID; 3280 } 3281 } 3282 } 3283 3284 /* Starting free loop ID. */ 3285 next_loopid = ha->min_external_loopid; 3286 3287 /* 3288 * Scan through our port list and login entries that need to be 3289 * logged in. 3290 */ 3291 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3292 if (atomic_read(&vha->loop_down_timer) || 3293 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 3294 break; 3295 3296 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 || 3297 (fcport->flags & FCF_LOGIN_NEEDED) == 0) 3298 continue; 3299 3300 if (fcport->loop_id == FC_NO_LOOP_ID) { 3301 fcport->loop_id = next_loopid; 3302 rval = qla2x00_find_new_loop_id( 3303 base_vha, fcport); 3304 if (rval != QLA_SUCCESS) { 3305 /* Ran out of IDs to use */ 3306 break; 3307 } 3308 } 3309 /* Login and update database */ 3310 qla2x00_fabric_dev_login(vha, fcport, &next_loopid); 3311 } 3312 3313 /* Exit if out of loop IDs. */ 3314 if (rval != QLA_SUCCESS) { 3315 break; 3316 } 3317 3318 /* 3319 * Login and add the new devices to our port list. 3320 */ 3321 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) { 3322 if (atomic_read(&vha->loop_down_timer) || 3323 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 3324 break; 3325 3326 /* Find a new loop ID to use. */ 3327 fcport->loop_id = next_loopid; 3328 rval = qla2x00_find_new_loop_id(base_vha, fcport); 3329 if (rval != QLA_SUCCESS) { 3330 /* Ran out of IDs to use */ 3331 break; 3332 } 3333 3334 /* Login and update database */ 3335 qla2x00_fabric_dev_login(vha, fcport, &next_loopid); 3336 3337 list_move_tail(&fcport->list, &vha->vp_fcports); 3338 } 3339 } while (0); 3340 3341 /* Free all new device structures not processed. */ 3342 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) { 3343 list_del(&fcport->list); 3344 kfree(fcport); 3345 } 3346 3347 if (rval) { 3348 ql_dbg(ql_dbg_disc, vha, 0x2068, 3349 "Configure fabric error exit rval=%d.\n", rval); 3350 } 3351 3352 return (rval); 3353 } 3354 3355 /* 3356 * qla2x00_find_all_fabric_devs 3357 * 3358 * Input: 3359 * ha = adapter block pointer. 3360 * dev = database device entry pointer. 3361 * 3362 * Returns: 3363 * 0 = success. 3364 * 3365 * Context: 3366 * Kernel context. 3367 */ 3368 static int 3369 qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha, 3370 struct list_head *new_fcports) 3371 { 3372 int rval; 3373 uint16_t loop_id; 3374 fc_port_t *fcport, *new_fcport, *fcptemp; 3375 int found; 3376 3377 sw_info_t *swl; 3378 int swl_idx; 3379 int first_dev, last_dev; 3380 port_id_t wrap = {}, nxt_d_id; 3381 struct qla_hw_data *ha = vha->hw; 3382 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3383 3384 rval = QLA_SUCCESS; 3385 3386 /* Try GID_PT to get device list, else GAN. */ 3387 if (!ha->swl) 3388 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t), 3389 GFP_KERNEL); 3390 swl = ha->swl; 3391 if (!swl) { 3392 /*EMPTY*/ 3393 ql_dbg(ql_dbg_disc, vha, 0x2054, 3394 "GID_PT allocations failed, fallback on GA_NXT.\n"); 3395 } else { 3396 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t)); 3397 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) { 3398 swl = NULL; 3399 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) { 3400 swl = NULL; 3401 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) { 3402 swl = NULL; 3403 } else if (ql2xiidmaenable && 3404 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) { 3405 qla2x00_gpsc(vha, swl); 3406 } 3407 3408 /* If other queries succeeded probe for FC-4 type */ 3409 if (swl) 3410 qla2x00_gff_id(vha, swl); 3411 } 3412 swl_idx = 0; 3413 3414 /* Allocate temporary fcport for any new fcports discovered. */ 3415 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 3416 if (new_fcport == NULL) { 3417 ql_log(ql_log_warn, vha, 0x205e, 3418 "Failed to allocate memory for fcport.\n"); 3419 return (QLA_MEMORY_ALLOC_FAILED); 3420 } 3421 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 3422 /* Set start port ID scan at adapter ID. */ 3423 first_dev = 1; 3424 last_dev = 0; 3425 3426 /* Starting free loop ID. */ 3427 loop_id = ha->min_external_loopid; 3428 for (; loop_id <= ha->max_loop_id; loop_id++) { 3429 if (qla2x00_is_reserved_id(vha, loop_id)) 3430 continue; 3431 3432 if (ha->current_topology == ISP_CFG_FL && 3433 (atomic_read(&vha->loop_down_timer) || 3434 LOOP_TRANSITION(vha))) { 3435 atomic_set(&vha->loop_down_timer, 0); 3436 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 3437 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 3438 break; 3439 } 3440 3441 if (swl != NULL) { 3442 if (last_dev) { 3443 wrap.b24 = new_fcport->d_id.b24; 3444 } else { 3445 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24; 3446 memcpy(new_fcport->node_name, 3447 swl[swl_idx].node_name, WWN_SIZE); 3448 memcpy(new_fcport->port_name, 3449 swl[swl_idx].port_name, WWN_SIZE); 3450 memcpy(new_fcport->fabric_port_name, 3451 swl[swl_idx].fabric_port_name, WWN_SIZE); 3452 new_fcport->fp_speed = swl[swl_idx].fp_speed; 3453 new_fcport->fc4_type = swl[swl_idx].fc4_type; 3454 3455 if (swl[swl_idx].d_id.b.rsvd_1 != 0) { 3456 last_dev = 1; 3457 } 3458 swl_idx++; 3459 } 3460 } else { 3461 /* Send GA_NXT to the switch */ 3462 rval = qla2x00_ga_nxt(vha, new_fcport); 3463 if (rval != QLA_SUCCESS) { 3464 ql_log(ql_log_warn, vha, 0x2064, 3465 "SNS scan failed -- assuming " 3466 "zero-entry result.\n"); 3467 list_for_each_entry_safe(fcport, fcptemp, 3468 new_fcports, list) { 3469 list_del(&fcport->list); 3470 kfree(fcport); 3471 } 3472 rval = QLA_SUCCESS; 3473 break; 3474 } 3475 } 3476 3477 /* If wrap on switch device list, exit. */ 3478 if (first_dev) { 3479 wrap.b24 = new_fcport->d_id.b24; 3480 first_dev = 0; 3481 } else if (new_fcport->d_id.b24 == wrap.b24) { 3482 ql_dbg(ql_dbg_disc, vha, 0x2065, 3483 "Device wrap (%02x%02x%02x).\n", 3484 new_fcport->d_id.b.domain, 3485 new_fcport->d_id.b.area, 3486 new_fcport->d_id.b.al_pa); 3487 break; 3488 } 3489 3490 /* Bypass if same physical adapter. */ 3491 if (new_fcport->d_id.b24 == base_vha->d_id.b24) 3492 continue; 3493 3494 /* Bypass virtual ports of the same host. */ 3495 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24)) 3496 continue; 3497 3498 /* Bypass if same domain and area of adapter. */ 3499 if (((new_fcport->d_id.b24 & 0xffff00) == 3500 (vha->d_id.b24 & 0xffff00)) && ha->current_topology == 3501 ISP_CFG_FL) 3502 continue; 3503 3504 /* Bypass reserved domain fields. */ 3505 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0) 3506 continue; 3507 3508 /* Bypass ports whose FCP-4 type is not FCP_SCSI */ 3509 if (ql2xgffidenable && 3510 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI && 3511 new_fcport->fc4_type != FC4_TYPE_UNKNOWN)) 3512 continue; 3513 3514 /* Locate matching device in database. */ 3515 found = 0; 3516 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3517 if (memcmp(new_fcport->port_name, fcport->port_name, 3518 WWN_SIZE)) 3519 continue; 3520 3521 fcport->scan_state = QLA_FCPORT_FOUND; 3522 3523 found++; 3524 3525 /* Update port state. */ 3526 memcpy(fcport->fabric_port_name, 3527 new_fcport->fabric_port_name, WWN_SIZE); 3528 fcport->fp_speed = new_fcport->fp_speed; 3529 3530 /* 3531 * If address the same and state FCS_ONLINE, nothing 3532 * changed. 3533 */ 3534 if (fcport->d_id.b24 == new_fcport->d_id.b24 && 3535 atomic_read(&fcport->state) == FCS_ONLINE) { 3536 break; 3537 } 3538 3539 /* 3540 * If device was not a fabric device before. 3541 */ 3542 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) { 3543 fcport->d_id.b24 = new_fcport->d_id.b24; 3544 qla2x00_clear_loop_id(fcport); 3545 fcport->flags |= (FCF_FABRIC_DEVICE | 3546 FCF_LOGIN_NEEDED); 3547 break; 3548 } 3549 3550 /* 3551 * Port ID changed or device was marked to be updated; 3552 * Log it out if still logged in and mark it for 3553 * relogin later. 3554 */ 3555 fcport->d_id.b24 = new_fcport->d_id.b24; 3556 fcport->flags |= FCF_LOGIN_NEEDED; 3557 if (fcport->loop_id != FC_NO_LOOP_ID && 3558 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 3559 (fcport->flags & FCF_ASYNC_SENT) == 0 && 3560 fcport->port_type != FCT_INITIATOR && 3561 fcport->port_type != FCT_BROADCAST) { 3562 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 3563 fcport->d_id.b.domain, fcport->d_id.b.area, 3564 fcport->d_id.b.al_pa); 3565 qla2x00_clear_loop_id(fcport); 3566 } 3567 3568 break; 3569 } 3570 3571 if (found) 3572 continue; 3573 /* If device was not in our fcports list, then add it. */ 3574 list_add_tail(&new_fcport->list, new_fcports); 3575 3576 /* Allocate a new replacement fcport. */ 3577 nxt_d_id.b24 = new_fcport->d_id.b24; 3578 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 3579 if (new_fcport == NULL) { 3580 ql_log(ql_log_warn, vha, 0x2066, 3581 "Memory allocation failed for fcport.\n"); 3582 return (QLA_MEMORY_ALLOC_FAILED); 3583 } 3584 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 3585 new_fcport->d_id.b24 = nxt_d_id.b24; 3586 } 3587 3588 kfree(new_fcport); 3589 3590 return (rval); 3591 } 3592 3593 /* 3594 * qla2x00_find_new_loop_id 3595 * Scan through our port list and find a new usable loop ID. 3596 * 3597 * Input: 3598 * ha: adapter state pointer. 3599 * dev: port structure pointer. 3600 * 3601 * Returns: 3602 * qla2x00 local function return status code. 3603 * 3604 * Context: 3605 * Kernel context. 3606 */ 3607 int 3608 qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) 3609 { 3610 int rval; 3611 struct qla_hw_data *ha = vha->hw; 3612 unsigned long flags = 0; 3613 3614 rval = QLA_SUCCESS; 3615 3616 spin_lock_irqsave(&ha->vport_slock, flags); 3617 3618 dev->loop_id = find_first_zero_bit(ha->loop_id_map, 3619 LOOPID_MAP_SIZE); 3620 if (dev->loop_id >= LOOPID_MAP_SIZE || 3621 qla2x00_is_reserved_id(vha, dev->loop_id)) { 3622 dev->loop_id = FC_NO_LOOP_ID; 3623 rval = QLA_FUNCTION_FAILED; 3624 } else 3625 set_bit(dev->loop_id, ha->loop_id_map); 3626 3627 spin_unlock_irqrestore(&ha->vport_slock, flags); 3628 3629 if (rval == QLA_SUCCESS) 3630 ql_dbg(ql_dbg_disc, dev->vha, 0x2086, 3631 "Assigning new loopid=%x, portid=%x.\n", 3632 dev->loop_id, dev->d_id.b24); 3633 else 3634 ql_log(ql_log_warn, dev->vha, 0x2087, 3635 "No loop_id's available, portid=%x.\n", 3636 dev->d_id.b24); 3637 3638 return (rval); 3639 } 3640 3641 /* 3642 * qla2x00_fabric_dev_login 3643 * Login fabric target device and update FC port database. 3644 * 3645 * Input: 3646 * ha: adapter state pointer. 3647 * fcport: port structure list pointer. 3648 * next_loopid: contains value of a new loop ID that can be used 3649 * by the next login attempt. 3650 * 3651 * Returns: 3652 * qla2x00 local function return status code. 3653 * 3654 * Context: 3655 * Kernel context. 3656 */ 3657 static int 3658 qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport, 3659 uint16_t *next_loopid) 3660 { 3661 int rval; 3662 int retry; 3663 uint8_t opts; 3664 struct qla_hw_data *ha = vha->hw; 3665 3666 rval = QLA_SUCCESS; 3667 retry = 0; 3668 3669 if (IS_ALOGIO_CAPABLE(ha)) { 3670 if (fcport->flags & FCF_ASYNC_SENT) 3671 return rval; 3672 fcport->flags |= FCF_ASYNC_SENT; 3673 rval = qla2x00_post_async_login_work(vha, fcport, NULL); 3674 if (!rval) 3675 return rval; 3676 } 3677 3678 fcport->flags &= ~FCF_ASYNC_SENT; 3679 rval = qla2x00_fabric_login(vha, fcport, next_loopid); 3680 if (rval == QLA_SUCCESS) { 3681 /* Send an ADISC to FCP2 devices.*/ 3682 opts = 0; 3683 if (fcport->flags & FCF_FCP2_DEVICE) 3684 opts |= BIT_1; 3685 rval = qla2x00_get_port_database(vha, fcport, opts); 3686 if (rval != QLA_SUCCESS) { 3687 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 3688 fcport->d_id.b.domain, fcport->d_id.b.area, 3689 fcport->d_id.b.al_pa); 3690 qla2x00_mark_device_lost(vha, fcport, 1, 0); 3691 } else { 3692 qla2x00_update_fcport(vha, fcport); 3693 } 3694 } else { 3695 /* Retry Login. */ 3696 qla2x00_mark_device_lost(vha, fcport, 1, 0); 3697 } 3698 3699 return (rval); 3700 } 3701 3702 /* 3703 * qla2x00_fabric_login 3704 * Issue fabric login command. 3705 * 3706 * Input: 3707 * ha = adapter block pointer. 3708 * device = pointer to FC device type structure. 3709 * 3710 * Returns: 3711 * 0 - Login successfully 3712 * 1 - Login failed 3713 * 2 - Initiator device 3714 * 3 - Fatal error 3715 */ 3716 int 3717 qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport, 3718 uint16_t *next_loopid) 3719 { 3720 int rval; 3721 int retry; 3722 uint16_t tmp_loopid; 3723 uint16_t mb[MAILBOX_REGISTER_COUNT]; 3724 struct qla_hw_data *ha = vha->hw; 3725 3726 retry = 0; 3727 tmp_loopid = 0; 3728 3729 for (;;) { 3730 ql_dbg(ql_dbg_disc, vha, 0x2000, 3731 "Trying Fabric Login w/loop id 0x%04x for port " 3732 "%02x%02x%02x.\n", 3733 fcport->loop_id, fcport->d_id.b.domain, 3734 fcport->d_id.b.area, fcport->d_id.b.al_pa); 3735 3736 /* Login fcport on switch. */ 3737 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id, 3738 fcport->d_id.b.domain, fcport->d_id.b.area, 3739 fcport->d_id.b.al_pa, mb, BIT_0); 3740 if (rval != QLA_SUCCESS) { 3741 return rval; 3742 } 3743 if (mb[0] == MBS_PORT_ID_USED) { 3744 /* 3745 * Device has another loop ID. The firmware team 3746 * recommends the driver perform an implicit login with 3747 * the specified ID again. The ID we just used is save 3748 * here so we return with an ID that can be tried by 3749 * the next login. 3750 */ 3751 retry++; 3752 tmp_loopid = fcport->loop_id; 3753 fcport->loop_id = mb[1]; 3754 3755 ql_dbg(ql_dbg_disc, vha, 0x2001, 3756 "Fabric Login: port in use - next loop " 3757 "id=0x%04x, port id= %02x%02x%02x.\n", 3758 fcport->loop_id, fcport->d_id.b.domain, 3759 fcport->d_id.b.area, fcport->d_id.b.al_pa); 3760 3761 } else if (mb[0] == MBS_COMMAND_COMPLETE) { 3762 /* 3763 * Login succeeded. 3764 */ 3765 if (retry) { 3766 /* A retry occurred before. */ 3767 *next_loopid = tmp_loopid; 3768 } else { 3769 /* 3770 * No retry occurred before. Just increment the 3771 * ID value for next login. 3772 */ 3773 *next_loopid = (fcport->loop_id + 1); 3774 } 3775 3776 if (mb[1] & BIT_0) { 3777 fcport->port_type = FCT_INITIATOR; 3778 } else { 3779 fcport->port_type = FCT_TARGET; 3780 if (mb[1] & BIT_1) { 3781 fcport->flags |= FCF_FCP2_DEVICE; 3782 } 3783 } 3784 3785 if (mb[10] & BIT_0) 3786 fcport->supported_classes |= FC_COS_CLASS2; 3787 if (mb[10] & BIT_1) 3788 fcport->supported_classes |= FC_COS_CLASS3; 3789 3790 if (IS_FWI2_CAPABLE(ha)) { 3791 if (mb[10] & BIT_7) 3792 fcport->flags |= 3793 FCF_CONF_COMP_SUPPORTED; 3794 } 3795 3796 rval = QLA_SUCCESS; 3797 break; 3798 } else if (mb[0] == MBS_LOOP_ID_USED) { 3799 /* 3800 * Loop ID already used, try next loop ID. 3801 */ 3802 fcport->loop_id++; 3803 rval = qla2x00_find_new_loop_id(vha, fcport); 3804 if (rval != QLA_SUCCESS) { 3805 /* Ran out of loop IDs to use */ 3806 break; 3807 } 3808 } else if (mb[0] == MBS_COMMAND_ERROR) { 3809 /* 3810 * Firmware possibly timed out during login. If NO 3811 * retries are left to do then the device is declared 3812 * dead. 3813 */ 3814 *next_loopid = fcport->loop_id; 3815 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 3816 fcport->d_id.b.domain, fcport->d_id.b.area, 3817 fcport->d_id.b.al_pa); 3818 qla2x00_mark_device_lost(vha, fcport, 1, 0); 3819 3820 rval = 1; 3821 break; 3822 } else { 3823 /* 3824 * unrecoverable / not handled error 3825 */ 3826 ql_dbg(ql_dbg_disc, vha, 0x2002, 3827 "Failed=%x port_id=%02x%02x%02x loop_id=%x " 3828 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain, 3829 fcport->d_id.b.area, fcport->d_id.b.al_pa, 3830 fcport->loop_id, jiffies); 3831 3832 *next_loopid = fcport->loop_id; 3833 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 3834 fcport->d_id.b.domain, fcport->d_id.b.area, 3835 fcport->d_id.b.al_pa); 3836 qla2x00_clear_loop_id(fcport); 3837 fcport->login_retry = 0; 3838 3839 rval = 3; 3840 break; 3841 } 3842 } 3843 3844 return (rval); 3845 } 3846 3847 /* 3848 * qla2x00_local_device_login 3849 * Issue local device login command. 3850 * 3851 * Input: 3852 * ha = adapter block pointer. 3853 * loop_id = loop id of device to login to. 3854 * 3855 * Returns (Where's the #define!!!!): 3856 * 0 - Login successfully 3857 * 1 - Login failed 3858 * 3 - Fatal error 3859 */ 3860 int 3861 qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport) 3862 { 3863 int rval; 3864 uint16_t mb[MAILBOX_REGISTER_COUNT]; 3865 3866 memset(mb, 0, sizeof(mb)); 3867 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0); 3868 if (rval == QLA_SUCCESS) { 3869 /* Interrogate mailbox registers for any errors */ 3870 if (mb[0] == MBS_COMMAND_ERROR) 3871 rval = 1; 3872 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR) 3873 /* device not in PCB table */ 3874 rval = 3; 3875 } 3876 3877 return (rval); 3878 } 3879 3880 /* 3881 * qla2x00_loop_resync 3882 * Resync with fibre channel devices. 3883 * 3884 * Input: 3885 * ha = adapter block pointer. 3886 * 3887 * Returns: 3888 * 0 = success 3889 */ 3890 int 3891 qla2x00_loop_resync(scsi_qla_host_t *vha) 3892 { 3893 int rval = QLA_SUCCESS; 3894 uint32_t wait_time; 3895 struct req_que *req; 3896 struct rsp_que *rsp; 3897 3898 if (vha->hw->flags.cpu_affinity_enabled) 3899 req = vha->hw->req_q_map[0]; 3900 else 3901 req = vha->req; 3902 rsp = req->rsp; 3903 3904 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 3905 if (vha->flags.online) { 3906 if (!(rval = qla2x00_fw_ready(vha))) { 3907 /* Wait at most MAX_TARGET RSCNs for a stable link. */ 3908 wait_time = 256; 3909 do { 3910 if (!IS_QLAFX00(vha->hw)) { 3911 /* 3912 * Issue a marker after FW becomes 3913 * ready. 3914 */ 3915 qla2x00_marker(vha, req, rsp, 0, 0, 3916 MK_SYNC_ALL); 3917 vha->marker_needed = 0; 3918 } 3919 3920 /* Remap devices on Loop. */ 3921 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 3922 3923 if (IS_QLAFX00(vha->hw)) 3924 qlafx00_configure_devices(vha); 3925 else 3926 qla2x00_configure_loop(vha); 3927 3928 wait_time--; 3929 } while (!atomic_read(&vha->loop_down_timer) && 3930 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 3931 && wait_time && (test_bit(LOOP_RESYNC_NEEDED, 3932 &vha->dpc_flags))); 3933 } 3934 } 3935 3936 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 3937 return (QLA_FUNCTION_FAILED); 3938 3939 if (rval) 3940 ql_dbg(ql_dbg_disc, vha, 0x206c, 3941 "%s *** FAILED ***.\n", __func__); 3942 3943 return (rval); 3944 } 3945 3946 /* 3947 * qla2x00_perform_loop_resync 3948 * Description: This function will set the appropriate flags and call 3949 * qla2x00_loop_resync. If successful loop will be resynced 3950 * Arguments : scsi_qla_host_t pointer 3951 * returm : Success or Failure 3952 */ 3953 3954 int qla2x00_perform_loop_resync(scsi_qla_host_t *ha) 3955 { 3956 int32_t rval = 0; 3957 3958 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) { 3959 /*Configure the flags so that resync happens properly*/ 3960 atomic_set(&ha->loop_down_timer, 0); 3961 if (!(ha->device_flags & DFLG_NO_CABLE)) { 3962 atomic_set(&ha->loop_state, LOOP_UP); 3963 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); 3964 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); 3965 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); 3966 3967 rval = qla2x00_loop_resync(ha); 3968 } else 3969 atomic_set(&ha->loop_state, LOOP_DEAD); 3970 3971 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags); 3972 } 3973 3974 return rval; 3975 } 3976 3977 void 3978 qla2x00_update_fcports(scsi_qla_host_t *base_vha) 3979 { 3980 fc_port_t *fcport; 3981 struct scsi_qla_host *vha; 3982 struct qla_hw_data *ha = base_vha->hw; 3983 unsigned long flags; 3984 3985 spin_lock_irqsave(&ha->vport_slock, flags); 3986 /* Go with deferred removal of rport references. */ 3987 list_for_each_entry(vha, &base_vha->hw->vp_list, list) { 3988 atomic_inc(&vha->vref_count); 3989 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3990 if (fcport->drport && 3991 atomic_read(&fcport->state) != FCS_UNCONFIGURED) { 3992 spin_unlock_irqrestore(&ha->vport_slock, flags); 3993 qla2x00_rport_del(fcport); 3994 spin_lock_irqsave(&ha->vport_slock, flags); 3995 } 3996 } 3997 atomic_dec(&vha->vref_count); 3998 } 3999 spin_unlock_irqrestore(&ha->vport_slock, flags); 4000 } 4001 4002 /* Assumes idc_lock always held on entry */ 4003 void 4004 qla83xx_reset_ownership(scsi_qla_host_t *vha) 4005 { 4006 struct qla_hw_data *ha = vha->hw; 4007 uint32_t drv_presence, drv_presence_mask; 4008 uint32_t dev_part_info1, dev_part_info2, class_type; 4009 uint32_t class_type_mask = 0x3; 4010 uint16_t fcoe_other_function = 0xffff, i; 4011 4012 if (IS_QLA8044(ha)) { 4013 drv_presence = qla8044_rd_direct(vha, 4014 QLA8044_CRB_DRV_ACTIVE_INDEX); 4015 dev_part_info1 = qla8044_rd_direct(vha, 4016 QLA8044_CRB_DEV_PART_INFO_INDEX); 4017 dev_part_info2 = qla8044_rd_direct(vha, 4018 QLA8044_CRB_DEV_PART_INFO2); 4019 } else { 4020 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4021 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1); 4022 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2); 4023 } 4024 for (i = 0; i < 8; i++) { 4025 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask); 4026 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 4027 (i != ha->portnum)) { 4028 fcoe_other_function = i; 4029 break; 4030 } 4031 } 4032 if (fcoe_other_function == 0xffff) { 4033 for (i = 0; i < 8; i++) { 4034 class_type = ((dev_part_info2 >> (i * 4)) & 4035 class_type_mask); 4036 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 4037 ((i + 8) != ha->portnum)) { 4038 fcoe_other_function = i + 8; 4039 break; 4040 } 4041 } 4042 } 4043 /* 4044 * Prepare drv-presence mask based on fcoe functions present. 4045 * However consider only valid physical fcoe function numbers (0-15). 4046 */ 4047 drv_presence_mask = ~((1 << (ha->portnum)) | 4048 ((fcoe_other_function == 0xffff) ? 4049 0 : (1 << (fcoe_other_function)))); 4050 4051 /* We are the reset owner iff: 4052 * - No other protocol drivers present. 4053 * - This is the lowest among fcoe functions. */ 4054 if (!(drv_presence & drv_presence_mask) && 4055 (ha->portnum < fcoe_other_function)) { 4056 ql_dbg(ql_dbg_p3p, vha, 0xb07f, 4057 "This host is Reset owner.\n"); 4058 ha->flags.nic_core_reset_owner = 1; 4059 } 4060 } 4061 4062 static int 4063 __qla83xx_set_drv_ack(scsi_qla_host_t *vha) 4064 { 4065 int rval = QLA_SUCCESS; 4066 struct qla_hw_data *ha = vha->hw; 4067 uint32_t drv_ack; 4068 4069 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4070 if (rval == QLA_SUCCESS) { 4071 drv_ack |= (1 << ha->portnum); 4072 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 4073 } 4074 4075 return rval; 4076 } 4077 4078 static int 4079 __qla83xx_clear_drv_ack(scsi_qla_host_t *vha) 4080 { 4081 int rval = QLA_SUCCESS; 4082 struct qla_hw_data *ha = vha->hw; 4083 uint32_t drv_ack; 4084 4085 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4086 if (rval == QLA_SUCCESS) { 4087 drv_ack &= ~(1 << ha->portnum); 4088 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 4089 } 4090 4091 return rval; 4092 } 4093 4094 static const char * 4095 qla83xx_dev_state_to_string(uint32_t dev_state) 4096 { 4097 switch (dev_state) { 4098 case QLA8XXX_DEV_COLD: 4099 return "COLD/RE-INIT"; 4100 case QLA8XXX_DEV_INITIALIZING: 4101 return "INITIALIZING"; 4102 case QLA8XXX_DEV_READY: 4103 return "READY"; 4104 case QLA8XXX_DEV_NEED_RESET: 4105 return "NEED RESET"; 4106 case QLA8XXX_DEV_NEED_QUIESCENT: 4107 return "NEED QUIESCENT"; 4108 case QLA8XXX_DEV_FAILED: 4109 return "FAILED"; 4110 case QLA8XXX_DEV_QUIESCENT: 4111 return "QUIESCENT"; 4112 default: 4113 return "Unknown"; 4114 } 4115 } 4116 4117 /* Assumes idc-lock always held on entry */ 4118 void 4119 qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type) 4120 { 4121 struct qla_hw_data *ha = vha->hw; 4122 uint32_t idc_audit_reg = 0, duration_secs = 0; 4123 4124 switch (audit_type) { 4125 case IDC_AUDIT_TIMESTAMP: 4126 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000); 4127 idc_audit_reg = (ha->portnum) | 4128 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8); 4129 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 4130 break; 4131 4132 case IDC_AUDIT_COMPLETION: 4133 duration_secs = ((jiffies_to_msecs(jiffies) - 4134 jiffies_to_msecs(ha->idc_audit_ts)) / 1000); 4135 idc_audit_reg = (ha->portnum) | 4136 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8); 4137 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 4138 break; 4139 4140 default: 4141 ql_log(ql_log_warn, vha, 0xb078, 4142 "Invalid audit type specified.\n"); 4143 break; 4144 } 4145 } 4146 4147 /* Assumes idc_lock always held on entry */ 4148 static int 4149 qla83xx_initiating_reset(scsi_qla_host_t *vha) 4150 { 4151 struct qla_hw_data *ha = vha->hw; 4152 uint32_t idc_control, dev_state; 4153 4154 __qla83xx_get_idc_control(vha, &idc_control); 4155 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) { 4156 ql_log(ql_log_info, vha, 0xb080, 4157 "NIC Core reset has been disabled. idc-control=0x%x\n", 4158 idc_control); 4159 return QLA_FUNCTION_FAILED; 4160 } 4161 4162 /* Set NEED-RESET iff in READY state and we are the reset-owner */ 4163 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4164 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) { 4165 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 4166 QLA8XXX_DEV_NEED_RESET); 4167 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n"); 4168 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP); 4169 } else { 4170 const char *state = qla83xx_dev_state_to_string(dev_state); 4171 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state); 4172 4173 /* SV: XXX: Is timeout required here? */ 4174 /* Wait for IDC state change READY -> NEED_RESET */ 4175 while (dev_state == QLA8XXX_DEV_READY) { 4176 qla83xx_idc_unlock(vha, 0); 4177 msleep(200); 4178 qla83xx_idc_lock(vha, 0); 4179 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4180 } 4181 } 4182 4183 /* Send IDC ack by writing to drv-ack register */ 4184 __qla83xx_set_drv_ack(vha); 4185 4186 return QLA_SUCCESS; 4187 } 4188 4189 int 4190 __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) 4191 { 4192 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 4193 } 4194 4195 int 4196 __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) 4197 { 4198 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 4199 } 4200 4201 static int 4202 qla83xx_check_driver_presence(scsi_qla_host_t *vha) 4203 { 4204 uint32_t drv_presence = 0; 4205 struct qla_hw_data *ha = vha->hw; 4206 4207 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4208 if (drv_presence & (1 << ha->portnum)) 4209 return QLA_SUCCESS; 4210 else 4211 return QLA_TEST_FAILED; 4212 } 4213 4214 int 4215 qla83xx_nic_core_reset(scsi_qla_host_t *vha) 4216 { 4217 int rval = QLA_SUCCESS; 4218 struct qla_hw_data *ha = vha->hw; 4219 4220 ql_dbg(ql_dbg_p3p, vha, 0xb058, 4221 "Entered %s().\n", __func__); 4222 4223 if (vha->device_flags & DFLG_DEV_FAILED) { 4224 ql_log(ql_log_warn, vha, 0xb059, 4225 "Device in unrecoverable FAILED state.\n"); 4226 return QLA_FUNCTION_FAILED; 4227 } 4228 4229 qla83xx_idc_lock(vha, 0); 4230 4231 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) { 4232 ql_log(ql_log_warn, vha, 0xb05a, 4233 "Function=0x%x has been removed from IDC participation.\n", 4234 ha->portnum); 4235 rval = QLA_FUNCTION_FAILED; 4236 goto exit; 4237 } 4238 4239 qla83xx_reset_ownership(vha); 4240 4241 rval = qla83xx_initiating_reset(vha); 4242 4243 /* 4244 * Perform reset if we are the reset-owner, 4245 * else wait till IDC state changes to READY/FAILED. 4246 */ 4247 if (rval == QLA_SUCCESS) { 4248 rval = qla83xx_idc_state_handler(vha); 4249 4250 if (rval == QLA_SUCCESS) 4251 ha->flags.nic_core_hung = 0; 4252 __qla83xx_clear_drv_ack(vha); 4253 } 4254 4255 exit: 4256 qla83xx_idc_unlock(vha, 0); 4257 4258 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__); 4259 4260 return rval; 4261 } 4262 4263 int 4264 qla2xxx_mctp_dump(scsi_qla_host_t *vha) 4265 { 4266 struct qla_hw_data *ha = vha->hw; 4267 int rval = QLA_FUNCTION_FAILED; 4268 4269 if (!IS_MCTP_CAPABLE(ha)) { 4270 /* This message can be removed from the final version */ 4271 ql_log(ql_log_info, vha, 0x506d, 4272 "This board is not MCTP capable\n"); 4273 return rval; 4274 } 4275 4276 if (!ha->mctp_dump) { 4277 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev, 4278 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL); 4279 4280 if (!ha->mctp_dump) { 4281 ql_log(ql_log_warn, vha, 0x506e, 4282 "Failed to allocate memory for mctp dump\n"); 4283 return rval; 4284 } 4285 } 4286 4287 #define MCTP_DUMP_STR_ADDR 0x00000000 4288 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma, 4289 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4); 4290 if (rval != QLA_SUCCESS) { 4291 ql_log(ql_log_warn, vha, 0x506f, 4292 "Failed to capture mctp dump\n"); 4293 } else { 4294 ql_log(ql_log_info, vha, 0x5070, 4295 "Mctp dump capture for host (%ld/%p).\n", 4296 vha->host_no, ha->mctp_dump); 4297 ha->mctp_dumped = 1; 4298 } 4299 4300 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) { 4301 ha->flags.nic_core_reset_hdlr_active = 1; 4302 rval = qla83xx_restart_nic_firmware(vha); 4303 if (rval) 4304 /* NIC Core reset failed. */ 4305 ql_log(ql_log_warn, vha, 0x5071, 4306 "Failed to restart nic firmware\n"); 4307 else 4308 ql_dbg(ql_dbg_p3p, vha, 0xb084, 4309 "Restarted NIC firmware successfully.\n"); 4310 ha->flags.nic_core_reset_hdlr_active = 0; 4311 } 4312 4313 return rval; 4314 4315 } 4316 4317 /* 4318 * qla2x00_quiesce_io 4319 * Description: This function will block the new I/Os 4320 * Its not aborting any I/Os as context 4321 * is not destroyed during quiescence 4322 * Arguments: scsi_qla_host_t 4323 * return : void 4324 */ 4325 void 4326 qla2x00_quiesce_io(scsi_qla_host_t *vha) 4327 { 4328 struct qla_hw_data *ha = vha->hw; 4329 struct scsi_qla_host *vp; 4330 4331 ql_dbg(ql_dbg_dpc, vha, 0x401d, 4332 "Quiescing I/O - ha=%p.\n", ha); 4333 4334 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); 4335 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 4336 atomic_set(&vha->loop_state, LOOP_DOWN); 4337 qla2x00_mark_all_devices_lost(vha, 0); 4338 list_for_each_entry(vp, &ha->vp_list, list) 4339 qla2x00_mark_all_devices_lost(vp, 0); 4340 } else { 4341 if (!atomic_read(&vha->loop_down_timer)) 4342 atomic_set(&vha->loop_down_timer, 4343 LOOP_DOWN_TIME); 4344 } 4345 /* Wait for pending cmds to complete */ 4346 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST); 4347 } 4348 4349 void 4350 qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) 4351 { 4352 struct qla_hw_data *ha = vha->hw; 4353 struct scsi_qla_host *vp; 4354 unsigned long flags; 4355 fc_port_t *fcport; 4356 4357 /* For ISP82XX, driver waits for completion of the commands. 4358 * online flag should be set. 4359 */ 4360 if (!(IS_P3P_TYPE(ha))) 4361 vha->flags.online = 0; 4362 ha->flags.chip_reset_done = 0; 4363 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 4364 vha->qla_stats.total_isp_aborts++; 4365 4366 ql_log(ql_log_info, vha, 0x00af, 4367 "Performing ISP error recovery - ha=%p.\n", ha); 4368 4369 /* For ISP82XX, reset_chip is just disabling interrupts. 4370 * Driver waits for the completion of the commands. 4371 * the interrupts need to be enabled. 4372 */ 4373 if (!(IS_P3P_TYPE(ha))) 4374 ha->isp_ops->reset_chip(vha); 4375 4376 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 4377 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 4378 atomic_set(&vha->loop_state, LOOP_DOWN); 4379 qla2x00_mark_all_devices_lost(vha, 0); 4380 4381 spin_lock_irqsave(&ha->vport_slock, flags); 4382 list_for_each_entry(vp, &ha->vp_list, list) { 4383 atomic_inc(&vp->vref_count); 4384 spin_unlock_irqrestore(&ha->vport_slock, flags); 4385 4386 qla2x00_mark_all_devices_lost(vp, 0); 4387 4388 spin_lock_irqsave(&ha->vport_slock, flags); 4389 atomic_dec(&vp->vref_count); 4390 } 4391 spin_unlock_irqrestore(&ha->vport_slock, flags); 4392 } else { 4393 if (!atomic_read(&vha->loop_down_timer)) 4394 atomic_set(&vha->loop_down_timer, 4395 LOOP_DOWN_TIME); 4396 } 4397 4398 /* Clear all async request states across all VPs. */ 4399 list_for_each_entry(fcport, &vha->vp_fcports, list) 4400 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 4401 spin_lock_irqsave(&ha->vport_slock, flags); 4402 list_for_each_entry(vp, &ha->vp_list, list) { 4403 atomic_inc(&vp->vref_count); 4404 spin_unlock_irqrestore(&ha->vport_slock, flags); 4405 4406 list_for_each_entry(fcport, &vp->vp_fcports, list) 4407 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 4408 4409 spin_lock_irqsave(&ha->vport_slock, flags); 4410 atomic_dec(&vp->vref_count); 4411 } 4412 spin_unlock_irqrestore(&ha->vport_slock, flags); 4413 4414 if (!ha->flags.eeh_busy) { 4415 /* Make sure for ISP 82XX IO DMA is complete */ 4416 if (IS_P3P_TYPE(ha)) { 4417 qla82xx_chip_reset_cleanup(vha); 4418 ql_log(ql_log_info, vha, 0x00b4, 4419 "Done chip reset cleanup.\n"); 4420 4421 /* Done waiting for pending commands. 4422 * Reset the online flag. 4423 */ 4424 vha->flags.online = 0; 4425 } 4426 4427 /* Requeue all commands in outstanding command list. */ 4428 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 4429 } 4430 } 4431 4432 /* 4433 * qla2x00_abort_isp 4434 * Resets ISP and aborts all outstanding commands. 4435 * 4436 * Input: 4437 * ha = adapter block pointer. 4438 * 4439 * Returns: 4440 * 0 = success 4441 */ 4442 int 4443 qla2x00_abort_isp(scsi_qla_host_t *vha) 4444 { 4445 int rval; 4446 uint8_t status = 0; 4447 struct qla_hw_data *ha = vha->hw; 4448 struct scsi_qla_host *vp; 4449 struct req_que *req = ha->req_q_map[0]; 4450 unsigned long flags; 4451 4452 if (vha->flags.online) { 4453 qla2x00_abort_isp_cleanup(vha); 4454 4455 if (IS_QLA8031(ha)) { 4456 ql_dbg(ql_dbg_p3p, vha, 0xb05c, 4457 "Clearing fcoe driver presence.\n"); 4458 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS) 4459 ql_dbg(ql_dbg_p3p, vha, 0xb073, 4460 "Error while clearing DRV-Presence.\n"); 4461 } 4462 4463 if (unlikely(pci_channel_offline(ha->pdev) && 4464 ha->flags.pci_channel_io_perm_failure)) { 4465 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 4466 status = 0; 4467 return status; 4468 } 4469 4470 ha->isp_ops->get_flash_version(vha, req->ring); 4471 4472 ha->isp_ops->nvram_config(vha); 4473 4474 if (!qla2x00_restart_isp(vha)) { 4475 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 4476 4477 if (!atomic_read(&vha->loop_down_timer)) { 4478 /* 4479 * Issue marker command only when we are going 4480 * to start the I/O . 4481 */ 4482 vha->marker_needed = 1; 4483 } 4484 4485 vha->flags.online = 1; 4486 4487 ha->isp_ops->enable_intrs(ha); 4488 4489 ha->isp_abort_cnt = 0; 4490 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 4491 4492 if (IS_QLA81XX(ha) || IS_QLA8031(ha)) 4493 qla2x00_get_fw_version(vha); 4494 if (ha->fce) { 4495 ha->flags.fce_enabled = 1; 4496 memset(ha->fce, 0, 4497 fce_calc_size(ha->fce_bufs)); 4498 rval = qla2x00_enable_fce_trace(vha, 4499 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 4500 &ha->fce_bufs); 4501 if (rval) { 4502 ql_log(ql_log_warn, vha, 0x8033, 4503 "Unable to reinitialize FCE " 4504 "(%d).\n", rval); 4505 ha->flags.fce_enabled = 0; 4506 } 4507 } 4508 4509 if (ha->eft) { 4510 memset(ha->eft, 0, EFT_SIZE); 4511 rval = qla2x00_enable_eft_trace(vha, 4512 ha->eft_dma, EFT_NUM_BUFFERS); 4513 if (rval) { 4514 ql_log(ql_log_warn, vha, 0x8034, 4515 "Unable to reinitialize EFT " 4516 "(%d).\n", rval); 4517 } 4518 } 4519 } else { /* failed the ISP abort */ 4520 vha->flags.online = 1; 4521 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 4522 if (ha->isp_abort_cnt == 0) { 4523 ql_log(ql_log_fatal, vha, 0x8035, 4524 "ISP error recover failed - " 4525 "board disabled.\n"); 4526 /* 4527 * The next call disables the board 4528 * completely. 4529 */ 4530 ha->isp_ops->reset_adapter(vha); 4531 vha->flags.online = 0; 4532 clear_bit(ISP_ABORT_RETRY, 4533 &vha->dpc_flags); 4534 status = 0; 4535 } else { /* schedule another ISP abort */ 4536 ha->isp_abort_cnt--; 4537 ql_dbg(ql_dbg_taskm, vha, 0x8020, 4538 "ISP abort - retry remaining %d.\n", 4539 ha->isp_abort_cnt); 4540 status = 1; 4541 } 4542 } else { 4543 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 4544 ql_dbg(ql_dbg_taskm, vha, 0x8021, 4545 "ISP error recovery - retrying (%d) " 4546 "more times.\n", ha->isp_abort_cnt); 4547 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 4548 status = 1; 4549 } 4550 } 4551 4552 } 4553 4554 if (!status) { 4555 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__); 4556 4557 spin_lock_irqsave(&ha->vport_slock, flags); 4558 list_for_each_entry(vp, &ha->vp_list, list) { 4559 if (vp->vp_idx) { 4560 atomic_inc(&vp->vref_count); 4561 spin_unlock_irqrestore(&ha->vport_slock, flags); 4562 4563 qla2x00_vp_abort_isp(vp); 4564 4565 spin_lock_irqsave(&ha->vport_slock, flags); 4566 atomic_dec(&vp->vref_count); 4567 } 4568 } 4569 spin_unlock_irqrestore(&ha->vport_slock, flags); 4570 4571 if (IS_QLA8031(ha)) { 4572 ql_dbg(ql_dbg_p3p, vha, 0xb05d, 4573 "Setting back fcoe driver presence.\n"); 4574 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS) 4575 ql_dbg(ql_dbg_p3p, vha, 0xb074, 4576 "Error while setting DRV-Presence.\n"); 4577 } 4578 } else { 4579 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n", 4580 __func__); 4581 } 4582 4583 return(status); 4584 } 4585 4586 /* 4587 * qla2x00_restart_isp 4588 * restarts the ISP after a reset 4589 * 4590 * Input: 4591 * ha = adapter block pointer. 4592 * 4593 * Returns: 4594 * 0 = success 4595 */ 4596 static int 4597 qla2x00_restart_isp(scsi_qla_host_t *vha) 4598 { 4599 int status = 0; 4600 uint32_t wait_time; 4601 struct qla_hw_data *ha = vha->hw; 4602 struct req_que *req = ha->req_q_map[0]; 4603 struct rsp_que *rsp = ha->rsp_q_map[0]; 4604 unsigned long flags; 4605 4606 /* If firmware needs to be loaded */ 4607 if (qla2x00_isp_firmware(vha)) { 4608 vha->flags.online = 0; 4609 status = ha->isp_ops->chip_diag(vha); 4610 if (!status) 4611 status = qla2x00_setup_chip(vha); 4612 } 4613 4614 if (!status && !(status = qla2x00_init_rings(vha))) { 4615 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 4616 ha->flags.chip_reset_done = 1; 4617 /* Initialize the queues in use */ 4618 qla25xx_init_queues(ha); 4619 4620 status = qla2x00_fw_ready(vha); 4621 if (!status) { 4622 ql_dbg(ql_dbg_taskm, vha, 0x8031, 4623 "Start configure loop status = %d.\n", status); 4624 4625 /* Issue a marker after FW becomes ready. */ 4626 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); 4627 4628 vha->flags.online = 1; 4629 4630 /* 4631 * Process any ATIO queue entries that came in 4632 * while we weren't online. 4633 */ 4634 spin_lock_irqsave(&ha->hardware_lock, flags); 4635 if (qla_tgt_mode_enabled(vha)) 4636 qlt_24xx_process_atio_queue(vha); 4637 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4638 4639 /* Wait at most MAX_TARGET RSCNs for a stable link. */ 4640 wait_time = 256; 4641 do { 4642 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 4643 qla2x00_configure_loop(vha); 4644 wait_time--; 4645 } while (!atomic_read(&vha->loop_down_timer) && 4646 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 4647 && wait_time && (test_bit(LOOP_RESYNC_NEEDED, 4648 &vha->dpc_flags))); 4649 } 4650 4651 /* if no cable then assume it's good */ 4652 if ((vha->device_flags & DFLG_NO_CABLE)) 4653 status = 0; 4654 4655 ql_dbg(ql_dbg_taskm, vha, 0x8032, 4656 "Configure loop done, status = 0x%x.\n", status); 4657 } 4658 return (status); 4659 } 4660 4661 static int 4662 qla25xx_init_queues(struct qla_hw_data *ha) 4663 { 4664 struct rsp_que *rsp = NULL; 4665 struct req_que *req = NULL; 4666 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 4667 int ret = -1; 4668 int i; 4669 4670 for (i = 1; i < ha->max_rsp_queues; i++) { 4671 rsp = ha->rsp_q_map[i]; 4672 if (rsp) { 4673 rsp->options &= ~BIT_0; 4674 ret = qla25xx_init_rsp_que(base_vha, rsp); 4675 if (ret != QLA_SUCCESS) 4676 ql_dbg(ql_dbg_init, base_vha, 0x00ff, 4677 "%s Rsp que: %d init failed.\n", 4678 __func__, rsp->id); 4679 else 4680 ql_dbg(ql_dbg_init, base_vha, 0x0100, 4681 "%s Rsp que: %d inited.\n", 4682 __func__, rsp->id); 4683 } 4684 } 4685 for (i = 1; i < ha->max_req_queues; i++) { 4686 req = ha->req_q_map[i]; 4687 if (req) { 4688 /* Clear outstanding commands array. */ 4689 req->options &= ~BIT_0; 4690 ret = qla25xx_init_req_que(base_vha, req); 4691 if (ret != QLA_SUCCESS) 4692 ql_dbg(ql_dbg_init, base_vha, 0x0101, 4693 "%s Req que: %d init failed.\n", 4694 __func__, req->id); 4695 else 4696 ql_dbg(ql_dbg_init, base_vha, 0x0102, 4697 "%s Req que: %d inited.\n", 4698 __func__, req->id); 4699 } 4700 } 4701 return ret; 4702 } 4703 4704 /* 4705 * qla2x00_reset_adapter 4706 * Reset adapter. 4707 * 4708 * Input: 4709 * ha = adapter block pointer. 4710 */ 4711 void 4712 qla2x00_reset_adapter(scsi_qla_host_t *vha) 4713 { 4714 unsigned long flags = 0; 4715 struct qla_hw_data *ha = vha->hw; 4716 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4717 4718 vha->flags.online = 0; 4719 ha->isp_ops->disable_intrs(ha); 4720 4721 spin_lock_irqsave(&ha->hardware_lock, flags); 4722 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 4723 RD_REG_WORD(®->hccr); /* PCI Posting. */ 4724 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 4725 RD_REG_WORD(®->hccr); /* PCI Posting. */ 4726 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4727 } 4728 4729 void 4730 qla24xx_reset_adapter(scsi_qla_host_t *vha) 4731 { 4732 unsigned long flags = 0; 4733 struct qla_hw_data *ha = vha->hw; 4734 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 4735 4736 if (IS_P3P_TYPE(ha)) 4737 return; 4738 4739 vha->flags.online = 0; 4740 ha->isp_ops->disable_intrs(ha); 4741 4742 spin_lock_irqsave(&ha->hardware_lock, flags); 4743 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); 4744 RD_REG_DWORD(®->hccr); 4745 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); 4746 RD_REG_DWORD(®->hccr); 4747 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4748 4749 if (IS_NOPOLLING_TYPE(ha)) 4750 ha->isp_ops->enable_intrs(ha); 4751 } 4752 4753 /* On sparc systems, obtain port and node WWN from firmware 4754 * properties. 4755 */ 4756 static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, 4757 struct nvram_24xx *nv) 4758 { 4759 #ifdef CONFIG_SPARC 4760 struct qla_hw_data *ha = vha->hw; 4761 struct pci_dev *pdev = ha->pdev; 4762 struct device_node *dp = pci_device_to_OF_node(pdev); 4763 const u8 *val; 4764 int len; 4765 4766 val = of_get_property(dp, "port-wwn", &len); 4767 if (val && len >= WWN_SIZE) 4768 memcpy(nv->port_name, val, WWN_SIZE); 4769 4770 val = of_get_property(dp, "node-wwn", &len); 4771 if (val && len >= WWN_SIZE) 4772 memcpy(nv->node_name, val, WWN_SIZE); 4773 #endif 4774 } 4775 4776 int 4777 qla24xx_nvram_config(scsi_qla_host_t *vha) 4778 { 4779 int rval; 4780 struct init_cb_24xx *icb; 4781 struct nvram_24xx *nv; 4782 uint32_t *dptr; 4783 uint8_t *dptr1, *dptr2; 4784 uint32_t chksum; 4785 uint16_t cnt; 4786 struct qla_hw_data *ha = vha->hw; 4787 4788 rval = QLA_SUCCESS; 4789 icb = (struct init_cb_24xx *)ha->init_cb; 4790 nv = ha->nvram; 4791 4792 /* Determine NVRAM starting address. */ 4793 if (ha->flags.port0) { 4794 ha->nvram_base = FA_NVRAM_FUNC0_ADDR; 4795 ha->vpd_base = FA_NVRAM_VPD0_ADDR; 4796 } else { 4797 ha->nvram_base = FA_NVRAM_FUNC1_ADDR; 4798 ha->vpd_base = FA_NVRAM_VPD1_ADDR; 4799 } 4800 ha->nvram_size = sizeof(struct nvram_24xx); 4801 ha->vpd_size = FA_NVRAM_VPD_SIZE; 4802 4803 /* Get VPD data into cache */ 4804 ha->vpd = ha->nvram + VPD_OFFSET; 4805 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd, 4806 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4); 4807 4808 /* Get NVRAM data into cache and calculate checksum. */ 4809 dptr = (uint32_t *)nv; 4810 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base, 4811 ha->nvram_size); 4812 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) 4813 chksum += le32_to_cpu(*dptr++); 4814 4815 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a, 4816 "Contents of NVRAM\n"); 4817 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d, 4818 (uint8_t *)nv, ha->nvram_size); 4819 4820 /* Bad NVRAM data, set defaults parameters. */ 4821 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' 4822 || nv->id[3] != ' ' || 4823 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) { 4824 /* Reset NVRAM data. */ 4825 ql_log(ql_log_warn, vha, 0x006b, 4826 "Inconsistent NVRAM detected: checksum=0x%x id=%c " 4827 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version); 4828 ql_log(ql_log_warn, vha, 0x006c, 4829 "Falling back to functioning (yet invalid -- WWPN) " 4830 "defaults.\n"); 4831 4832 /* 4833 * Set default initialization control block. 4834 */ 4835 memset(nv, 0, ha->nvram_size); 4836 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION); 4837 nv->version = __constant_cpu_to_le16(ICB_VERSION); 4838 nv->frame_payload_size = __constant_cpu_to_le16(2048); 4839 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF); 4840 nv->exchange_count = __constant_cpu_to_le16(0); 4841 nv->hard_address = __constant_cpu_to_le16(124); 4842 nv->port_name[0] = 0x21; 4843 nv->port_name[1] = 0x00 + ha->port_no; 4844 nv->port_name[2] = 0x00; 4845 nv->port_name[3] = 0xe0; 4846 nv->port_name[4] = 0x8b; 4847 nv->port_name[5] = 0x1c; 4848 nv->port_name[6] = 0x55; 4849 nv->port_name[7] = 0x86; 4850 nv->node_name[0] = 0x20; 4851 nv->node_name[1] = 0x00; 4852 nv->node_name[2] = 0x00; 4853 nv->node_name[3] = 0xe0; 4854 nv->node_name[4] = 0x8b; 4855 nv->node_name[5] = 0x1c; 4856 nv->node_name[6] = 0x55; 4857 nv->node_name[7] = 0x86; 4858 qla24xx_nvram_wwn_from_ofw(vha, nv); 4859 nv->login_retry_count = __constant_cpu_to_le16(8); 4860 nv->interrupt_delay_timer = __constant_cpu_to_le16(0); 4861 nv->login_timeout = __constant_cpu_to_le16(0); 4862 nv->firmware_options_1 = 4863 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 4864 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4); 4865 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12); 4866 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13); 4867 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10); 4868 nv->efi_parameters = __constant_cpu_to_le32(0); 4869 nv->reset_delay = 5; 4870 nv->max_luns_per_target = __constant_cpu_to_le16(128); 4871 nv->port_down_retry_count = __constant_cpu_to_le16(30); 4872 nv->link_down_timeout = __constant_cpu_to_le16(30); 4873 4874 rval = 1; 4875 } 4876 4877 if (!qla_ini_mode_enabled(vha)) { 4878 /* Don't enable full login after initial LIP */ 4879 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13); 4880 /* Don't enable LIP full login for initiator */ 4881 nv->host_p &= __constant_cpu_to_le32(~BIT_10); 4882 } 4883 4884 qlt_24xx_config_nvram_stage1(vha, nv); 4885 4886 /* Reset Initialization control block */ 4887 memset(icb, 0, ha->init_cb_size); 4888 4889 /* Copy 1st segment. */ 4890 dptr1 = (uint8_t *)icb; 4891 dptr2 = (uint8_t *)&nv->version; 4892 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 4893 while (cnt--) 4894 *dptr1++ = *dptr2++; 4895 4896 icb->login_retry_count = nv->login_retry_count; 4897 icb->link_down_on_nos = nv->link_down_on_nos; 4898 4899 /* Copy 2nd segment. */ 4900 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 4901 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 4902 cnt = (uint8_t *)&icb->reserved_3 - 4903 (uint8_t *)&icb->interrupt_delay_timer; 4904 while (cnt--) 4905 *dptr1++ = *dptr2++; 4906 4907 /* 4908 * Setup driver NVRAM options. 4909 */ 4910 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 4911 "QLA2462"); 4912 4913 qlt_24xx_config_nvram_stage2(vha, icb); 4914 4915 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) { 4916 /* Use alternate WWN? */ 4917 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 4918 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 4919 } 4920 4921 /* Prepare nodename */ 4922 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) { 4923 /* 4924 * Firmware will apply the following mask if the nodename was 4925 * not provided. 4926 */ 4927 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 4928 icb->node_name[0] &= 0xF0; 4929 } 4930 4931 /* Set host adapter parameters. */ 4932 ha->flags.disable_risc_code_load = 0; 4933 ha->flags.enable_lip_reset = 0; 4934 ha->flags.enable_lip_full_login = 4935 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; 4936 ha->flags.enable_target_reset = 4937 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; 4938 ha->flags.enable_led_scheme = 0; 4939 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; 4940 4941 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 4942 (BIT_6 | BIT_5 | BIT_4)) >> 4; 4943 4944 memcpy(ha->fw_seriallink_options24, nv->seriallink_options, 4945 sizeof(ha->fw_seriallink_options24)); 4946 4947 /* save HBA serial number */ 4948 ha->serial0 = icb->port_name[5]; 4949 ha->serial1 = icb->port_name[6]; 4950 ha->serial2 = icb->port_name[7]; 4951 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 4952 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 4953 4954 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); 4955 4956 ha->retry_count = le16_to_cpu(nv->login_retry_count); 4957 4958 /* Set minimum login_timeout to 4 seconds. */ 4959 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 4960 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 4961 if (le16_to_cpu(nv->login_timeout) < 4) 4962 nv->login_timeout = __constant_cpu_to_le16(4); 4963 ha->login_timeout = le16_to_cpu(nv->login_timeout); 4964 icb->login_timeout = nv->login_timeout; 4965 4966 /* Set minimum RATOV to 100 tenths of a second. */ 4967 ha->r_a_tov = 100; 4968 4969 ha->loop_reset_delay = nv->reset_delay; 4970 4971 /* Link Down Timeout = 0: 4972 * 4973 * When Port Down timer expires we will start returning 4974 * I/O's to OS with "DID_NO_CONNECT". 4975 * 4976 * Link Down Timeout != 0: 4977 * 4978 * The driver waits for the link to come up after link down 4979 * before returning I/Os to OS with "DID_NO_CONNECT". 4980 */ 4981 if (le16_to_cpu(nv->link_down_timeout) == 0) { 4982 ha->loop_down_abort_time = 4983 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 4984 } else { 4985 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 4986 ha->loop_down_abort_time = 4987 (LOOP_DOWN_TIME - ha->link_down_timeout); 4988 } 4989 4990 /* Need enough time to try and get the port back. */ 4991 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 4992 if (qlport_down_retry) 4993 ha->port_down_retry_count = qlport_down_retry; 4994 4995 /* Set login_retry_count */ 4996 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 4997 if (ha->port_down_retry_count == 4998 le16_to_cpu(nv->port_down_retry_count) && 4999 ha->port_down_retry_count > 3) 5000 ha->login_retry_count = ha->port_down_retry_count; 5001 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 5002 ha->login_retry_count = ha->port_down_retry_count; 5003 if (ql2xloginretrycount) 5004 ha->login_retry_count = ql2xloginretrycount; 5005 5006 /* Enable ZIO. */ 5007 if (!vha->flags.init_done) { 5008 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 5009 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 5010 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 5011 le16_to_cpu(icb->interrupt_delay_timer): 2; 5012 } 5013 icb->firmware_options_2 &= __constant_cpu_to_le32( 5014 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 5015 vha->flags.process_response_queue = 0; 5016 if (ha->zio_mode != QLA_ZIO_DISABLED) { 5017 ha->zio_mode = QLA_ZIO_MODE_6; 5018 5019 ql_log(ql_log_info, vha, 0x006f, 5020 "ZIO mode %d enabled; timer delay (%d us).\n", 5021 ha->zio_mode, ha->zio_timer * 100); 5022 5023 icb->firmware_options_2 |= cpu_to_le32( 5024 (uint32_t)ha->zio_mode); 5025 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 5026 vha->flags.process_response_queue = 1; 5027 } 5028 5029 if (rval) { 5030 ql_log(ql_log_warn, vha, 0x0070, 5031 "NVRAM configuration failed.\n"); 5032 } 5033 return (rval); 5034 } 5035 5036 static int 5037 qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, 5038 uint32_t faddr) 5039 { 5040 int rval = QLA_SUCCESS; 5041 int segments, fragment; 5042 uint32_t *dcode, dlen; 5043 uint32_t risc_addr; 5044 uint32_t risc_size; 5045 uint32_t i; 5046 struct qla_hw_data *ha = vha->hw; 5047 struct req_que *req = ha->req_q_map[0]; 5048 5049 ql_dbg(ql_dbg_init, vha, 0x008b, 5050 "FW: Loading firmware from flash (%x).\n", faddr); 5051 5052 rval = QLA_SUCCESS; 5053 5054 segments = FA_RISC_CODE_SEGMENTS; 5055 dcode = (uint32_t *)req->ring; 5056 *srisc_addr = 0; 5057 5058 /* Validate firmware image by checking version. */ 5059 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4); 5060 for (i = 0; i < 4; i++) 5061 dcode[i] = be32_to_cpu(dcode[i]); 5062 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 5063 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 5064 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 5065 dcode[3] == 0)) { 5066 ql_log(ql_log_fatal, vha, 0x008c, 5067 "Unable to verify the integrity of flash firmware " 5068 "image.\n"); 5069 ql_log(ql_log_fatal, vha, 0x008d, 5070 "Firmware data: %08x %08x %08x %08x.\n", 5071 dcode[0], dcode[1], dcode[2], dcode[3]); 5072 5073 return QLA_FUNCTION_FAILED; 5074 } 5075 5076 while (segments && rval == QLA_SUCCESS) { 5077 /* Read segment's load information. */ 5078 qla24xx_read_flash_data(vha, dcode, faddr, 4); 5079 5080 risc_addr = be32_to_cpu(dcode[2]); 5081 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; 5082 risc_size = be32_to_cpu(dcode[3]); 5083 5084 fragment = 0; 5085 while (risc_size > 0 && rval == QLA_SUCCESS) { 5086 dlen = (uint32_t)(ha->fw_transfer_size >> 2); 5087 if (dlen > risc_size) 5088 dlen = risc_size; 5089 5090 ql_dbg(ql_dbg_init, vha, 0x008e, 5091 "Loading risc segment@ risc addr %x " 5092 "number of dwords 0x%x offset 0x%x.\n", 5093 risc_addr, dlen, faddr); 5094 5095 qla24xx_read_flash_data(vha, dcode, faddr, dlen); 5096 for (i = 0; i < dlen; i++) 5097 dcode[i] = swab32(dcode[i]); 5098 5099 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 5100 dlen); 5101 if (rval) { 5102 ql_log(ql_log_fatal, vha, 0x008f, 5103 "Failed to load segment %d of firmware.\n", 5104 fragment); 5105 break; 5106 } 5107 5108 faddr += dlen; 5109 risc_addr += dlen; 5110 risc_size -= dlen; 5111 fragment++; 5112 } 5113 5114 /* Next segment. */ 5115 segments--; 5116 } 5117 5118 return rval; 5119 } 5120 5121 #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/" 5122 5123 int 5124 qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 5125 { 5126 int rval; 5127 int i, fragment; 5128 uint16_t *wcode, *fwcode; 5129 uint32_t risc_addr, risc_size, fwclen, wlen, *seg; 5130 struct fw_blob *blob; 5131 struct qla_hw_data *ha = vha->hw; 5132 struct req_que *req = ha->req_q_map[0]; 5133 5134 /* Load firmware blob. */ 5135 blob = qla2x00_request_firmware(vha); 5136 if (!blob) { 5137 ql_log(ql_log_info, vha, 0x0083, 5138 "Fimware image unavailable.\n"); 5139 ql_log(ql_log_info, vha, 0x0084, 5140 "Firmware images can be retrieved from: "QLA_FW_URL ".\n"); 5141 return QLA_FUNCTION_FAILED; 5142 } 5143 5144 rval = QLA_SUCCESS; 5145 5146 wcode = (uint16_t *)req->ring; 5147 *srisc_addr = 0; 5148 fwcode = (uint16_t *)blob->fw->data; 5149 fwclen = 0; 5150 5151 /* Validate firmware image by checking version. */ 5152 if (blob->fw->size < 8 * sizeof(uint16_t)) { 5153 ql_log(ql_log_fatal, vha, 0x0085, 5154 "Unable to verify integrity of firmware image (%Zd).\n", 5155 blob->fw->size); 5156 goto fail_fw_integrity; 5157 } 5158 for (i = 0; i < 4; i++) 5159 wcode[i] = be16_to_cpu(fwcode[i + 4]); 5160 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff && 5161 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 && 5162 wcode[2] == 0 && wcode[3] == 0)) { 5163 ql_log(ql_log_fatal, vha, 0x0086, 5164 "Unable to verify integrity of firmware image.\n"); 5165 ql_log(ql_log_fatal, vha, 0x0087, 5166 "Firmware data: %04x %04x %04x %04x.\n", 5167 wcode[0], wcode[1], wcode[2], wcode[3]); 5168 goto fail_fw_integrity; 5169 } 5170 5171 seg = blob->segs; 5172 while (*seg && rval == QLA_SUCCESS) { 5173 risc_addr = *seg; 5174 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr; 5175 risc_size = be16_to_cpu(fwcode[3]); 5176 5177 /* Validate firmware image size. */ 5178 fwclen += risc_size * sizeof(uint16_t); 5179 if (blob->fw->size < fwclen) { 5180 ql_log(ql_log_fatal, vha, 0x0088, 5181 "Unable to verify integrity of firmware image " 5182 "(%Zd).\n", blob->fw->size); 5183 goto fail_fw_integrity; 5184 } 5185 5186 fragment = 0; 5187 while (risc_size > 0 && rval == QLA_SUCCESS) { 5188 wlen = (uint16_t)(ha->fw_transfer_size >> 1); 5189 if (wlen > risc_size) 5190 wlen = risc_size; 5191 ql_dbg(ql_dbg_init, vha, 0x0089, 5192 "Loading risc segment@ risc addr %x number of " 5193 "words 0x%x.\n", risc_addr, wlen); 5194 5195 for (i = 0; i < wlen; i++) 5196 wcode[i] = swab16(fwcode[i]); 5197 5198 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 5199 wlen); 5200 if (rval) { 5201 ql_log(ql_log_fatal, vha, 0x008a, 5202 "Failed to load segment %d of firmware.\n", 5203 fragment); 5204 break; 5205 } 5206 5207 fwcode += wlen; 5208 risc_addr += wlen; 5209 risc_size -= wlen; 5210 fragment++; 5211 } 5212 5213 /* Next segment. */ 5214 seg++; 5215 } 5216 return rval; 5217 5218 fail_fw_integrity: 5219 return QLA_FUNCTION_FAILED; 5220 } 5221 5222 static int 5223 qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) 5224 { 5225 int rval; 5226 int segments, fragment; 5227 uint32_t *dcode, dlen; 5228 uint32_t risc_addr; 5229 uint32_t risc_size; 5230 uint32_t i; 5231 struct fw_blob *blob; 5232 uint32_t *fwcode, fwclen; 5233 struct qla_hw_data *ha = vha->hw; 5234 struct req_que *req = ha->req_q_map[0]; 5235 5236 /* Load firmware blob. */ 5237 blob = qla2x00_request_firmware(vha); 5238 if (!blob) { 5239 ql_log(ql_log_warn, vha, 0x0090, 5240 "Fimware image unavailable.\n"); 5241 ql_log(ql_log_warn, vha, 0x0091, 5242 "Firmware images can be retrieved from: " 5243 QLA_FW_URL ".\n"); 5244 5245 return QLA_FUNCTION_FAILED; 5246 } 5247 5248 ql_dbg(ql_dbg_init, vha, 0x0092, 5249 "FW: Loading via request-firmware.\n"); 5250 5251 rval = QLA_SUCCESS; 5252 5253 segments = FA_RISC_CODE_SEGMENTS; 5254 dcode = (uint32_t *)req->ring; 5255 *srisc_addr = 0; 5256 fwcode = (uint32_t *)blob->fw->data; 5257 fwclen = 0; 5258 5259 /* Validate firmware image by checking version. */ 5260 if (blob->fw->size < 8 * sizeof(uint32_t)) { 5261 ql_log(ql_log_fatal, vha, 0x0093, 5262 "Unable to verify integrity of firmware image (%Zd).\n", 5263 blob->fw->size); 5264 goto fail_fw_integrity; 5265 } 5266 for (i = 0; i < 4; i++) 5267 dcode[i] = be32_to_cpu(fwcode[i + 4]); 5268 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 5269 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 5270 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 5271 dcode[3] == 0)) { 5272 ql_log(ql_log_fatal, vha, 0x0094, 5273 "Unable to verify integrity of firmware image (%Zd).\n", 5274 blob->fw->size); 5275 ql_log(ql_log_fatal, vha, 0x0095, 5276 "Firmware data: %08x %08x %08x %08x.\n", 5277 dcode[0], dcode[1], dcode[2], dcode[3]); 5278 goto fail_fw_integrity; 5279 } 5280 5281 while (segments && rval == QLA_SUCCESS) { 5282 risc_addr = be32_to_cpu(fwcode[2]); 5283 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; 5284 risc_size = be32_to_cpu(fwcode[3]); 5285 5286 /* Validate firmware image size. */ 5287 fwclen += risc_size * sizeof(uint32_t); 5288 if (blob->fw->size < fwclen) { 5289 ql_log(ql_log_fatal, vha, 0x0096, 5290 "Unable to verify integrity of firmware image " 5291 "(%Zd).\n", blob->fw->size); 5292 5293 goto fail_fw_integrity; 5294 } 5295 5296 fragment = 0; 5297 while (risc_size > 0 && rval == QLA_SUCCESS) { 5298 dlen = (uint32_t)(ha->fw_transfer_size >> 2); 5299 if (dlen > risc_size) 5300 dlen = risc_size; 5301 5302 ql_dbg(ql_dbg_init, vha, 0x0097, 5303 "Loading risc segment@ risc addr %x " 5304 "number of dwords 0x%x.\n", risc_addr, dlen); 5305 5306 for (i = 0; i < dlen; i++) 5307 dcode[i] = swab32(fwcode[i]); 5308 5309 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 5310 dlen); 5311 if (rval) { 5312 ql_log(ql_log_fatal, vha, 0x0098, 5313 "Failed to load segment %d of firmware.\n", 5314 fragment); 5315 break; 5316 } 5317 5318 fwcode += dlen; 5319 risc_addr += dlen; 5320 risc_size -= dlen; 5321 fragment++; 5322 } 5323 5324 /* Next segment. */ 5325 segments--; 5326 } 5327 return rval; 5328 5329 fail_fw_integrity: 5330 return QLA_FUNCTION_FAILED; 5331 } 5332 5333 int 5334 qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 5335 { 5336 int rval; 5337 5338 if (ql2xfwloadbin == 1) 5339 return qla81xx_load_risc(vha, srisc_addr); 5340 5341 /* 5342 * FW Load priority: 5343 * 1) Firmware via request-firmware interface (.bin file). 5344 * 2) Firmware residing in flash. 5345 */ 5346 rval = qla24xx_load_risc_blob(vha, srisc_addr); 5347 if (rval == QLA_SUCCESS) 5348 return rval; 5349 5350 return qla24xx_load_risc_flash(vha, srisc_addr, 5351 vha->hw->flt_region_fw); 5352 } 5353 5354 int 5355 qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 5356 { 5357 int rval; 5358 struct qla_hw_data *ha = vha->hw; 5359 5360 if (ql2xfwloadbin == 2) 5361 goto try_blob_fw; 5362 5363 /* 5364 * FW Load priority: 5365 * 1) Firmware residing in flash. 5366 * 2) Firmware via request-firmware interface (.bin file). 5367 * 3) Golden-Firmware residing in flash -- limited operation. 5368 */ 5369 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw); 5370 if (rval == QLA_SUCCESS) 5371 return rval; 5372 5373 try_blob_fw: 5374 rval = qla24xx_load_risc_blob(vha, srisc_addr); 5375 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw) 5376 return rval; 5377 5378 ql_log(ql_log_info, vha, 0x0099, 5379 "Attempting to fallback to golden firmware.\n"); 5380 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw); 5381 if (rval != QLA_SUCCESS) 5382 return rval; 5383 5384 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n"); 5385 ha->flags.running_gold_fw = 1; 5386 return rval; 5387 } 5388 5389 void 5390 qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) 5391 { 5392 int ret, retries; 5393 struct qla_hw_data *ha = vha->hw; 5394 5395 if (ha->flags.pci_channel_io_perm_failure) 5396 return; 5397 if (!IS_FWI2_CAPABLE(ha)) 5398 return; 5399 if (!ha->fw_major_version) 5400 return; 5401 5402 ret = qla2x00_stop_firmware(vha); 5403 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT && 5404 ret != QLA_INVALID_COMMAND && retries ; retries--) { 5405 ha->isp_ops->reset_chip(vha); 5406 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS) 5407 continue; 5408 if (qla2x00_setup_chip(vha) != QLA_SUCCESS) 5409 continue; 5410 ql_log(ql_log_info, vha, 0x8015, 5411 "Attempting retry of stop-firmware command.\n"); 5412 ret = qla2x00_stop_firmware(vha); 5413 } 5414 } 5415 5416 int 5417 qla24xx_configure_vhba(scsi_qla_host_t *vha) 5418 { 5419 int rval = QLA_SUCCESS; 5420 int rval2; 5421 uint16_t mb[MAILBOX_REGISTER_COUNT]; 5422 struct qla_hw_data *ha = vha->hw; 5423 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 5424 struct req_que *req; 5425 struct rsp_que *rsp; 5426 5427 if (!vha->vp_idx) 5428 return -EINVAL; 5429 5430 rval = qla2x00_fw_ready(base_vha); 5431 if (ha->flags.cpu_affinity_enabled) 5432 req = ha->req_q_map[0]; 5433 else 5434 req = vha->req; 5435 rsp = req->rsp; 5436 5437 if (rval == QLA_SUCCESS) { 5438 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5439 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); 5440 } 5441 5442 vha->flags.management_server_logged_in = 0; 5443 5444 /* Login to SNS first */ 5445 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, 5446 BIT_1); 5447 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 5448 if (rval2 == QLA_MEMORY_ALLOC_FAILED) 5449 ql_dbg(ql_dbg_init, vha, 0x0120, 5450 "Failed SNS login: loop_id=%x, rval2=%d\n", 5451 NPH_SNS, rval2); 5452 else 5453 ql_dbg(ql_dbg_init, vha, 0x0103, 5454 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x " 5455 "mb[2]=%x mb[6]=%x mb[7]=%x.\n", 5456 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]); 5457 return (QLA_FUNCTION_FAILED); 5458 } 5459 5460 atomic_set(&vha->loop_down_timer, 0); 5461 atomic_set(&vha->loop_state, LOOP_UP); 5462 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5463 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5464 rval = qla2x00_loop_resync(base_vha); 5465 5466 return rval; 5467 } 5468 5469 /* 84XX Support **************************************************************/ 5470 5471 static LIST_HEAD(qla_cs84xx_list); 5472 static DEFINE_MUTEX(qla_cs84xx_mutex); 5473 5474 static struct qla_chip_state_84xx * 5475 qla84xx_get_chip(struct scsi_qla_host *vha) 5476 { 5477 struct qla_chip_state_84xx *cs84xx; 5478 struct qla_hw_data *ha = vha->hw; 5479 5480 mutex_lock(&qla_cs84xx_mutex); 5481 5482 /* Find any shared 84xx chip. */ 5483 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) { 5484 if (cs84xx->bus == ha->pdev->bus) { 5485 kref_get(&cs84xx->kref); 5486 goto done; 5487 } 5488 } 5489 5490 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL); 5491 if (!cs84xx) 5492 goto done; 5493 5494 kref_init(&cs84xx->kref); 5495 spin_lock_init(&cs84xx->access_lock); 5496 mutex_init(&cs84xx->fw_update_mutex); 5497 cs84xx->bus = ha->pdev->bus; 5498 5499 list_add_tail(&cs84xx->list, &qla_cs84xx_list); 5500 done: 5501 mutex_unlock(&qla_cs84xx_mutex); 5502 return cs84xx; 5503 } 5504 5505 static void 5506 __qla84xx_chip_release(struct kref *kref) 5507 { 5508 struct qla_chip_state_84xx *cs84xx = 5509 container_of(kref, struct qla_chip_state_84xx, kref); 5510 5511 mutex_lock(&qla_cs84xx_mutex); 5512 list_del(&cs84xx->list); 5513 mutex_unlock(&qla_cs84xx_mutex); 5514 kfree(cs84xx); 5515 } 5516 5517 void 5518 qla84xx_put_chip(struct scsi_qla_host *vha) 5519 { 5520 struct qla_hw_data *ha = vha->hw; 5521 if (ha->cs84xx) 5522 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release); 5523 } 5524 5525 static int 5526 qla84xx_init_chip(scsi_qla_host_t *vha) 5527 { 5528 int rval; 5529 uint16_t status[2]; 5530 struct qla_hw_data *ha = vha->hw; 5531 5532 mutex_lock(&ha->cs84xx->fw_update_mutex); 5533 5534 rval = qla84xx_verify_chip(vha, status); 5535 5536 mutex_unlock(&ha->cs84xx->fw_update_mutex); 5537 5538 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED: 5539 QLA_SUCCESS; 5540 } 5541 5542 /* 81XX Support **************************************************************/ 5543 5544 int 5545 qla81xx_nvram_config(scsi_qla_host_t *vha) 5546 { 5547 int rval; 5548 struct init_cb_81xx *icb; 5549 struct nvram_81xx *nv; 5550 uint32_t *dptr; 5551 uint8_t *dptr1, *dptr2; 5552 uint32_t chksum; 5553 uint16_t cnt; 5554 struct qla_hw_data *ha = vha->hw; 5555 5556 rval = QLA_SUCCESS; 5557 icb = (struct init_cb_81xx *)ha->init_cb; 5558 nv = ha->nvram; 5559 5560 /* Determine NVRAM starting address. */ 5561 ha->nvram_size = sizeof(struct nvram_81xx); 5562 ha->vpd_size = FA_NVRAM_VPD_SIZE; 5563 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 5564 ha->vpd_size = FA_VPD_SIZE_82XX; 5565 5566 /* Get VPD data into cache */ 5567 ha->vpd = ha->nvram + VPD_OFFSET; 5568 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2, 5569 ha->vpd_size); 5570 5571 /* Get NVRAM data into cache and calculate checksum. */ 5572 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2, 5573 ha->nvram_size); 5574 dptr = (uint32_t *)nv; 5575 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) 5576 chksum += le32_to_cpu(*dptr++); 5577 5578 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111, 5579 "Contents of NVRAM:\n"); 5580 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112, 5581 (uint8_t *)nv, ha->nvram_size); 5582 5583 /* Bad NVRAM data, set defaults parameters. */ 5584 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' 5585 || nv->id[3] != ' ' || 5586 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) { 5587 /* Reset NVRAM data. */ 5588 ql_log(ql_log_info, vha, 0x0073, 5589 "Inconsistent NVRAM detected: checksum=0x%x id=%c " 5590 "version=0x%x.\n", chksum, nv->id[0], 5591 le16_to_cpu(nv->nvram_version)); 5592 ql_log(ql_log_info, vha, 0x0074, 5593 "Falling back to functioning (yet invalid -- WWPN) " 5594 "defaults.\n"); 5595 5596 /* 5597 * Set default initialization control block. 5598 */ 5599 memset(nv, 0, ha->nvram_size); 5600 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION); 5601 nv->version = __constant_cpu_to_le16(ICB_VERSION); 5602 nv->frame_payload_size = __constant_cpu_to_le16(2048); 5603 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF); 5604 nv->exchange_count = __constant_cpu_to_le16(0); 5605 nv->port_name[0] = 0x21; 5606 nv->port_name[1] = 0x00 + ha->port_no; 5607 nv->port_name[2] = 0x00; 5608 nv->port_name[3] = 0xe0; 5609 nv->port_name[4] = 0x8b; 5610 nv->port_name[5] = 0x1c; 5611 nv->port_name[6] = 0x55; 5612 nv->port_name[7] = 0x86; 5613 nv->node_name[0] = 0x20; 5614 nv->node_name[1] = 0x00; 5615 nv->node_name[2] = 0x00; 5616 nv->node_name[3] = 0xe0; 5617 nv->node_name[4] = 0x8b; 5618 nv->node_name[5] = 0x1c; 5619 nv->node_name[6] = 0x55; 5620 nv->node_name[7] = 0x86; 5621 nv->login_retry_count = __constant_cpu_to_le16(8); 5622 nv->interrupt_delay_timer = __constant_cpu_to_le16(0); 5623 nv->login_timeout = __constant_cpu_to_le16(0); 5624 nv->firmware_options_1 = 5625 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 5626 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4); 5627 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12); 5628 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13); 5629 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10); 5630 nv->efi_parameters = __constant_cpu_to_le32(0); 5631 nv->reset_delay = 5; 5632 nv->max_luns_per_target = __constant_cpu_to_le16(128); 5633 nv->port_down_retry_count = __constant_cpu_to_le16(30); 5634 nv->link_down_timeout = __constant_cpu_to_le16(180); 5635 nv->enode_mac[0] = 0x00; 5636 nv->enode_mac[1] = 0xC0; 5637 nv->enode_mac[2] = 0xDD; 5638 nv->enode_mac[3] = 0x04; 5639 nv->enode_mac[4] = 0x05; 5640 nv->enode_mac[5] = 0x06 + ha->port_no; 5641 5642 rval = 1; 5643 } 5644 5645 if (IS_T10_PI_CAPABLE(ha)) 5646 nv->frame_payload_size &= ~7; 5647 5648 qlt_81xx_config_nvram_stage1(vha, nv); 5649 5650 /* Reset Initialization control block */ 5651 memset(icb, 0, ha->init_cb_size); 5652 5653 /* Copy 1st segment. */ 5654 dptr1 = (uint8_t *)icb; 5655 dptr2 = (uint8_t *)&nv->version; 5656 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 5657 while (cnt--) 5658 *dptr1++ = *dptr2++; 5659 5660 icb->login_retry_count = nv->login_retry_count; 5661 5662 /* Copy 2nd segment. */ 5663 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 5664 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 5665 cnt = (uint8_t *)&icb->reserved_5 - 5666 (uint8_t *)&icb->interrupt_delay_timer; 5667 while (cnt--) 5668 *dptr1++ = *dptr2++; 5669 5670 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac)); 5671 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */ 5672 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) { 5673 icb->enode_mac[0] = 0x00; 5674 icb->enode_mac[1] = 0xC0; 5675 icb->enode_mac[2] = 0xDD; 5676 icb->enode_mac[3] = 0x04; 5677 icb->enode_mac[4] = 0x05; 5678 icb->enode_mac[5] = 0x06 + ha->port_no; 5679 } 5680 5681 /* Use extended-initialization control block. */ 5682 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb)); 5683 5684 /* 5685 * Setup driver NVRAM options. 5686 */ 5687 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 5688 "QLE8XXX"); 5689 5690 qlt_81xx_config_nvram_stage2(vha, icb); 5691 5692 /* Use alternate WWN? */ 5693 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) { 5694 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 5695 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 5696 } 5697 5698 /* Prepare nodename */ 5699 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) { 5700 /* 5701 * Firmware will apply the following mask if the nodename was 5702 * not provided. 5703 */ 5704 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 5705 icb->node_name[0] &= 0xF0; 5706 } 5707 5708 /* Set host adapter parameters. */ 5709 ha->flags.disable_risc_code_load = 0; 5710 ha->flags.enable_lip_reset = 0; 5711 ha->flags.enable_lip_full_login = 5712 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; 5713 ha->flags.enable_target_reset = 5714 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; 5715 ha->flags.enable_led_scheme = 0; 5716 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; 5717 5718 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 5719 (BIT_6 | BIT_5 | BIT_4)) >> 4; 5720 5721 /* save HBA serial number */ 5722 ha->serial0 = icb->port_name[5]; 5723 ha->serial1 = icb->port_name[6]; 5724 ha->serial2 = icb->port_name[7]; 5725 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 5726 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 5727 5728 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); 5729 5730 ha->retry_count = le16_to_cpu(nv->login_retry_count); 5731 5732 /* Set minimum login_timeout to 4 seconds. */ 5733 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 5734 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 5735 if (le16_to_cpu(nv->login_timeout) < 4) 5736 nv->login_timeout = __constant_cpu_to_le16(4); 5737 ha->login_timeout = le16_to_cpu(nv->login_timeout); 5738 icb->login_timeout = nv->login_timeout; 5739 5740 /* Set minimum RATOV to 100 tenths of a second. */ 5741 ha->r_a_tov = 100; 5742 5743 ha->loop_reset_delay = nv->reset_delay; 5744 5745 /* Link Down Timeout = 0: 5746 * 5747 * When Port Down timer expires we will start returning 5748 * I/O's to OS with "DID_NO_CONNECT". 5749 * 5750 * Link Down Timeout != 0: 5751 * 5752 * The driver waits for the link to come up after link down 5753 * before returning I/Os to OS with "DID_NO_CONNECT". 5754 */ 5755 if (le16_to_cpu(nv->link_down_timeout) == 0) { 5756 ha->loop_down_abort_time = 5757 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 5758 } else { 5759 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 5760 ha->loop_down_abort_time = 5761 (LOOP_DOWN_TIME - ha->link_down_timeout); 5762 } 5763 5764 /* Need enough time to try and get the port back. */ 5765 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 5766 if (qlport_down_retry) 5767 ha->port_down_retry_count = qlport_down_retry; 5768 5769 /* Set login_retry_count */ 5770 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 5771 if (ha->port_down_retry_count == 5772 le16_to_cpu(nv->port_down_retry_count) && 5773 ha->port_down_retry_count > 3) 5774 ha->login_retry_count = ha->port_down_retry_count; 5775 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 5776 ha->login_retry_count = ha->port_down_retry_count; 5777 if (ql2xloginretrycount) 5778 ha->login_retry_count = ql2xloginretrycount; 5779 5780 /* if not running MSI-X we need handshaking on interrupts */ 5781 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha)) 5782 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22); 5783 5784 /* Enable ZIO. */ 5785 if (!vha->flags.init_done) { 5786 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 5787 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 5788 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 5789 le16_to_cpu(icb->interrupt_delay_timer): 2; 5790 } 5791 icb->firmware_options_2 &= __constant_cpu_to_le32( 5792 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 5793 vha->flags.process_response_queue = 0; 5794 if (ha->zio_mode != QLA_ZIO_DISABLED) { 5795 ha->zio_mode = QLA_ZIO_MODE_6; 5796 5797 ql_log(ql_log_info, vha, 0x0075, 5798 "ZIO mode %d enabled; timer delay (%d us).\n", 5799 ha->zio_mode, 5800 ha->zio_timer * 100); 5801 5802 icb->firmware_options_2 |= cpu_to_le32( 5803 (uint32_t)ha->zio_mode); 5804 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 5805 vha->flags.process_response_queue = 1; 5806 } 5807 5808 if (rval) { 5809 ql_log(ql_log_warn, vha, 0x0076, 5810 "NVRAM configuration failed.\n"); 5811 } 5812 return (rval); 5813 } 5814 5815 int 5816 qla82xx_restart_isp(scsi_qla_host_t *vha) 5817 { 5818 int status, rval; 5819 uint32_t wait_time; 5820 struct qla_hw_data *ha = vha->hw; 5821 struct req_que *req = ha->req_q_map[0]; 5822 struct rsp_que *rsp = ha->rsp_q_map[0]; 5823 struct scsi_qla_host *vp; 5824 unsigned long flags; 5825 5826 status = qla2x00_init_rings(vha); 5827 if (!status) { 5828 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5829 ha->flags.chip_reset_done = 1; 5830 5831 status = qla2x00_fw_ready(vha); 5832 if (!status) { 5833 ql_log(ql_log_info, vha, 0x803c, 5834 "Start configure loop, status =%d.\n", status); 5835 5836 /* Issue a marker after FW becomes ready. */ 5837 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); 5838 5839 vha->flags.online = 1; 5840 /* Wait at most MAX_TARGET RSCNs for a stable link. */ 5841 wait_time = 256; 5842 do { 5843 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5844 qla2x00_configure_loop(vha); 5845 wait_time--; 5846 } while (!atomic_read(&vha->loop_down_timer) && 5847 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) && 5848 wait_time && 5849 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))); 5850 } 5851 5852 /* if no cable then assume it's good */ 5853 if ((vha->device_flags & DFLG_NO_CABLE)) 5854 status = 0; 5855 5856 ql_log(ql_log_info, vha, 0x8000, 5857 "Configure loop done, status = 0x%x.\n", status); 5858 } 5859 5860 if (!status) { 5861 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5862 5863 if (!atomic_read(&vha->loop_down_timer)) { 5864 /* 5865 * Issue marker command only when we are going 5866 * to start the I/O . 5867 */ 5868 vha->marker_needed = 1; 5869 } 5870 5871 vha->flags.online = 1; 5872 5873 ha->isp_ops->enable_intrs(ha); 5874 5875 ha->isp_abort_cnt = 0; 5876 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 5877 5878 /* Update the firmware version */ 5879 status = qla82xx_check_md_needed(vha); 5880 5881 if (ha->fce) { 5882 ha->flags.fce_enabled = 1; 5883 memset(ha->fce, 0, 5884 fce_calc_size(ha->fce_bufs)); 5885 rval = qla2x00_enable_fce_trace(vha, 5886 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 5887 &ha->fce_bufs); 5888 if (rval) { 5889 ql_log(ql_log_warn, vha, 0x8001, 5890 "Unable to reinitialize FCE (%d).\n", 5891 rval); 5892 ha->flags.fce_enabled = 0; 5893 } 5894 } 5895 5896 if (ha->eft) { 5897 memset(ha->eft, 0, EFT_SIZE); 5898 rval = qla2x00_enable_eft_trace(vha, 5899 ha->eft_dma, EFT_NUM_BUFFERS); 5900 if (rval) { 5901 ql_log(ql_log_warn, vha, 0x8010, 5902 "Unable to reinitialize EFT (%d).\n", 5903 rval); 5904 } 5905 } 5906 } 5907 5908 if (!status) { 5909 ql_dbg(ql_dbg_taskm, vha, 0x8011, 5910 "qla82xx_restart_isp succeeded.\n"); 5911 5912 spin_lock_irqsave(&ha->vport_slock, flags); 5913 list_for_each_entry(vp, &ha->vp_list, list) { 5914 if (vp->vp_idx) { 5915 atomic_inc(&vp->vref_count); 5916 spin_unlock_irqrestore(&ha->vport_slock, flags); 5917 5918 qla2x00_vp_abort_isp(vp); 5919 5920 spin_lock_irqsave(&ha->vport_slock, flags); 5921 atomic_dec(&vp->vref_count); 5922 } 5923 } 5924 spin_unlock_irqrestore(&ha->vport_slock, flags); 5925 5926 } else { 5927 ql_log(ql_log_warn, vha, 0x8016, 5928 "qla82xx_restart_isp **** FAILED ****.\n"); 5929 } 5930 5931 return status; 5932 } 5933 5934 void 5935 qla81xx_update_fw_options(scsi_qla_host_t *vha) 5936 { 5937 struct qla_hw_data *ha = vha->hw; 5938 5939 if (!ql2xetsenable) 5940 return; 5941 5942 /* Enable ETS Burst. */ 5943 memset(ha->fw_options, 0, sizeof(ha->fw_options)); 5944 ha->fw_options[2] |= BIT_9; 5945 qla2x00_set_fw_options(vha, ha->fw_options); 5946 } 5947 5948 /* 5949 * qla24xx_get_fcp_prio 5950 * Gets the fcp cmd priority value for the logged in port. 5951 * Looks for a match of the port descriptors within 5952 * each of the fcp prio config entries. If a match is found, 5953 * the tag (priority) value is returned. 5954 * 5955 * Input: 5956 * vha = scsi host structure pointer. 5957 * fcport = port structure pointer. 5958 * 5959 * Return: 5960 * non-zero (if found) 5961 * -1 (if not found) 5962 * 5963 * Context: 5964 * Kernel context 5965 */ 5966 static int 5967 qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 5968 { 5969 int i, entries; 5970 uint8_t pid_match, wwn_match; 5971 int priority; 5972 uint32_t pid1, pid2; 5973 uint64_t wwn1, wwn2; 5974 struct qla_fcp_prio_entry *pri_entry; 5975 struct qla_hw_data *ha = vha->hw; 5976 5977 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled) 5978 return -1; 5979 5980 priority = -1; 5981 entries = ha->fcp_prio_cfg->num_entries; 5982 pri_entry = &ha->fcp_prio_cfg->entry[0]; 5983 5984 for (i = 0; i < entries; i++) { 5985 pid_match = wwn_match = 0; 5986 5987 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) { 5988 pri_entry++; 5989 continue; 5990 } 5991 5992 /* check source pid for a match */ 5993 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) { 5994 pid1 = pri_entry->src_pid & INVALID_PORT_ID; 5995 pid2 = vha->d_id.b24 & INVALID_PORT_ID; 5996 if (pid1 == INVALID_PORT_ID) 5997 pid_match++; 5998 else if (pid1 == pid2) 5999 pid_match++; 6000 } 6001 6002 /* check destination pid for a match */ 6003 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) { 6004 pid1 = pri_entry->dst_pid & INVALID_PORT_ID; 6005 pid2 = fcport->d_id.b24 & INVALID_PORT_ID; 6006 if (pid1 == INVALID_PORT_ID) 6007 pid_match++; 6008 else if (pid1 == pid2) 6009 pid_match++; 6010 } 6011 6012 /* check source WWN for a match */ 6013 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) { 6014 wwn1 = wwn_to_u64(vha->port_name); 6015 wwn2 = wwn_to_u64(pri_entry->src_wwpn); 6016 if (wwn2 == (uint64_t)-1) 6017 wwn_match++; 6018 else if (wwn1 == wwn2) 6019 wwn_match++; 6020 } 6021 6022 /* check destination WWN for a match */ 6023 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) { 6024 wwn1 = wwn_to_u64(fcport->port_name); 6025 wwn2 = wwn_to_u64(pri_entry->dst_wwpn); 6026 if (wwn2 == (uint64_t)-1) 6027 wwn_match++; 6028 else if (wwn1 == wwn2) 6029 wwn_match++; 6030 } 6031 6032 if (pid_match == 2 || wwn_match == 2) { 6033 /* Found a matching entry */ 6034 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID) 6035 priority = pri_entry->tag; 6036 break; 6037 } 6038 6039 pri_entry++; 6040 } 6041 6042 return priority; 6043 } 6044 6045 /* 6046 * qla24xx_update_fcport_fcp_prio 6047 * Activates fcp priority for the logged in fc port 6048 * 6049 * Input: 6050 * vha = scsi host structure pointer. 6051 * fcp = port structure pointer. 6052 * 6053 * Return: 6054 * QLA_SUCCESS or QLA_FUNCTION_FAILED 6055 * 6056 * Context: 6057 * Kernel context. 6058 */ 6059 int 6060 qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 6061 { 6062 int ret; 6063 int priority; 6064 uint16_t mb[5]; 6065 6066 if (fcport->port_type != FCT_TARGET || 6067 fcport->loop_id == FC_NO_LOOP_ID) 6068 return QLA_FUNCTION_FAILED; 6069 6070 priority = qla24xx_get_fcp_prio(vha, fcport); 6071 if (priority < 0) 6072 return QLA_FUNCTION_FAILED; 6073 6074 if (IS_P3P_TYPE(vha->hw)) { 6075 fcport->fcp_prio = priority & 0xf; 6076 return QLA_SUCCESS; 6077 } 6078 6079 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb); 6080 if (ret == QLA_SUCCESS) { 6081 if (fcport->fcp_prio != priority) 6082 ql_dbg(ql_dbg_user, vha, 0x709e, 6083 "Updated FCP_CMND priority - value=%d loop_id=%d " 6084 "port_id=%02x%02x%02x.\n", priority, 6085 fcport->loop_id, fcport->d_id.b.domain, 6086 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6087 fcport->fcp_prio = priority & 0xf; 6088 } else 6089 ql_dbg(ql_dbg_user, vha, 0x704f, 6090 "Unable to update FCP_CMND priority - ret=0x%x for " 6091 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id, 6092 fcport->d_id.b.domain, fcport->d_id.b.area, 6093 fcport->d_id.b.al_pa); 6094 return ret; 6095 } 6096 6097 /* 6098 * qla24xx_update_all_fcp_prio 6099 * Activates fcp priority for all the logged in ports 6100 * 6101 * Input: 6102 * ha = adapter block pointer. 6103 * 6104 * Return: 6105 * QLA_SUCCESS or QLA_FUNCTION_FAILED 6106 * 6107 * Context: 6108 * Kernel context. 6109 */ 6110 int 6111 qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha) 6112 { 6113 int ret; 6114 fc_port_t *fcport; 6115 6116 ret = QLA_FUNCTION_FAILED; 6117 /* We need to set priority for all logged in ports */ 6118 list_for_each_entry(fcport, &vha->vp_fcports, list) 6119 ret = qla24xx_update_fcport_fcp_prio(vha, fcport); 6120 6121 return ret; 6122 } 6123