1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 #include "qla_gbl.h" 8 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/vmalloc.h> 12 13 #include "qla_devtbl.h" 14 15 #ifdef CONFIG_SPARC 16 #include <asm/prom.h> 17 #endif 18 19 #include "qla_target.h" 20 21 /* 22 * QLogic ISP2x00 Hardware Support Function Prototypes. 23 */ 24 static int qla2x00_isp_firmware(scsi_qla_host_t *); 25 static int qla2x00_setup_chip(scsi_qla_host_t *); 26 static int qla2x00_fw_ready(scsi_qla_host_t *); 27 static int qla2x00_configure_hba(scsi_qla_host_t *); 28 static int qla2x00_configure_loop(scsi_qla_host_t *); 29 static int qla2x00_configure_local_loop(scsi_qla_host_t *); 30 static int qla2x00_configure_fabric(scsi_qla_host_t *); 31 static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *); 32 static int qla2x00_restart_isp(scsi_qla_host_t *); 33 34 static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *); 35 static int qla84xx_init_chip(scsi_qla_host_t *); 36 static int qla25xx_init_queues(struct qla_hw_data *); 37 static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *); 38 static void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, 39 struct event_arg *ea); 40 static void qla24xx_handle_prli_done_event(struct scsi_qla_host *, 41 struct event_arg *); 42 static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *); 43 44 /* SRB Extensions ---------------------------------------------------------- */ 45 46 void 47 qla2x00_sp_timeout(struct timer_list *t) 48 { 49 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer); 50 struct srb_iocb *iocb; 51 52 WARN_ON(irqs_disabled()); 53 iocb = &sp->u.iocb_cmd; 54 iocb->timeout(sp); 55 } 56 57 void qla2x00_sp_free(srb_t *sp) 58 { 59 struct srb_iocb *iocb = &sp->u.iocb_cmd; 60 61 del_timer(&iocb->timer); 62 qla2x00_rel_sp(sp); 63 } 64 65 void qla2xxx_rel_done_warning(srb_t *sp, int res) 66 { 67 WARN_ONCE(1, "Calling done() of an already freed srb %p object\n", sp); 68 } 69 70 void qla2xxx_rel_free_warning(srb_t *sp) 71 { 72 WARN_ONCE(1, "Calling free() of an already freed srb %p object\n", sp); 73 } 74 75 /* Asynchronous Login/Logout Routines -------------------------------------- */ 76 77 unsigned long 78 qla2x00_get_async_timeout(struct scsi_qla_host *vha) 79 { 80 unsigned long tmo; 81 struct qla_hw_data *ha = vha->hw; 82 83 /* Firmware should use switch negotiated r_a_tov for timeout. */ 84 tmo = ha->r_a_tov / 10 * 2; 85 if (IS_QLAFX00(ha)) { 86 tmo = FX00_DEF_RATOV * 2; 87 } else if (!IS_FWI2_CAPABLE(ha)) { 88 /* 89 * Except for earlier ISPs where the timeout is seeded from the 90 * initialization control block. 91 */ 92 tmo = ha->login_timeout; 93 } 94 return tmo; 95 } 96 97 static void qla24xx_abort_iocb_timeout(void *data) 98 { 99 srb_t *sp = data; 100 struct srb_iocb *abt = &sp->u.iocb_cmd; 101 struct qla_qpair *qpair = sp->qpair; 102 u32 handle; 103 unsigned long flags; 104 105 if (sp->cmd_sp) 106 ql_dbg(ql_dbg_async, sp->vha, 0x507c, 107 "Abort timeout - cmd hdl=%x, cmd type=%x hdl=%x, type=%x\n", 108 sp->cmd_sp->handle, sp->cmd_sp->type, 109 sp->handle, sp->type); 110 else 111 ql_dbg(ql_dbg_async, sp->vha, 0x507c, 112 "Abort timeout 2 - hdl=%x, type=%x\n", 113 sp->handle, sp->type); 114 115 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 116 for (handle = 1; handle < qpair->req->num_outstanding_cmds; handle++) { 117 if (sp->cmd_sp && (qpair->req->outstanding_cmds[handle] == 118 sp->cmd_sp)) 119 qpair->req->outstanding_cmds[handle] = NULL; 120 121 /* removing the abort */ 122 if (qpair->req->outstanding_cmds[handle] == sp) { 123 qpair->req->outstanding_cmds[handle] = NULL; 124 break; 125 } 126 } 127 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 128 129 if (sp->cmd_sp) 130 sp->cmd_sp->done(sp->cmd_sp, QLA_OS_TIMER_EXPIRED); 131 132 abt->u.abt.comp_status = cpu_to_le16(CS_TIMEOUT); 133 sp->done(sp, QLA_OS_TIMER_EXPIRED); 134 } 135 136 static void qla24xx_abort_sp_done(srb_t *sp, int res) 137 { 138 struct srb_iocb *abt = &sp->u.iocb_cmd; 139 srb_t *orig_sp = sp->cmd_sp; 140 141 if (orig_sp) 142 qla_wait_nvme_release_cmd_kref(orig_sp); 143 144 del_timer(&sp->u.iocb_cmd.timer); 145 if (sp->flags & SRB_WAKEUP_ON_COMP) 146 complete(&abt->u.abt.comp); 147 else 148 sp->free(sp); 149 } 150 151 int qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait) 152 { 153 scsi_qla_host_t *vha = cmd_sp->vha; 154 struct srb_iocb *abt_iocb; 155 srb_t *sp; 156 int rval = QLA_FUNCTION_FAILED; 157 158 sp = qla2xxx_get_qpair_sp(cmd_sp->vha, cmd_sp->qpair, cmd_sp->fcport, 159 GFP_ATOMIC); 160 if (!sp) 161 return rval; 162 163 abt_iocb = &sp->u.iocb_cmd; 164 sp->type = SRB_ABT_CMD; 165 sp->name = "abort"; 166 sp->qpair = cmd_sp->qpair; 167 sp->cmd_sp = cmd_sp; 168 if (wait) 169 sp->flags = SRB_WAKEUP_ON_COMP; 170 171 abt_iocb->timeout = qla24xx_abort_iocb_timeout; 172 init_completion(&abt_iocb->u.abt.comp); 173 /* FW can send 2 x ABTS's timeout/20s */ 174 qla2x00_init_timer(sp, 42); 175 176 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle; 177 abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id); 178 179 sp->done = qla24xx_abort_sp_done; 180 181 ql_dbg(ql_dbg_async, vha, 0x507c, 182 "Abort command issued - hdl=%x, type=%x\n", cmd_sp->handle, 183 cmd_sp->type); 184 185 rval = qla2x00_start_sp(sp); 186 if (rval != QLA_SUCCESS) { 187 sp->free(sp); 188 return rval; 189 } 190 191 if (wait) { 192 wait_for_completion(&abt_iocb->u.abt.comp); 193 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ? 194 QLA_SUCCESS : QLA_FUNCTION_FAILED; 195 sp->free(sp); 196 } 197 198 return rval; 199 } 200 201 void 202 qla2x00_async_iocb_timeout(void *data) 203 { 204 srb_t *sp = data; 205 fc_port_t *fcport = sp->fcport; 206 struct srb_iocb *lio = &sp->u.iocb_cmd; 207 int rc, h; 208 unsigned long flags; 209 210 if (fcport) { 211 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, 212 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n", 213 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name); 214 215 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 216 } else { 217 pr_info("Async-%s timeout - hdl=%x.\n", 218 sp->name, sp->handle); 219 } 220 221 switch (sp->type) { 222 case SRB_LOGIN_CMD: 223 rc = qla24xx_async_abort_cmd(sp, false); 224 if (rc) { 225 /* Retry as needed. */ 226 lio->u.logio.data[0] = MBS_COMMAND_ERROR; 227 lio->u.logio.data[1] = 228 lio->u.logio.flags & SRB_LOGIN_RETRIED ? 229 QLA_LOGIO_LOGIN_RETRIED : 0; 230 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 231 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; 232 h++) { 233 if (sp->qpair->req->outstanding_cmds[h] == 234 sp) { 235 sp->qpair->req->outstanding_cmds[h] = 236 NULL; 237 break; 238 } 239 } 240 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 241 sp->done(sp, QLA_FUNCTION_TIMEOUT); 242 } 243 break; 244 case SRB_LOGOUT_CMD: 245 case SRB_CT_PTHRU_CMD: 246 case SRB_MB_IOCB: 247 case SRB_NACK_PLOGI: 248 case SRB_NACK_PRLI: 249 case SRB_NACK_LOGO: 250 case SRB_CTRL_VP: 251 default: 252 rc = qla24xx_async_abort_cmd(sp, false); 253 if (rc) { 254 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 255 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; 256 h++) { 257 if (sp->qpair->req->outstanding_cmds[h] == 258 sp) { 259 sp->qpair->req->outstanding_cmds[h] = 260 NULL; 261 break; 262 } 263 } 264 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 265 sp->done(sp, QLA_FUNCTION_TIMEOUT); 266 } 267 break; 268 } 269 } 270 271 static void qla2x00_async_login_sp_done(srb_t *sp, int res) 272 { 273 struct scsi_qla_host *vha = sp->vha; 274 struct srb_iocb *lio = &sp->u.iocb_cmd; 275 struct event_arg ea; 276 277 ql_dbg(ql_dbg_disc, vha, 0x20dd, 278 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res); 279 280 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 281 282 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 283 memset(&ea, 0, sizeof(ea)); 284 ea.fcport = sp->fcport; 285 ea.data[0] = lio->u.logio.data[0]; 286 ea.data[1] = lio->u.logio.data[1]; 287 ea.iop[0] = lio->u.logio.iop[0]; 288 ea.iop[1] = lio->u.logio.iop[1]; 289 ea.sp = sp; 290 qla24xx_handle_plogi_done_event(vha, &ea); 291 } 292 293 sp->free(sp); 294 } 295 296 static inline bool 297 fcport_is_smaller(fc_port_t *fcport) 298 { 299 if (wwn_to_u64(fcport->port_name) < 300 wwn_to_u64(fcport->vha->port_name)) 301 return true; 302 else 303 return false; 304 } 305 306 static inline bool 307 fcport_is_bigger(fc_port_t *fcport) 308 { 309 return !fcport_is_smaller(fcport); 310 } 311 312 int 313 qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport, 314 uint16_t *data) 315 { 316 srb_t *sp; 317 struct srb_iocb *lio; 318 int rval = QLA_FUNCTION_FAILED; 319 320 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) || 321 fcport->loop_id == FC_NO_LOOP_ID) { 322 ql_log(ql_log_warn, vha, 0xffff, 323 "%s: %8phC - not sending command.\n", 324 __func__, fcport->port_name); 325 return rval; 326 } 327 328 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 329 if (!sp) 330 goto done; 331 332 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND); 333 fcport->flags |= FCF_ASYNC_SENT; 334 fcport->logout_completed = 0; 335 336 sp->type = SRB_LOGIN_CMD; 337 sp->name = "login"; 338 sp->gen1 = fcport->rscn_gen; 339 sp->gen2 = fcport->login_gen; 340 341 lio = &sp->u.iocb_cmd; 342 lio->timeout = qla2x00_async_iocb_timeout; 343 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 344 345 sp->done = qla2x00_async_login_sp_done; 346 if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport)) 347 lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY; 348 else 349 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI; 350 351 if (NVME_TARGET(vha->hw, fcport)) 352 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI; 353 354 ql_log(ql_log_warn, vha, 0x2072, 355 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x retries=%d.\n", 356 fcport->port_name, sp->handle, fcport->loop_id, 357 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa, 358 fcport->login_retry); 359 360 rval = qla2x00_start_sp(sp); 361 if (rval != QLA_SUCCESS) { 362 fcport->flags |= FCF_LOGIN_NEEDED; 363 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 364 goto done_free_sp; 365 } 366 367 return rval; 368 369 done_free_sp: 370 sp->free(sp); 371 fcport->flags &= ~FCF_ASYNC_SENT; 372 done: 373 fcport->flags &= ~FCF_ASYNC_ACTIVE; 374 return rval; 375 } 376 377 static void qla2x00_async_logout_sp_done(srb_t *sp, int res) 378 { 379 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 380 sp->fcport->login_gen++; 381 qlt_logo_completion_handler(sp->fcport, res); 382 sp->free(sp); 383 } 384 385 int 386 qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport) 387 { 388 srb_t *sp; 389 struct srb_iocb *lio; 390 int rval = QLA_FUNCTION_FAILED; 391 392 fcport->flags |= FCF_ASYNC_SENT; 393 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 394 if (!sp) 395 goto done; 396 397 sp->type = SRB_LOGOUT_CMD; 398 sp->name = "logout"; 399 400 lio = &sp->u.iocb_cmd; 401 lio->timeout = qla2x00_async_iocb_timeout; 402 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 403 404 sp->done = qla2x00_async_logout_sp_done; 405 406 ql_dbg(ql_dbg_disc, vha, 0x2070, 407 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n", 408 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 409 fcport->d_id.b.area, fcport->d_id.b.al_pa, 410 fcport->port_name); 411 412 rval = qla2x00_start_sp(sp); 413 if (rval != QLA_SUCCESS) 414 goto done_free_sp; 415 return rval; 416 417 done_free_sp: 418 sp->free(sp); 419 done: 420 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 421 return rval; 422 } 423 424 void 425 qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport, 426 uint16_t *data) 427 { 428 fcport->flags &= ~FCF_ASYNC_ACTIVE; 429 /* Don't re-login in target mode */ 430 if (!fcport->tgt_session) 431 qla2x00_mark_device_lost(vha, fcport, 1); 432 qlt_logo_completion_handler(fcport, data[0]); 433 } 434 435 static void qla2x00_async_prlo_sp_done(srb_t *sp, int res) 436 { 437 struct srb_iocb *lio = &sp->u.iocb_cmd; 438 struct scsi_qla_host *vha = sp->vha; 439 440 sp->fcport->flags &= ~FCF_ASYNC_ACTIVE; 441 if (!test_bit(UNLOADING, &vha->dpc_flags)) 442 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport, 443 lio->u.logio.data); 444 sp->free(sp); 445 } 446 447 int 448 qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport) 449 { 450 srb_t *sp; 451 struct srb_iocb *lio; 452 int rval; 453 454 rval = QLA_FUNCTION_FAILED; 455 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 456 if (!sp) 457 goto done; 458 459 sp->type = SRB_PRLO_CMD; 460 sp->name = "prlo"; 461 462 lio = &sp->u.iocb_cmd; 463 lio->timeout = qla2x00_async_iocb_timeout; 464 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 465 466 sp->done = qla2x00_async_prlo_sp_done; 467 468 ql_dbg(ql_dbg_disc, vha, 0x2070, 469 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 470 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 471 fcport->d_id.b.area, fcport->d_id.b.al_pa); 472 473 rval = qla2x00_start_sp(sp); 474 if (rval != QLA_SUCCESS) 475 goto done_free_sp; 476 477 return rval; 478 479 done_free_sp: 480 sp->free(sp); 481 done: 482 fcport->flags &= ~FCF_ASYNC_ACTIVE; 483 return rval; 484 } 485 486 static 487 void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea) 488 { 489 struct fc_port *fcport = ea->fcport; 490 491 ql_dbg(ql_dbg_disc, vha, 0x20d2, 492 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n", 493 __func__, fcport->port_name, fcport->disc_state, 494 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2, 495 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id); 496 497 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 498 ea->data[0]); 499 500 if (ea->data[0] != MBS_COMMAND_COMPLETE) { 501 ql_dbg(ql_dbg_disc, vha, 0x2066, 502 "%s %8phC: adisc fail: post delete\n", 503 __func__, ea->fcport->port_name); 504 /* deleted = 0 & logout_on_delete = force fw cleanup */ 505 fcport->deleted = 0; 506 fcport->logout_on_delete = 1; 507 qlt_schedule_sess_for_deletion(ea->fcport); 508 return; 509 } 510 511 if (ea->fcport->disc_state == DSC_DELETE_PEND) 512 return; 513 514 if (ea->sp->gen2 != ea->fcport->login_gen) { 515 /* target side must have changed it. */ 516 ql_dbg(ql_dbg_disc, vha, 0x20d3, 517 "%s %8phC generation changed\n", 518 __func__, ea->fcport->port_name); 519 return; 520 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) { 521 qla_rscn_replay(fcport); 522 qlt_schedule_sess_for_deletion(fcport); 523 return; 524 } 525 526 __qla24xx_handle_gpdb_event(vha, ea); 527 } 528 529 static int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport) 530 { 531 struct qla_work_evt *e; 532 533 e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI); 534 if (!e) 535 return QLA_FUNCTION_FAILED; 536 537 e->u.fcport.fcport = fcport; 538 fcport->flags |= FCF_ASYNC_ACTIVE; 539 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND); 540 return qla2x00_post_work(vha, e); 541 } 542 543 static void qla2x00_async_adisc_sp_done(srb_t *sp, int res) 544 { 545 struct scsi_qla_host *vha = sp->vha; 546 struct event_arg ea; 547 struct srb_iocb *lio = &sp->u.iocb_cmd; 548 549 ql_dbg(ql_dbg_disc, vha, 0x2066, 550 "Async done-%s res %x %8phC\n", 551 sp->name, res, sp->fcport->port_name); 552 553 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 554 555 memset(&ea, 0, sizeof(ea)); 556 ea.rc = res; 557 ea.data[0] = lio->u.logio.data[0]; 558 ea.data[1] = lio->u.logio.data[1]; 559 ea.iop[0] = lio->u.logio.iop[0]; 560 ea.iop[1] = lio->u.logio.iop[1]; 561 ea.fcport = sp->fcport; 562 ea.sp = sp; 563 564 qla24xx_handle_adisc_event(vha, &ea); 565 566 sp->free(sp); 567 } 568 569 int 570 qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport, 571 uint16_t *data) 572 { 573 srb_t *sp; 574 struct srb_iocb *lio; 575 int rval = QLA_FUNCTION_FAILED; 576 577 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT)) 578 return rval; 579 580 fcport->flags |= FCF_ASYNC_SENT; 581 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 582 if (!sp) 583 goto done; 584 585 sp->type = SRB_ADISC_CMD; 586 sp->name = "adisc"; 587 588 lio = &sp->u.iocb_cmd; 589 lio->timeout = qla2x00_async_iocb_timeout; 590 sp->gen1 = fcport->rscn_gen; 591 sp->gen2 = fcport->login_gen; 592 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 593 594 sp->done = qla2x00_async_adisc_sp_done; 595 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 596 lio->u.logio.flags |= SRB_LOGIN_RETRIED; 597 598 ql_dbg(ql_dbg_disc, vha, 0x206f, 599 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n", 600 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name); 601 602 rval = qla2x00_start_sp(sp); 603 if (rval != QLA_SUCCESS) 604 goto done_free_sp; 605 606 return rval; 607 608 done_free_sp: 609 sp->free(sp); 610 done: 611 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 612 qla2x00_post_async_adisc_work(vha, fcport, data); 613 return rval; 614 } 615 616 static bool qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id) 617 { 618 struct qla_hw_data *ha = vha->hw; 619 620 if (IS_FWI2_CAPABLE(ha)) 621 return loop_id > NPH_LAST_HANDLE; 622 623 return (loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) || 624 loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST; 625 } 626 627 /** 628 * qla2x00_find_new_loop_id - scan through our port list and find a new usable loop ID 629 * @vha: adapter state pointer. 630 * @dev: port structure pointer. 631 * 632 * Returns: 633 * qla2x00 local function return status code. 634 * 635 * Context: 636 * Kernel context. 637 */ 638 static int qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) 639 { 640 int rval; 641 struct qla_hw_data *ha = vha->hw; 642 unsigned long flags = 0; 643 644 rval = QLA_SUCCESS; 645 646 spin_lock_irqsave(&ha->vport_slock, flags); 647 648 dev->loop_id = find_first_zero_bit(ha->loop_id_map, LOOPID_MAP_SIZE); 649 if (dev->loop_id >= LOOPID_MAP_SIZE || 650 qla2x00_is_reserved_id(vha, dev->loop_id)) { 651 dev->loop_id = FC_NO_LOOP_ID; 652 rval = QLA_FUNCTION_FAILED; 653 } else { 654 set_bit(dev->loop_id, ha->loop_id_map); 655 } 656 spin_unlock_irqrestore(&ha->vport_slock, flags); 657 658 if (rval == QLA_SUCCESS) 659 ql_dbg(ql_dbg_disc, dev->vha, 0x2086, 660 "Assigning new loopid=%x, portid=%x.\n", 661 dev->loop_id, dev->d_id.b24); 662 else 663 ql_log(ql_log_warn, dev->vha, 0x2087, 664 "No loop_id's available, portid=%x.\n", 665 dev->d_id.b24); 666 667 return rval; 668 } 669 670 void qla2x00_clear_loop_id(fc_port_t *fcport) 671 { 672 struct qla_hw_data *ha = fcport->vha->hw; 673 674 if (fcport->loop_id == FC_NO_LOOP_ID || 675 qla2x00_is_reserved_id(fcport->vha, fcport->loop_id)) 676 return; 677 678 clear_bit(fcport->loop_id, ha->loop_id_map); 679 fcport->loop_id = FC_NO_LOOP_ID; 680 } 681 682 static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha, 683 struct event_arg *ea) 684 { 685 fc_port_t *fcport, *conflict_fcport; 686 struct get_name_list_extended *e; 687 u16 i, n, found = 0, loop_id; 688 port_id_t id; 689 u64 wwn; 690 u16 data[2]; 691 u8 current_login_state, nvme_cls; 692 693 fcport = ea->fcport; 694 ql_dbg(ql_dbg_disc, vha, 0xffff, 695 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n", 696 __func__, fcport->port_name, fcport->disc_state, 697 fcport->fw_login_state, ea->rc, 698 fcport->login_gen, fcport->last_login_gen, 699 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id); 700 701 if (fcport->disc_state == DSC_DELETE_PEND) 702 return; 703 704 if (ea->rc) { /* rval */ 705 if (fcport->login_retry == 0) { 706 ql_dbg(ql_dbg_disc, vha, 0x20de, 707 "GNL failed Port login retry %8phN, retry cnt=%d.\n", 708 fcport->port_name, fcport->login_retry); 709 } 710 return; 711 } 712 713 if (fcport->last_rscn_gen != fcport->rscn_gen) { 714 qla_rscn_replay(fcport); 715 qlt_schedule_sess_for_deletion(fcport); 716 return; 717 } else if (fcport->last_login_gen != fcport->login_gen) { 718 ql_dbg(ql_dbg_disc, vha, 0x20e0, 719 "%s %8phC login gen changed\n", 720 __func__, fcport->port_name); 721 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 722 return; 723 } 724 725 n = ea->data[0] / sizeof(struct get_name_list_extended); 726 727 ql_dbg(ql_dbg_disc, vha, 0x20e1, 728 "%s %d %8phC n %d %02x%02x%02x lid %d \n", 729 __func__, __LINE__, fcport->port_name, n, 730 fcport->d_id.b.domain, fcport->d_id.b.area, 731 fcport->d_id.b.al_pa, fcport->loop_id); 732 733 for (i = 0; i < n; i++) { 734 e = &vha->gnl.l[i]; 735 wwn = wwn_to_u64(e->port_name); 736 id.b.domain = e->port_id[2]; 737 id.b.area = e->port_id[1]; 738 id.b.al_pa = e->port_id[0]; 739 id.b.rsvd_1 = 0; 740 741 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE)) 742 continue; 743 744 if (IS_SW_RESV_ADDR(id)) 745 continue; 746 747 found = 1; 748 749 loop_id = le16_to_cpu(e->nport_handle); 750 loop_id = (loop_id & 0x7fff); 751 nvme_cls = e->current_login_state >> 4; 752 current_login_state = e->current_login_state & 0xf; 753 754 if (PRLI_PHASE(nvme_cls)) { 755 current_login_state = nvme_cls; 756 fcport->fc4_type &= ~FS_FC4TYPE_FCP; 757 fcport->fc4_type |= FS_FC4TYPE_NVME; 758 } else if (PRLI_PHASE(current_login_state)) { 759 fcport->fc4_type |= FS_FC4TYPE_FCP; 760 fcport->fc4_type &= ~FS_FC4TYPE_NVME; 761 } 762 763 ql_dbg(ql_dbg_disc, vha, 0x20e2, 764 "%s found %8phC CLS [%x|%x] fc4_type %d ID[%06x|%06x] lid[%d|%d]\n", 765 __func__, fcport->port_name, 766 e->current_login_state, fcport->fw_login_state, 767 fcport->fc4_type, id.b24, fcport->d_id.b24, 768 loop_id, fcport->loop_id); 769 770 switch (fcport->disc_state) { 771 case DSC_DELETE_PEND: 772 case DSC_DELETED: 773 break; 774 default: 775 if ((id.b24 != fcport->d_id.b24 && 776 fcport->d_id.b24 && 777 fcport->loop_id != FC_NO_LOOP_ID) || 778 (fcport->loop_id != FC_NO_LOOP_ID && 779 fcport->loop_id != loop_id)) { 780 ql_dbg(ql_dbg_disc, vha, 0x20e3, 781 "%s %d %8phC post del sess\n", 782 __func__, __LINE__, fcport->port_name); 783 if (fcport->n2n_flag) 784 fcport->d_id.b24 = 0; 785 qlt_schedule_sess_for_deletion(fcport); 786 return; 787 } 788 break; 789 } 790 791 fcport->loop_id = loop_id; 792 if (fcport->n2n_flag) 793 fcport->d_id.b24 = id.b24; 794 795 wwn = wwn_to_u64(fcport->port_name); 796 qlt_find_sess_invalidate_other(vha, wwn, 797 id, loop_id, &conflict_fcport); 798 799 if (conflict_fcport) { 800 /* 801 * Another share fcport share the same loop_id & 802 * nport id. Conflict fcport needs to finish 803 * cleanup before this fcport can proceed to login. 804 */ 805 conflict_fcport->conflict = fcport; 806 fcport->login_pause = 1; 807 } 808 809 switch (vha->hw->current_topology) { 810 default: 811 switch (current_login_state) { 812 case DSC_LS_PRLI_COMP: 813 ql_dbg(ql_dbg_disc + ql_dbg_verbose, 814 vha, 0x20e4, "%s %d %8phC post gpdb\n", 815 __func__, __LINE__, fcport->port_name); 816 817 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0) 818 fcport->port_type = FCT_INITIATOR; 819 else 820 fcport->port_type = FCT_TARGET; 821 data[0] = data[1] = 0; 822 qla2x00_post_async_adisc_work(vha, fcport, 823 data); 824 break; 825 case DSC_LS_PORT_UNAVAIL: 826 default: 827 if (fcport->loop_id == FC_NO_LOOP_ID) { 828 qla2x00_find_new_loop_id(vha, fcport); 829 fcport->fw_login_state = 830 DSC_LS_PORT_UNAVAIL; 831 } 832 ql_dbg(ql_dbg_disc, vha, 0x20e5, 833 "%s %d %8phC\n", __func__, __LINE__, 834 fcport->port_name); 835 qla24xx_fcport_handle_login(vha, fcport); 836 break; 837 } 838 break; 839 case ISP_CFG_N: 840 fcport->fw_login_state = current_login_state; 841 fcport->d_id = id; 842 switch (current_login_state) { 843 case DSC_LS_PRLI_PEND: 844 /* 845 * In the middle of PRLI. Let it finish. 846 * Allow relogin code to recheck state again 847 * with GNL. Push disc_state back to DELETED 848 * so GNL can go out again 849 */ 850 qla2x00_set_fcport_disc_state(fcport, 851 DSC_DELETED); 852 break; 853 case DSC_LS_PRLI_COMP: 854 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0) 855 fcport->port_type = FCT_INITIATOR; 856 else 857 fcport->port_type = FCT_TARGET; 858 859 data[0] = data[1] = 0; 860 qla2x00_post_async_adisc_work(vha, fcport, 861 data); 862 break; 863 case DSC_LS_PLOGI_COMP: 864 if (fcport_is_bigger(fcport)) { 865 /* local adapter is smaller */ 866 if (fcport->loop_id != FC_NO_LOOP_ID) 867 qla2x00_clear_loop_id(fcport); 868 869 fcport->loop_id = loop_id; 870 qla24xx_fcport_handle_login(vha, 871 fcport); 872 break; 873 } 874 fallthrough; 875 default: 876 if (fcport_is_smaller(fcport)) { 877 /* local adapter is bigger */ 878 if (fcport->loop_id != FC_NO_LOOP_ID) 879 qla2x00_clear_loop_id(fcport); 880 881 fcport->loop_id = loop_id; 882 qla24xx_fcport_handle_login(vha, 883 fcport); 884 } 885 break; 886 } 887 break; 888 } /* switch (ha->current_topology) */ 889 } 890 891 if (!found) { 892 switch (vha->hw->current_topology) { 893 case ISP_CFG_F: 894 case ISP_CFG_FL: 895 for (i = 0; i < n; i++) { 896 e = &vha->gnl.l[i]; 897 id.b.domain = e->port_id[0]; 898 id.b.area = e->port_id[1]; 899 id.b.al_pa = e->port_id[2]; 900 id.b.rsvd_1 = 0; 901 loop_id = le16_to_cpu(e->nport_handle); 902 903 if (fcport->d_id.b24 == id.b24) { 904 conflict_fcport = 905 qla2x00_find_fcport_by_wwpn(vha, 906 e->port_name, 0); 907 if (conflict_fcport) { 908 ql_dbg(ql_dbg_disc + ql_dbg_verbose, 909 vha, 0x20e5, 910 "%s %d %8phC post del sess\n", 911 __func__, __LINE__, 912 conflict_fcport->port_name); 913 qlt_schedule_sess_for_deletion 914 (conflict_fcport); 915 } 916 } 917 /* 918 * FW already picked this loop id for 919 * another fcport 920 */ 921 if (fcport->loop_id == loop_id) 922 fcport->loop_id = FC_NO_LOOP_ID; 923 } 924 qla24xx_fcport_handle_login(vha, fcport); 925 break; 926 case ISP_CFG_N: 927 qla2x00_set_fcport_disc_state(fcport, DSC_DELETED); 928 if (time_after_eq(jiffies, fcport->dm_login_expire)) { 929 if (fcport->n2n_link_reset_cnt < 2) { 930 fcport->n2n_link_reset_cnt++; 931 /* 932 * remote port is not sending PLOGI. 933 * Reset link to kick start his state 934 * machine 935 */ 936 set_bit(N2N_LINK_RESET, 937 &vha->dpc_flags); 938 } else { 939 if (fcport->n2n_chip_reset < 1) { 940 ql_log(ql_log_info, vha, 0x705d, 941 "Chip reset to bring laser down"); 942 set_bit(ISP_ABORT_NEEDED, 943 &vha->dpc_flags); 944 fcport->n2n_chip_reset++; 945 } else { 946 ql_log(ql_log_info, vha, 0x705d, 947 "Remote port %8ph is not coming back\n", 948 fcport->port_name); 949 fcport->scan_state = 0; 950 } 951 } 952 qla2xxx_wake_dpc(vha); 953 } else { 954 /* 955 * report port suppose to do PLOGI. Give him 956 * more time. FW will catch it. 957 */ 958 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 959 } 960 break; 961 default: 962 break; 963 } 964 } 965 } /* gnl_event */ 966 967 static void qla24xx_async_gnl_sp_done(srb_t *sp, int res) 968 { 969 struct scsi_qla_host *vha = sp->vha; 970 unsigned long flags; 971 struct fc_port *fcport = NULL, *tf; 972 u16 i, n = 0, loop_id; 973 struct event_arg ea; 974 struct get_name_list_extended *e; 975 u64 wwn; 976 struct list_head h; 977 bool found = false; 978 979 ql_dbg(ql_dbg_disc, vha, 0x20e7, 980 "Async done-%s res %x mb[1]=%x mb[2]=%x \n", 981 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1], 982 sp->u.iocb_cmd.u.mbx.in_mb[2]); 983 984 if (res == QLA_FUNCTION_TIMEOUT) 985 return; 986 987 sp->fcport->flags &= ~(FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE); 988 memset(&ea, 0, sizeof(ea)); 989 ea.sp = sp; 990 ea.rc = res; 991 992 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >= 993 sizeof(struct get_name_list_extended)) { 994 n = sp->u.iocb_cmd.u.mbx.in_mb[1] / 995 sizeof(struct get_name_list_extended); 996 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */ 997 } 998 999 for (i = 0; i < n; i++) { 1000 e = &vha->gnl.l[i]; 1001 loop_id = le16_to_cpu(e->nport_handle); 1002 /* mask out reserve bit */ 1003 loop_id = (loop_id & 0x7fff); 1004 set_bit(loop_id, vha->hw->loop_id_map); 1005 wwn = wwn_to_u64(e->port_name); 1006 1007 ql_dbg(ql_dbg_disc, vha, 0x20e8, 1008 "%s %8phC %02x:%02x:%02x CLS %x/%x lid %x \n", 1009 __func__, &wwn, e->port_id[2], e->port_id[1], 1010 e->port_id[0], e->current_login_state, e->last_login_state, 1011 (loop_id & 0x7fff)); 1012 } 1013 1014 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1015 1016 INIT_LIST_HEAD(&h); 1017 fcport = tf = NULL; 1018 if (!list_empty(&vha->gnl.fcports)) 1019 list_splice_init(&vha->gnl.fcports, &h); 1020 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1021 1022 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) { 1023 list_del_init(&fcport->gnl_entry); 1024 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1025 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1026 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1027 ea.fcport = fcport; 1028 1029 qla24xx_handle_gnl_done_event(vha, &ea); 1030 } 1031 1032 /* create new fcport if fw has knowledge of new sessions */ 1033 for (i = 0; i < n; i++) { 1034 port_id_t id; 1035 u64 wwnn; 1036 1037 e = &vha->gnl.l[i]; 1038 wwn = wwn_to_u64(e->port_name); 1039 1040 found = false; 1041 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) { 1042 if (!memcmp((u8 *)&wwn, fcport->port_name, 1043 WWN_SIZE)) { 1044 found = true; 1045 break; 1046 } 1047 } 1048 1049 id.b.domain = e->port_id[2]; 1050 id.b.area = e->port_id[1]; 1051 id.b.al_pa = e->port_id[0]; 1052 id.b.rsvd_1 = 0; 1053 1054 if (!found && wwn && !IS_SW_RESV_ADDR(id)) { 1055 ql_dbg(ql_dbg_disc, vha, 0x2065, 1056 "%s %d %8phC %06x post new sess\n", 1057 __func__, __LINE__, (u8 *)&wwn, id.b24); 1058 wwnn = wwn_to_u64(e->node_name); 1059 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn, 1060 (u8 *)&wwnn, NULL, 0); 1061 } 1062 } 1063 1064 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1065 vha->gnl.sent = 0; 1066 if (!list_empty(&vha->gnl.fcports)) { 1067 /* retrigger gnl */ 1068 list_for_each_entry_safe(fcport, tf, &vha->gnl.fcports, 1069 gnl_entry) { 1070 list_del_init(&fcport->gnl_entry); 1071 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1072 if (qla24xx_post_gnl_work(vha, fcport) == QLA_SUCCESS) 1073 break; 1074 } 1075 } 1076 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1077 1078 sp->free(sp); 1079 } 1080 1081 int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport) 1082 { 1083 srb_t *sp; 1084 struct srb_iocb *mbx; 1085 int rval = QLA_FUNCTION_FAILED; 1086 unsigned long flags; 1087 u16 *mb; 1088 1089 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT)) 1090 return rval; 1091 1092 ql_dbg(ql_dbg_disc, vha, 0x20d9, 1093 "Async-gnlist WWPN %8phC \n", fcport->port_name); 1094 1095 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1096 fcport->flags |= FCF_ASYNC_SENT; 1097 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 1098 fcport->last_rscn_gen = fcport->rscn_gen; 1099 fcport->last_login_gen = fcport->login_gen; 1100 1101 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports); 1102 if (vha->gnl.sent) { 1103 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1104 return QLA_SUCCESS; 1105 } 1106 vha->gnl.sent = 1; 1107 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1108 1109 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1110 if (!sp) 1111 goto done; 1112 1113 sp->type = SRB_MB_IOCB; 1114 sp->name = "gnlist"; 1115 sp->gen1 = fcport->rscn_gen; 1116 sp->gen2 = fcport->login_gen; 1117 1118 mbx = &sp->u.iocb_cmd; 1119 mbx->timeout = qla2x00_async_iocb_timeout; 1120 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2); 1121 1122 mb = sp->u.iocb_cmd.u.mbx.out_mb; 1123 mb[0] = MBC_PORT_NODE_NAME_LIST; 1124 mb[1] = BIT_2 | BIT_3; 1125 mb[2] = MSW(vha->gnl.ldma); 1126 mb[3] = LSW(vha->gnl.ldma); 1127 mb[6] = MSW(MSD(vha->gnl.ldma)); 1128 mb[7] = LSW(MSD(vha->gnl.ldma)); 1129 mb[8] = vha->gnl.size; 1130 mb[9] = vha->vp_idx; 1131 1132 sp->done = qla24xx_async_gnl_sp_done; 1133 1134 ql_dbg(ql_dbg_disc, vha, 0x20da, 1135 "Async-%s - OUT WWPN %8phC hndl %x\n", 1136 sp->name, fcport->port_name, sp->handle); 1137 1138 rval = qla2x00_start_sp(sp); 1139 if (rval != QLA_SUCCESS) 1140 goto done_free_sp; 1141 1142 return rval; 1143 1144 done_free_sp: 1145 sp->free(sp); 1146 done: 1147 fcport->flags &= ~(FCF_ASYNC_ACTIVE | FCF_ASYNC_SENT); 1148 return rval; 1149 } 1150 1151 int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport) 1152 { 1153 struct qla_work_evt *e; 1154 1155 e = qla2x00_alloc_work(vha, QLA_EVT_GNL); 1156 if (!e) 1157 return QLA_FUNCTION_FAILED; 1158 1159 e->u.fcport.fcport = fcport; 1160 fcport->flags |= FCF_ASYNC_ACTIVE; 1161 return qla2x00_post_work(vha, e); 1162 } 1163 1164 static void qla24xx_async_gpdb_sp_done(srb_t *sp, int res) 1165 { 1166 struct scsi_qla_host *vha = sp->vha; 1167 struct qla_hw_data *ha = vha->hw; 1168 fc_port_t *fcport = sp->fcport; 1169 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb; 1170 struct event_arg ea; 1171 1172 ql_dbg(ql_dbg_disc, vha, 0x20db, 1173 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n", 1174 sp->name, res, fcport->port_name, mb[1], mb[2]); 1175 1176 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1177 1178 if (res == QLA_FUNCTION_TIMEOUT) 1179 goto done; 1180 1181 memset(&ea, 0, sizeof(ea)); 1182 ea.fcport = fcport; 1183 ea.sp = sp; 1184 1185 qla24xx_handle_gpdb_event(vha, &ea); 1186 1187 done: 1188 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in, 1189 sp->u.iocb_cmd.u.mbx.in_dma); 1190 1191 sp->free(sp); 1192 } 1193 1194 static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport) 1195 { 1196 struct qla_work_evt *e; 1197 1198 if (vha->host->active_mode == MODE_TARGET) 1199 return QLA_FUNCTION_FAILED; 1200 1201 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI); 1202 if (!e) 1203 return QLA_FUNCTION_FAILED; 1204 1205 e->u.fcport.fcport = fcport; 1206 1207 return qla2x00_post_work(vha, e); 1208 } 1209 1210 static void qla2x00_async_prli_sp_done(srb_t *sp, int res) 1211 { 1212 struct scsi_qla_host *vha = sp->vha; 1213 struct srb_iocb *lio = &sp->u.iocb_cmd; 1214 struct event_arg ea; 1215 1216 ql_dbg(ql_dbg_disc, vha, 0x2129, 1217 "%s %8phC res %d \n", __func__, 1218 sp->fcport->port_name, res); 1219 1220 sp->fcport->flags &= ~FCF_ASYNC_SENT; 1221 1222 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 1223 memset(&ea, 0, sizeof(ea)); 1224 ea.fcport = sp->fcport; 1225 ea.data[0] = lio->u.logio.data[0]; 1226 ea.data[1] = lio->u.logio.data[1]; 1227 ea.iop[0] = lio->u.logio.iop[0]; 1228 ea.iop[1] = lio->u.logio.iop[1]; 1229 ea.sp = sp; 1230 1231 qla24xx_handle_prli_done_event(vha, &ea); 1232 } 1233 1234 sp->free(sp); 1235 } 1236 1237 int 1238 qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport) 1239 { 1240 srb_t *sp; 1241 struct srb_iocb *lio; 1242 int rval = QLA_FUNCTION_FAILED; 1243 1244 if (!vha->flags.online) { 1245 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n", 1246 __func__, __LINE__, fcport->port_name); 1247 return rval; 1248 } 1249 1250 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND || 1251 fcport->fw_login_state == DSC_LS_PRLI_PEND) && 1252 qla_dual_mode_enabled(vha)) { 1253 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n", 1254 __func__, __LINE__, fcport->port_name); 1255 return rval; 1256 } 1257 1258 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1259 if (!sp) 1260 return rval; 1261 1262 fcport->flags |= FCF_ASYNC_SENT; 1263 fcport->logout_completed = 0; 1264 1265 sp->type = SRB_PRLI_CMD; 1266 sp->name = "prli"; 1267 1268 lio = &sp->u.iocb_cmd; 1269 lio->timeout = qla2x00_async_iocb_timeout; 1270 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 1271 1272 sp->done = qla2x00_async_prli_sp_done; 1273 lio->u.logio.flags = 0; 1274 1275 if (NVME_TARGET(vha->hw, fcport)) 1276 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI; 1277 1278 ql_dbg(ql_dbg_disc, vha, 0x211b, 1279 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d fc4type %x priority %x %s.\n", 1280 fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24, 1281 fcport->login_retry, fcport->fc4_type, vha->hw->fc4_type_priority, 1282 NVME_TARGET(vha->hw, fcport) ? "nvme" : "fcp"); 1283 1284 rval = qla2x00_start_sp(sp); 1285 if (rval != QLA_SUCCESS) { 1286 fcport->flags |= FCF_LOGIN_NEEDED; 1287 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1288 goto done_free_sp; 1289 } 1290 1291 return rval; 1292 1293 done_free_sp: 1294 sp->free(sp); 1295 fcport->flags &= ~FCF_ASYNC_SENT; 1296 return rval; 1297 } 1298 1299 int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 1300 { 1301 struct qla_work_evt *e; 1302 1303 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB); 1304 if (!e) 1305 return QLA_FUNCTION_FAILED; 1306 1307 e->u.fcport.fcport = fcport; 1308 e->u.fcport.opt = opt; 1309 fcport->flags |= FCF_ASYNC_ACTIVE; 1310 return qla2x00_post_work(vha, e); 1311 } 1312 1313 int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 1314 { 1315 srb_t *sp; 1316 struct srb_iocb *mbx; 1317 int rval = QLA_FUNCTION_FAILED; 1318 u16 *mb; 1319 dma_addr_t pd_dma; 1320 struct port_database_24xx *pd; 1321 struct qla_hw_data *ha = vha->hw; 1322 1323 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) || 1324 fcport->loop_id == FC_NO_LOOP_ID) { 1325 ql_log(ql_log_warn, vha, 0xffff, 1326 "%s: %8phC - not sending command.\n", 1327 __func__, fcport->port_name); 1328 return rval; 1329 } 1330 1331 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1332 if (!sp) 1333 goto done; 1334 1335 qla2x00_set_fcport_disc_state(fcport, DSC_GPDB); 1336 1337 fcport->flags |= FCF_ASYNC_SENT; 1338 sp->type = SRB_MB_IOCB; 1339 sp->name = "gpdb"; 1340 sp->gen1 = fcport->rscn_gen; 1341 sp->gen2 = fcport->login_gen; 1342 1343 mbx = &sp->u.iocb_cmd; 1344 mbx->timeout = qla2x00_async_iocb_timeout; 1345 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 1346 1347 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1348 if (pd == NULL) { 1349 ql_log(ql_log_warn, vha, 0xd043, 1350 "Failed to allocate port database structure.\n"); 1351 goto done_free_sp; 1352 } 1353 1354 mb = sp->u.iocb_cmd.u.mbx.out_mb; 1355 mb[0] = MBC_GET_PORT_DATABASE; 1356 mb[1] = fcport->loop_id; 1357 mb[2] = MSW(pd_dma); 1358 mb[3] = LSW(pd_dma); 1359 mb[6] = MSW(MSD(pd_dma)); 1360 mb[7] = LSW(MSD(pd_dma)); 1361 mb[9] = vha->vp_idx; 1362 mb[10] = opt; 1363 1364 mbx->u.mbx.in = pd; 1365 mbx->u.mbx.in_dma = pd_dma; 1366 1367 sp->done = qla24xx_async_gpdb_sp_done; 1368 1369 ql_dbg(ql_dbg_disc, vha, 0x20dc, 1370 "Async-%s %8phC hndl %x opt %x\n", 1371 sp->name, fcport->port_name, sp->handle, opt); 1372 1373 rval = qla2x00_start_sp(sp); 1374 if (rval != QLA_SUCCESS) 1375 goto done_free_sp; 1376 return rval; 1377 1378 done_free_sp: 1379 if (pd) 1380 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1381 1382 sp->free(sp); 1383 fcport->flags &= ~FCF_ASYNC_SENT; 1384 done: 1385 fcport->flags &= ~FCF_ASYNC_ACTIVE; 1386 qla24xx_post_gpdb_work(vha, fcport, opt); 1387 return rval; 1388 } 1389 1390 static 1391 void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea) 1392 { 1393 unsigned long flags; 1394 1395 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1396 ea->fcport->login_gen++; 1397 ea->fcport->deleted = 0; 1398 ea->fcport->logout_on_delete = 1; 1399 1400 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) { 1401 vha->fcport_count++; 1402 ea->fcport->login_succ = 1; 1403 1404 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1405 qla24xx_sched_upd_fcport(ea->fcport); 1406 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1407 } else if (ea->fcport->login_succ) { 1408 /* 1409 * We have an existing session. A late RSCN delivery 1410 * must have triggered the session to be re-validate. 1411 * Session is still valid. 1412 */ 1413 ql_dbg(ql_dbg_disc, vha, 0x20d6, 1414 "%s %d %8phC session revalidate success\n", 1415 __func__, __LINE__, ea->fcport->port_name); 1416 qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_COMPLETE); 1417 } 1418 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1419 } 1420 1421 static 1422 void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea) 1423 { 1424 fc_port_t *fcport = ea->fcport; 1425 struct port_database_24xx *pd; 1426 struct srb *sp = ea->sp; 1427 uint8_t ls; 1428 1429 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in; 1430 1431 fcport->flags &= ~FCF_ASYNC_SENT; 1432 1433 ql_dbg(ql_dbg_disc, vha, 0x20d2, 1434 "%s %8phC DS %d LS %d fc4_type %x rc %d\n", __func__, 1435 fcport->port_name, fcport->disc_state, pd->current_login_state, 1436 fcport->fc4_type, ea->rc); 1437 1438 if (fcport->disc_state == DSC_DELETE_PEND) 1439 return; 1440 1441 if (NVME_TARGET(vha->hw, fcport)) 1442 ls = pd->current_login_state >> 4; 1443 else 1444 ls = pd->current_login_state & 0xf; 1445 1446 if (ea->sp->gen2 != fcport->login_gen) { 1447 /* target side must have changed it. */ 1448 1449 ql_dbg(ql_dbg_disc, vha, 0x20d3, 1450 "%s %8phC generation changed\n", 1451 __func__, fcport->port_name); 1452 return; 1453 } else if (ea->sp->gen1 != fcport->rscn_gen) { 1454 qla_rscn_replay(fcport); 1455 qlt_schedule_sess_for_deletion(fcport); 1456 return; 1457 } 1458 1459 switch (ls) { 1460 case PDS_PRLI_COMPLETE: 1461 __qla24xx_parse_gpdb(vha, fcport, pd); 1462 break; 1463 case PDS_PLOGI_PENDING: 1464 case PDS_PLOGI_COMPLETE: 1465 case PDS_PRLI_PENDING: 1466 case PDS_PRLI2_PENDING: 1467 /* Set discovery state back to GNL to Relogin attempt */ 1468 if (qla_dual_mode_enabled(vha) || 1469 qla_ini_mode_enabled(vha)) { 1470 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 1471 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1472 } 1473 return; 1474 case PDS_LOGO_PENDING: 1475 case PDS_PORT_UNAVAILABLE: 1476 default: 1477 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n", 1478 __func__, __LINE__, fcport->port_name); 1479 qlt_schedule_sess_for_deletion(fcport); 1480 return; 1481 } 1482 __qla24xx_handle_gpdb_event(vha, ea); 1483 } /* gpdb event */ 1484 1485 static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport) 1486 { 1487 u8 login = 0; 1488 int rc; 1489 1490 if (qla_tgt_mode_enabled(vha)) 1491 return; 1492 1493 if (qla_dual_mode_enabled(vha)) { 1494 if (N2N_TOPO(vha->hw)) { 1495 u64 mywwn, wwn; 1496 1497 mywwn = wwn_to_u64(vha->port_name); 1498 wwn = wwn_to_u64(fcport->port_name); 1499 if (mywwn > wwn) 1500 login = 1; 1501 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP) 1502 && time_after_eq(jiffies, 1503 fcport->plogi_nack_done_deadline)) 1504 login = 1; 1505 } else { 1506 login = 1; 1507 } 1508 } else { 1509 /* initiator mode */ 1510 login = 1; 1511 } 1512 1513 if (login && fcport->login_retry) { 1514 fcport->login_retry--; 1515 if (fcport->loop_id == FC_NO_LOOP_ID) { 1516 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 1517 rc = qla2x00_find_new_loop_id(vha, fcport); 1518 if (rc) { 1519 ql_dbg(ql_dbg_disc, vha, 0x20e6, 1520 "%s %d %8phC post del sess - out of loopid\n", 1521 __func__, __LINE__, fcport->port_name); 1522 fcport->scan_state = 0; 1523 qlt_schedule_sess_for_deletion(fcport); 1524 return; 1525 } 1526 } 1527 ql_dbg(ql_dbg_disc, vha, 0x20bf, 1528 "%s %d %8phC post login\n", 1529 __func__, __LINE__, fcport->port_name); 1530 qla2x00_post_async_login_work(vha, fcport, NULL); 1531 } 1532 } 1533 1534 int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport) 1535 { 1536 u16 data[2]; 1537 u64 wwn; 1538 u16 sec; 1539 1540 ql_dbg(ql_dbg_disc, vha, 0x20d8, 1541 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d\n", 1542 __func__, fcport->port_name, fcport->disc_state, 1543 fcport->fw_login_state, fcport->login_pause, fcport->flags, 1544 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen, 1545 fcport->login_gen, fcport->loop_id, fcport->scan_state); 1546 1547 if (fcport->scan_state != QLA_FCPORT_FOUND) 1548 return 0; 1549 1550 if ((fcport->loop_id != FC_NO_LOOP_ID) && 1551 qla_dual_mode_enabled(vha) && 1552 ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) || 1553 (fcport->fw_login_state == DSC_LS_PRLI_PEND))) 1554 return 0; 1555 1556 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP && 1557 !N2N_TOPO(vha->hw)) { 1558 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) { 1559 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1560 return 0; 1561 } 1562 } 1563 1564 /* Target won't initiate port login if fabric is present */ 1565 if (vha->host->active_mode == MODE_TARGET && !N2N_TOPO(vha->hw)) 1566 return 0; 1567 1568 if (fcport->flags & FCF_ASYNC_SENT) { 1569 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1570 return 0; 1571 } 1572 1573 switch (fcport->disc_state) { 1574 case DSC_DELETED: 1575 wwn = wwn_to_u64(fcport->node_name); 1576 switch (vha->hw->current_topology) { 1577 case ISP_CFG_N: 1578 if (fcport_is_smaller(fcport)) { 1579 /* this adapter is bigger */ 1580 if (fcport->login_retry) { 1581 if (fcport->loop_id == FC_NO_LOOP_ID) { 1582 qla2x00_find_new_loop_id(vha, 1583 fcport); 1584 fcport->fw_login_state = 1585 DSC_LS_PORT_UNAVAIL; 1586 } 1587 fcport->login_retry--; 1588 qla_post_els_plogi_work(vha, fcport); 1589 } else { 1590 ql_log(ql_log_info, vha, 0x705d, 1591 "Unable to reach remote port %8phC", 1592 fcport->port_name); 1593 } 1594 } else { 1595 qla24xx_post_gnl_work(vha, fcport); 1596 } 1597 break; 1598 default: 1599 if (wwn == 0) { 1600 ql_dbg(ql_dbg_disc, vha, 0xffff, 1601 "%s %d %8phC post GNNID\n", 1602 __func__, __LINE__, fcport->port_name); 1603 qla24xx_post_gnnid_work(vha, fcport); 1604 } else if (fcport->loop_id == FC_NO_LOOP_ID) { 1605 ql_dbg(ql_dbg_disc, vha, 0x20bd, 1606 "%s %d %8phC post gnl\n", 1607 __func__, __LINE__, fcport->port_name); 1608 qla24xx_post_gnl_work(vha, fcport); 1609 } else { 1610 qla_chk_n2n_b4_login(vha, fcport); 1611 } 1612 break; 1613 } 1614 break; 1615 1616 case DSC_GNL: 1617 switch (vha->hw->current_topology) { 1618 case ISP_CFG_N: 1619 if ((fcport->current_login_state & 0xf) == 0x6) { 1620 ql_dbg(ql_dbg_disc, vha, 0x2118, 1621 "%s %d %8phC post GPDB work\n", 1622 __func__, __LINE__, fcport->port_name); 1623 fcport->chip_reset = 1624 vha->hw->base_qpair->chip_reset; 1625 qla24xx_post_gpdb_work(vha, fcport, 0); 1626 } else { 1627 ql_dbg(ql_dbg_disc, vha, 0x2118, 1628 "%s %d %8phC post %s PRLI\n", 1629 __func__, __LINE__, fcport->port_name, 1630 NVME_TARGET(vha->hw, fcport) ? "NVME" : 1631 "FC"); 1632 qla24xx_post_prli_work(vha, fcport); 1633 } 1634 break; 1635 default: 1636 if (fcport->login_pause) { 1637 ql_dbg(ql_dbg_disc, vha, 0x20d8, 1638 "%s %d %8phC exit\n", 1639 __func__, __LINE__, 1640 fcport->port_name); 1641 fcport->last_rscn_gen = fcport->rscn_gen; 1642 fcport->last_login_gen = fcport->login_gen; 1643 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1644 break; 1645 } 1646 qla_chk_n2n_b4_login(vha, fcport); 1647 break; 1648 } 1649 break; 1650 1651 case DSC_LOGIN_FAILED: 1652 if (N2N_TOPO(vha->hw)) 1653 qla_chk_n2n_b4_login(vha, fcport); 1654 else 1655 qlt_schedule_sess_for_deletion(fcport); 1656 break; 1657 1658 case DSC_LOGIN_COMPLETE: 1659 /* recheck login state */ 1660 data[0] = data[1] = 0; 1661 qla2x00_post_async_adisc_work(vha, fcport, data); 1662 break; 1663 1664 case DSC_LOGIN_PEND: 1665 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) 1666 qla24xx_post_prli_work(vha, fcport); 1667 break; 1668 1669 case DSC_UPD_FCPORT: 1670 sec = jiffies_to_msecs(jiffies - 1671 fcport->jiffies_at_registration)/1000; 1672 if (fcport->sec_since_registration < sec && sec && 1673 !(sec % 60)) { 1674 fcport->sec_since_registration = sec; 1675 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff, 1676 "%s %8phC - Slow Rport registration(%d Sec)\n", 1677 __func__, fcport->port_name, sec); 1678 } 1679 1680 if (fcport->next_disc_state != DSC_DELETE_PEND) 1681 fcport->next_disc_state = DSC_ADISC; 1682 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1683 break; 1684 1685 default: 1686 break; 1687 } 1688 1689 return 0; 1690 } 1691 1692 int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id, 1693 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type) 1694 { 1695 struct qla_work_evt *e; 1696 1697 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS); 1698 if (!e) 1699 return QLA_FUNCTION_FAILED; 1700 1701 e->u.new_sess.id = *id; 1702 e->u.new_sess.pla = pla; 1703 e->u.new_sess.fc4_type = fc4_type; 1704 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE); 1705 if (node_name) 1706 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE); 1707 1708 return qla2x00_post_work(vha, e); 1709 } 1710 1711 void qla2x00_handle_rscn(scsi_qla_host_t *vha, struct event_arg *ea) 1712 { 1713 fc_port_t *fcport; 1714 unsigned long flags; 1715 1716 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1); 1717 if (fcport) { 1718 fcport->scan_needed = 1; 1719 fcport->rscn_gen++; 1720 } 1721 1722 spin_lock_irqsave(&vha->work_lock, flags); 1723 if (vha->scan.scan_flags == 0) { 1724 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s: schedule\n", __func__); 1725 vha->scan.scan_flags |= SF_QUEUED; 1726 schedule_delayed_work(&vha->scan.scan_work, 5); 1727 } 1728 spin_unlock_irqrestore(&vha->work_lock, flags); 1729 } 1730 1731 void qla24xx_handle_relogin_event(scsi_qla_host_t *vha, 1732 struct event_arg *ea) 1733 { 1734 fc_port_t *fcport = ea->fcport; 1735 1736 if (test_bit(UNLOADING, &vha->dpc_flags)) 1737 return; 1738 1739 ql_dbg(ql_dbg_disc, vha, 0x2102, 1740 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n", 1741 __func__, fcport->port_name, fcport->disc_state, 1742 fcport->fw_login_state, fcport->login_pause, 1743 fcport->deleted, fcport->conflict, 1744 fcport->last_rscn_gen, fcport->rscn_gen, 1745 fcport->last_login_gen, fcport->login_gen, 1746 fcport->flags); 1747 1748 if (fcport->last_rscn_gen != fcport->rscn_gen) { 1749 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gnl\n", 1750 __func__, __LINE__, fcport->port_name); 1751 qla24xx_post_gnl_work(vha, fcport); 1752 return; 1753 } 1754 1755 qla24xx_fcport_handle_login(vha, fcport); 1756 } 1757 1758 void qla_handle_els_plogi_done(scsi_qla_host_t *vha, 1759 struct event_arg *ea) 1760 { 1761 /* for pure Target Mode, PRLI will not be initiated */ 1762 if (vha->host->active_mode == MODE_TARGET) 1763 return; 1764 1765 ql_dbg(ql_dbg_disc, vha, 0x2118, 1766 "%s %d %8phC post PRLI\n", 1767 __func__, __LINE__, ea->fcport->port_name); 1768 qla24xx_post_prli_work(vha, ea->fcport); 1769 } 1770 1771 /* 1772 * RSCN(s) came in for this fcport, but the RSCN(s) was not able 1773 * to be consumed by the fcport 1774 */ 1775 void qla_rscn_replay(fc_port_t *fcport) 1776 { 1777 struct event_arg ea; 1778 1779 switch (fcport->disc_state) { 1780 case DSC_DELETE_PEND: 1781 return; 1782 default: 1783 break; 1784 } 1785 1786 if (fcport->scan_needed) { 1787 memset(&ea, 0, sizeof(ea)); 1788 ea.id = fcport->d_id; 1789 ea.id.b.rsvd_1 = RSCN_PORT_ADDR; 1790 qla2x00_handle_rscn(fcport->vha, &ea); 1791 } 1792 } 1793 1794 static void 1795 qla2x00_tmf_iocb_timeout(void *data) 1796 { 1797 srb_t *sp = data; 1798 struct srb_iocb *tmf = &sp->u.iocb_cmd; 1799 int rc, h; 1800 unsigned long flags; 1801 1802 rc = qla24xx_async_abort_cmd(sp, false); 1803 if (rc) { 1804 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 1805 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; h++) { 1806 if (sp->qpair->req->outstanding_cmds[h] == sp) { 1807 sp->qpair->req->outstanding_cmds[h] = NULL; 1808 break; 1809 } 1810 } 1811 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 1812 tmf->u.tmf.comp_status = cpu_to_le16(CS_TIMEOUT); 1813 tmf->u.tmf.data = QLA_FUNCTION_FAILED; 1814 complete(&tmf->u.tmf.comp); 1815 } 1816 } 1817 1818 static void qla2x00_tmf_sp_done(srb_t *sp, int res) 1819 { 1820 struct srb_iocb *tmf = &sp->u.iocb_cmd; 1821 1822 complete(&tmf->u.tmf.comp); 1823 } 1824 1825 int 1826 qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun, 1827 uint32_t tag) 1828 { 1829 struct scsi_qla_host *vha = fcport->vha; 1830 struct srb_iocb *tm_iocb; 1831 srb_t *sp; 1832 int rval = QLA_FUNCTION_FAILED; 1833 1834 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1835 if (!sp) 1836 goto done; 1837 1838 tm_iocb = &sp->u.iocb_cmd; 1839 sp->type = SRB_TM_CMD; 1840 sp->name = "tmf"; 1841 1842 tm_iocb->timeout = qla2x00_tmf_iocb_timeout; 1843 init_completion(&tm_iocb->u.tmf.comp); 1844 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)); 1845 1846 tm_iocb->u.tmf.flags = flags; 1847 tm_iocb->u.tmf.lun = lun; 1848 tm_iocb->u.tmf.data = tag; 1849 sp->done = qla2x00_tmf_sp_done; 1850 1851 ql_dbg(ql_dbg_taskm, vha, 0x802f, 1852 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 1853 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 1854 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1855 1856 rval = qla2x00_start_sp(sp); 1857 if (rval != QLA_SUCCESS) 1858 goto done_free_sp; 1859 wait_for_completion(&tm_iocb->u.tmf.comp); 1860 1861 rval = tm_iocb->u.tmf.data; 1862 1863 if (rval != QLA_SUCCESS) { 1864 ql_log(ql_log_warn, vha, 0x8030, 1865 "TM IOCB failed (%x).\n", rval); 1866 } 1867 1868 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) { 1869 flags = tm_iocb->u.tmf.flags; 1870 lun = (uint16_t)tm_iocb->u.tmf.lun; 1871 1872 /* Issue Marker IOCB */ 1873 qla2x00_marker(vha, vha->hw->base_qpair, 1874 fcport->loop_id, lun, 1875 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID); 1876 } 1877 1878 done_free_sp: 1879 sp->free(sp); 1880 fcport->flags &= ~FCF_ASYNC_SENT; 1881 done: 1882 return rval; 1883 } 1884 1885 int 1886 qla24xx_async_abort_command(srb_t *sp) 1887 { 1888 unsigned long flags = 0; 1889 1890 uint32_t handle; 1891 fc_port_t *fcport = sp->fcport; 1892 struct qla_qpair *qpair = sp->qpair; 1893 struct scsi_qla_host *vha = fcport->vha; 1894 struct req_que *req = qpair->req; 1895 1896 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1897 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 1898 if (req->outstanding_cmds[handle] == sp) 1899 break; 1900 } 1901 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1902 1903 if (handle == req->num_outstanding_cmds) { 1904 /* Command not found. */ 1905 return QLA_FUNCTION_FAILED; 1906 } 1907 if (sp->type == SRB_FXIOCB_DCMD) 1908 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport, 1909 FXDISC_ABORT_IOCTL); 1910 1911 return qla24xx_async_abort_cmd(sp, true); 1912 } 1913 1914 static void 1915 qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea) 1916 { 1917 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 1918 ea->data[0]); 1919 1920 switch (ea->data[0]) { 1921 case MBS_COMMAND_COMPLETE: 1922 ql_dbg(ql_dbg_disc, vha, 0x2118, 1923 "%s %d %8phC post gpdb\n", 1924 __func__, __LINE__, ea->fcport->port_name); 1925 1926 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset; 1927 ea->fcport->logout_on_delete = 1; 1928 ea->fcport->nvme_prli_service_param = ea->iop[0]; 1929 if (ea->iop[0] & NVME_PRLI_SP_FIRST_BURST) 1930 ea->fcport->nvme_first_burst_size = 1931 (ea->iop[1] & 0xffff) * 512; 1932 else 1933 ea->fcport->nvme_first_burst_size = 0; 1934 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 1935 break; 1936 default: 1937 if ((ea->iop[0] == LSC_SCODE_ELS_REJECT) && 1938 (ea->iop[1] == 0x50000)) { /* reson 5=busy expl:0x0 */ 1939 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1940 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP; 1941 break; 1942 } 1943 1944 ql_dbg(ql_dbg_disc, vha, 0x2118, 1945 "%s %d %8phC priority %s, fc4type %x\n", 1946 __func__, __LINE__, ea->fcport->port_name, 1947 vha->hw->fc4_type_priority == FC4_PRIORITY_FCP ? 1948 "FCP" : "NVMe", ea->fcport->fc4_type); 1949 1950 if (N2N_TOPO(vha->hw)) { 1951 if (vha->hw->fc4_type_priority == FC4_PRIORITY_NVME) { 1952 ea->fcport->fc4_type &= ~FS_FC4TYPE_NVME; 1953 ea->fcport->fc4_type |= FS_FC4TYPE_FCP; 1954 } else { 1955 ea->fcport->fc4_type &= ~FS_FC4TYPE_FCP; 1956 ea->fcport->fc4_type |= FS_FC4TYPE_NVME; 1957 } 1958 1959 if (ea->fcport->n2n_link_reset_cnt < 3) { 1960 ea->fcport->n2n_link_reset_cnt++; 1961 vha->relogin_jif = jiffies + 2 * HZ; 1962 /* 1963 * PRLI failed. Reset link to kick start 1964 * state machine 1965 */ 1966 set_bit(N2N_LINK_RESET, &vha->dpc_flags); 1967 } else { 1968 ql_log(ql_log_warn, vha, 0x2119, 1969 "%s %d %8phC Unable to reconnect\n", 1970 __func__, __LINE__, 1971 ea->fcport->port_name); 1972 } 1973 } else { 1974 /* 1975 * switch connect. login failed. Take connection down 1976 * and allow relogin to retrigger 1977 */ 1978 if (NVME_FCP_TARGET(ea->fcport)) { 1979 ql_dbg(ql_dbg_disc, vha, 0x2118, 1980 "%s %d %8phC post %s prli\n", 1981 __func__, __LINE__, 1982 ea->fcport->port_name, 1983 (ea->fcport->fc4_type & FS_FC4TYPE_NVME) 1984 ? "NVMe" : "FCP"); 1985 if (vha->hw->fc4_type_priority == FC4_PRIORITY_NVME) 1986 ea->fcport->fc4_type &= ~FS_FC4TYPE_NVME; 1987 else 1988 ea->fcport->fc4_type &= ~FS_FC4TYPE_FCP; 1989 } 1990 1991 ea->fcport->flags &= ~FCF_ASYNC_SENT; 1992 ea->fcport->keep_nport_handle = 0; 1993 ea->fcport->logout_on_delete = 1; 1994 qlt_schedule_sess_for_deletion(ea->fcport); 1995 } 1996 break; 1997 } 1998 } 1999 2000 void 2001 qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea) 2002 { 2003 port_id_t cid; /* conflict Nport id */ 2004 u16 lid; 2005 struct fc_port *conflict_fcport; 2006 unsigned long flags; 2007 struct fc_port *fcport = ea->fcport; 2008 2009 ql_dbg(ql_dbg_disc, vha, 0xffff, 2010 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n", 2011 __func__, fcport->port_name, fcport->disc_state, 2012 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen, 2013 ea->sp->gen1, fcport->rscn_gen, 2014 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]); 2015 2016 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) || 2017 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) { 2018 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2019 "%s %d %8phC Remote is trying to login\n", 2020 __func__, __LINE__, fcport->port_name); 2021 return; 2022 } 2023 2024 if ((fcport->disc_state == DSC_DELETE_PEND) || 2025 (fcport->disc_state == DSC_DELETED)) { 2026 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2027 return; 2028 } 2029 2030 if (ea->sp->gen2 != fcport->login_gen) { 2031 /* target side must have changed it. */ 2032 ql_dbg(ql_dbg_disc, vha, 0x20d3, 2033 "%s %8phC generation changed\n", 2034 __func__, fcport->port_name); 2035 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2036 return; 2037 } else if (ea->sp->gen1 != fcport->rscn_gen) { 2038 ql_dbg(ql_dbg_disc, vha, 0x20d3, 2039 "%s %8phC RSCN generation changed\n", 2040 __func__, fcport->port_name); 2041 qla_rscn_replay(fcport); 2042 qlt_schedule_sess_for_deletion(fcport); 2043 return; 2044 } 2045 2046 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 2047 ea->data[0]); 2048 2049 switch (ea->data[0]) { 2050 case MBS_COMMAND_COMPLETE: 2051 /* 2052 * Driver must validate login state - If PRLI not complete, 2053 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI 2054 * requests. 2055 */ 2056 if (NVME_TARGET(vha->hw, ea->fcport)) { 2057 ql_dbg(ql_dbg_disc, vha, 0x2117, 2058 "%s %d %8phC post prli\n", 2059 __func__, __LINE__, ea->fcport->port_name); 2060 qla24xx_post_prli_work(vha, ea->fcport); 2061 } else { 2062 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2063 "%s %d %8phC LoopID 0x%x in use with %06x. post gpdb\n", 2064 __func__, __LINE__, ea->fcport->port_name, 2065 ea->fcport->loop_id, ea->fcport->d_id.b24); 2066 2067 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map); 2068 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 2069 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset; 2070 ea->fcport->logout_on_delete = 1; 2071 ea->fcport->send_els_logo = 0; 2072 ea->fcport->fw_login_state = DSC_LS_PRLI_COMP; 2073 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 2074 2075 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 2076 } 2077 break; 2078 case MBS_COMMAND_ERROR: 2079 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n", 2080 __func__, __LINE__, ea->fcport->port_name, ea->data[1]); 2081 2082 ea->fcport->flags &= ~FCF_ASYNC_SENT; 2083 qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_FAILED); 2084 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED) 2085 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2086 else 2087 qla2x00_mark_device_lost(vha, ea->fcport, 1); 2088 break; 2089 case MBS_LOOP_ID_USED: 2090 /* data[1] = IO PARAM 1 = nport ID */ 2091 cid.b.domain = (ea->iop[1] >> 16) & 0xff; 2092 cid.b.area = (ea->iop[1] >> 8) & 0xff; 2093 cid.b.al_pa = ea->iop[1] & 0xff; 2094 cid.b.rsvd_1 = 0; 2095 2096 ql_dbg(ql_dbg_disc, vha, 0x20ec, 2097 "%s %d %8phC lid %#x in use with pid %06x post gnl\n", 2098 __func__, __LINE__, ea->fcport->port_name, 2099 ea->fcport->loop_id, cid.b24); 2100 2101 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map); 2102 ea->fcport->loop_id = FC_NO_LOOP_ID; 2103 qla24xx_post_gnl_work(vha, ea->fcport); 2104 break; 2105 case MBS_PORT_ID_USED: 2106 lid = ea->iop[1] & 0xffff; 2107 qlt_find_sess_invalidate_other(vha, 2108 wwn_to_u64(ea->fcport->port_name), 2109 ea->fcport->d_id, lid, &conflict_fcport); 2110 2111 if (conflict_fcport) { 2112 /* 2113 * Another fcport share the same loop_id/nport id. 2114 * Conflict fcport needs to finish cleanup before this 2115 * fcport can proceed to login. 2116 */ 2117 conflict_fcport->conflict = ea->fcport; 2118 ea->fcport->login_pause = 1; 2119 2120 ql_dbg(ql_dbg_disc, vha, 0x20ed, 2121 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n", 2122 __func__, __LINE__, ea->fcport->port_name, 2123 ea->fcport->d_id.b24, lid); 2124 } else { 2125 ql_dbg(ql_dbg_disc, vha, 0x20ed, 2126 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n", 2127 __func__, __LINE__, ea->fcport->port_name, 2128 ea->fcport->d_id.b24, lid); 2129 2130 qla2x00_clear_loop_id(ea->fcport); 2131 set_bit(lid, vha->hw->loop_id_map); 2132 ea->fcport->loop_id = lid; 2133 ea->fcport->keep_nport_handle = 0; 2134 ea->fcport->logout_on_delete = 1; 2135 qlt_schedule_sess_for_deletion(ea->fcport); 2136 } 2137 break; 2138 } 2139 return; 2140 } 2141 2142 /****************************************************************************/ 2143 /* QLogic ISP2x00 Hardware Support Functions. */ 2144 /****************************************************************************/ 2145 2146 static int 2147 qla83xx_nic_core_fw_load(scsi_qla_host_t *vha) 2148 { 2149 int rval = QLA_SUCCESS; 2150 struct qla_hw_data *ha = vha->hw; 2151 uint32_t idc_major_ver, idc_minor_ver; 2152 uint16_t config[4]; 2153 2154 qla83xx_idc_lock(vha, 0); 2155 2156 /* SV: TODO: Assign initialization timeout from 2157 * flash-info / other param 2158 */ 2159 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT; 2160 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT; 2161 2162 /* Set our fcoe function presence */ 2163 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) { 2164 ql_dbg(ql_dbg_p3p, vha, 0xb077, 2165 "Error while setting DRV-Presence.\n"); 2166 rval = QLA_FUNCTION_FAILED; 2167 goto exit; 2168 } 2169 2170 /* Decide the reset ownership */ 2171 qla83xx_reset_ownership(vha); 2172 2173 /* 2174 * On first protocol driver load: 2175 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery 2176 * register. 2177 * Others: Check compatibility with current IDC Major version. 2178 */ 2179 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver); 2180 if (ha->flags.nic_core_reset_owner) { 2181 /* Set IDC Major version */ 2182 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION; 2183 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver); 2184 2185 /* Clearing IDC-Lock-Recovery register */ 2186 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0); 2187 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) { 2188 /* 2189 * Clear further IDC participation if we are not compatible with 2190 * the current IDC Major Version. 2191 */ 2192 ql_log(ql_log_warn, vha, 0xb07d, 2193 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n", 2194 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION); 2195 __qla83xx_clear_drv_presence(vha); 2196 rval = QLA_FUNCTION_FAILED; 2197 goto exit; 2198 } 2199 /* Each function sets its supported Minor version. */ 2200 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver); 2201 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2)); 2202 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver); 2203 2204 if (ha->flags.nic_core_reset_owner) { 2205 memset(config, 0, sizeof(config)); 2206 if (!qla81xx_get_port_config(vha, config)) 2207 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 2208 QLA8XXX_DEV_READY); 2209 } 2210 2211 rval = qla83xx_idc_state_handler(vha); 2212 2213 exit: 2214 qla83xx_idc_unlock(vha, 0); 2215 2216 return rval; 2217 } 2218 2219 /* 2220 * qla2x00_initialize_adapter 2221 * Initialize board. 2222 * 2223 * Input: 2224 * ha = adapter block pointer. 2225 * 2226 * Returns: 2227 * 0 = success 2228 */ 2229 int 2230 qla2x00_initialize_adapter(scsi_qla_host_t *vha) 2231 { 2232 int rval; 2233 struct qla_hw_data *ha = vha->hw; 2234 struct req_que *req = ha->req_q_map[0]; 2235 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2236 2237 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats)); 2238 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat)); 2239 2240 /* Clear adapter flags. */ 2241 vha->flags.online = 0; 2242 ha->flags.chip_reset_done = 0; 2243 vha->flags.reset_active = 0; 2244 ha->flags.pci_channel_io_perm_failure = 0; 2245 ha->flags.eeh_busy = 0; 2246 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64(); 2247 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 2248 atomic_set(&vha->loop_state, LOOP_DOWN); 2249 vha->device_flags = DFLG_NO_CABLE; 2250 vha->dpc_flags = 0; 2251 vha->flags.management_server_logged_in = 0; 2252 vha->marker_needed = 0; 2253 ha->isp_abort_cnt = 0; 2254 ha->beacon_blink_led = 0; 2255 2256 set_bit(0, ha->req_qid_map); 2257 set_bit(0, ha->rsp_qid_map); 2258 2259 ql_dbg(ql_dbg_init, vha, 0x0040, 2260 "Configuring PCI space...\n"); 2261 rval = ha->isp_ops->pci_config(vha); 2262 if (rval) { 2263 ql_log(ql_log_warn, vha, 0x0044, 2264 "Unable to configure PCI space.\n"); 2265 return (rval); 2266 } 2267 2268 ha->isp_ops->reset_chip(vha); 2269 2270 /* Check for secure flash support */ 2271 if (IS_QLA28XX(ha)) { 2272 if (rd_reg_word(®->mailbox12) & BIT_0) 2273 ha->flags.secure_adapter = 1; 2274 ql_log(ql_log_info, vha, 0xffff, "Secure Adapter: %s\n", 2275 (ha->flags.secure_adapter) ? "Yes" : "No"); 2276 } 2277 2278 2279 rval = qla2xxx_get_flash_info(vha); 2280 if (rval) { 2281 ql_log(ql_log_fatal, vha, 0x004f, 2282 "Unable to validate FLASH data.\n"); 2283 return rval; 2284 } 2285 2286 if (IS_QLA8044(ha)) { 2287 qla8044_read_reset_template(vha); 2288 2289 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0. 2290 * If DONRESET_BIT0 is set, drivers should not set dev_state 2291 * to NEED_RESET. But if NEED_RESET is set, drivers should 2292 * should honor the reset. */ 2293 if (ql2xdontresethba == 1) 2294 qla8044_set_idc_dontreset(vha); 2295 } 2296 2297 ha->isp_ops->get_flash_version(vha, req->ring); 2298 ql_dbg(ql_dbg_init, vha, 0x0061, 2299 "Configure NVRAM parameters...\n"); 2300 2301 /* Let priority default to FCP, can be overridden by nvram_config */ 2302 ha->fc4_type_priority = FC4_PRIORITY_FCP; 2303 2304 ha->isp_ops->nvram_config(vha); 2305 2306 if (ha->fc4_type_priority != FC4_PRIORITY_FCP && 2307 ha->fc4_type_priority != FC4_PRIORITY_NVME) 2308 ha->fc4_type_priority = FC4_PRIORITY_FCP; 2309 2310 ql_log(ql_log_info, vha, 0xffff, "FC4 priority set to %s\n", 2311 ha->fc4_type_priority == FC4_PRIORITY_FCP ? "FCP" : "NVMe"); 2312 2313 if (ha->flags.disable_serdes) { 2314 /* Mask HBA via NVRAM settings? */ 2315 ql_log(ql_log_info, vha, 0x0077, 2316 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name); 2317 return QLA_FUNCTION_FAILED; 2318 } 2319 2320 ql_dbg(ql_dbg_init, vha, 0x0078, 2321 "Verifying loaded RISC code...\n"); 2322 2323 /* If smartsan enabled then require fdmi and rdp enabled */ 2324 if (ql2xsmartsan) { 2325 ql2xfdmienable = 1; 2326 ql2xrdpenable = 1; 2327 } 2328 2329 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) { 2330 rval = ha->isp_ops->chip_diag(vha); 2331 if (rval) 2332 return (rval); 2333 rval = qla2x00_setup_chip(vha); 2334 if (rval) 2335 return (rval); 2336 } 2337 2338 if (IS_QLA84XX(ha)) { 2339 ha->cs84xx = qla84xx_get_chip(vha); 2340 if (!ha->cs84xx) { 2341 ql_log(ql_log_warn, vha, 0x00d0, 2342 "Unable to configure ISP84XX.\n"); 2343 return QLA_FUNCTION_FAILED; 2344 } 2345 } 2346 2347 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha)) 2348 rval = qla2x00_init_rings(vha); 2349 2350 /* No point in continuing if firmware initialization failed. */ 2351 if (rval != QLA_SUCCESS) 2352 return rval; 2353 2354 ha->flags.chip_reset_done = 1; 2355 2356 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) { 2357 /* Issue verify 84xx FW IOCB to complete 84xx initialization */ 2358 rval = qla84xx_init_chip(vha); 2359 if (rval != QLA_SUCCESS) { 2360 ql_log(ql_log_warn, vha, 0x00d4, 2361 "Unable to initialize ISP84XX.\n"); 2362 qla84xx_put_chip(vha); 2363 } 2364 } 2365 2366 /* Load the NIC Core f/w if we are the first protocol driver. */ 2367 if (IS_QLA8031(ha)) { 2368 rval = qla83xx_nic_core_fw_load(vha); 2369 if (rval) 2370 ql_log(ql_log_warn, vha, 0x0124, 2371 "Error in initializing NIC Core f/w.\n"); 2372 } 2373 2374 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)) 2375 qla24xx_read_fcp_prio_cfg(vha); 2376 2377 if (IS_P3P_TYPE(ha)) 2378 qla82xx_set_driver_version(vha, QLA2XXX_VERSION); 2379 else 2380 qla25xx_set_driver_version(vha, QLA2XXX_VERSION); 2381 2382 return (rval); 2383 } 2384 2385 /** 2386 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers. 2387 * @vha: HA context 2388 * 2389 * Returns 0 on success. 2390 */ 2391 int 2392 qla2100_pci_config(scsi_qla_host_t *vha) 2393 { 2394 uint16_t w; 2395 unsigned long flags; 2396 struct qla_hw_data *ha = vha->hw; 2397 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2398 2399 pci_set_master(ha->pdev); 2400 pci_try_set_mwi(ha->pdev); 2401 2402 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2403 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2404 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2405 2406 pci_disable_rom(ha->pdev); 2407 2408 /* Get PCI bus information. */ 2409 spin_lock_irqsave(&ha->hardware_lock, flags); 2410 ha->pci_attr = rd_reg_word(®->ctrl_status); 2411 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2412 2413 return QLA_SUCCESS; 2414 } 2415 2416 /** 2417 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers. 2418 * @vha: HA context 2419 * 2420 * Returns 0 on success. 2421 */ 2422 int 2423 qla2300_pci_config(scsi_qla_host_t *vha) 2424 { 2425 uint16_t w; 2426 unsigned long flags = 0; 2427 uint32_t cnt; 2428 struct qla_hw_data *ha = vha->hw; 2429 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2430 2431 pci_set_master(ha->pdev); 2432 pci_try_set_mwi(ha->pdev); 2433 2434 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2435 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2436 2437 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2438 w &= ~PCI_COMMAND_INTX_DISABLE; 2439 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2440 2441 /* 2442 * If this is a 2300 card and not 2312, reset the 2443 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately, 2444 * the 2310 also reports itself as a 2300 so we need to get the 2445 * fb revision level -- a 6 indicates it really is a 2300 and 2446 * not a 2310. 2447 */ 2448 if (IS_QLA2300(ha)) { 2449 spin_lock_irqsave(&ha->hardware_lock, flags); 2450 2451 /* Pause RISC. */ 2452 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2453 for (cnt = 0; cnt < 30000; cnt++) { 2454 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) 2455 break; 2456 2457 udelay(10); 2458 } 2459 2460 /* Select FPM registers. */ 2461 wrt_reg_word(®->ctrl_status, 0x20); 2462 rd_reg_word(®->ctrl_status); 2463 2464 /* Get the fb rev level */ 2465 ha->fb_rev = RD_FB_CMD_REG(ha, reg); 2466 2467 if (ha->fb_rev == FPM_2300) 2468 pci_clear_mwi(ha->pdev); 2469 2470 /* Deselect FPM registers. */ 2471 wrt_reg_word(®->ctrl_status, 0x0); 2472 rd_reg_word(®->ctrl_status); 2473 2474 /* Release RISC module. */ 2475 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 2476 for (cnt = 0; cnt < 30000; cnt++) { 2477 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0) 2478 break; 2479 2480 udelay(10); 2481 } 2482 2483 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2484 } 2485 2486 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 2487 2488 pci_disable_rom(ha->pdev); 2489 2490 /* Get PCI bus information. */ 2491 spin_lock_irqsave(&ha->hardware_lock, flags); 2492 ha->pci_attr = rd_reg_word(®->ctrl_status); 2493 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2494 2495 return QLA_SUCCESS; 2496 } 2497 2498 /** 2499 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers. 2500 * @vha: HA context 2501 * 2502 * Returns 0 on success. 2503 */ 2504 int 2505 qla24xx_pci_config(scsi_qla_host_t *vha) 2506 { 2507 uint16_t w; 2508 unsigned long flags = 0; 2509 struct qla_hw_data *ha = vha->hw; 2510 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2511 2512 pci_set_master(ha->pdev); 2513 pci_try_set_mwi(ha->pdev); 2514 2515 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2516 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2517 w &= ~PCI_COMMAND_INTX_DISABLE; 2518 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2519 2520 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 2521 2522 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ 2523 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) 2524 pcix_set_mmrbc(ha->pdev, 2048); 2525 2526 /* PCIe -- adjust Maximum Read Request Size (2048). */ 2527 if (pci_is_pcie(ha->pdev)) 2528 pcie_set_readrq(ha->pdev, 4096); 2529 2530 pci_disable_rom(ha->pdev); 2531 2532 ha->chip_revision = ha->pdev->revision; 2533 2534 /* Get PCI bus information. */ 2535 spin_lock_irqsave(&ha->hardware_lock, flags); 2536 ha->pci_attr = rd_reg_dword(®->ctrl_status); 2537 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2538 2539 return QLA_SUCCESS; 2540 } 2541 2542 /** 2543 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. 2544 * @vha: HA context 2545 * 2546 * Returns 0 on success. 2547 */ 2548 int 2549 qla25xx_pci_config(scsi_qla_host_t *vha) 2550 { 2551 uint16_t w; 2552 struct qla_hw_data *ha = vha->hw; 2553 2554 pci_set_master(ha->pdev); 2555 pci_try_set_mwi(ha->pdev); 2556 2557 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2558 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2559 w &= ~PCI_COMMAND_INTX_DISABLE; 2560 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2561 2562 /* PCIe -- adjust Maximum Read Request Size (2048). */ 2563 if (pci_is_pcie(ha->pdev)) 2564 pcie_set_readrq(ha->pdev, 4096); 2565 2566 pci_disable_rom(ha->pdev); 2567 2568 ha->chip_revision = ha->pdev->revision; 2569 2570 return QLA_SUCCESS; 2571 } 2572 2573 /** 2574 * qla2x00_isp_firmware() - Choose firmware image. 2575 * @vha: HA context 2576 * 2577 * Returns 0 on success. 2578 */ 2579 static int 2580 qla2x00_isp_firmware(scsi_qla_host_t *vha) 2581 { 2582 int rval; 2583 uint16_t loop_id, topo, sw_cap; 2584 uint8_t domain, area, al_pa; 2585 struct qla_hw_data *ha = vha->hw; 2586 2587 /* Assume loading risc code */ 2588 rval = QLA_FUNCTION_FAILED; 2589 2590 if (ha->flags.disable_risc_code_load) { 2591 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n"); 2592 2593 /* Verify checksum of loaded RISC code. */ 2594 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address); 2595 if (rval == QLA_SUCCESS) { 2596 /* And, verify we are not in ROM code. */ 2597 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa, 2598 &area, &domain, &topo, &sw_cap); 2599 } 2600 } 2601 2602 if (rval) 2603 ql_dbg(ql_dbg_init, vha, 0x007a, 2604 "**** Load RISC code ****.\n"); 2605 2606 return (rval); 2607 } 2608 2609 /** 2610 * qla2x00_reset_chip() - Reset ISP chip. 2611 * @vha: HA context 2612 * 2613 * Returns 0 on success. 2614 */ 2615 int 2616 qla2x00_reset_chip(scsi_qla_host_t *vha) 2617 { 2618 unsigned long flags = 0; 2619 struct qla_hw_data *ha = vha->hw; 2620 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2621 uint32_t cnt; 2622 uint16_t cmd; 2623 int rval = QLA_FUNCTION_FAILED; 2624 2625 if (unlikely(pci_channel_offline(ha->pdev))) 2626 return rval; 2627 2628 ha->isp_ops->disable_intrs(ha); 2629 2630 spin_lock_irqsave(&ha->hardware_lock, flags); 2631 2632 /* Turn off master enable */ 2633 cmd = 0; 2634 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd); 2635 cmd &= ~PCI_COMMAND_MASTER; 2636 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 2637 2638 if (!IS_QLA2100(ha)) { 2639 /* Pause RISC. */ 2640 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2641 if (IS_QLA2200(ha) || IS_QLA2300(ha)) { 2642 for (cnt = 0; cnt < 30000; cnt++) { 2643 if ((rd_reg_word(®->hccr) & 2644 HCCR_RISC_PAUSE) != 0) 2645 break; 2646 udelay(100); 2647 } 2648 } else { 2649 rd_reg_word(®->hccr); /* PCI Posting. */ 2650 udelay(10); 2651 } 2652 2653 /* Select FPM registers. */ 2654 wrt_reg_word(®->ctrl_status, 0x20); 2655 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2656 2657 /* FPM Soft Reset. */ 2658 wrt_reg_word(®->fpm_diag_config, 0x100); 2659 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */ 2660 2661 /* Toggle Fpm Reset. */ 2662 if (!IS_QLA2200(ha)) { 2663 wrt_reg_word(®->fpm_diag_config, 0x0); 2664 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */ 2665 } 2666 2667 /* Select frame buffer registers. */ 2668 wrt_reg_word(®->ctrl_status, 0x10); 2669 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2670 2671 /* Reset frame buffer FIFOs. */ 2672 if (IS_QLA2200(ha)) { 2673 WRT_FB_CMD_REG(ha, reg, 0xa000); 2674 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ 2675 } else { 2676 WRT_FB_CMD_REG(ha, reg, 0x00fc); 2677 2678 /* Read back fb_cmd until zero or 3 seconds max */ 2679 for (cnt = 0; cnt < 3000; cnt++) { 2680 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) 2681 break; 2682 udelay(100); 2683 } 2684 } 2685 2686 /* Select RISC module registers. */ 2687 wrt_reg_word(®->ctrl_status, 0); 2688 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2689 2690 /* Reset RISC processor. */ 2691 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 2692 rd_reg_word(®->hccr); /* PCI Posting. */ 2693 2694 /* Release RISC processor. */ 2695 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 2696 rd_reg_word(®->hccr); /* PCI Posting. */ 2697 } 2698 2699 wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT); 2700 wrt_reg_word(®->hccr, HCCR_CLR_HOST_INT); 2701 2702 /* Reset ISP chip. */ 2703 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 2704 2705 /* Wait for RISC to recover from reset. */ 2706 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2707 /* 2708 * It is necessary to for a delay here since the card doesn't 2709 * respond to PCI reads during a reset. On some architectures 2710 * this will result in an MCA. 2711 */ 2712 udelay(20); 2713 for (cnt = 30000; cnt; cnt--) { 2714 if ((rd_reg_word(®->ctrl_status) & 2715 CSR_ISP_SOFT_RESET) == 0) 2716 break; 2717 udelay(100); 2718 } 2719 } else 2720 udelay(10); 2721 2722 /* Reset RISC processor. */ 2723 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 2724 2725 wrt_reg_word(®->semaphore, 0); 2726 2727 /* Release RISC processor. */ 2728 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 2729 rd_reg_word(®->hccr); /* PCI Posting. */ 2730 2731 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2732 for (cnt = 0; cnt < 30000; cnt++) { 2733 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) 2734 break; 2735 2736 udelay(100); 2737 } 2738 } else 2739 udelay(100); 2740 2741 /* Turn on master enable */ 2742 cmd |= PCI_COMMAND_MASTER; 2743 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 2744 2745 /* Disable RISC pause on FPM parity error. */ 2746 if (!IS_QLA2100(ha)) { 2747 wrt_reg_word(®->hccr, HCCR_DISABLE_PARITY_PAUSE); 2748 rd_reg_word(®->hccr); /* PCI Posting. */ 2749 } 2750 2751 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2752 2753 return QLA_SUCCESS; 2754 } 2755 2756 /** 2757 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC. 2758 * @vha: HA context 2759 * 2760 * Returns 0 on success. 2761 */ 2762 static int 2763 qla81xx_reset_mpi(scsi_qla_host_t *vha) 2764 { 2765 uint16_t mb[4] = {0x1010, 0, 1, 0}; 2766 2767 if (!IS_QLA81XX(vha->hw)) 2768 return QLA_SUCCESS; 2769 2770 return qla81xx_write_mpi_register(vha, mb); 2771 } 2772 2773 static int 2774 qla_chk_risc_recovery(scsi_qla_host_t *vha) 2775 { 2776 struct qla_hw_data *ha = vha->hw; 2777 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2778 __le16 __iomem *mbptr = ®->mailbox0; 2779 int i; 2780 u16 mb[32]; 2781 int rc = QLA_SUCCESS; 2782 2783 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 2784 return rc; 2785 2786 /* this check is only valid after RISC reset */ 2787 mb[0] = rd_reg_word(mbptr); 2788 mbptr++; 2789 if (mb[0] == 0xf) { 2790 rc = QLA_FUNCTION_FAILED; 2791 2792 for (i = 1; i < 32; i++) { 2793 mb[i] = rd_reg_word(mbptr); 2794 mbptr++; 2795 } 2796 2797 ql_log(ql_log_warn, vha, 0x1015, 2798 "RISC reset failed. mb[0-7] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 2799 mb[0], mb[1], mb[2], mb[3], mb[4], mb[5], mb[6], mb[7]); 2800 ql_log(ql_log_warn, vha, 0x1015, 2801 "RISC reset failed. mb[8-15] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 2802 mb[8], mb[9], mb[10], mb[11], mb[12], mb[13], mb[14], 2803 mb[15]); 2804 ql_log(ql_log_warn, vha, 0x1015, 2805 "RISC reset failed. mb[16-23] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 2806 mb[16], mb[17], mb[18], mb[19], mb[20], mb[21], mb[22], 2807 mb[23]); 2808 ql_log(ql_log_warn, vha, 0x1015, 2809 "RISC reset failed. mb[24-31] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 2810 mb[24], mb[25], mb[26], mb[27], mb[28], mb[29], mb[30], 2811 mb[31]); 2812 } 2813 return rc; 2814 } 2815 2816 /** 2817 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. 2818 * @vha: HA context 2819 * 2820 * Returns 0 on success. 2821 */ 2822 static inline int 2823 qla24xx_reset_risc(scsi_qla_host_t *vha) 2824 { 2825 unsigned long flags = 0; 2826 struct qla_hw_data *ha = vha->hw; 2827 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2828 uint32_t cnt; 2829 uint16_t wd; 2830 static int abts_cnt; /* ISP abort retry counts */ 2831 int rval = QLA_SUCCESS; 2832 int print = 1; 2833 2834 spin_lock_irqsave(&ha->hardware_lock, flags); 2835 2836 /* Reset RISC. */ 2837 wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 2838 for (cnt = 0; cnt < 30000; cnt++) { 2839 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 2840 break; 2841 2842 udelay(10); 2843 } 2844 2845 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)) 2846 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); 2847 2848 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e, 2849 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n", 2850 rd_reg_dword(®->hccr), 2851 rd_reg_dword(®->ctrl_status), 2852 (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)); 2853 2854 wrt_reg_dword(®->ctrl_status, 2855 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 2856 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2857 2858 udelay(100); 2859 2860 /* Wait for firmware to complete NVRAM accesses. */ 2861 rd_reg_word(®->mailbox0); 2862 for (cnt = 10000; rd_reg_word(®->mailbox0) != 0 && 2863 rval == QLA_SUCCESS; cnt--) { 2864 barrier(); 2865 if (cnt) 2866 udelay(5); 2867 else 2868 rval = QLA_FUNCTION_TIMEOUT; 2869 } 2870 2871 if (rval == QLA_SUCCESS) 2872 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags); 2873 2874 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f, 2875 "HCCR: 0x%x, MailBox0 Status 0x%x\n", 2876 rd_reg_dword(®->hccr), 2877 rd_reg_word(®->mailbox0)); 2878 2879 /* Wait for soft-reset to complete. */ 2880 rd_reg_dword(®->ctrl_status); 2881 for (cnt = 0; cnt < 60; cnt++) { 2882 barrier(); 2883 if ((rd_reg_dword(®->ctrl_status) & 2884 CSRX_ISP_SOFT_RESET) == 0) 2885 break; 2886 2887 udelay(5); 2888 } 2889 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) 2890 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags); 2891 2892 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d, 2893 "HCCR: 0x%x, Soft Reset status: 0x%x\n", 2894 rd_reg_dword(®->hccr), 2895 rd_reg_dword(®->ctrl_status)); 2896 2897 /* If required, do an MPI FW reset now */ 2898 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) { 2899 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) { 2900 if (++abts_cnt < 5) { 2901 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2902 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags); 2903 } else { 2904 /* 2905 * We exhausted the ISP abort retries. We have to 2906 * set the board offline. 2907 */ 2908 abts_cnt = 0; 2909 vha->flags.online = 0; 2910 } 2911 } 2912 } 2913 2914 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET); 2915 rd_reg_dword(®->hccr); 2916 2917 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE); 2918 rd_reg_dword(®->hccr); 2919 2920 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET); 2921 mdelay(10); 2922 rd_reg_dword(®->hccr); 2923 2924 wd = rd_reg_word(®->mailbox0); 2925 for (cnt = 300; wd != 0 && rval == QLA_SUCCESS; cnt--) { 2926 barrier(); 2927 if (cnt) { 2928 mdelay(1); 2929 if (print && qla_chk_risc_recovery(vha)) 2930 print = 0; 2931 2932 wd = rd_reg_word(®->mailbox0); 2933 } else { 2934 rval = QLA_FUNCTION_TIMEOUT; 2935 2936 ql_log(ql_log_warn, vha, 0x015e, 2937 "RISC reset timeout\n"); 2938 } 2939 } 2940 2941 if (rval == QLA_SUCCESS) 2942 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); 2943 2944 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e, 2945 "Host Risc 0x%x, mailbox0 0x%x\n", 2946 rd_reg_dword(®->hccr), 2947 rd_reg_word(®->mailbox0)); 2948 2949 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2950 2951 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f, 2952 "Driver in %s mode\n", 2953 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling"); 2954 2955 if (IS_NOPOLLING_TYPE(ha)) 2956 ha->isp_ops->enable_intrs(ha); 2957 2958 return rval; 2959 } 2960 2961 static void 2962 qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) 2963 { 2964 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 2965 2966 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 2967 *data = rd_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET); 2968 } 2969 2970 static void 2971 qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) 2972 { 2973 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 2974 2975 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 2976 wrt_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET, data); 2977 } 2978 2979 static void 2980 qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) 2981 { 2982 uint32_t wd32 = 0; 2983 uint delta_msec = 100; 2984 uint elapsed_msec = 0; 2985 uint timeout_msec; 2986 ulong n; 2987 2988 if (vha->hw->pdev->subsystem_device != 0x0175 && 2989 vha->hw->pdev->subsystem_device != 0x0240) 2990 return; 2991 2992 wrt_reg_dword(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE); 2993 udelay(100); 2994 2995 attempt: 2996 timeout_msec = TIMEOUT_SEMAPHORE; 2997 n = timeout_msec / delta_msec; 2998 while (n--) { 2999 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET); 3000 qla25xx_read_risc_sema_reg(vha, &wd32); 3001 if (wd32 & RISC_SEMAPHORE) 3002 break; 3003 msleep(delta_msec); 3004 elapsed_msec += delta_msec; 3005 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 3006 goto force; 3007 } 3008 3009 if (!(wd32 & RISC_SEMAPHORE)) 3010 goto force; 3011 3012 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 3013 goto acquired; 3014 3015 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR); 3016 timeout_msec = TIMEOUT_SEMAPHORE_FORCE; 3017 n = timeout_msec / delta_msec; 3018 while (n--) { 3019 qla25xx_read_risc_sema_reg(vha, &wd32); 3020 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 3021 break; 3022 msleep(delta_msec); 3023 elapsed_msec += delta_msec; 3024 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 3025 goto force; 3026 } 3027 3028 if (wd32 & RISC_SEMAPHORE_FORCE) 3029 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR); 3030 3031 goto attempt; 3032 3033 force: 3034 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET); 3035 3036 acquired: 3037 return; 3038 } 3039 3040 /** 3041 * qla24xx_reset_chip() - Reset ISP24xx chip. 3042 * @vha: HA context 3043 * 3044 * Returns 0 on success. 3045 */ 3046 int 3047 qla24xx_reset_chip(scsi_qla_host_t *vha) 3048 { 3049 struct qla_hw_data *ha = vha->hw; 3050 int rval = QLA_FUNCTION_FAILED; 3051 3052 if (pci_channel_offline(ha->pdev) && 3053 ha->flags.pci_channel_io_perm_failure) { 3054 return rval; 3055 } 3056 3057 ha->isp_ops->disable_intrs(ha); 3058 3059 qla25xx_manipulate_risc_semaphore(vha); 3060 3061 /* Perform RISC reset. */ 3062 rval = qla24xx_reset_risc(vha); 3063 3064 return rval; 3065 } 3066 3067 /** 3068 * qla2x00_chip_diag() - Test chip for proper operation. 3069 * @vha: HA context 3070 * 3071 * Returns 0 on success. 3072 */ 3073 int 3074 qla2x00_chip_diag(scsi_qla_host_t *vha) 3075 { 3076 int rval; 3077 struct qla_hw_data *ha = vha->hw; 3078 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3079 unsigned long flags = 0; 3080 uint16_t data; 3081 uint32_t cnt; 3082 uint16_t mb[5]; 3083 struct req_que *req = ha->req_q_map[0]; 3084 3085 /* Assume a failed state */ 3086 rval = QLA_FUNCTION_FAILED; 3087 3088 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n", 3089 ®->flash_address); 3090 3091 spin_lock_irqsave(&ha->hardware_lock, flags); 3092 3093 /* Reset ISP chip. */ 3094 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 3095 3096 /* 3097 * We need to have a delay here since the card will not respond while 3098 * in reset causing an MCA on some architectures. 3099 */ 3100 udelay(20); 3101 data = qla2x00_debounce_register(®->ctrl_status); 3102 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) { 3103 udelay(5); 3104 data = rd_reg_word(®->ctrl_status); 3105 barrier(); 3106 } 3107 3108 if (!cnt) 3109 goto chip_diag_failed; 3110 3111 ql_dbg(ql_dbg_init, vha, 0x007c, 3112 "Reset register cleared by chip reset.\n"); 3113 3114 /* Reset RISC processor. */ 3115 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 3116 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 3117 3118 /* Workaround for QLA2312 PCI parity error */ 3119 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 3120 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); 3121 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) { 3122 udelay(5); 3123 data = RD_MAILBOX_REG(ha, reg, 0); 3124 barrier(); 3125 } 3126 } else 3127 udelay(10); 3128 3129 if (!cnt) 3130 goto chip_diag_failed; 3131 3132 /* Check product ID of chip */ 3133 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n"); 3134 3135 mb[1] = RD_MAILBOX_REG(ha, reg, 1); 3136 mb[2] = RD_MAILBOX_REG(ha, reg, 2); 3137 mb[3] = RD_MAILBOX_REG(ha, reg, 3); 3138 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); 3139 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) || 3140 mb[3] != PROD_ID_3) { 3141 ql_log(ql_log_warn, vha, 0x0062, 3142 "Wrong product ID = 0x%x,0x%x,0x%x.\n", 3143 mb[1], mb[2], mb[3]); 3144 3145 goto chip_diag_failed; 3146 } 3147 ha->product_id[0] = mb[1]; 3148 ha->product_id[1] = mb[2]; 3149 ha->product_id[2] = mb[3]; 3150 ha->product_id[3] = mb[4]; 3151 3152 /* Adjust fw RISC transfer size */ 3153 if (req->length > 1024) 3154 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; 3155 else 3156 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 3157 req->length; 3158 3159 if (IS_QLA2200(ha) && 3160 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { 3161 /* Limit firmware transfer size with a 2200A */ 3162 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n"); 3163 3164 ha->device_type |= DT_ISP2200A; 3165 ha->fw_transfer_size = 128; 3166 } 3167 3168 /* Wrap Incoming Mailboxes Test. */ 3169 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3170 3171 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n"); 3172 rval = qla2x00_mbx_reg_test(vha); 3173 if (rval) 3174 ql_log(ql_log_warn, vha, 0x0080, 3175 "Failed mailbox send register test.\n"); 3176 else 3177 /* Flag a successful rval */ 3178 rval = QLA_SUCCESS; 3179 spin_lock_irqsave(&ha->hardware_lock, flags); 3180 3181 chip_diag_failed: 3182 if (rval) 3183 ql_log(ql_log_info, vha, 0x0081, 3184 "Chip diagnostics **** FAILED ****.\n"); 3185 3186 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3187 3188 return (rval); 3189 } 3190 3191 /** 3192 * qla24xx_chip_diag() - Test ISP24xx for proper operation. 3193 * @vha: HA context 3194 * 3195 * Returns 0 on success. 3196 */ 3197 int 3198 qla24xx_chip_diag(scsi_qla_host_t *vha) 3199 { 3200 int rval; 3201 struct qla_hw_data *ha = vha->hw; 3202 struct req_que *req = ha->req_q_map[0]; 3203 3204 if (IS_P3P_TYPE(ha)) 3205 return QLA_SUCCESS; 3206 3207 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; 3208 3209 rval = qla2x00_mbx_reg_test(vha); 3210 if (rval) { 3211 ql_log(ql_log_warn, vha, 0x0082, 3212 "Failed mailbox send register test.\n"); 3213 } else { 3214 /* Flag a successful rval */ 3215 rval = QLA_SUCCESS; 3216 } 3217 3218 return rval; 3219 } 3220 3221 static void 3222 qla2x00_init_fce_trace(scsi_qla_host_t *vha) 3223 { 3224 int rval; 3225 dma_addr_t tc_dma; 3226 void *tc; 3227 struct qla_hw_data *ha = vha->hw; 3228 3229 if (!IS_FWI2_CAPABLE(ha)) 3230 return; 3231 3232 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 3233 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 3234 return; 3235 3236 if (ha->fce) { 3237 ql_dbg(ql_dbg_init, vha, 0x00bd, 3238 "%s: FCE Mem is already allocated.\n", 3239 __func__); 3240 return; 3241 } 3242 3243 /* Allocate memory for Fibre Channel Event Buffer. */ 3244 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, 3245 GFP_KERNEL); 3246 if (!tc) { 3247 ql_log(ql_log_warn, vha, 0x00be, 3248 "Unable to allocate (%d KB) for FCE.\n", 3249 FCE_SIZE / 1024); 3250 return; 3251 } 3252 3253 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS, 3254 ha->fce_mb, &ha->fce_bufs); 3255 if (rval) { 3256 ql_log(ql_log_warn, vha, 0x00bf, 3257 "Unable to initialize FCE (%d).\n", rval); 3258 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc, tc_dma); 3259 return; 3260 } 3261 3262 ql_dbg(ql_dbg_init, vha, 0x00c0, 3263 "Allocated (%d KB) for FCE...\n", FCE_SIZE / 1024); 3264 3265 ha->flags.fce_enabled = 1; 3266 ha->fce_dma = tc_dma; 3267 ha->fce = tc; 3268 } 3269 3270 static void 3271 qla2x00_init_eft_trace(scsi_qla_host_t *vha) 3272 { 3273 int rval; 3274 dma_addr_t tc_dma; 3275 void *tc; 3276 struct qla_hw_data *ha = vha->hw; 3277 3278 if (!IS_FWI2_CAPABLE(ha)) 3279 return; 3280 3281 if (ha->eft) { 3282 ql_dbg(ql_dbg_init, vha, 0x00bd, 3283 "%s: EFT Mem is already allocated.\n", 3284 __func__); 3285 return; 3286 } 3287 3288 /* Allocate memory for Extended Trace Buffer. */ 3289 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma, 3290 GFP_KERNEL); 3291 if (!tc) { 3292 ql_log(ql_log_warn, vha, 0x00c1, 3293 "Unable to allocate (%d KB) for EFT.\n", 3294 EFT_SIZE / 1024); 3295 return; 3296 } 3297 3298 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS); 3299 if (rval) { 3300 ql_log(ql_log_warn, vha, 0x00c2, 3301 "Unable to initialize EFT (%d).\n", rval); 3302 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc, tc_dma); 3303 return; 3304 } 3305 3306 ql_dbg(ql_dbg_init, vha, 0x00c3, 3307 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024); 3308 3309 ha->eft_dma = tc_dma; 3310 ha->eft = tc; 3311 } 3312 3313 static void 3314 qla2x00_alloc_offload_mem(scsi_qla_host_t *vha) 3315 { 3316 qla2x00_init_fce_trace(vha); 3317 qla2x00_init_eft_trace(vha); 3318 } 3319 3320 void 3321 qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) 3322 { 3323 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, 3324 eft_size, fce_size, mq_size; 3325 struct qla_hw_data *ha = vha->hw; 3326 struct req_que *req = ha->req_q_map[0]; 3327 struct rsp_que *rsp = ha->rsp_q_map[0]; 3328 struct qla2xxx_fw_dump *fw_dump; 3329 3330 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; 3331 req_q_size = rsp_q_size = 0; 3332 3333 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3334 fixed_size = sizeof(struct qla2100_fw_dump); 3335 } else if (IS_QLA23XX(ha)) { 3336 fixed_size = offsetof(struct qla2300_fw_dump, data_ram); 3337 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 3338 sizeof(uint16_t); 3339 } else if (IS_FWI2_CAPABLE(ha)) { 3340 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3341 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem); 3342 else if (IS_QLA81XX(ha)) 3343 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); 3344 else if (IS_QLA25XX(ha)) 3345 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); 3346 else 3347 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); 3348 3349 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 3350 sizeof(uint32_t); 3351 if (ha->mqenable) { 3352 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && 3353 !IS_QLA28XX(ha)) 3354 mq_size = sizeof(struct qla2xxx_mq_chain); 3355 /* 3356 * Allocate maximum buffer size for all queues - Q0. 3357 * Resizing must be done at end-of-dump processing. 3358 */ 3359 mq_size += (ha->max_req_queues - 1) * 3360 (req->length * sizeof(request_t)); 3361 mq_size += (ha->max_rsp_queues - 1) * 3362 (rsp->length * sizeof(response_t)); 3363 } 3364 if (ha->tgt.atio_ring) 3365 mq_size += ha->tgt.atio_q_length * sizeof(request_t); 3366 3367 qla2x00_init_fce_trace(vha); 3368 if (ha->fce) 3369 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE; 3370 qla2x00_init_eft_trace(vha); 3371 if (ha->eft) 3372 eft_size = EFT_SIZE; 3373 } 3374 3375 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3376 struct fwdt *fwdt = ha->fwdt; 3377 uint j; 3378 3379 for (j = 0; j < 2; j++, fwdt++) { 3380 if (!fwdt->template) { 3381 ql_dbg(ql_dbg_init, vha, 0x00ba, 3382 "-> fwdt%u no template\n", j); 3383 continue; 3384 } 3385 ql_dbg(ql_dbg_init, vha, 0x00fa, 3386 "-> fwdt%u calculating fwdump size...\n", j); 3387 fwdt->dump_size = qla27xx_fwdt_calculate_dump_size( 3388 vha, fwdt->template); 3389 ql_dbg(ql_dbg_init, vha, 0x00fa, 3390 "-> fwdt%u calculated fwdump size = %#lx bytes\n", 3391 j, fwdt->dump_size); 3392 dump_size += fwdt->dump_size; 3393 } 3394 /* Add space for spare MPI fw dump. */ 3395 dump_size += ha->fwdt[1].dump_size; 3396 } else { 3397 req_q_size = req->length * sizeof(request_t); 3398 rsp_q_size = rsp->length * sizeof(response_t); 3399 dump_size = offsetof(struct qla2xxx_fw_dump, isp); 3400 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size 3401 + eft_size; 3402 ha->chain_offset = dump_size; 3403 dump_size += mq_size + fce_size; 3404 if (ha->exchoffld_buf) 3405 dump_size += sizeof(struct qla2xxx_offld_chain) + 3406 ha->exchoffld_size; 3407 if (ha->exlogin_buf) 3408 dump_size += sizeof(struct qla2xxx_offld_chain) + 3409 ha->exlogin_size; 3410 } 3411 3412 if (!ha->fw_dump_len || dump_size > ha->fw_dump_alloc_len) { 3413 3414 ql_dbg(ql_dbg_init, vha, 0x00c5, 3415 "%s dump_size %d fw_dump_len %d fw_dump_alloc_len %d\n", 3416 __func__, dump_size, ha->fw_dump_len, 3417 ha->fw_dump_alloc_len); 3418 3419 fw_dump = vmalloc(dump_size); 3420 if (!fw_dump) { 3421 ql_log(ql_log_warn, vha, 0x00c4, 3422 "Unable to allocate (%d KB) for firmware dump.\n", 3423 dump_size / 1024); 3424 } else { 3425 mutex_lock(&ha->optrom_mutex); 3426 if (ha->fw_dumped) { 3427 memcpy(fw_dump, ha->fw_dump, ha->fw_dump_len); 3428 vfree(ha->fw_dump); 3429 ha->fw_dump = fw_dump; 3430 ha->fw_dump_alloc_len = dump_size; 3431 ql_dbg(ql_dbg_init, vha, 0x00c5, 3432 "Re-Allocated (%d KB) and save firmware dump.\n", 3433 dump_size / 1024); 3434 } else { 3435 vfree(ha->fw_dump); 3436 ha->fw_dump = fw_dump; 3437 3438 ha->fw_dump_len = ha->fw_dump_alloc_len = 3439 dump_size; 3440 ql_dbg(ql_dbg_init, vha, 0x00c5, 3441 "Allocated (%d KB) for firmware dump.\n", 3442 dump_size / 1024); 3443 3444 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3445 ha->mpi_fw_dump = (char *)fw_dump + 3446 ha->fwdt[1].dump_size; 3447 mutex_unlock(&ha->optrom_mutex); 3448 return; 3449 } 3450 3451 ha->fw_dump->signature[0] = 'Q'; 3452 ha->fw_dump->signature[1] = 'L'; 3453 ha->fw_dump->signature[2] = 'G'; 3454 ha->fw_dump->signature[3] = 'C'; 3455 ha->fw_dump->version = htonl(1); 3456 3457 ha->fw_dump->fixed_size = htonl(fixed_size); 3458 ha->fw_dump->mem_size = htonl(mem_size); 3459 ha->fw_dump->req_q_size = htonl(req_q_size); 3460 ha->fw_dump->rsp_q_size = htonl(rsp_q_size); 3461 3462 ha->fw_dump->eft_size = htonl(eft_size); 3463 ha->fw_dump->eft_addr_l = 3464 htonl(LSD(ha->eft_dma)); 3465 ha->fw_dump->eft_addr_h = 3466 htonl(MSD(ha->eft_dma)); 3467 3468 ha->fw_dump->header_size = 3469 htonl(offsetof 3470 (struct qla2xxx_fw_dump, isp)); 3471 } 3472 mutex_unlock(&ha->optrom_mutex); 3473 } 3474 } 3475 } 3476 3477 static int 3478 qla81xx_mpi_sync(scsi_qla_host_t *vha) 3479 { 3480 #define MPS_MASK 0xe0 3481 int rval; 3482 uint16_t dc; 3483 uint32_t dw; 3484 3485 if (!IS_QLA81XX(vha->hw)) 3486 return QLA_SUCCESS; 3487 3488 rval = qla2x00_write_ram_word(vha, 0x7c00, 1); 3489 if (rval != QLA_SUCCESS) { 3490 ql_log(ql_log_warn, vha, 0x0105, 3491 "Unable to acquire semaphore.\n"); 3492 goto done; 3493 } 3494 3495 pci_read_config_word(vha->hw->pdev, 0x54, &dc); 3496 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw); 3497 if (rval != QLA_SUCCESS) { 3498 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n"); 3499 goto done_release; 3500 } 3501 3502 dc &= MPS_MASK; 3503 if (dc == (dw & MPS_MASK)) 3504 goto done_release; 3505 3506 dw &= ~MPS_MASK; 3507 dw |= dc; 3508 rval = qla2x00_write_ram_word(vha, 0x7a15, dw); 3509 if (rval != QLA_SUCCESS) { 3510 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n"); 3511 } 3512 3513 done_release: 3514 rval = qla2x00_write_ram_word(vha, 0x7c00, 0); 3515 if (rval != QLA_SUCCESS) { 3516 ql_log(ql_log_warn, vha, 0x006d, 3517 "Unable to release semaphore.\n"); 3518 } 3519 3520 done: 3521 return rval; 3522 } 3523 3524 int 3525 qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req) 3526 { 3527 /* Don't try to reallocate the array */ 3528 if (req->outstanding_cmds) 3529 return QLA_SUCCESS; 3530 3531 if (!IS_FWI2_CAPABLE(ha)) 3532 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS; 3533 else { 3534 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count) 3535 req->num_outstanding_cmds = ha->cur_fw_xcb_count; 3536 else 3537 req->num_outstanding_cmds = ha->cur_fw_iocb_count; 3538 } 3539 3540 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds, 3541 sizeof(srb_t *), 3542 GFP_KERNEL); 3543 3544 if (!req->outstanding_cmds) { 3545 /* 3546 * Try to allocate a minimal size just so we can get through 3547 * initialization. 3548 */ 3549 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS; 3550 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds, 3551 sizeof(srb_t *), 3552 GFP_KERNEL); 3553 3554 if (!req->outstanding_cmds) { 3555 ql_log(ql_log_fatal, NULL, 0x0126, 3556 "Failed to allocate memory for " 3557 "outstanding_cmds for req_que %p.\n", req); 3558 req->num_outstanding_cmds = 0; 3559 return QLA_FUNCTION_FAILED; 3560 } 3561 } 3562 3563 return QLA_SUCCESS; 3564 } 3565 3566 #define PRINT_FIELD(_field, _flag, _str) { \ 3567 if (a0->_field & _flag) {\ 3568 if (p) {\ 3569 strcat(ptr, "|");\ 3570 ptr++;\ 3571 leftover--;\ 3572 } \ 3573 len = snprintf(ptr, leftover, "%s", _str); \ 3574 p = 1;\ 3575 leftover -= len;\ 3576 ptr += len; \ 3577 } \ 3578 } 3579 3580 static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha) 3581 { 3582 #define STR_LEN 64 3583 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data; 3584 u8 str[STR_LEN], *ptr, p; 3585 int leftover, len; 3586 3587 memset(str, 0, STR_LEN); 3588 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name); 3589 ql_dbg(ql_dbg_init, vha, 0x015a, 3590 "SFP MFG Name: %s\n", str); 3591 3592 memset(str, 0, STR_LEN); 3593 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn); 3594 ql_dbg(ql_dbg_init, vha, 0x015c, 3595 "SFP Part Name: %s\n", str); 3596 3597 /* media */ 3598 memset(str, 0, STR_LEN); 3599 ptr = str; 3600 leftover = STR_LEN; 3601 p = len = 0; 3602 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX"); 3603 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair"); 3604 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax"); 3605 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax"); 3606 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um"); 3607 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um"); 3608 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode"); 3609 ql_dbg(ql_dbg_init, vha, 0x0160, 3610 "SFP Media: %s\n", str); 3611 3612 /* link length */ 3613 memset(str, 0, STR_LEN); 3614 ptr = str; 3615 leftover = STR_LEN; 3616 p = len = 0; 3617 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long"); 3618 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short"); 3619 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate"); 3620 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long"); 3621 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium"); 3622 ql_dbg(ql_dbg_init, vha, 0x0196, 3623 "SFP Link Length: %s\n", str); 3624 3625 memset(str, 0, STR_LEN); 3626 ptr = str; 3627 leftover = STR_LEN; 3628 p = len = 0; 3629 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)"); 3630 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)"); 3631 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)"); 3632 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)"); 3633 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)"); 3634 ql_dbg(ql_dbg_init, vha, 0x016e, 3635 "SFP FC Link Tech: %s\n", str); 3636 3637 if (a0->length_km) 3638 ql_dbg(ql_dbg_init, vha, 0x016f, 3639 "SFP Distant: %d km\n", a0->length_km); 3640 if (a0->length_100m) 3641 ql_dbg(ql_dbg_init, vha, 0x0170, 3642 "SFP Distant: %d m\n", a0->length_100m*100); 3643 if (a0->length_50um_10m) 3644 ql_dbg(ql_dbg_init, vha, 0x0189, 3645 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10); 3646 if (a0->length_62um_10m) 3647 ql_dbg(ql_dbg_init, vha, 0x018a, 3648 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10); 3649 if (a0->length_om4_10m) 3650 ql_dbg(ql_dbg_init, vha, 0x0194, 3651 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10); 3652 if (a0->length_om3_10m) 3653 ql_dbg(ql_dbg_init, vha, 0x0195, 3654 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10); 3655 } 3656 3657 3658 /** 3659 * qla24xx_detect_sfp() 3660 * 3661 * @vha: adapter state pointer. 3662 * 3663 * @return 3664 * 0 -- Configure firmware to use short-range settings -- normal 3665 * buffer-to-buffer credits. 3666 * 3667 * 1 -- Configure firmware to use long-range settings -- extra 3668 * buffer-to-buffer credits should be allocated with 3669 * ha->lr_distance containing distance settings from NVRAM or SFP 3670 * (if supported). 3671 */ 3672 int 3673 qla24xx_detect_sfp(scsi_qla_host_t *vha) 3674 { 3675 int rc, used_nvram; 3676 struct sff_8247_a0 *a; 3677 struct qla_hw_data *ha = vha->hw; 3678 struct nvram_81xx *nv = ha->nvram; 3679 #define LR_DISTANCE_UNKNOWN 2 3680 static const char * const types[] = { "Short", "Long" }; 3681 static const char * const lengths[] = { "(10km)", "(5km)", "" }; 3682 u8 ll = 0; 3683 3684 /* Seed with NVRAM settings. */ 3685 used_nvram = 0; 3686 ha->flags.lr_detected = 0; 3687 if (IS_BPM_RANGE_CAPABLE(ha) && 3688 (nv->enhanced_features & NEF_LR_DIST_ENABLE)) { 3689 used_nvram = 1; 3690 ha->flags.lr_detected = 1; 3691 ha->lr_distance = 3692 (nv->enhanced_features >> LR_DIST_NV_POS) 3693 & LR_DIST_NV_MASK; 3694 } 3695 3696 if (!IS_BPM_ENABLED(vha)) 3697 goto out; 3698 /* Determine SR/LR capabilities of SFP/Transceiver. */ 3699 rc = qla2x00_read_sfp_dev(vha, NULL, 0); 3700 if (rc) 3701 goto out; 3702 3703 used_nvram = 0; 3704 a = (struct sff_8247_a0 *)vha->hw->sfp_data; 3705 qla2xxx_print_sfp_info(vha); 3706 3707 ha->flags.lr_detected = 0; 3708 ll = a->fc_ll_cc7; 3709 if (ll & FC_LL_VL || ll & FC_LL_L) { 3710 /* Long range, track length. */ 3711 ha->flags.lr_detected = 1; 3712 3713 if (a->length_km > 5 || a->length_100m > 50) 3714 ha->lr_distance = LR_DISTANCE_10K; 3715 else 3716 ha->lr_distance = LR_DISTANCE_5K; 3717 } 3718 3719 out: 3720 ql_dbg(ql_dbg_async, vha, 0x507b, 3721 "SFP detect: %s-Range SFP %s (nvr=%x ll=%x lr=%x lrd=%x).\n", 3722 types[ha->flags.lr_detected], 3723 ha->flags.lr_detected ? lengths[ha->lr_distance] : 3724 lengths[LR_DISTANCE_UNKNOWN], 3725 used_nvram, ll, ha->flags.lr_detected, ha->lr_distance); 3726 return ha->flags.lr_detected; 3727 } 3728 3729 void qla_init_iocb_limit(scsi_qla_host_t *vha) 3730 { 3731 u16 i, num_qps; 3732 u32 limit; 3733 struct qla_hw_data *ha = vha->hw; 3734 3735 num_qps = ha->num_qpairs + 1; 3736 limit = (ha->orig_fw_iocb_count * QLA_IOCB_PCT_LIMIT) / 100; 3737 3738 ha->base_qpair->fwres.iocbs_total = ha->orig_fw_iocb_count; 3739 ha->base_qpair->fwres.iocbs_limit = limit; 3740 ha->base_qpair->fwres.iocbs_qp_limit = limit / num_qps; 3741 ha->base_qpair->fwres.iocbs_used = 0; 3742 for (i = 0; i < ha->max_qpairs; i++) { 3743 if (ha->queue_pair_map[i]) { 3744 ha->queue_pair_map[i]->fwres.iocbs_total = 3745 ha->orig_fw_iocb_count; 3746 ha->queue_pair_map[i]->fwres.iocbs_limit = limit; 3747 ha->queue_pair_map[i]->fwres.iocbs_qp_limit = 3748 limit / num_qps; 3749 ha->queue_pair_map[i]->fwres.iocbs_used = 0; 3750 } 3751 } 3752 } 3753 3754 /** 3755 * qla2x00_setup_chip() - Load and start RISC firmware. 3756 * @vha: HA context 3757 * 3758 * Returns 0 on success. 3759 */ 3760 static int 3761 qla2x00_setup_chip(scsi_qla_host_t *vha) 3762 { 3763 int rval; 3764 uint32_t srisc_address = 0; 3765 struct qla_hw_data *ha = vha->hw; 3766 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3767 unsigned long flags; 3768 uint16_t fw_major_version; 3769 int done_once = 0; 3770 3771 if (IS_P3P_TYPE(ha)) { 3772 rval = ha->isp_ops->load_risc(vha, &srisc_address); 3773 if (rval == QLA_SUCCESS) { 3774 qla2x00_stop_firmware(vha); 3775 goto enable_82xx_npiv; 3776 } else 3777 goto failed; 3778 } 3779 3780 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 3781 /* Disable SRAM, Instruction RAM and GP RAM parity. */ 3782 spin_lock_irqsave(&ha->hardware_lock, flags); 3783 wrt_reg_word(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); 3784 rd_reg_word(®->hccr); 3785 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3786 } 3787 3788 qla81xx_mpi_sync(vha); 3789 3790 execute_fw_with_lr: 3791 /* Load firmware sequences */ 3792 rval = ha->isp_ops->load_risc(vha, &srisc_address); 3793 if (rval == QLA_SUCCESS) { 3794 ql_dbg(ql_dbg_init, vha, 0x00c9, 3795 "Verifying Checksum of loaded RISC code.\n"); 3796 3797 rval = qla2x00_verify_checksum(vha, srisc_address); 3798 if (rval == QLA_SUCCESS) { 3799 /* Start firmware execution. */ 3800 ql_dbg(ql_dbg_init, vha, 0x00ca, 3801 "Starting firmware.\n"); 3802 3803 if (ql2xexlogins) 3804 ha->flags.exlogins_enabled = 1; 3805 3806 if (qla_is_exch_offld_enabled(vha)) 3807 ha->flags.exchoffld_enabled = 1; 3808 3809 rval = qla2x00_execute_fw(vha, srisc_address); 3810 /* Retrieve firmware information. */ 3811 if (rval == QLA_SUCCESS) { 3812 /* Enable BPM support? */ 3813 if (!done_once++ && qla24xx_detect_sfp(vha)) { 3814 ql_dbg(ql_dbg_init, vha, 0x00ca, 3815 "Re-starting firmware -- BPM.\n"); 3816 /* Best-effort - re-init. */ 3817 ha->isp_ops->reset_chip(vha); 3818 ha->isp_ops->chip_diag(vha); 3819 goto execute_fw_with_lr; 3820 } 3821 3822 if (IS_ZIO_THRESHOLD_CAPABLE(ha)) 3823 qla27xx_set_zio_threshold(vha, 3824 ha->last_zio_threshold); 3825 3826 rval = qla2x00_set_exlogins_buffer(vha); 3827 if (rval != QLA_SUCCESS) 3828 goto failed; 3829 3830 rval = qla2x00_set_exchoffld_buffer(vha); 3831 if (rval != QLA_SUCCESS) 3832 goto failed; 3833 3834 enable_82xx_npiv: 3835 fw_major_version = ha->fw_major_version; 3836 if (IS_P3P_TYPE(ha)) 3837 qla82xx_check_md_needed(vha); 3838 else 3839 rval = qla2x00_get_fw_version(vha); 3840 if (rval != QLA_SUCCESS) 3841 goto failed; 3842 ha->flags.npiv_supported = 0; 3843 if (IS_QLA2XXX_MIDTYPE(ha) && 3844 (ha->fw_attributes & BIT_2)) { 3845 ha->flags.npiv_supported = 1; 3846 if ((!ha->max_npiv_vports) || 3847 ((ha->max_npiv_vports + 1) % 3848 MIN_MULTI_ID_FABRIC)) 3849 ha->max_npiv_vports = 3850 MIN_MULTI_ID_FABRIC - 1; 3851 } 3852 qla2x00_get_resource_cnts(vha); 3853 qla_init_iocb_limit(vha); 3854 3855 /* 3856 * Allocate the array of outstanding commands 3857 * now that we know the firmware resources. 3858 */ 3859 rval = qla2x00_alloc_outstanding_cmds(ha, 3860 vha->req); 3861 if (rval != QLA_SUCCESS) 3862 goto failed; 3863 3864 if (!fw_major_version && !(IS_P3P_TYPE(ha))) 3865 qla2x00_alloc_offload_mem(vha); 3866 3867 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha))) 3868 qla2x00_alloc_fw_dump(vha); 3869 3870 } else { 3871 goto failed; 3872 } 3873 } else { 3874 ql_log(ql_log_fatal, vha, 0x00cd, 3875 "ISP Firmware failed checksum.\n"); 3876 goto failed; 3877 } 3878 3879 /* Enable PUREX PASSTHRU */ 3880 if (ql2xrdpenable || ha->flags.scm_supported_f) 3881 qla25xx_set_els_cmds_supported(vha); 3882 } else 3883 goto failed; 3884 3885 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 3886 /* Enable proper parity. */ 3887 spin_lock_irqsave(&ha->hardware_lock, flags); 3888 if (IS_QLA2300(ha)) 3889 /* SRAM parity */ 3890 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x1); 3891 else 3892 /* SRAM, Instruction RAM and GP RAM parity */ 3893 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x7); 3894 rd_reg_word(®->hccr); 3895 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3896 } 3897 3898 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3899 ha->flags.fac_supported = 1; 3900 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { 3901 uint32_t size; 3902 3903 rval = qla81xx_fac_get_sector_size(vha, &size); 3904 if (rval == QLA_SUCCESS) { 3905 ha->flags.fac_supported = 1; 3906 ha->fdt_block_size = size << 2; 3907 } else { 3908 ql_log(ql_log_warn, vha, 0x00ce, 3909 "Unsupported FAC firmware (%d.%02d.%02d).\n", 3910 ha->fw_major_version, ha->fw_minor_version, 3911 ha->fw_subminor_version); 3912 3913 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3914 IS_QLA28XX(ha)) { 3915 ha->flags.fac_supported = 0; 3916 rval = QLA_SUCCESS; 3917 } 3918 } 3919 } 3920 failed: 3921 if (rval) { 3922 ql_log(ql_log_fatal, vha, 0x00cf, 3923 "Setup chip ****FAILED****.\n"); 3924 } 3925 3926 return (rval); 3927 } 3928 3929 /** 3930 * qla2x00_init_response_q_entries() - Initializes response queue entries. 3931 * @rsp: response queue 3932 * 3933 * Beginning of request ring has initialization control block already built 3934 * by nvram config routine. 3935 * 3936 * Returns 0 on success. 3937 */ 3938 void 3939 qla2x00_init_response_q_entries(struct rsp_que *rsp) 3940 { 3941 uint16_t cnt; 3942 response_t *pkt; 3943 3944 rsp->ring_ptr = rsp->ring; 3945 rsp->ring_index = 0; 3946 rsp->status_srb = NULL; 3947 pkt = rsp->ring_ptr; 3948 for (cnt = 0; cnt < rsp->length; cnt++) { 3949 pkt->signature = RESPONSE_PROCESSED; 3950 pkt++; 3951 } 3952 } 3953 3954 /** 3955 * qla2x00_update_fw_options() - Read and process firmware options. 3956 * @vha: HA context 3957 * 3958 * Returns 0 on success. 3959 */ 3960 void 3961 qla2x00_update_fw_options(scsi_qla_host_t *vha) 3962 { 3963 uint16_t swing, emphasis, tx_sens, rx_sens; 3964 struct qla_hw_data *ha = vha->hw; 3965 3966 memset(ha->fw_options, 0, sizeof(ha->fw_options)); 3967 qla2x00_get_fw_options(vha, ha->fw_options); 3968 3969 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 3970 return; 3971 3972 /* Serial Link options. */ 3973 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115, 3974 "Serial link options.\n"); 3975 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109, 3976 ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options)); 3977 3978 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 3979 if (ha->fw_seriallink_options[3] & BIT_2) { 3980 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING; 3981 3982 /* 1G settings */ 3983 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); 3984 emphasis = (ha->fw_seriallink_options[2] & 3985 (BIT_4 | BIT_3)) >> 3; 3986 tx_sens = ha->fw_seriallink_options[0] & 3987 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 3988 rx_sens = (ha->fw_seriallink_options[0] & 3989 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 3990 ha->fw_options[10] = (emphasis << 14) | (swing << 8); 3991 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 3992 if (rx_sens == 0x0) 3993 rx_sens = 0x3; 3994 ha->fw_options[10] |= (tx_sens << 4) | rx_sens; 3995 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3996 ha->fw_options[10] |= BIT_5 | 3997 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 3998 (tx_sens & (BIT_1 | BIT_0)); 3999 4000 /* 2G settings */ 4001 swing = (ha->fw_seriallink_options[2] & 4002 (BIT_7 | BIT_6 | BIT_5)) >> 5; 4003 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); 4004 tx_sens = ha->fw_seriallink_options[1] & 4005 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 4006 rx_sens = (ha->fw_seriallink_options[1] & 4007 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 4008 ha->fw_options[11] = (emphasis << 14) | (swing << 8); 4009 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 4010 if (rx_sens == 0x0) 4011 rx_sens = 0x3; 4012 ha->fw_options[11] |= (tx_sens << 4) | rx_sens; 4013 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 4014 ha->fw_options[11] |= BIT_5 | 4015 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 4016 (tx_sens & (BIT_1 | BIT_0)); 4017 } 4018 4019 /* FCP2 options. */ 4020 /* Return command IOCBs without waiting for an ABTS to complete. */ 4021 ha->fw_options[3] |= BIT_13; 4022 4023 /* LED scheme. */ 4024 if (ha->flags.enable_led_scheme) 4025 ha->fw_options[2] |= BIT_12; 4026 4027 /* Detect ISP6312. */ 4028 if (IS_QLA6312(ha)) 4029 ha->fw_options[2] |= BIT_13; 4030 4031 /* Set Retry FLOGI in case of P2P connection */ 4032 if (ha->operating_mode == P2P) { 4033 ha->fw_options[2] |= BIT_3; 4034 ql_dbg(ql_dbg_disc, vha, 0x2100, 4035 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 4036 __func__, ha->fw_options[2]); 4037 } 4038 4039 /* Update firmware options. */ 4040 qla2x00_set_fw_options(vha, ha->fw_options); 4041 } 4042 4043 void 4044 qla24xx_update_fw_options(scsi_qla_host_t *vha) 4045 { 4046 int rval; 4047 struct qla_hw_data *ha = vha->hw; 4048 4049 if (IS_P3P_TYPE(ha)) 4050 return; 4051 4052 /* Hold status IOCBs until ABTS response received. */ 4053 if (ql2xfwholdabts) 4054 ha->fw_options[3] |= BIT_12; 4055 4056 /* Set Retry FLOGI in case of P2P connection */ 4057 if (ha->operating_mode == P2P) { 4058 ha->fw_options[2] |= BIT_3; 4059 ql_dbg(ql_dbg_disc, vha, 0x2101, 4060 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 4061 __func__, ha->fw_options[2]); 4062 } 4063 4064 /* Move PUREX, ABTS RX & RIDA to ATIOQ */ 4065 if (ql2xmvasynctoatio && 4066 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) { 4067 if (qla_tgt_mode_enabled(vha) || 4068 qla_dual_mode_enabled(vha)) 4069 ha->fw_options[2] |= BIT_11; 4070 else 4071 ha->fw_options[2] &= ~BIT_11; 4072 } 4073 4074 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 4075 IS_QLA28XX(ha)) { 4076 /* 4077 * Tell FW to track each exchange to prevent 4078 * driver from using stale exchange. 4079 */ 4080 if (qla_tgt_mode_enabled(vha) || 4081 qla_dual_mode_enabled(vha)) 4082 ha->fw_options[2] |= BIT_4; 4083 else 4084 ha->fw_options[2] &= ~BIT_4; 4085 4086 /* Reserve 1/2 of emergency exchanges for ELS.*/ 4087 if (qla2xuseresexchforels) 4088 ha->fw_options[2] |= BIT_8; 4089 else 4090 ha->fw_options[2] &= ~BIT_8; 4091 } 4092 4093 if (ql2xrdpenable || ha->flags.scm_supported_f) 4094 ha->fw_options[1] |= ADD_FO1_ENABLE_PUREX_IOCB; 4095 4096 /* Enable Async 8130/8131 events -- transceiver insertion/removal */ 4097 if (IS_BPM_RANGE_CAPABLE(ha)) 4098 ha->fw_options[3] |= BIT_10; 4099 4100 ql_dbg(ql_dbg_init, vha, 0x00e8, 4101 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n", 4102 __func__, ha->fw_options[1], ha->fw_options[2], 4103 ha->fw_options[3], vha->host->active_mode); 4104 4105 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3]) 4106 qla2x00_set_fw_options(vha, ha->fw_options); 4107 4108 /* Update Serial Link options. */ 4109 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) 4110 return; 4111 4112 rval = qla2x00_set_serdes_params(vha, 4113 le16_to_cpu(ha->fw_seriallink_options24[1]), 4114 le16_to_cpu(ha->fw_seriallink_options24[2]), 4115 le16_to_cpu(ha->fw_seriallink_options24[3])); 4116 if (rval != QLA_SUCCESS) { 4117 ql_log(ql_log_warn, vha, 0x0104, 4118 "Unable to update Serial Link options (%x).\n", rval); 4119 } 4120 } 4121 4122 void 4123 qla2x00_config_rings(struct scsi_qla_host *vha) 4124 { 4125 struct qla_hw_data *ha = vha->hw; 4126 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4127 struct req_que *req = ha->req_q_map[0]; 4128 struct rsp_que *rsp = ha->rsp_q_map[0]; 4129 4130 /* Setup ring parameters in initialization control block. */ 4131 ha->init_cb->request_q_outpointer = cpu_to_le16(0); 4132 ha->init_cb->response_q_inpointer = cpu_to_le16(0); 4133 ha->init_cb->request_q_length = cpu_to_le16(req->length); 4134 ha->init_cb->response_q_length = cpu_to_le16(rsp->length); 4135 put_unaligned_le64(req->dma, &ha->init_cb->request_q_address); 4136 put_unaligned_le64(rsp->dma, &ha->init_cb->response_q_address); 4137 4138 wrt_reg_word(ISP_REQ_Q_IN(ha, reg), 0); 4139 wrt_reg_word(ISP_REQ_Q_OUT(ha, reg), 0); 4140 wrt_reg_word(ISP_RSP_Q_IN(ha, reg), 0); 4141 wrt_reg_word(ISP_RSP_Q_OUT(ha, reg), 0); 4142 rd_reg_word(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ 4143 } 4144 4145 void 4146 qla24xx_config_rings(struct scsi_qla_host *vha) 4147 { 4148 struct qla_hw_data *ha = vha->hw; 4149 device_reg_t *reg = ISP_QUE_REG(ha, 0); 4150 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; 4151 struct qla_msix_entry *msix; 4152 struct init_cb_24xx *icb; 4153 uint16_t rid = 0; 4154 struct req_que *req = ha->req_q_map[0]; 4155 struct rsp_que *rsp = ha->rsp_q_map[0]; 4156 4157 /* Setup ring parameters in initialization control block. */ 4158 icb = (struct init_cb_24xx *)ha->init_cb; 4159 icb->request_q_outpointer = cpu_to_le16(0); 4160 icb->response_q_inpointer = cpu_to_le16(0); 4161 icb->request_q_length = cpu_to_le16(req->length); 4162 icb->response_q_length = cpu_to_le16(rsp->length); 4163 put_unaligned_le64(req->dma, &icb->request_q_address); 4164 put_unaligned_le64(rsp->dma, &icb->response_q_address); 4165 4166 /* Setup ATIO queue dma pointers for target mode */ 4167 icb->atio_q_inpointer = cpu_to_le16(0); 4168 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length); 4169 put_unaligned_le64(ha->tgt.atio_dma, &icb->atio_q_address); 4170 4171 if (IS_SHADOW_REG_CAPABLE(ha)) 4172 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29); 4173 4174 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 4175 IS_QLA28XX(ha)) { 4176 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS); 4177 icb->rid = cpu_to_le16(rid); 4178 if (ha->flags.msix_enabled) { 4179 msix = &ha->msix_entries[1]; 4180 ql_dbg(ql_dbg_init, vha, 0x0019, 4181 "Registering vector 0x%x for base que.\n", 4182 msix->entry); 4183 icb->msix = cpu_to_le16(msix->entry); 4184 } 4185 /* Use alternate PCI bus number */ 4186 if (MSB(rid)) 4187 icb->firmware_options_2 |= cpu_to_le32(BIT_19); 4188 /* Use alternate PCI devfn */ 4189 if (LSB(rid)) 4190 icb->firmware_options_2 |= cpu_to_le32(BIT_18); 4191 4192 /* Use Disable MSIX Handshake mode for capable adapters */ 4193 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) && 4194 (ha->flags.msix_enabled)) { 4195 icb->firmware_options_2 &= cpu_to_le32(~BIT_22); 4196 ha->flags.disable_msix_handshake = 1; 4197 ql_dbg(ql_dbg_init, vha, 0x00fe, 4198 "MSIX Handshake Disable Mode turned on.\n"); 4199 } else { 4200 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 4201 } 4202 icb->firmware_options_2 |= cpu_to_le32(BIT_23); 4203 4204 wrt_reg_dword(®->isp25mq.req_q_in, 0); 4205 wrt_reg_dword(®->isp25mq.req_q_out, 0); 4206 wrt_reg_dword(®->isp25mq.rsp_q_in, 0); 4207 wrt_reg_dword(®->isp25mq.rsp_q_out, 0); 4208 } else { 4209 wrt_reg_dword(®->isp24.req_q_in, 0); 4210 wrt_reg_dword(®->isp24.req_q_out, 0); 4211 wrt_reg_dword(®->isp24.rsp_q_in, 0); 4212 wrt_reg_dword(®->isp24.rsp_q_out, 0); 4213 } 4214 4215 qlt_24xx_config_rings(vha); 4216 4217 /* If the user has configured the speed, set it here */ 4218 if (ha->set_data_rate) { 4219 ql_dbg(ql_dbg_init, vha, 0x00fd, 4220 "Speed set by user : %s Gbps \n", 4221 qla2x00_get_link_speed_str(ha, ha->set_data_rate)); 4222 icb->firmware_options_3 = cpu_to_le32(ha->set_data_rate << 13); 4223 } 4224 4225 /* PCI posting */ 4226 rd_reg_word(&ioreg->hccr); 4227 } 4228 4229 /** 4230 * qla2x00_init_rings() - Initializes firmware. 4231 * @vha: HA context 4232 * 4233 * Beginning of request ring has initialization control block already built 4234 * by nvram config routine. 4235 * 4236 * Returns 0 on success. 4237 */ 4238 int 4239 qla2x00_init_rings(scsi_qla_host_t *vha) 4240 { 4241 int rval; 4242 unsigned long flags = 0; 4243 int cnt, que; 4244 struct qla_hw_data *ha = vha->hw; 4245 struct req_que *req; 4246 struct rsp_que *rsp; 4247 struct mid_init_cb_24xx *mid_init_cb = 4248 (struct mid_init_cb_24xx *) ha->init_cb; 4249 4250 spin_lock_irqsave(&ha->hardware_lock, flags); 4251 4252 /* Clear outstanding commands array. */ 4253 for (que = 0; que < ha->max_req_queues; que++) { 4254 req = ha->req_q_map[que]; 4255 if (!req || !test_bit(que, ha->req_qid_map)) 4256 continue; 4257 req->out_ptr = (uint16_t *)(req->ring + req->length); 4258 *req->out_ptr = 0; 4259 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) 4260 req->outstanding_cmds[cnt] = NULL; 4261 4262 req->current_outstanding_cmd = 1; 4263 4264 /* Initialize firmware. */ 4265 req->ring_ptr = req->ring; 4266 req->ring_index = 0; 4267 req->cnt = req->length; 4268 } 4269 4270 for (que = 0; que < ha->max_rsp_queues; que++) { 4271 rsp = ha->rsp_q_map[que]; 4272 if (!rsp || !test_bit(que, ha->rsp_qid_map)) 4273 continue; 4274 rsp->in_ptr = (uint16_t *)(rsp->ring + rsp->length); 4275 *rsp->in_ptr = 0; 4276 /* Initialize response queue entries */ 4277 if (IS_QLAFX00(ha)) 4278 qlafx00_init_response_q_entries(rsp); 4279 else 4280 qla2x00_init_response_q_entries(rsp); 4281 } 4282 4283 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring; 4284 ha->tgt.atio_ring_index = 0; 4285 /* Initialize ATIO queue entries */ 4286 qlt_init_atio_q_entries(vha); 4287 4288 ha->isp_ops->config_rings(vha); 4289 4290 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4291 4292 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n"); 4293 4294 if (IS_QLAFX00(ha)) { 4295 rval = qlafx00_init_firmware(vha, ha->init_cb_size); 4296 goto next_check; 4297 } 4298 4299 /* Update any ISP specific firmware options before initialization. */ 4300 ha->isp_ops->update_fw_options(vha); 4301 4302 if (ha->flags.npiv_supported) { 4303 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha)) 4304 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; 4305 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); 4306 } 4307 4308 if (IS_FWI2_CAPABLE(ha)) { 4309 mid_init_cb->options = cpu_to_le16(BIT_1); 4310 mid_init_cb->init_cb.execution_throttle = 4311 cpu_to_le16(ha->cur_fw_xcb_count); 4312 ha->flags.dport_enabled = 4313 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) & 4314 BIT_7) != 0; 4315 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n", 4316 (ha->flags.dport_enabled) ? "enabled" : "disabled"); 4317 /* FA-WWPN Status */ 4318 ha->flags.fawwpn_enabled = 4319 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) & 4320 BIT_6) != 0; 4321 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n", 4322 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled"); 4323 } 4324 4325 rval = qla2x00_init_firmware(vha, ha->init_cb_size); 4326 next_check: 4327 if (rval) { 4328 ql_log(ql_log_fatal, vha, 0x00d2, 4329 "Init Firmware **** FAILED ****.\n"); 4330 } else { 4331 ql_dbg(ql_dbg_init, vha, 0x00d3, 4332 "Init Firmware -- success.\n"); 4333 QLA_FW_STARTED(ha); 4334 vha->u_ql2xexchoffld = vha->u_ql2xiniexchg = 0; 4335 } 4336 4337 return (rval); 4338 } 4339 4340 /** 4341 * qla2x00_fw_ready() - Waits for firmware ready. 4342 * @vha: HA context 4343 * 4344 * Returns 0 on success. 4345 */ 4346 static int 4347 qla2x00_fw_ready(scsi_qla_host_t *vha) 4348 { 4349 int rval; 4350 unsigned long wtime, mtime, cs84xx_time; 4351 uint16_t min_wait; /* Minimum wait time if loop is down */ 4352 uint16_t wait_time; /* Wait time if loop is coming ready */ 4353 uint16_t state[6]; 4354 struct qla_hw_data *ha = vha->hw; 4355 4356 if (IS_QLAFX00(vha->hw)) 4357 return qlafx00_fw_ready(vha); 4358 4359 rval = QLA_SUCCESS; 4360 4361 /* Time to wait for loop down */ 4362 if (IS_P3P_TYPE(ha)) 4363 min_wait = 30; 4364 else 4365 min_wait = 20; 4366 4367 /* 4368 * Firmware should take at most one RATOV to login, plus 5 seconds for 4369 * our own processing. 4370 */ 4371 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) { 4372 wait_time = min_wait; 4373 } 4374 4375 /* Min wait time if loop down */ 4376 mtime = jiffies + (min_wait * HZ); 4377 4378 /* wait time before firmware ready */ 4379 wtime = jiffies + (wait_time * HZ); 4380 4381 /* Wait for ISP to finish LIP */ 4382 if (!vha->flags.init_done) 4383 ql_log(ql_log_info, vha, 0x801e, 4384 "Waiting for LIP to complete.\n"); 4385 4386 do { 4387 memset(state, -1, sizeof(state)); 4388 rval = qla2x00_get_firmware_state(vha, state); 4389 if (rval == QLA_SUCCESS) { 4390 if (state[0] < FSTATE_LOSS_OF_SYNC) { 4391 vha->device_flags &= ~DFLG_NO_CABLE; 4392 } 4393 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) { 4394 ql_dbg(ql_dbg_taskm, vha, 0x801f, 4395 "fw_state=%x 84xx=%x.\n", state[0], 4396 state[2]); 4397 if ((state[2] & FSTATE_LOGGED_IN) && 4398 (state[2] & FSTATE_WAITING_FOR_VERIFY)) { 4399 ql_dbg(ql_dbg_taskm, vha, 0x8028, 4400 "Sending verify iocb.\n"); 4401 4402 cs84xx_time = jiffies; 4403 rval = qla84xx_init_chip(vha); 4404 if (rval != QLA_SUCCESS) { 4405 ql_log(ql_log_warn, 4406 vha, 0x8007, 4407 "Init chip failed.\n"); 4408 break; 4409 } 4410 4411 /* Add time taken to initialize. */ 4412 cs84xx_time = jiffies - cs84xx_time; 4413 wtime += cs84xx_time; 4414 mtime += cs84xx_time; 4415 ql_dbg(ql_dbg_taskm, vha, 0x8008, 4416 "Increasing wait time by %ld. " 4417 "New time %ld.\n", cs84xx_time, 4418 wtime); 4419 } 4420 } else if (state[0] == FSTATE_READY) { 4421 ql_dbg(ql_dbg_taskm, vha, 0x8037, 4422 "F/W Ready - OK.\n"); 4423 4424 qla2x00_get_retry_cnt(vha, &ha->retry_count, 4425 &ha->login_timeout, &ha->r_a_tov); 4426 4427 rval = QLA_SUCCESS; 4428 break; 4429 } 4430 4431 rval = QLA_FUNCTION_FAILED; 4432 4433 if (atomic_read(&vha->loop_down_timer) && 4434 state[0] != FSTATE_READY) { 4435 /* Loop down. Timeout on min_wait for states 4436 * other than Wait for Login. 4437 */ 4438 if (time_after_eq(jiffies, mtime)) { 4439 ql_log(ql_log_info, vha, 0x8038, 4440 "Cable is unplugged...\n"); 4441 4442 vha->device_flags |= DFLG_NO_CABLE; 4443 break; 4444 } 4445 } 4446 } else { 4447 /* Mailbox cmd failed. Timeout on min_wait. */ 4448 if (time_after_eq(jiffies, mtime) || 4449 ha->flags.isp82xx_fw_hung) 4450 break; 4451 } 4452 4453 if (time_after_eq(jiffies, wtime)) 4454 break; 4455 4456 /* Delay for a while */ 4457 msleep(500); 4458 } while (1); 4459 4460 ql_dbg(ql_dbg_taskm, vha, 0x803a, 4461 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0], 4462 state[1], state[2], state[3], state[4], state[5], jiffies); 4463 4464 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) { 4465 ql_log(ql_log_warn, vha, 0x803b, 4466 "Firmware ready **** FAILED ****.\n"); 4467 } 4468 4469 return (rval); 4470 } 4471 4472 /* 4473 * qla2x00_configure_hba 4474 * Setup adapter context. 4475 * 4476 * Input: 4477 * ha = adapter state pointer. 4478 * 4479 * Returns: 4480 * 0 = success 4481 * 4482 * Context: 4483 * Kernel context. 4484 */ 4485 static int 4486 qla2x00_configure_hba(scsi_qla_host_t *vha) 4487 { 4488 int rval; 4489 uint16_t loop_id; 4490 uint16_t topo; 4491 uint16_t sw_cap; 4492 uint8_t al_pa; 4493 uint8_t area; 4494 uint8_t domain; 4495 char connect_type[22]; 4496 struct qla_hw_data *ha = vha->hw; 4497 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4498 port_id_t id; 4499 unsigned long flags; 4500 4501 /* Get host addresses. */ 4502 rval = qla2x00_get_adapter_id(vha, 4503 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); 4504 if (rval != QLA_SUCCESS) { 4505 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || 4506 IS_CNA_CAPABLE(ha) || 4507 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { 4508 ql_dbg(ql_dbg_disc, vha, 0x2008, 4509 "Loop is in a transition state.\n"); 4510 } else { 4511 ql_log(ql_log_warn, vha, 0x2009, 4512 "Unable to get host loop ID.\n"); 4513 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) && 4514 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) { 4515 ql_log(ql_log_warn, vha, 0x1151, 4516 "Doing link init.\n"); 4517 if (qla24xx_link_initialize(vha) == QLA_SUCCESS) 4518 return rval; 4519 } 4520 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 4521 } 4522 return (rval); 4523 } 4524 4525 if (topo == 4) { 4526 ql_log(ql_log_info, vha, 0x200a, 4527 "Cannot get topology - retrying.\n"); 4528 return (QLA_FUNCTION_FAILED); 4529 } 4530 4531 vha->loop_id = loop_id; 4532 4533 /* initialize */ 4534 ha->min_external_loopid = SNS_FIRST_LOOP_ID; 4535 ha->operating_mode = LOOP; 4536 ha->switch_cap = 0; 4537 4538 switch (topo) { 4539 case 0: 4540 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n"); 4541 ha->current_topology = ISP_CFG_NL; 4542 strcpy(connect_type, "(Loop)"); 4543 break; 4544 4545 case 1: 4546 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n"); 4547 ha->switch_cap = sw_cap; 4548 ha->current_topology = ISP_CFG_FL; 4549 strcpy(connect_type, "(FL_Port)"); 4550 break; 4551 4552 case 2: 4553 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n"); 4554 ha->operating_mode = P2P; 4555 ha->current_topology = ISP_CFG_N; 4556 strcpy(connect_type, "(N_Port-to-N_Port)"); 4557 break; 4558 4559 case 3: 4560 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n"); 4561 ha->switch_cap = sw_cap; 4562 ha->operating_mode = P2P; 4563 ha->current_topology = ISP_CFG_F; 4564 strcpy(connect_type, "(F_Port)"); 4565 break; 4566 4567 default: 4568 ql_dbg(ql_dbg_disc, vha, 0x200f, 4569 "HBA in unknown topology %x, using NL.\n", topo); 4570 ha->current_topology = ISP_CFG_NL; 4571 strcpy(connect_type, "(Loop)"); 4572 break; 4573 } 4574 4575 /* Save Host port and loop ID. */ 4576 /* byte order - Big Endian */ 4577 id.b.domain = domain; 4578 id.b.area = area; 4579 id.b.al_pa = al_pa; 4580 id.b.rsvd_1 = 0; 4581 spin_lock_irqsave(&ha->hardware_lock, flags); 4582 if (!(topo == 2 && ha->flags.n2n_bigger)) 4583 qlt_update_host_map(vha, id); 4584 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4585 4586 if (!vha->flags.init_done) 4587 ql_log(ql_log_info, vha, 0x2010, 4588 "Topology - %s, Host Loop address 0x%x.\n", 4589 connect_type, vha->loop_id); 4590 4591 return(rval); 4592 } 4593 4594 inline void 4595 qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, 4596 const char *def) 4597 { 4598 char *st, *en; 4599 uint16_t index; 4600 uint64_t zero[2] = { 0 }; 4601 struct qla_hw_data *ha = vha->hw; 4602 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 4603 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha); 4604 4605 if (len > sizeof(zero)) 4606 len = sizeof(zero); 4607 if (memcmp(model, &zero, len) != 0) { 4608 memcpy(ha->model_number, model, len); 4609 st = en = ha->model_number; 4610 en += len - 1; 4611 while (en > st) { 4612 if (*en != 0x20 && *en != 0x00) 4613 break; 4614 *en-- = '\0'; 4615 } 4616 4617 index = (ha->pdev->subsystem_device & 0xff); 4618 if (use_tbl && 4619 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 4620 index < QLA_MODEL_NAMES) 4621 strlcpy(ha->model_desc, 4622 qla2x00_model_name[index * 2 + 1], 4623 sizeof(ha->model_desc)); 4624 } else { 4625 index = (ha->pdev->subsystem_device & 0xff); 4626 if (use_tbl && 4627 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 4628 index < QLA_MODEL_NAMES) { 4629 strlcpy(ha->model_number, 4630 qla2x00_model_name[index * 2], 4631 sizeof(ha->model_number)); 4632 strlcpy(ha->model_desc, 4633 qla2x00_model_name[index * 2 + 1], 4634 sizeof(ha->model_desc)); 4635 } else { 4636 strlcpy(ha->model_number, def, 4637 sizeof(ha->model_number)); 4638 } 4639 } 4640 if (IS_FWI2_CAPABLE(ha)) 4641 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc, 4642 sizeof(ha->model_desc)); 4643 } 4644 4645 /* On sparc systems, obtain port and node WWN from firmware 4646 * properties. 4647 */ 4648 static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv) 4649 { 4650 #ifdef CONFIG_SPARC 4651 struct qla_hw_data *ha = vha->hw; 4652 struct pci_dev *pdev = ha->pdev; 4653 struct device_node *dp = pci_device_to_OF_node(pdev); 4654 const u8 *val; 4655 int len; 4656 4657 val = of_get_property(dp, "port-wwn", &len); 4658 if (val && len >= WWN_SIZE) 4659 memcpy(nv->port_name, val, WWN_SIZE); 4660 4661 val = of_get_property(dp, "node-wwn", &len); 4662 if (val && len >= WWN_SIZE) 4663 memcpy(nv->node_name, val, WWN_SIZE); 4664 #endif 4665 } 4666 4667 /* 4668 * NVRAM configuration for ISP 2xxx 4669 * 4670 * Input: 4671 * ha = adapter block pointer. 4672 * 4673 * Output: 4674 * initialization control block in response_ring 4675 * host adapters parameters in host adapter block 4676 * 4677 * Returns: 4678 * 0 = success. 4679 */ 4680 int 4681 qla2x00_nvram_config(scsi_qla_host_t *vha) 4682 { 4683 int rval; 4684 uint8_t chksum = 0; 4685 uint16_t cnt; 4686 uint8_t *dptr1, *dptr2; 4687 struct qla_hw_data *ha = vha->hw; 4688 init_cb_t *icb = ha->init_cb; 4689 nvram_t *nv = ha->nvram; 4690 uint8_t *ptr = ha->nvram; 4691 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4692 4693 rval = QLA_SUCCESS; 4694 4695 /* Determine NVRAM starting address. */ 4696 ha->nvram_size = sizeof(*nv); 4697 ha->nvram_base = 0; 4698 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) 4699 if ((rd_reg_word(®->ctrl_status) >> 14) == 1) 4700 ha->nvram_base = 0x80; 4701 4702 /* Get NVRAM data and calculate checksum. */ 4703 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size); 4704 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) 4705 chksum += *ptr++; 4706 4707 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f, 4708 "Contents of NVRAM.\n"); 4709 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110, 4710 nv, ha->nvram_size); 4711 4712 /* Bad NVRAM data, set defaults parameters. */ 4713 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 4714 nv->nvram_version < 1) { 4715 /* Reset NVRAM data. */ 4716 ql_log(ql_log_warn, vha, 0x0064, 4717 "Inconsistent NVRAM detected: checksum=%#x id=%.4s version=%#x.\n", 4718 chksum, nv->id, nv->nvram_version); 4719 ql_log(ql_log_warn, vha, 0x0065, 4720 "Falling back to " 4721 "functioning (yet invalid -- WWPN) defaults.\n"); 4722 4723 /* 4724 * Set default initialization control block. 4725 */ 4726 memset(nv, 0, ha->nvram_size); 4727 nv->parameter_block_version = ICB_VERSION; 4728 4729 if (IS_QLA23XX(ha)) { 4730 nv->firmware_options[0] = BIT_2 | BIT_1; 4731 nv->firmware_options[1] = BIT_7 | BIT_5; 4732 nv->add_firmware_options[0] = BIT_5; 4733 nv->add_firmware_options[1] = BIT_5 | BIT_4; 4734 nv->frame_payload_size = cpu_to_le16(2048); 4735 nv->special_options[1] = BIT_7; 4736 } else if (IS_QLA2200(ha)) { 4737 nv->firmware_options[0] = BIT_2 | BIT_1; 4738 nv->firmware_options[1] = BIT_7 | BIT_5; 4739 nv->add_firmware_options[0] = BIT_5; 4740 nv->add_firmware_options[1] = BIT_5 | BIT_4; 4741 nv->frame_payload_size = cpu_to_le16(1024); 4742 } else if (IS_QLA2100(ha)) { 4743 nv->firmware_options[0] = BIT_3 | BIT_1; 4744 nv->firmware_options[1] = BIT_5; 4745 nv->frame_payload_size = cpu_to_le16(1024); 4746 } 4747 4748 nv->max_iocb_allocation = cpu_to_le16(256); 4749 nv->execution_throttle = cpu_to_le16(16); 4750 nv->retry_count = 8; 4751 nv->retry_delay = 1; 4752 4753 nv->port_name[0] = 33; 4754 nv->port_name[3] = 224; 4755 nv->port_name[4] = 139; 4756 4757 qla2xxx_nvram_wwn_from_ofw(vha, nv); 4758 4759 nv->login_timeout = 4; 4760 4761 /* 4762 * Set default host adapter parameters 4763 */ 4764 nv->host_p[1] = BIT_2; 4765 nv->reset_delay = 5; 4766 nv->port_down_retry_count = 8; 4767 nv->max_luns_per_target = cpu_to_le16(8); 4768 nv->link_down_timeout = 60; 4769 4770 rval = 1; 4771 } 4772 4773 /* Reset Initialization control block */ 4774 memset(icb, 0, ha->init_cb_size); 4775 4776 /* 4777 * Setup driver NVRAM options. 4778 */ 4779 nv->firmware_options[0] |= (BIT_6 | BIT_1); 4780 nv->firmware_options[0] &= ~(BIT_5 | BIT_4); 4781 nv->firmware_options[1] |= (BIT_5 | BIT_0); 4782 nv->firmware_options[1] &= ~BIT_4; 4783 4784 if (IS_QLA23XX(ha)) { 4785 nv->firmware_options[0] |= BIT_2; 4786 nv->firmware_options[0] &= ~BIT_3; 4787 nv->special_options[0] &= ~BIT_6; 4788 nv->add_firmware_options[1] |= BIT_5 | BIT_4; 4789 4790 if (IS_QLA2300(ha)) { 4791 if (ha->fb_rev == FPM_2310) { 4792 strcpy(ha->model_number, "QLA2310"); 4793 } else { 4794 strcpy(ha->model_number, "QLA2300"); 4795 } 4796 } else { 4797 qla2x00_set_model_info(vha, nv->model_number, 4798 sizeof(nv->model_number), "QLA23xx"); 4799 } 4800 } else if (IS_QLA2200(ha)) { 4801 nv->firmware_options[0] |= BIT_2; 4802 /* 4803 * 'Point-to-point preferred, else loop' is not a safe 4804 * connection mode setting. 4805 */ 4806 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == 4807 (BIT_5 | BIT_4)) { 4808 /* Force 'loop preferred, else point-to-point'. */ 4809 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); 4810 nv->add_firmware_options[0] |= BIT_5; 4811 } 4812 strcpy(ha->model_number, "QLA22xx"); 4813 } else /*if (IS_QLA2100(ha))*/ { 4814 strcpy(ha->model_number, "QLA2100"); 4815 } 4816 4817 /* 4818 * Copy over NVRAM RISC parameter block to initialization control block. 4819 */ 4820 dptr1 = (uint8_t *)icb; 4821 dptr2 = (uint8_t *)&nv->parameter_block_version; 4822 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version; 4823 while (cnt--) 4824 *dptr1++ = *dptr2++; 4825 4826 /* Copy 2nd half. */ 4827 dptr1 = (uint8_t *)icb->add_firmware_options; 4828 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options; 4829 while (cnt--) 4830 *dptr1++ = *dptr2++; 4831 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 4832 /* Use alternate WWN? */ 4833 if (nv->host_p[1] & BIT_7) { 4834 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 4835 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 4836 } 4837 4838 /* Prepare nodename */ 4839 if ((icb->firmware_options[1] & BIT_6) == 0) { 4840 /* 4841 * Firmware will apply the following mask if the nodename was 4842 * not provided. 4843 */ 4844 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 4845 icb->node_name[0] &= 0xF0; 4846 } 4847 4848 /* 4849 * Set host adapter parameters. 4850 */ 4851 4852 /* 4853 * BIT_7 in the host-parameters section allows for modification to 4854 * internal driver logging. 4855 */ 4856 if (nv->host_p[0] & BIT_7) 4857 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 4858 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); 4859 /* Always load RISC code on non ISP2[12]00 chips. */ 4860 if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) 4861 ha->flags.disable_risc_code_load = 0; 4862 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0); 4863 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); 4864 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); 4865 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; 4866 ha->flags.disable_serdes = 0; 4867 4868 ha->operating_mode = 4869 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; 4870 4871 memcpy(ha->fw_seriallink_options, nv->seriallink_options, 4872 sizeof(ha->fw_seriallink_options)); 4873 4874 /* save HBA serial number */ 4875 ha->serial0 = icb->port_name[5]; 4876 ha->serial1 = icb->port_name[6]; 4877 ha->serial2 = icb->port_name[7]; 4878 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 4879 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 4880 4881 icb->execution_throttle = cpu_to_le16(0xFFFF); 4882 4883 ha->retry_count = nv->retry_count; 4884 4885 /* Set minimum login_timeout to 4 seconds. */ 4886 if (nv->login_timeout != ql2xlogintimeout) 4887 nv->login_timeout = ql2xlogintimeout; 4888 if (nv->login_timeout < 4) 4889 nv->login_timeout = 4; 4890 ha->login_timeout = nv->login_timeout; 4891 4892 /* Set minimum RATOV to 100 tenths of a second. */ 4893 ha->r_a_tov = 100; 4894 4895 ha->loop_reset_delay = nv->reset_delay; 4896 4897 /* Link Down Timeout = 0: 4898 * 4899 * When Port Down timer expires we will start returning 4900 * I/O's to OS with "DID_NO_CONNECT". 4901 * 4902 * Link Down Timeout != 0: 4903 * 4904 * The driver waits for the link to come up after link down 4905 * before returning I/Os to OS with "DID_NO_CONNECT". 4906 */ 4907 if (nv->link_down_timeout == 0) { 4908 ha->loop_down_abort_time = 4909 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 4910 } else { 4911 ha->link_down_timeout = nv->link_down_timeout; 4912 ha->loop_down_abort_time = 4913 (LOOP_DOWN_TIME - ha->link_down_timeout); 4914 } 4915 4916 /* 4917 * Need enough time to try and get the port back. 4918 */ 4919 ha->port_down_retry_count = nv->port_down_retry_count; 4920 if (qlport_down_retry) 4921 ha->port_down_retry_count = qlport_down_retry; 4922 /* Set login_retry_count */ 4923 ha->login_retry_count = nv->retry_count; 4924 if (ha->port_down_retry_count == nv->port_down_retry_count && 4925 ha->port_down_retry_count > 3) 4926 ha->login_retry_count = ha->port_down_retry_count; 4927 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 4928 ha->login_retry_count = ha->port_down_retry_count; 4929 if (ql2xloginretrycount) 4930 ha->login_retry_count = ql2xloginretrycount; 4931 4932 icb->lun_enables = cpu_to_le16(0); 4933 icb->command_resource_count = 0; 4934 icb->immediate_notify_resource_count = 0; 4935 icb->timeout = cpu_to_le16(0); 4936 4937 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4938 /* Enable RIO */ 4939 icb->firmware_options[0] &= ~BIT_3; 4940 icb->add_firmware_options[0] &= 4941 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 4942 icb->add_firmware_options[0] |= BIT_2; 4943 icb->response_accumulation_timer = 3; 4944 icb->interrupt_delay_timer = 5; 4945 4946 vha->flags.process_response_queue = 1; 4947 } else { 4948 /* Enable ZIO. */ 4949 if (!vha->flags.init_done) { 4950 ha->zio_mode = icb->add_firmware_options[0] & 4951 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 4952 ha->zio_timer = icb->interrupt_delay_timer ? 4953 icb->interrupt_delay_timer : 2; 4954 } 4955 icb->add_firmware_options[0] &= 4956 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 4957 vha->flags.process_response_queue = 0; 4958 if (ha->zio_mode != QLA_ZIO_DISABLED) { 4959 ha->zio_mode = QLA_ZIO_MODE_6; 4960 4961 ql_log(ql_log_info, vha, 0x0068, 4962 "ZIO mode %d enabled; timer delay (%d us).\n", 4963 ha->zio_mode, ha->zio_timer * 100); 4964 4965 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode; 4966 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer; 4967 vha->flags.process_response_queue = 1; 4968 } 4969 } 4970 4971 if (rval) { 4972 ql_log(ql_log_warn, vha, 0x0069, 4973 "NVRAM configuration failed.\n"); 4974 } 4975 return (rval); 4976 } 4977 4978 static void 4979 qla2x00_rport_del(void *data) 4980 { 4981 fc_port_t *fcport = data; 4982 struct fc_rport *rport; 4983 unsigned long flags; 4984 4985 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 4986 rport = fcport->drport ? fcport->drport : fcport->rport; 4987 fcport->drport = NULL; 4988 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 4989 if (rport) { 4990 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b, 4991 "%s %8phN. rport %p roles %x\n", 4992 __func__, fcport->port_name, rport, 4993 rport->roles); 4994 4995 fc_remote_port_delete(rport); 4996 } 4997 } 4998 4999 void qla2x00_set_fcport_state(fc_port_t *fcport, int state) 5000 { 5001 int old_state; 5002 5003 old_state = atomic_read(&fcport->state); 5004 atomic_set(&fcport->state, state); 5005 5006 /* Don't print state transitions during initial allocation of fcport */ 5007 if (old_state && old_state != state) { 5008 ql_dbg(ql_dbg_disc, fcport->vha, 0x207d, 5009 "FCPort %8phC state transitioned from %s to %s - portid=%02x%02x%02x.\n", 5010 fcport->port_name, port_state_str[old_state], 5011 port_state_str[state], fcport->d_id.b.domain, 5012 fcport->d_id.b.area, fcport->d_id.b.al_pa); 5013 } 5014 } 5015 5016 /** 5017 * qla2x00_alloc_fcport() - Allocate a generic fcport. 5018 * @vha: HA context 5019 * @flags: allocation flags 5020 * 5021 * Returns a pointer to the allocated fcport, or NULL, if none available. 5022 */ 5023 fc_port_t * 5024 qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags) 5025 { 5026 fc_port_t *fcport; 5027 5028 fcport = kzalloc(sizeof(fc_port_t), flags); 5029 if (!fcport) 5030 return NULL; 5031 5032 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev, 5033 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma, 5034 flags); 5035 if (!fcport->ct_desc.ct_sns) { 5036 ql_log(ql_log_warn, vha, 0xd049, 5037 "Failed to allocate ct_sns request.\n"); 5038 kfree(fcport); 5039 return NULL; 5040 } 5041 5042 /* Setup fcport template structure. */ 5043 fcport->vha = vha; 5044 fcport->port_type = FCT_UNKNOWN; 5045 fcport->loop_id = FC_NO_LOOP_ID; 5046 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED); 5047 fcport->supported_classes = FC_COS_UNSPECIFIED; 5048 fcport->fp_speed = PORT_SPEED_UNKNOWN; 5049 5050 fcport->disc_state = DSC_DELETED; 5051 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 5052 fcport->deleted = QLA_SESS_DELETED; 5053 fcport->login_retry = vha->hw->login_retry_count; 5054 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5055 fcport->logout_on_delete = 1; 5056 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 5057 fcport->tgt_short_link_down_cnt = 0; 5058 fcport->dev_loss_tmo = 0; 5059 5060 if (!fcport->ct_desc.ct_sns) { 5061 ql_log(ql_log_warn, vha, 0xd049, 5062 "Failed to allocate ct_sns request.\n"); 5063 kfree(fcport); 5064 return NULL; 5065 } 5066 5067 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn); 5068 INIT_WORK(&fcport->free_work, qlt_free_session_done); 5069 INIT_WORK(&fcport->reg_work, qla_register_fcport_fn); 5070 INIT_LIST_HEAD(&fcport->gnl_entry); 5071 INIT_LIST_HEAD(&fcport->list); 5072 5073 INIT_LIST_HEAD(&fcport->sess_cmd_list); 5074 spin_lock_init(&fcport->sess_cmd_lock); 5075 5076 return fcport; 5077 } 5078 5079 void 5080 qla2x00_free_fcport(fc_port_t *fcport) 5081 { 5082 if (fcport->ct_desc.ct_sns) { 5083 dma_free_coherent(&fcport->vha->hw->pdev->dev, 5084 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns, 5085 fcport->ct_desc.ct_sns_dma); 5086 5087 fcport->ct_desc.ct_sns = NULL; 5088 } 5089 list_del(&fcport->list); 5090 qla2x00_clear_loop_id(fcport); 5091 kfree(fcport); 5092 } 5093 5094 static void qla_get_login_template(scsi_qla_host_t *vha) 5095 { 5096 struct qla_hw_data *ha = vha->hw; 5097 int rval; 5098 u32 *bp, sz; 5099 __be32 *q; 5100 5101 memset(ha->init_cb, 0, ha->init_cb_size); 5102 sz = min_t(int, sizeof(struct fc_els_flogi), ha->init_cb_size); 5103 rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma, 5104 ha->init_cb, sz); 5105 if (rval != QLA_SUCCESS) { 5106 ql_dbg(ql_dbg_init, vha, 0x00d1, 5107 "PLOGI ELS param read fail.\n"); 5108 return; 5109 } 5110 q = (__be32 *)&ha->plogi_els_payld.fl_csp; 5111 5112 bp = (uint32_t *)ha->init_cb; 5113 cpu_to_be32_array(q, bp, sz / 4); 5114 ha->flags.plogi_template_valid = 1; 5115 } 5116 5117 /* 5118 * qla2x00_configure_loop 5119 * Updates Fibre Channel Device Database with what is actually on loop. 5120 * 5121 * Input: 5122 * ha = adapter block pointer. 5123 * 5124 * Returns: 5125 * 0 = success. 5126 * 1 = error. 5127 * 2 = database was full and device was not configured. 5128 */ 5129 static int 5130 qla2x00_configure_loop(scsi_qla_host_t *vha) 5131 { 5132 int rval; 5133 unsigned long flags, save_flags; 5134 struct qla_hw_data *ha = vha->hw; 5135 5136 rval = QLA_SUCCESS; 5137 5138 /* Get Initiator ID */ 5139 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) { 5140 rval = qla2x00_configure_hba(vha); 5141 if (rval != QLA_SUCCESS) { 5142 ql_dbg(ql_dbg_disc, vha, 0x2013, 5143 "Unable to configure HBA.\n"); 5144 return (rval); 5145 } 5146 } 5147 5148 save_flags = flags = vha->dpc_flags; 5149 ql_dbg(ql_dbg_disc, vha, 0x2014, 5150 "Configure loop -- dpc flags = 0x%lx.\n", flags); 5151 5152 /* 5153 * If we have both an RSCN and PORT UPDATE pending then handle them 5154 * both at the same time. 5155 */ 5156 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5157 clear_bit(RSCN_UPDATE, &vha->dpc_flags); 5158 5159 qla2x00_get_data_rate(vha); 5160 qla_get_login_template(vha); 5161 5162 /* Determine what we need to do */ 5163 if ((ha->current_topology == ISP_CFG_FL || 5164 ha->current_topology == ISP_CFG_F) && 5165 (test_bit(LOCAL_LOOP_UPDATE, &flags))) { 5166 5167 set_bit(RSCN_UPDATE, &flags); 5168 clear_bit(LOCAL_LOOP_UPDATE, &flags); 5169 5170 } else if (ha->current_topology == ISP_CFG_NL || 5171 ha->current_topology == ISP_CFG_N) { 5172 clear_bit(RSCN_UPDATE, &flags); 5173 set_bit(LOCAL_LOOP_UPDATE, &flags); 5174 } else if (!vha->flags.online || 5175 (test_bit(ABORT_ISP_ACTIVE, &flags))) { 5176 set_bit(RSCN_UPDATE, &flags); 5177 set_bit(LOCAL_LOOP_UPDATE, &flags); 5178 } 5179 5180 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) { 5181 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5182 ql_dbg(ql_dbg_disc, vha, 0x2015, 5183 "Loop resync needed, failing.\n"); 5184 rval = QLA_FUNCTION_FAILED; 5185 } else 5186 rval = qla2x00_configure_local_loop(vha); 5187 } 5188 5189 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) { 5190 if (LOOP_TRANSITION(vha)) { 5191 ql_dbg(ql_dbg_disc, vha, 0x2099, 5192 "Needs RSCN update and loop transition.\n"); 5193 rval = QLA_FUNCTION_FAILED; 5194 } 5195 else 5196 rval = qla2x00_configure_fabric(vha); 5197 } 5198 5199 if (rval == QLA_SUCCESS) { 5200 if (atomic_read(&vha->loop_down_timer) || 5201 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5202 rval = QLA_FUNCTION_FAILED; 5203 } else { 5204 atomic_set(&vha->loop_state, LOOP_READY); 5205 ql_dbg(ql_dbg_disc, vha, 0x2069, 5206 "LOOP READY.\n"); 5207 ha->flags.fw_init_done = 1; 5208 5209 /* 5210 * Process any ATIO queue entries that came in 5211 * while we weren't online. 5212 */ 5213 if (qla_tgt_mode_enabled(vha) || 5214 qla_dual_mode_enabled(vha)) { 5215 spin_lock_irqsave(&ha->tgt.atio_lock, flags); 5216 qlt_24xx_process_atio_queue(vha, 0); 5217 spin_unlock_irqrestore(&ha->tgt.atio_lock, 5218 flags); 5219 } 5220 } 5221 } 5222 5223 if (rval) { 5224 ql_dbg(ql_dbg_disc, vha, 0x206a, 5225 "%s *** FAILED ***.\n", __func__); 5226 } else { 5227 ql_dbg(ql_dbg_disc, vha, 0x206b, 5228 "%s: exiting normally.\n", __func__); 5229 } 5230 5231 /* Restore state if a resync event occurred during processing */ 5232 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5233 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags)) 5234 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5235 if (test_bit(RSCN_UPDATE, &save_flags)) { 5236 set_bit(RSCN_UPDATE, &vha->dpc_flags); 5237 } 5238 } 5239 5240 return (rval); 5241 } 5242 5243 static int qla2x00_configure_n2n_loop(scsi_qla_host_t *vha) 5244 { 5245 unsigned long flags; 5246 fc_port_t *fcport; 5247 5248 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) 5249 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5250 5251 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5252 if (fcport->n2n_flag) { 5253 qla24xx_fcport_handle_login(vha, fcport); 5254 return QLA_SUCCESS; 5255 } 5256 } 5257 5258 spin_lock_irqsave(&vha->work_lock, flags); 5259 vha->scan.scan_retry++; 5260 spin_unlock_irqrestore(&vha->work_lock, flags); 5261 5262 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) { 5263 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5264 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5265 } 5266 return QLA_FUNCTION_FAILED; 5267 } 5268 5269 /* 5270 * qla2x00_configure_local_loop 5271 * Updates Fibre Channel Device Database with local loop devices. 5272 * 5273 * Input: 5274 * ha = adapter block pointer. 5275 * 5276 * Returns: 5277 * 0 = success. 5278 */ 5279 static int 5280 qla2x00_configure_local_loop(scsi_qla_host_t *vha) 5281 { 5282 int rval, rval2; 5283 int found_devs; 5284 int found; 5285 fc_port_t *fcport, *new_fcport; 5286 uint16_t index; 5287 uint16_t entries; 5288 struct gid_list_info *gid; 5289 uint16_t loop_id; 5290 uint8_t domain, area, al_pa; 5291 struct qla_hw_data *ha = vha->hw; 5292 unsigned long flags; 5293 5294 /* Inititae N2N login. */ 5295 if (N2N_TOPO(ha)) 5296 return qla2x00_configure_n2n_loop(vha); 5297 5298 found_devs = 0; 5299 new_fcport = NULL; 5300 entries = MAX_FIBRE_DEVICES_LOOP; 5301 5302 /* Get list of logged in devices. */ 5303 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha)); 5304 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma, 5305 &entries); 5306 if (rval != QLA_SUCCESS) 5307 goto err; 5308 5309 ql_dbg(ql_dbg_disc, vha, 0x2011, 5310 "Entries in ID list (%d).\n", entries); 5311 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075, 5312 ha->gid_list, entries * sizeof(*ha->gid_list)); 5313 5314 if (entries == 0) { 5315 spin_lock_irqsave(&vha->work_lock, flags); 5316 vha->scan.scan_retry++; 5317 spin_unlock_irqrestore(&vha->work_lock, flags); 5318 5319 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) { 5320 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5321 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5322 } 5323 } else { 5324 vha->scan.scan_retry = 0; 5325 } 5326 5327 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5328 fcport->scan_state = QLA_FCPORT_SCAN; 5329 } 5330 5331 /* Allocate temporary fcport for any new fcports discovered. */ 5332 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5333 if (new_fcport == NULL) { 5334 ql_log(ql_log_warn, vha, 0x2012, 5335 "Memory allocation failed for fcport.\n"); 5336 rval = QLA_MEMORY_ALLOC_FAILED; 5337 goto err; 5338 } 5339 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 5340 5341 /* Add devices to port list. */ 5342 gid = ha->gid_list; 5343 for (index = 0; index < entries; index++) { 5344 domain = gid->domain; 5345 area = gid->area; 5346 al_pa = gid->al_pa; 5347 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 5348 loop_id = gid->loop_id_2100; 5349 else 5350 loop_id = le16_to_cpu(gid->loop_id); 5351 gid = (void *)gid + ha->gid_list_info_size; 5352 5353 /* Bypass reserved domain fields. */ 5354 if ((domain & 0xf0) == 0xf0) 5355 continue; 5356 5357 /* Bypass if not same domain and area of adapter. */ 5358 if (area && domain && ((area != vha->d_id.b.area) || 5359 (domain != vha->d_id.b.domain)) && 5360 (ha->current_topology == ISP_CFG_NL)) 5361 continue; 5362 5363 5364 /* Bypass invalid local loop ID. */ 5365 if (loop_id > LAST_LOCAL_LOOP_ID) 5366 continue; 5367 5368 memset(new_fcport->port_name, 0, WWN_SIZE); 5369 5370 /* Fill in member data. */ 5371 new_fcport->d_id.b.domain = domain; 5372 new_fcport->d_id.b.area = area; 5373 new_fcport->d_id.b.al_pa = al_pa; 5374 new_fcport->loop_id = loop_id; 5375 new_fcport->scan_state = QLA_FCPORT_FOUND; 5376 5377 rval2 = qla2x00_get_port_database(vha, new_fcport, 0); 5378 if (rval2 != QLA_SUCCESS) { 5379 ql_dbg(ql_dbg_disc, vha, 0x2097, 5380 "Failed to retrieve fcport information " 5381 "-- get_port_database=%x, loop_id=0x%04x.\n", 5382 rval2, new_fcport->loop_id); 5383 /* Skip retry if N2N */ 5384 if (ha->current_topology != ISP_CFG_N) { 5385 ql_dbg(ql_dbg_disc, vha, 0x2105, 5386 "Scheduling resync.\n"); 5387 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5388 continue; 5389 } 5390 } 5391 5392 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5393 /* Check for matching device in port list. */ 5394 found = 0; 5395 fcport = NULL; 5396 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5397 if (memcmp(new_fcport->port_name, fcport->port_name, 5398 WWN_SIZE)) 5399 continue; 5400 5401 fcport->flags &= ~FCF_FABRIC_DEVICE; 5402 fcport->loop_id = new_fcport->loop_id; 5403 fcport->port_type = new_fcport->port_type; 5404 fcport->d_id.b24 = new_fcport->d_id.b24; 5405 memcpy(fcport->node_name, new_fcport->node_name, 5406 WWN_SIZE); 5407 fcport->scan_state = QLA_FCPORT_FOUND; 5408 found++; 5409 break; 5410 } 5411 5412 if (!found) { 5413 /* New device, add to fcports list. */ 5414 list_add_tail(&new_fcport->list, &vha->vp_fcports); 5415 5416 /* Allocate a new replacement fcport. */ 5417 fcport = new_fcport; 5418 5419 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5420 5421 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5422 5423 if (new_fcport == NULL) { 5424 ql_log(ql_log_warn, vha, 0xd031, 5425 "Failed to allocate memory for fcport.\n"); 5426 rval = QLA_MEMORY_ALLOC_FAILED; 5427 goto err; 5428 } 5429 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5430 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 5431 } 5432 5433 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5434 5435 /* Base iIDMA settings on HBA port speed. */ 5436 fcport->fp_speed = ha->link_data_rate; 5437 5438 found_devs++; 5439 } 5440 5441 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5442 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5443 break; 5444 5445 if (fcport->scan_state == QLA_FCPORT_SCAN) { 5446 if ((qla_dual_mode_enabled(vha) || 5447 qla_ini_mode_enabled(vha)) && 5448 atomic_read(&fcport->state) == FCS_ONLINE) { 5449 qla2x00_mark_device_lost(vha, fcport, 5450 ql2xplogiabsentdevice); 5451 if (fcport->loop_id != FC_NO_LOOP_ID && 5452 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 5453 fcport->port_type != FCT_INITIATOR && 5454 fcport->port_type != FCT_BROADCAST) { 5455 ql_dbg(ql_dbg_disc, vha, 0x20f0, 5456 "%s %d %8phC post del sess\n", 5457 __func__, __LINE__, 5458 fcport->port_name); 5459 5460 qlt_schedule_sess_for_deletion(fcport); 5461 continue; 5462 } 5463 } 5464 } 5465 5466 if (fcport->scan_state == QLA_FCPORT_FOUND) 5467 qla24xx_fcport_handle_login(vha, fcport); 5468 } 5469 5470 qla2x00_free_fcport(new_fcport); 5471 5472 return rval; 5473 5474 err: 5475 ql_dbg(ql_dbg_disc, vha, 0x2098, 5476 "Configure local loop error exit: rval=%x.\n", rval); 5477 return rval; 5478 } 5479 5480 static void 5481 qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 5482 { 5483 int rval; 5484 uint16_t mb[MAILBOX_REGISTER_COUNT]; 5485 struct qla_hw_data *ha = vha->hw; 5486 5487 if (!IS_IIDMA_CAPABLE(ha)) 5488 return; 5489 5490 if (atomic_read(&fcport->state) != FCS_ONLINE) 5491 return; 5492 5493 if (fcport->fp_speed == PORT_SPEED_UNKNOWN || 5494 fcport->fp_speed > ha->link_data_rate || 5495 !ha->flags.gpsc_supported) 5496 return; 5497 5498 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed, 5499 mb); 5500 if (rval != QLA_SUCCESS) { 5501 ql_dbg(ql_dbg_disc, vha, 0x2004, 5502 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n", 5503 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]); 5504 } else { 5505 ql_dbg(ql_dbg_disc, vha, 0x2005, 5506 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n", 5507 qla2x00_get_link_speed_str(ha, fcport->fp_speed), 5508 fcport->fp_speed, fcport->port_name); 5509 } 5510 } 5511 5512 void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport) 5513 { 5514 qla2x00_iidma_fcport(vha, fcport); 5515 qla24xx_update_fcport_fcp_prio(vha, fcport); 5516 } 5517 5518 int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport) 5519 { 5520 struct qla_work_evt *e; 5521 5522 e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA); 5523 if (!e) 5524 return QLA_FUNCTION_FAILED; 5525 5526 e->u.fcport.fcport = fcport; 5527 return qla2x00_post_work(vha, e); 5528 } 5529 5530 /* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/ 5531 static void 5532 qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport) 5533 { 5534 struct fc_rport_identifiers rport_ids; 5535 struct fc_rport *rport; 5536 unsigned long flags; 5537 5538 if (atomic_read(&fcport->state) == FCS_ONLINE) 5539 return; 5540 5541 rport_ids.node_name = wwn_to_u64(fcport->node_name); 5542 rport_ids.port_name = wwn_to_u64(fcport->port_name); 5543 rport_ids.port_id = fcport->d_id.b.domain << 16 | 5544 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa; 5545 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; 5546 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids); 5547 if (!rport) { 5548 ql_log(ql_log_warn, vha, 0x2006, 5549 "Unable to allocate fc remote port.\n"); 5550 return; 5551 } 5552 5553 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 5554 *((fc_port_t **)rport->dd_data) = fcport; 5555 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 5556 fcport->dev_loss_tmo = rport->dev_loss_tmo; 5557 5558 rport->supported_classes = fcport->supported_classes; 5559 5560 rport_ids.roles = FC_PORT_ROLE_UNKNOWN; 5561 if (fcport->port_type == FCT_INITIATOR) 5562 rport_ids.roles |= FC_PORT_ROLE_FCP_INITIATOR; 5563 if (fcport->port_type == FCT_TARGET) 5564 rport_ids.roles |= FC_PORT_ROLE_FCP_TARGET; 5565 if (fcport->port_type & FCT_NVME_INITIATOR) 5566 rport_ids.roles |= FC_PORT_ROLE_NVME_INITIATOR; 5567 if (fcport->port_type & FCT_NVME_TARGET) 5568 rport_ids.roles |= FC_PORT_ROLE_NVME_TARGET; 5569 if (fcport->port_type & FCT_NVME_DISCOVERY) 5570 rport_ids.roles |= FC_PORT_ROLE_NVME_DISCOVERY; 5571 5572 fc_remote_port_rolechg(rport, rport_ids.roles); 5573 5574 ql_dbg(ql_dbg_disc, vha, 0x20ee, 5575 "%s: %8phN. rport %ld:0:%d (%p) is %s mode\n", 5576 __func__, fcport->port_name, vha->host_no, 5577 rport->scsi_target_id, rport, 5578 (fcport->port_type == FCT_TARGET) ? "tgt" : 5579 ((fcport->port_type & FCT_NVME) ? "nvme" : "ini")); 5580 } 5581 5582 /* 5583 * qla2x00_update_fcport 5584 * Updates device on list. 5585 * 5586 * Input: 5587 * ha = adapter block pointer. 5588 * fcport = port structure pointer. 5589 * 5590 * Return: 5591 * 0 - Success 5592 * BIT_0 - error 5593 * 5594 * Context: 5595 * Kernel context. 5596 */ 5597 void 5598 qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 5599 { 5600 if (IS_SW_RESV_ADDR(fcport->d_id)) 5601 return; 5602 5603 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n", 5604 __func__, fcport->port_name); 5605 5606 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5607 fcport->login_retry = vha->hw->login_retry_count; 5608 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 5609 fcport->deleted = 0; 5610 if (vha->hw->current_topology == ISP_CFG_NL) 5611 fcport->logout_on_delete = 0; 5612 else 5613 fcport->logout_on_delete = 1; 5614 fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0; 5615 5616 if (fcport->tgt_link_down_time < fcport->dev_loss_tmo) { 5617 fcport->tgt_short_link_down_cnt++; 5618 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 5619 } 5620 5621 switch (vha->hw->current_topology) { 5622 case ISP_CFG_N: 5623 case ISP_CFG_NL: 5624 fcport->keep_nport_handle = 1; 5625 break; 5626 default: 5627 break; 5628 } 5629 5630 qla2x00_iidma_fcport(vha, fcport); 5631 5632 qla2x00_dfs_create_rport(vha, fcport); 5633 5634 if (NVME_TARGET(vha->hw, fcport)) { 5635 qla_nvme_register_remote(vha, fcport); 5636 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE); 5637 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 5638 return; 5639 } 5640 5641 qla24xx_update_fcport_fcp_prio(vha, fcport); 5642 5643 switch (vha->host->active_mode) { 5644 case MODE_INITIATOR: 5645 qla2x00_reg_remote_port(vha, fcport); 5646 break; 5647 case MODE_TARGET: 5648 if (!vha->vha_tgt.qla_tgt->tgt_stop && 5649 !vha->vha_tgt.qla_tgt->tgt_stopped) 5650 qlt_fc_port_added(vha, fcport); 5651 break; 5652 case MODE_DUAL: 5653 qla2x00_reg_remote_port(vha, fcport); 5654 if (!vha->vha_tgt.qla_tgt->tgt_stop && 5655 !vha->vha_tgt.qla_tgt->tgt_stopped) 5656 qlt_fc_port_added(vha, fcport); 5657 break; 5658 default: 5659 break; 5660 } 5661 5662 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 5663 5664 if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) { 5665 if (fcport->id_changed) { 5666 fcport->id_changed = 0; 5667 ql_dbg(ql_dbg_disc, vha, 0x20d7, 5668 "%s %d %8phC post gfpnid fcp_cnt %d\n", 5669 __func__, __LINE__, fcport->port_name, 5670 vha->fcport_count); 5671 qla24xx_post_gfpnid_work(vha, fcport); 5672 } else { 5673 ql_dbg(ql_dbg_disc, vha, 0x20d7, 5674 "%s %d %8phC post gpsc fcp_cnt %d\n", 5675 __func__, __LINE__, fcport->port_name, 5676 vha->fcport_count); 5677 qla24xx_post_gpsc_work(vha, fcport); 5678 } 5679 } 5680 5681 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE); 5682 } 5683 5684 void qla_register_fcport_fn(struct work_struct *work) 5685 { 5686 fc_port_t *fcport = container_of(work, struct fc_port, reg_work); 5687 u32 rscn_gen = fcport->rscn_gen; 5688 u16 data[2]; 5689 5690 if (IS_SW_RESV_ADDR(fcport->d_id)) 5691 return; 5692 5693 qla2x00_update_fcport(fcport->vha, fcport); 5694 5695 if (rscn_gen != fcport->rscn_gen) { 5696 /* RSCN(s) came in while registration */ 5697 switch (fcport->next_disc_state) { 5698 case DSC_DELETE_PEND: 5699 qlt_schedule_sess_for_deletion(fcport); 5700 break; 5701 case DSC_ADISC: 5702 data[0] = data[1] = 0; 5703 qla2x00_post_async_adisc_work(fcport->vha, fcport, 5704 data); 5705 break; 5706 default: 5707 break; 5708 } 5709 } 5710 } 5711 5712 /* 5713 * qla2x00_configure_fabric 5714 * Setup SNS devices with loop ID's. 5715 * 5716 * Input: 5717 * ha = adapter block pointer. 5718 * 5719 * Returns: 5720 * 0 = success. 5721 * BIT_0 = error 5722 */ 5723 static int 5724 qla2x00_configure_fabric(scsi_qla_host_t *vha) 5725 { 5726 int rval; 5727 fc_port_t *fcport; 5728 uint16_t mb[MAILBOX_REGISTER_COUNT]; 5729 uint16_t loop_id; 5730 LIST_HEAD(new_fcports); 5731 struct qla_hw_data *ha = vha->hw; 5732 int discovery_gen; 5733 5734 /* If FL port exists, then SNS is present */ 5735 if (IS_FWI2_CAPABLE(ha)) 5736 loop_id = NPH_F_PORT; 5737 else 5738 loop_id = SNS_FL_PORT; 5739 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1); 5740 if (rval != QLA_SUCCESS) { 5741 ql_dbg(ql_dbg_disc, vha, 0x20a0, 5742 "MBX_GET_PORT_NAME failed, No FL Port.\n"); 5743 5744 vha->device_flags &= ~SWITCH_FOUND; 5745 return (QLA_SUCCESS); 5746 } 5747 vha->device_flags |= SWITCH_FOUND; 5748 5749 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_port_name, 0); 5750 if (rval != QLA_SUCCESS) 5751 ql_dbg(ql_dbg_disc, vha, 0x20ff, 5752 "Failed to get Fabric Port Name\n"); 5753 5754 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) { 5755 rval = qla2x00_send_change_request(vha, 0x3, 0); 5756 if (rval != QLA_SUCCESS) 5757 ql_log(ql_log_warn, vha, 0x121, 5758 "Failed to enable receiving of RSCN requests: 0x%x.\n", 5759 rval); 5760 } 5761 5762 do { 5763 qla2x00_mgmt_svr_login(vha); 5764 5765 /* Ensure we are logged into the SNS. */ 5766 loop_id = NPH_SNS_LID(ha); 5767 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff, 5768 0xfc, mb, BIT_1|BIT_0); 5769 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 5770 ql_dbg(ql_dbg_disc, vha, 0x20a1, 5771 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n", 5772 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval); 5773 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5774 return rval; 5775 } 5776 5777 /* FDMI support. */ 5778 if (ql2xfdmienable && 5779 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags)) 5780 qla2x00_fdmi_register(vha); 5781 5782 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) { 5783 if (qla2x00_rft_id(vha)) { 5784 /* EMPTY */ 5785 ql_dbg(ql_dbg_disc, vha, 0x20a2, 5786 "Register FC-4 TYPE failed.\n"); 5787 if (test_bit(LOOP_RESYNC_NEEDED, 5788 &vha->dpc_flags)) 5789 break; 5790 } 5791 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) { 5792 /* EMPTY */ 5793 ql_dbg(ql_dbg_disc, vha, 0x209a, 5794 "Register FC-4 Features failed.\n"); 5795 if (test_bit(LOOP_RESYNC_NEEDED, 5796 &vha->dpc_flags)) 5797 break; 5798 } 5799 if (vha->flags.nvme_enabled) { 5800 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) { 5801 ql_dbg(ql_dbg_disc, vha, 0x2049, 5802 "Register NVME FC Type Features failed.\n"); 5803 } 5804 } 5805 if (qla2x00_rnn_id(vha)) { 5806 /* EMPTY */ 5807 ql_dbg(ql_dbg_disc, vha, 0x2104, 5808 "Register Node Name failed.\n"); 5809 if (test_bit(LOOP_RESYNC_NEEDED, 5810 &vha->dpc_flags)) 5811 break; 5812 } else if (qla2x00_rsnn_nn(vha)) { 5813 /* EMPTY */ 5814 ql_dbg(ql_dbg_disc, vha, 0x209b, 5815 "Register Symbolic Node Name failed.\n"); 5816 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5817 break; 5818 } 5819 } 5820 5821 5822 /* Mark the time right before querying FW for connected ports. 5823 * This process is long, asynchronous and by the time it's done, 5824 * collected information might not be accurate anymore. E.g. 5825 * disconnected port might have re-connected and a brand new 5826 * session has been created. In this case session's generation 5827 * will be newer than discovery_gen. */ 5828 qlt_do_generation_tick(vha, &discovery_gen); 5829 5830 if (USE_ASYNC_SCAN(ha)) { 5831 rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI, 5832 NULL); 5833 if (rval) 5834 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5835 } else { 5836 list_for_each_entry(fcport, &vha->vp_fcports, list) 5837 fcport->scan_state = QLA_FCPORT_SCAN; 5838 5839 rval = qla2x00_find_all_fabric_devs(vha); 5840 } 5841 if (rval != QLA_SUCCESS) 5842 break; 5843 } while (0); 5844 5845 if (!vha->nvme_local_port && vha->flags.nvme_enabled) 5846 qla_nvme_register_hba(vha); 5847 5848 if (rval) 5849 ql_dbg(ql_dbg_disc, vha, 0x2068, 5850 "Configure fabric error exit rval=%d.\n", rval); 5851 5852 return (rval); 5853 } 5854 5855 /* 5856 * qla2x00_find_all_fabric_devs 5857 * 5858 * Input: 5859 * ha = adapter block pointer. 5860 * dev = database device entry pointer. 5861 * 5862 * Returns: 5863 * 0 = success. 5864 * 5865 * Context: 5866 * Kernel context. 5867 */ 5868 static int 5869 qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha) 5870 { 5871 int rval; 5872 uint16_t loop_id; 5873 fc_port_t *fcport, *new_fcport; 5874 int found; 5875 5876 sw_info_t *swl; 5877 int swl_idx; 5878 int first_dev, last_dev; 5879 port_id_t wrap = {}, nxt_d_id; 5880 struct qla_hw_data *ha = vha->hw; 5881 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 5882 unsigned long flags; 5883 5884 rval = QLA_SUCCESS; 5885 5886 /* Try GID_PT to get device list, else GAN. */ 5887 if (!ha->swl) 5888 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t), 5889 GFP_KERNEL); 5890 swl = ha->swl; 5891 if (!swl) { 5892 /*EMPTY*/ 5893 ql_dbg(ql_dbg_disc, vha, 0x209c, 5894 "GID_PT allocations failed, fallback on GA_NXT.\n"); 5895 } else { 5896 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t)); 5897 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) { 5898 swl = NULL; 5899 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5900 return rval; 5901 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) { 5902 swl = NULL; 5903 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5904 return rval; 5905 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) { 5906 swl = NULL; 5907 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5908 return rval; 5909 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) { 5910 swl = NULL; 5911 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5912 return rval; 5913 } 5914 5915 /* If other queries succeeded probe for FC-4 type */ 5916 if (swl) { 5917 qla2x00_gff_id(vha, swl); 5918 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5919 return rval; 5920 } 5921 } 5922 swl_idx = 0; 5923 5924 /* Allocate temporary fcport for any new fcports discovered. */ 5925 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5926 if (new_fcport == NULL) { 5927 ql_log(ql_log_warn, vha, 0x209d, 5928 "Failed to allocate memory for fcport.\n"); 5929 return (QLA_MEMORY_ALLOC_FAILED); 5930 } 5931 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 5932 /* Set start port ID scan at adapter ID. */ 5933 first_dev = 1; 5934 last_dev = 0; 5935 5936 /* Starting free loop ID. */ 5937 loop_id = ha->min_external_loopid; 5938 for (; loop_id <= ha->max_loop_id; loop_id++) { 5939 if (qla2x00_is_reserved_id(vha, loop_id)) 5940 continue; 5941 5942 if (ha->current_topology == ISP_CFG_FL && 5943 (atomic_read(&vha->loop_down_timer) || 5944 LOOP_TRANSITION(vha))) { 5945 atomic_set(&vha->loop_down_timer, 0); 5946 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5947 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5948 break; 5949 } 5950 5951 if (swl != NULL) { 5952 if (last_dev) { 5953 wrap.b24 = new_fcport->d_id.b24; 5954 } else { 5955 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24; 5956 memcpy(new_fcport->node_name, 5957 swl[swl_idx].node_name, WWN_SIZE); 5958 memcpy(new_fcport->port_name, 5959 swl[swl_idx].port_name, WWN_SIZE); 5960 memcpy(new_fcport->fabric_port_name, 5961 swl[swl_idx].fabric_port_name, WWN_SIZE); 5962 new_fcport->fp_speed = swl[swl_idx].fp_speed; 5963 new_fcport->fc4_type = swl[swl_idx].fc4_type; 5964 5965 new_fcport->nvme_flag = 0; 5966 if (vha->flags.nvme_enabled && 5967 swl[swl_idx].fc4_type & FS_FC4TYPE_NVME) { 5968 ql_log(ql_log_info, vha, 0x2131, 5969 "FOUND: NVME port %8phC as FC Type 28h\n", 5970 new_fcport->port_name); 5971 } 5972 5973 if (swl[swl_idx].d_id.b.rsvd_1 != 0) { 5974 last_dev = 1; 5975 } 5976 swl_idx++; 5977 } 5978 } else { 5979 /* Send GA_NXT to the switch */ 5980 rval = qla2x00_ga_nxt(vha, new_fcport); 5981 if (rval != QLA_SUCCESS) { 5982 ql_log(ql_log_warn, vha, 0x209e, 5983 "SNS scan failed -- assuming " 5984 "zero-entry result.\n"); 5985 rval = QLA_SUCCESS; 5986 break; 5987 } 5988 } 5989 5990 /* If wrap on switch device list, exit. */ 5991 if (first_dev) { 5992 wrap.b24 = new_fcport->d_id.b24; 5993 first_dev = 0; 5994 } else if (new_fcport->d_id.b24 == wrap.b24) { 5995 ql_dbg(ql_dbg_disc, vha, 0x209f, 5996 "Device wrap (%02x%02x%02x).\n", 5997 new_fcport->d_id.b.domain, 5998 new_fcport->d_id.b.area, 5999 new_fcport->d_id.b.al_pa); 6000 break; 6001 } 6002 6003 /* Bypass if same physical adapter. */ 6004 if (new_fcport->d_id.b24 == base_vha->d_id.b24) 6005 continue; 6006 6007 /* Bypass virtual ports of the same host. */ 6008 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24)) 6009 continue; 6010 6011 /* Bypass if same domain and area of adapter. */ 6012 if (((new_fcport->d_id.b24 & 0xffff00) == 6013 (vha->d_id.b24 & 0xffff00)) && ha->current_topology == 6014 ISP_CFG_FL) 6015 continue; 6016 6017 /* Bypass reserved domain fields. */ 6018 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0) 6019 continue; 6020 6021 /* Bypass ports whose FCP-4 type is not FCP_SCSI */ 6022 if (ql2xgffidenable && 6023 (!(new_fcport->fc4_type & FS_FC4TYPE_FCP) && 6024 new_fcport->fc4_type != 0)) 6025 continue; 6026 6027 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 6028 6029 /* Locate matching device in database. */ 6030 found = 0; 6031 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6032 if (memcmp(new_fcport->port_name, fcport->port_name, 6033 WWN_SIZE)) 6034 continue; 6035 6036 fcport->scan_state = QLA_FCPORT_FOUND; 6037 6038 found++; 6039 6040 /* Update port state. */ 6041 memcpy(fcport->fabric_port_name, 6042 new_fcport->fabric_port_name, WWN_SIZE); 6043 fcport->fp_speed = new_fcport->fp_speed; 6044 6045 /* 6046 * If address the same and state FCS_ONLINE 6047 * (or in target mode), nothing changed. 6048 */ 6049 if (fcport->d_id.b24 == new_fcport->d_id.b24 && 6050 (atomic_read(&fcport->state) == FCS_ONLINE || 6051 (vha->host->active_mode == MODE_TARGET))) { 6052 break; 6053 } 6054 6055 if (fcport->login_retry == 0) 6056 fcport->login_retry = 6057 vha->hw->login_retry_count; 6058 /* 6059 * If device was not a fabric device before. 6060 */ 6061 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) { 6062 fcport->d_id.b24 = new_fcport->d_id.b24; 6063 qla2x00_clear_loop_id(fcport); 6064 fcport->flags |= (FCF_FABRIC_DEVICE | 6065 FCF_LOGIN_NEEDED); 6066 break; 6067 } 6068 6069 /* 6070 * Port ID changed or device was marked to be updated; 6071 * Log it out if still logged in and mark it for 6072 * relogin later. 6073 */ 6074 if (qla_tgt_mode_enabled(base_vha)) { 6075 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080, 6076 "port changed FC ID, %8phC" 6077 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n", 6078 fcport->port_name, 6079 fcport->d_id.b.domain, 6080 fcport->d_id.b.area, 6081 fcport->d_id.b.al_pa, 6082 fcport->loop_id, 6083 new_fcport->d_id.b.domain, 6084 new_fcport->d_id.b.area, 6085 new_fcport->d_id.b.al_pa); 6086 fcport->d_id.b24 = new_fcport->d_id.b24; 6087 break; 6088 } 6089 6090 fcport->d_id.b24 = new_fcport->d_id.b24; 6091 fcport->flags |= FCF_LOGIN_NEEDED; 6092 break; 6093 } 6094 6095 if (found && NVME_TARGET(vha->hw, fcport)) { 6096 if (fcport->disc_state == DSC_DELETE_PEND) { 6097 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 6098 vha->fcport_count--; 6099 fcport->login_succ = 0; 6100 } 6101 } 6102 6103 if (found) { 6104 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6105 continue; 6106 } 6107 /* If device was not in our fcports list, then add it. */ 6108 new_fcport->scan_state = QLA_FCPORT_FOUND; 6109 list_add_tail(&new_fcport->list, &vha->vp_fcports); 6110 6111 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6112 6113 6114 /* Allocate a new replacement fcport. */ 6115 nxt_d_id.b24 = new_fcport->d_id.b24; 6116 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 6117 if (new_fcport == NULL) { 6118 ql_log(ql_log_warn, vha, 0xd032, 6119 "Memory allocation failed for fcport.\n"); 6120 return (QLA_MEMORY_ALLOC_FAILED); 6121 } 6122 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 6123 new_fcport->d_id.b24 = nxt_d_id.b24; 6124 } 6125 6126 qla2x00_free_fcport(new_fcport); 6127 6128 /* 6129 * Logout all previous fabric dev marked lost, except FCP2 devices. 6130 */ 6131 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6132 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6133 break; 6134 6135 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) 6136 continue; 6137 6138 if (fcport->scan_state == QLA_FCPORT_SCAN) { 6139 if ((qla_dual_mode_enabled(vha) || 6140 qla_ini_mode_enabled(vha)) && 6141 atomic_read(&fcport->state) == FCS_ONLINE) { 6142 qla2x00_mark_device_lost(vha, fcport, 6143 ql2xplogiabsentdevice); 6144 if (fcport->loop_id != FC_NO_LOOP_ID && 6145 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 6146 fcport->port_type != FCT_INITIATOR && 6147 fcport->port_type != FCT_BROADCAST) { 6148 ql_dbg(ql_dbg_disc, vha, 0x20f0, 6149 "%s %d %8phC post del sess\n", 6150 __func__, __LINE__, 6151 fcport->port_name); 6152 qlt_schedule_sess_for_deletion(fcport); 6153 continue; 6154 } 6155 } 6156 } 6157 6158 if (fcport->scan_state == QLA_FCPORT_FOUND && 6159 (fcport->flags & FCF_LOGIN_NEEDED) != 0) 6160 qla24xx_fcport_handle_login(vha, fcport); 6161 } 6162 return (rval); 6163 } 6164 6165 /* FW does not set aside Loop id for MGMT Server/FFFFFAh */ 6166 int 6167 qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha) 6168 { 6169 int loop_id = FC_NO_LOOP_ID; 6170 int lid = NPH_MGMT_SERVER - vha->vp_idx; 6171 unsigned long flags; 6172 struct qla_hw_data *ha = vha->hw; 6173 6174 if (vha->vp_idx == 0) { 6175 set_bit(NPH_MGMT_SERVER, ha->loop_id_map); 6176 return NPH_MGMT_SERVER; 6177 } 6178 6179 /* pick id from high and work down to low */ 6180 spin_lock_irqsave(&ha->vport_slock, flags); 6181 for (; lid > 0; lid--) { 6182 if (!test_bit(lid, vha->hw->loop_id_map)) { 6183 set_bit(lid, vha->hw->loop_id_map); 6184 loop_id = lid; 6185 break; 6186 } 6187 } 6188 spin_unlock_irqrestore(&ha->vport_slock, flags); 6189 6190 return loop_id; 6191 } 6192 6193 /* 6194 * qla2x00_fabric_login 6195 * Issue fabric login command. 6196 * 6197 * Input: 6198 * ha = adapter block pointer. 6199 * device = pointer to FC device type structure. 6200 * 6201 * Returns: 6202 * 0 - Login successfully 6203 * 1 - Login failed 6204 * 2 - Initiator device 6205 * 3 - Fatal error 6206 */ 6207 int 6208 qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport, 6209 uint16_t *next_loopid) 6210 { 6211 int rval; 6212 int retry; 6213 uint16_t tmp_loopid; 6214 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6215 struct qla_hw_data *ha = vha->hw; 6216 6217 retry = 0; 6218 tmp_loopid = 0; 6219 6220 for (;;) { 6221 ql_dbg(ql_dbg_disc, vha, 0x2000, 6222 "Trying Fabric Login w/loop id 0x%04x for port " 6223 "%02x%02x%02x.\n", 6224 fcport->loop_id, fcport->d_id.b.domain, 6225 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6226 6227 /* Login fcport on switch. */ 6228 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id, 6229 fcport->d_id.b.domain, fcport->d_id.b.area, 6230 fcport->d_id.b.al_pa, mb, BIT_0); 6231 if (rval != QLA_SUCCESS) { 6232 return rval; 6233 } 6234 if (mb[0] == MBS_PORT_ID_USED) { 6235 /* 6236 * Device has another loop ID. The firmware team 6237 * recommends the driver perform an implicit login with 6238 * the specified ID again. The ID we just used is save 6239 * here so we return with an ID that can be tried by 6240 * the next login. 6241 */ 6242 retry++; 6243 tmp_loopid = fcport->loop_id; 6244 fcport->loop_id = mb[1]; 6245 6246 ql_dbg(ql_dbg_disc, vha, 0x2001, 6247 "Fabric Login: port in use - next loop " 6248 "id=0x%04x, port id= %02x%02x%02x.\n", 6249 fcport->loop_id, fcport->d_id.b.domain, 6250 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6251 6252 } else if (mb[0] == MBS_COMMAND_COMPLETE) { 6253 /* 6254 * Login succeeded. 6255 */ 6256 if (retry) { 6257 /* A retry occurred before. */ 6258 *next_loopid = tmp_loopid; 6259 } else { 6260 /* 6261 * No retry occurred before. Just increment the 6262 * ID value for next login. 6263 */ 6264 *next_loopid = (fcport->loop_id + 1); 6265 } 6266 6267 if (mb[1] & BIT_0) { 6268 fcport->port_type = FCT_INITIATOR; 6269 } else { 6270 fcport->port_type = FCT_TARGET; 6271 if (mb[1] & BIT_1) { 6272 fcport->flags |= FCF_FCP2_DEVICE; 6273 } 6274 } 6275 6276 if (mb[10] & BIT_0) 6277 fcport->supported_classes |= FC_COS_CLASS2; 6278 if (mb[10] & BIT_1) 6279 fcport->supported_classes |= FC_COS_CLASS3; 6280 6281 if (IS_FWI2_CAPABLE(ha)) { 6282 if (mb[10] & BIT_7) 6283 fcport->flags |= 6284 FCF_CONF_COMP_SUPPORTED; 6285 } 6286 6287 rval = QLA_SUCCESS; 6288 break; 6289 } else if (mb[0] == MBS_LOOP_ID_USED) { 6290 /* 6291 * Loop ID already used, try next loop ID. 6292 */ 6293 fcport->loop_id++; 6294 rval = qla2x00_find_new_loop_id(vha, fcport); 6295 if (rval != QLA_SUCCESS) { 6296 /* Ran out of loop IDs to use */ 6297 break; 6298 } 6299 } else if (mb[0] == MBS_COMMAND_ERROR) { 6300 /* 6301 * Firmware possibly timed out during login. If NO 6302 * retries are left to do then the device is declared 6303 * dead. 6304 */ 6305 *next_loopid = fcport->loop_id; 6306 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 6307 fcport->d_id.b.domain, fcport->d_id.b.area, 6308 fcport->d_id.b.al_pa); 6309 qla2x00_mark_device_lost(vha, fcport, 1); 6310 6311 rval = 1; 6312 break; 6313 } else { 6314 /* 6315 * unrecoverable / not handled error 6316 */ 6317 ql_dbg(ql_dbg_disc, vha, 0x2002, 6318 "Failed=%x port_id=%02x%02x%02x loop_id=%x " 6319 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain, 6320 fcport->d_id.b.area, fcport->d_id.b.al_pa, 6321 fcport->loop_id, jiffies); 6322 6323 *next_loopid = fcport->loop_id; 6324 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 6325 fcport->d_id.b.domain, fcport->d_id.b.area, 6326 fcport->d_id.b.al_pa); 6327 qla2x00_clear_loop_id(fcport); 6328 fcport->login_retry = 0; 6329 6330 rval = 3; 6331 break; 6332 } 6333 } 6334 6335 return (rval); 6336 } 6337 6338 /* 6339 * qla2x00_local_device_login 6340 * Issue local device login command. 6341 * 6342 * Input: 6343 * ha = adapter block pointer. 6344 * loop_id = loop id of device to login to. 6345 * 6346 * Returns (Where's the #define!!!!): 6347 * 0 - Login successfully 6348 * 1 - Login failed 6349 * 3 - Fatal error 6350 */ 6351 int 6352 qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport) 6353 { 6354 int rval; 6355 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6356 6357 memset(mb, 0, sizeof(mb)); 6358 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0); 6359 if (rval == QLA_SUCCESS) { 6360 /* Interrogate mailbox registers for any errors */ 6361 if (mb[0] == MBS_COMMAND_ERROR) 6362 rval = 1; 6363 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR) 6364 /* device not in PCB table */ 6365 rval = 3; 6366 } 6367 6368 return (rval); 6369 } 6370 6371 /* 6372 * qla2x00_loop_resync 6373 * Resync with fibre channel devices. 6374 * 6375 * Input: 6376 * ha = adapter block pointer. 6377 * 6378 * Returns: 6379 * 0 = success 6380 */ 6381 int 6382 qla2x00_loop_resync(scsi_qla_host_t *vha) 6383 { 6384 int rval = QLA_SUCCESS; 6385 uint32_t wait_time; 6386 6387 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 6388 if (vha->flags.online) { 6389 if (!(rval = qla2x00_fw_ready(vha))) { 6390 /* Wait at most MAX_TARGET RSCNs for a stable link. */ 6391 wait_time = 256; 6392 do { 6393 if (!IS_QLAFX00(vha->hw)) { 6394 /* 6395 * Issue a marker after FW becomes 6396 * ready. 6397 */ 6398 qla2x00_marker(vha, vha->hw->base_qpair, 6399 0, 0, MK_SYNC_ALL); 6400 vha->marker_needed = 0; 6401 } 6402 6403 /* Remap devices on Loop. */ 6404 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 6405 6406 if (IS_QLAFX00(vha->hw)) 6407 qlafx00_configure_devices(vha); 6408 else 6409 qla2x00_configure_loop(vha); 6410 6411 wait_time--; 6412 } while (!atomic_read(&vha->loop_down_timer) && 6413 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 6414 && wait_time && (test_bit(LOOP_RESYNC_NEEDED, 6415 &vha->dpc_flags))); 6416 } 6417 } 6418 6419 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 6420 return (QLA_FUNCTION_FAILED); 6421 6422 if (rval) 6423 ql_dbg(ql_dbg_disc, vha, 0x206c, 6424 "%s *** FAILED ***.\n", __func__); 6425 6426 return (rval); 6427 } 6428 6429 /* 6430 * qla2x00_perform_loop_resync 6431 * Description: This function will set the appropriate flags and call 6432 * qla2x00_loop_resync. If successful loop will be resynced 6433 * Arguments : scsi_qla_host_t pointer 6434 * returm : Success or Failure 6435 */ 6436 6437 int qla2x00_perform_loop_resync(scsi_qla_host_t *ha) 6438 { 6439 int32_t rval = 0; 6440 6441 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) { 6442 /*Configure the flags so that resync happens properly*/ 6443 atomic_set(&ha->loop_down_timer, 0); 6444 if (!(ha->device_flags & DFLG_NO_CABLE)) { 6445 atomic_set(&ha->loop_state, LOOP_UP); 6446 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); 6447 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); 6448 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); 6449 6450 rval = qla2x00_loop_resync(ha); 6451 } else 6452 atomic_set(&ha->loop_state, LOOP_DEAD); 6453 6454 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags); 6455 } 6456 6457 return rval; 6458 } 6459 6460 void 6461 qla2x00_update_fcports(scsi_qla_host_t *base_vha) 6462 { 6463 fc_port_t *fcport; 6464 struct scsi_qla_host *vha; 6465 struct qla_hw_data *ha = base_vha->hw; 6466 unsigned long flags; 6467 6468 spin_lock_irqsave(&ha->vport_slock, flags); 6469 /* Go with deferred removal of rport references. */ 6470 list_for_each_entry(vha, &base_vha->hw->vp_list, list) { 6471 atomic_inc(&vha->vref_count); 6472 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6473 if (fcport->drport && 6474 atomic_read(&fcport->state) != FCS_UNCONFIGURED) { 6475 spin_unlock_irqrestore(&ha->vport_slock, flags); 6476 qla2x00_rport_del(fcport); 6477 6478 spin_lock_irqsave(&ha->vport_slock, flags); 6479 } 6480 } 6481 atomic_dec(&vha->vref_count); 6482 wake_up(&vha->vref_waitq); 6483 } 6484 spin_unlock_irqrestore(&ha->vport_slock, flags); 6485 } 6486 6487 /* Assumes idc_lock always held on entry */ 6488 void 6489 qla83xx_reset_ownership(scsi_qla_host_t *vha) 6490 { 6491 struct qla_hw_data *ha = vha->hw; 6492 uint32_t drv_presence, drv_presence_mask; 6493 uint32_t dev_part_info1, dev_part_info2, class_type; 6494 uint32_t class_type_mask = 0x3; 6495 uint16_t fcoe_other_function = 0xffff, i; 6496 6497 if (IS_QLA8044(ha)) { 6498 drv_presence = qla8044_rd_direct(vha, 6499 QLA8044_CRB_DRV_ACTIVE_INDEX); 6500 dev_part_info1 = qla8044_rd_direct(vha, 6501 QLA8044_CRB_DEV_PART_INFO_INDEX); 6502 dev_part_info2 = qla8044_rd_direct(vha, 6503 QLA8044_CRB_DEV_PART_INFO2); 6504 } else { 6505 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6506 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1); 6507 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2); 6508 } 6509 for (i = 0; i < 8; i++) { 6510 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask); 6511 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 6512 (i != ha->portnum)) { 6513 fcoe_other_function = i; 6514 break; 6515 } 6516 } 6517 if (fcoe_other_function == 0xffff) { 6518 for (i = 0; i < 8; i++) { 6519 class_type = ((dev_part_info2 >> (i * 4)) & 6520 class_type_mask); 6521 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 6522 ((i + 8) != ha->portnum)) { 6523 fcoe_other_function = i + 8; 6524 break; 6525 } 6526 } 6527 } 6528 /* 6529 * Prepare drv-presence mask based on fcoe functions present. 6530 * However consider only valid physical fcoe function numbers (0-15). 6531 */ 6532 drv_presence_mask = ~((1 << (ha->portnum)) | 6533 ((fcoe_other_function == 0xffff) ? 6534 0 : (1 << (fcoe_other_function)))); 6535 6536 /* We are the reset owner iff: 6537 * - No other protocol drivers present. 6538 * - This is the lowest among fcoe functions. */ 6539 if (!(drv_presence & drv_presence_mask) && 6540 (ha->portnum < fcoe_other_function)) { 6541 ql_dbg(ql_dbg_p3p, vha, 0xb07f, 6542 "This host is Reset owner.\n"); 6543 ha->flags.nic_core_reset_owner = 1; 6544 } 6545 } 6546 6547 static int 6548 __qla83xx_set_drv_ack(scsi_qla_host_t *vha) 6549 { 6550 int rval = QLA_SUCCESS; 6551 struct qla_hw_data *ha = vha->hw; 6552 uint32_t drv_ack; 6553 6554 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6555 if (rval == QLA_SUCCESS) { 6556 drv_ack |= (1 << ha->portnum); 6557 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 6558 } 6559 6560 return rval; 6561 } 6562 6563 static int 6564 __qla83xx_clear_drv_ack(scsi_qla_host_t *vha) 6565 { 6566 int rval = QLA_SUCCESS; 6567 struct qla_hw_data *ha = vha->hw; 6568 uint32_t drv_ack; 6569 6570 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6571 if (rval == QLA_SUCCESS) { 6572 drv_ack &= ~(1 << ha->portnum); 6573 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 6574 } 6575 6576 return rval; 6577 } 6578 6579 static const char * 6580 qla83xx_dev_state_to_string(uint32_t dev_state) 6581 { 6582 switch (dev_state) { 6583 case QLA8XXX_DEV_COLD: 6584 return "COLD/RE-INIT"; 6585 case QLA8XXX_DEV_INITIALIZING: 6586 return "INITIALIZING"; 6587 case QLA8XXX_DEV_READY: 6588 return "READY"; 6589 case QLA8XXX_DEV_NEED_RESET: 6590 return "NEED RESET"; 6591 case QLA8XXX_DEV_NEED_QUIESCENT: 6592 return "NEED QUIESCENT"; 6593 case QLA8XXX_DEV_FAILED: 6594 return "FAILED"; 6595 case QLA8XXX_DEV_QUIESCENT: 6596 return "QUIESCENT"; 6597 default: 6598 return "Unknown"; 6599 } 6600 } 6601 6602 /* Assumes idc-lock always held on entry */ 6603 void 6604 qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type) 6605 { 6606 struct qla_hw_data *ha = vha->hw; 6607 uint32_t idc_audit_reg = 0, duration_secs = 0; 6608 6609 switch (audit_type) { 6610 case IDC_AUDIT_TIMESTAMP: 6611 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000); 6612 idc_audit_reg = (ha->portnum) | 6613 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8); 6614 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 6615 break; 6616 6617 case IDC_AUDIT_COMPLETION: 6618 duration_secs = ((jiffies_to_msecs(jiffies) - 6619 jiffies_to_msecs(ha->idc_audit_ts)) / 1000); 6620 idc_audit_reg = (ha->portnum) | 6621 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8); 6622 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 6623 break; 6624 6625 default: 6626 ql_log(ql_log_warn, vha, 0xb078, 6627 "Invalid audit type specified.\n"); 6628 break; 6629 } 6630 } 6631 6632 /* Assumes idc_lock always held on entry */ 6633 static int 6634 qla83xx_initiating_reset(scsi_qla_host_t *vha) 6635 { 6636 struct qla_hw_data *ha = vha->hw; 6637 uint32_t idc_control, dev_state; 6638 6639 __qla83xx_get_idc_control(vha, &idc_control); 6640 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) { 6641 ql_log(ql_log_info, vha, 0xb080, 6642 "NIC Core reset has been disabled. idc-control=0x%x\n", 6643 idc_control); 6644 return QLA_FUNCTION_FAILED; 6645 } 6646 6647 /* Set NEED-RESET iff in READY state and we are the reset-owner */ 6648 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6649 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) { 6650 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 6651 QLA8XXX_DEV_NEED_RESET); 6652 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n"); 6653 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP); 6654 } else { 6655 const char *state = qla83xx_dev_state_to_string(dev_state); 6656 6657 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state); 6658 6659 /* SV: XXX: Is timeout required here? */ 6660 /* Wait for IDC state change READY -> NEED_RESET */ 6661 while (dev_state == QLA8XXX_DEV_READY) { 6662 qla83xx_idc_unlock(vha, 0); 6663 msleep(200); 6664 qla83xx_idc_lock(vha, 0); 6665 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6666 } 6667 } 6668 6669 /* Send IDC ack by writing to drv-ack register */ 6670 __qla83xx_set_drv_ack(vha); 6671 6672 return QLA_SUCCESS; 6673 } 6674 6675 int 6676 __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) 6677 { 6678 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 6679 } 6680 6681 int 6682 __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) 6683 { 6684 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 6685 } 6686 6687 static int 6688 qla83xx_check_driver_presence(scsi_qla_host_t *vha) 6689 { 6690 uint32_t drv_presence = 0; 6691 struct qla_hw_data *ha = vha->hw; 6692 6693 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6694 if (drv_presence & (1 << ha->portnum)) 6695 return QLA_SUCCESS; 6696 else 6697 return QLA_TEST_FAILED; 6698 } 6699 6700 int 6701 qla83xx_nic_core_reset(scsi_qla_host_t *vha) 6702 { 6703 int rval = QLA_SUCCESS; 6704 struct qla_hw_data *ha = vha->hw; 6705 6706 ql_dbg(ql_dbg_p3p, vha, 0xb058, 6707 "Entered %s().\n", __func__); 6708 6709 if (vha->device_flags & DFLG_DEV_FAILED) { 6710 ql_log(ql_log_warn, vha, 0xb059, 6711 "Device in unrecoverable FAILED state.\n"); 6712 return QLA_FUNCTION_FAILED; 6713 } 6714 6715 qla83xx_idc_lock(vha, 0); 6716 6717 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) { 6718 ql_log(ql_log_warn, vha, 0xb05a, 6719 "Function=0x%x has been removed from IDC participation.\n", 6720 ha->portnum); 6721 rval = QLA_FUNCTION_FAILED; 6722 goto exit; 6723 } 6724 6725 qla83xx_reset_ownership(vha); 6726 6727 rval = qla83xx_initiating_reset(vha); 6728 6729 /* 6730 * Perform reset if we are the reset-owner, 6731 * else wait till IDC state changes to READY/FAILED. 6732 */ 6733 if (rval == QLA_SUCCESS) { 6734 rval = qla83xx_idc_state_handler(vha); 6735 6736 if (rval == QLA_SUCCESS) 6737 ha->flags.nic_core_hung = 0; 6738 __qla83xx_clear_drv_ack(vha); 6739 } 6740 6741 exit: 6742 qla83xx_idc_unlock(vha, 0); 6743 6744 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__); 6745 6746 return rval; 6747 } 6748 6749 int 6750 qla2xxx_mctp_dump(scsi_qla_host_t *vha) 6751 { 6752 struct qla_hw_data *ha = vha->hw; 6753 int rval = QLA_FUNCTION_FAILED; 6754 6755 if (!IS_MCTP_CAPABLE(ha)) { 6756 /* This message can be removed from the final version */ 6757 ql_log(ql_log_info, vha, 0x506d, 6758 "This board is not MCTP capable\n"); 6759 return rval; 6760 } 6761 6762 if (!ha->mctp_dump) { 6763 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev, 6764 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL); 6765 6766 if (!ha->mctp_dump) { 6767 ql_log(ql_log_warn, vha, 0x506e, 6768 "Failed to allocate memory for mctp dump\n"); 6769 return rval; 6770 } 6771 } 6772 6773 #define MCTP_DUMP_STR_ADDR 0x00000000 6774 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma, 6775 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4); 6776 if (rval != QLA_SUCCESS) { 6777 ql_log(ql_log_warn, vha, 0x506f, 6778 "Failed to capture mctp dump\n"); 6779 } else { 6780 ql_log(ql_log_info, vha, 0x5070, 6781 "Mctp dump capture for host (%ld/%p).\n", 6782 vha->host_no, ha->mctp_dump); 6783 ha->mctp_dumped = 1; 6784 } 6785 6786 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) { 6787 ha->flags.nic_core_reset_hdlr_active = 1; 6788 rval = qla83xx_restart_nic_firmware(vha); 6789 if (rval) 6790 /* NIC Core reset failed. */ 6791 ql_log(ql_log_warn, vha, 0x5071, 6792 "Failed to restart nic firmware\n"); 6793 else 6794 ql_dbg(ql_dbg_p3p, vha, 0xb084, 6795 "Restarted NIC firmware successfully.\n"); 6796 ha->flags.nic_core_reset_hdlr_active = 0; 6797 } 6798 6799 return rval; 6800 6801 } 6802 6803 /* 6804 * qla2x00_quiesce_io 6805 * Description: This function will block the new I/Os 6806 * Its not aborting any I/Os as context 6807 * is not destroyed during quiescence 6808 * Arguments: scsi_qla_host_t 6809 * return : void 6810 */ 6811 void 6812 qla2x00_quiesce_io(scsi_qla_host_t *vha) 6813 { 6814 struct qla_hw_data *ha = vha->hw; 6815 struct scsi_qla_host *vp; 6816 6817 ql_dbg(ql_dbg_dpc, vha, 0x401d, 6818 "Quiescing I/O - ha=%p.\n", ha); 6819 6820 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); 6821 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 6822 atomic_set(&vha->loop_state, LOOP_DOWN); 6823 qla2x00_mark_all_devices_lost(vha); 6824 list_for_each_entry(vp, &ha->vp_list, list) 6825 qla2x00_mark_all_devices_lost(vp); 6826 } else { 6827 if (!atomic_read(&vha->loop_down_timer)) 6828 atomic_set(&vha->loop_down_timer, 6829 LOOP_DOWN_TIME); 6830 } 6831 /* Wait for pending cmds to complete */ 6832 WARN_ON_ONCE(qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) 6833 != QLA_SUCCESS); 6834 } 6835 6836 void 6837 qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) 6838 { 6839 struct qla_hw_data *ha = vha->hw; 6840 struct scsi_qla_host *vp; 6841 unsigned long flags; 6842 fc_port_t *fcport; 6843 u16 i; 6844 6845 /* For ISP82XX, driver waits for completion of the commands. 6846 * online flag should be set. 6847 */ 6848 if (!(IS_P3P_TYPE(ha))) 6849 vha->flags.online = 0; 6850 ha->flags.chip_reset_done = 0; 6851 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 6852 vha->qla_stats.total_isp_aborts++; 6853 6854 ql_log(ql_log_info, vha, 0x00af, 6855 "Performing ISP error recovery - ha=%p.\n", ha); 6856 6857 ha->flags.purge_mbox = 1; 6858 /* For ISP82XX, reset_chip is just disabling interrupts. 6859 * Driver waits for the completion of the commands. 6860 * the interrupts need to be enabled. 6861 */ 6862 if (!(IS_P3P_TYPE(ha))) 6863 ha->isp_ops->reset_chip(vha); 6864 6865 ha->link_data_rate = PORT_SPEED_UNKNOWN; 6866 SAVE_TOPO(ha); 6867 ha->flags.rida_fmt2 = 0; 6868 ha->flags.n2n_ae = 0; 6869 ha->flags.lip_ae = 0; 6870 ha->current_topology = 0; 6871 QLA_FW_STOPPED(ha); 6872 ha->flags.fw_init_done = 0; 6873 ha->chip_reset++; 6874 ha->base_qpair->chip_reset = ha->chip_reset; 6875 for (i = 0; i < ha->max_qpairs; i++) { 6876 if (ha->queue_pair_map[i]) 6877 ha->queue_pair_map[i]->chip_reset = 6878 ha->base_qpair->chip_reset; 6879 } 6880 6881 /* purge MBox commands */ 6882 if (atomic_read(&ha->num_pend_mbx_stage3)) { 6883 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 6884 complete(&ha->mbx_intr_comp); 6885 } 6886 6887 i = 0; 6888 while (atomic_read(&ha->num_pend_mbx_stage3) || 6889 atomic_read(&ha->num_pend_mbx_stage2) || 6890 atomic_read(&ha->num_pend_mbx_stage1)) { 6891 msleep(20); 6892 i++; 6893 if (i > 50) 6894 break; 6895 } 6896 ha->flags.purge_mbox = 0; 6897 6898 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 6899 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 6900 atomic_set(&vha->loop_state, LOOP_DOWN); 6901 qla2x00_mark_all_devices_lost(vha); 6902 6903 spin_lock_irqsave(&ha->vport_slock, flags); 6904 list_for_each_entry(vp, &ha->vp_list, list) { 6905 atomic_inc(&vp->vref_count); 6906 spin_unlock_irqrestore(&ha->vport_slock, flags); 6907 6908 qla2x00_mark_all_devices_lost(vp); 6909 6910 spin_lock_irqsave(&ha->vport_slock, flags); 6911 atomic_dec(&vp->vref_count); 6912 } 6913 spin_unlock_irqrestore(&ha->vport_slock, flags); 6914 } else { 6915 if (!atomic_read(&vha->loop_down_timer)) 6916 atomic_set(&vha->loop_down_timer, 6917 LOOP_DOWN_TIME); 6918 } 6919 6920 /* Clear all async request states across all VPs. */ 6921 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6922 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6923 fcport->scan_state = 0; 6924 } 6925 spin_lock_irqsave(&ha->vport_slock, flags); 6926 list_for_each_entry(vp, &ha->vp_list, list) { 6927 atomic_inc(&vp->vref_count); 6928 spin_unlock_irqrestore(&ha->vport_slock, flags); 6929 6930 list_for_each_entry(fcport, &vp->vp_fcports, list) 6931 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6932 6933 spin_lock_irqsave(&ha->vport_slock, flags); 6934 atomic_dec(&vp->vref_count); 6935 } 6936 spin_unlock_irqrestore(&ha->vport_slock, flags); 6937 6938 /* Make sure for ISP 82XX IO DMA is complete */ 6939 if (IS_P3P_TYPE(ha)) { 6940 qla82xx_chip_reset_cleanup(vha); 6941 ql_log(ql_log_info, vha, 0x00b4, 6942 "Done chip reset cleanup.\n"); 6943 6944 /* Done waiting for pending commands. Reset online flag */ 6945 vha->flags.online = 0; 6946 } 6947 6948 /* Requeue all commands in outstanding command list. */ 6949 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6950 /* memory barrier */ 6951 wmb(); 6952 } 6953 6954 /* 6955 * qla2x00_abort_isp 6956 * Resets ISP and aborts all outstanding commands. 6957 * 6958 * Input: 6959 * ha = adapter block pointer. 6960 * 6961 * Returns: 6962 * 0 = success 6963 */ 6964 int 6965 qla2x00_abort_isp(scsi_qla_host_t *vha) 6966 { 6967 int rval; 6968 uint8_t status = 0; 6969 struct qla_hw_data *ha = vha->hw; 6970 struct scsi_qla_host *vp; 6971 struct req_que *req = ha->req_q_map[0]; 6972 unsigned long flags; 6973 6974 if (vha->flags.online) { 6975 qla2x00_abort_isp_cleanup(vha); 6976 6977 if (vha->hw->flags.port_isolated) 6978 return status; 6979 6980 if (qla2x00_isp_reg_stat(ha)) { 6981 ql_log(ql_log_info, vha, 0x803f, 6982 "ISP Abort - ISP reg disconnect, exiting.\n"); 6983 return status; 6984 } 6985 6986 if (test_and_clear_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags)) { 6987 ha->flags.chip_reset_done = 1; 6988 vha->flags.online = 1; 6989 status = 0; 6990 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 6991 return status; 6992 } 6993 6994 if (IS_QLA8031(ha)) { 6995 ql_dbg(ql_dbg_p3p, vha, 0xb05c, 6996 "Clearing fcoe driver presence.\n"); 6997 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS) 6998 ql_dbg(ql_dbg_p3p, vha, 0xb073, 6999 "Error while clearing DRV-Presence.\n"); 7000 } 7001 7002 if (unlikely(pci_channel_offline(ha->pdev) && 7003 ha->flags.pci_channel_io_perm_failure)) { 7004 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7005 status = 0; 7006 return status; 7007 } 7008 7009 switch (vha->qlini_mode) { 7010 case QLA2XXX_INI_MODE_DISABLED: 7011 if (!qla_tgt_mode_enabled(vha)) 7012 return 0; 7013 break; 7014 case QLA2XXX_INI_MODE_DUAL: 7015 if (!qla_dual_mode_enabled(vha)) 7016 return 0; 7017 break; 7018 case QLA2XXX_INI_MODE_ENABLED: 7019 default: 7020 break; 7021 } 7022 7023 ha->isp_ops->get_flash_version(vha, req->ring); 7024 7025 if (qla2x00_isp_reg_stat(ha)) { 7026 ql_log(ql_log_info, vha, 0x803f, 7027 "ISP Abort - ISP reg disconnect pre nvram config, exiting.\n"); 7028 return status; 7029 } 7030 ha->isp_ops->nvram_config(vha); 7031 7032 if (qla2x00_isp_reg_stat(ha)) { 7033 ql_log(ql_log_info, vha, 0x803f, 7034 "ISP Abort - ISP reg disconnect post nvmram config, exiting.\n"); 7035 return status; 7036 } 7037 if (!qla2x00_restart_isp(vha)) { 7038 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7039 7040 if (!atomic_read(&vha->loop_down_timer)) { 7041 /* 7042 * Issue marker command only when we are going 7043 * to start the I/O . 7044 */ 7045 vha->marker_needed = 1; 7046 } 7047 7048 vha->flags.online = 1; 7049 7050 ha->isp_ops->enable_intrs(ha); 7051 7052 ha->isp_abort_cnt = 0; 7053 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7054 7055 if (IS_QLA81XX(ha) || IS_QLA8031(ha)) 7056 qla2x00_get_fw_version(vha); 7057 if (ha->fce) { 7058 ha->flags.fce_enabled = 1; 7059 memset(ha->fce, 0, 7060 fce_calc_size(ha->fce_bufs)); 7061 rval = qla2x00_enable_fce_trace(vha, 7062 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 7063 &ha->fce_bufs); 7064 if (rval) { 7065 ql_log(ql_log_warn, vha, 0x8033, 7066 "Unable to reinitialize FCE " 7067 "(%d).\n", rval); 7068 ha->flags.fce_enabled = 0; 7069 } 7070 } 7071 7072 if (ha->eft) { 7073 memset(ha->eft, 0, EFT_SIZE); 7074 rval = qla2x00_enable_eft_trace(vha, 7075 ha->eft_dma, EFT_NUM_BUFFERS); 7076 if (rval) { 7077 ql_log(ql_log_warn, vha, 0x8034, 7078 "Unable to reinitialize EFT " 7079 "(%d).\n", rval); 7080 } 7081 } 7082 } else { /* failed the ISP abort */ 7083 vha->flags.online = 1; 7084 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 7085 if (ha->isp_abort_cnt == 0) { 7086 ql_log(ql_log_fatal, vha, 0x8035, 7087 "ISP error recover failed - " 7088 "board disabled.\n"); 7089 /* 7090 * The next call disables the board 7091 * completely. 7092 */ 7093 qla2x00_abort_isp_cleanup(vha); 7094 vha->flags.online = 0; 7095 clear_bit(ISP_ABORT_RETRY, 7096 &vha->dpc_flags); 7097 status = 0; 7098 } else { /* schedule another ISP abort */ 7099 ha->isp_abort_cnt--; 7100 ql_dbg(ql_dbg_taskm, vha, 0x8020, 7101 "ISP abort - retry remaining %d.\n", 7102 ha->isp_abort_cnt); 7103 status = 1; 7104 } 7105 } else { 7106 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 7107 ql_dbg(ql_dbg_taskm, vha, 0x8021, 7108 "ISP error recovery - retrying (%d) " 7109 "more times.\n", ha->isp_abort_cnt); 7110 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7111 status = 1; 7112 } 7113 } 7114 7115 } 7116 7117 if (vha->hw->flags.port_isolated) { 7118 qla2x00_abort_isp_cleanup(vha); 7119 return status; 7120 } 7121 7122 if (!status) { 7123 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__); 7124 qla2x00_configure_hba(vha); 7125 spin_lock_irqsave(&ha->vport_slock, flags); 7126 list_for_each_entry(vp, &ha->vp_list, list) { 7127 if (vp->vp_idx) { 7128 atomic_inc(&vp->vref_count); 7129 spin_unlock_irqrestore(&ha->vport_slock, flags); 7130 7131 qla2x00_vp_abort_isp(vp); 7132 7133 spin_lock_irqsave(&ha->vport_slock, flags); 7134 atomic_dec(&vp->vref_count); 7135 } 7136 } 7137 spin_unlock_irqrestore(&ha->vport_slock, flags); 7138 7139 if (IS_QLA8031(ha)) { 7140 ql_dbg(ql_dbg_p3p, vha, 0xb05d, 7141 "Setting back fcoe driver presence.\n"); 7142 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS) 7143 ql_dbg(ql_dbg_p3p, vha, 0xb074, 7144 "Error while setting DRV-Presence.\n"); 7145 } 7146 } else { 7147 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n", 7148 __func__); 7149 } 7150 7151 return(status); 7152 } 7153 7154 /* 7155 * qla2x00_restart_isp 7156 * restarts the ISP after a reset 7157 * 7158 * Input: 7159 * ha = adapter block pointer. 7160 * 7161 * Returns: 7162 * 0 = success 7163 */ 7164 static int 7165 qla2x00_restart_isp(scsi_qla_host_t *vha) 7166 { 7167 int status; 7168 struct qla_hw_data *ha = vha->hw; 7169 7170 /* If firmware needs to be loaded */ 7171 if (qla2x00_isp_firmware(vha)) { 7172 vha->flags.online = 0; 7173 status = ha->isp_ops->chip_diag(vha); 7174 if (status) 7175 return status; 7176 status = qla2x00_setup_chip(vha); 7177 if (status) 7178 return status; 7179 } 7180 7181 status = qla2x00_init_rings(vha); 7182 if (status) 7183 return status; 7184 7185 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7186 ha->flags.chip_reset_done = 1; 7187 7188 /* Initialize the queues in use */ 7189 qla25xx_init_queues(ha); 7190 7191 status = qla2x00_fw_ready(vha); 7192 if (status) { 7193 /* if no cable then assume it's good */ 7194 return vha->device_flags & DFLG_NO_CABLE ? 0 : status; 7195 } 7196 7197 /* Issue a marker after FW becomes ready. */ 7198 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 7199 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 7200 7201 return 0; 7202 } 7203 7204 static int 7205 qla25xx_init_queues(struct qla_hw_data *ha) 7206 { 7207 struct rsp_que *rsp = NULL; 7208 struct req_que *req = NULL; 7209 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7210 int ret = -1; 7211 int i; 7212 7213 for (i = 1; i < ha->max_rsp_queues; i++) { 7214 rsp = ha->rsp_q_map[i]; 7215 if (rsp && test_bit(i, ha->rsp_qid_map)) { 7216 rsp->options &= ~BIT_0; 7217 ret = qla25xx_init_rsp_que(base_vha, rsp); 7218 if (ret != QLA_SUCCESS) 7219 ql_dbg(ql_dbg_init, base_vha, 0x00ff, 7220 "%s Rsp que: %d init failed.\n", 7221 __func__, rsp->id); 7222 else 7223 ql_dbg(ql_dbg_init, base_vha, 0x0100, 7224 "%s Rsp que: %d inited.\n", 7225 __func__, rsp->id); 7226 } 7227 } 7228 for (i = 1; i < ha->max_req_queues; i++) { 7229 req = ha->req_q_map[i]; 7230 if (req && test_bit(i, ha->req_qid_map)) { 7231 /* Clear outstanding commands array. */ 7232 req->options &= ~BIT_0; 7233 ret = qla25xx_init_req_que(base_vha, req); 7234 if (ret != QLA_SUCCESS) 7235 ql_dbg(ql_dbg_init, base_vha, 0x0101, 7236 "%s Req que: %d init failed.\n", 7237 __func__, req->id); 7238 else 7239 ql_dbg(ql_dbg_init, base_vha, 0x0102, 7240 "%s Req que: %d inited.\n", 7241 __func__, req->id); 7242 } 7243 } 7244 return ret; 7245 } 7246 7247 /* 7248 * qla2x00_reset_adapter 7249 * Reset adapter. 7250 * 7251 * Input: 7252 * ha = adapter block pointer. 7253 */ 7254 int 7255 qla2x00_reset_adapter(scsi_qla_host_t *vha) 7256 { 7257 unsigned long flags = 0; 7258 struct qla_hw_data *ha = vha->hw; 7259 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7260 7261 vha->flags.online = 0; 7262 ha->isp_ops->disable_intrs(ha); 7263 7264 spin_lock_irqsave(&ha->hardware_lock, flags); 7265 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 7266 rd_reg_word(®->hccr); /* PCI Posting. */ 7267 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 7268 rd_reg_word(®->hccr); /* PCI Posting. */ 7269 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7270 7271 return QLA_SUCCESS; 7272 } 7273 7274 int 7275 qla24xx_reset_adapter(scsi_qla_host_t *vha) 7276 { 7277 unsigned long flags = 0; 7278 struct qla_hw_data *ha = vha->hw; 7279 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 7280 7281 if (IS_P3P_TYPE(ha)) 7282 return QLA_SUCCESS; 7283 7284 vha->flags.online = 0; 7285 ha->isp_ops->disable_intrs(ha); 7286 7287 spin_lock_irqsave(&ha->hardware_lock, flags); 7288 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET); 7289 rd_reg_dword(®->hccr); 7290 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE); 7291 rd_reg_dword(®->hccr); 7292 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7293 7294 if (IS_NOPOLLING_TYPE(ha)) 7295 ha->isp_ops->enable_intrs(ha); 7296 7297 return QLA_SUCCESS; 7298 } 7299 7300 /* On sparc systems, obtain port and node WWN from firmware 7301 * properties. 7302 */ 7303 static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, 7304 struct nvram_24xx *nv) 7305 { 7306 #ifdef CONFIG_SPARC 7307 struct qla_hw_data *ha = vha->hw; 7308 struct pci_dev *pdev = ha->pdev; 7309 struct device_node *dp = pci_device_to_OF_node(pdev); 7310 const u8 *val; 7311 int len; 7312 7313 val = of_get_property(dp, "port-wwn", &len); 7314 if (val && len >= WWN_SIZE) 7315 memcpy(nv->port_name, val, WWN_SIZE); 7316 7317 val = of_get_property(dp, "node-wwn", &len); 7318 if (val && len >= WWN_SIZE) 7319 memcpy(nv->node_name, val, WWN_SIZE); 7320 #endif 7321 } 7322 7323 int 7324 qla24xx_nvram_config(scsi_qla_host_t *vha) 7325 { 7326 int rval; 7327 struct init_cb_24xx *icb; 7328 struct nvram_24xx *nv; 7329 __le32 *dptr; 7330 uint8_t *dptr1, *dptr2; 7331 uint32_t chksum; 7332 uint16_t cnt; 7333 struct qla_hw_data *ha = vha->hw; 7334 7335 rval = QLA_SUCCESS; 7336 icb = (struct init_cb_24xx *)ha->init_cb; 7337 nv = ha->nvram; 7338 7339 /* Determine NVRAM starting address. */ 7340 if (ha->port_no == 0) { 7341 ha->nvram_base = FA_NVRAM_FUNC0_ADDR; 7342 ha->vpd_base = FA_NVRAM_VPD0_ADDR; 7343 } else { 7344 ha->nvram_base = FA_NVRAM_FUNC1_ADDR; 7345 ha->vpd_base = FA_NVRAM_VPD1_ADDR; 7346 } 7347 7348 ha->nvram_size = sizeof(*nv); 7349 ha->vpd_size = FA_NVRAM_VPD_SIZE; 7350 7351 /* Get VPD data into cache */ 7352 ha->vpd = ha->nvram + VPD_OFFSET; 7353 ha->isp_ops->read_nvram(vha, ha->vpd, 7354 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4); 7355 7356 /* Get NVRAM data into cache and calculate checksum. */ 7357 dptr = (__force __le32 *)nv; 7358 ha->isp_ops->read_nvram(vha, dptr, ha->nvram_base, ha->nvram_size); 7359 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 7360 chksum += le32_to_cpu(*dptr); 7361 7362 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a, 7363 "Contents of NVRAM\n"); 7364 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d, 7365 nv, ha->nvram_size); 7366 7367 /* Bad NVRAM data, set defaults parameters. */ 7368 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 7369 le16_to_cpu(nv->nvram_version) < ICB_VERSION) { 7370 /* Reset NVRAM data. */ 7371 ql_log(ql_log_warn, vha, 0x006b, 7372 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n", 7373 chksum, nv->id, nv->nvram_version); 7374 ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, sizeof(*nv)); 7375 ql_log(ql_log_warn, vha, 0x006c, 7376 "Falling back to functioning (yet invalid -- WWPN) " 7377 "defaults.\n"); 7378 7379 /* 7380 * Set default initialization control block. 7381 */ 7382 memset(nv, 0, ha->nvram_size); 7383 nv->nvram_version = cpu_to_le16(ICB_VERSION); 7384 nv->version = cpu_to_le16(ICB_VERSION); 7385 nv->frame_payload_size = cpu_to_le16(2048); 7386 nv->execution_throttle = cpu_to_le16(0xFFFF); 7387 nv->exchange_count = cpu_to_le16(0); 7388 nv->hard_address = cpu_to_le16(124); 7389 nv->port_name[0] = 0x21; 7390 nv->port_name[1] = 0x00 + ha->port_no + 1; 7391 nv->port_name[2] = 0x00; 7392 nv->port_name[3] = 0xe0; 7393 nv->port_name[4] = 0x8b; 7394 nv->port_name[5] = 0x1c; 7395 nv->port_name[6] = 0x55; 7396 nv->port_name[7] = 0x86; 7397 nv->node_name[0] = 0x20; 7398 nv->node_name[1] = 0x00; 7399 nv->node_name[2] = 0x00; 7400 nv->node_name[3] = 0xe0; 7401 nv->node_name[4] = 0x8b; 7402 nv->node_name[5] = 0x1c; 7403 nv->node_name[6] = 0x55; 7404 nv->node_name[7] = 0x86; 7405 qla24xx_nvram_wwn_from_ofw(vha, nv); 7406 nv->login_retry_count = cpu_to_le16(8); 7407 nv->interrupt_delay_timer = cpu_to_le16(0); 7408 nv->login_timeout = cpu_to_le16(0); 7409 nv->firmware_options_1 = 7410 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 7411 nv->firmware_options_2 = cpu_to_le32(2 << 4); 7412 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 7413 nv->firmware_options_3 = cpu_to_le32(2 << 13); 7414 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 7415 nv->efi_parameters = cpu_to_le32(0); 7416 nv->reset_delay = 5; 7417 nv->max_luns_per_target = cpu_to_le16(128); 7418 nv->port_down_retry_count = cpu_to_le16(30); 7419 nv->link_down_timeout = cpu_to_le16(30); 7420 7421 rval = 1; 7422 } 7423 7424 if (qla_tgt_mode_enabled(vha)) { 7425 /* Don't enable full login after initial LIP */ 7426 nv->firmware_options_1 &= cpu_to_le32(~BIT_13); 7427 /* Don't enable LIP full login for initiator */ 7428 nv->host_p &= cpu_to_le32(~BIT_10); 7429 } 7430 7431 qlt_24xx_config_nvram_stage1(vha, nv); 7432 7433 /* Reset Initialization control block */ 7434 memset(icb, 0, ha->init_cb_size); 7435 7436 /* Copy 1st segment. */ 7437 dptr1 = (uint8_t *)icb; 7438 dptr2 = (uint8_t *)&nv->version; 7439 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 7440 while (cnt--) 7441 *dptr1++ = *dptr2++; 7442 7443 icb->login_retry_count = nv->login_retry_count; 7444 icb->link_down_on_nos = nv->link_down_on_nos; 7445 7446 /* Copy 2nd segment. */ 7447 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 7448 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 7449 cnt = (uint8_t *)&icb->reserved_3 - 7450 (uint8_t *)&icb->interrupt_delay_timer; 7451 while (cnt--) 7452 *dptr1++ = *dptr2++; 7453 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 7454 /* 7455 * Setup driver NVRAM options. 7456 */ 7457 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 7458 "QLA2462"); 7459 7460 qlt_24xx_config_nvram_stage2(vha, icb); 7461 7462 if (nv->host_p & cpu_to_le32(BIT_15)) { 7463 /* Use alternate WWN? */ 7464 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 7465 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 7466 } 7467 7468 /* Prepare nodename */ 7469 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 7470 /* 7471 * Firmware will apply the following mask if the nodename was 7472 * not provided. 7473 */ 7474 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 7475 icb->node_name[0] &= 0xF0; 7476 } 7477 7478 /* Set host adapter parameters. */ 7479 ha->flags.disable_risc_code_load = 0; 7480 ha->flags.enable_lip_reset = 0; 7481 ha->flags.enable_lip_full_login = 7482 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0; 7483 ha->flags.enable_target_reset = 7484 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0; 7485 ha->flags.enable_led_scheme = 0; 7486 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0; 7487 7488 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 7489 (BIT_6 | BIT_5 | BIT_4)) >> 4; 7490 7491 memcpy(ha->fw_seriallink_options24, nv->seriallink_options, 7492 sizeof(ha->fw_seriallink_options24)); 7493 7494 /* save HBA serial number */ 7495 ha->serial0 = icb->port_name[5]; 7496 ha->serial1 = icb->port_name[6]; 7497 ha->serial2 = icb->port_name[7]; 7498 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 7499 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 7500 7501 icb->execution_throttle = cpu_to_le16(0xFFFF); 7502 7503 ha->retry_count = le16_to_cpu(nv->login_retry_count); 7504 7505 /* Set minimum login_timeout to 4 seconds. */ 7506 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 7507 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 7508 if (le16_to_cpu(nv->login_timeout) < 4) 7509 nv->login_timeout = cpu_to_le16(4); 7510 ha->login_timeout = le16_to_cpu(nv->login_timeout); 7511 7512 /* Set minimum RATOV to 100 tenths of a second. */ 7513 ha->r_a_tov = 100; 7514 7515 ha->loop_reset_delay = nv->reset_delay; 7516 7517 /* Link Down Timeout = 0: 7518 * 7519 * When Port Down timer expires we will start returning 7520 * I/O's to OS with "DID_NO_CONNECT". 7521 * 7522 * Link Down Timeout != 0: 7523 * 7524 * The driver waits for the link to come up after link down 7525 * before returning I/Os to OS with "DID_NO_CONNECT". 7526 */ 7527 if (le16_to_cpu(nv->link_down_timeout) == 0) { 7528 ha->loop_down_abort_time = 7529 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 7530 } else { 7531 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 7532 ha->loop_down_abort_time = 7533 (LOOP_DOWN_TIME - ha->link_down_timeout); 7534 } 7535 7536 /* Need enough time to try and get the port back. */ 7537 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 7538 if (qlport_down_retry) 7539 ha->port_down_retry_count = qlport_down_retry; 7540 7541 /* Set login_retry_count */ 7542 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 7543 if (ha->port_down_retry_count == 7544 le16_to_cpu(nv->port_down_retry_count) && 7545 ha->port_down_retry_count > 3) 7546 ha->login_retry_count = ha->port_down_retry_count; 7547 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 7548 ha->login_retry_count = ha->port_down_retry_count; 7549 if (ql2xloginretrycount) 7550 ha->login_retry_count = ql2xloginretrycount; 7551 7552 /* N2N: driver will initiate Login instead of FW */ 7553 icb->firmware_options_3 |= cpu_to_le32(BIT_8); 7554 7555 /* Enable ZIO. */ 7556 if (!vha->flags.init_done) { 7557 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 7558 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 7559 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 7560 le16_to_cpu(icb->interrupt_delay_timer) : 2; 7561 } 7562 icb->firmware_options_2 &= cpu_to_le32( 7563 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 7564 if (ha->zio_mode != QLA_ZIO_DISABLED) { 7565 ha->zio_mode = QLA_ZIO_MODE_6; 7566 7567 ql_log(ql_log_info, vha, 0x006f, 7568 "ZIO mode %d enabled; timer delay (%d us).\n", 7569 ha->zio_mode, ha->zio_timer * 100); 7570 7571 icb->firmware_options_2 |= cpu_to_le32( 7572 (uint32_t)ha->zio_mode); 7573 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 7574 } 7575 7576 if (rval) { 7577 ql_log(ql_log_warn, vha, 0x0070, 7578 "NVRAM configuration failed.\n"); 7579 } 7580 return (rval); 7581 } 7582 7583 static void 7584 qla27xx_print_image(struct scsi_qla_host *vha, char *name, 7585 struct qla27xx_image_status *image_status) 7586 { 7587 ql_dbg(ql_dbg_init, vha, 0x018b, 7588 "%s %s: mask=%#02x gen=%#04x ver=%u.%u map=%#01x sum=%#08x sig=%#08x\n", 7589 name, "status", 7590 image_status->image_status_mask, 7591 le16_to_cpu(image_status->generation), 7592 image_status->ver_major, 7593 image_status->ver_minor, 7594 image_status->bitmap, 7595 le32_to_cpu(image_status->checksum), 7596 le32_to_cpu(image_status->signature)); 7597 } 7598 7599 static bool 7600 qla28xx_check_aux_image_status_signature( 7601 struct qla27xx_image_status *image_status) 7602 { 7603 ulong signature = le32_to_cpu(image_status->signature); 7604 7605 return signature != QLA28XX_AUX_IMG_STATUS_SIGN; 7606 } 7607 7608 static bool 7609 qla27xx_check_image_status_signature(struct qla27xx_image_status *image_status) 7610 { 7611 ulong signature = le32_to_cpu(image_status->signature); 7612 7613 return 7614 signature != QLA27XX_IMG_STATUS_SIGN && 7615 signature != QLA28XX_IMG_STATUS_SIGN; 7616 } 7617 7618 static ulong 7619 qla27xx_image_status_checksum(struct qla27xx_image_status *image_status) 7620 { 7621 __le32 *p = (__force __le32 *)image_status; 7622 uint n = sizeof(*image_status) / sizeof(*p); 7623 uint32_t sum = 0; 7624 7625 for ( ; n--; p++) 7626 sum += le32_to_cpup(p); 7627 7628 return sum; 7629 } 7630 7631 static inline uint 7632 qla28xx_component_bitmask(struct qla27xx_image_status *aux, uint bitmask) 7633 { 7634 return aux->bitmap & bitmask ? 7635 QLA27XX_SECONDARY_IMAGE : QLA27XX_PRIMARY_IMAGE; 7636 } 7637 7638 static void 7639 qla28xx_component_status( 7640 struct active_regions *active_regions, struct qla27xx_image_status *aux) 7641 { 7642 active_regions->aux.board_config = 7643 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_BOARD_CONFIG); 7644 7645 active_regions->aux.vpd_nvram = 7646 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_VPD_NVRAM); 7647 7648 active_regions->aux.npiv_config_0_1 = 7649 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_0_1); 7650 7651 active_regions->aux.npiv_config_2_3 = 7652 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_2_3); 7653 } 7654 7655 static int 7656 qla27xx_compare_image_generation( 7657 struct qla27xx_image_status *pri_image_status, 7658 struct qla27xx_image_status *sec_image_status) 7659 { 7660 /* calculate generation delta as uint16 (this accounts for wrap) */ 7661 int16_t delta = 7662 le16_to_cpu(pri_image_status->generation) - 7663 le16_to_cpu(sec_image_status->generation); 7664 7665 ql_dbg(ql_dbg_init, NULL, 0x0180, "generation delta = %d\n", delta); 7666 7667 return delta; 7668 } 7669 7670 void 7671 qla28xx_get_aux_images( 7672 struct scsi_qla_host *vha, struct active_regions *active_regions) 7673 { 7674 struct qla_hw_data *ha = vha->hw; 7675 struct qla27xx_image_status pri_aux_image_status, sec_aux_image_status; 7676 bool valid_pri_image = false, valid_sec_image = false; 7677 bool active_pri_image = false, active_sec_image = false; 7678 7679 if (!ha->flt_region_aux_img_status_pri) { 7680 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary aux image not addressed\n"); 7681 goto check_sec_image; 7682 } 7683 7684 qla24xx_read_flash_data(vha, (uint32_t *)&pri_aux_image_status, 7685 ha->flt_region_aux_img_status_pri, 7686 sizeof(pri_aux_image_status) >> 2); 7687 qla27xx_print_image(vha, "Primary aux image", &pri_aux_image_status); 7688 7689 if (qla28xx_check_aux_image_status_signature(&pri_aux_image_status)) { 7690 ql_dbg(ql_dbg_init, vha, 0x018b, 7691 "Primary aux image signature (%#x) not valid\n", 7692 le32_to_cpu(pri_aux_image_status.signature)); 7693 goto check_sec_image; 7694 } 7695 7696 if (qla27xx_image_status_checksum(&pri_aux_image_status)) { 7697 ql_dbg(ql_dbg_init, vha, 0x018c, 7698 "Primary aux image checksum failed\n"); 7699 goto check_sec_image; 7700 } 7701 7702 valid_pri_image = true; 7703 7704 if (pri_aux_image_status.image_status_mask & 1) { 7705 ql_dbg(ql_dbg_init, vha, 0x018d, 7706 "Primary aux image is active\n"); 7707 active_pri_image = true; 7708 } 7709 7710 check_sec_image: 7711 if (!ha->flt_region_aux_img_status_sec) { 7712 ql_dbg(ql_dbg_init, vha, 0x018a, 7713 "Secondary aux image not addressed\n"); 7714 goto check_valid_image; 7715 } 7716 7717 qla24xx_read_flash_data(vha, (uint32_t *)&sec_aux_image_status, 7718 ha->flt_region_aux_img_status_sec, 7719 sizeof(sec_aux_image_status) >> 2); 7720 qla27xx_print_image(vha, "Secondary aux image", &sec_aux_image_status); 7721 7722 if (qla28xx_check_aux_image_status_signature(&sec_aux_image_status)) { 7723 ql_dbg(ql_dbg_init, vha, 0x018b, 7724 "Secondary aux image signature (%#x) not valid\n", 7725 le32_to_cpu(sec_aux_image_status.signature)); 7726 goto check_valid_image; 7727 } 7728 7729 if (qla27xx_image_status_checksum(&sec_aux_image_status)) { 7730 ql_dbg(ql_dbg_init, vha, 0x018c, 7731 "Secondary aux image checksum failed\n"); 7732 goto check_valid_image; 7733 } 7734 7735 valid_sec_image = true; 7736 7737 if (sec_aux_image_status.image_status_mask & 1) { 7738 ql_dbg(ql_dbg_init, vha, 0x018d, 7739 "Secondary aux image is active\n"); 7740 active_sec_image = true; 7741 } 7742 7743 check_valid_image: 7744 if (valid_pri_image && active_pri_image && 7745 valid_sec_image && active_sec_image) { 7746 if (qla27xx_compare_image_generation(&pri_aux_image_status, 7747 &sec_aux_image_status) >= 0) { 7748 qla28xx_component_status(active_regions, 7749 &pri_aux_image_status); 7750 } else { 7751 qla28xx_component_status(active_regions, 7752 &sec_aux_image_status); 7753 } 7754 } else if (valid_pri_image && active_pri_image) { 7755 qla28xx_component_status(active_regions, &pri_aux_image_status); 7756 } else if (valid_sec_image && active_sec_image) { 7757 qla28xx_component_status(active_regions, &sec_aux_image_status); 7758 } 7759 7760 ql_dbg(ql_dbg_init, vha, 0x018f, 7761 "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u\n", 7762 active_regions->aux.board_config, 7763 active_regions->aux.vpd_nvram, 7764 active_regions->aux.npiv_config_0_1, 7765 active_regions->aux.npiv_config_2_3); 7766 } 7767 7768 void 7769 qla27xx_get_active_image(struct scsi_qla_host *vha, 7770 struct active_regions *active_regions) 7771 { 7772 struct qla_hw_data *ha = vha->hw; 7773 struct qla27xx_image_status pri_image_status, sec_image_status; 7774 bool valid_pri_image = false, valid_sec_image = false; 7775 bool active_pri_image = false, active_sec_image = false; 7776 7777 if (!ha->flt_region_img_status_pri) { 7778 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary image not addressed\n"); 7779 goto check_sec_image; 7780 } 7781 7782 if (qla24xx_read_flash_data(vha, (uint32_t *)&pri_image_status, 7783 ha->flt_region_img_status_pri, sizeof(pri_image_status) >> 2) != 7784 QLA_SUCCESS) { 7785 WARN_ON_ONCE(true); 7786 goto check_sec_image; 7787 } 7788 qla27xx_print_image(vha, "Primary image", &pri_image_status); 7789 7790 if (qla27xx_check_image_status_signature(&pri_image_status)) { 7791 ql_dbg(ql_dbg_init, vha, 0x018b, 7792 "Primary image signature (%#x) not valid\n", 7793 le32_to_cpu(pri_image_status.signature)); 7794 goto check_sec_image; 7795 } 7796 7797 if (qla27xx_image_status_checksum(&pri_image_status)) { 7798 ql_dbg(ql_dbg_init, vha, 0x018c, 7799 "Primary image checksum failed\n"); 7800 goto check_sec_image; 7801 } 7802 7803 valid_pri_image = true; 7804 7805 if (pri_image_status.image_status_mask & 1) { 7806 ql_dbg(ql_dbg_init, vha, 0x018d, 7807 "Primary image is active\n"); 7808 active_pri_image = true; 7809 } 7810 7811 check_sec_image: 7812 if (!ha->flt_region_img_status_sec) { 7813 ql_dbg(ql_dbg_init, vha, 0x018a, "Secondary image not addressed\n"); 7814 goto check_valid_image; 7815 } 7816 7817 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status), 7818 ha->flt_region_img_status_sec, sizeof(sec_image_status) >> 2); 7819 qla27xx_print_image(vha, "Secondary image", &sec_image_status); 7820 7821 if (qla27xx_check_image_status_signature(&sec_image_status)) { 7822 ql_dbg(ql_dbg_init, vha, 0x018b, 7823 "Secondary image signature (%#x) not valid\n", 7824 le32_to_cpu(sec_image_status.signature)); 7825 goto check_valid_image; 7826 } 7827 7828 if (qla27xx_image_status_checksum(&sec_image_status)) { 7829 ql_dbg(ql_dbg_init, vha, 0x018c, 7830 "Secondary image checksum failed\n"); 7831 goto check_valid_image; 7832 } 7833 7834 valid_sec_image = true; 7835 7836 if (sec_image_status.image_status_mask & 1) { 7837 ql_dbg(ql_dbg_init, vha, 0x018d, 7838 "Secondary image is active\n"); 7839 active_sec_image = true; 7840 } 7841 7842 check_valid_image: 7843 if (valid_pri_image && active_pri_image) 7844 active_regions->global = QLA27XX_PRIMARY_IMAGE; 7845 7846 if (valid_sec_image && active_sec_image) { 7847 if (!active_regions->global || 7848 qla27xx_compare_image_generation( 7849 &pri_image_status, &sec_image_status) < 0) { 7850 active_regions->global = QLA27XX_SECONDARY_IMAGE; 7851 } 7852 } 7853 7854 ql_dbg(ql_dbg_init, vha, 0x018f, "active image %s (%u)\n", 7855 active_regions->global == QLA27XX_DEFAULT_IMAGE ? 7856 "default (boot/fw)" : 7857 active_regions->global == QLA27XX_PRIMARY_IMAGE ? 7858 "primary" : 7859 active_regions->global == QLA27XX_SECONDARY_IMAGE ? 7860 "secondary" : "invalid", 7861 active_regions->global); 7862 } 7863 7864 bool qla24xx_risc_firmware_invalid(uint32_t *dword) 7865 { 7866 return 7867 !(dword[4] | dword[5] | dword[6] | dword[7]) || 7868 !(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]); 7869 } 7870 7871 static int 7872 qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, 7873 uint32_t faddr) 7874 { 7875 int rval; 7876 uint templates, segments, fragment; 7877 ulong i; 7878 uint j; 7879 ulong dlen; 7880 uint32_t *dcode; 7881 uint32_t risc_addr, risc_size, risc_attr = 0; 7882 struct qla_hw_data *ha = vha->hw; 7883 struct req_que *req = ha->req_q_map[0]; 7884 struct fwdt *fwdt = ha->fwdt; 7885 7886 ql_dbg(ql_dbg_init, vha, 0x008b, 7887 "FW: Loading firmware from flash (%x).\n", faddr); 7888 7889 dcode = (uint32_t *)req->ring; 7890 qla24xx_read_flash_data(vha, dcode, faddr, 8); 7891 if (qla24xx_risc_firmware_invalid(dcode)) { 7892 ql_log(ql_log_fatal, vha, 0x008c, 7893 "Unable to verify the integrity of flash firmware " 7894 "image.\n"); 7895 ql_log(ql_log_fatal, vha, 0x008d, 7896 "Firmware data: %08x %08x %08x %08x.\n", 7897 dcode[0], dcode[1], dcode[2], dcode[3]); 7898 7899 return QLA_FUNCTION_FAILED; 7900 } 7901 7902 dcode = (uint32_t *)req->ring; 7903 *srisc_addr = 0; 7904 segments = FA_RISC_CODE_SEGMENTS; 7905 for (j = 0; j < segments; j++) { 7906 ql_dbg(ql_dbg_init, vha, 0x008d, 7907 "-> Loading segment %u...\n", j); 7908 qla24xx_read_flash_data(vha, dcode, faddr, 10); 7909 risc_addr = be32_to_cpu((__force __be32)dcode[2]); 7910 risc_size = be32_to_cpu((__force __be32)dcode[3]); 7911 if (!*srisc_addr) { 7912 *srisc_addr = risc_addr; 7913 risc_attr = be32_to_cpu((__force __be32)dcode[9]); 7914 } 7915 7916 dlen = ha->fw_transfer_size >> 2; 7917 for (fragment = 0; risc_size; fragment++) { 7918 if (dlen > risc_size) 7919 dlen = risc_size; 7920 7921 ql_dbg(ql_dbg_init, vha, 0x008e, 7922 "-> Loading fragment %u: %#x <- %#x (%#lx dwords)...\n", 7923 fragment, risc_addr, faddr, dlen); 7924 qla24xx_read_flash_data(vha, dcode, faddr, dlen); 7925 for (i = 0; i < dlen; i++) 7926 dcode[i] = swab32(dcode[i]); 7927 7928 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen); 7929 if (rval) { 7930 ql_log(ql_log_fatal, vha, 0x008f, 7931 "-> Failed load firmware fragment %u.\n", 7932 fragment); 7933 return QLA_FUNCTION_FAILED; 7934 } 7935 7936 faddr += dlen; 7937 risc_addr += dlen; 7938 risc_size -= dlen; 7939 } 7940 } 7941 7942 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 7943 return QLA_SUCCESS; 7944 7945 templates = (risc_attr & BIT_9) ? 2 : 1; 7946 ql_dbg(ql_dbg_init, vha, 0x0160, "-> templates = %u\n", templates); 7947 for (j = 0; j < templates; j++, fwdt++) { 7948 vfree(fwdt->template); 7949 fwdt->template = NULL; 7950 fwdt->length = 0; 7951 7952 dcode = (uint32_t *)req->ring; 7953 qla24xx_read_flash_data(vha, dcode, faddr, 7); 7954 risc_size = be32_to_cpu((__force __be32)dcode[2]); 7955 ql_dbg(ql_dbg_init, vha, 0x0161, 7956 "-> fwdt%u template array at %#x (%#x dwords)\n", 7957 j, faddr, risc_size); 7958 if (!risc_size || !~risc_size) { 7959 ql_dbg(ql_dbg_init, vha, 0x0162, 7960 "-> fwdt%u failed to read array\n", j); 7961 goto failed; 7962 } 7963 7964 /* skip header and ignore checksum */ 7965 faddr += 7; 7966 risc_size -= 8; 7967 7968 ql_dbg(ql_dbg_init, vha, 0x0163, 7969 "-> fwdt%u template allocate template %#x words...\n", 7970 j, risc_size); 7971 fwdt->template = vmalloc(risc_size * sizeof(*dcode)); 7972 if (!fwdt->template) { 7973 ql_log(ql_log_warn, vha, 0x0164, 7974 "-> fwdt%u failed allocate template.\n", j); 7975 goto failed; 7976 } 7977 7978 dcode = fwdt->template; 7979 qla24xx_read_flash_data(vha, dcode, faddr, risc_size); 7980 7981 if (!qla27xx_fwdt_template_valid(dcode)) { 7982 ql_log(ql_log_warn, vha, 0x0165, 7983 "-> fwdt%u failed template validate\n", j); 7984 goto failed; 7985 } 7986 7987 dlen = qla27xx_fwdt_template_size(dcode); 7988 ql_dbg(ql_dbg_init, vha, 0x0166, 7989 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 7990 j, dlen, dlen / sizeof(*dcode)); 7991 if (dlen > risc_size * sizeof(*dcode)) { 7992 ql_log(ql_log_warn, vha, 0x0167, 7993 "-> fwdt%u template exceeds array (%-lu bytes)\n", 7994 j, dlen - risc_size * sizeof(*dcode)); 7995 goto failed; 7996 } 7997 7998 fwdt->length = dlen; 7999 ql_dbg(ql_dbg_init, vha, 0x0168, 8000 "-> fwdt%u loaded template ok\n", j); 8001 8002 faddr += risc_size + 1; 8003 } 8004 8005 return QLA_SUCCESS; 8006 8007 failed: 8008 vfree(fwdt->template); 8009 fwdt->template = NULL; 8010 fwdt->length = 0; 8011 8012 return QLA_SUCCESS; 8013 } 8014 8015 #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/" 8016 8017 int 8018 qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8019 { 8020 int rval; 8021 int i, fragment; 8022 uint16_t *wcode; 8023 __be16 *fwcode; 8024 uint32_t risc_addr, risc_size, fwclen, wlen, *seg; 8025 struct fw_blob *blob; 8026 struct qla_hw_data *ha = vha->hw; 8027 struct req_que *req = ha->req_q_map[0]; 8028 8029 /* Load firmware blob. */ 8030 blob = qla2x00_request_firmware(vha); 8031 if (!blob) { 8032 ql_log(ql_log_info, vha, 0x0083, 8033 "Firmware image unavailable.\n"); 8034 ql_log(ql_log_info, vha, 0x0084, 8035 "Firmware images can be retrieved from: "QLA_FW_URL ".\n"); 8036 return QLA_FUNCTION_FAILED; 8037 } 8038 8039 rval = QLA_SUCCESS; 8040 8041 wcode = (uint16_t *)req->ring; 8042 *srisc_addr = 0; 8043 fwcode = (__force __be16 *)blob->fw->data; 8044 fwclen = 0; 8045 8046 /* Validate firmware image by checking version. */ 8047 if (blob->fw->size < 8 * sizeof(uint16_t)) { 8048 ql_log(ql_log_fatal, vha, 0x0085, 8049 "Unable to verify integrity of firmware image (%zd).\n", 8050 blob->fw->size); 8051 goto fail_fw_integrity; 8052 } 8053 for (i = 0; i < 4; i++) 8054 wcode[i] = be16_to_cpu(fwcode[i + 4]); 8055 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff && 8056 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 && 8057 wcode[2] == 0 && wcode[3] == 0)) { 8058 ql_log(ql_log_fatal, vha, 0x0086, 8059 "Unable to verify integrity of firmware image.\n"); 8060 ql_log(ql_log_fatal, vha, 0x0087, 8061 "Firmware data: %04x %04x %04x %04x.\n", 8062 wcode[0], wcode[1], wcode[2], wcode[3]); 8063 goto fail_fw_integrity; 8064 } 8065 8066 seg = blob->segs; 8067 while (*seg && rval == QLA_SUCCESS) { 8068 risc_addr = *seg; 8069 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr; 8070 risc_size = be16_to_cpu(fwcode[3]); 8071 8072 /* Validate firmware image size. */ 8073 fwclen += risc_size * sizeof(uint16_t); 8074 if (blob->fw->size < fwclen) { 8075 ql_log(ql_log_fatal, vha, 0x0088, 8076 "Unable to verify integrity of firmware image " 8077 "(%zd).\n", blob->fw->size); 8078 goto fail_fw_integrity; 8079 } 8080 8081 fragment = 0; 8082 while (risc_size > 0 && rval == QLA_SUCCESS) { 8083 wlen = (uint16_t)(ha->fw_transfer_size >> 1); 8084 if (wlen > risc_size) 8085 wlen = risc_size; 8086 ql_dbg(ql_dbg_init, vha, 0x0089, 8087 "Loading risc segment@ risc addr %x number of " 8088 "words 0x%x.\n", risc_addr, wlen); 8089 8090 for (i = 0; i < wlen; i++) 8091 wcode[i] = swab16((__force u32)fwcode[i]); 8092 8093 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 8094 wlen); 8095 if (rval) { 8096 ql_log(ql_log_fatal, vha, 0x008a, 8097 "Failed to load segment %d of firmware.\n", 8098 fragment); 8099 break; 8100 } 8101 8102 fwcode += wlen; 8103 risc_addr += wlen; 8104 risc_size -= wlen; 8105 fragment++; 8106 } 8107 8108 /* Next segment. */ 8109 seg++; 8110 } 8111 return rval; 8112 8113 fail_fw_integrity: 8114 return QLA_FUNCTION_FAILED; 8115 } 8116 8117 static int 8118 qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8119 { 8120 int rval; 8121 uint templates, segments, fragment; 8122 uint32_t *dcode; 8123 ulong dlen; 8124 uint32_t risc_addr, risc_size, risc_attr = 0; 8125 ulong i; 8126 uint j; 8127 struct fw_blob *blob; 8128 __be32 *fwcode; 8129 struct qla_hw_data *ha = vha->hw; 8130 struct req_que *req = ha->req_q_map[0]; 8131 struct fwdt *fwdt = ha->fwdt; 8132 8133 ql_dbg(ql_dbg_init, vha, 0x0090, 8134 "-> FW: Loading via request-firmware.\n"); 8135 8136 blob = qla2x00_request_firmware(vha); 8137 if (!blob) { 8138 ql_log(ql_log_warn, vha, 0x0092, 8139 "-> Firmware file not found.\n"); 8140 8141 return QLA_FUNCTION_FAILED; 8142 } 8143 8144 fwcode = (__force __be32 *)blob->fw->data; 8145 dcode = (__force uint32_t *)fwcode; 8146 if (qla24xx_risc_firmware_invalid(dcode)) { 8147 ql_log(ql_log_fatal, vha, 0x0093, 8148 "Unable to verify integrity of firmware image (%zd).\n", 8149 blob->fw->size); 8150 ql_log(ql_log_fatal, vha, 0x0095, 8151 "Firmware data: %08x %08x %08x %08x.\n", 8152 dcode[0], dcode[1], dcode[2], dcode[3]); 8153 return QLA_FUNCTION_FAILED; 8154 } 8155 8156 dcode = (uint32_t *)req->ring; 8157 *srisc_addr = 0; 8158 segments = FA_RISC_CODE_SEGMENTS; 8159 for (j = 0; j < segments; j++) { 8160 ql_dbg(ql_dbg_init, vha, 0x0096, 8161 "-> Loading segment %u...\n", j); 8162 risc_addr = be32_to_cpu(fwcode[2]); 8163 risc_size = be32_to_cpu(fwcode[3]); 8164 8165 if (!*srisc_addr) { 8166 *srisc_addr = risc_addr; 8167 risc_attr = be32_to_cpu(fwcode[9]); 8168 } 8169 8170 dlen = ha->fw_transfer_size >> 2; 8171 for (fragment = 0; risc_size; fragment++) { 8172 if (dlen > risc_size) 8173 dlen = risc_size; 8174 8175 ql_dbg(ql_dbg_init, vha, 0x0097, 8176 "-> Loading fragment %u: %#x <- %#x (%#lx words)...\n", 8177 fragment, risc_addr, 8178 (uint32_t)(fwcode - (typeof(fwcode))blob->fw->data), 8179 dlen); 8180 8181 for (i = 0; i < dlen; i++) 8182 dcode[i] = swab32((__force u32)fwcode[i]); 8183 8184 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen); 8185 if (rval) { 8186 ql_log(ql_log_fatal, vha, 0x0098, 8187 "-> Failed load firmware fragment %u.\n", 8188 fragment); 8189 return QLA_FUNCTION_FAILED; 8190 } 8191 8192 fwcode += dlen; 8193 risc_addr += dlen; 8194 risc_size -= dlen; 8195 } 8196 } 8197 8198 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 8199 return QLA_SUCCESS; 8200 8201 templates = (risc_attr & BIT_9) ? 2 : 1; 8202 ql_dbg(ql_dbg_init, vha, 0x0170, "-> templates = %u\n", templates); 8203 for (j = 0; j < templates; j++, fwdt++) { 8204 vfree(fwdt->template); 8205 fwdt->template = NULL; 8206 fwdt->length = 0; 8207 8208 risc_size = be32_to_cpu(fwcode[2]); 8209 ql_dbg(ql_dbg_init, vha, 0x0171, 8210 "-> fwdt%u template array at %#x (%#x dwords)\n", 8211 j, (uint32_t)((void *)fwcode - (void *)blob->fw->data), 8212 risc_size); 8213 if (!risc_size || !~risc_size) { 8214 ql_dbg(ql_dbg_init, vha, 0x0172, 8215 "-> fwdt%u failed to read array\n", j); 8216 goto failed; 8217 } 8218 8219 /* skip header and ignore checksum */ 8220 fwcode += 7; 8221 risc_size -= 8; 8222 8223 ql_dbg(ql_dbg_init, vha, 0x0173, 8224 "-> fwdt%u template allocate template %#x words...\n", 8225 j, risc_size); 8226 fwdt->template = vmalloc(risc_size * sizeof(*dcode)); 8227 if (!fwdt->template) { 8228 ql_log(ql_log_warn, vha, 0x0174, 8229 "-> fwdt%u failed allocate template.\n", j); 8230 goto failed; 8231 } 8232 8233 dcode = fwdt->template; 8234 for (i = 0; i < risc_size; i++) 8235 dcode[i] = (__force u32)fwcode[i]; 8236 8237 if (!qla27xx_fwdt_template_valid(dcode)) { 8238 ql_log(ql_log_warn, vha, 0x0175, 8239 "-> fwdt%u failed template validate\n", j); 8240 goto failed; 8241 } 8242 8243 dlen = qla27xx_fwdt_template_size(dcode); 8244 ql_dbg(ql_dbg_init, vha, 0x0176, 8245 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 8246 j, dlen, dlen / sizeof(*dcode)); 8247 if (dlen > risc_size * sizeof(*dcode)) { 8248 ql_log(ql_log_warn, vha, 0x0177, 8249 "-> fwdt%u template exceeds array (%-lu bytes)\n", 8250 j, dlen - risc_size * sizeof(*dcode)); 8251 goto failed; 8252 } 8253 8254 fwdt->length = dlen; 8255 ql_dbg(ql_dbg_init, vha, 0x0178, 8256 "-> fwdt%u loaded template ok\n", j); 8257 8258 fwcode += risc_size + 1; 8259 } 8260 8261 return QLA_SUCCESS; 8262 8263 failed: 8264 vfree(fwdt->template); 8265 fwdt->template = NULL; 8266 fwdt->length = 0; 8267 8268 return QLA_SUCCESS; 8269 } 8270 8271 int 8272 qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8273 { 8274 int rval; 8275 8276 if (ql2xfwloadbin == 1) 8277 return qla81xx_load_risc(vha, srisc_addr); 8278 8279 /* 8280 * FW Load priority: 8281 * 1) Firmware via request-firmware interface (.bin file). 8282 * 2) Firmware residing in flash. 8283 */ 8284 rval = qla24xx_load_risc_blob(vha, srisc_addr); 8285 if (rval == QLA_SUCCESS) 8286 return rval; 8287 8288 return qla24xx_load_risc_flash(vha, srisc_addr, 8289 vha->hw->flt_region_fw); 8290 } 8291 8292 int 8293 qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8294 { 8295 int rval; 8296 struct qla_hw_data *ha = vha->hw; 8297 struct active_regions active_regions = { }; 8298 8299 if (ql2xfwloadbin == 2) 8300 goto try_blob_fw; 8301 8302 /* FW Load priority: 8303 * 1) Firmware residing in flash. 8304 * 2) Firmware via request-firmware interface (.bin file). 8305 * 3) Golden-Firmware residing in flash -- (limited operation). 8306 */ 8307 8308 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 8309 goto try_primary_fw; 8310 8311 qla27xx_get_active_image(vha, &active_regions); 8312 8313 if (active_regions.global != QLA27XX_SECONDARY_IMAGE) 8314 goto try_primary_fw; 8315 8316 ql_dbg(ql_dbg_init, vha, 0x008b, 8317 "Loading secondary firmware image.\n"); 8318 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec); 8319 if (!rval) 8320 return rval; 8321 8322 try_primary_fw: 8323 ql_dbg(ql_dbg_init, vha, 0x008b, 8324 "Loading primary firmware image.\n"); 8325 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw); 8326 if (!rval) 8327 return rval; 8328 8329 try_blob_fw: 8330 rval = qla24xx_load_risc_blob(vha, srisc_addr); 8331 if (!rval || !ha->flt_region_gold_fw) 8332 return rval; 8333 8334 ql_log(ql_log_info, vha, 0x0099, 8335 "Attempting to fallback to golden firmware.\n"); 8336 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw); 8337 if (rval) 8338 return rval; 8339 8340 ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n"); 8341 ha->flags.running_gold_fw = 1; 8342 return rval; 8343 } 8344 8345 void 8346 qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) 8347 { 8348 int ret, retries; 8349 struct qla_hw_data *ha = vha->hw; 8350 8351 if (ha->flags.pci_channel_io_perm_failure) 8352 return; 8353 if (!IS_FWI2_CAPABLE(ha)) 8354 return; 8355 if (!ha->fw_major_version) 8356 return; 8357 if (!ha->flags.fw_started) 8358 return; 8359 8360 ret = qla2x00_stop_firmware(vha); 8361 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT && 8362 ret != QLA_INVALID_COMMAND && retries ; retries--) { 8363 ha->isp_ops->reset_chip(vha); 8364 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS) 8365 continue; 8366 if (qla2x00_setup_chip(vha) != QLA_SUCCESS) 8367 continue; 8368 ql_log(ql_log_info, vha, 0x8015, 8369 "Attempting retry of stop-firmware command.\n"); 8370 ret = qla2x00_stop_firmware(vha); 8371 } 8372 8373 QLA_FW_STOPPED(ha); 8374 ha->flags.fw_init_done = 0; 8375 } 8376 8377 int 8378 qla24xx_configure_vhba(scsi_qla_host_t *vha) 8379 { 8380 int rval = QLA_SUCCESS; 8381 int rval2; 8382 uint16_t mb[MAILBOX_REGISTER_COUNT]; 8383 struct qla_hw_data *ha = vha->hw; 8384 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 8385 8386 if (!vha->vp_idx) 8387 return -EINVAL; 8388 8389 rval = qla2x00_fw_ready(base_vha); 8390 8391 if (rval == QLA_SUCCESS) { 8392 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 8393 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 8394 } 8395 8396 vha->flags.management_server_logged_in = 0; 8397 8398 /* Login to SNS first */ 8399 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, 8400 BIT_1); 8401 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 8402 if (rval2 == QLA_MEMORY_ALLOC_FAILED) 8403 ql_dbg(ql_dbg_init, vha, 0x0120, 8404 "Failed SNS login: loop_id=%x, rval2=%d\n", 8405 NPH_SNS, rval2); 8406 else 8407 ql_dbg(ql_dbg_init, vha, 0x0103, 8408 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x " 8409 "mb[2]=%x mb[6]=%x mb[7]=%x.\n", 8410 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]); 8411 return (QLA_FUNCTION_FAILED); 8412 } 8413 8414 atomic_set(&vha->loop_down_timer, 0); 8415 atomic_set(&vha->loop_state, LOOP_UP); 8416 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 8417 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 8418 rval = qla2x00_loop_resync(base_vha); 8419 8420 return rval; 8421 } 8422 8423 /* 84XX Support **************************************************************/ 8424 8425 static LIST_HEAD(qla_cs84xx_list); 8426 static DEFINE_MUTEX(qla_cs84xx_mutex); 8427 8428 static struct qla_chip_state_84xx * 8429 qla84xx_get_chip(struct scsi_qla_host *vha) 8430 { 8431 struct qla_chip_state_84xx *cs84xx; 8432 struct qla_hw_data *ha = vha->hw; 8433 8434 mutex_lock(&qla_cs84xx_mutex); 8435 8436 /* Find any shared 84xx chip. */ 8437 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) { 8438 if (cs84xx->bus == ha->pdev->bus) { 8439 kref_get(&cs84xx->kref); 8440 goto done; 8441 } 8442 } 8443 8444 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL); 8445 if (!cs84xx) 8446 goto done; 8447 8448 kref_init(&cs84xx->kref); 8449 spin_lock_init(&cs84xx->access_lock); 8450 mutex_init(&cs84xx->fw_update_mutex); 8451 cs84xx->bus = ha->pdev->bus; 8452 8453 list_add_tail(&cs84xx->list, &qla_cs84xx_list); 8454 done: 8455 mutex_unlock(&qla_cs84xx_mutex); 8456 return cs84xx; 8457 } 8458 8459 static void 8460 __qla84xx_chip_release(struct kref *kref) 8461 { 8462 struct qla_chip_state_84xx *cs84xx = 8463 container_of(kref, struct qla_chip_state_84xx, kref); 8464 8465 mutex_lock(&qla_cs84xx_mutex); 8466 list_del(&cs84xx->list); 8467 mutex_unlock(&qla_cs84xx_mutex); 8468 kfree(cs84xx); 8469 } 8470 8471 void 8472 qla84xx_put_chip(struct scsi_qla_host *vha) 8473 { 8474 struct qla_hw_data *ha = vha->hw; 8475 8476 if (ha->cs84xx) 8477 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release); 8478 } 8479 8480 static int 8481 qla84xx_init_chip(scsi_qla_host_t *vha) 8482 { 8483 int rval; 8484 uint16_t status[2]; 8485 struct qla_hw_data *ha = vha->hw; 8486 8487 mutex_lock(&ha->cs84xx->fw_update_mutex); 8488 8489 rval = qla84xx_verify_chip(vha, status); 8490 8491 mutex_unlock(&ha->cs84xx->fw_update_mutex); 8492 8493 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED : 8494 QLA_SUCCESS; 8495 } 8496 8497 /* 81XX Support **************************************************************/ 8498 8499 int 8500 qla81xx_nvram_config(scsi_qla_host_t *vha) 8501 { 8502 int rval; 8503 struct init_cb_81xx *icb; 8504 struct nvram_81xx *nv; 8505 __le32 *dptr; 8506 uint8_t *dptr1, *dptr2; 8507 uint32_t chksum; 8508 uint16_t cnt; 8509 struct qla_hw_data *ha = vha->hw; 8510 uint32_t faddr; 8511 struct active_regions active_regions = { }; 8512 8513 rval = QLA_SUCCESS; 8514 icb = (struct init_cb_81xx *)ha->init_cb; 8515 nv = ha->nvram; 8516 8517 /* Determine NVRAM starting address. */ 8518 ha->nvram_size = sizeof(*nv); 8519 ha->vpd_size = FA_NVRAM_VPD_SIZE; 8520 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 8521 ha->vpd_size = FA_VPD_SIZE_82XX; 8522 8523 if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) 8524 qla28xx_get_aux_images(vha, &active_regions); 8525 8526 /* Get VPD data into cache */ 8527 ha->vpd = ha->nvram + VPD_OFFSET; 8528 8529 faddr = ha->flt_region_vpd; 8530 if (IS_QLA28XX(ha)) { 8531 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE) 8532 faddr = ha->flt_region_vpd_sec; 8533 ql_dbg(ql_dbg_init, vha, 0x0110, 8534 "Loading %s nvram image.\n", 8535 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ? 8536 "primary" : "secondary"); 8537 } 8538 ha->isp_ops->read_optrom(vha, ha->vpd, faddr << 2, ha->vpd_size); 8539 8540 /* Get NVRAM data into cache and calculate checksum. */ 8541 faddr = ha->flt_region_nvram; 8542 if (IS_QLA28XX(ha)) { 8543 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE) 8544 faddr = ha->flt_region_nvram_sec; 8545 } 8546 ql_dbg(ql_dbg_init, vha, 0x0110, 8547 "Loading %s nvram image.\n", 8548 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ? 8549 "primary" : "secondary"); 8550 ha->isp_ops->read_optrom(vha, ha->nvram, faddr << 2, ha->nvram_size); 8551 8552 dptr = (__force __le32 *)nv; 8553 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 8554 chksum += le32_to_cpu(*dptr); 8555 8556 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111, 8557 "Contents of NVRAM:\n"); 8558 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112, 8559 nv, ha->nvram_size); 8560 8561 /* Bad NVRAM data, set defaults parameters. */ 8562 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 8563 le16_to_cpu(nv->nvram_version) < ICB_VERSION) { 8564 /* Reset NVRAM data. */ 8565 ql_log(ql_log_info, vha, 0x0073, 8566 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n", 8567 chksum, nv->id, le16_to_cpu(nv->nvram_version)); 8568 ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, sizeof(*nv)); 8569 ql_log(ql_log_info, vha, 0x0074, 8570 "Falling back to functioning (yet invalid -- WWPN) " 8571 "defaults.\n"); 8572 8573 /* 8574 * Set default initialization control block. 8575 */ 8576 memset(nv, 0, ha->nvram_size); 8577 nv->nvram_version = cpu_to_le16(ICB_VERSION); 8578 nv->version = cpu_to_le16(ICB_VERSION); 8579 nv->frame_payload_size = cpu_to_le16(2048); 8580 nv->execution_throttle = cpu_to_le16(0xFFFF); 8581 nv->exchange_count = cpu_to_le16(0); 8582 nv->port_name[0] = 0x21; 8583 nv->port_name[1] = 0x00 + ha->port_no + 1; 8584 nv->port_name[2] = 0x00; 8585 nv->port_name[3] = 0xe0; 8586 nv->port_name[4] = 0x8b; 8587 nv->port_name[5] = 0x1c; 8588 nv->port_name[6] = 0x55; 8589 nv->port_name[7] = 0x86; 8590 nv->node_name[0] = 0x20; 8591 nv->node_name[1] = 0x00; 8592 nv->node_name[2] = 0x00; 8593 nv->node_name[3] = 0xe0; 8594 nv->node_name[4] = 0x8b; 8595 nv->node_name[5] = 0x1c; 8596 nv->node_name[6] = 0x55; 8597 nv->node_name[7] = 0x86; 8598 nv->login_retry_count = cpu_to_le16(8); 8599 nv->interrupt_delay_timer = cpu_to_le16(0); 8600 nv->login_timeout = cpu_to_le16(0); 8601 nv->firmware_options_1 = 8602 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 8603 nv->firmware_options_2 = cpu_to_le32(2 << 4); 8604 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 8605 nv->firmware_options_3 = cpu_to_le32(2 << 13); 8606 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 8607 nv->efi_parameters = cpu_to_le32(0); 8608 nv->reset_delay = 5; 8609 nv->max_luns_per_target = cpu_to_le16(128); 8610 nv->port_down_retry_count = cpu_to_le16(30); 8611 nv->link_down_timeout = cpu_to_le16(180); 8612 nv->enode_mac[0] = 0x00; 8613 nv->enode_mac[1] = 0xC0; 8614 nv->enode_mac[2] = 0xDD; 8615 nv->enode_mac[3] = 0x04; 8616 nv->enode_mac[4] = 0x05; 8617 nv->enode_mac[5] = 0x06 + ha->port_no + 1; 8618 8619 rval = 1; 8620 } 8621 8622 if (IS_T10_PI_CAPABLE(ha)) 8623 nv->frame_payload_size &= cpu_to_le16(~7); 8624 8625 qlt_81xx_config_nvram_stage1(vha, nv); 8626 8627 /* Reset Initialization control block */ 8628 memset(icb, 0, ha->init_cb_size); 8629 8630 /* Copy 1st segment. */ 8631 dptr1 = (uint8_t *)icb; 8632 dptr2 = (uint8_t *)&nv->version; 8633 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 8634 while (cnt--) 8635 *dptr1++ = *dptr2++; 8636 8637 icb->login_retry_count = nv->login_retry_count; 8638 8639 /* Copy 2nd segment. */ 8640 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 8641 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 8642 cnt = (uint8_t *)&icb->reserved_5 - 8643 (uint8_t *)&icb->interrupt_delay_timer; 8644 while (cnt--) 8645 *dptr1++ = *dptr2++; 8646 8647 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac)); 8648 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */ 8649 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) { 8650 icb->enode_mac[0] = 0x00; 8651 icb->enode_mac[1] = 0xC0; 8652 icb->enode_mac[2] = 0xDD; 8653 icb->enode_mac[3] = 0x04; 8654 icb->enode_mac[4] = 0x05; 8655 icb->enode_mac[5] = 0x06 + ha->port_no + 1; 8656 } 8657 8658 /* Use extended-initialization control block. */ 8659 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb)); 8660 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 8661 /* 8662 * Setup driver NVRAM options. 8663 */ 8664 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 8665 "QLE8XXX"); 8666 8667 qlt_81xx_config_nvram_stage2(vha, icb); 8668 8669 /* Use alternate WWN? */ 8670 if (nv->host_p & cpu_to_le32(BIT_15)) { 8671 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 8672 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 8673 } 8674 8675 /* Prepare nodename */ 8676 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 8677 /* 8678 * Firmware will apply the following mask if the nodename was 8679 * not provided. 8680 */ 8681 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 8682 icb->node_name[0] &= 0xF0; 8683 } 8684 8685 if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) { 8686 if ((nv->enhanced_features & BIT_7) == 0) 8687 ha->flags.scm_supported_a = 1; 8688 } 8689 8690 /* Set host adapter parameters. */ 8691 ha->flags.disable_risc_code_load = 0; 8692 ha->flags.enable_lip_reset = 0; 8693 ha->flags.enable_lip_full_login = 8694 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0; 8695 ha->flags.enable_target_reset = 8696 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0; 8697 ha->flags.enable_led_scheme = 0; 8698 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0; 8699 8700 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 8701 (BIT_6 | BIT_5 | BIT_4)) >> 4; 8702 8703 /* save HBA serial number */ 8704 ha->serial0 = icb->port_name[5]; 8705 ha->serial1 = icb->port_name[6]; 8706 ha->serial2 = icb->port_name[7]; 8707 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 8708 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 8709 8710 icb->execution_throttle = cpu_to_le16(0xFFFF); 8711 8712 ha->retry_count = le16_to_cpu(nv->login_retry_count); 8713 8714 /* Set minimum login_timeout to 4 seconds. */ 8715 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 8716 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 8717 if (le16_to_cpu(nv->login_timeout) < 4) 8718 nv->login_timeout = cpu_to_le16(4); 8719 ha->login_timeout = le16_to_cpu(nv->login_timeout); 8720 8721 /* Set minimum RATOV to 100 tenths of a second. */ 8722 ha->r_a_tov = 100; 8723 8724 ha->loop_reset_delay = nv->reset_delay; 8725 8726 /* Link Down Timeout = 0: 8727 * 8728 * When Port Down timer expires we will start returning 8729 * I/O's to OS with "DID_NO_CONNECT". 8730 * 8731 * Link Down Timeout != 0: 8732 * 8733 * The driver waits for the link to come up after link down 8734 * before returning I/Os to OS with "DID_NO_CONNECT". 8735 */ 8736 if (le16_to_cpu(nv->link_down_timeout) == 0) { 8737 ha->loop_down_abort_time = 8738 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 8739 } else { 8740 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 8741 ha->loop_down_abort_time = 8742 (LOOP_DOWN_TIME - ha->link_down_timeout); 8743 } 8744 8745 /* Need enough time to try and get the port back. */ 8746 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 8747 if (qlport_down_retry) 8748 ha->port_down_retry_count = qlport_down_retry; 8749 8750 /* Set login_retry_count */ 8751 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 8752 if (ha->port_down_retry_count == 8753 le16_to_cpu(nv->port_down_retry_count) && 8754 ha->port_down_retry_count > 3) 8755 ha->login_retry_count = ha->port_down_retry_count; 8756 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 8757 ha->login_retry_count = ha->port_down_retry_count; 8758 if (ql2xloginretrycount) 8759 ha->login_retry_count = ql2xloginretrycount; 8760 8761 /* if not running MSI-X we need handshaking on interrupts */ 8762 if (!vha->hw->flags.msix_enabled && 8763 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) 8764 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 8765 8766 /* Enable ZIO. */ 8767 if (!vha->flags.init_done) { 8768 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 8769 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 8770 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 8771 le16_to_cpu(icb->interrupt_delay_timer) : 2; 8772 } 8773 icb->firmware_options_2 &= cpu_to_le32( 8774 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 8775 vha->flags.process_response_queue = 0; 8776 if (ha->zio_mode != QLA_ZIO_DISABLED) { 8777 ha->zio_mode = QLA_ZIO_MODE_6; 8778 8779 ql_log(ql_log_info, vha, 0x0075, 8780 "ZIO mode %d enabled; timer delay (%d us).\n", 8781 ha->zio_mode, 8782 ha->zio_timer * 100); 8783 8784 icb->firmware_options_2 |= cpu_to_le32( 8785 (uint32_t)ha->zio_mode); 8786 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 8787 vha->flags.process_response_queue = 1; 8788 } 8789 8790 /* enable RIDA Format2 */ 8791 icb->firmware_options_3 |= cpu_to_le32(BIT_0); 8792 8793 /* N2N: driver will initiate Login instead of FW */ 8794 icb->firmware_options_3 |= cpu_to_le32(BIT_8); 8795 8796 /* Determine NVMe/FCP priority for target ports */ 8797 ha->fc4_type_priority = qla2xxx_get_fc4_priority(vha); 8798 8799 if (rval) { 8800 ql_log(ql_log_warn, vha, 0x0076, 8801 "NVRAM configuration failed.\n"); 8802 } 8803 return (rval); 8804 } 8805 8806 int 8807 qla82xx_restart_isp(scsi_qla_host_t *vha) 8808 { 8809 int status, rval; 8810 struct qla_hw_data *ha = vha->hw; 8811 struct scsi_qla_host *vp; 8812 unsigned long flags; 8813 8814 status = qla2x00_init_rings(vha); 8815 if (!status) { 8816 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 8817 ha->flags.chip_reset_done = 1; 8818 8819 status = qla2x00_fw_ready(vha); 8820 if (!status) { 8821 /* Issue a marker after FW becomes ready. */ 8822 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 8823 vha->flags.online = 1; 8824 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 8825 } 8826 8827 /* if no cable then assume it's good */ 8828 if ((vha->device_flags & DFLG_NO_CABLE)) 8829 status = 0; 8830 } 8831 8832 if (!status) { 8833 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 8834 8835 if (!atomic_read(&vha->loop_down_timer)) { 8836 /* 8837 * Issue marker command only when we are going 8838 * to start the I/O . 8839 */ 8840 vha->marker_needed = 1; 8841 } 8842 8843 ha->isp_ops->enable_intrs(ha); 8844 8845 ha->isp_abort_cnt = 0; 8846 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 8847 8848 /* Update the firmware version */ 8849 status = qla82xx_check_md_needed(vha); 8850 8851 if (ha->fce) { 8852 ha->flags.fce_enabled = 1; 8853 memset(ha->fce, 0, 8854 fce_calc_size(ha->fce_bufs)); 8855 rval = qla2x00_enable_fce_trace(vha, 8856 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 8857 &ha->fce_bufs); 8858 if (rval) { 8859 ql_log(ql_log_warn, vha, 0x8001, 8860 "Unable to reinitialize FCE (%d).\n", 8861 rval); 8862 ha->flags.fce_enabled = 0; 8863 } 8864 } 8865 8866 if (ha->eft) { 8867 memset(ha->eft, 0, EFT_SIZE); 8868 rval = qla2x00_enable_eft_trace(vha, 8869 ha->eft_dma, EFT_NUM_BUFFERS); 8870 if (rval) { 8871 ql_log(ql_log_warn, vha, 0x8010, 8872 "Unable to reinitialize EFT (%d).\n", 8873 rval); 8874 } 8875 } 8876 } 8877 8878 if (!status) { 8879 ql_dbg(ql_dbg_taskm, vha, 0x8011, 8880 "qla82xx_restart_isp succeeded.\n"); 8881 8882 spin_lock_irqsave(&ha->vport_slock, flags); 8883 list_for_each_entry(vp, &ha->vp_list, list) { 8884 if (vp->vp_idx) { 8885 atomic_inc(&vp->vref_count); 8886 spin_unlock_irqrestore(&ha->vport_slock, flags); 8887 8888 qla2x00_vp_abort_isp(vp); 8889 8890 spin_lock_irqsave(&ha->vport_slock, flags); 8891 atomic_dec(&vp->vref_count); 8892 } 8893 } 8894 spin_unlock_irqrestore(&ha->vport_slock, flags); 8895 8896 } else { 8897 ql_log(ql_log_warn, vha, 0x8016, 8898 "qla82xx_restart_isp **** FAILED ****.\n"); 8899 } 8900 8901 return status; 8902 } 8903 8904 /* 8905 * qla24xx_get_fcp_prio 8906 * Gets the fcp cmd priority value for the logged in port. 8907 * Looks for a match of the port descriptors within 8908 * each of the fcp prio config entries. If a match is found, 8909 * the tag (priority) value is returned. 8910 * 8911 * Input: 8912 * vha = scsi host structure pointer. 8913 * fcport = port structure pointer. 8914 * 8915 * Return: 8916 * non-zero (if found) 8917 * -1 (if not found) 8918 * 8919 * Context: 8920 * Kernel context 8921 */ 8922 static int 8923 qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 8924 { 8925 int i, entries; 8926 uint8_t pid_match, wwn_match; 8927 int priority; 8928 uint32_t pid1, pid2; 8929 uint64_t wwn1, wwn2; 8930 struct qla_fcp_prio_entry *pri_entry; 8931 struct qla_hw_data *ha = vha->hw; 8932 8933 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled) 8934 return -1; 8935 8936 priority = -1; 8937 entries = ha->fcp_prio_cfg->num_entries; 8938 pri_entry = &ha->fcp_prio_cfg->entry[0]; 8939 8940 for (i = 0; i < entries; i++) { 8941 pid_match = wwn_match = 0; 8942 8943 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) { 8944 pri_entry++; 8945 continue; 8946 } 8947 8948 /* check source pid for a match */ 8949 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) { 8950 pid1 = pri_entry->src_pid & INVALID_PORT_ID; 8951 pid2 = vha->d_id.b24 & INVALID_PORT_ID; 8952 if (pid1 == INVALID_PORT_ID) 8953 pid_match++; 8954 else if (pid1 == pid2) 8955 pid_match++; 8956 } 8957 8958 /* check destination pid for a match */ 8959 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) { 8960 pid1 = pri_entry->dst_pid & INVALID_PORT_ID; 8961 pid2 = fcport->d_id.b24 & INVALID_PORT_ID; 8962 if (pid1 == INVALID_PORT_ID) 8963 pid_match++; 8964 else if (pid1 == pid2) 8965 pid_match++; 8966 } 8967 8968 /* check source WWN for a match */ 8969 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) { 8970 wwn1 = wwn_to_u64(vha->port_name); 8971 wwn2 = wwn_to_u64(pri_entry->src_wwpn); 8972 if (wwn2 == (uint64_t)-1) 8973 wwn_match++; 8974 else if (wwn1 == wwn2) 8975 wwn_match++; 8976 } 8977 8978 /* check destination WWN for a match */ 8979 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) { 8980 wwn1 = wwn_to_u64(fcport->port_name); 8981 wwn2 = wwn_to_u64(pri_entry->dst_wwpn); 8982 if (wwn2 == (uint64_t)-1) 8983 wwn_match++; 8984 else if (wwn1 == wwn2) 8985 wwn_match++; 8986 } 8987 8988 if (pid_match == 2 || wwn_match == 2) { 8989 /* Found a matching entry */ 8990 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID) 8991 priority = pri_entry->tag; 8992 break; 8993 } 8994 8995 pri_entry++; 8996 } 8997 8998 return priority; 8999 } 9000 9001 /* 9002 * qla24xx_update_fcport_fcp_prio 9003 * Activates fcp priority for the logged in fc port 9004 * 9005 * Input: 9006 * vha = scsi host structure pointer. 9007 * fcp = port structure pointer. 9008 * 9009 * Return: 9010 * QLA_SUCCESS or QLA_FUNCTION_FAILED 9011 * 9012 * Context: 9013 * Kernel context. 9014 */ 9015 int 9016 qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 9017 { 9018 int ret; 9019 int priority; 9020 uint16_t mb[5]; 9021 9022 if (fcport->port_type != FCT_TARGET || 9023 fcport->loop_id == FC_NO_LOOP_ID) 9024 return QLA_FUNCTION_FAILED; 9025 9026 priority = qla24xx_get_fcp_prio(vha, fcport); 9027 if (priority < 0) 9028 return QLA_FUNCTION_FAILED; 9029 9030 if (IS_P3P_TYPE(vha->hw)) { 9031 fcport->fcp_prio = priority & 0xf; 9032 return QLA_SUCCESS; 9033 } 9034 9035 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb); 9036 if (ret == QLA_SUCCESS) { 9037 if (fcport->fcp_prio != priority) 9038 ql_dbg(ql_dbg_user, vha, 0x709e, 9039 "Updated FCP_CMND priority - value=%d loop_id=%d " 9040 "port_id=%02x%02x%02x.\n", priority, 9041 fcport->loop_id, fcport->d_id.b.domain, 9042 fcport->d_id.b.area, fcport->d_id.b.al_pa); 9043 fcport->fcp_prio = priority & 0xf; 9044 } else 9045 ql_dbg(ql_dbg_user, vha, 0x704f, 9046 "Unable to update FCP_CMND priority - ret=0x%x for " 9047 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id, 9048 fcport->d_id.b.domain, fcport->d_id.b.area, 9049 fcport->d_id.b.al_pa); 9050 return ret; 9051 } 9052 9053 /* 9054 * qla24xx_update_all_fcp_prio 9055 * Activates fcp priority for all the logged in ports 9056 * 9057 * Input: 9058 * ha = adapter block pointer. 9059 * 9060 * Return: 9061 * QLA_SUCCESS or QLA_FUNCTION_FAILED 9062 * 9063 * Context: 9064 * Kernel context. 9065 */ 9066 int 9067 qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha) 9068 { 9069 int ret; 9070 fc_port_t *fcport; 9071 9072 ret = QLA_FUNCTION_FAILED; 9073 /* We need to set priority for all logged in ports */ 9074 list_for_each_entry(fcport, &vha->vp_fcports, list) 9075 ret = qla24xx_update_fcport_fcp_prio(vha, fcport); 9076 9077 return ret; 9078 } 9079 9080 struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, 9081 int vp_idx, bool startqp) 9082 { 9083 int rsp_id = 0; 9084 int req_id = 0; 9085 int i; 9086 struct qla_hw_data *ha = vha->hw; 9087 uint16_t qpair_id = 0; 9088 struct qla_qpair *qpair = NULL; 9089 struct qla_msix_entry *msix; 9090 9091 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) { 9092 ql_log(ql_log_warn, vha, 0x00181, 9093 "FW/Driver is not multi-queue capable.\n"); 9094 return NULL; 9095 } 9096 9097 if (ql2xmqsupport || ql2xnvmeenable) { 9098 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 9099 if (qpair == NULL) { 9100 ql_log(ql_log_warn, vha, 0x0182, 9101 "Failed to allocate memory for queue pair.\n"); 9102 return NULL; 9103 } 9104 9105 qpair->hw = vha->hw; 9106 qpair->vha = vha; 9107 qpair->qp_lock_ptr = &qpair->qp_lock; 9108 spin_lock_init(&qpair->qp_lock); 9109 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 9110 9111 /* Assign available que pair id */ 9112 mutex_lock(&ha->mq_lock); 9113 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs); 9114 if (ha->num_qpairs >= ha->max_qpairs) { 9115 mutex_unlock(&ha->mq_lock); 9116 ql_log(ql_log_warn, vha, 0x0183, 9117 "No resources to create additional q pair.\n"); 9118 goto fail_qid_map; 9119 } 9120 ha->num_qpairs++; 9121 set_bit(qpair_id, ha->qpair_qid_map); 9122 ha->queue_pair_map[qpair_id] = qpair; 9123 qpair->id = qpair_id; 9124 qpair->vp_idx = vp_idx; 9125 qpair->fw_started = ha->flags.fw_started; 9126 INIT_LIST_HEAD(&qpair->hints_list); 9127 qpair->chip_reset = ha->base_qpair->chip_reset; 9128 qpair->enable_class_2 = ha->base_qpair->enable_class_2; 9129 qpair->enable_explicit_conf = 9130 ha->base_qpair->enable_explicit_conf; 9131 9132 for (i = 0; i < ha->msix_count; i++) { 9133 msix = &ha->msix_entries[i]; 9134 if (msix->in_use) 9135 continue; 9136 qpair->msix = msix; 9137 ql_dbg(ql_dbg_multiq, vha, 0xc00f, 9138 "Vector %x selected for qpair\n", msix->vector); 9139 break; 9140 } 9141 if (!qpair->msix) { 9142 ql_log(ql_log_warn, vha, 0x0184, 9143 "Out of MSI-X vectors!.\n"); 9144 goto fail_msix; 9145 } 9146 9147 qpair->msix->in_use = 1; 9148 list_add_tail(&qpair->qp_list_elem, &vha->qp_list); 9149 qpair->pdev = ha->pdev; 9150 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 9151 qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 9152 9153 mutex_unlock(&ha->mq_lock); 9154 9155 /* Create response queue first */ 9156 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp); 9157 if (!rsp_id) { 9158 ql_log(ql_log_warn, vha, 0x0185, 9159 "Failed to create response queue.\n"); 9160 goto fail_rsp; 9161 } 9162 9163 qpair->rsp = ha->rsp_q_map[rsp_id]; 9164 9165 /* Create request queue */ 9166 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos, 9167 startqp); 9168 if (!req_id) { 9169 ql_log(ql_log_warn, vha, 0x0186, 9170 "Failed to create request queue.\n"); 9171 goto fail_req; 9172 } 9173 9174 qpair->req = ha->req_q_map[req_id]; 9175 qpair->rsp->req = qpair->req; 9176 qpair->rsp->qpair = qpair; 9177 /* init qpair to this cpu. Will adjust at run time. */ 9178 qla_cpu_update(qpair, smp_processor_id()); 9179 9180 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 9181 if (ha->fw_attributes & BIT_4) 9182 qpair->difdix_supported = 1; 9183 } 9184 9185 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 9186 if (!qpair->srb_mempool) { 9187 ql_log(ql_log_warn, vha, 0xd036, 9188 "Failed to create srb mempool for qpair %d\n", 9189 qpair->id); 9190 goto fail_mempool; 9191 } 9192 9193 /* Mark as online */ 9194 qpair->online = 1; 9195 9196 if (!vha->flags.qpairs_available) 9197 vha->flags.qpairs_available = 1; 9198 9199 ql_dbg(ql_dbg_multiq, vha, 0xc00d, 9200 "Request/Response queue pair created, id %d\n", 9201 qpair->id); 9202 ql_dbg(ql_dbg_init, vha, 0x0187, 9203 "Request/Response queue pair created, id %d\n", 9204 qpair->id); 9205 } 9206 return qpair; 9207 9208 fail_mempool: 9209 fail_req: 9210 qla25xx_delete_rsp_que(vha, qpair->rsp); 9211 fail_rsp: 9212 mutex_lock(&ha->mq_lock); 9213 qpair->msix->in_use = 0; 9214 list_del(&qpair->qp_list_elem); 9215 if (list_empty(&vha->qp_list)) 9216 vha->flags.qpairs_available = 0; 9217 fail_msix: 9218 ha->queue_pair_map[qpair_id] = NULL; 9219 clear_bit(qpair_id, ha->qpair_qid_map); 9220 ha->num_qpairs--; 9221 mutex_unlock(&ha->mq_lock); 9222 fail_qid_map: 9223 kfree(qpair); 9224 return NULL; 9225 } 9226 9227 int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair) 9228 { 9229 int ret = QLA_FUNCTION_FAILED; 9230 struct qla_hw_data *ha = qpair->hw; 9231 9232 qpair->delete_in_progress = 1; 9233 9234 ret = qla25xx_delete_req_que(vha, qpair->req); 9235 if (ret != QLA_SUCCESS) 9236 goto fail; 9237 9238 ret = qla25xx_delete_rsp_que(vha, qpair->rsp); 9239 if (ret != QLA_SUCCESS) 9240 goto fail; 9241 9242 mutex_lock(&ha->mq_lock); 9243 ha->queue_pair_map[qpair->id] = NULL; 9244 clear_bit(qpair->id, ha->qpair_qid_map); 9245 ha->num_qpairs--; 9246 list_del(&qpair->qp_list_elem); 9247 if (list_empty(&vha->qp_list)) { 9248 vha->flags.qpairs_available = 0; 9249 vha->flags.qpairs_req_created = 0; 9250 vha->flags.qpairs_rsp_created = 0; 9251 } 9252 mempool_destroy(qpair->srb_mempool); 9253 kfree(qpair); 9254 mutex_unlock(&ha->mq_lock); 9255 9256 return QLA_SUCCESS; 9257 fail: 9258 return ret; 9259 } 9260 9261 uint64_t 9262 qla2x00_count_set_bits(uint32_t num) 9263 { 9264 /* Brian Kernighan's Algorithm */ 9265 u64 count = 0; 9266 9267 while (num) { 9268 num &= (num - 1); 9269 count++; 9270 } 9271 return count; 9272 } 9273 9274 uint64_t 9275 qla2x00_get_num_tgts(scsi_qla_host_t *vha) 9276 { 9277 fc_port_t *f, *tf; 9278 u64 count = 0; 9279 9280 f = NULL; 9281 tf = NULL; 9282 9283 list_for_each_entry_safe(f, tf, &vha->vp_fcports, list) { 9284 if (f->port_type != FCT_TARGET) 9285 continue; 9286 count++; 9287 } 9288 return count; 9289 } 9290 9291 int qla2xxx_reset_stats(struct Scsi_Host *host, u32 flags) 9292 { 9293 scsi_qla_host_t *vha = shost_priv(host); 9294 fc_port_t *fcport = NULL; 9295 unsigned long int_flags; 9296 9297 if (flags & QLA2XX_HW_ERROR) 9298 vha->hw_err_cnt = 0; 9299 if (flags & QLA2XX_SHT_LNK_DWN) 9300 vha->short_link_down_cnt = 0; 9301 if (flags & QLA2XX_INT_ERR) 9302 vha->interface_err_cnt = 0; 9303 if (flags & QLA2XX_CMD_TIMEOUT) 9304 vha->cmd_timeout_cnt = 0; 9305 if (flags & QLA2XX_RESET_CMD_ERR) 9306 vha->reset_cmd_err_cnt = 0; 9307 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) { 9308 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags); 9309 list_for_each_entry(fcport, &vha->vp_fcports, list) { 9310 fcport->tgt_short_link_down_cnt = 0; 9311 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 9312 } 9313 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags); 9314 } 9315 vha->link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 9316 return 0; 9317 } 9318 9319 int qla2xxx_start_stats(struct Scsi_Host *host, u32 flags) 9320 { 9321 return qla2xxx_reset_stats(host, flags); 9322 } 9323 9324 int qla2xxx_stop_stats(struct Scsi_Host *host, u32 flags) 9325 { 9326 return qla2xxx_reset_stats(host, flags); 9327 } 9328 9329 int qla2xxx_get_ini_stats(struct Scsi_Host *host, u32 flags, 9330 void *data, u64 size) 9331 { 9332 scsi_qla_host_t *vha = shost_priv(host); 9333 struct ql_vnd_host_stats_resp *resp = (struct ql_vnd_host_stats_resp *)data; 9334 struct ql_vnd_stats *rsp_data = &resp->stats; 9335 u64 ini_entry_count = 0; 9336 u64 i = 0; 9337 u64 entry_count = 0; 9338 u64 num_tgt = 0; 9339 u32 tmp_stat_type = 0; 9340 fc_port_t *fcport = NULL; 9341 unsigned long int_flags; 9342 9343 /* Copy stat type to work on it */ 9344 tmp_stat_type = flags; 9345 9346 if (tmp_stat_type & BIT_17) { 9347 num_tgt = qla2x00_get_num_tgts(vha); 9348 /* unset BIT_17 */ 9349 tmp_stat_type &= ~(1 << 17); 9350 } 9351 ini_entry_count = qla2x00_count_set_bits(tmp_stat_type); 9352 9353 entry_count = ini_entry_count + num_tgt; 9354 9355 rsp_data->entry_count = entry_count; 9356 9357 i = 0; 9358 if (flags & QLA2XX_HW_ERROR) { 9359 rsp_data->entry[i].stat_type = QLA2XX_HW_ERROR; 9360 rsp_data->entry[i].tgt_num = 0x0; 9361 rsp_data->entry[i].cnt = vha->hw_err_cnt; 9362 i++; 9363 } 9364 9365 if (flags & QLA2XX_SHT_LNK_DWN) { 9366 rsp_data->entry[i].stat_type = QLA2XX_SHT_LNK_DWN; 9367 rsp_data->entry[i].tgt_num = 0x0; 9368 rsp_data->entry[i].cnt = vha->short_link_down_cnt; 9369 i++; 9370 } 9371 9372 if (flags & QLA2XX_INT_ERR) { 9373 rsp_data->entry[i].stat_type = QLA2XX_INT_ERR; 9374 rsp_data->entry[i].tgt_num = 0x0; 9375 rsp_data->entry[i].cnt = vha->interface_err_cnt; 9376 i++; 9377 } 9378 9379 if (flags & QLA2XX_CMD_TIMEOUT) { 9380 rsp_data->entry[i].stat_type = QLA2XX_CMD_TIMEOUT; 9381 rsp_data->entry[i].tgt_num = 0x0; 9382 rsp_data->entry[i].cnt = vha->cmd_timeout_cnt; 9383 i++; 9384 } 9385 9386 if (flags & QLA2XX_RESET_CMD_ERR) { 9387 rsp_data->entry[i].stat_type = QLA2XX_RESET_CMD_ERR; 9388 rsp_data->entry[i].tgt_num = 0x0; 9389 rsp_data->entry[i].cnt = vha->reset_cmd_err_cnt; 9390 i++; 9391 } 9392 9393 /* i will continue from previous loop, as target 9394 * entries are after initiator 9395 */ 9396 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) { 9397 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags); 9398 list_for_each_entry(fcport, &vha->vp_fcports, list) { 9399 if (fcport->port_type != FCT_TARGET) 9400 continue; 9401 if (!fcport->rport) 9402 continue; 9403 rsp_data->entry[i].stat_type = QLA2XX_TGT_SHT_LNK_DOWN; 9404 rsp_data->entry[i].tgt_num = fcport->rport->number; 9405 rsp_data->entry[i].cnt = fcport->tgt_short_link_down_cnt; 9406 i++; 9407 } 9408 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags); 9409 } 9410 resp->status = EXT_STATUS_OK; 9411 9412 return 0; 9413 } 9414 9415 int qla2xxx_get_tgt_stats(struct Scsi_Host *host, u32 flags, 9416 struct fc_rport *rport, void *data, u64 size) 9417 { 9418 struct ql_vnd_tgt_stats_resp *tgt_data = data; 9419 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 9420 9421 tgt_data->status = 0; 9422 tgt_data->stats.entry_count = 1; 9423 tgt_data->stats.entry[0].stat_type = flags; 9424 tgt_data->stats.entry[0].tgt_num = rport->number; 9425 tgt_data->stats.entry[0].cnt = fcport->tgt_short_link_down_cnt; 9426 9427 return 0; 9428 } 9429 9430 int qla2xxx_disable_port(struct Scsi_Host *host) 9431 { 9432 scsi_qla_host_t *vha = shost_priv(host); 9433 9434 vha->hw->flags.port_isolated = 1; 9435 9436 if (qla2x00_chip_is_down(vha)) 9437 return 0; 9438 9439 if (vha->flags.online) { 9440 qla2x00_abort_isp_cleanup(vha); 9441 qla2x00_wait_for_sess_deletion(vha); 9442 } 9443 9444 return 0; 9445 } 9446 9447 int qla2xxx_enable_port(struct Scsi_Host *host) 9448 { 9449 scsi_qla_host_t *vha = shost_priv(host); 9450 9451 vha->hw->flags.port_isolated = 0; 9452 /* Set the flag to 1, so that isp_abort can proceed */ 9453 vha->flags.online = 1; 9454 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 9455 qla2xxx_wake_dpc(vha); 9456 9457 return 0; 9458 } 9459