1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_gbl.h" 9 10 #include <linux/delay.h> 11 #include <linux/slab.h> 12 #include <linux/vmalloc.h> 13 14 #include "qla_devtbl.h" 15 16 #ifdef CONFIG_SPARC 17 #include <asm/prom.h> 18 #endif 19 20 #include <target/target_core_base.h> 21 #include "qla_target.h" 22 23 /* 24 * QLogic ISP2x00 Hardware Support Function Prototypes. 25 */ 26 static int qla2x00_isp_firmware(scsi_qla_host_t *); 27 static int qla2x00_setup_chip(scsi_qla_host_t *); 28 static int qla2x00_fw_ready(scsi_qla_host_t *); 29 static int qla2x00_configure_hba(scsi_qla_host_t *); 30 static int qla2x00_configure_loop(scsi_qla_host_t *); 31 static int qla2x00_configure_local_loop(scsi_qla_host_t *); 32 static int qla2x00_configure_fabric(scsi_qla_host_t *); 33 static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *); 34 static int qla2x00_restart_isp(scsi_qla_host_t *); 35 36 static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *); 37 static int qla84xx_init_chip(scsi_qla_host_t *); 38 static int qla25xx_init_queues(struct qla_hw_data *); 39 static int qla24xx_post_gpdb_work(struct scsi_qla_host *, fc_port_t *, u8); 40 static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *, 41 struct event_arg *); 42 43 /* SRB Extensions ---------------------------------------------------------- */ 44 45 void 46 qla2x00_sp_timeout(unsigned long __data) 47 { 48 srb_t *sp = (srb_t *)__data; 49 struct srb_iocb *iocb; 50 scsi_qla_host_t *vha = sp->vha; 51 struct req_que *req; 52 unsigned long flags; 53 54 spin_lock_irqsave(&vha->hw->hardware_lock, flags); 55 req = vha->hw->req_q_map[0]; 56 req->outstanding_cmds[sp->handle] = NULL; 57 iocb = &sp->u.iocb_cmd; 58 iocb->timeout(sp); 59 sp->free(sp); 60 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags); 61 } 62 63 void 64 qla2x00_sp_free(void *ptr) 65 { 66 srb_t *sp = ptr; 67 struct srb_iocb *iocb = &sp->u.iocb_cmd; 68 69 del_timer(&iocb->timer); 70 qla2x00_rel_sp(sp); 71 } 72 73 /* Asynchronous Login/Logout Routines -------------------------------------- */ 74 75 unsigned long 76 qla2x00_get_async_timeout(struct scsi_qla_host *vha) 77 { 78 unsigned long tmo; 79 struct qla_hw_data *ha = vha->hw; 80 81 /* Firmware should use switch negotiated r_a_tov for timeout. */ 82 tmo = ha->r_a_tov / 10 * 2; 83 if (IS_QLAFX00(ha)) { 84 tmo = FX00_DEF_RATOV * 2; 85 } else if (!IS_FWI2_CAPABLE(ha)) { 86 /* 87 * Except for earlier ISPs where the timeout is seeded from the 88 * initialization control block. 89 */ 90 tmo = ha->login_timeout; 91 } 92 return tmo; 93 } 94 95 void 96 qla2x00_async_iocb_timeout(void *data) 97 { 98 srb_t *sp = data; 99 fc_port_t *fcport = sp->fcport; 100 struct srb_iocb *lio = &sp->u.iocb_cmd; 101 struct event_arg ea; 102 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, 104 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n", 105 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name); 106 107 fcport->flags &= ~FCF_ASYNC_SENT; 108 109 switch (sp->type) { 110 case SRB_LOGIN_CMD: 111 /* Retry as needed. */ 112 lio->u.logio.data[0] = MBS_COMMAND_ERROR; 113 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ? 114 QLA_LOGIO_LOGIN_RETRIED : 0; 115 memset(&ea, 0, sizeof(ea)); 116 ea.event = FCME_PLOGI_DONE; 117 ea.fcport = sp->fcport; 118 ea.data[0] = lio->u.logio.data[0]; 119 ea.data[1] = lio->u.logio.data[1]; 120 ea.sp = sp; 121 qla24xx_handle_plogi_done_event(fcport->vha, &ea); 122 break; 123 case SRB_LOGOUT_CMD: 124 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT); 125 break; 126 case SRB_CT_PTHRU_CMD: 127 case SRB_MB_IOCB: 128 case SRB_NACK_PLOGI: 129 case SRB_NACK_PRLI: 130 case SRB_NACK_LOGO: 131 sp->done(sp, QLA_FUNCTION_TIMEOUT); 132 break; 133 } 134 } 135 136 static void 137 qla2x00_async_login_sp_done(void *ptr, int res) 138 { 139 srb_t *sp = ptr; 140 struct scsi_qla_host *vha = sp->vha; 141 struct srb_iocb *lio = &sp->u.iocb_cmd; 142 struct event_arg ea; 143 144 ql_dbg(ql_dbg_disc, vha, 0xffff, 145 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res); 146 147 sp->fcport->flags &= ~FCF_ASYNC_SENT; 148 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 149 memset(&ea, 0, sizeof(ea)); 150 ea.event = FCME_PLOGI_DONE; 151 ea.fcport = sp->fcport; 152 ea.data[0] = lio->u.logio.data[0]; 153 ea.data[1] = lio->u.logio.data[1]; 154 ea.iop[0] = lio->u.logio.iop[0]; 155 ea.iop[1] = lio->u.logio.iop[1]; 156 ea.sp = sp; 157 qla2x00_fcport_event_handler(vha, &ea); 158 } 159 160 sp->free(sp); 161 } 162 163 int 164 qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport, 165 uint16_t *data) 166 { 167 srb_t *sp; 168 struct srb_iocb *lio; 169 int rval = QLA_FUNCTION_FAILED; 170 171 if (!vha->flags.online) 172 goto done; 173 174 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) || 175 (fcport->fw_login_state == DSC_LS_PLOGI_COMP) || 176 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) 177 goto done; 178 179 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 180 if (!sp) 181 goto done; 182 183 fcport->flags |= FCF_ASYNC_SENT; 184 fcport->logout_completed = 0; 185 186 sp->type = SRB_LOGIN_CMD; 187 sp->name = "login"; 188 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 189 190 lio = &sp->u.iocb_cmd; 191 lio->timeout = qla2x00_async_iocb_timeout; 192 sp->done = qla2x00_async_login_sp_done; 193 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI; 194 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 195 lio->u.logio.flags |= SRB_LOGIN_RETRIED; 196 rval = qla2x00_start_sp(sp); 197 if (rval != QLA_SUCCESS) { 198 fcport->flags &= ~FCF_ASYNC_SENT; 199 fcport->flags |= FCF_LOGIN_NEEDED; 200 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 201 goto done_free_sp; 202 } 203 204 ql_dbg(ql_dbg_disc, vha, 0x2072, 205 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x " 206 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id, 207 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa, 208 fcport->login_retry); 209 return rval; 210 211 done_free_sp: 212 sp->free(sp); 213 done: 214 fcport->flags &= ~FCF_ASYNC_SENT; 215 return rval; 216 } 217 218 static void 219 qla2x00_async_logout_sp_done(void *ptr, int res) 220 { 221 srb_t *sp = ptr; 222 struct srb_iocb *lio = &sp->u.iocb_cmd; 223 224 sp->fcport->flags &= ~FCF_ASYNC_SENT; 225 if (!test_bit(UNLOADING, &sp->vha->dpc_flags)) 226 qla2x00_post_async_logout_done_work(sp->vha, sp->fcport, 227 lio->u.logio.data); 228 sp->free(sp); 229 } 230 231 int 232 qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport) 233 { 234 srb_t *sp; 235 struct srb_iocb *lio; 236 int rval; 237 238 rval = QLA_FUNCTION_FAILED; 239 fcport->flags |= FCF_ASYNC_SENT; 240 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 241 if (!sp) 242 goto done; 243 244 sp->type = SRB_LOGOUT_CMD; 245 sp->name = "logout"; 246 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 247 248 lio = &sp->u.iocb_cmd; 249 lio->timeout = qla2x00_async_iocb_timeout; 250 sp->done = qla2x00_async_logout_sp_done; 251 rval = qla2x00_start_sp(sp); 252 if (rval != QLA_SUCCESS) 253 goto done_free_sp; 254 255 ql_dbg(ql_dbg_disc, vha, 0x2070, 256 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n", 257 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 258 fcport->d_id.b.area, fcport->d_id.b.al_pa, 259 fcport->port_name); 260 return rval; 261 262 done_free_sp: 263 sp->free(sp); 264 done: 265 fcport->flags &= ~FCF_ASYNC_SENT; 266 return rval; 267 } 268 269 static void 270 qla2x00_async_adisc_sp_done(void *ptr, int res) 271 { 272 srb_t *sp = ptr; 273 struct scsi_qla_host *vha = sp->vha; 274 struct srb_iocb *lio = &sp->u.iocb_cmd; 275 276 if (!test_bit(UNLOADING, &vha->dpc_flags)) 277 qla2x00_post_async_adisc_done_work(sp->vha, sp->fcport, 278 lio->u.logio.data); 279 sp->free(sp); 280 } 281 282 int 283 qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport, 284 uint16_t *data) 285 { 286 srb_t *sp; 287 struct srb_iocb *lio; 288 int rval; 289 290 rval = QLA_FUNCTION_FAILED; 291 fcport->flags |= FCF_ASYNC_SENT; 292 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 293 if (!sp) 294 goto done; 295 296 sp->type = SRB_ADISC_CMD; 297 sp->name = "adisc"; 298 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 299 300 lio = &sp->u.iocb_cmd; 301 lio->timeout = qla2x00_async_iocb_timeout; 302 sp->done = qla2x00_async_adisc_sp_done; 303 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 304 lio->u.logio.flags |= SRB_LOGIN_RETRIED; 305 rval = qla2x00_start_sp(sp); 306 if (rval != QLA_SUCCESS) 307 goto done_free_sp; 308 309 ql_dbg(ql_dbg_disc, vha, 0x206f, 310 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n", 311 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 312 fcport->d_id.b.area, fcport->d_id.b.al_pa); 313 return rval; 314 315 done_free_sp: 316 sp->free(sp); 317 done: 318 fcport->flags &= ~FCF_ASYNC_SENT; 319 return rval; 320 } 321 322 static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha, 323 struct event_arg *ea) 324 { 325 fc_port_t *fcport, *conflict_fcport; 326 struct get_name_list_extended *e; 327 u16 i, n, found = 0, loop_id; 328 port_id_t id; 329 u64 wwn; 330 u8 opt = 0; 331 332 fcport = ea->fcport; 333 334 if (ea->rc) { /* rval */ 335 if (fcport->login_retry == 0) { 336 fcport->login_retry = vha->hw->login_retry_count; 337 ql_dbg(ql_dbg_disc, vha, 0xffff, 338 "GNL failed Port login retry %8phN, retry cnt=%d.\n", 339 fcport->port_name, fcport->login_retry); 340 } 341 return; 342 } 343 344 if (fcport->last_rscn_gen != fcport->rscn_gen) { 345 ql_dbg(ql_dbg_disc, vha, 0xffff, 346 "%s %8phC rscn gen changed rscn %d|%d \n", 347 __func__, fcport->port_name, 348 fcport->last_rscn_gen, fcport->rscn_gen); 349 qla24xx_post_gidpn_work(vha, fcport); 350 return; 351 } else if (fcport->last_login_gen != fcport->login_gen) { 352 ql_dbg(ql_dbg_disc, vha, 0xffff, 353 "%s %8phC login gen changed login %d|%d \n", 354 __func__, fcport->port_name, 355 fcport->last_login_gen, fcport->login_gen); 356 return; 357 } 358 359 n = ea->data[0] / sizeof(struct get_name_list_extended); 360 361 ql_dbg(ql_dbg_disc, vha, 0xffff, 362 "%s %d %8phC n %d %02x%02x%02x lid %d \n", 363 __func__, __LINE__, fcport->port_name, n, 364 fcport->d_id.b.domain, fcport->d_id.b.area, 365 fcport->d_id.b.al_pa, fcport->loop_id); 366 367 for (i = 0; i < n; i++) { 368 e = &vha->gnl.l[i]; 369 wwn = wwn_to_u64(e->port_name); 370 371 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE)) 372 continue; 373 374 found = 1; 375 id.b.domain = e->port_id[2]; 376 id.b.area = e->port_id[1]; 377 id.b.al_pa = e->port_id[0]; 378 id.b.rsvd_1 = 0; 379 380 loop_id = le16_to_cpu(e->nport_handle); 381 loop_id = (loop_id & 0x7fff); 382 383 ql_dbg(ql_dbg_disc, vha, 0xffff, 384 "%s found %8phC CLS [%d|%d] ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n", 385 __func__, fcport->port_name, 386 e->current_login_state, fcport->fw_login_state, 387 id.b.domain, id.b.area, id.b.al_pa, 388 fcport->d_id.b.domain, fcport->d_id.b.area, 389 fcport->d_id.b.al_pa, loop_id, fcport->loop_id); 390 391 if ((id.b24 != fcport->d_id.b24) || 392 ((fcport->loop_id != FC_NO_LOOP_ID) && 393 (fcport->loop_id != loop_id))) { 394 ql_dbg(ql_dbg_disc, vha, 0xffff, 395 "%s %d %8phC post del sess\n", 396 __func__, __LINE__, fcport->port_name); 397 qlt_schedule_sess_for_deletion(fcport, 1); 398 return; 399 } 400 401 fcport->loop_id = loop_id; 402 403 wwn = wwn_to_u64(fcport->port_name); 404 qlt_find_sess_invalidate_other(vha, wwn, 405 id, loop_id, &conflict_fcport); 406 407 if (conflict_fcport) { 408 /* 409 * Another share fcport share the same loop_id & 410 * nport id. Conflict fcport needs to finish 411 * cleanup before this fcport can proceed to login. 412 */ 413 conflict_fcport->conflict = fcport; 414 fcport->login_pause = 1; 415 } 416 417 switch (e->current_login_state) { 418 case DSC_LS_PRLI_COMP: 419 ql_dbg(ql_dbg_disc, vha, 0xffff, 420 "%s %d %8phC post gpdb\n", 421 __func__, __LINE__, fcport->port_name); 422 opt = PDO_FORCE_ADISC; 423 qla24xx_post_gpdb_work(vha, fcport, opt); 424 break; 425 426 case DSC_LS_PORT_UNAVAIL: 427 default: 428 if (fcport->loop_id == FC_NO_LOOP_ID) { 429 qla2x00_find_new_loop_id(vha, fcport); 430 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 431 } 432 ql_dbg(ql_dbg_disc, vha, 0xffff, 433 "%s %d %8phC \n", 434 __func__, __LINE__, fcport->port_name); 435 qla24xx_fcport_handle_login(vha, fcport); 436 break; 437 } 438 } 439 440 if (!found) { 441 /* fw has no record of this port */ 442 if (fcport->loop_id == FC_NO_LOOP_ID) { 443 qla2x00_find_new_loop_id(vha, fcport); 444 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 445 } else { 446 for (i = 0; i < n; i++) { 447 e = &vha->gnl.l[i]; 448 id.b.domain = e->port_id[0]; 449 id.b.area = e->port_id[1]; 450 id.b.al_pa = e->port_id[2]; 451 id.b.rsvd_1 = 0; 452 loop_id = le16_to_cpu(e->nport_handle); 453 454 if (fcport->d_id.b24 == id.b24) { 455 conflict_fcport = 456 qla2x00_find_fcport_by_wwpn(vha, 457 e->port_name, 0); 458 459 ql_dbg(ql_dbg_disc, vha, 0xffff, 460 "%s %d %8phC post del sess\n", 461 __func__, __LINE__, 462 conflict_fcport->port_name); 463 qlt_schedule_sess_for_deletion 464 (conflict_fcport, 1); 465 } 466 467 if (fcport->loop_id == loop_id) { 468 /* FW already picked this loop id for another fcport */ 469 qla2x00_find_new_loop_id(vha, fcport); 470 } 471 } 472 } 473 qla24xx_fcport_handle_login(vha, fcport); 474 } 475 } /* gnl_event */ 476 477 static void 478 qla24xx_async_gnl_sp_done(void *s, int res) 479 { 480 struct srb *sp = s; 481 struct scsi_qla_host *vha = sp->vha; 482 unsigned long flags; 483 struct fc_port *fcport = NULL, *tf; 484 u16 i, n = 0, loop_id; 485 struct event_arg ea; 486 struct get_name_list_extended *e; 487 u64 wwn; 488 struct list_head h; 489 490 ql_dbg(ql_dbg_disc, vha, 0xffff, 491 "Async done-%s res %x mb[1]=%x mb[2]=%x \n", 492 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1], 493 sp->u.iocb_cmd.u.mbx.in_mb[2]); 494 495 memset(&ea, 0, sizeof(ea)); 496 ea.sp = sp; 497 ea.rc = res; 498 ea.event = FCME_GNL_DONE; 499 500 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >= 501 sizeof(struct get_name_list_extended)) { 502 n = sp->u.iocb_cmd.u.mbx.in_mb[1] / 503 sizeof(struct get_name_list_extended); 504 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */ 505 } 506 507 for (i = 0; i < n; i++) { 508 e = &vha->gnl.l[i]; 509 loop_id = le16_to_cpu(e->nport_handle); 510 /* mask out reserve bit */ 511 loop_id = (loop_id & 0x7fff); 512 set_bit(loop_id, vha->hw->loop_id_map); 513 wwn = wwn_to_u64(e->port_name); 514 515 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0xffff, 516 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n", 517 __func__, (void *)&wwn, e->port_id[2], e->port_id[1], 518 e->port_id[0], e->current_login_state, e->last_login_state, 519 (loop_id & 0x7fff)); 520 } 521 522 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 523 vha->gnl.sent = 0; 524 525 INIT_LIST_HEAD(&h); 526 fcport = tf = NULL; 527 if (!list_empty(&vha->gnl.fcports)) 528 list_splice_init(&vha->gnl.fcports, &h); 529 530 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) { 531 list_del_init(&fcport->gnl_entry); 532 fcport->flags &= ~FCF_ASYNC_SENT; 533 ea.fcport = fcport; 534 535 qla2x00_fcport_event_handler(vha, &ea); 536 } 537 538 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 539 540 sp->free(sp); 541 } 542 543 int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport) 544 { 545 srb_t *sp; 546 struct srb_iocb *mbx; 547 int rval = QLA_FUNCTION_FAILED; 548 unsigned long flags; 549 u16 *mb; 550 551 if (!vha->flags.online) 552 goto done; 553 554 ql_dbg(ql_dbg_disc, vha, 0xffff, 555 "Async-gnlist WWPN %8phC \n", fcport->port_name); 556 557 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 558 fcport->flags |= FCF_ASYNC_SENT; 559 fcport->disc_state = DSC_GNL; 560 fcport->last_rscn_gen = fcport->rscn_gen; 561 fcport->last_login_gen = fcport->login_gen; 562 563 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports); 564 if (vha->gnl.sent) { 565 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 566 rval = QLA_SUCCESS; 567 goto done; 568 } 569 vha->gnl.sent = 1; 570 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 571 572 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 573 if (!sp) 574 goto done; 575 sp->type = SRB_MB_IOCB; 576 sp->name = "gnlist"; 577 sp->gen1 = fcport->rscn_gen; 578 sp->gen2 = fcport->login_gen; 579 580 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2); 581 582 mb = sp->u.iocb_cmd.u.mbx.out_mb; 583 mb[0] = MBC_PORT_NODE_NAME_LIST; 584 mb[1] = BIT_2 | BIT_3; 585 mb[2] = MSW(vha->gnl.ldma); 586 mb[3] = LSW(vha->gnl.ldma); 587 mb[6] = MSW(MSD(vha->gnl.ldma)); 588 mb[7] = LSW(MSD(vha->gnl.ldma)); 589 mb[8] = vha->gnl.size; 590 mb[9] = vha->vp_idx; 591 592 mbx = &sp->u.iocb_cmd; 593 mbx->timeout = qla2x00_async_iocb_timeout; 594 595 sp->done = qla24xx_async_gnl_sp_done; 596 597 rval = qla2x00_start_sp(sp); 598 if (rval != QLA_SUCCESS) 599 goto done_free_sp; 600 601 ql_dbg(ql_dbg_disc, vha, 0xffff, 602 "Async-%s - OUT WWPN %8phC hndl %x\n", 603 sp->name, fcport->port_name, sp->handle); 604 605 return rval; 606 607 done_free_sp: 608 sp->free(sp); 609 done: 610 fcport->flags &= ~FCF_ASYNC_SENT; 611 return rval; 612 } 613 614 int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport) 615 { 616 struct qla_work_evt *e; 617 618 e = qla2x00_alloc_work(vha, QLA_EVT_GNL); 619 if (!e) 620 return QLA_FUNCTION_FAILED; 621 622 e->u.fcport.fcport = fcport; 623 return qla2x00_post_work(vha, e); 624 } 625 626 static 627 void qla24xx_async_gpdb_sp_done(void *s, int res) 628 { 629 struct srb *sp = s; 630 struct scsi_qla_host *vha = sp->vha; 631 struct qla_hw_data *ha = vha->hw; 632 struct port_database_24xx *pd; 633 fc_port_t *fcport = sp->fcport; 634 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb; 635 int rval = QLA_SUCCESS; 636 struct event_arg ea; 637 638 ql_dbg(ql_dbg_disc, vha, 0xffff, 639 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n", 640 sp->name, res, fcport->port_name, mb[1], mb[2]); 641 642 fcport->flags &= ~FCF_ASYNC_SENT; 643 644 if (res) { 645 rval = res; 646 goto gpd_error_out; 647 } 648 649 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in; 650 651 rval = __qla24xx_parse_gpdb(vha, fcport, pd); 652 653 gpd_error_out: 654 memset(&ea, 0, sizeof(ea)); 655 ea.event = FCME_GPDB_DONE; 656 ea.rc = rval; 657 ea.fcport = fcport; 658 ea.sp = sp; 659 660 qla2x00_fcport_event_handler(vha, &ea); 661 662 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in, 663 sp->u.iocb_cmd.u.mbx.in_dma); 664 665 sp->free(sp); 666 } 667 668 static int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, 669 u8 opt) 670 { 671 struct qla_work_evt *e; 672 673 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB); 674 if (!e) 675 return QLA_FUNCTION_FAILED; 676 677 e->u.fcport.fcport = fcport; 678 e->u.fcport.opt = opt; 679 return qla2x00_post_work(vha, e); 680 } 681 682 int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 683 { 684 srb_t *sp; 685 struct srb_iocb *mbx; 686 int rval = QLA_FUNCTION_FAILED; 687 u16 *mb; 688 dma_addr_t pd_dma; 689 struct port_database_24xx *pd; 690 struct qla_hw_data *ha = vha->hw; 691 692 if (!vha->flags.online) 693 goto done; 694 695 fcport->flags |= FCF_ASYNC_SENT; 696 fcport->disc_state = DSC_GPDB; 697 698 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 699 if (!sp) 700 goto done; 701 702 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 703 if (pd == NULL) { 704 ql_log(ql_log_warn, vha, 0xffff, 705 "Failed to allocate port database structure.\n"); 706 goto done_free_sp; 707 } 708 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE)); 709 710 sp->type = SRB_MB_IOCB; 711 sp->name = "gpdb"; 712 sp->gen1 = fcport->rscn_gen; 713 sp->gen2 = fcport->login_gen; 714 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 715 716 mb = sp->u.iocb_cmd.u.mbx.out_mb; 717 mb[0] = MBC_GET_PORT_DATABASE; 718 mb[1] = fcport->loop_id; 719 mb[2] = MSW(pd_dma); 720 mb[3] = LSW(pd_dma); 721 mb[6] = MSW(MSD(pd_dma)); 722 mb[7] = LSW(MSD(pd_dma)); 723 mb[9] = vha->vp_idx; 724 mb[10] = opt; 725 726 mbx = &sp->u.iocb_cmd; 727 mbx->timeout = qla2x00_async_iocb_timeout; 728 mbx->u.mbx.in = (void *)pd; 729 mbx->u.mbx.in_dma = pd_dma; 730 731 sp->done = qla24xx_async_gpdb_sp_done; 732 733 rval = qla2x00_start_sp(sp); 734 if (rval != QLA_SUCCESS) 735 goto done_free_sp; 736 737 ql_dbg(ql_dbg_disc, vha, 0xffff, 738 "Async-%s %8phC hndl %x opt %x\n", 739 sp->name, fcport->port_name, sp->handle, opt); 740 741 return rval; 742 743 done_free_sp: 744 if (pd) 745 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 746 747 sp->free(sp); 748 done: 749 fcport->flags &= ~FCF_ASYNC_SENT; 750 qla24xx_post_gpdb_work(vha, fcport, opt); 751 return rval; 752 } 753 754 static 755 void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea) 756 { 757 int rval = ea->rc; 758 fc_port_t *fcport = ea->fcport; 759 unsigned long flags; 760 761 fcport->flags &= ~FCF_ASYNC_SENT; 762 763 ql_dbg(ql_dbg_disc, vha, 0xffff, 764 "%s %8phC DS %d LS %d rval %d\n", __func__, fcport->port_name, 765 fcport->disc_state, fcport->fw_login_state, rval); 766 767 if (ea->sp->gen2 != fcport->login_gen) { 768 /* target side must have changed it. */ 769 ql_dbg(ql_dbg_disc, vha, 0xffff, 770 "%s %8phC generation changed rscn %d|%d login %d|%d \n", 771 __func__, fcport->port_name, fcport->last_rscn_gen, 772 fcport->rscn_gen, fcport->last_login_gen, 773 fcport->login_gen); 774 return; 775 } else if (ea->sp->gen1 != fcport->rscn_gen) { 776 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post gidpn\n", 777 __func__, __LINE__, fcport->port_name); 778 qla24xx_post_gidpn_work(vha, fcport); 779 return; 780 } 781 782 if (rval != QLA_SUCCESS) { 783 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post del sess\n", 784 __func__, __LINE__, fcport->port_name); 785 qlt_schedule_sess_for_deletion_lock(fcport); 786 return; 787 } 788 789 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 790 ea->fcport->login_gen++; 791 ea->fcport->deleted = 0; 792 ea->fcport->logout_on_delete = 1; 793 794 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) { 795 vha->fcport_count++; 796 ea->fcport->login_succ = 1; 797 798 if (!IS_IIDMA_CAPABLE(vha->hw) || 799 !vha->hw->flags.gpsc_supported) { 800 ql_dbg(ql_dbg_disc, vha, 0xffff, 801 "%s %d %8phC post upd_fcport fcp_cnt %d\n", 802 __func__, __LINE__, fcport->port_name, 803 vha->fcport_count); 804 805 qla24xx_post_upd_fcport_work(vha, fcport); 806 } else { 807 ql_dbg(ql_dbg_disc, vha, 0xffff, 808 "%s %d %8phC post gpsc fcp_cnt %d\n", 809 __func__, __LINE__, fcport->port_name, 810 vha->fcport_count); 811 812 qla24xx_post_gpsc_work(vha, fcport); 813 } 814 } 815 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 816 } /* gpdb event */ 817 818 int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport) 819 { 820 if (fcport->login_retry == 0) 821 return 0; 822 823 if (fcport->scan_state != QLA_FCPORT_FOUND) 824 return 0; 825 826 ql_dbg(ql_dbg_disc, vha, 0xffff, 827 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d|%d retry %d lid %d\n", 828 __func__, fcport->port_name, fcport->disc_state, 829 fcport->fw_login_state, fcport->login_pause, fcport->flags, 830 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen, 831 fcport->last_login_gen, fcport->login_gen, fcport->login_retry, 832 fcport->loop_id); 833 834 fcport->login_retry--; 835 836 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) || 837 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) 838 return 0; 839 840 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) { 841 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) 842 return 0; 843 } 844 845 /* for pure Target Mode. Login will not be initiated */ 846 if (vha->host->active_mode == MODE_TARGET) 847 return 0; 848 849 if (fcport->flags & FCF_ASYNC_SENT) { 850 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 851 return 0; 852 } 853 854 switch (fcport->disc_state) { 855 case DSC_DELETED: 856 if (fcport->loop_id == FC_NO_LOOP_ID) { 857 ql_dbg(ql_dbg_disc, vha, 0xffff, 858 "%s %d %8phC post gnl\n", 859 __func__, __LINE__, fcport->port_name); 860 qla24xx_async_gnl(vha, fcport); 861 } else { 862 ql_dbg(ql_dbg_disc, vha, 0xffff, 863 "%s %d %8phC post login\n", 864 __func__, __LINE__, fcport->port_name); 865 fcport->disc_state = DSC_LOGIN_PEND; 866 qla2x00_post_async_login_work(vha, fcport, NULL); 867 } 868 break; 869 870 case DSC_GNL: 871 if (fcport->login_pause) { 872 fcport->last_rscn_gen = fcport->rscn_gen; 873 fcport->last_login_gen = fcport->login_gen; 874 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 875 break; 876 } 877 878 if (fcport->flags & FCF_FCP2_DEVICE) { 879 u8 opt = PDO_FORCE_ADISC; 880 881 ql_dbg(ql_dbg_disc, vha, 0xffff, 882 "%s %d %8phC post gpdb\n", 883 __func__, __LINE__, fcport->port_name); 884 885 fcport->disc_state = DSC_GPDB; 886 qla24xx_post_gpdb_work(vha, fcport, opt); 887 } else { 888 ql_dbg(ql_dbg_disc, vha, 0xffff, 889 "%s %d %8phC post login \n", 890 __func__, __LINE__, fcport->port_name); 891 fcport->disc_state = DSC_LOGIN_PEND; 892 qla2x00_post_async_login_work(vha, fcport, NULL); 893 } 894 895 break; 896 897 case DSC_LOGIN_FAILED: 898 ql_dbg(ql_dbg_disc, vha, 0xffff, 899 "%s %d %8phC post gidpn \n", 900 __func__, __LINE__, fcport->port_name); 901 902 qla24xx_post_gidpn_work(vha, fcport); 903 break; 904 905 case DSC_LOGIN_COMPLETE: 906 /* recheck login state */ 907 ql_dbg(ql_dbg_disc, vha, 0xffff, 908 "%s %d %8phC post gpdb \n", 909 __func__, __LINE__, fcport->port_name); 910 911 qla24xx_post_gpdb_work(vha, fcport, PDO_FORCE_ADISC); 912 break; 913 914 default: 915 break; 916 } 917 918 return 0; 919 } 920 921 static 922 void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea) 923 { 924 fcport->rscn_gen++; 925 926 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff, 927 "%s %8phC DS %d LS %d\n", 928 __func__, fcport->port_name, fcport->disc_state, 929 fcport->fw_login_state); 930 931 if (fcport->flags & FCF_ASYNC_SENT) 932 return; 933 934 switch (fcport->disc_state) { 935 case DSC_DELETED: 936 case DSC_LOGIN_COMPLETE: 937 qla24xx_post_gidpn_work(fcport->vha, fcport); 938 break; 939 940 default: 941 break; 942 } 943 } 944 945 int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id, 946 u8 *port_name, void *pla) 947 { 948 struct qla_work_evt *e; 949 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS); 950 if (!e) 951 return QLA_FUNCTION_FAILED; 952 953 e->u.new_sess.id = *id; 954 e->u.new_sess.pla = pla; 955 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE); 956 957 return qla2x00_post_work(vha, e); 958 } 959 960 static 961 int qla24xx_handle_delete_done_event(scsi_qla_host_t *vha, 962 struct event_arg *ea) 963 { 964 fc_port_t *fcport = ea->fcport; 965 966 if (test_bit(UNLOADING, &vha->dpc_flags)) 967 return 0; 968 969 switch (vha->host->active_mode) { 970 case MODE_INITIATOR: 971 case MODE_DUAL: 972 if (fcport->scan_state == QLA_FCPORT_FOUND) 973 qla24xx_fcport_handle_login(vha, fcport); 974 break; 975 976 case MODE_TARGET: 977 default: 978 /* no-op */ 979 break; 980 } 981 982 return 0; 983 } 984 985 static 986 void qla24xx_handle_relogin_event(scsi_qla_host_t *vha, 987 struct event_arg *ea) 988 { 989 fc_port_t *fcport = ea->fcport; 990 991 if (fcport->scan_state != QLA_FCPORT_FOUND) { 992 fcport->login_retry++; 993 return; 994 } 995 996 ql_dbg(ql_dbg_disc, vha, 0xffff, 997 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n", 998 __func__, fcport->port_name, fcport->disc_state, 999 fcport->fw_login_state, fcport->login_pause, 1000 fcport->deleted, fcport->conflict, 1001 fcport->last_rscn_gen, fcport->rscn_gen, 1002 fcport->last_login_gen, fcport->login_gen, 1003 fcport->flags); 1004 1005 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) || 1006 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) 1007 return; 1008 1009 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) { 1010 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) 1011 return; 1012 } 1013 1014 if (fcport->flags & FCF_ASYNC_SENT) { 1015 fcport->login_retry++; 1016 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1017 return; 1018 } 1019 1020 if (fcport->disc_state == DSC_DELETE_PEND) { 1021 fcport->login_retry++; 1022 return; 1023 } 1024 1025 if (fcport->last_rscn_gen != fcport->rscn_gen) { 1026 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC post gidpn\n", 1027 __func__, __LINE__, fcport->port_name); 1028 1029 qla24xx_async_gidpn(vha, fcport); 1030 return; 1031 } 1032 1033 qla24xx_fcport_handle_login(vha, fcport); 1034 } 1035 1036 void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea) 1037 { 1038 fc_port_t *fcport, *f, *tf; 1039 uint32_t id = 0, mask, rid; 1040 int rc; 1041 1042 switch (ea->event) { 1043 case FCME_RELOGIN: 1044 if (test_bit(UNLOADING, &vha->dpc_flags)) 1045 return; 1046 1047 qla24xx_handle_relogin_event(vha, ea); 1048 break; 1049 case FCME_RSCN: 1050 if (test_bit(UNLOADING, &vha->dpc_flags)) 1051 return; 1052 switch (ea->id.b.rsvd_1) { 1053 case RSCN_PORT_ADDR: 1054 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1); 1055 if (!fcport) { 1056 /* cable moved */ 1057 rc = qla24xx_post_gpnid_work(vha, &ea->id); 1058 if (rc) { 1059 ql_log(ql_log_warn, vha, 0xffff, 1060 "RSCN GPNID work failed %02x%02x%02x\n", 1061 ea->id.b.domain, ea->id.b.area, 1062 ea->id.b.al_pa); 1063 } 1064 } else { 1065 ea->fcport = fcport; 1066 qla24xx_handle_rscn_event(fcport, ea); 1067 } 1068 break; 1069 case RSCN_AREA_ADDR: 1070 case RSCN_DOM_ADDR: 1071 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) { 1072 mask = 0xffff00; 1073 ql_log(ql_dbg_async, vha, 0xffff, 1074 "RSCN: Area 0x%06x was affected\n", 1075 ea->id.b24); 1076 } else { 1077 mask = 0xff0000; 1078 ql_log(ql_dbg_async, vha, 0xffff, 1079 "RSCN: Domain 0x%06x was affected\n", 1080 ea->id.b24); 1081 } 1082 1083 rid = ea->id.b24 & mask; 1084 list_for_each_entry_safe(f, tf, &vha->vp_fcports, 1085 list) { 1086 id = f->d_id.b24 & mask; 1087 if (rid == id) { 1088 ea->fcport = f; 1089 qla24xx_handle_rscn_event(f, ea); 1090 } 1091 } 1092 break; 1093 case RSCN_FAB_ADDR: 1094 default: 1095 ql_log(ql_log_warn, vha, 0xffff, 1096 "RSCN: Fabric was affected. Addr format %d\n", 1097 ea->id.b.rsvd_1); 1098 qla2x00_mark_all_devices_lost(vha, 1); 1099 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 1100 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 1101 } 1102 break; 1103 case FCME_GIDPN_DONE: 1104 qla24xx_handle_gidpn_event(vha, ea); 1105 break; 1106 case FCME_GNL_DONE: 1107 qla24xx_handle_gnl_done_event(vha, ea); 1108 break; 1109 case FCME_GPSC_DONE: 1110 qla24xx_post_upd_fcport_work(vha, ea->fcport); 1111 break; 1112 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */ 1113 qla24xx_handle_plogi_done_event(vha, ea); 1114 break; 1115 case FCME_GPDB_DONE: 1116 qla24xx_handle_gpdb_event(vha, ea); 1117 break; 1118 case FCME_GPNID_DONE: 1119 qla24xx_handle_gpnid_event(vha, ea); 1120 break; 1121 case FCME_DELETE_DONE: 1122 qla24xx_handle_delete_done_event(vha, ea); 1123 break; 1124 default: 1125 BUG_ON(1); 1126 break; 1127 } 1128 } 1129 1130 static void 1131 qla2x00_tmf_iocb_timeout(void *data) 1132 { 1133 srb_t *sp = data; 1134 struct srb_iocb *tmf = &sp->u.iocb_cmd; 1135 1136 tmf->u.tmf.comp_status = CS_TIMEOUT; 1137 complete(&tmf->u.tmf.comp); 1138 } 1139 1140 static void 1141 qla2x00_tmf_sp_done(void *ptr, int res) 1142 { 1143 srb_t *sp = ptr; 1144 struct srb_iocb *tmf = &sp->u.iocb_cmd; 1145 1146 complete(&tmf->u.tmf.comp); 1147 } 1148 1149 int 1150 qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun, 1151 uint32_t tag) 1152 { 1153 struct scsi_qla_host *vha = fcport->vha; 1154 struct srb_iocb *tm_iocb; 1155 srb_t *sp; 1156 int rval = QLA_FUNCTION_FAILED; 1157 1158 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1159 if (!sp) 1160 goto done; 1161 1162 tm_iocb = &sp->u.iocb_cmd; 1163 sp->type = SRB_TM_CMD; 1164 sp->name = "tmf"; 1165 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)); 1166 tm_iocb->u.tmf.flags = flags; 1167 tm_iocb->u.tmf.lun = lun; 1168 tm_iocb->u.tmf.data = tag; 1169 sp->done = qla2x00_tmf_sp_done; 1170 tm_iocb->timeout = qla2x00_tmf_iocb_timeout; 1171 init_completion(&tm_iocb->u.tmf.comp); 1172 1173 rval = qla2x00_start_sp(sp); 1174 if (rval != QLA_SUCCESS) 1175 goto done_free_sp; 1176 1177 ql_dbg(ql_dbg_taskm, vha, 0x802f, 1178 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 1179 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 1180 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1181 1182 wait_for_completion(&tm_iocb->u.tmf.comp); 1183 1184 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ? 1185 QLA_SUCCESS : QLA_FUNCTION_FAILED; 1186 1187 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) { 1188 ql_dbg(ql_dbg_taskm, vha, 0x8030, 1189 "TM IOCB failed (%x).\n", rval); 1190 } 1191 1192 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) { 1193 flags = tm_iocb->u.tmf.flags; 1194 lun = (uint16_t)tm_iocb->u.tmf.lun; 1195 1196 /* Issue Marker IOCB */ 1197 qla2x00_marker(vha, vha->hw->req_q_map[0], 1198 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun, 1199 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID); 1200 } 1201 1202 done_free_sp: 1203 sp->free(sp); 1204 done: 1205 return rval; 1206 } 1207 1208 static void 1209 qla24xx_abort_iocb_timeout(void *data) 1210 { 1211 srb_t *sp = data; 1212 struct srb_iocb *abt = &sp->u.iocb_cmd; 1213 1214 abt->u.abt.comp_status = CS_TIMEOUT; 1215 complete(&abt->u.abt.comp); 1216 } 1217 1218 static void 1219 qla24xx_abort_sp_done(void *ptr, int res) 1220 { 1221 srb_t *sp = ptr; 1222 struct srb_iocb *abt = &sp->u.iocb_cmd; 1223 1224 complete(&abt->u.abt.comp); 1225 } 1226 1227 int 1228 qla24xx_async_abort_cmd(srb_t *cmd_sp) 1229 { 1230 scsi_qla_host_t *vha = cmd_sp->vha; 1231 fc_port_t *fcport = cmd_sp->fcport; 1232 struct srb_iocb *abt_iocb; 1233 srb_t *sp; 1234 int rval = QLA_FUNCTION_FAILED; 1235 1236 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1237 if (!sp) 1238 goto done; 1239 1240 abt_iocb = &sp->u.iocb_cmd; 1241 sp->type = SRB_ABT_CMD; 1242 sp->name = "abort"; 1243 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)); 1244 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle; 1245 sp->done = qla24xx_abort_sp_done; 1246 abt_iocb->timeout = qla24xx_abort_iocb_timeout; 1247 init_completion(&abt_iocb->u.abt.comp); 1248 1249 rval = qla2x00_start_sp(sp); 1250 if (rval != QLA_SUCCESS) 1251 goto done_free_sp; 1252 1253 ql_dbg(ql_dbg_async, vha, 0x507c, 1254 "Abort command issued - hdl=%x, target_id=%x\n", 1255 cmd_sp->handle, fcport->tgt_id); 1256 1257 wait_for_completion(&abt_iocb->u.abt.comp); 1258 1259 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ? 1260 QLA_SUCCESS : QLA_FUNCTION_FAILED; 1261 1262 done_free_sp: 1263 sp->free(sp); 1264 done: 1265 return rval; 1266 } 1267 1268 int 1269 qla24xx_async_abort_command(srb_t *sp) 1270 { 1271 unsigned long flags = 0; 1272 1273 uint32_t handle; 1274 fc_port_t *fcport = sp->fcport; 1275 struct scsi_qla_host *vha = fcport->vha; 1276 struct qla_hw_data *ha = vha->hw; 1277 struct req_que *req = vha->req; 1278 1279 spin_lock_irqsave(&ha->hardware_lock, flags); 1280 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 1281 if (req->outstanding_cmds[handle] == sp) 1282 break; 1283 } 1284 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1285 if (handle == req->num_outstanding_cmds) { 1286 /* Command not found. */ 1287 return QLA_FUNCTION_FAILED; 1288 } 1289 if (sp->type == SRB_FXIOCB_DCMD) 1290 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport, 1291 FXDISC_ABORT_IOCTL); 1292 1293 return qla24xx_async_abort_cmd(sp); 1294 } 1295 1296 static void 1297 qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea) 1298 { 1299 port_id_t cid; /* conflict Nport id */ 1300 1301 switch (ea->data[0]) { 1302 case MBS_COMMAND_COMPLETE: 1303 /* 1304 * Driver must validate login state - If PRLI not complete, 1305 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI 1306 * requests. 1307 */ 1308 ql_dbg(ql_dbg_disc, vha, 0xffff, 1309 "%s %d %8phC post gpdb\n", 1310 __func__, __LINE__, ea->fcport->port_name); 1311 ea->fcport->chip_reset = vha->hw->chip_reset; 1312 ea->fcport->logout_on_delete = 1; 1313 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 1314 break; 1315 case MBS_COMMAND_ERROR: 1316 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC cmd error %x\n", 1317 __func__, __LINE__, ea->fcport->port_name, ea->data[1]); 1318 1319 ea->fcport->flags &= ~FCF_ASYNC_SENT; 1320 ea->fcport->disc_state = DSC_LOGIN_FAILED; 1321 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED) 1322 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1323 else 1324 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0); 1325 break; 1326 case MBS_LOOP_ID_USED: 1327 /* data[1] = IO PARAM 1 = nport ID */ 1328 cid.b.domain = (ea->iop[1] >> 16) & 0xff; 1329 cid.b.area = (ea->iop[1] >> 8) & 0xff; 1330 cid.b.al_pa = ea->iop[1] & 0xff; 1331 cid.b.rsvd_1 = 0; 1332 1333 ql_dbg(ql_dbg_disc, vha, 0xffff, 1334 "%s %d %8phC LoopID 0x%x in use post gnl\n", 1335 __func__, __LINE__, ea->fcport->port_name, 1336 ea->fcport->loop_id); 1337 1338 if (IS_SW_RESV_ADDR(cid)) { 1339 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map); 1340 ea->fcport->loop_id = FC_NO_LOOP_ID; 1341 } else { 1342 qla2x00_clear_loop_id(ea->fcport); 1343 } 1344 qla24xx_post_gnl_work(vha, ea->fcport); 1345 break; 1346 case MBS_PORT_ID_USED: 1347 ql_dbg(ql_dbg_disc, vha, 0xffff, 1348 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n", 1349 __func__, __LINE__, ea->fcport->port_name, 1350 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area, 1351 ea->fcport->d_id.b.al_pa); 1352 1353 qla2x00_clear_loop_id(ea->fcport); 1354 qla24xx_post_gidpn_work(vha, ea->fcport); 1355 break; 1356 } 1357 return; 1358 } 1359 1360 void 1361 qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport, 1362 uint16_t *data) 1363 { 1364 qla2x00_mark_device_lost(vha, fcport, 1, 0); 1365 qlt_logo_completion_handler(fcport, data[0]); 1366 fcport->login_gen++; 1367 return; 1368 } 1369 1370 void 1371 qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport, 1372 uint16_t *data) 1373 { 1374 if (data[0] == MBS_COMMAND_COMPLETE) { 1375 qla2x00_update_fcport(vha, fcport); 1376 1377 return; 1378 } 1379 1380 /* Retry login. */ 1381 fcport->flags &= ~FCF_ASYNC_SENT; 1382 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 1383 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1384 else 1385 qla2x00_mark_device_lost(vha, fcport, 1, 0); 1386 1387 return; 1388 } 1389 1390 /****************************************************************************/ 1391 /* QLogic ISP2x00 Hardware Support Functions. */ 1392 /****************************************************************************/ 1393 1394 static int 1395 qla83xx_nic_core_fw_load(scsi_qla_host_t *vha) 1396 { 1397 int rval = QLA_SUCCESS; 1398 struct qla_hw_data *ha = vha->hw; 1399 uint32_t idc_major_ver, idc_minor_ver; 1400 uint16_t config[4]; 1401 1402 qla83xx_idc_lock(vha, 0); 1403 1404 /* SV: TODO: Assign initialization timeout from 1405 * flash-info / other param 1406 */ 1407 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT; 1408 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT; 1409 1410 /* Set our fcoe function presence */ 1411 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) { 1412 ql_dbg(ql_dbg_p3p, vha, 0xb077, 1413 "Error while setting DRV-Presence.\n"); 1414 rval = QLA_FUNCTION_FAILED; 1415 goto exit; 1416 } 1417 1418 /* Decide the reset ownership */ 1419 qla83xx_reset_ownership(vha); 1420 1421 /* 1422 * On first protocol driver load: 1423 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery 1424 * register. 1425 * Others: Check compatibility with current IDC Major version. 1426 */ 1427 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver); 1428 if (ha->flags.nic_core_reset_owner) { 1429 /* Set IDC Major version */ 1430 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION; 1431 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver); 1432 1433 /* Clearing IDC-Lock-Recovery register */ 1434 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0); 1435 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) { 1436 /* 1437 * Clear further IDC participation if we are not compatible with 1438 * the current IDC Major Version. 1439 */ 1440 ql_log(ql_log_warn, vha, 0xb07d, 1441 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n", 1442 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION); 1443 __qla83xx_clear_drv_presence(vha); 1444 rval = QLA_FUNCTION_FAILED; 1445 goto exit; 1446 } 1447 /* Each function sets its supported Minor version. */ 1448 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver); 1449 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2)); 1450 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver); 1451 1452 if (ha->flags.nic_core_reset_owner) { 1453 memset(config, 0, sizeof(config)); 1454 if (!qla81xx_get_port_config(vha, config)) 1455 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 1456 QLA8XXX_DEV_READY); 1457 } 1458 1459 rval = qla83xx_idc_state_handler(vha); 1460 1461 exit: 1462 qla83xx_idc_unlock(vha, 0); 1463 1464 return rval; 1465 } 1466 1467 /* 1468 * qla2x00_initialize_adapter 1469 * Initialize board. 1470 * 1471 * Input: 1472 * ha = adapter block pointer. 1473 * 1474 * Returns: 1475 * 0 = success 1476 */ 1477 int 1478 qla2x00_initialize_adapter(scsi_qla_host_t *vha) 1479 { 1480 int rval; 1481 struct qla_hw_data *ha = vha->hw; 1482 struct req_que *req = ha->req_q_map[0]; 1483 1484 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats)); 1485 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat)); 1486 1487 /* Clear adapter flags. */ 1488 vha->flags.online = 0; 1489 ha->flags.chip_reset_done = 0; 1490 vha->flags.reset_active = 0; 1491 ha->flags.pci_channel_io_perm_failure = 0; 1492 ha->flags.eeh_busy = 0; 1493 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64(); 1494 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1495 atomic_set(&vha->loop_state, LOOP_DOWN); 1496 vha->device_flags = DFLG_NO_CABLE; 1497 vha->dpc_flags = 0; 1498 vha->flags.management_server_logged_in = 0; 1499 vha->marker_needed = 0; 1500 ha->isp_abort_cnt = 0; 1501 ha->beacon_blink_led = 0; 1502 1503 set_bit(0, ha->req_qid_map); 1504 set_bit(0, ha->rsp_qid_map); 1505 1506 ql_dbg(ql_dbg_init, vha, 0x0040, 1507 "Configuring PCI space...\n"); 1508 rval = ha->isp_ops->pci_config(vha); 1509 if (rval) { 1510 ql_log(ql_log_warn, vha, 0x0044, 1511 "Unable to configure PCI space.\n"); 1512 return (rval); 1513 } 1514 1515 ha->isp_ops->reset_chip(vha); 1516 1517 rval = qla2xxx_get_flash_info(vha); 1518 if (rval) { 1519 ql_log(ql_log_fatal, vha, 0x004f, 1520 "Unable to validate FLASH data.\n"); 1521 return rval; 1522 } 1523 1524 if (IS_QLA8044(ha)) { 1525 qla8044_read_reset_template(vha); 1526 1527 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0. 1528 * If DONRESET_BIT0 is set, drivers should not set dev_state 1529 * to NEED_RESET. But if NEED_RESET is set, drivers should 1530 * should honor the reset. */ 1531 if (ql2xdontresethba == 1) 1532 qla8044_set_idc_dontreset(vha); 1533 } 1534 1535 ha->isp_ops->get_flash_version(vha, req->ring); 1536 ql_dbg(ql_dbg_init, vha, 0x0061, 1537 "Configure NVRAM parameters...\n"); 1538 1539 ha->isp_ops->nvram_config(vha); 1540 1541 if (ha->flags.disable_serdes) { 1542 /* Mask HBA via NVRAM settings? */ 1543 ql_log(ql_log_info, vha, 0x0077, 1544 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name); 1545 return QLA_FUNCTION_FAILED; 1546 } 1547 1548 ql_dbg(ql_dbg_init, vha, 0x0078, 1549 "Verifying loaded RISC code...\n"); 1550 1551 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) { 1552 rval = ha->isp_ops->chip_diag(vha); 1553 if (rval) 1554 return (rval); 1555 rval = qla2x00_setup_chip(vha); 1556 if (rval) 1557 return (rval); 1558 } 1559 1560 if (IS_QLA84XX(ha)) { 1561 ha->cs84xx = qla84xx_get_chip(vha); 1562 if (!ha->cs84xx) { 1563 ql_log(ql_log_warn, vha, 0x00d0, 1564 "Unable to configure ISP84XX.\n"); 1565 return QLA_FUNCTION_FAILED; 1566 } 1567 } 1568 1569 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha)) 1570 rval = qla2x00_init_rings(vha); 1571 1572 ha->flags.chip_reset_done = 1; 1573 1574 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) { 1575 /* Issue verify 84xx FW IOCB to complete 84xx initialization */ 1576 rval = qla84xx_init_chip(vha); 1577 if (rval != QLA_SUCCESS) { 1578 ql_log(ql_log_warn, vha, 0x00d4, 1579 "Unable to initialize ISP84XX.\n"); 1580 qla84xx_put_chip(vha); 1581 } 1582 } 1583 1584 /* Load the NIC Core f/w if we are the first protocol driver. */ 1585 if (IS_QLA8031(ha)) { 1586 rval = qla83xx_nic_core_fw_load(vha); 1587 if (rval) 1588 ql_log(ql_log_warn, vha, 0x0124, 1589 "Error in initializing NIC Core f/w.\n"); 1590 } 1591 1592 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)) 1593 qla24xx_read_fcp_prio_cfg(vha); 1594 1595 if (IS_P3P_TYPE(ha)) 1596 qla82xx_set_driver_version(vha, QLA2XXX_VERSION); 1597 else 1598 qla25xx_set_driver_version(vha, QLA2XXX_VERSION); 1599 1600 return (rval); 1601 } 1602 1603 /** 1604 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers. 1605 * @ha: HA context 1606 * 1607 * Returns 0 on success. 1608 */ 1609 int 1610 qla2100_pci_config(scsi_qla_host_t *vha) 1611 { 1612 uint16_t w; 1613 unsigned long flags; 1614 struct qla_hw_data *ha = vha->hw; 1615 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1616 1617 pci_set_master(ha->pdev); 1618 pci_try_set_mwi(ha->pdev); 1619 1620 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 1621 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 1622 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 1623 1624 pci_disable_rom(ha->pdev); 1625 1626 /* Get PCI bus information. */ 1627 spin_lock_irqsave(&ha->hardware_lock, flags); 1628 ha->pci_attr = RD_REG_WORD(®->ctrl_status); 1629 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1630 1631 return QLA_SUCCESS; 1632 } 1633 1634 /** 1635 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers. 1636 * @ha: HA context 1637 * 1638 * Returns 0 on success. 1639 */ 1640 int 1641 qla2300_pci_config(scsi_qla_host_t *vha) 1642 { 1643 uint16_t w; 1644 unsigned long flags = 0; 1645 uint32_t cnt; 1646 struct qla_hw_data *ha = vha->hw; 1647 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1648 1649 pci_set_master(ha->pdev); 1650 pci_try_set_mwi(ha->pdev); 1651 1652 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 1653 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 1654 1655 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 1656 w &= ~PCI_COMMAND_INTX_DISABLE; 1657 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 1658 1659 /* 1660 * If this is a 2300 card and not 2312, reset the 1661 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately, 1662 * the 2310 also reports itself as a 2300 so we need to get the 1663 * fb revision level -- a 6 indicates it really is a 2300 and 1664 * not a 2310. 1665 */ 1666 if (IS_QLA2300(ha)) { 1667 spin_lock_irqsave(&ha->hardware_lock, flags); 1668 1669 /* Pause RISC. */ 1670 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 1671 for (cnt = 0; cnt < 30000; cnt++) { 1672 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) 1673 break; 1674 1675 udelay(10); 1676 } 1677 1678 /* Select FPM registers. */ 1679 WRT_REG_WORD(®->ctrl_status, 0x20); 1680 RD_REG_WORD(®->ctrl_status); 1681 1682 /* Get the fb rev level */ 1683 ha->fb_rev = RD_FB_CMD_REG(ha, reg); 1684 1685 if (ha->fb_rev == FPM_2300) 1686 pci_clear_mwi(ha->pdev); 1687 1688 /* Deselect FPM registers. */ 1689 WRT_REG_WORD(®->ctrl_status, 0x0); 1690 RD_REG_WORD(®->ctrl_status); 1691 1692 /* Release RISC module. */ 1693 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 1694 for (cnt = 0; cnt < 30000; cnt++) { 1695 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0) 1696 break; 1697 1698 udelay(10); 1699 } 1700 1701 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1702 } 1703 1704 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 1705 1706 pci_disable_rom(ha->pdev); 1707 1708 /* Get PCI bus information. */ 1709 spin_lock_irqsave(&ha->hardware_lock, flags); 1710 ha->pci_attr = RD_REG_WORD(®->ctrl_status); 1711 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1712 1713 return QLA_SUCCESS; 1714 } 1715 1716 /** 1717 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers. 1718 * @ha: HA context 1719 * 1720 * Returns 0 on success. 1721 */ 1722 int 1723 qla24xx_pci_config(scsi_qla_host_t *vha) 1724 { 1725 uint16_t w; 1726 unsigned long flags = 0; 1727 struct qla_hw_data *ha = vha->hw; 1728 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1729 1730 pci_set_master(ha->pdev); 1731 pci_try_set_mwi(ha->pdev); 1732 1733 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 1734 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 1735 w &= ~PCI_COMMAND_INTX_DISABLE; 1736 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 1737 1738 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 1739 1740 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ 1741 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) 1742 pcix_set_mmrbc(ha->pdev, 2048); 1743 1744 /* PCIe -- adjust Maximum Read Request Size (2048). */ 1745 if (pci_is_pcie(ha->pdev)) 1746 pcie_set_readrq(ha->pdev, 4096); 1747 1748 pci_disable_rom(ha->pdev); 1749 1750 ha->chip_revision = ha->pdev->revision; 1751 1752 /* Get PCI bus information. */ 1753 spin_lock_irqsave(&ha->hardware_lock, flags); 1754 ha->pci_attr = RD_REG_DWORD(®->ctrl_status); 1755 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1756 1757 return QLA_SUCCESS; 1758 } 1759 1760 /** 1761 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. 1762 * @ha: HA context 1763 * 1764 * Returns 0 on success. 1765 */ 1766 int 1767 qla25xx_pci_config(scsi_qla_host_t *vha) 1768 { 1769 uint16_t w; 1770 struct qla_hw_data *ha = vha->hw; 1771 1772 pci_set_master(ha->pdev); 1773 pci_try_set_mwi(ha->pdev); 1774 1775 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 1776 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 1777 w &= ~PCI_COMMAND_INTX_DISABLE; 1778 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 1779 1780 /* PCIe -- adjust Maximum Read Request Size (2048). */ 1781 if (pci_is_pcie(ha->pdev)) 1782 pcie_set_readrq(ha->pdev, 4096); 1783 1784 pci_disable_rom(ha->pdev); 1785 1786 ha->chip_revision = ha->pdev->revision; 1787 1788 return QLA_SUCCESS; 1789 } 1790 1791 /** 1792 * qla2x00_isp_firmware() - Choose firmware image. 1793 * @ha: HA context 1794 * 1795 * Returns 0 on success. 1796 */ 1797 static int 1798 qla2x00_isp_firmware(scsi_qla_host_t *vha) 1799 { 1800 int rval; 1801 uint16_t loop_id, topo, sw_cap; 1802 uint8_t domain, area, al_pa; 1803 struct qla_hw_data *ha = vha->hw; 1804 1805 /* Assume loading risc code */ 1806 rval = QLA_FUNCTION_FAILED; 1807 1808 if (ha->flags.disable_risc_code_load) { 1809 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n"); 1810 1811 /* Verify checksum of loaded RISC code. */ 1812 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address); 1813 if (rval == QLA_SUCCESS) { 1814 /* And, verify we are not in ROM code. */ 1815 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa, 1816 &area, &domain, &topo, &sw_cap); 1817 } 1818 } 1819 1820 if (rval) 1821 ql_dbg(ql_dbg_init, vha, 0x007a, 1822 "**** Load RISC code ****.\n"); 1823 1824 return (rval); 1825 } 1826 1827 /** 1828 * qla2x00_reset_chip() - Reset ISP chip. 1829 * @ha: HA context 1830 * 1831 * Returns 0 on success. 1832 */ 1833 void 1834 qla2x00_reset_chip(scsi_qla_host_t *vha) 1835 { 1836 unsigned long flags = 0; 1837 struct qla_hw_data *ha = vha->hw; 1838 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1839 uint32_t cnt; 1840 uint16_t cmd; 1841 1842 if (unlikely(pci_channel_offline(ha->pdev))) 1843 return; 1844 1845 ha->isp_ops->disable_intrs(ha); 1846 1847 spin_lock_irqsave(&ha->hardware_lock, flags); 1848 1849 /* Turn off master enable */ 1850 cmd = 0; 1851 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd); 1852 cmd &= ~PCI_COMMAND_MASTER; 1853 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 1854 1855 if (!IS_QLA2100(ha)) { 1856 /* Pause RISC. */ 1857 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 1858 if (IS_QLA2200(ha) || IS_QLA2300(ha)) { 1859 for (cnt = 0; cnt < 30000; cnt++) { 1860 if ((RD_REG_WORD(®->hccr) & 1861 HCCR_RISC_PAUSE) != 0) 1862 break; 1863 udelay(100); 1864 } 1865 } else { 1866 RD_REG_WORD(®->hccr); /* PCI Posting. */ 1867 udelay(10); 1868 } 1869 1870 /* Select FPM registers. */ 1871 WRT_REG_WORD(®->ctrl_status, 0x20); 1872 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1873 1874 /* FPM Soft Reset. */ 1875 WRT_REG_WORD(®->fpm_diag_config, 0x100); 1876 RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ 1877 1878 /* Toggle Fpm Reset. */ 1879 if (!IS_QLA2200(ha)) { 1880 WRT_REG_WORD(®->fpm_diag_config, 0x0); 1881 RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ 1882 } 1883 1884 /* Select frame buffer registers. */ 1885 WRT_REG_WORD(®->ctrl_status, 0x10); 1886 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1887 1888 /* Reset frame buffer FIFOs. */ 1889 if (IS_QLA2200(ha)) { 1890 WRT_FB_CMD_REG(ha, reg, 0xa000); 1891 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ 1892 } else { 1893 WRT_FB_CMD_REG(ha, reg, 0x00fc); 1894 1895 /* Read back fb_cmd until zero or 3 seconds max */ 1896 for (cnt = 0; cnt < 3000; cnt++) { 1897 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) 1898 break; 1899 udelay(100); 1900 } 1901 } 1902 1903 /* Select RISC module registers. */ 1904 WRT_REG_WORD(®->ctrl_status, 0); 1905 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1906 1907 /* Reset RISC processor. */ 1908 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 1909 RD_REG_WORD(®->hccr); /* PCI Posting. */ 1910 1911 /* Release RISC processor. */ 1912 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 1913 RD_REG_WORD(®->hccr); /* PCI Posting. */ 1914 } 1915 1916 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 1917 WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT); 1918 1919 /* Reset ISP chip. */ 1920 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 1921 1922 /* Wait for RISC to recover from reset. */ 1923 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 1924 /* 1925 * It is necessary to for a delay here since the card doesn't 1926 * respond to PCI reads during a reset. On some architectures 1927 * this will result in an MCA. 1928 */ 1929 udelay(20); 1930 for (cnt = 30000; cnt; cnt--) { 1931 if ((RD_REG_WORD(®->ctrl_status) & 1932 CSR_ISP_SOFT_RESET) == 0) 1933 break; 1934 udelay(100); 1935 } 1936 } else 1937 udelay(10); 1938 1939 /* Reset RISC processor. */ 1940 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 1941 1942 WRT_REG_WORD(®->semaphore, 0); 1943 1944 /* Release RISC processor. */ 1945 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 1946 RD_REG_WORD(®->hccr); /* PCI Posting. */ 1947 1948 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 1949 for (cnt = 0; cnt < 30000; cnt++) { 1950 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) 1951 break; 1952 1953 udelay(100); 1954 } 1955 } else 1956 udelay(100); 1957 1958 /* Turn on master enable */ 1959 cmd |= PCI_COMMAND_MASTER; 1960 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 1961 1962 /* Disable RISC pause on FPM parity error. */ 1963 if (!IS_QLA2100(ha)) { 1964 WRT_REG_WORD(®->hccr, HCCR_DISABLE_PARITY_PAUSE); 1965 RD_REG_WORD(®->hccr); /* PCI Posting. */ 1966 } 1967 1968 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1969 } 1970 1971 /** 1972 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC. 1973 * 1974 * Returns 0 on success. 1975 */ 1976 static int 1977 qla81xx_reset_mpi(scsi_qla_host_t *vha) 1978 { 1979 uint16_t mb[4] = {0x1010, 0, 1, 0}; 1980 1981 if (!IS_QLA81XX(vha->hw)) 1982 return QLA_SUCCESS; 1983 1984 return qla81xx_write_mpi_register(vha, mb); 1985 } 1986 1987 /** 1988 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. 1989 * @ha: HA context 1990 * 1991 * Returns 0 on success. 1992 */ 1993 static inline int 1994 qla24xx_reset_risc(scsi_qla_host_t *vha) 1995 { 1996 unsigned long flags = 0; 1997 struct qla_hw_data *ha = vha->hw; 1998 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1999 uint32_t cnt; 2000 uint16_t wd; 2001 static int abts_cnt; /* ISP abort retry counts */ 2002 int rval = QLA_SUCCESS; 2003 2004 spin_lock_irqsave(&ha->hardware_lock, flags); 2005 2006 /* Reset RISC. */ 2007 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 2008 for (cnt = 0; cnt < 30000; cnt++) { 2009 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 2010 break; 2011 2012 udelay(10); 2013 } 2014 2015 if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) 2016 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); 2017 2018 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e, 2019 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n", 2020 RD_REG_DWORD(®->hccr), 2021 RD_REG_DWORD(®->ctrl_status), 2022 (RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)); 2023 2024 WRT_REG_DWORD(®->ctrl_status, 2025 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 2026 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2027 2028 udelay(100); 2029 2030 /* Wait for firmware to complete NVRAM accesses. */ 2031 RD_REG_WORD(®->mailbox0); 2032 for (cnt = 10000; RD_REG_WORD(®->mailbox0) != 0 && 2033 rval == QLA_SUCCESS; cnt--) { 2034 barrier(); 2035 if (cnt) 2036 udelay(5); 2037 else 2038 rval = QLA_FUNCTION_TIMEOUT; 2039 } 2040 2041 if (rval == QLA_SUCCESS) 2042 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags); 2043 2044 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f, 2045 "HCCR: 0x%x, MailBox0 Status 0x%x\n", 2046 RD_REG_DWORD(®->hccr), 2047 RD_REG_DWORD(®->mailbox0)); 2048 2049 /* Wait for soft-reset to complete. */ 2050 RD_REG_DWORD(®->ctrl_status); 2051 for (cnt = 0; cnt < 60; cnt++) { 2052 barrier(); 2053 if ((RD_REG_DWORD(®->ctrl_status) & 2054 CSRX_ISP_SOFT_RESET) == 0) 2055 break; 2056 2057 udelay(5); 2058 } 2059 if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) 2060 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags); 2061 2062 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d, 2063 "HCCR: 0x%x, Soft Reset status: 0x%x\n", 2064 RD_REG_DWORD(®->hccr), 2065 RD_REG_DWORD(®->ctrl_status)); 2066 2067 /* If required, do an MPI FW reset now */ 2068 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) { 2069 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) { 2070 if (++abts_cnt < 5) { 2071 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2072 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags); 2073 } else { 2074 /* 2075 * We exhausted the ISP abort retries. We have to 2076 * set the board offline. 2077 */ 2078 abts_cnt = 0; 2079 vha->flags.online = 0; 2080 } 2081 } 2082 } 2083 2084 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); 2085 RD_REG_DWORD(®->hccr); 2086 2087 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); 2088 RD_REG_DWORD(®->hccr); 2089 2090 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 2091 RD_REG_DWORD(®->hccr); 2092 2093 RD_REG_WORD(®->mailbox0); 2094 for (cnt = 60; RD_REG_WORD(®->mailbox0) != 0 && 2095 rval == QLA_SUCCESS; cnt--) { 2096 barrier(); 2097 if (cnt) 2098 udelay(5); 2099 else 2100 rval = QLA_FUNCTION_TIMEOUT; 2101 } 2102 if (rval == QLA_SUCCESS) 2103 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); 2104 2105 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e, 2106 "Host Risc 0x%x, mailbox0 0x%x\n", 2107 RD_REG_DWORD(®->hccr), 2108 RD_REG_WORD(®->mailbox0)); 2109 2110 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2111 2112 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f, 2113 "Driver in %s mode\n", 2114 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling"); 2115 2116 if (IS_NOPOLLING_TYPE(ha)) 2117 ha->isp_ops->enable_intrs(ha); 2118 2119 return rval; 2120 } 2121 2122 static void 2123 qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) 2124 { 2125 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 2126 2127 WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 2128 *data = RD_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET); 2129 2130 } 2131 2132 static void 2133 qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) 2134 { 2135 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 2136 2137 WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 2138 WRT_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET, data); 2139 } 2140 2141 static void 2142 qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) 2143 { 2144 uint32_t wd32 = 0; 2145 uint delta_msec = 100; 2146 uint elapsed_msec = 0; 2147 uint timeout_msec; 2148 ulong n; 2149 2150 if (vha->hw->pdev->subsystem_device != 0x0175 && 2151 vha->hw->pdev->subsystem_device != 0x0240) 2152 return; 2153 2154 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE); 2155 udelay(100); 2156 2157 attempt: 2158 timeout_msec = TIMEOUT_SEMAPHORE; 2159 n = timeout_msec / delta_msec; 2160 while (n--) { 2161 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET); 2162 qla25xx_read_risc_sema_reg(vha, &wd32); 2163 if (wd32 & RISC_SEMAPHORE) 2164 break; 2165 msleep(delta_msec); 2166 elapsed_msec += delta_msec; 2167 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 2168 goto force; 2169 } 2170 2171 if (!(wd32 & RISC_SEMAPHORE)) 2172 goto force; 2173 2174 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 2175 goto acquired; 2176 2177 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR); 2178 timeout_msec = TIMEOUT_SEMAPHORE_FORCE; 2179 n = timeout_msec / delta_msec; 2180 while (n--) { 2181 qla25xx_read_risc_sema_reg(vha, &wd32); 2182 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 2183 break; 2184 msleep(delta_msec); 2185 elapsed_msec += delta_msec; 2186 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 2187 goto force; 2188 } 2189 2190 if (wd32 & RISC_SEMAPHORE_FORCE) 2191 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR); 2192 2193 goto attempt; 2194 2195 force: 2196 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET); 2197 2198 acquired: 2199 return; 2200 } 2201 2202 /** 2203 * qla24xx_reset_chip() - Reset ISP24xx chip. 2204 * @ha: HA context 2205 * 2206 * Returns 0 on success. 2207 */ 2208 void 2209 qla24xx_reset_chip(scsi_qla_host_t *vha) 2210 { 2211 struct qla_hw_data *ha = vha->hw; 2212 2213 if (pci_channel_offline(ha->pdev) && 2214 ha->flags.pci_channel_io_perm_failure) { 2215 return; 2216 } 2217 2218 ha->isp_ops->disable_intrs(ha); 2219 2220 qla25xx_manipulate_risc_semaphore(vha); 2221 2222 /* Perform RISC reset. */ 2223 qla24xx_reset_risc(vha); 2224 } 2225 2226 /** 2227 * qla2x00_chip_diag() - Test chip for proper operation. 2228 * @ha: HA context 2229 * 2230 * Returns 0 on success. 2231 */ 2232 int 2233 qla2x00_chip_diag(scsi_qla_host_t *vha) 2234 { 2235 int rval; 2236 struct qla_hw_data *ha = vha->hw; 2237 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2238 unsigned long flags = 0; 2239 uint16_t data; 2240 uint32_t cnt; 2241 uint16_t mb[5]; 2242 struct req_que *req = ha->req_q_map[0]; 2243 2244 /* Assume a failed state */ 2245 rval = QLA_FUNCTION_FAILED; 2246 2247 ql_dbg(ql_dbg_init, vha, 0x007b, 2248 "Testing device at %lx.\n", (u_long)®->flash_address); 2249 2250 spin_lock_irqsave(&ha->hardware_lock, flags); 2251 2252 /* Reset ISP chip. */ 2253 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 2254 2255 /* 2256 * We need to have a delay here since the card will not respond while 2257 * in reset causing an MCA on some architectures. 2258 */ 2259 udelay(20); 2260 data = qla2x00_debounce_register(®->ctrl_status); 2261 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) { 2262 udelay(5); 2263 data = RD_REG_WORD(®->ctrl_status); 2264 barrier(); 2265 } 2266 2267 if (!cnt) 2268 goto chip_diag_failed; 2269 2270 ql_dbg(ql_dbg_init, vha, 0x007c, 2271 "Reset register cleared by chip reset.\n"); 2272 2273 /* Reset RISC processor. */ 2274 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 2275 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 2276 2277 /* Workaround for QLA2312 PCI parity error */ 2278 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2279 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); 2280 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) { 2281 udelay(5); 2282 data = RD_MAILBOX_REG(ha, reg, 0); 2283 barrier(); 2284 } 2285 } else 2286 udelay(10); 2287 2288 if (!cnt) 2289 goto chip_diag_failed; 2290 2291 /* Check product ID of chip */ 2292 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n"); 2293 2294 mb[1] = RD_MAILBOX_REG(ha, reg, 1); 2295 mb[2] = RD_MAILBOX_REG(ha, reg, 2); 2296 mb[3] = RD_MAILBOX_REG(ha, reg, 3); 2297 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); 2298 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) || 2299 mb[3] != PROD_ID_3) { 2300 ql_log(ql_log_warn, vha, 0x0062, 2301 "Wrong product ID = 0x%x,0x%x,0x%x.\n", 2302 mb[1], mb[2], mb[3]); 2303 2304 goto chip_diag_failed; 2305 } 2306 ha->product_id[0] = mb[1]; 2307 ha->product_id[1] = mb[2]; 2308 ha->product_id[2] = mb[3]; 2309 ha->product_id[3] = mb[4]; 2310 2311 /* Adjust fw RISC transfer size */ 2312 if (req->length > 1024) 2313 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; 2314 else 2315 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 2316 req->length; 2317 2318 if (IS_QLA2200(ha) && 2319 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { 2320 /* Limit firmware transfer size with a 2200A */ 2321 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n"); 2322 2323 ha->device_type |= DT_ISP2200A; 2324 ha->fw_transfer_size = 128; 2325 } 2326 2327 /* Wrap Incoming Mailboxes Test. */ 2328 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2329 2330 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n"); 2331 rval = qla2x00_mbx_reg_test(vha); 2332 if (rval) 2333 ql_log(ql_log_warn, vha, 0x0080, 2334 "Failed mailbox send register test.\n"); 2335 else 2336 /* Flag a successful rval */ 2337 rval = QLA_SUCCESS; 2338 spin_lock_irqsave(&ha->hardware_lock, flags); 2339 2340 chip_diag_failed: 2341 if (rval) 2342 ql_log(ql_log_info, vha, 0x0081, 2343 "Chip diagnostics **** FAILED ****.\n"); 2344 2345 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2346 2347 return (rval); 2348 } 2349 2350 /** 2351 * qla24xx_chip_diag() - Test ISP24xx for proper operation. 2352 * @ha: HA context 2353 * 2354 * Returns 0 on success. 2355 */ 2356 int 2357 qla24xx_chip_diag(scsi_qla_host_t *vha) 2358 { 2359 int rval; 2360 struct qla_hw_data *ha = vha->hw; 2361 struct req_que *req = ha->req_q_map[0]; 2362 2363 if (IS_P3P_TYPE(ha)) 2364 return QLA_SUCCESS; 2365 2366 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; 2367 2368 rval = qla2x00_mbx_reg_test(vha); 2369 if (rval) { 2370 ql_log(ql_log_warn, vha, 0x0082, 2371 "Failed mailbox send register test.\n"); 2372 } else { 2373 /* Flag a successful rval */ 2374 rval = QLA_SUCCESS; 2375 } 2376 2377 return rval; 2378 } 2379 2380 void 2381 qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) 2382 { 2383 int rval; 2384 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, 2385 eft_size, fce_size, mq_size; 2386 dma_addr_t tc_dma; 2387 void *tc; 2388 struct qla_hw_data *ha = vha->hw; 2389 struct req_que *req = ha->req_q_map[0]; 2390 struct rsp_que *rsp = ha->rsp_q_map[0]; 2391 2392 if (ha->fw_dump) { 2393 ql_dbg(ql_dbg_init, vha, 0x00bd, 2394 "Firmware dump already allocated.\n"); 2395 return; 2396 } 2397 2398 ha->fw_dumped = 0; 2399 ha->fw_dump_cap_flags = 0; 2400 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; 2401 req_q_size = rsp_q_size = 0; 2402 2403 if (IS_QLA27XX(ha)) 2404 goto try_fce; 2405 2406 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 2407 fixed_size = sizeof(struct qla2100_fw_dump); 2408 } else if (IS_QLA23XX(ha)) { 2409 fixed_size = offsetof(struct qla2300_fw_dump, data_ram); 2410 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 2411 sizeof(uint16_t); 2412 } else if (IS_FWI2_CAPABLE(ha)) { 2413 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2414 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem); 2415 else if (IS_QLA81XX(ha)) 2416 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); 2417 else if (IS_QLA25XX(ha)) 2418 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); 2419 else 2420 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); 2421 2422 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 2423 sizeof(uint32_t); 2424 if (ha->mqenable) { 2425 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha)) 2426 mq_size = sizeof(struct qla2xxx_mq_chain); 2427 /* 2428 * Allocate maximum buffer size for all queues. 2429 * Resizing must be done at end-of-dump processing. 2430 */ 2431 mq_size += ha->max_req_queues * 2432 (req->length * sizeof(request_t)); 2433 mq_size += ha->max_rsp_queues * 2434 (rsp->length * sizeof(response_t)); 2435 } 2436 if (ha->tgt.atio_ring) 2437 mq_size += ha->tgt.atio_q_length * sizeof(request_t); 2438 /* Allocate memory for Fibre Channel Event Buffer. */ 2439 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 2440 !IS_QLA27XX(ha)) 2441 goto try_eft; 2442 2443 try_fce: 2444 if (ha->fce) 2445 dma_free_coherent(&ha->pdev->dev, 2446 FCE_SIZE, ha->fce, ha->fce_dma); 2447 2448 /* Allocate memory for Fibre Channel Event Buffer. */ 2449 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, 2450 GFP_KERNEL); 2451 if (!tc) { 2452 ql_log(ql_log_warn, vha, 0x00be, 2453 "Unable to allocate (%d KB) for FCE.\n", 2454 FCE_SIZE / 1024); 2455 goto try_eft; 2456 } 2457 2458 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS, 2459 ha->fce_mb, &ha->fce_bufs); 2460 if (rval) { 2461 ql_log(ql_log_warn, vha, 0x00bf, 2462 "Unable to initialize FCE (%d).\n", rval); 2463 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc, 2464 tc_dma); 2465 ha->flags.fce_enabled = 0; 2466 goto try_eft; 2467 } 2468 ql_dbg(ql_dbg_init, vha, 0x00c0, 2469 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024); 2470 2471 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE; 2472 ha->flags.fce_enabled = 1; 2473 ha->fce_dma = tc_dma; 2474 ha->fce = tc; 2475 2476 try_eft: 2477 if (ha->eft) 2478 dma_free_coherent(&ha->pdev->dev, 2479 EFT_SIZE, ha->eft, ha->eft_dma); 2480 2481 /* Allocate memory for Extended Trace Buffer. */ 2482 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma, 2483 GFP_KERNEL); 2484 if (!tc) { 2485 ql_log(ql_log_warn, vha, 0x00c1, 2486 "Unable to allocate (%d KB) for EFT.\n", 2487 EFT_SIZE / 1024); 2488 goto cont_alloc; 2489 } 2490 2491 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS); 2492 if (rval) { 2493 ql_log(ql_log_warn, vha, 0x00c2, 2494 "Unable to initialize EFT (%d).\n", rval); 2495 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc, 2496 tc_dma); 2497 goto cont_alloc; 2498 } 2499 ql_dbg(ql_dbg_init, vha, 0x00c3, 2500 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024); 2501 2502 eft_size = EFT_SIZE; 2503 ha->eft_dma = tc_dma; 2504 ha->eft = tc; 2505 } 2506 2507 cont_alloc: 2508 if (IS_QLA27XX(ha)) { 2509 if (!ha->fw_dump_template) { 2510 ql_log(ql_log_warn, vha, 0x00ba, 2511 "Failed missing fwdump template\n"); 2512 return; 2513 } 2514 dump_size = qla27xx_fwdt_calculate_dump_size(vha); 2515 ql_dbg(ql_dbg_init, vha, 0x00fa, 2516 "-> allocating fwdump (%x bytes)...\n", dump_size); 2517 goto allocate; 2518 } 2519 2520 req_q_size = req->length * sizeof(request_t); 2521 rsp_q_size = rsp->length * sizeof(response_t); 2522 dump_size = offsetof(struct qla2xxx_fw_dump, isp); 2523 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size; 2524 ha->chain_offset = dump_size; 2525 dump_size += mq_size + fce_size; 2526 2527 allocate: 2528 ha->fw_dump = vmalloc(dump_size); 2529 if (!ha->fw_dump) { 2530 ql_log(ql_log_warn, vha, 0x00c4, 2531 "Unable to allocate (%d KB) for firmware dump.\n", 2532 dump_size / 1024); 2533 2534 if (ha->fce) { 2535 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, 2536 ha->fce_dma); 2537 ha->fce = NULL; 2538 ha->fce_dma = 0; 2539 } 2540 2541 if (ha->eft) { 2542 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft, 2543 ha->eft_dma); 2544 ha->eft = NULL; 2545 ha->eft_dma = 0; 2546 } 2547 return; 2548 } 2549 ha->fw_dump_len = dump_size; 2550 ql_dbg(ql_dbg_init, vha, 0x00c5, 2551 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024); 2552 2553 if (IS_QLA27XX(ha)) 2554 return; 2555 2556 ha->fw_dump->signature[0] = 'Q'; 2557 ha->fw_dump->signature[1] = 'L'; 2558 ha->fw_dump->signature[2] = 'G'; 2559 ha->fw_dump->signature[3] = 'C'; 2560 ha->fw_dump->version = htonl(1); 2561 2562 ha->fw_dump->fixed_size = htonl(fixed_size); 2563 ha->fw_dump->mem_size = htonl(mem_size); 2564 ha->fw_dump->req_q_size = htonl(req_q_size); 2565 ha->fw_dump->rsp_q_size = htonl(rsp_q_size); 2566 2567 ha->fw_dump->eft_size = htonl(eft_size); 2568 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma)); 2569 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma)); 2570 2571 ha->fw_dump->header_size = 2572 htonl(offsetof(struct qla2xxx_fw_dump, isp)); 2573 } 2574 2575 static int 2576 qla81xx_mpi_sync(scsi_qla_host_t *vha) 2577 { 2578 #define MPS_MASK 0xe0 2579 int rval; 2580 uint16_t dc; 2581 uint32_t dw; 2582 2583 if (!IS_QLA81XX(vha->hw)) 2584 return QLA_SUCCESS; 2585 2586 rval = qla2x00_write_ram_word(vha, 0x7c00, 1); 2587 if (rval != QLA_SUCCESS) { 2588 ql_log(ql_log_warn, vha, 0x0105, 2589 "Unable to acquire semaphore.\n"); 2590 goto done; 2591 } 2592 2593 pci_read_config_word(vha->hw->pdev, 0x54, &dc); 2594 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw); 2595 if (rval != QLA_SUCCESS) { 2596 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n"); 2597 goto done_release; 2598 } 2599 2600 dc &= MPS_MASK; 2601 if (dc == (dw & MPS_MASK)) 2602 goto done_release; 2603 2604 dw &= ~MPS_MASK; 2605 dw |= dc; 2606 rval = qla2x00_write_ram_word(vha, 0x7a15, dw); 2607 if (rval != QLA_SUCCESS) { 2608 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n"); 2609 } 2610 2611 done_release: 2612 rval = qla2x00_write_ram_word(vha, 0x7c00, 0); 2613 if (rval != QLA_SUCCESS) { 2614 ql_log(ql_log_warn, vha, 0x006d, 2615 "Unable to release semaphore.\n"); 2616 } 2617 2618 done: 2619 return rval; 2620 } 2621 2622 int 2623 qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req) 2624 { 2625 /* Don't try to reallocate the array */ 2626 if (req->outstanding_cmds) 2627 return QLA_SUCCESS; 2628 2629 if (!IS_FWI2_CAPABLE(ha)) 2630 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS; 2631 else { 2632 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count) 2633 req->num_outstanding_cmds = ha->cur_fw_xcb_count; 2634 else 2635 req->num_outstanding_cmds = ha->cur_fw_iocb_count; 2636 } 2637 2638 req->outstanding_cmds = kzalloc(sizeof(srb_t *) * 2639 req->num_outstanding_cmds, GFP_KERNEL); 2640 2641 if (!req->outstanding_cmds) { 2642 /* 2643 * Try to allocate a minimal size just so we can get through 2644 * initialization. 2645 */ 2646 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS; 2647 req->outstanding_cmds = kzalloc(sizeof(srb_t *) * 2648 req->num_outstanding_cmds, GFP_KERNEL); 2649 2650 if (!req->outstanding_cmds) { 2651 ql_log(ql_log_fatal, NULL, 0x0126, 2652 "Failed to allocate memory for " 2653 "outstanding_cmds for req_que %p.\n", req); 2654 req->num_outstanding_cmds = 0; 2655 return QLA_FUNCTION_FAILED; 2656 } 2657 } 2658 2659 return QLA_SUCCESS; 2660 } 2661 2662 /** 2663 * qla2x00_setup_chip() - Load and start RISC firmware. 2664 * @ha: HA context 2665 * 2666 * Returns 0 on success. 2667 */ 2668 static int 2669 qla2x00_setup_chip(scsi_qla_host_t *vha) 2670 { 2671 int rval; 2672 uint32_t srisc_address = 0; 2673 struct qla_hw_data *ha = vha->hw; 2674 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2675 unsigned long flags; 2676 uint16_t fw_major_version; 2677 2678 if (IS_P3P_TYPE(ha)) { 2679 rval = ha->isp_ops->load_risc(vha, &srisc_address); 2680 if (rval == QLA_SUCCESS) { 2681 qla2x00_stop_firmware(vha); 2682 goto enable_82xx_npiv; 2683 } else 2684 goto failed; 2685 } 2686 2687 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 2688 /* Disable SRAM, Instruction RAM and GP RAM parity. */ 2689 spin_lock_irqsave(&ha->hardware_lock, flags); 2690 WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); 2691 RD_REG_WORD(®->hccr); 2692 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2693 } 2694 2695 qla81xx_mpi_sync(vha); 2696 2697 /* Load firmware sequences */ 2698 rval = ha->isp_ops->load_risc(vha, &srisc_address); 2699 if (rval == QLA_SUCCESS) { 2700 ql_dbg(ql_dbg_init, vha, 0x00c9, 2701 "Verifying Checksum of loaded RISC code.\n"); 2702 2703 rval = qla2x00_verify_checksum(vha, srisc_address); 2704 if (rval == QLA_SUCCESS) { 2705 /* Start firmware execution. */ 2706 ql_dbg(ql_dbg_init, vha, 0x00ca, 2707 "Starting firmware.\n"); 2708 2709 if (ql2xexlogins) 2710 ha->flags.exlogins_enabled = 1; 2711 2712 if (ql2xexchoffld) 2713 ha->flags.exchoffld_enabled = 1; 2714 2715 rval = qla2x00_execute_fw(vha, srisc_address); 2716 /* Retrieve firmware information. */ 2717 if (rval == QLA_SUCCESS) { 2718 rval = qla2x00_set_exlogins_buffer(vha); 2719 if (rval != QLA_SUCCESS) 2720 goto failed; 2721 2722 rval = qla2x00_set_exchoffld_buffer(vha); 2723 if (rval != QLA_SUCCESS) 2724 goto failed; 2725 2726 enable_82xx_npiv: 2727 fw_major_version = ha->fw_major_version; 2728 if (IS_P3P_TYPE(ha)) 2729 qla82xx_check_md_needed(vha); 2730 else 2731 rval = qla2x00_get_fw_version(vha); 2732 if (rval != QLA_SUCCESS) 2733 goto failed; 2734 ha->flags.npiv_supported = 0; 2735 if (IS_QLA2XXX_MIDTYPE(ha) && 2736 (ha->fw_attributes & BIT_2)) { 2737 ha->flags.npiv_supported = 1; 2738 if ((!ha->max_npiv_vports) || 2739 ((ha->max_npiv_vports + 1) % 2740 MIN_MULTI_ID_FABRIC)) 2741 ha->max_npiv_vports = 2742 MIN_MULTI_ID_FABRIC - 1; 2743 } 2744 qla2x00_get_resource_cnts(vha); 2745 2746 /* 2747 * Allocate the array of outstanding commands 2748 * now that we know the firmware resources. 2749 */ 2750 rval = qla2x00_alloc_outstanding_cmds(ha, 2751 vha->req); 2752 if (rval != QLA_SUCCESS) 2753 goto failed; 2754 2755 if (!fw_major_version && ql2xallocfwdump 2756 && !(IS_P3P_TYPE(ha))) 2757 qla2x00_alloc_fw_dump(vha); 2758 } else { 2759 goto failed; 2760 } 2761 } else { 2762 ql_log(ql_log_fatal, vha, 0x00cd, 2763 "ISP Firmware failed checksum.\n"); 2764 goto failed; 2765 } 2766 } else 2767 goto failed; 2768 2769 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 2770 /* Enable proper parity. */ 2771 spin_lock_irqsave(&ha->hardware_lock, flags); 2772 if (IS_QLA2300(ha)) 2773 /* SRAM parity */ 2774 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1); 2775 else 2776 /* SRAM, Instruction RAM and GP RAM parity */ 2777 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7); 2778 RD_REG_WORD(®->hccr); 2779 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2780 } 2781 2782 if (IS_QLA27XX(ha)) 2783 ha->flags.fac_supported = 1; 2784 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { 2785 uint32_t size; 2786 2787 rval = qla81xx_fac_get_sector_size(vha, &size); 2788 if (rval == QLA_SUCCESS) { 2789 ha->flags.fac_supported = 1; 2790 ha->fdt_block_size = size << 2; 2791 } else { 2792 ql_log(ql_log_warn, vha, 0x00ce, 2793 "Unsupported FAC firmware (%d.%02d.%02d).\n", 2794 ha->fw_major_version, ha->fw_minor_version, 2795 ha->fw_subminor_version); 2796 2797 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2798 ha->flags.fac_supported = 0; 2799 rval = QLA_SUCCESS; 2800 } 2801 } 2802 } 2803 failed: 2804 if (rval) { 2805 ql_log(ql_log_fatal, vha, 0x00cf, 2806 "Setup chip ****FAILED****.\n"); 2807 } 2808 2809 return (rval); 2810 } 2811 2812 /** 2813 * qla2x00_init_response_q_entries() - Initializes response queue entries. 2814 * @ha: HA context 2815 * 2816 * Beginning of request ring has initialization control block already built 2817 * by nvram config routine. 2818 * 2819 * Returns 0 on success. 2820 */ 2821 void 2822 qla2x00_init_response_q_entries(struct rsp_que *rsp) 2823 { 2824 uint16_t cnt; 2825 response_t *pkt; 2826 2827 rsp->ring_ptr = rsp->ring; 2828 rsp->ring_index = 0; 2829 rsp->status_srb = NULL; 2830 pkt = rsp->ring_ptr; 2831 for (cnt = 0; cnt < rsp->length; cnt++) { 2832 pkt->signature = RESPONSE_PROCESSED; 2833 pkt++; 2834 } 2835 } 2836 2837 /** 2838 * qla2x00_update_fw_options() - Read and process firmware options. 2839 * @ha: HA context 2840 * 2841 * Returns 0 on success. 2842 */ 2843 void 2844 qla2x00_update_fw_options(scsi_qla_host_t *vha) 2845 { 2846 uint16_t swing, emphasis, tx_sens, rx_sens; 2847 struct qla_hw_data *ha = vha->hw; 2848 2849 memset(ha->fw_options, 0, sizeof(ha->fw_options)); 2850 qla2x00_get_fw_options(vha, ha->fw_options); 2851 2852 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 2853 return; 2854 2855 /* Serial Link options. */ 2856 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115, 2857 "Serial link options.\n"); 2858 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109, 2859 (uint8_t *)&ha->fw_seriallink_options, 2860 sizeof(ha->fw_seriallink_options)); 2861 2862 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 2863 if (ha->fw_seriallink_options[3] & BIT_2) { 2864 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING; 2865 2866 /* 1G settings */ 2867 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); 2868 emphasis = (ha->fw_seriallink_options[2] & 2869 (BIT_4 | BIT_3)) >> 3; 2870 tx_sens = ha->fw_seriallink_options[0] & 2871 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 2872 rx_sens = (ha->fw_seriallink_options[0] & 2873 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 2874 ha->fw_options[10] = (emphasis << 14) | (swing << 8); 2875 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 2876 if (rx_sens == 0x0) 2877 rx_sens = 0x3; 2878 ha->fw_options[10] |= (tx_sens << 4) | rx_sens; 2879 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2880 ha->fw_options[10] |= BIT_5 | 2881 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 2882 (tx_sens & (BIT_1 | BIT_0)); 2883 2884 /* 2G settings */ 2885 swing = (ha->fw_seriallink_options[2] & 2886 (BIT_7 | BIT_6 | BIT_5)) >> 5; 2887 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); 2888 tx_sens = ha->fw_seriallink_options[1] & 2889 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 2890 rx_sens = (ha->fw_seriallink_options[1] & 2891 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 2892 ha->fw_options[11] = (emphasis << 14) | (swing << 8); 2893 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 2894 if (rx_sens == 0x0) 2895 rx_sens = 0x3; 2896 ha->fw_options[11] |= (tx_sens << 4) | rx_sens; 2897 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2898 ha->fw_options[11] |= BIT_5 | 2899 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 2900 (tx_sens & (BIT_1 | BIT_0)); 2901 } 2902 2903 /* FCP2 options. */ 2904 /* Return command IOCBs without waiting for an ABTS to complete. */ 2905 ha->fw_options[3] |= BIT_13; 2906 2907 /* LED scheme. */ 2908 if (ha->flags.enable_led_scheme) 2909 ha->fw_options[2] |= BIT_12; 2910 2911 /* Detect ISP6312. */ 2912 if (IS_QLA6312(ha)) 2913 ha->fw_options[2] |= BIT_13; 2914 2915 /* Set Retry FLOGI in case of P2P connection */ 2916 if (ha->operating_mode == P2P) { 2917 ha->fw_options[2] |= BIT_3; 2918 ql_dbg(ql_dbg_disc, vha, 0x2100, 2919 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 2920 __func__, ha->fw_options[2]); 2921 } 2922 2923 /* Update firmware options. */ 2924 qla2x00_set_fw_options(vha, ha->fw_options); 2925 } 2926 2927 void 2928 qla24xx_update_fw_options(scsi_qla_host_t *vha) 2929 { 2930 int rval; 2931 struct qla_hw_data *ha = vha->hw; 2932 2933 if (IS_P3P_TYPE(ha)) 2934 return; 2935 2936 /* Hold status IOCBs until ABTS response received. */ 2937 if (ql2xfwholdabts) 2938 ha->fw_options[3] |= BIT_12; 2939 2940 /* Set Retry FLOGI in case of P2P connection */ 2941 if (ha->operating_mode == P2P) { 2942 ha->fw_options[2] |= BIT_3; 2943 ql_dbg(ql_dbg_disc, vha, 0x2101, 2944 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 2945 __func__, ha->fw_options[2]); 2946 } 2947 2948 /* Move PUREX, ABTS RX & RIDA to ATIOQ */ 2949 if (ql2xmvasynctoatio) { 2950 if (qla_tgt_mode_enabled(vha) || 2951 qla_dual_mode_enabled(vha)) 2952 ha->fw_options[2] |= BIT_11; 2953 else 2954 ha->fw_options[2] &= ~BIT_11; 2955 } 2956 2957 ql_dbg(ql_dbg_init, vha, 0xffff, 2958 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n", 2959 __func__, ha->fw_options[1], ha->fw_options[2], 2960 ha->fw_options[3], vha->host->active_mode); 2961 qla2x00_set_fw_options(vha, ha->fw_options); 2962 2963 /* Update Serial Link options. */ 2964 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) 2965 return; 2966 2967 rval = qla2x00_set_serdes_params(vha, 2968 le16_to_cpu(ha->fw_seriallink_options24[1]), 2969 le16_to_cpu(ha->fw_seriallink_options24[2]), 2970 le16_to_cpu(ha->fw_seriallink_options24[3])); 2971 if (rval != QLA_SUCCESS) { 2972 ql_log(ql_log_warn, vha, 0x0104, 2973 "Unable to update Serial Link options (%x).\n", rval); 2974 } 2975 } 2976 2977 void 2978 qla2x00_config_rings(struct scsi_qla_host *vha) 2979 { 2980 struct qla_hw_data *ha = vha->hw; 2981 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2982 struct req_que *req = ha->req_q_map[0]; 2983 struct rsp_que *rsp = ha->rsp_q_map[0]; 2984 2985 /* Setup ring parameters in initialization control block. */ 2986 ha->init_cb->request_q_outpointer = cpu_to_le16(0); 2987 ha->init_cb->response_q_inpointer = cpu_to_le16(0); 2988 ha->init_cb->request_q_length = cpu_to_le16(req->length); 2989 ha->init_cb->response_q_length = cpu_to_le16(rsp->length); 2990 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 2991 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 2992 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 2993 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 2994 2995 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0); 2996 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0); 2997 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0); 2998 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0); 2999 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ 3000 } 3001 3002 void 3003 qla24xx_config_rings(struct scsi_qla_host *vha) 3004 { 3005 struct qla_hw_data *ha = vha->hw; 3006 device_reg_t *reg = ISP_QUE_REG(ha, 0); 3007 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; 3008 struct qla_msix_entry *msix; 3009 struct init_cb_24xx *icb; 3010 uint16_t rid = 0; 3011 struct req_que *req = ha->req_q_map[0]; 3012 struct rsp_que *rsp = ha->rsp_q_map[0]; 3013 3014 /* Setup ring parameters in initialization control block. */ 3015 icb = (struct init_cb_24xx *)ha->init_cb; 3016 icb->request_q_outpointer = cpu_to_le16(0); 3017 icb->response_q_inpointer = cpu_to_le16(0); 3018 icb->request_q_length = cpu_to_le16(req->length); 3019 icb->response_q_length = cpu_to_le16(rsp->length); 3020 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 3021 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 3022 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 3023 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 3024 3025 /* Setup ATIO queue dma pointers for target mode */ 3026 icb->atio_q_inpointer = cpu_to_le16(0); 3027 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length); 3028 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma)); 3029 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma)); 3030 3031 if (IS_SHADOW_REG_CAPABLE(ha)) 3032 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29); 3033 3034 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3035 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS); 3036 icb->rid = cpu_to_le16(rid); 3037 if (ha->flags.msix_enabled) { 3038 msix = &ha->msix_entries[1]; 3039 ql_dbg(ql_dbg_init, vha, 0x00fd, 3040 "Registering vector 0x%x for base que.\n", 3041 msix->entry); 3042 icb->msix = cpu_to_le16(msix->entry); 3043 } 3044 /* Use alternate PCI bus number */ 3045 if (MSB(rid)) 3046 icb->firmware_options_2 |= cpu_to_le32(BIT_19); 3047 /* Use alternate PCI devfn */ 3048 if (LSB(rid)) 3049 icb->firmware_options_2 |= cpu_to_le32(BIT_18); 3050 3051 /* Use Disable MSIX Handshake mode for capable adapters */ 3052 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) && 3053 (ha->flags.msix_enabled)) { 3054 icb->firmware_options_2 &= cpu_to_le32(~BIT_22); 3055 ha->flags.disable_msix_handshake = 1; 3056 ql_dbg(ql_dbg_init, vha, 0x00fe, 3057 "MSIX Handshake Disable Mode turned on.\n"); 3058 } else { 3059 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 3060 } 3061 icb->firmware_options_2 |= cpu_to_le32(BIT_23); 3062 3063 WRT_REG_DWORD(®->isp25mq.req_q_in, 0); 3064 WRT_REG_DWORD(®->isp25mq.req_q_out, 0); 3065 WRT_REG_DWORD(®->isp25mq.rsp_q_in, 0); 3066 WRT_REG_DWORD(®->isp25mq.rsp_q_out, 0); 3067 } else { 3068 WRT_REG_DWORD(®->isp24.req_q_in, 0); 3069 WRT_REG_DWORD(®->isp24.req_q_out, 0); 3070 WRT_REG_DWORD(®->isp24.rsp_q_in, 0); 3071 WRT_REG_DWORD(®->isp24.rsp_q_out, 0); 3072 } 3073 qlt_24xx_config_rings(vha); 3074 3075 /* PCI posting */ 3076 RD_REG_DWORD(&ioreg->hccr); 3077 } 3078 3079 /** 3080 * qla2x00_init_rings() - Initializes firmware. 3081 * @ha: HA context 3082 * 3083 * Beginning of request ring has initialization control block already built 3084 * by nvram config routine. 3085 * 3086 * Returns 0 on success. 3087 */ 3088 int 3089 qla2x00_init_rings(scsi_qla_host_t *vha) 3090 { 3091 int rval; 3092 unsigned long flags = 0; 3093 int cnt, que; 3094 struct qla_hw_data *ha = vha->hw; 3095 struct req_que *req; 3096 struct rsp_que *rsp; 3097 struct mid_init_cb_24xx *mid_init_cb = 3098 (struct mid_init_cb_24xx *) ha->init_cb; 3099 3100 spin_lock_irqsave(&ha->hardware_lock, flags); 3101 3102 /* Clear outstanding commands array. */ 3103 for (que = 0; que < ha->max_req_queues; que++) { 3104 req = ha->req_q_map[que]; 3105 if (!req || !test_bit(que, ha->req_qid_map)) 3106 continue; 3107 req->out_ptr = (void *)(req->ring + req->length); 3108 *req->out_ptr = 0; 3109 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) 3110 req->outstanding_cmds[cnt] = NULL; 3111 3112 req->current_outstanding_cmd = 1; 3113 3114 /* Initialize firmware. */ 3115 req->ring_ptr = req->ring; 3116 req->ring_index = 0; 3117 req->cnt = req->length; 3118 } 3119 3120 for (que = 0; que < ha->max_rsp_queues; que++) { 3121 rsp = ha->rsp_q_map[que]; 3122 if (!rsp || !test_bit(que, ha->rsp_qid_map)) 3123 continue; 3124 rsp->in_ptr = (void *)(rsp->ring + rsp->length); 3125 *rsp->in_ptr = 0; 3126 /* Initialize response queue entries */ 3127 if (IS_QLAFX00(ha)) 3128 qlafx00_init_response_q_entries(rsp); 3129 else 3130 qla2x00_init_response_q_entries(rsp); 3131 } 3132 3133 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring; 3134 ha->tgt.atio_ring_index = 0; 3135 /* Initialize ATIO queue entries */ 3136 qlt_init_atio_q_entries(vha); 3137 3138 ha->isp_ops->config_rings(vha); 3139 3140 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3141 3142 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n"); 3143 3144 if (IS_QLAFX00(ha)) { 3145 rval = qlafx00_init_firmware(vha, ha->init_cb_size); 3146 goto next_check; 3147 } 3148 3149 /* Update any ISP specific firmware options before initialization. */ 3150 ha->isp_ops->update_fw_options(vha); 3151 3152 if (ha->flags.npiv_supported) { 3153 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha)) 3154 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; 3155 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); 3156 } 3157 3158 if (IS_FWI2_CAPABLE(ha)) { 3159 mid_init_cb->options = cpu_to_le16(BIT_1); 3160 mid_init_cb->init_cb.execution_throttle = 3161 cpu_to_le16(ha->cur_fw_xcb_count); 3162 ha->flags.dport_enabled = 3163 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0; 3164 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n", 3165 (ha->flags.dport_enabled) ? "enabled" : "disabled"); 3166 /* FA-WWPN Status */ 3167 ha->flags.fawwpn_enabled = 3168 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0; 3169 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n", 3170 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled"); 3171 } 3172 3173 rval = qla2x00_init_firmware(vha, ha->init_cb_size); 3174 next_check: 3175 if (rval) { 3176 ql_log(ql_log_fatal, vha, 0x00d2, 3177 "Init Firmware **** FAILED ****.\n"); 3178 } else { 3179 ql_dbg(ql_dbg_init, vha, 0x00d3, 3180 "Init Firmware -- success.\n"); 3181 ha->flags.fw_started = 1; 3182 } 3183 3184 return (rval); 3185 } 3186 3187 /** 3188 * qla2x00_fw_ready() - Waits for firmware ready. 3189 * @ha: HA context 3190 * 3191 * Returns 0 on success. 3192 */ 3193 static int 3194 qla2x00_fw_ready(scsi_qla_host_t *vha) 3195 { 3196 int rval; 3197 unsigned long wtime, mtime, cs84xx_time; 3198 uint16_t min_wait; /* Minimum wait time if loop is down */ 3199 uint16_t wait_time; /* Wait time if loop is coming ready */ 3200 uint16_t state[6]; 3201 struct qla_hw_data *ha = vha->hw; 3202 3203 if (IS_QLAFX00(vha->hw)) 3204 return qlafx00_fw_ready(vha); 3205 3206 rval = QLA_SUCCESS; 3207 3208 /* Time to wait for loop down */ 3209 if (IS_P3P_TYPE(ha)) 3210 min_wait = 30; 3211 else 3212 min_wait = 20; 3213 3214 /* 3215 * Firmware should take at most one RATOV to login, plus 5 seconds for 3216 * our own processing. 3217 */ 3218 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) { 3219 wait_time = min_wait; 3220 } 3221 3222 /* Min wait time if loop down */ 3223 mtime = jiffies + (min_wait * HZ); 3224 3225 /* wait time before firmware ready */ 3226 wtime = jiffies + (wait_time * HZ); 3227 3228 /* Wait for ISP to finish LIP */ 3229 if (!vha->flags.init_done) 3230 ql_log(ql_log_info, vha, 0x801e, 3231 "Waiting for LIP to complete.\n"); 3232 3233 do { 3234 memset(state, -1, sizeof(state)); 3235 rval = qla2x00_get_firmware_state(vha, state); 3236 if (rval == QLA_SUCCESS) { 3237 if (state[0] < FSTATE_LOSS_OF_SYNC) { 3238 vha->device_flags &= ~DFLG_NO_CABLE; 3239 } 3240 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) { 3241 ql_dbg(ql_dbg_taskm, vha, 0x801f, 3242 "fw_state=%x 84xx=%x.\n", state[0], 3243 state[2]); 3244 if ((state[2] & FSTATE_LOGGED_IN) && 3245 (state[2] & FSTATE_WAITING_FOR_VERIFY)) { 3246 ql_dbg(ql_dbg_taskm, vha, 0x8028, 3247 "Sending verify iocb.\n"); 3248 3249 cs84xx_time = jiffies; 3250 rval = qla84xx_init_chip(vha); 3251 if (rval != QLA_SUCCESS) { 3252 ql_log(ql_log_warn, 3253 vha, 0x8007, 3254 "Init chip failed.\n"); 3255 break; 3256 } 3257 3258 /* Add time taken to initialize. */ 3259 cs84xx_time = jiffies - cs84xx_time; 3260 wtime += cs84xx_time; 3261 mtime += cs84xx_time; 3262 ql_dbg(ql_dbg_taskm, vha, 0x8008, 3263 "Increasing wait time by %ld. " 3264 "New time %ld.\n", cs84xx_time, 3265 wtime); 3266 } 3267 } else if (state[0] == FSTATE_READY) { 3268 ql_dbg(ql_dbg_taskm, vha, 0x8037, 3269 "F/W Ready - OK.\n"); 3270 3271 qla2x00_get_retry_cnt(vha, &ha->retry_count, 3272 &ha->login_timeout, &ha->r_a_tov); 3273 3274 rval = QLA_SUCCESS; 3275 break; 3276 } 3277 3278 rval = QLA_FUNCTION_FAILED; 3279 3280 if (atomic_read(&vha->loop_down_timer) && 3281 state[0] != FSTATE_READY) { 3282 /* Loop down. Timeout on min_wait for states 3283 * other than Wait for Login. 3284 */ 3285 if (time_after_eq(jiffies, mtime)) { 3286 ql_log(ql_log_info, vha, 0x8038, 3287 "Cable is unplugged...\n"); 3288 3289 vha->device_flags |= DFLG_NO_CABLE; 3290 break; 3291 } 3292 } 3293 } else { 3294 /* Mailbox cmd failed. Timeout on min_wait. */ 3295 if (time_after_eq(jiffies, mtime) || 3296 ha->flags.isp82xx_fw_hung) 3297 break; 3298 } 3299 3300 if (time_after_eq(jiffies, wtime)) 3301 break; 3302 3303 /* Delay for a while */ 3304 msleep(500); 3305 } while (1); 3306 3307 ql_dbg(ql_dbg_taskm, vha, 0x803a, 3308 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0], 3309 state[1], state[2], state[3], state[4], state[5], jiffies); 3310 3311 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) { 3312 ql_log(ql_log_warn, vha, 0x803b, 3313 "Firmware ready **** FAILED ****.\n"); 3314 } 3315 3316 return (rval); 3317 } 3318 3319 /* 3320 * qla2x00_configure_hba 3321 * Setup adapter context. 3322 * 3323 * Input: 3324 * ha = adapter state pointer. 3325 * 3326 * Returns: 3327 * 0 = success 3328 * 3329 * Context: 3330 * Kernel context. 3331 */ 3332 static int 3333 qla2x00_configure_hba(scsi_qla_host_t *vha) 3334 { 3335 int rval; 3336 uint16_t loop_id; 3337 uint16_t topo; 3338 uint16_t sw_cap; 3339 uint8_t al_pa; 3340 uint8_t area; 3341 uint8_t domain; 3342 char connect_type[22]; 3343 struct qla_hw_data *ha = vha->hw; 3344 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 3345 port_id_t id; 3346 3347 /* Get host addresses. */ 3348 rval = qla2x00_get_adapter_id(vha, 3349 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); 3350 if (rval != QLA_SUCCESS) { 3351 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || 3352 IS_CNA_CAPABLE(ha) || 3353 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { 3354 ql_dbg(ql_dbg_disc, vha, 0x2008, 3355 "Loop is in a transition state.\n"); 3356 } else { 3357 ql_log(ql_log_warn, vha, 0x2009, 3358 "Unable to get host loop ID.\n"); 3359 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) && 3360 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) { 3361 ql_log(ql_log_warn, vha, 0x1151, 3362 "Doing link init.\n"); 3363 if (qla24xx_link_initialize(vha) == QLA_SUCCESS) 3364 return rval; 3365 } 3366 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3367 } 3368 return (rval); 3369 } 3370 3371 if (topo == 4) { 3372 ql_log(ql_log_info, vha, 0x200a, 3373 "Cannot get topology - retrying.\n"); 3374 return (QLA_FUNCTION_FAILED); 3375 } 3376 3377 vha->loop_id = loop_id; 3378 3379 /* initialize */ 3380 ha->min_external_loopid = SNS_FIRST_LOOP_ID; 3381 ha->operating_mode = LOOP; 3382 ha->switch_cap = 0; 3383 3384 switch (topo) { 3385 case 0: 3386 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n"); 3387 ha->current_topology = ISP_CFG_NL; 3388 strcpy(connect_type, "(Loop)"); 3389 break; 3390 3391 case 1: 3392 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n"); 3393 ha->switch_cap = sw_cap; 3394 ha->current_topology = ISP_CFG_FL; 3395 strcpy(connect_type, "(FL_Port)"); 3396 break; 3397 3398 case 2: 3399 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n"); 3400 ha->operating_mode = P2P; 3401 ha->current_topology = ISP_CFG_N; 3402 strcpy(connect_type, "(N_Port-to-N_Port)"); 3403 break; 3404 3405 case 3: 3406 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n"); 3407 ha->switch_cap = sw_cap; 3408 ha->operating_mode = P2P; 3409 ha->current_topology = ISP_CFG_F; 3410 strcpy(connect_type, "(F_Port)"); 3411 break; 3412 3413 default: 3414 ql_dbg(ql_dbg_disc, vha, 0x200f, 3415 "HBA in unknown topology %x, using NL.\n", topo); 3416 ha->current_topology = ISP_CFG_NL; 3417 strcpy(connect_type, "(Loop)"); 3418 break; 3419 } 3420 3421 /* Save Host port and loop ID. */ 3422 /* byte order - Big Endian */ 3423 id.b.domain = domain; 3424 id.b.area = area; 3425 id.b.al_pa = al_pa; 3426 id.b.rsvd_1 = 0; 3427 qlt_update_host_map(vha, id); 3428 3429 if (!vha->flags.init_done) 3430 ql_log(ql_log_info, vha, 0x2010, 3431 "Topology - %s, Host Loop address 0x%x.\n", 3432 connect_type, vha->loop_id); 3433 3434 return(rval); 3435 } 3436 3437 inline void 3438 qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, 3439 char *def) 3440 { 3441 char *st, *en; 3442 uint16_t index; 3443 struct qla_hw_data *ha = vha->hw; 3444 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 3445 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha); 3446 3447 if (memcmp(model, BINZERO, len) != 0) { 3448 strncpy(ha->model_number, model, len); 3449 st = en = ha->model_number; 3450 en += len - 1; 3451 while (en > st) { 3452 if (*en != 0x20 && *en != 0x00) 3453 break; 3454 *en-- = '\0'; 3455 } 3456 3457 index = (ha->pdev->subsystem_device & 0xff); 3458 if (use_tbl && 3459 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 3460 index < QLA_MODEL_NAMES) 3461 strncpy(ha->model_desc, 3462 qla2x00_model_name[index * 2 + 1], 3463 sizeof(ha->model_desc) - 1); 3464 } else { 3465 index = (ha->pdev->subsystem_device & 0xff); 3466 if (use_tbl && 3467 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 3468 index < QLA_MODEL_NAMES) { 3469 strcpy(ha->model_number, 3470 qla2x00_model_name[index * 2]); 3471 strncpy(ha->model_desc, 3472 qla2x00_model_name[index * 2 + 1], 3473 sizeof(ha->model_desc) - 1); 3474 } else { 3475 strcpy(ha->model_number, def); 3476 } 3477 } 3478 if (IS_FWI2_CAPABLE(ha)) 3479 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc, 3480 sizeof(ha->model_desc)); 3481 } 3482 3483 /* On sparc systems, obtain port and node WWN from firmware 3484 * properties. 3485 */ 3486 static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv) 3487 { 3488 #ifdef CONFIG_SPARC 3489 struct qla_hw_data *ha = vha->hw; 3490 struct pci_dev *pdev = ha->pdev; 3491 struct device_node *dp = pci_device_to_OF_node(pdev); 3492 const u8 *val; 3493 int len; 3494 3495 val = of_get_property(dp, "port-wwn", &len); 3496 if (val && len >= WWN_SIZE) 3497 memcpy(nv->port_name, val, WWN_SIZE); 3498 3499 val = of_get_property(dp, "node-wwn", &len); 3500 if (val && len >= WWN_SIZE) 3501 memcpy(nv->node_name, val, WWN_SIZE); 3502 #endif 3503 } 3504 3505 /* 3506 * NVRAM configuration for ISP 2xxx 3507 * 3508 * Input: 3509 * ha = adapter block pointer. 3510 * 3511 * Output: 3512 * initialization control block in response_ring 3513 * host adapters parameters in host adapter block 3514 * 3515 * Returns: 3516 * 0 = success. 3517 */ 3518 int 3519 qla2x00_nvram_config(scsi_qla_host_t *vha) 3520 { 3521 int rval; 3522 uint8_t chksum = 0; 3523 uint16_t cnt; 3524 uint8_t *dptr1, *dptr2; 3525 struct qla_hw_data *ha = vha->hw; 3526 init_cb_t *icb = ha->init_cb; 3527 nvram_t *nv = ha->nvram; 3528 uint8_t *ptr = ha->nvram; 3529 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3530 3531 rval = QLA_SUCCESS; 3532 3533 /* Determine NVRAM starting address. */ 3534 ha->nvram_size = sizeof(nvram_t); 3535 ha->nvram_base = 0; 3536 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) 3537 if ((RD_REG_WORD(®->ctrl_status) >> 14) == 1) 3538 ha->nvram_base = 0x80; 3539 3540 /* Get NVRAM data and calculate checksum. */ 3541 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size); 3542 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) 3543 chksum += *ptr++; 3544 3545 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f, 3546 "Contents of NVRAM.\n"); 3547 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110, 3548 (uint8_t *)nv, ha->nvram_size); 3549 3550 /* Bad NVRAM data, set defaults parameters. */ 3551 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || 3552 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) { 3553 /* Reset NVRAM data. */ 3554 ql_log(ql_log_warn, vha, 0x0064, 3555 "Inconsistent NVRAM " 3556 "detected: checksum=0x%x id=%c version=0x%x.\n", 3557 chksum, nv->id[0], nv->nvram_version); 3558 ql_log(ql_log_warn, vha, 0x0065, 3559 "Falling back to " 3560 "functioning (yet invalid -- WWPN) defaults.\n"); 3561 3562 /* 3563 * Set default initialization control block. 3564 */ 3565 memset(nv, 0, ha->nvram_size); 3566 nv->parameter_block_version = ICB_VERSION; 3567 3568 if (IS_QLA23XX(ha)) { 3569 nv->firmware_options[0] = BIT_2 | BIT_1; 3570 nv->firmware_options[1] = BIT_7 | BIT_5; 3571 nv->add_firmware_options[0] = BIT_5; 3572 nv->add_firmware_options[1] = BIT_5 | BIT_4; 3573 nv->frame_payload_size = 2048; 3574 nv->special_options[1] = BIT_7; 3575 } else if (IS_QLA2200(ha)) { 3576 nv->firmware_options[0] = BIT_2 | BIT_1; 3577 nv->firmware_options[1] = BIT_7 | BIT_5; 3578 nv->add_firmware_options[0] = BIT_5; 3579 nv->add_firmware_options[1] = BIT_5 | BIT_4; 3580 nv->frame_payload_size = 1024; 3581 } else if (IS_QLA2100(ha)) { 3582 nv->firmware_options[0] = BIT_3 | BIT_1; 3583 nv->firmware_options[1] = BIT_5; 3584 nv->frame_payload_size = 1024; 3585 } 3586 3587 nv->max_iocb_allocation = cpu_to_le16(256); 3588 nv->execution_throttle = cpu_to_le16(16); 3589 nv->retry_count = 8; 3590 nv->retry_delay = 1; 3591 3592 nv->port_name[0] = 33; 3593 nv->port_name[3] = 224; 3594 nv->port_name[4] = 139; 3595 3596 qla2xxx_nvram_wwn_from_ofw(vha, nv); 3597 3598 nv->login_timeout = 4; 3599 3600 /* 3601 * Set default host adapter parameters 3602 */ 3603 nv->host_p[1] = BIT_2; 3604 nv->reset_delay = 5; 3605 nv->port_down_retry_count = 8; 3606 nv->max_luns_per_target = cpu_to_le16(8); 3607 nv->link_down_timeout = 60; 3608 3609 rval = 1; 3610 } 3611 3612 #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) 3613 /* 3614 * The SN2 does not provide BIOS emulation which means you can't change 3615 * potentially bogus BIOS settings. Force the use of default settings 3616 * for link rate and frame size. Hope that the rest of the settings 3617 * are valid. 3618 */ 3619 if (ia64_platform_is("sn2")) { 3620 nv->frame_payload_size = 2048; 3621 if (IS_QLA23XX(ha)) 3622 nv->special_options[1] = BIT_7; 3623 } 3624 #endif 3625 3626 /* Reset Initialization control block */ 3627 memset(icb, 0, ha->init_cb_size); 3628 3629 /* 3630 * Setup driver NVRAM options. 3631 */ 3632 nv->firmware_options[0] |= (BIT_6 | BIT_1); 3633 nv->firmware_options[0] &= ~(BIT_5 | BIT_4); 3634 nv->firmware_options[1] |= (BIT_5 | BIT_0); 3635 nv->firmware_options[1] &= ~BIT_4; 3636 3637 if (IS_QLA23XX(ha)) { 3638 nv->firmware_options[0] |= BIT_2; 3639 nv->firmware_options[0] &= ~BIT_3; 3640 nv->special_options[0] &= ~BIT_6; 3641 nv->add_firmware_options[1] |= BIT_5 | BIT_4; 3642 3643 if (IS_QLA2300(ha)) { 3644 if (ha->fb_rev == FPM_2310) { 3645 strcpy(ha->model_number, "QLA2310"); 3646 } else { 3647 strcpy(ha->model_number, "QLA2300"); 3648 } 3649 } else { 3650 qla2x00_set_model_info(vha, nv->model_number, 3651 sizeof(nv->model_number), "QLA23xx"); 3652 } 3653 } else if (IS_QLA2200(ha)) { 3654 nv->firmware_options[0] |= BIT_2; 3655 /* 3656 * 'Point-to-point preferred, else loop' is not a safe 3657 * connection mode setting. 3658 */ 3659 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == 3660 (BIT_5 | BIT_4)) { 3661 /* Force 'loop preferred, else point-to-point'. */ 3662 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); 3663 nv->add_firmware_options[0] |= BIT_5; 3664 } 3665 strcpy(ha->model_number, "QLA22xx"); 3666 } else /*if (IS_QLA2100(ha))*/ { 3667 strcpy(ha->model_number, "QLA2100"); 3668 } 3669 3670 /* 3671 * Copy over NVRAM RISC parameter block to initialization control block. 3672 */ 3673 dptr1 = (uint8_t *)icb; 3674 dptr2 = (uint8_t *)&nv->parameter_block_version; 3675 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version; 3676 while (cnt--) 3677 *dptr1++ = *dptr2++; 3678 3679 /* Copy 2nd half. */ 3680 dptr1 = (uint8_t *)icb->add_firmware_options; 3681 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options; 3682 while (cnt--) 3683 *dptr1++ = *dptr2++; 3684 3685 /* Use alternate WWN? */ 3686 if (nv->host_p[1] & BIT_7) { 3687 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 3688 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 3689 } 3690 3691 /* Prepare nodename */ 3692 if ((icb->firmware_options[1] & BIT_6) == 0) { 3693 /* 3694 * Firmware will apply the following mask if the nodename was 3695 * not provided. 3696 */ 3697 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 3698 icb->node_name[0] &= 0xF0; 3699 } 3700 3701 /* 3702 * Set host adapter parameters. 3703 */ 3704 3705 /* 3706 * BIT_7 in the host-parameters section allows for modification to 3707 * internal driver logging. 3708 */ 3709 if (nv->host_p[0] & BIT_7) 3710 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 3711 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); 3712 /* Always load RISC code on non ISP2[12]00 chips. */ 3713 if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) 3714 ha->flags.disable_risc_code_load = 0; 3715 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0); 3716 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); 3717 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); 3718 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; 3719 ha->flags.disable_serdes = 0; 3720 3721 ha->operating_mode = 3722 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; 3723 3724 memcpy(ha->fw_seriallink_options, nv->seriallink_options, 3725 sizeof(ha->fw_seriallink_options)); 3726 3727 /* save HBA serial number */ 3728 ha->serial0 = icb->port_name[5]; 3729 ha->serial1 = icb->port_name[6]; 3730 ha->serial2 = icb->port_name[7]; 3731 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 3732 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 3733 3734 icb->execution_throttle = cpu_to_le16(0xFFFF); 3735 3736 ha->retry_count = nv->retry_count; 3737 3738 /* Set minimum login_timeout to 4 seconds. */ 3739 if (nv->login_timeout != ql2xlogintimeout) 3740 nv->login_timeout = ql2xlogintimeout; 3741 if (nv->login_timeout < 4) 3742 nv->login_timeout = 4; 3743 ha->login_timeout = nv->login_timeout; 3744 3745 /* Set minimum RATOV to 100 tenths of a second. */ 3746 ha->r_a_tov = 100; 3747 3748 ha->loop_reset_delay = nv->reset_delay; 3749 3750 /* Link Down Timeout = 0: 3751 * 3752 * When Port Down timer expires we will start returning 3753 * I/O's to OS with "DID_NO_CONNECT". 3754 * 3755 * Link Down Timeout != 0: 3756 * 3757 * The driver waits for the link to come up after link down 3758 * before returning I/Os to OS with "DID_NO_CONNECT". 3759 */ 3760 if (nv->link_down_timeout == 0) { 3761 ha->loop_down_abort_time = 3762 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 3763 } else { 3764 ha->link_down_timeout = nv->link_down_timeout; 3765 ha->loop_down_abort_time = 3766 (LOOP_DOWN_TIME - ha->link_down_timeout); 3767 } 3768 3769 /* 3770 * Need enough time to try and get the port back. 3771 */ 3772 ha->port_down_retry_count = nv->port_down_retry_count; 3773 if (qlport_down_retry) 3774 ha->port_down_retry_count = qlport_down_retry; 3775 /* Set login_retry_count */ 3776 ha->login_retry_count = nv->retry_count; 3777 if (ha->port_down_retry_count == nv->port_down_retry_count && 3778 ha->port_down_retry_count > 3) 3779 ha->login_retry_count = ha->port_down_retry_count; 3780 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 3781 ha->login_retry_count = ha->port_down_retry_count; 3782 if (ql2xloginretrycount) 3783 ha->login_retry_count = ql2xloginretrycount; 3784 3785 icb->lun_enables = cpu_to_le16(0); 3786 icb->command_resource_count = 0; 3787 icb->immediate_notify_resource_count = 0; 3788 icb->timeout = cpu_to_le16(0); 3789 3790 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3791 /* Enable RIO */ 3792 icb->firmware_options[0] &= ~BIT_3; 3793 icb->add_firmware_options[0] &= 3794 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 3795 icb->add_firmware_options[0] |= BIT_2; 3796 icb->response_accumulation_timer = 3; 3797 icb->interrupt_delay_timer = 5; 3798 3799 vha->flags.process_response_queue = 1; 3800 } else { 3801 /* Enable ZIO. */ 3802 if (!vha->flags.init_done) { 3803 ha->zio_mode = icb->add_firmware_options[0] & 3804 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 3805 ha->zio_timer = icb->interrupt_delay_timer ? 3806 icb->interrupt_delay_timer: 2; 3807 } 3808 icb->add_firmware_options[0] &= 3809 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 3810 vha->flags.process_response_queue = 0; 3811 if (ha->zio_mode != QLA_ZIO_DISABLED) { 3812 ha->zio_mode = QLA_ZIO_MODE_6; 3813 3814 ql_log(ql_log_info, vha, 0x0068, 3815 "ZIO mode %d enabled; timer delay (%d us).\n", 3816 ha->zio_mode, ha->zio_timer * 100); 3817 3818 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode; 3819 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer; 3820 vha->flags.process_response_queue = 1; 3821 } 3822 } 3823 3824 if (rval) { 3825 ql_log(ql_log_warn, vha, 0x0069, 3826 "NVRAM configuration failed.\n"); 3827 } 3828 return (rval); 3829 } 3830 3831 static void 3832 qla2x00_rport_del(void *data) 3833 { 3834 fc_port_t *fcport = data; 3835 struct fc_rport *rport; 3836 unsigned long flags; 3837 3838 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 3839 rport = fcport->drport ? fcport->drport: fcport->rport; 3840 fcport->drport = NULL; 3841 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 3842 if (rport) { 3843 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff, 3844 "%s %8phN. rport %p roles %x \n", 3845 __func__, fcport->port_name, rport, 3846 rport->roles); 3847 3848 fc_remote_port_delete(rport); 3849 } 3850 } 3851 3852 /** 3853 * qla2x00_alloc_fcport() - Allocate a generic fcport. 3854 * @ha: HA context 3855 * @flags: allocation flags 3856 * 3857 * Returns a pointer to the allocated fcport, or NULL, if none available. 3858 */ 3859 fc_port_t * 3860 qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags) 3861 { 3862 fc_port_t *fcport; 3863 3864 fcport = kzalloc(sizeof(fc_port_t), flags); 3865 if (!fcport) 3866 return NULL; 3867 3868 /* Setup fcport template structure. */ 3869 fcport->vha = vha; 3870 fcport->port_type = FCT_UNKNOWN; 3871 fcport->loop_id = FC_NO_LOOP_ID; 3872 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED); 3873 fcport->supported_classes = FC_COS_UNSPECIFIED; 3874 3875 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev, 3876 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma, 3877 flags); 3878 fcport->disc_state = DSC_DELETED; 3879 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 3880 fcport->deleted = QLA_SESS_DELETED; 3881 fcport->login_retry = vha->hw->login_retry_count; 3882 fcport->login_retry = 5; 3883 fcport->logout_on_delete = 1; 3884 3885 if (!fcport->ct_desc.ct_sns) { 3886 ql_log(ql_log_warn, vha, 0xffff, 3887 "Failed to allocate ct_sns request.\n"); 3888 kfree(fcport); 3889 fcport = NULL; 3890 } 3891 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn); 3892 INIT_LIST_HEAD(&fcport->gnl_entry); 3893 INIT_LIST_HEAD(&fcport->list); 3894 3895 return fcport; 3896 } 3897 3898 void 3899 qla2x00_free_fcport(fc_port_t *fcport) 3900 { 3901 if (fcport->ct_desc.ct_sns) { 3902 dma_free_coherent(&fcport->vha->hw->pdev->dev, 3903 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns, 3904 fcport->ct_desc.ct_sns_dma); 3905 3906 fcport->ct_desc.ct_sns = NULL; 3907 } 3908 kfree(fcport); 3909 } 3910 3911 /* 3912 * qla2x00_configure_loop 3913 * Updates Fibre Channel Device Database with what is actually on loop. 3914 * 3915 * Input: 3916 * ha = adapter block pointer. 3917 * 3918 * Returns: 3919 * 0 = success. 3920 * 1 = error. 3921 * 2 = database was full and device was not configured. 3922 */ 3923 static int 3924 qla2x00_configure_loop(scsi_qla_host_t *vha) 3925 { 3926 int rval; 3927 unsigned long flags, save_flags; 3928 struct qla_hw_data *ha = vha->hw; 3929 rval = QLA_SUCCESS; 3930 3931 /* Get Initiator ID */ 3932 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) { 3933 rval = qla2x00_configure_hba(vha); 3934 if (rval != QLA_SUCCESS) { 3935 ql_dbg(ql_dbg_disc, vha, 0x2013, 3936 "Unable to configure HBA.\n"); 3937 return (rval); 3938 } 3939 } 3940 3941 save_flags = flags = vha->dpc_flags; 3942 ql_dbg(ql_dbg_disc, vha, 0x2014, 3943 "Configure loop -- dpc flags = 0x%lx.\n", flags); 3944 3945 /* 3946 * If we have both an RSCN and PORT UPDATE pending then handle them 3947 * both at the same time. 3948 */ 3949 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 3950 clear_bit(RSCN_UPDATE, &vha->dpc_flags); 3951 3952 qla2x00_get_data_rate(vha); 3953 3954 /* Determine what we need to do */ 3955 if (ha->current_topology == ISP_CFG_FL && 3956 (test_bit(LOCAL_LOOP_UPDATE, &flags))) { 3957 3958 set_bit(RSCN_UPDATE, &flags); 3959 3960 } else if (ha->current_topology == ISP_CFG_F && 3961 (test_bit(LOCAL_LOOP_UPDATE, &flags))) { 3962 3963 set_bit(RSCN_UPDATE, &flags); 3964 clear_bit(LOCAL_LOOP_UPDATE, &flags); 3965 3966 } else if (ha->current_topology == ISP_CFG_N) { 3967 clear_bit(RSCN_UPDATE, &flags); 3968 } else if (ha->current_topology == ISP_CFG_NL) { 3969 clear_bit(RSCN_UPDATE, &flags); 3970 set_bit(LOCAL_LOOP_UPDATE, &flags); 3971 } else if (!vha->flags.online || 3972 (test_bit(ABORT_ISP_ACTIVE, &flags))) { 3973 set_bit(RSCN_UPDATE, &flags); 3974 set_bit(LOCAL_LOOP_UPDATE, &flags); 3975 } 3976 3977 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) { 3978 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 3979 ql_dbg(ql_dbg_disc, vha, 0x2015, 3980 "Loop resync needed, failing.\n"); 3981 rval = QLA_FUNCTION_FAILED; 3982 } else 3983 rval = qla2x00_configure_local_loop(vha); 3984 } 3985 3986 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) { 3987 if (LOOP_TRANSITION(vha)) { 3988 ql_dbg(ql_dbg_disc, vha, 0x201e, 3989 "Needs RSCN update and loop transition.\n"); 3990 rval = QLA_FUNCTION_FAILED; 3991 } 3992 else 3993 rval = qla2x00_configure_fabric(vha); 3994 } 3995 3996 if (rval == QLA_SUCCESS) { 3997 if (atomic_read(&vha->loop_down_timer) || 3998 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 3999 rval = QLA_FUNCTION_FAILED; 4000 } else { 4001 atomic_set(&vha->loop_state, LOOP_READY); 4002 ql_dbg(ql_dbg_disc, vha, 0x2069, 4003 "LOOP READY.\n"); 4004 ha->flags.fw_init_done = 1; 4005 4006 /* 4007 * Process any ATIO queue entries that came in 4008 * while we weren't online. 4009 */ 4010 if (qla_tgt_mode_enabled(vha) || 4011 qla_dual_mode_enabled(vha)) { 4012 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) { 4013 spin_lock_irqsave(&ha->tgt.atio_lock, 4014 flags); 4015 qlt_24xx_process_atio_queue(vha, 0); 4016 spin_unlock_irqrestore( 4017 &ha->tgt.atio_lock, flags); 4018 } else { 4019 spin_lock_irqsave(&ha->hardware_lock, 4020 flags); 4021 qlt_24xx_process_atio_queue(vha, 1); 4022 spin_unlock_irqrestore( 4023 &ha->hardware_lock, flags); 4024 } 4025 } 4026 } 4027 } 4028 4029 if (rval) { 4030 ql_dbg(ql_dbg_disc, vha, 0x206a, 4031 "%s *** FAILED ***.\n", __func__); 4032 } else { 4033 ql_dbg(ql_dbg_disc, vha, 0x206b, 4034 "%s: exiting normally.\n", __func__); 4035 } 4036 4037 /* Restore state if a resync event occurred during processing */ 4038 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 4039 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags)) 4040 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 4041 if (test_bit(RSCN_UPDATE, &save_flags)) { 4042 set_bit(RSCN_UPDATE, &vha->dpc_flags); 4043 } 4044 } 4045 4046 return (rval); 4047 } 4048 4049 4050 4051 /* 4052 * qla2x00_configure_local_loop 4053 * Updates Fibre Channel Device Database with local loop devices. 4054 * 4055 * Input: 4056 * ha = adapter block pointer. 4057 * 4058 * Returns: 4059 * 0 = success. 4060 */ 4061 static int 4062 qla2x00_configure_local_loop(scsi_qla_host_t *vha) 4063 { 4064 int rval, rval2; 4065 int found_devs; 4066 int found; 4067 fc_port_t *fcport, *new_fcport; 4068 4069 uint16_t index; 4070 uint16_t entries; 4071 char *id_iter; 4072 uint16_t loop_id; 4073 uint8_t domain, area, al_pa; 4074 struct qla_hw_data *ha = vha->hw; 4075 unsigned long flags; 4076 4077 found_devs = 0; 4078 new_fcport = NULL; 4079 entries = MAX_FIBRE_DEVICES_LOOP; 4080 4081 /* Get list of logged in devices. */ 4082 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha)); 4083 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma, 4084 &entries); 4085 if (rval != QLA_SUCCESS) 4086 goto cleanup_allocation; 4087 4088 ql_dbg(ql_dbg_disc, vha, 0x2017, 4089 "Entries in ID list (%d).\n", entries); 4090 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075, 4091 (uint8_t *)ha->gid_list, 4092 entries * sizeof(struct gid_list_info)); 4093 4094 /* Allocate temporary fcport for any new fcports discovered. */ 4095 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4096 if (new_fcport == NULL) { 4097 ql_log(ql_log_warn, vha, 0x2018, 4098 "Memory allocation failed for fcport.\n"); 4099 rval = QLA_MEMORY_ALLOC_FAILED; 4100 goto cleanup_allocation; 4101 } 4102 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 4103 4104 /* 4105 * Mark local devices that were present with FCF_DEVICE_LOST for now. 4106 */ 4107 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4108 if (atomic_read(&fcport->state) == FCS_ONLINE && 4109 fcport->port_type != FCT_BROADCAST && 4110 (fcport->flags & FCF_FABRIC_DEVICE) == 0) { 4111 4112 ql_dbg(ql_dbg_disc, vha, 0x2019, 4113 "Marking port lost loop_id=0x%04x.\n", 4114 fcport->loop_id); 4115 4116 qla2x00_mark_device_lost(vha, fcport, 0, 0); 4117 } 4118 } 4119 4120 /* Add devices to port list. */ 4121 id_iter = (char *)ha->gid_list; 4122 for (index = 0; index < entries; index++) { 4123 domain = ((struct gid_list_info *)id_iter)->domain; 4124 area = ((struct gid_list_info *)id_iter)->area; 4125 al_pa = ((struct gid_list_info *)id_iter)->al_pa; 4126 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 4127 loop_id = (uint16_t) 4128 ((struct gid_list_info *)id_iter)->loop_id_2100; 4129 else 4130 loop_id = le16_to_cpu( 4131 ((struct gid_list_info *)id_iter)->loop_id); 4132 id_iter += ha->gid_list_info_size; 4133 4134 /* Bypass reserved domain fields. */ 4135 if ((domain & 0xf0) == 0xf0) 4136 continue; 4137 4138 /* Bypass if not same domain and area of adapter. */ 4139 if (area && domain && 4140 (area != vha->d_id.b.area || domain != vha->d_id.b.domain)) 4141 continue; 4142 4143 /* Bypass invalid local loop ID. */ 4144 if (loop_id > LAST_LOCAL_LOOP_ID) 4145 continue; 4146 4147 memset(new_fcport->port_name, 0, WWN_SIZE); 4148 4149 /* Fill in member data. */ 4150 new_fcport->d_id.b.domain = domain; 4151 new_fcport->d_id.b.area = area; 4152 new_fcport->d_id.b.al_pa = al_pa; 4153 new_fcport->loop_id = loop_id; 4154 4155 rval2 = qla2x00_get_port_database(vha, new_fcport, 0); 4156 if (rval2 != QLA_SUCCESS) { 4157 ql_dbg(ql_dbg_disc, vha, 0x201a, 4158 "Failed to retrieve fcport information " 4159 "-- get_port_database=%x, loop_id=0x%04x.\n", 4160 rval2, new_fcport->loop_id); 4161 ql_dbg(ql_dbg_disc, vha, 0x201b, 4162 "Scheduling resync.\n"); 4163 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 4164 continue; 4165 } 4166 4167 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4168 /* Check for matching device in port list. */ 4169 found = 0; 4170 fcport = NULL; 4171 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4172 if (memcmp(new_fcport->port_name, fcport->port_name, 4173 WWN_SIZE)) 4174 continue; 4175 4176 fcport->flags &= ~FCF_FABRIC_DEVICE; 4177 fcport->loop_id = new_fcport->loop_id; 4178 fcport->port_type = new_fcport->port_type; 4179 fcport->d_id.b24 = new_fcport->d_id.b24; 4180 memcpy(fcport->node_name, new_fcport->node_name, 4181 WWN_SIZE); 4182 4183 if (!fcport->login_succ) { 4184 vha->fcport_count++; 4185 fcport->login_succ = 1; 4186 fcport->disc_state = DSC_LOGIN_COMPLETE; 4187 } 4188 4189 found++; 4190 break; 4191 } 4192 4193 if (!found) { 4194 /* New device, add to fcports list. */ 4195 list_add_tail(&new_fcport->list, &vha->vp_fcports); 4196 4197 /* Allocate a new replacement fcport. */ 4198 fcport = new_fcport; 4199 if (!fcport->login_succ) { 4200 vha->fcport_count++; 4201 fcport->login_succ = 1; 4202 fcport->disc_state = DSC_LOGIN_COMPLETE; 4203 } 4204 4205 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4206 4207 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4208 4209 if (new_fcport == NULL) { 4210 ql_log(ql_log_warn, vha, 0x201c, 4211 "Failed to allocate memory for fcport.\n"); 4212 rval = QLA_MEMORY_ALLOC_FAILED; 4213 goto cleanup_allocation; 4214 } 4215 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4216 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 4217 } 4218 4219 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4220 4221 /* Base iIDMA settings on HBA port speed. */ 4222 fcport->fp_speed = ha->link_data_rate; 4223 4224 qla2x00_update_fcport(vha, fcport); 4225 4226 found_devs++; 4227 } 4228 4229 cleanup_allocation: 4230 kfree(new_fcport); 4231 4232 if (rval != QLA_SUCCESS) { 4233 ql_dbg(ql_dbg_disc, vha, 0x201d, 4234 "Configure local loop error exit: rval=%x.\n", rval); 4235 } 4236 4237 return (rval); 4238 } 4239 4240 static void 4241 qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 4242 { 4243 int rval; 4244 uint16_t mb[MAILBOX_REGISTER_COUNT]; 4245 struct qla_hw_data *ha = vha->hw; 4246 4247 if (!IS_IIDMA_CAPABLE(ha)) 4248 return; 4249 4250 if (atomic_read(&fcport->state) != FCS_ONLINE) 4251 return; 4252 4253 if (fcport->fp_speed == PORT_SPEED_UNKNOWN || 4254 fcport->fp_speed > ha->link_data_rate) 4255 return; 4256 4257 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed, 4258 mb); 4259 if (rval != QLA_SUCCESS) { 4260 ql_dbg(ql_dbg_disc, vha, 0x2004, 4261 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n", 4262 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]); 4263 } else { 4264 ql_dbg(ql_dbg_disc, vha, 0x2005, 4265 "iIDMA adjusted to %s GB/s on %8phN.\n", 4266 qla2x00_get_link_speed_str(ha, fcport->fp_speed), 4267 fcport->port_name); 4268 } 4269 } 4270 4271 /* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/ 4272 static void 4273 qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport) 4274 { 4275 struct fc_rport_identifiers rport_ids; 4276 struct fc_rport *rport; 4277 unsigned long flags; 4278 4279 rport_ids.node_name = wwn_to_u64(fcport->node_name); 4280 rport_ids.port_name = wwn_to_u64(fcport->port_name); 4281 rport_ids.port_id = fcport->d_id.b.domain << 16 | 4282 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa; 4283 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; 4284 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids); 4285 if (!rport) { 4286 ql_log(ql_log_warn, vha, 0x2006, 4287 "Unable to allocate fc remote port.\n"); 4288 return; 4289 } 4290 4291 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 4292 *((fc_port_t **)rport->dd_data) = fcport; 4293 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 4294 4295 rport->supported_classes = fcport->supported_classes; 4296 4297 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; 4298 if (fcport->port_type == FCT_INITIATOR) 4299 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR; 4300 if (fcport->port_type == FCT_TARGET) 4301 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET; 4302 4303 ql_dbg(ql_dbg_disc, vha, 0xffff, 4304 "%s %8phN. rport %p is %s mode \n", 4305 __func__, fcport->port_name, rport, 4306 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini"); 4307 4308 fc_remote_port_rolechg(rport, rport_ids.roles); 4309 } 4310 4311 /* 4312 * qla2x00_update_fcport 4313 * Updates device on list. 4314 * 4315 * Input: 4316 * ha = adapter block pointer. 4317 * fcport = port structure pointer. 4318 * 4319 * Return: 4320 * 0 - Success 4321 * BIT_0 - error 4322 * 4323 * Context: 4324 * Kernel context. 4325 */ 4326 void 4327 qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 4328 { 4329 fcport->vha = vha; 4330 4331 if (IS_SW_RESV_ADDR(fcport->d_id)) 4332 return; 4333 4334 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %8phC \n", 4335 __func__, fcport->port_name); 4336 4337 if (IS_QLAFX00(vha->hw)) { 4338 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 4339 goto reg_port; 4340 } 4341 fcport->login_retry = 0; 4342 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 4343 fcport->disc_state = DSC_LOGIN_COMPLETE; 4344 fcport->deleted = 0; 4345 fcport->logout_on_delete = 1; 4346 4347 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 4348 qla2x00_iidma_fcport(vha, fcport); 4349 qla24xx_update_fcport_fcp_prio(vha, fcport); 4350 4351 reg_port: 4352 switch (vha->host->active_mode) { 4353 case MODE_INITIATOR: 4354 qla2x00_reg_remote_port(vha, fcport); 4355 break; 4356 case MODE_TARGET: 4357 if (!vha->vha_tgt.qla_tgt->tgt_stop && 4358 !vha->vha_tgt.qla_tgt->tgt_stopped) 4359 qlt_fc_port_added(vha, fcport); 4360 break; 4361 case MODE_DUAL: 4362 qla2x00_reg_remote_port(vha, fcport); 4363 if (!vha->vha_tgt.qla_tgt->tgt_stop && 4364 !vha->vha_tgt.qla_tgt->tgt_stopped) 4365 qlt_fc_port_added(vha, fcport); 4366 break; 4367 default: 4368 break; 4369 } 4370 } 4371 4372 /* 4373 * qla2x00_configure_fabric 4374 * Setup SNS devices with loop ID's. 4375 * 4376 * Input: 4377 * ha = adapter block pointer. 4378 * 4379 * Returns: 4380 * 0 = success. 4381 * BIT_0 = error 4382 */ 4383 static int 4384 qla2x00_configure_fabric(scsi_qla_host_t *vha) 4385 { 4386 int rval; 4387 fc_port_t *fcport; 4388 uint16_t mb[MAILBOX_REGISTER_COUNT]; 4389 uint16_t loop_id; 4390 LIST_HEAD(new_fcports); 4391 struct qla_hw_data *ha = vha->hw; 4392 int discovery_gen; 4393 4394 /* If FL port exists, then SNS is present */ 4395 if (IS_FWI2_CAPABLE(ha)) 4396 loop_id = NPH_F_PORT; 4397 else 4398 loop_id = SNS_FL_PORT; 4399 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1); 4400 if (rval != QLA_SUCCESS) { 4401 ql_dbg(ql_dbg_disc, vha, 0x201f, 4402 "MBX_GET_PORT_NAME failed, No FL Port.\n"); 4403 4404 vha->device_flags &= ~SWITCH_FOUND; 4405 return (QLA_SUCCESS); 4406 } 4407 vha->device_flags |= SWITCH_FOUND; 4408 4409 4410 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) { 4411 rval = qla2x00_send_change_request(vha, 0x3, 0); 4412 if (rval != QLA_SUCCESS) 4413 ql_log(ql_log_warn, vha, 0x121, 4414 "Failed to enable receiving of RSCN requests: 0x%x.\n", 4415 rval); 4416 } 4417 4418 4419 do { 4420 qla2x00_mgmt_svr_login(vha); 4421 4422 /* FDMI support. */ 4423 if (ql2xfdmienable && 4424 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags)) 4425 qla2x00_fdmi_register(vha); 4426 4427 /* Ensure we are logged into the SNS. */ 4428 if (IS_FWI2_CAPABLE(ha)) 4429 loop_id = NPH_SNS; 4430 else 4431 loop_id = SIMPLE_NAME_SERVER; 4432 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff, 4433 0xfc, mb, BIT_1|BIT_0); 4434 if (rval != QLA_SUCCESS) { 4435 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 4436 return rval; 4437 } 4438 if (mb[0] != MBS_COMMAND_COMPLETE) { 4439 ql_dbg(ql_dbg_disc, vha, 0x2042, 4440 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x " 4441 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1], 4442 mb[2], mb[6], mb[7]); 4443 return (QLA_SUCCESS); 4444 } 4445 4446 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) { 4447 if (qla2x00_rft_id(vha)) { 4448 /* EMPTY */ 4449 ql_dbg(ql_dbg_disc, vha, 0x2045, 4450 "Register FC-4 TYPE failed.\n"); 4451 } 4452 if (qla2x00_rff_id(vha)) { 4453 /* EMPTY */ 4454 ql_dbg(ql_dbg_disc, vha, 0x2049, 4455 "Register FC-4 Features failed.\n"); 4456 } 4457 if (qla2x00_rnn_id(vha)) { 4458 /* EMPTY */ 4459 ql_dbg(ql_dbg_disc, vha, 0x204f, 4460 "Register Node Name failed.\n"); 4461 } else if (qla2x00_rsnn_nn(vha)) { 4462 /* EMPTY */ 4463 ql_dbg(ql_dbg_disc, vha, 0x2053, 4464 "Register Symobilic Node Name failed.\n"); 4465 } 4466 } 4467 4468 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4469 fcport->scan_state = QLA_FCPORT_SCAN; 4470 } 4471 4472 /* Mark the time right before querying FW for connected ports. 4473 * This process is long, asynchronous and by the time it's done, 4474 * collected information might not be accurate anymore. E.g. 4475 * disconnected port might have re-connected and a brand new 4476 * session has been created. In this case session's generation 4477 * will be newer than discovery_gen. */ 4478 qlt_do_generation_tick(vha, &discovery_gen); 4479 4480 rval = qla2x00_find_all_fabric_devs(vha); 4481 if (rval != QLA_SUCCESS) 4482 break; 4483 } while (0); 4484 4485 if (rval) 4486 ql_dbg(ql_dbg_disc, vha, 0x2068, 4487 "Configure fabric error exit rval=%d.\n", rval); 4488 4489 return (rval); 4490 } 4491 4492 /* 4493 * qla2x00_find_all_fabric_devs 4494 * 4495 * Input: 4496 * ha = adapter block pointer. 4497 * dev = database device entry pointer. 4498 * 4499 * Returns: 4500 * 0 = success. 4501 * 4502 * Context: 4503 * Kernel context. 4504 */ 4505 static int 4506 qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha) 4507 { 4508 int rval; 4509 uint16_t loop_id; 4510 fc_port_t *fcport, *new_fcport; 4511 int found; 4512 4513 sw_info_t *swl; 4514 int swl_idx; 4515 int first_dev, last_dev; 4516 port_id_t wrap = {}, nxt_d_id; 4517 struct qla_hw_data *ha = vha->hw; 4518 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 4519 unsigned long flags; 4520 4521 rval = QLA_SUCCESS; 4522 4523 /* Try GID_PT to get device list, else GAN. */ 4524 if (!ha->swl) 4525 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t), 4526 GFP_KERNEL); 4527 swl = ha->swl; 4528 if (!swl) { 4529 /*EMPTY*/ 4530 ql_dbg(ql_dbg_disc, vha, 0x2054, 4531 "GID_PT allocations failed, fallback on GA_NXT.\n"); 4532 } else { 4533 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t)); 4534 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) { 4535 swl = NULL; 4536 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) { 4537 swl = NULL; 4538 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) { 4539 swl = NULL; 4540 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) { 4541 swl = NULL; 4542 } 4543 4544 /* If other queries succeeded probe for FC-4 type */ 4545 if (swl) 4546 qla2x00_gff_id(vha, swl); 4547 } 4548 swl_idx = 0; 4549 4550 /* Allocate temporary fcport for any new fcports discovered. */ 4551 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4552 if (new_fcport == NULL) { 4553 ql_log(ql_log_warn, vha, 0x205e, 4554 "Failed to allocate memory for fcport.\n"); 4555 return (QLA_MEMORY_ALLOC_FAILED); 4556 } 4557 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 4558 /* Set start port ID scan at adapter ID. */ 4559 first_dev = 1; 4560 last_dev = 0; 4561 4562 /* Starting free loop ID. */ 4563 loop_id = ha->min_external_loopid; 4564 for (; loop_id <= ha->max_loop_id; loop_id++) { 4565 if (qla2x00_is_reserved_id(vha, loop_id)) 4566 continue; 4567 4568 if (ha->current_topology == ISP_CFG_FL && 4569 (atomic_read(&vha->loop_down_timer) || 4570 LOOP_TRANSITION(vha))) { 4571 atomic_set(&vha->loop_down_timer, 0); 4572 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 4573 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 4574 break; 4575 } 4576 4577 if (swl != NULL) { 4578 if (last_dev) { 4579 wrap.b24 = new_fcport->d_id.b24; 4580 } else { 4581 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24; 4582 memcpy(new_fcport->node_name, 4583 swl[swl_idx].node_name, WWN_SIZE); 4584 memcpy(new_fcport->port_name, 4585 swl[swl_idx].port_name, WWN_SIZE); 4586 memcpy(new_fcport->fabric_port_name, 4587 swl[swl_idx].fabric_port_name, WWN_SIZE); 4588 new_fcport->fp_speed = swl[swl_idx].fp_speed; 4589 new_fcport->fc4_type = swl[swl_idx].fc4_type; 4590 4591 if (swl[swl_idx].d_id.b.rsvd_1 != 0) { 4592 last_dev = 1; 4593 } 4594 swl_idx++; 4595 } 4596 } else { 4597 /* Send GA_NXT to the switch */ 4598 rval = qla2x00_ga_nxt(vha, new_fcport); 4599 if (rval != QLA_SUCCESS) { 4600 ql_log(ql_log_warn, vha, 0x2064, 4601 "SNS scan failed -- assuming " 4602 "zero-entry result.\n"); 4603 rval = QLA_SUCCESS; 4604 break; 4605 } 4606 } 4607 4608 /* If wrap on switch device list, exit. */ 4609 if (first_dev) { 4610 wrap.b24 = new_fcport->d_id.b24; 4611 first_dev = 0; 4612 } else if (new_fcport->d_id.b24 == wrap.b24) { 4613 ql_dbg(ql_dbg_disc, vha, 0x2065, 4614 "Device wrap (%02x%02x%02x).\n", 4615 new_fcport->d_id.b.domain, 4616 new_fcport->d_id.b.area, 4617 new_fcport->d_id.b.al_pa); 4618 break; 4619 } 4620 4621 /* Bypass if same physical adapter. */ 4622 if (new_fcport->d_id.b24 == base_vha->d_id.b24) 4623 continue; 4624 4625 /* Bypass virtual ports of the same host. */ 4626 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24)) 4627 continue; 4628 4629 /* Bypass if same domain and area of adapter. */ 4630 if (((new_fcport->d_id.b24 & 0xffff00) == 4631 (vha->d_id.b24 & 0xffff00)) && ha->current_topology == 4632 ISP_CFG_FL) 4633 continue; 4634 4635 /* Bypass reserved domain fields. */ 4636 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0) 4637 continue; 4638 4639 /* Bypass ports whose FCP-4 type is not FCP_SCSI */ 4640 if (ql2xgffidenable && 4641 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI && 4642 new_fcport->fc4_type != FC4_TYPE_UNKNOWN)) 4643 continue; 4644 4645 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4646 4647 /* Locate matching device in database. */ 4648 found = 0; 4649 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4650 if (memcmp(new_fcport->port_name, fcport->port_name, 4651 WWN_SIZE)) 4652 continue; 4653 4654 fcport->scan_state = QLA_FCPORT_FOUND; 4655 4656 found++; 4657 4658 /* Update port state. */ 4659 memcpy(fcport->fabric_port_name, 4660 new_fcport->fabric_port_name, WWN_SIZE); 4661 fcport->fp_speed = new_fcport->fp_speed; 4662 4663 /* 4664 * If address the same and state FCS_ONLINE 4665 * (or in target mode), nothing changed. 4666 */ 4667 if (fcport->d_id.b24 == new_fcport->d_id.b24 && 4668 (atomic_read(&fcport->state) == FCS_ONLINE || 4669 (vha->host->active_mode == MODE_TARGET))) { 4670 break; 4671 } 4672 4673 /* 4674 * If device was not a fabric device before. 4675 */ 4676 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) { 4677 fcport->d_id.b24 = new_fcport->d_id.b24; 4678 qla2x00_clear_loop_id(fcport); 4679 fcport->flags |= (FCF_FABRIC_DEVICE | 4680 FCF_LOGIN_NEEDED); 4681 break; 4682 } 4683 4684 /* 4685 * Port ID changed or device was marked to be updated; 4686 * Log it out if still logged in and mark it for 4687 * relogin later. 4688 */ 4689 if (qla_tgt_mode_enabled(base_vha)) { 4690 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080, 4691 "port changed FC ID, %8phC" 4692 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n", 4693 fcport->port_name, 4694 fcport->d_id.b.domain, 4695 fcport->d_id.b.area, 4696 fcport->d_id.b.al_pa, 4697 fcport->loop_id, 4698 new_fcport->d_id.b.domain, 4699 new_fcport->d_id.b.area, 4700 new_fcport->d_id.b.al_pa); 4701 fcport->d_id.b24 = new_fcport->d_id.b24; 4702 break; 4703 } 4704 4705 fcport->d_id.b24 = new_fcport->d_id.b24; 4706 fcport->flags |= FCF_LOGIN_NEEDED; 4707 break; 4708 } 4709 4710 if (found) { 4711 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4712 continue; 4713 } 4714 /* If device was not in our fcports list, then add it. */ 4715 new_fcport->scan_state = QLA_FCPORT_FOUND; 4716 list_add_tail(&new_fcport->list, &vha->vp_fcports); 4717 4718 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4719 4720 4721 /* Allocate a new replacement fcport. */ 4722 nxt_d_id.b24 = new_fcport->d_id.b24; 4723 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4724 if (new_fcport == NULL) { 4725 ql_log(ql_log_warn, vha, 0x2066, 4726 "Memory allocation failed for fcport.\n"); 4727 return (QLA_MEMORY_ALLOC_FAILED); 4728 } 4729 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 4730 new_fcport->d_id.b24 = nxt_d_id.b24; 4731 } 4732 4733 qla2x00_free_fcport(new_fcport); 4734 4735 /* 4736 * Logout all previous fabric dev marked lost, except FCP2 devices. 4737 */ 4738 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4739 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 4740 break; 4741 4742 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 || 4743 (fcport->flags & FCF_LOGIN_NEEDED) == 0) 4744 continue; 4745 4746 if (fcport->scan_state == QLA_FCPORT_SCAN) { 4747 if ((qla_dual_mode_enabled(vha) || 4748 qla_ini_mode_enabled(vha)) && 4749 atomic_read(&fcport->state) == FCS_ONLINE) { 4750 qla2x00_mark_device_lost(vha, fcport, 4751 ql2xplogiabsentdevice, 0); 4752 if (fcport->loop_id != FC_NO_LOOP_ID && 4753 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 4754 fcport->port_type != FCT_INITIATOR && 4755 fcport->port_type != FCT_BROADCAST) { 4756 ql_dbg(ql_dbg_disc, vha, 0xffff, 4757 "%s %d %8phC post del sess\n", 4758 __func__, __LINE__, 4759 fcport->port_name); 4760 4761 qlt_schedule_sess_for_deletion_lock 4762 (fcport); 4763 continue; 4764 } 4765 } 4766 } 4767 4768 if (fcport->scan_state == QLA_FCPORT_FOUND) 4769 qla24xx_fcport_handle_login(vha, fcport); 4770 } 4771 return (rval); 4772 } 4773 4774 /* 4775 * qla2x00_find_new_loop_id 4776 * Scan through our port list and find a new usable loop ID. 4777 * 4778 * Input: 4779 * ha: adapter state pointer. 4780 * dev: port structure pointer. 4781 * 4782 * Returns: 4783 * qla2x00 local function return status code. 4784 * 4785 * Context: 4786 * Kernel context. 4787 */ 4788 int 4789 qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) 4790 { 4791 int rval; 4792 struct qla_hw_data *ha = vha->hw; 4793 unsigned long flags = 0; 4794 4795 rval = QLA_SUCCESS; 4796 4797 spin_lock_irqsave(&ha->vport_slock, flags); 4798 4799 dev->loop_id = find_first_zero_bit(ha->loop_id_map, 4800 LOOPID_MAP_SIZE); 4801 if (dev->loop_id >= LOOPID_MAP_SIZE || 4802 qla2x00_is_reserved_id(vha, dev->loop_id)) { 4803 dev->loop_id = FC_NO_LOOP_ID; 4804 rval = QLA_FUNCTION_FAILED; 4805 } else 4806 set_bit(dev->loop_id, ha->loop_id_map); 4807 4808 spin_unlock_irqrestore(&ha->vport_slock, flags); 4809 4810 if (rval == QLA_SUCCESS) 4811 ql_dbg(ql_dbg_disc, dev->vha, 0x2086, 4812 "Assigning new loopid=%x, portid=%x.\n", 4813 dev->loop_id, dev->d_id.b24); 4814 else 4815 ql_log(ql_log_warn, dev->vha, 0x2087, 4816 "No loop_id's available, portid=%x.\n", 4817 dev->d_id.b24); 4818 4819 return (rval); 4820 } 4821 4822 4823 /* 4824 * qla2x00_fabric_login 4825 * Issue fabric login command. 4826 * 4827 * Input: 4828 * ha = adapter block pointer. 4829 * device = pointer to FC device type structure. 4830 * 4831 * Returns: 4832 * 0 - Login successfully 4833 * 1 - Login failed 4834 * 2 - Initiator device 4835 * 3 - Fatal error 4836 */ 4837 int 4838 qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport, 4839 uint16_t *next_loopid) 4840 { 4841 int rval; 4842 int retry; 4843 uint16_t tmp_loopid; 4844 uint16_t mb[MAILBOX_REGISTER_COUNT]; 4845 struct qla_hw_data *ha = vha->hw; 4846 4847 retry = 0; 4848 tmp_loopid = 0; 4849 4850 for (;;) { 4851 ql_dbg(ql_dbg_disc, vha, 0x2000, 4852 "Trying Fabric Login w/loop id 0x%04x for port " 4853 "%02x%02x%02x.\n", 4854 fcport->loop_id, fcport->d_id.b.domain, 4855 fcport->d_id.b.area, fcport->d_id.b.al_pa); 4856 4857 /* Login fcport on switch. */ 4858 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id, 4859 fcport->d_id.b.domain, fcport->d_id.b.area, 4860 fcport->d_id.b.al_pa, mb, BIT_0); 4861 if (rval != QLA_SUCCESS) { 4862 return rval; 4863 } 4864 if (mb[0] == MBS_PORT_ID_USED) { 4865 /* 4866 * Device has another loop ID. The firmware team 4867 * recommends the driver perform an implicit login with 4868 * the specified ID again. The ID we just used is save 4869 * here so we return with an ID that can be tried by 4870 * the next login. 4871 */ 4872 retry++; 4873 tmp_loopid = fcport->loop_id; 4874 fcport->loop_id = mb[1]; 4875 4876 ql_dbg(ql_dbg_disc, vha, 0x2001, 4877 "Fabric Login: port in use - next loop " 4878 "id=0x%04x, port id= %02x%02x%02x.\n", 4879 fcport->loop_id, fcport->d_id.b.domain, 4880 fcport->d_id.b.area, fcport->d_id.b.al_pa); 4881 4882 } else if (mb[0] == MBS_COMMAND_COMPLETE) { 4883 /* 4884 * Login succeeded. 4885 */ 4886 if (retry) { 4887 /* A retry occurred before. */ 4888 *next_loopid = tmp_loopid; 4889 } else { 4890 /* 4891 * No retry occurred before. Just increment the 4892 * ID value for next login. 4893 */ 4894 *next_loopid = (fcport->loop_id + 1); 4895 } 4896 4897 if (mb[1] & BIT_0) { 4898 fcport->port_type = FCT_INITIATOR; 4899 } else { 4900 fcport->port_type = FCT_TARGET; 4901 if (mb[1] & BIT_1) { 4902 fcport->flags |= FCF_FCP2_DEVICE; 4903 } 4904 } 4905 4906 if (mb[10] & BIT_0) 4907 fcport->supported_classes |= FC_COS_CLASS2; 4908 if (mb[10] & BIT_1) 4909 fcport->supported_classes |= FC_COS_CLASS3; 4910 4911 if (IS_FWI2_CAPABLE(ha)) { 4912 if (mb[10] & BIT_7) 4913 fcport->flags |= 4914 FCF_CONF_COMP_SUPPORTED; 4915 } 4916 4917 rval = QLA_SUCCESS; 4918 break; 4919 } else if (mb[0] == MBS_LOOP_ID_USED) { 4920 /* 4921 * Loop ID already used, try next loop ID. 4922 */ 4923 fcport->loop_id++; 4924 rval = qla2x00_find_new_loop_id(vha, fcport); 4925 if (rval != QLA_SUCCESS) { 4926 /* Ran out of loop IDs to use */ 4927 break; 4928 } 4929 } else if (mb[0] == MBS_COMMAND_ERROR) { 4930 /* 4931 * Firmware possibly timed out during login. If NO 4932 * retries are left to do then the device is declared 4933 * dead. 4934 */ 4935 *next_loopid = fcport->loop_id; 4936 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 4937 fcport->d_id.b.domain, fcport->d_id.b.area, 4938 fcport->d_id.b.al_pa); 4939 qla2x00_mark_device_lost(vha, fcport, 1, 0); 4940 4941 rval = 1; 4942 break; 4943 } else { 4944 /* 4945 * unrecoverable / not handled error 4946 */ 4947 ql_dbg(ql_dbg_disc, vha, 0x2002, 4948 "Failed=%x port_id=%02x%02x%02x loop_id=%x " 4949 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain, 4950 fcport->d_id.b.area, fcport->d_id.b.al_pa, 4951 fcport->loop_id, jiffies); 4952 4953 *next_loopid = fcport->loop_id; 4954 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 4955 fcport->d_id.b.domain, fcport->d_id.b.area, 4956 fcport->d_id.b.al_pa); 4957 qla2x00_clear_loop_id(fcport); 4958 fcport->login_retry = 0; 4959 4960 rval = 3; 4961 break; 4962 } 4963 } 4964 4965 return (rval); 4966 } 4967 4968 /* 4969 * qla2x00_local_device_login 4970 * Issue local device login command. 4971 * 4972 * Input: 4973 * ha = adapter block pointer. 4974 * loop_id = loop id of device to login to. 4975 * 4976 * Returns (Where's the #define!!!!): 4977 * 0 - Login successfully 4978 * 1 - Login failed 4979 * 3 - Fatal error 4980 */ 4981 int 4982 qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport) 4983 { 4984 int rval; 4985 uint16_t mb[MAILBOX_REGISTER_COUNT]; 4986 4987 memset(mb, 0, sizeof(mb)); 4988 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0); 4989 if (rval == QLA_SUCCESS) { 4990 /* Interrogate mailbox registers for any errors */ 4991 if (mb[0] == MBS_COMMAND_ERROR) 4992 rval = 1; 4993 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR) 4994 /* device not in PCB table */ 4995 rval = 3; 4996 } 4997 4998 return (rval); 4999 } 5000 5001 /* 5002 * qla2x00_loop_resync 5003 * Resync with fibre channel devices. 5004 * 5005 * Input: 5006 * ha = adapter block pointer. 5007 * 5008 * Returns: 5009 * 0 = success 5010 */ 5011 int 5012 qla2x00_loop_resync(scsi_qla_host_t *vha) 5013 { 5014 int rval = QLA_SUCCESS; 5015 uint32_t wait_time; 5016 struct req_que *req; 5017 struct rsp_que *rsp; 5018 5019 req = vha->req; 5020 rsp = req->rsp; 5021 5022 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 5023 if (vha->flags.online) { 5024 if (!(rval = qla2x00_fw_ready(vha))) { 5025 /* Wait at most MAX_TARGET RSCNs for a stable link. */ 5026 wait_time = 256; 5027 do { 5028 if (!IS_QLAFX00(vha->hw)) { 5029 /* 5030 * Issue a marker after FW becomes 5031 * ready. 5032 */ 5033 qla2x00_marker(vha, req, rsp, 0, 0, 5034 MK_SYNC_ALL); 5035 vha->marker_needed = 0; 5036 } 5037 5038 /* Remap devices on Loop. */ 5039 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5040 5041 if (IS_QLAFX00(vha->hw)) 5042 qlafx00_configure_devices(vha); 5043 else 5044 qla2x00_configure_loop(vha); 5045 5046 wait_time--; 5047 } while (!atomic_read(&vha->loop_down_timer) && 5048 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 5049 && wait_time && (test_bit(LOOP_RESYNC_NEEDED, 5050 &vha->dpc_flags))); 5051 } 5052 } 5053 5054 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 5055 return (QLA_FUNCTION_FAILED); 5056 5057 if (rval) 5058 ql_dbg(ql_dbg_disc, vha, 0x206c, 5059 "%s *** FAILED ***.\n", __func__); 5060 5061 return (rval); 5062 } 5063 5064 /* 5065 * qla2x00_perform_loop_resync 5066 * Description: This function will set the appropriate flags and call 5067 * qla2x00_loop_resync. If successful loop will be resynced 5068 * Arguments : scsi_qla_host_t pointer 5069 * returm : Success or Failure 5070 */ 5071 5072 int qla2x00_perform_loop_resync(scsi_qla_host_t *ha) 5073 { 5074 int32_t rval = 0; 5075 5076 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) { 5077 /*Configure the flags so that resync happens properly*/ 5078 atomic_set(&ha->loop_down_timer, 0); 5079 if (!(ha->device_flags & DFLG_NO_CABLE)) { 5080 atomic_set(&ha->loop_state, LOOP_UP); 5081 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); 5082 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); 5083 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); 5084 5085 rval = qla2x00_loop_resync(ha); 5086 } else 5087 atomic_set(&ha->loop_state, LOOP_DEAD); 5088 5089 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags); 5090 } 5091 5092 return rval; 5093 } 5094 5095 void 5096 qla2x00_update_fcports(scsi_qla_host_t *base_vha) 5097 { 5098 fc_port_t *fcport; 5099 struct scsi_qla_host *vha; 5100 struct qla_hw_data *ha = base_vha->hw; 5101 unsigned long flags; 5102 5103 spin_lock_irqsave(&ha->vport_slock, flags); 5104 /* Go with deferred removal of rport references. */ 5105 list_for_each_entry(vha, &base_vha->hw->vp_list, list) { 5106 atomic_inc(&vha->vref_count); 5107 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5108 if (fcport->drport && 5109 atomic_read(&fcport->state) != FCS_UNCONFIGURED) { 5110 spin_unlock_irqrestore(&ha->vport_slock, flags); 5111 qla2x00_rport_del(fcport); 5112 5113 spin_lock_irqsave(&ha->vport_slock, flags); 5114 } 5115 } 5116 atomic_dec(&vha->vref_count); 5117 wake_up(&vha->vref_waitq); 5118 } 5119 spin_unlock_irqrestore(&ha->vport_slock, flags); 5120 } 5121 5122 /* Assumes idc_lock always held on entry */ 5123 void 5124 qla83xx_reset_ownership(scsi_qla_host_t *vha) 5125 { 5126 struct qla_hw_data *ha = vha->hw; 5127 uint32_t drv_presence, drv_presence_mask; 5128 uint32_t dev_part_info1, dev_part_info2, class_type; 5129 uint32_t class_type_mask = 0x3; 5130 uint16_t fcoe_other_function = 0xffff, i; 5131 5132 if (IS_QLA8044(ha)) { 5133 drv_presence = qla8044_rd_direct(vha, 5134 QLA8044_CRB_DRV_ACTIVE_INDEX); 5135 dev_part_info1 = qla8044_rd_direct(vha, 5136 QLA8044_CRB_DEV_PART_INFO_INDEX); 5137 dev_part_info2 = qla8044_rd_direct(vha, 5138 QLA8044_CRB_DEV_PART_INFO2); 5139 } else { 5140 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5141 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1); 5142 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2); 5143 } 5144 for (i = 0; i < 8; i++) { 5145 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask); 5146 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 5147 (i != ha->portnum)) { 5148 fcoe_other_function = i; 5149 break; 5150 } 5151 } 5152 if (fcoe_other_function == 0xffff) { 5153 for (i = 0; i < 8; i++) { 5154 class_type = ((dev_part_info2 >> (i * 4)) & 5155 class_type_mask); 5156 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 5157 ((i + 8) != ha->portnum)) { 5158 fcoe_other_function = i + 8; 5159 break; 5160 } 5161 } 5162 } 5163 /* 5164 * Prepare drv-presence mask based on fcoe functions present. 5165 * However consider only valid physical fcoe function numbers (0-15). 5166 */ 5167 drv_presence_mask = ~((1 << (ha->portnum)) | 5168 ((fcoe_other_function == 0xffff) ? 5169 0 : (1 << (fcoe_other_function)))); 5170 5171 /* We are the reset owner iff: 5172 * - No other protocol drivers present. 5173 * - This is the lowest among fcoe functions. */ 5174 if (!(drv_presence & drv_presence_mask) && 5175 (ha->portnum < fcoe_other_function)) { 5176 ql_dbg(ql_dbg_p3p, vha, 0xb07f, 5177 "This host is Reset owner.\n"); 5178 ha->flags.nic_core_reset_owner = 1; 5179 } 5180 } 5181 5182 static int 5183 __qla83xx_set_drv_ack(scsi_qla_host_t *vha) 5184 { 5185 int rval = QLA_SUCCESS; 5186 struct qla_hw_data *ha = vha->hw; 5187 uint32_t drv_ack; 5188 5189 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5190 if (rval == QLA_SUCCESS) { 5191 drv_ack |= (1 << ha->portnum); 5192 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 5193 } 5194 5195 return rval; 5196 } 5197 5198 static int 5199 __qla83xx_clear_drv_ack(scsi_qla_host_t *vha) 5200 { 5201 int rval = QLA_SUCCESS; 5202 struct qla_hw_data *ha = vha->hw; 5203 uint32_t drv_ack; 5204 5205 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5206 if (rval == QLA_SUCCESS) { 5207 drv_ack &= ~(1 << ha->portnum); 5208 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 5209 } 5210 5211 return rval; 5212 } 5213 5214 static const char * 5215 qla83xx_dev_state_to_string(uint32_t dev_state) 5216 { 5217 switch (dev_state) { 5218 case QLA8XXX_DEV_COLD: 5219 return "COLD/RE-INIT"; 5220 case QLA8XXX_DEV_INITIALIZING: 5221 return "INITIALIZING"; 5222 case QLA8XXX_DEV_READY: 5223 return "READY"; 5224 case QLA8XXX_DEV_NEED_RESET: 5225 return "NEED RESET"; 5226 case QLA8XXX_DEV_NEED_QUIESCENT: 5227 return "NEED QUIESCENT"; 5228 case QLA8XXX_DEV_FAILED: 5229 return "FAILED"; 5230 case QLA8XXX_DEV_QUIESCENT: 5231 return "QUIESCENT"; 5232 default: 5233 return "Unknown"; 5234 } 5235 } 5236 5237 /* Assumes idc-lock always held on entry */ 5238 void 5239 qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type) 5240 { 5241 struct qla_hw_data *ha = vha->hw; 5242 uint32_t idc_audit_reg = 0, duration_secs = 0; 5243 5244 switch (audit_type) { 5245 case IDC_AUDIT_TIMESTAMP: 5246 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000); 5247 idc_audit_reg = (ha->portnum) | 5248 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8); 5249 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 5250 break; 5251 5252 case IDC_AUDIT_COMPLETION: 5253 duration_secs = ((jiffies_to_msecs(jiffies) - 5254 jiffies_to_msecs(ha->idc_audit_ts)) / 1000); 5255 idc_audit_reg = (ha->portnum) | 5256 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8); 5257 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 5258 break; 5259 5260 default: 5261 ql_log(ql_log_warn, vha, 0xb078, 5262 "Invalid audit type specified.\n"); 5263 break; 5264 } 5265 } 5266 5267 /* Assumes idc_lock always held on entry */ 5268 static int 5269 qla83xx_initiating_reset(scsi_qla_host_t *vha) 5270 { 5271 struct qla_hw_data *ha = vha->hw; 5272 uint32_t idc_control, dev_state; 5273 5274 __qla83xx_get_idc_control(vha, &idc_control); 5275 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) { 5276 ql_log(ql_log_info, vha, 0xb080, 5277 "NIC Core reset has been disabled. idc-control=0x%x\n", 5278 idc_control); 5279 return QLA_FUNCTION_FAILED; 5280 } 5281 5282 /* Set NEED-RESET iff in READY state and we are the reset-owner */ 5283 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5284 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) { 5285 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 5286 QLA8XXX_DEV_NEED_RESET); 5287 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n"); 5288 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP); 5289 } else { 5290 const char *state = qla83xx_dev_state_to_string(dev_state); 5291 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state); 5292 5293 /* SV: XXX: Is timeout required here? */ 5294 /* Wait for IDC state change READY -> NEED_RESET */ 5295 while (dev_state == QLA8XXX_DEV_READY) { 5296 qla83xx_idc_unlock(vha, 0); 5297 msleep(200); 5298 qla83xx_idc_lock(vha, 0); 5299 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5300 } 5301 } 5302 5303 /* Send IDC ack by writing to drv-ack register */ 5304 __qla83xx_set_drv_ack(vha); 5305 5306 return QLA_SUCCESS; 5307 } 5308 5309 int 5310 __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) 5311 { 5312 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 5313 } 5314 5315 int 5316 __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) 5317 { 5318 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 5319 } 5320 5321 static int 5322 qla83xx_check_driver_presence(scsi_qla_host_t *vha) 5323 { 5324 uint32_t drv_presence = 0; 5325 struct qla_hw_data *ha = vha->hw; 5326 5327 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5328 if (drv_presence & (1 << ha->portnum)) 5329 return QLA_SUCCESS; 5330 else 5331 return QLA_TEST_FAILED; 5332 } 5333 5334 int 5335 qla83xx_nic_core_reset(scsi_qla_host_t *vha) 5336 { 5337 int rval = QLA_SUCCESS; 5338 struct qla_hw_data *ha = vha->hw; 5339 5340 ql_dbg(ql_dbg_p3p, vha, 0xb058, 5341 "Entered %s().\n", __func__); 5342 5343 if (vha->device_flags & DFLG_DEV_FAILED) { 5344 ql_log(ql_log_warn, vha, 0xb059, 5345 "Device in unrecoverable FAILED state.\n"); 5346 return QLA_FUNCTION_FAILED; 5347 } 5348 5349 qla83xx_idc_lock(vha, 0); 5350 5351 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) { 5352 ql_log(ql_log_warn, vha, 0xb05a, 5353 "Function=0x%x has been removed from IDC participation.\n", 5354 ha->portnum); 5355 rval = QLA_FUNCTION_FAILED; 5356 goto exit; 5357 } 5358 5359 qla83xx_reset_ownership(vha); 5360 5361 rval = qla83xx_initiating_reset(vha); 5362 5363 /* 5364 * Perform reset if we are the reset-owner, 5365 * else wait till IDC state changes to READY/FAILED. 5366 */ 5367 if (rval == QLA_SUCCESS) { 5368 rval = qla83xx_idc_state_handler(vha); 5369 5370 if (rval == QLA_SUCCESS) 5371 ha->flags.nic_core_hung = 0; 5372 __qla83xx_clear_drv_ack(vha); 5373 } 5374 5375 exit: 5376 qla83xx_idc_unlock(vha, 0); 5377 5378 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__); 5379 5380 return rval; 5381 } 5382 5383 int 5384 qla2xxx_mctp_dump(scsi_qla_host_t *vha) 5385 { 5386 struct qla_hw_data *ha = vha->hw; 5387 int rval = QLA_FUNCTION_FAILED; 5388 5389 if (!IS_MCTP_CAPABLE(ha)) { 5390 /* This message can be removed from the final version */ 5391 ql_log(ql_log_info, vha, 0x506d, 5392 "This board is not MCTP capable\n"); 5393 return rval; 5394 } 5395 5396 if (!ha->mctp_dump) { 5397 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev, 5398 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL); 5399 5400 if (!ha->mctp_dump) { 5401 ql_log(ql_log_warn, vha, 0x506e, 5402 "Failed to allocate memory for mctp dump\n"); 5403 return rval; 5404 } 5405 } 5406 5407 #define MCTP_DUMP_STR_ADDR 0x00000000 5408 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma, 5409 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4); 5410 if (rval != QLA_SUCCESS) { 5411 ql_log(ql_log_warn, vha, 0x506f, 5412 "Failed to capture mctp dump\n"); 5413 } else { 5414 ql_log(ql_log_info, vha, 0x5070, 5415 "Mctp dump capture for host (%ld/%p).\n", 5416 vha->host_no, ha->mctp_dump); 5417 ha->mctp_dumped = 1; 5418 } 5419 5420 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) { 5421 ha->flags.nic_core_reset_hdlr_active = 1; 5422 rval = qla83xx_restart_nic_firmware(vha); 5423 if (rval) 5424 /* NIC Core reset failed. */ 5425 ql_log(ql_log_warn, vha, 0x5071, 5426 "Failed to restart nic firmware\n"); 5427 else 5428 ql_dbg(ql_dbg_p3p, vha, 0xb084, 5429 "Restarted NIC firmware successfully.\n"); 5430 ha->flags.nic_core_reset_hdlr_active = 0; 5431 } 5432 5433 return rval; 5434 5435 } 5436 5437 /* 5438 * qla2x00_quiesce_io 5439 * Description: This function will block the new I/Os 5440 * Its not aborting any I/Os as context 5441 * is not destroyed during quiescence 5442 * Arguments: scsi_qla_host_t 5443 * return : void 5444 */ 5445 void 5446 qla2x00_quiesce_io(scsi_qla_host_t *vha) 5447 { 5448 struct qla_hw_data *ha = vha->hw; 5449 struct scsi_qla_host *vp; 5450 5451 ql_dbg(ql_dbg_dpc, vha, 0x401d, 5452 "Quiescing I/O - ha=%p.\n", ha); 5453 5454 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); 5455 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 5456 atomic_set(&vha->loop_state, LOOP_DOWN); 5457 qla2x00_mark_all_devices_lost(vha, 0); 5458 list_for_each_entry(vp, &ha->vp_list, list) 5459 qla2x00_mark_all_devices_lost(vp, 0); 5460 } else { 5461 if (!atomic_read(&vha->loop_down_timer)) 5462 atomic_set(&vha->loop_down_timer, 5463 LOOP_DOWN_TIME); 5464 } 5465 /* Wait for pending cmds to complete */ 5466 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST); 5467 } 5468 5469 void 5470 qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) 5471 { 5472 struct qla_hw_data *ha = vha->hw; 5473 struct scsi_qla_host *vp; 5474 unsigned long flags; 5475 fc_port_t *fcport; 5476 5477 /* For ISP82XX, driver waits for completion of the commands. 5478 * online flag should be set. 5479 */ 5480 if (!(IS_P3P_TYPE(ha))) 5481 vha->flags.online = 0; 5482 ha->flags.chip_reset_done = 0; 5483 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 5484 vha->qla_stats.total_isp_aborts++; 5485 5486 ql_log(ql_log_info, vha, 0x00af, 5487 "Performing ISP error recovery - ha=%p.\n", ha); 5488 5489 /* For ISP82XX, reset_chip is just disabling interrupts. 5490 * Driver waits for the completion of the commands. 5491 * the interrupts need to be enabled. 5492 */ 5493 if (!(IS_P3P_TYPE(ha))) 5494 ha->isp_ops->reset_chip(vha); 5495 5496 ha->flags.n2n_ae = 0; 5497 ha->flags.lip_ae = 0; 5498 ha->current_topology = 0; 5499 ha->flags.fw_started = 0; 5500 ha->flags.fw_init_done = 0; 5501 ha->chip_reset++; 5502 5503 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 5504 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 5505 atomic_set(&vha->loop_state, LOOP_DOWN); 5506 qla2x00_mark_all_devices_lost(vha, 0); 5507 5508 spin_lock_irqsave(&ha->vport_slock, flags); 5509 list_for_each_entry(vp, &ha->vp_list, list) { 5510 atomic_inc(&vp->vref_count); 5511 spin_unlock_irqrestore(&ha->vport_slock, flags); 5512 5513 qla2x00_mark_all_devices_lost(vp, 0); 5514 5515 spin_lock_irqsave(&ha->vport_slock, flags); 5516 atomic_dec(&vp->vref_count); 5517 } 5518 spin_unlock_irqrestore(&ha->vport_slock, flags); 5519 } else { 5520 if (!atomic_read(&vha->loop_down_timer)) 5521 atomic_set(&vha->loop_down_timer, 5522 LOOP_DOWN_TIME); 5523 } 5524 5525 /* Clear all async request states across all VPs. */ 5526 list_for_each_entry(fcport, &vha->vp_fcports, list) 5527 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 5528 spin_lock_irqsave(&ha->vport_slock, flags); 5529 list_for_each_entry(vp, &ha->vp_list, list) { 5530 atomic_inc(&vp->vref_count); 5531 spin_unlock_irqrestore(&ha->vport_slock, flags); 5532 5533 list_for_each_entry(fcport, &vp->vp_fcports, list) 5534 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 5535 5536 spin_lock_irqsave(&ha->vport_slock, flags); 5537 atomic_dec(&vp->vref_count); 5538 } 5539 spin_unlock_irqrestore(&ha->vport_slock, flags); 5540 5541 if (!ha->flags.eeh_busy) { 5542 /* Make sure for ISP 82XX IO DMA is complete */ 5543 if (IS_P3P_TYPE(ha)) { 5544 qla82xx_chip_reset_cleanup(vha); 5545 ql_log(ql_log_info, vha, 0x00b4, 5546 "Done chip reset cleanup.\n"); 5547 5548 /* Done waiting for pending commands. 5549 * Reset the online flag. 5550 */ 5551 vha->flags.online = 0; 5552 } 5553 5554 /* Requeue all commands in outstanding command list. */ 5555 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 5556 } 5557 /* memory barrier */ 5558 wmb(); 5559 } 5560 5561 /* 5562 * qla2x00_abort_isp 5563 * Resets ISP and aborts all outstanding commands. 5564 * 5565 * Input: 5566 * ha = adapter block pointer. 5567 * 5568 * Returns: 5569 * 0 = success 5570 */ 5571 int 5572 qla2x00_abort_isp(scsi_qla_host_t *vha) 5573 { 5574 int rval; 5575 uint8_t status = 0; 5576 struct qla_hw_data *ha = vha->hw; 5577 struct scsi_qla_host *vp; 5578 struct req_que *req = ha->req_q_map[0]; 5579 unsigned long flags; 5580 5581 if (vha->flags.online) { 5582 qla2x00_abort_isp_cleanup(vha); 5583 5584 if (IS_QLA8031(ha)) { 5585 ql_dbg(ql_dbg_p3p, vha, 0xb05c, 5586 "Clearing fcoe driver presence.\n"); 5587 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS) 5588 ql_dbg(ql_dbg_p3p, vha, 0xb073, 5589 "Error while clearing DRV-Presence.\n"); 5590 } 5591 5592 if (unlikely(pci_channel_offline(ha->pdev) && 5593 ha->flags.pci_channel_io_perm_failure)) { 5594 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 5595 status = 0; 5596 return status; 5597 } 5598 5599 ha->isp_ops->get_flash_version(vha, req->ring); 5600 5601 ha->isp_ops->nvram_config(vha); 5602 5603 if (!qla2x00_restart_isp(vha)) { 5604 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5605 5606 if (!atomic_read(&vha->loop_down_timer)) { 5607 /* 5608 * Issue marker command only when we are going 5609 * to start the I/O . 5610 */ 5611 vha->marker_needed = 1; 5612 } 5613 5614 vha->flags.online = 1; 5615 5616 ha->isp_ops->enable_intrs(ha); 5617 5618 ha->isp_abort_cnt = 0; 5619 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 5620 5621 if (IS_QLA81XX(ha) || IS_QLA8031(ha)) 5622 qla2x00_get_fw_version(vha); 5623 if (ha->fce) { 5624 ha->flags.fce_enabled = 1; 5625 memset(ha->fce, 0, 5626 fce_calc_size(ha->fce_bufs)); 5627 rval = qla2x00_enable_fce_trace(vha, 5628 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 5629 &ha->fce_bufs); 5630 if (rval) { 5631 ql_log(ql_log_warn, vha, 0x8033, 5632 "Unable to reinitialize FCE " 5633 "(%d).\n", rval); 5634 ha->flags.fce_enabled = 0; 5635 } 5636 } 5637 5638 if (ha->eft) { 5639 memset(ha->eft, 0, EFT_SIZE); 5640 rval = qla2x00_enable_eft_trace(vha, 5641 ha->eft_dma, EFT_NUM_BUFFERS); 5642 if (rval) { 5643 ql_log(ql_log_warn, vha, 0x8034, 5644 "Unable to reinitialize EFT " 5645 "(%d).\n", rval); 5646 } 5647 } 5648 } else { /* failed the ISP abort */ 5649 vha->flags.online = 1; 5650 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 5651 if (ha->isp_abort_cnt == 0) { 5652 ql_log(ql_log_fatal, vha, 0x8035, 5653 "ISP error recover failed - " 5654 "board disabled.\n"); 5655 /* 5656 * The next call disables the board 5657 * completely. 5658 */ 5659 ha->isp_ops->reset_adapter(vha); 5660 vha->flags.online = 0; 5661 clear_bit(ISP_ABORT_RETRY, 5662 &vha->dpc_flags); 5663 status = 0; 5664 } else { /* schedule another ISP abort */ 5665 ha->isp_abort_cnt--; 5666 ql_dbg(ql_dbg_taskm, vha, 0x8020, 5667 "ISP abort - retry remaining %d.\n", 5668 ha->isp_abort_cnt); 5669 status = 1; 5670 } 5671 } else { 5672 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 5673 ql_dbg(ql_dbg_taskm, vha, 0x8021, 5674 "ISP error recovery - retrying (%d) " 5675 "more times.\n", ha->isp_abort_cnt); 5676 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 5677 status = 1; 5678 } 5679 } 5680 5681 } 5682 5683 if (!status) { 5684 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__); 5685 5686 spin_lock_irqsave(&ha->vport_slock, flags); 5687 list_for_each_entry(vp, &ha->vp_list, list) { 5688 if (vp->vp_idx) { 5689 atomic_inc(&vp->vref_count); 5690 spin_unlock_irqrestore(&ha->vport_slock, flags); 5691 5692 qla2x00_vp_abort_isp(vp); 5693 5694 spin_lock_irqsave(&ha->vport_slock, flags); 5695 atomic_dec(&vp->vref_count); 5696 } 5697 } 5698 spin_unlock_irqrestore(&ha->vport_slock, flags); 5699 5700 if (IS_QLA8031(ha)) { 5701 ql_dbg(ql_dbg_p3p, vha, 0xb05d, 5702 "Setting back fcoe driver presence.\n"); 5703 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS) 5704 ql_dbg(ql_dbg_p3p, vha, 0xb074, 5705 "Error while setting DRV-Presence.\n"); 5706 } 5707 } else { 5708 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n", 5709 __func__); 5710 } 5711 5712 return(status); 5713 } 5714 5715 /* 5716 * qla2x00_restart_isp 5717 * restarts the ISP after a reset 5718 * 5719 * Input: 5720 * ha = adapter block pointer. 5721 * 5722 * Returns: 5723 * 0 = success 5724 */ 5725 static int 5726 qla2x00_restart_isp(scsi_qla_host_t *vha) 5727 { 5728 int status = 0; 5729 struct qla_hw_data *ha = vha->hw; 5730 struct req_que *req = ha->req_q_map[0]; 5731 struct rsp_que *rsp = ha->rsp_q_map[0]; 5732 5733 /* If firmware needs to be loaded */ 5734 if (qla2x00_isp_firmware(vha)) { 5735 vha->flags.online = 0; 5736 status = ha->isp_ops->chip_diag(vha); 5737 if (!status) 5738 status = qla2x00_setup_chip(vha); 5739 } 5740 5741 if (!status && !(status = qla2x00_init_rings(vha))) { 5742 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5743 ha->flags.chip_reset_done = 1; 5744 5745 /* Initialize the queues in use */ 5746 qla25xx_init_queues(ha); 5747 5748 status = qla2x00_fw_ready(vha); 5749 if (!status) { 5750 /* Issue a marker after FW becomes ready. */ 5751 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); 5752 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5753 } 5754 5755 /* if no cable then assume it's good */ 5756 if ((vha->device_flags & DFLG_NO_CABLE)) 5757 status = 0; 5758 } 5759 return (status); 5760 } 5761 5762 static int 5763 qla25xx_init_queues(struct qla_hw_data *ha) 5764 { 5765 struct rsp_que *rsp = NULL; 5766 struct req_que *req = NULL; 5767 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 5768 int ret = -1; 5769 int i; 5770 5771 for (i = 1; i < ha->max_rsp_queues; i++) { 5772 rsp = ha->rsp_q_map[i]; 5773 if (rsp && test_bit(i, ha->rsp_qid_map)) { 5774 rsp->options &= ~BIT_0; 5775 ret = qla25xx_init_rsp_que(base_vha, rsp); 5776 if (ret != QLA_SUCCESS) 5777 ql_dbg(ql_dbg_init, base_vha, 0x00ff, 5778 "%s Rsp que: %d init failed.\n", 5779 __func__, rsp->id); 5780 else 5781 ql_dbg(ql_dbg_init, base_vha, 0x0100, 5782 "%s Rsp que: %d inited.\n", 5783 __func__, rsp->id); 5784 } 5785 } 5786 for (i = 1; i < ha->max_req_queues; i++) { 5787 req = ha->req_q_map[i]; 5788 if (req && test_bit(i, ha->req_qid_map)) { 5789 /* Clear outstanding commands array. */ 5790 req->options &= ~BIT_0; 5791 ret = qla25xx_init_req_que(base_vha, req); 5792 if (ret != QLA_SUCCESS) 5793 ql_dbg(ql_dbg_init, base_vha, 0x0101, 5794 "%s Req que: %d init failed.\n", 5795 __func__, req->id); 5796 else 5797 ql_dbg(ql_dbg_init, base_vha, 0x0102, 5798 "%s Req que: %d inited.\n", 5799 __func__, req->id); 5800 } 5801 } 5802 return ret; 5803 } 5804 5805 /* 5806 * qla2x00_reset_adapter 5807 * Reset adapter. 5808 * 5809 * Input: 5810 * ha = adapter block pointer. 5811 */ 5812 void 5813 qla2x00_reset_adapter(scsi_qla_host_t *vha) 5814 { 5815 unsigned long flags = 0; 5816 struct qla_hw_data *ha = vha->hw; 5817 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5818 5819 vha->flags.online = 0; 5820 ha->isp_ops->disable_intrs(ha); 5821 5822 spin_lock_irqsave(&ha->hardware_lock, flags); 5823 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 5824 RD_REG_WORD(®->hccr); /* PCI Posting. */ 5825 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 5826 RD_REG_WORD(®->hccr); /* PCI Posting. */ 5827 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5828 } 5829 5830 void 5831 qla24xx_reset_adapter(scsi_qla_host_t *vha) 5832 { 5833 unsigned long flags = 0; 5834 struct qla_hw_data *ha = vha->hw; 5835 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 5836 5837 if (IS_P3P_TYPE(ha)) 5838 return; 5839 5840 vha->flags.online = 0; 5841 ha->isp_ops->disable_intrs(ha); 5842 5843 spin_lock_irqsave(&ha->hardware_lock, flags); 5844 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); 5845 RD_REG_DWORD(®->hccr); 5846 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); 5847 RD_REG_DWORD(®->hccr); 5848 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5849 5850 if (IS_NOPOLLING_TYPE(ha)) 5851 ha->isp_ops->enable_intrs(ha); 5852 } 5853 5854 /* On sparc systems, obtain port and node WWN from firmware 5855 * properties. 5856 */ 5857 static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, 5858 struct nvram_24xx *nv) 5859 { 5860 #ifdef CONFIG_SPARC 5861 struct qla_hw_data *ha = vha->hw; 5862 struct pci_dev *pdev = ha->pdev; 5863 struct device_node *dp = pci_device_to_OF_node(pdev); 5864 const u8 *val; 5865 int len; 5866 5867 val = of_get_property(dp, "port-wwn", &len); 5868 if (val && len >= WWN_SIZE) 5869 memcpy(nv->port_name, val, WWN_SIZE); 5870 5871 val = of_get_property(dp, "node-wwn", &len); 5872 if (val && len >= WWN_SIZE) 5873 memcpy(nv->node_name, val, WWN_SIZE); 5874 #endif 5875 } 5876 5877 int 5878 qla24xx_nvram_config(scsi_qla_host_t *vha) 5879 { 5880 int rval; 5881 struct init_cb_24xx *icb; 5882 struct nvram_24xx *nv; 5883 uint32_t *dptr; 5884 uint8_t *dptr1, *dptr2; 5885 uint32_t chksum; 5886 uint16_t cnt; 5887 struct qla_hw_data *ha = vha->hw; 5888 5889 rval = QLA_SUCCESS; 5890 icb = (struct init_cb_24xx *)ha->init_cb; 5891 nv = ha->nvram; 5892 5893 /* Determine NVRAM starting address. */ 5894 if (ha->port_no == 0) { 5895 ha->nvram_base = FA_NVRAM_FUNC0_ADDR; 5896 ha->vpd_base = FA_NVRAM_VPD0_ADDR; 5897 } else { 5898 ha->nvram_base = FA_NVRAM_FUNC1_ADDR; 5899 ha->vpd_base = FA_NVRAM_VPD1_ADDR; 5900 } 5901 5902 ha->nvram_size = sizeof(struct nvram_24xx); 5903 ha->vpd_size = FA_NVRAM_VPD_SIZE; 5904 5905 /* Get VPD data into cache */ 5906 ha->vpd = ha->nvram + VPD_OFFSET; 5907 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd, 5908 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4); 5909 5910 /* Get NVRAM data into cache and calculate checksum. */ 5911 dptr = (uint32_t *)nv; 5912 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base, 5913 ha->nvram_size); 5914 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 5915 chksum += le32_to_cpu(*dptr); 5916 5917 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a, 5918 "Contents of NVRAM\n"); 5919 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d, 5920 (uint8_t *)nv, ha->nvram_size); 5921 5922 /* Bad NVRAM data, set defaults parameters. */ 5923 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' 5924 || nv->id[3] != ' ' || 5925 nv->nvram_version < cpu_to_le16(ICB_VERSION)) { 5926 /* Reset NVRAM data. */ 5927 ql_log(ql_log_warn, vha, 0x006b, 5928 "Inconsistent NVRAM detected: checksum=0x%x id=%c " 5929 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version); 5930 ql_log(ql_log_warn, vha, 0x006c, 5931 "Falling back to functioning (yet invalid -- WWPN) " 5932 "defaults.\n"); 5933 5934 /* 5935 * Set default initialization control block. 5936 */ 5937 memset(nv, 0, ha->nvram_size); 5938 nv->nvram_version = cpu_to_le16(ICB_VERSION); 5939 nv->version = cpu_to_le16(ICB_VERSION); 5940 nv->frame_payload_size = 2048; 5941 nv->execution_throttle = cpu_to_le16(0xFFFF); 5942 nv->exchange_count = cpu_to_le16(0); 5943 nv->hard_address = cpu_to_le16(124); 5944 nv->port_name[0] = 0x21; 5945 nv->port_name[1] = 0x00 + ha->port_no + 1; 5946 nv->port_name[2] = 0x00; 5947 nv->port_name[3] = 0xe0; 5948 nv->port_name[4] = 0x8b; 5949 nv->port_name[5] = 0x1c; 5950 nv->port_name[6] = 0x55; 5951 nv->port_name[7] = 0x86; 5952 nv->node_name[0] = 0x20; 5953 nv->node_name[1] = 0x00; 5954 nv->node_name[2] = 0x00; 5955 nv->node_name[3] = 0xe0; 5956 nv->node_name[4] = 0x8b; 5957 nv->node_name[5] = 0x1c; 5958 nv->node_name[6] = 0x55; 5959 nv->node_name[7] = 0x86; 5960 qla24xx_nvram_wwn_from_ofw(vha, nv); 5961 nv->login_retry_count = cpu_to_le16(8); 5962 nv->interrupt_delay_timer = cpu_to_le16(0); 5963 nv->login_timeout = cpu_to_le16(0); 5964 nv->firmware_options_1 = 5965 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 5966 nv->firmware_options_2 = cpu_to_le32(2 << 4); 5967 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 5968 nv->firmware_options_3 = cpu_to_le32(2 << 13); 5969 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 5970 nv->efi_parameters = cpu_to_le32(0); 5971 nv->reset_delay = 5; 5972 nv->max_luns_per_target = cpu_to_le16(128); 5973 nv->port_down_retry_count = cpu_to_le16(30); 5974 nv->link_down_timeout = cpu_to_le16(30); 5975 5976 rval = 1; 5977 } 5978 5979 if (qla_tgt_mode_enabled(vha)) { 5980 /* Don't enable full login after initial LIP */ 5981 nv->firmware_options_1 &= cpu_to_le32(~BIT_13); 5982 /* Don't enable LIP full login for initiator */ 5983 nv->host_p &= cpu_to_le32(~BIT_10); 5984 } 5985 5986 qlt_24xx_config_nvram_stage1(vha, nv); 5987 5988 /* Reset Initialization control block */ 5989 memset(icb, 0, ha->init_cb_size); 5990 5991 /* Copy 1st segment. */ 5992 dptr1 = (uint8_t *)icb; 5993 dptr2 = (uint8_t *)&nv->version; 5994 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 5995 while (cnt--) 5996 *dptr1++ = *dptr2++; 5997 5998 icb->login_retry_count = nv->login_retry_count; 5999 icb->link_down_on_nos = nv->link_down_on_nos; 6000 6001 /* Copy 2nd segment. */ 6002 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 6003 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 6004 cnt = (uint8_t *)&icb->reserved_3 - 6005 (uint8_t *)&icb->interrupt_delay_timer; 6006 while (cnt--) 6007 *dptr1++ = *dptr2++; 6008 6009 /* 6010 * Setup driver NVRAM options. 6011 */ 6012 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 6013 "QLA2462"); 6014 6015 qlt_24xx_config_nvram_stage2(vha, icb); 6016 6017 if (nv->host_p & cpu_to_le32(BIT_15)) { 6018 /* Use alternate WWN? */ 6019 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 6020 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 6021 } 6022 6023 /* Prepare nodename */ 6024 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 6025 /* 6026 * Firmware will apply the following mask if the nodename was 6027 * not provided. 6028 */ 6029 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 6030 icb->node_name[0] &= 0xF0; 6031 } 6032 6033 /* Set host adapter parameters. */ 6034 ha->flags.disable_risc_code_load = 0; 6035 ha->flags.enable_lip_reset = 0; 6036 ha->flags.enable_lip_full_login = 6037 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; 6038 ha->flags.enable_target_reset = 6039 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; 6040 ha->flags.enable_led_scheme = 0; 6041 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; 6042 6043 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 6044 (BIT_6 | BIT_5 | BIT_4)) >> 4; 6045 6046 memcpy(ha->fw_seriallink_options24, nv->seriallink_options, 6047 sizeof(ha->fw_seriallink_options24)); 6048 6049 /* save HBA serial number */ 6050 ha->serial0 = icb->port_name[5]; 6051 ha->serial1 = icb->port_name[6]; 6052 ha->serial2 = icb->port_name[7]; 6053 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 6054 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 6055 6056 icb->execution_throttle = cpu_to_le16(0xFFFF); 6057 6058 ha->retry_count = le16_to_cpu(nv->login_retry_count); 6059 6060 /* Set minimum login_timeout to 4 seconds. */ 6061 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 6062 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 6063 if (le16_to_cpu(nv->login_timeout) < 4) 6064 nv->login_timeout = cpu_to_le16(4); 6065 ha->login_timeout = le16_to_cpu(nv->login_timeout); 6066 6067 /* Set minimum RATOV to 100 tenths of a second. */ 6068 ha->r_a_tov = 100; 6069 6070 ha->loop_reset_delay = nv->reset_delay; 6071 6072 /* Link Down Timeout = 0: 6073 * 6074 * When Port Down timer expires we will start returning 6075 * I/O's to OS with "DID_NO_CONNECT". 6076 * 6077 * Link Down Timeout != 0: 6078 * 6079 * The driver waits for the link to come up after link down 6080 * before returning I/Os to OS with "DID_NO_CONNECT". 6081 */ 6082 if (le16_to_cpu(nv->link_down_timeout) == 0) { 6083 ha->loop_down_abort_time = 6084 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 6085 } else { 6086 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 6087 ha->loop_down_abort_time = 6088 (LOOP_DOWN_TIME - ha->link_down_timeout); 6089 } 6090 6091 /* Need enough time to try and get the port back. */ 6092 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 6093 if (qlport_down_retry) 6094 ha->port_down_retry_count = qlport_down_retry; 6095 6096 /* Set login_retry_count */ 6097 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 6098 if (ha->port_down_retry_count == 6099 le16_to_cpu(nv->port_down_retry_count) && 6100 ha->port_down_retry_count > 3) 6101 ha->login_retry_count = ha->port_down_retry_count; 6102 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 6103 ha->login_retry_count = ha->port_down_retry_count; 6104 if (ql2xloginretrycount) 6105 ha->login_retry_count = ql2xloginretrycount; 6106 6107 /* Enable ZIO. */ 6108 if (!vha->flags.init_done) { 6109 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 6110 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 6111 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 6112 le16_to_cpu(icb->interrupt_delay_timer): 2; 6113 } 6114 icb->firmware_options_2 &= cpu_to_le32( 6115 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 6116 vha->flags.process_response_queue = 0; 6117 if (ha->zio_mode != QLA_ZIO_DISABLED) { 6118 ha->zio_mode = QLA_ZIO_MODE_6; 6119 6120 ql_log(ql_log_info, vha, 0x006f, 6121 "ZIO mode %d enabled; timer delay (%d us).\n", 6122 ha->zio_mode, ha->zio_timer * 100); 6123 6124 icb->firmware_options_2 |= cpu_to_le32( 6125 (uint32_t)ha->zio_mode); 6126 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 6127 vha->flags.process_response_queue = 1; 6128 } 6129 6130 if (rval) { 6131 ql_log(ql_log_warn, vha, 0x0070, 6132 "NVRAM configuration failed.\n"); 6133 } 6134 return (rval); 6135 } 6136 6137 uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha) 6138 { 6139 struct qla27xx_image_status pri_image_status, sec_image_status; 6140 uint8_t valid_pri_image, valid_sec_image; 6141 uint32_t *wptr; 6142 uint32_t cnt, chksum, size; 6143 struct qla_hw_data *ha = vha->hw; 6144 6145 valid_pri_image = valid_sec_image = 1; 6146 ha->active_image = 0; 6147 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t); 6148 6149 if (!ha->flt_region_img_status_pri) { 6150 valid_pri_image = 0; 6151 goto check_sec_image; 6152 } 6153 6154 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status), 6155 ha->flt_region_img_status_pri, size); 6156 6157 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) { 6158 ql_dbg(ql_dbg_init, vha, 0x018b, 6159 "Primary image signature (0x%x) not valid\n", 6160 pri_image_status.signature); 6161 valid_pri_image = 0; 6162 goto check_sec_image; 6163 } 6164 6165 wptr = (uint32_t *)(&pri_image_status); 6166 cnt = size; 6167 6168 for (chksum = 0; cnt--; wptr++) 6169 chksum += le32_to_cpu(*wptr); 6170 6171 if (chksum) { 6172 ql_dbg(ql_dbg_init, vha, 0x018c, 6173 "Checksum validation failed for primary image (0x%x)\n", 6174 chksum); 6175 valid_pri_image = 0; 6176 } 6177 6178 check_sec_image: 6179 if (!ha->flt_region_img_status_sec) { 6180 valid_sec_image = 0; 6181 goto check_valid_image; 6182 } 6183 6184 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status), 6185 ha->flt_region_img_status_sec, size); 6186 6187 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) { 6188 ql_dbg(ql_dbg_init, vha, 0x018d, 6189 "Secondary image signature(0x%x) not valid\n", 6190 sec_image_status.signature); 6191 valid_sec_image = 0; 6192 goto check_valid_image; 6193 } 6194 6195 wptr = (uint32_t *)(&sec_image_status); 6196 cnt = size; 6197 for (chksum = 0; cnt--; wptr++) 6198 chksum += le32_to_cpu(*wptr); 6199 if (chksum) { 6200 ql_dbg(ql_dbg_init, vha, 0x018e, 6201 "Checksum validation failed for secondary image (0x%x)\n", 6202 chksum); 6203 valid_sec_image = 0; 6204 } 6205 6206 check_valid_image: 6207 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1)) 6208 ha->active_image = QLA27XX_PRIMARY_IMAGE; 6209 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) { 6210 if (!ha->active_image || 6211 pri_image_status.generation_number < 6212 sec_image_status.generation_number) 6213 ha->active_image = QLA27XX_SECONDARY_IMAGE; 6214 } 6215 6216 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n", 6217 ha->active_image == 0 ? "default bootld and fw" : 6218 ha->active_image == 1 ? "primary" : 6219 ha->active_image == 2 ? "secondary" : 6220 "Invalid"); 6221 6222 return ha->active_image; 6223 } 6224 6225 static int 6226 qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, 6227 uint32_t faddr) 6228 { 6229 int rval = QLA_SUCCESS; 6230 int segments, fragment; 6231 uint32_t *dcode, dlen; 6232 uint32_t risc_addr; 6233 uint32_t risc_size; 6234 uint32_t i; 6235 struct qla_hw_data *ha = vha->hw; 6236 struct req_que *req = ha->req_q_map[0]; 6237 6238 ql_dbg(ql_dbg_init, vha, 0x008b, 6239 "FW: Loading firmware from flash (%x).\n", faddr); 6240 6241 rval = QLA_SUCCESS; 6242 6243 segments = FA_RISC_CODE_SEGMENTS; 6244 dcode = (uint32_t *)req->ring; 6245 *srisc_addr = 0; 6246 6247 if (IS_QLA27XX(ha) && 6248 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE) 6249 faddr = ha->flt_region_fw_sec; 6250 6251 /* Validate firmware image by checking version. */ 6252 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4); 6253 for (i = 0; i < 4; i++) 6254 dcode[i] = be32_to_cpu(dcode[i]); 6255 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 6256 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 6257 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 6258 dcode[3] == 0)) { 6259 ql_log(ql_log_fatal, vha, 0x008c, 6260 "Unable to verify the integrity of flash firmware " 6261 "image.\n"); 6262 ql_log(ql_log_fatal, vha, 0x008d, 6263 "Firmware data: %08x %08x %08x %08x.\n", 6264 dcode[0], dcode[1], dcode[2], dcode[3]); 6265 6266 return QLA_FUNCTION_FAILED; 6267 } 6268 6269 while (segments && rval == QLA_SUCCESS) { 6270 /* Read segment's load information. */ 6271 qla24xx_read_flash_data(vha, dcode, faddr, 4); 6272 6273 risc_addr = be32_to_cpu(dcode[2]); 6274 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; 6275 risc_size = be32_to_cpu(dcode[3]); 6276 6277 fragment = 0; 6278 while (risc_size > 0 && rval == QLA_SUCCESS) { 6279 dlen = (uint32_t)(ha->fw_transfer_size >> 2); 6280 if (dlen > risc_size) 6281 dlen = risc_size; 6282 6283 ql_dbg(ql_dbg_init, vha, 0x008e, 6284 "Loading risc segment@ risc addr %x " 6285 "number of dwords 0x%x offset 0x%x.\n", 6286 risc_addr, dlen, faddr); 6287 6288 qla24xx_read_flash_data(vha, dcode, faddr, dlen); 6289 for (i = 0; i < dlen; i++) 6290 dcode[i] = swab32(dcode[i]); 6291 6292 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 6293 dlen); 6294 if (rval) { 6295 ql_log(ql_log_fatal, vha, 0x008f, 6296 "Failed to load segment %d of firmware.\n", 6297 fragment); 6298 return QLA_FUNCTION_FAILED; 6299 } 6300 6301 faddr += dlen; 6302 risc_addr += dlen; 6303 risc_size -= dlen; 6304 fragment++; 6305 } 6306 6307 /* Next segment. */ 6308 segments--; 6309 } 6310 6311 if (!IS_QLA27XX(ha)) 6312 return rval; 6313 6314 if (ha->fw_dump_template) 6315 vfree(ha->fw_dump_template); 6316 ha->fw_dump_template = NULL; 6317 ha->fw_dump_template_len = 0; 6318 6319 ql_dbg(ql_dbg_init, vha, 0x0161, 6320 "Loading fwdump template from %x\n", faddr); 6321 qla24xx_read_flash_data(vha, dcode, faddr, 7); 6322 risc_size = be32_to_cpu(dcode[2]); 6323 ql_dbg(ql_dbg_init, vha, 0x0162, 6324 "-> array size %x dwords\n", risc_size); 6325 if (risc_size == 0 || risc_size == ~0) 6326 goto default_template; 6327 6328 dlen = (risc_size - 8) * sizeof(*dcode); 6329 ql_dbg(ql_dbg_init, vha, 0x0163, 6330 "-> template allocating %x bytes...\n", dlen); 6331 ha->fw_dump_template = vmalloc(dlen); 6332 if (!ha->fw_dump_template) { 6333 ql_log(ql_log_warn, vha, 0x0164, 6334 "Failed fwdump template allocate %x bytes.\n", risc_size); 6335 goto default_template; 6336 } 6337 6338 faddr += 7; 6339 risc_size -= 8; 6340 dcode = ha->fw_dump_template; 6341 qla24xx_read_flash_data(vha, dcode, faddr, risc_size); 6342 for (i = 0; i < risc_size; i++) 6343 dcode[i] = le32_to_cpu(dcode[i]); 6344 6345 if (!qla27xx_fwdt_template_valid(dcode)) { 6346 ql_log(ql_log_warn, vha, 0x0165, 6347 "Failed fwdump template validate\n"); 6348 goto default_template; 6349 } 6350 6351 dlen = qla27xx_fwdt_template_size(dcode); 6352 ql_dbg(ql_dbg_init, vha, 0x0166, 6353 "-> template size %x bytes\n", dlen); 6354 if (dlen > risc_size * sizeof(*dcode)) { 6355 ql_log(ql_log_warn, vha, 0x0167, 6356 "Failed fwdump template exceeds array by %x bytes\n", 6357 (uint32_t)(dlen - risc_size * sizeof(*dcode))); 6358 goto default_template; 6359 } 6360 ha->fw_dump_template_len = dlen; 6361 return rval; 6362 6363 default_template: 6364 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n"); 6365 if (ha->fw_dump_template) 6366 vfree(ha->fw_dump_template); 6367 ha->fw_dump_template = NULL; 6368 ha->fw_dump_template_len = 0; 6369 6370 dlen = qla27xx_fwdt_template_default_size(); 6371 ql_dbg(ql_dbg_init, vha, 0x0169, 6372 "-> template allocating %x bytes...\n", dlen); 6373 ha->fw_dump_template = vmalloc(dlen); 6374 if (!ha->fw_dump_template) { 6375 ql_log(ql_log_warn, vha, 0x016a, 6376 "Failed fwdump template allocate %x bytes.\n", risc_size); 6377 goto failed_template; 6378 } 6379 6380 dcode = ha->fw_dump_template; 6381 risc_size = dlen / sizeof(*dcode); 6382 memcpy(dcode, qla27xx_fwdt_template_default(), dlen); 6383 for (i = 0; i < risc_size; i++) 6384 dcode[i] = be32_to_cpu(dcode[i]); 6385 6386 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) { 6387 ql_log(ql_log_warn, vha, 0x016b, 6388 "Failed fwdump template validate\n"); 6389 goto failed_template; 6390 } 6391 6392 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template); 6393 ql_dbg(ql_dbg_init, vha, 0x016c, 6394 "-> template size %x bytes\n", dlen); 6395 ha->fw_dump_template_len = dlen; 6396 return rval; 6397 6398 failed_template: 6399 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n"); 6400 if (ha->fw_dump_template) 6401 vfree(ha->fw_dump_template); 6402 ha->fw_dump_template = NULL; 6403 ha->fw_dump_template_len = 0; 6404 return rval; 6405 } 6406 6407 #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/" 6408 6409 int 6410 qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 6411 { 6412 int rval; 6413 int i, fragment; 6414 uint16_t *wcode, *fwcode; 6415 uint32_t risc_addr, risc_size, fwclen, wlen, *seg; 6416 struct fw_blob *blob; 6417 struct qla_hw_data *ha = vha->hw; 6418 struct req_que *req = ha->req_q_map[0]; 6419 6420 /* Load firmware blob. */ 6421 blob = qla2x00_request_firmware(vha); 6422 if (!blob) { 6423 ql_log(ql_log_info, vha, 0x0083, 6424 "Firmware image unavailable.\n"); 6425 ql_log(ql_log_info, vha, 0x0084, 6426 "Firmware images can be retrieved from: "QLA_FW_URL ".\n"); 6427 return QLA_FUNCTION_FAILED; 6428 } 6429 6430 rval = QLA_SUCCESS; 6431 6432 wcode = (uint16_t *)req->ring; 6433 *srisc_addr = 0; 6434 fwcode = (uint16_t *)blob->fw->data; 6435 fwclen = 0; 6436 6437 /* Validate firmware image by checking version. */ 6438 if (blob->fw->size < 8 * sizeof(uint16_t)) { 6439 ql_log(ql_log_fatal, vha, 0x0085, 6440 "Unable to verify integrity of firmware image (%zd).\n", 6441 blob->fw->size); 6442 goto fail_fw_integrity; 6443 } 6444 for (i = 0; i < 4; i++) 6445 wcode[i] = be16_to_cpu(fwcode[i + 4]); 6446 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff && 6447 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 && 6448 wcode[2] == 0 && wcode[3] == 0)) { 6449 ql_log(ql_log_fatal, vha, 0x0086, 6450 "Unable to verify integrity of firmware image.\n"); 6451 ql_log(ql_log_fatal, vha, 0x0087, 6452 "Firmware data: %04x %04x %04x %04x.\n", 6453 wcode[0], wcode[1], wcode[2], wcode[3]); 6454 goto fail_fw_integrity; 6455 } 6456 6457 seg = blob->segs; 6458 while (*seg && rval == QLA_SUCCESS) { 6459 risc_addr = *seg; 6460 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr; 6461 risc_size = be16_to_cpu(fwcode[3]); 6462 6463 /* Validate firmware image size. */ 6464 fwclen += risc_size * sizeof(uint16_t); 6465 if (blob->fw->size < fwclen) { 6466 ql_log(ql_log_fatal, vha, 0x0088, 6467 "Unable to verify integrity of firmware image " 6468 "(%zd).\n", blob->fw->size); 6469 goto fail_fw_integrity; 6470 } 6471 6472 fragment = 0; 6473 while (risc_size > 0 && rval == QLA_SUCCESS) { 6474 wlen = (uint16_t)(ha->fw_transfer_size >> 1); 6475 if (wlen > risc_size) 6476 wlen = risc_size; 6477 ql_dbg(ql_dbg_init, vha, 0x0089, 6478 "Loading risc segment@ risc addr %x number of " 6479 "words 0x%x.\n", risc_addr, wlen); 6480 6481 for (i = 0; i < wlen; i++) 6482 wcode[i] = swab16(fwcode[i]); 6483 6484 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 6485 wlen); 6486 if (rval) { 6487 ql_log(ql_log_fatal, vha, 0x008a, 6488 "Failed to load segment %d of firmware.\n", 6489 fragment); 6490 break; 6491 } 6492 6493 fwcode += wlen; 6494 risc_addr += wlen; 6495 risc_size -= wlen; 6496 fragment++; 6497 } 6498 6499 /* Next segment. */ 6500 seg++; 6501 } 6502 return rval; 6503 6504 fail_fw_integrity: 6505 return QLA_FUNCTION_FAILED; 6506 } 6507 6508 static int 6509 qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) 6510 { 6511 int rval; 6512 int segments, fragment; 6513 uint32_t *dcode, dlen; 6514 uint32_t risc_addr; 6515 uint32_t risc_size; 6516 uint32_t i; 6517 struct fw_blob *blob; 6518 const uint32_t *fwcode; 6519 uint32_t fwclen; 6520 struct qla_hw_data *ha = vha->hw; 6521 struct req_que *req = ha->req_q_map[0]; 6522 6523 /* Load firmware blob. */ 6524 blob = qla2x00_request_firmware(vha); 6525 if (!blob) { 6526 ql_log(ql_log_warn, vha, 0x0090, 6527 "Firmware image unavailable.\n"); 6528 ql_log(ql_log_warn, vha, 0x0091, 6529 "Firmware images can be retrieved from: " 6530 QLA_FW_URL ".\n"); 6531 6532 return QLA_FUNCTION_FAILED; 6533 } 6534 6535 ql_dbg(ql_dbg_init, vha, 0x0092, 6536 "FW: Loading via request-firmware.\n"); 6537 6538 rval = QLA_SUCCESS; 6539 6540 segments = FA_RISC_CODE_SEGMENTS; 6541 dcode = (uint32_t *)req->ring; 6542 *srisc_addr = 0; 6543 fwcode = (uint32_t *)blob->fw->data; 6544 fwclen = 0; 6545 6546 /* Validate firmware image by checking version. */ 6547 if (blob->fw->size < 8 * sizeof(uint32_t)) { 6548 ql_log(ql_log_fatal, vha, 0x0093, 6549 "Unable to verify integrity of firmware image (%zd).\n", 6550 blob->fw->size); 6551 return QLA_FUNCTION_FAILED; 6552 } 6553 for (i = 0; i < 4; i++) 6554 dcode[i] = be32_to_cpu(fwcode[i + 4]); 6555 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 6556 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 6557 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 6558 dcode[3] == 0)) { 6559 ql_log(ql_log_fatal, vha, 0x0094, 6560 "Unable to verify integrity of firmware image (%zd).\n", 6561 blob->fw->size); 6562 ql_log(ql_log_fatal, vha, 0x0095, 6563 "Firmware data: %08x %08x %08x %08x.\n", 6564 dcode[0], dcode[1], dcode[2], dcode[3]); 6565 return QLA_FUNCTION_FAILED; 6566 } 6567 6568 while (segments && rval == QLA_SUCCESS) { 6569 risc_addr = be32_to_cpu(fwcode[2]); 6570 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; 6571 risc_size = be32_to_cpu(fwcode[3]); 6572 6573 /* Validate firmware image size. */ 6574 fwclen += risc_size * sizeof(uint32_t); 6575 if (blob->fw->size < fwclen) { 6576 ql_log(ql_log_fatal, vha, 0x0096, 6577 "Unable to verify integrity of firmware image " 6578 "(%zd).\n", blob->fw->size); 6579 return QLA_FUNCTION_FAILED; 6580 } 6581 6582 fragment = 0; 6583 while (risc_size > 0 && rval == QLA_SUCCESS) { 6584 dlen = (uint32_t)(ha->fw_transfer_size >> 2); 6585 if (dlen > risc_size) 6586 dlen = risc_size; 6587 6588 ql_dbg(ql_dbg_init, vha, 0x0097, 6589 "Loading risc segment@ risc addr %x " 6590 "number of dwords 0x%x.\n", risc_addr, dlen); 6591 6592 for (i = 0; i < dlen; i++) 6593 dcode[i] = swab32(fwcode[i]); 6594 6595 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 6596 dlen); 6597 if (rval) { 6598 ql_log(ql_log_fatal, vha, 0x0098, 6599 "Failed to load segment %d of firmware.\n", 6600 fragment); 6601 return QLA_FUNCTION_FAILED; 6602 } 6603 6604 fwcode += dlen; 6605 risc_addr += dlen; 6606 risc_size -= dlen; 6607 fragment++; 6608 } 6609 6610 /* Next segment. */ 6611 segments--; 6612 } 6613 6614 if (!IS_QLA27XX(ha)) 6615 return rval; 6616 6617 if (ha->fw_dump_template) 6618 vfree(ha->fw_dump_template); 6619 ha->fw_dump_template = NULL; 6620 ha->fw_dump_template_len = 0; 6621 6622 ql_dbg(ql_dbg_init, vha, 0x171, 6623 "Loading fwdump template from %x\n", 6624 (uint32_t)((void *)fwcode - (void *)blob->fw->data)); 6625 risc_size = be32_to_cpu(fwcode[2]); 6626 ql_dbg(ql_dbg_init, vha, 0x172, 6627 "-> array size %x dwords\n", risc_size); 6628 if (risc_size == 0 || risc_size == ~0) 6629 goto default_template; 6630 6631 dlen = (risc_size - 8) * sizeof(*fwcode); 6632 ql_dbg(ql_dbg_init, vha, 0x0173, 6633 "-> template allocating %x bytes...\n", dlen); 6634 ha->fw_dump_template = vmalloc(dlen); 6635 if (!ha->fw_dump_template) { 6636 ql_log(ql_log_warn, vha, 0x0174, 6637 "Failed fwdump template allocate %x bytes.\n", risc_size); 6638 goto default_template; 6639 } 6640 6641 fwcode += 7; 6642 risc_size -= 8; 6643 dcode = ha->fw_dump_template; 6644 for (i = 0; i < risc_size; i++) 6645 dcode[i] = le32_to_cpu(fwcode[i]); 6646 6647 if (!qla27xx_fwdt_template_valid(dcode)) { 6648 ql_log(ql_log_warn, vha, 0x0175, 6649 "Failed fwdump template validate\n"); 6650 goto default_template; 6651 } 6652 6653 dlen = qla27xx_fwdt_template_size(dcode); 6654 ql_dbg(ql_dbg_init, vha, 0x0176, 6655 "-> template size %x bytes\n", dlen); 6656 if (dlen > risc_size * sizeof(*fwcode)) { 6657 ql_log(ql_log_warn, vha, 0x0177, 6658 "Failed fwdump template exceeds array by %x bytes\n", 6659 (uint32_t)(dlen - risc_size * sizeof(*fwcode))); 6660 goto default_template; 6661 } 6662 ha->fw_dump_template_len = dlen; 6663 return rval; 6664 6665 default_template: 6666 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n"); 6667 if (ha->fw_dump_template) 6668 vfree(ha->fw_dump_template); 6669 ha->fw_dump_template = NULL; 6670 ha->fw_dump_template_len = 0; 6671 6672 dlen = qla27xx_fwdt_template_default_size(); 6673 ql_dbg(ql_dbg_init, vha, 0x0179, 6674 "-> template allocating %x bytes...\n", dlen); 6675 ha->fw_dump_template = vmalloc(dlen); 6676 if (!ha->fw_dump_template) { 6677 ql_log(ql_log_warn, vha, 0x017a, 6678 "Failed fwdump template allocate %x bytes.\n", risc_size); 6679 goto failed_template; 6680 } 6681 6682 dcode = ha->fw_dump_template; 6683 risc_size = dlen / sizeof(*fwcode); 6684 fwcode = qla27xx_fwdt_template_default(); 6685 for (i = 0; i < risc_size; i++) 6686 dcode[i] = be32_to_cpu(fwcode[i]); 6687 6688 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) { 6689 ql_log(ql_log_warn, vha, 0x017b, 6690 "Failed fwdump template validate\n"); 6691 goto failed_template; 6692 } 6693 6694 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template); 6695 ql_dbg(ql_dbg_init, vha, 0x017c, 6696 "-> template size %x bytes\n", dlen); 6697 ha->fw_dump_template_len = dlen; 6698 return rval; 6699 6700 failed_template: 6701 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n"); 6702 if (ha->fw_dump_template) 6703 vfree(ha->fw_dump_template); 6704 ha->fw_dump_template = NULL; 6705 ha->fw_dump_template_len = 0; 6706 return rval; 6707 } 6708 6709 int 6710 qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 6711 { 6712 int rval; 6713 6714 if (ql2xfwloadbin == 1) 6715 return qla81xx_load_risc(vha, srisc_addr); 6716 6717 /* 6718 * FW Load priority: 6719 * 1) Firmware via request-firmware interface (.bin file). 6720 * 2) Firmware residing in flash. 6721 */ 6722 rval = qla24xx_load_risc_blob(vha, srisc_addr); 6723 if (rval == QLA_SUCCESS) 6724 return rval; 6725 6726 return qla24xx_load_risc_flash(vha, srisc_addr, 6727 vha->hw->flt_region_fw); 6728 } 6729 6730 int 6731 qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 6732 { 6733 int rval; 6734 struct qla_hw_data *ha = vha->hw; 6735 6736 if (ql2xfwloadbin == 2) 6737 goto try_blob_fw; 6738 6739 /* 6740 * FW Load priority: 6741 * 1) Firmware residing in flash. 6742 * 2) Firmware via request-firmware interface (.bin file). 6743 * 3) Golden-Firmware residing in flash -- limited operation. 6744 */ 6745 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw); 6746 if (rval == QLA_SUCCESS) 6747 return rval; 6748 6749 try_blob_fw: 6750 rval = qla24xx_load_risc_blob(vha, srisc_addr); 6751 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw) 6752 return rval; 6753 6754 ql_log(ql_log_info, vha, 0x0099, 6755 "Attempting to fallback to golden firmware.\n"); 6756 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw); 6757 if (rval != QLA_SUCCESS) 6758 return rval; 6759 6760 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n"); 6761 ha->flags.running_gold_fw = 1; 6762 return rval; 6763 } 6764 6765 void 6766 qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) 6767 { 6768 int ret, retries; 6769 struct qla_hw_data *ha = vha->hw; 6770 6771 if (ha->flags.pci_channel_io_perm_failure) 6772 return; 6773 if (!IS_FWI2_CAPABLE(ha)) 6774 return; 6775 if (!ha->fw_major_version) 6776 return; 6777 if (!ha->flags.fw_started) 6778 return; 6779 6780 ret = qla2x00_stop_firmware(vha); 6781 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT && 6782 ret != QLA_INVALID_COMMAND && retries ; retries--) { 6783 ha->isp_ops->reset_chip(vha); 6784 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS) 6785 continue; 6786 if (qla2x00_setup_chip(vha) != QLA_SUCCESS) 6787 continue; 6788 ql_log(ql_log_info, vha, 0x8015, 6789 "Attempting retry of stop-firmware command.\n"); 6790 ret = qla2x00_stop_firmware(vha); 6791 } 6792 6793 ha->flags.fw_started = 0; 6794 ha->flags.fw_init_done = 0; 6795 } 6796 6797 int 6798 qla24xx_configure_vhba(scsi_qla_host_t *vha) 6799 { 6800 int rval = QLA_SUCCESS; 6801 int rval2; 6802 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6803 struct qla_hw_data *ha = vha->hw; 6804 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 6805 struct req_que *req; 6806 struct rsp_que *rsp; 6807 6808 if (!vha->vp_idx) 6809 return -EINVAL; 6810 6811 rval = qla2x00_fw_ready(base_vha); 6812 if (vha->qpair) 6813 req = vha->qpair->req; 6814 else 6815 req = ha->req_q_map[0]; 6816 rsp = req->rsp; 6817 6818 if (rval == QLA_SUCCESS) { 6819 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6820 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); 6821 } 6822 6823 vha->flags.management_server_logged_in = 0; 6824 6825 /* Login to SNS first */ 6826 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, 6827 BIT_1); 6828 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 6829 if (rval2 == QLA_MEMORY_ALLOC_FAILED) 6830 ql_dbg(ql_dbg_init, vha, 0x0120, 6831 "Failed SNS login: loop_id=%x, rval2=%d\n", 6832 NPH_SNS, rval2); 6833 else 6834 ql_dbg(ql_dbg_init, vha, 0x0103, 6835 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x " 6836 "mb[2]=%x mb[6]=%x mb[7]=%x.\n", 6837 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]); 6838 return (QLA_FUNCTION_FAILED); 6839 } 6840 6841 atomic_set(&vha->loop_down_timer, 0); 6842 atomic_set(&vha->loop_state, LOOP_UP); 6843 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 6844 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 6845 rval = qla2x00_loop_resync(base_vha); 6846 6847 return rval; 6848 } 6849 6850 /* 84XX Support **************************************************************/ 6851 6852 static LIST_HEAD(qla_cs84xx_list); 6853 static DEFINE_MUTEX(qla_cs84xx_mutex); 6854 6855 static struct qla_chip_state_84xx * 6856 qla84xx_get_chip(struct scsi_qla_host *vha) 6857 { 6858 struct qla_chip_state_84xx *cs84xx; 6859 struct qla_hw_data *ha = vha->hw; 6860 6861 mutex_lock(&qla_cs84xx_mutex); 6862 6863 /* Find any shared 84xx chip. */ 6864 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) { 6865 if (cs84xx->bus == ha->pdev->bus) { 6866 kref_get(&cs84xx->kref); 6867 goto done; 6868 } 6869 } 6870 6871 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL); 6872 if (!cs84xx) 6873 goto done; 6874 6875 kref_init(&cs84xx->kref); 6876 spin_lock_init(&cs84xx->access_lock); 6877 mutex_init(&cs84xx->fw_update_mutex); 6878 cs84xx->bus = ha->pdev->bus; 6879 6880 list_add_tail(&cs84xx->list, &qla_cs84xx_list); 6881 done: 6882 mutex_unlock(&qla_cs84xx_mutex); 6883 return cs84xx; 6884 } 6885 6886 static void 6887 __qla84xx_chip_release(struct kref *kref) 6888 { 6889 struct qla_chip_state_84xx *cs84xx = 6890 container_of(kref, struct qla_chip_state_84xx, kref); 6891 6892 mutex_lock(&qla_cs84xx_mutex); 6893 list_del(&cs84xx->list); 6894 mutex_unlock(&qla_cs84xx_mutex); 6895 kfree(cs84xx); 6896 } 6897 6898 void 6899 qla84xx_put_chip(struct scsi_qla_host *vha) 6900 { 6901 struct qla_hw_data *ha = vha->hw; 6902 if (ha->cs84xx) 6903 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release); 6904 } 6905 6906 static int 6907 qla84xx_init_chip(scsi_qla_host_t *vha) 6908 { 6909 int rval; 6910 uint16_t status[2]; 6911 struct qla_hw_data *ha = vha->hw; 6912 6913 mutex_lock(&ha->cs84xx->fw_update_mutex); 6914 6915 rval = qla84xx_verify_chip(vha, status); 6916 6917 mutex_unlock(&ha->cs84xx->fw_update_mutex); 6918 6919 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED: 6920 QLA_SUCCESS; 6921 } 6922 6923 /* 81XX Support **************************************************************/ 6924 6925 int 6926 qla81xx_nvram_config(scsi_qla_host_t *vha) 6927 { 6928 int rval; 6929 struct init_cb_81xx *icb; 6930 struct nvram_81xx *nv; 6931 uint32_t *dptr; 6932 uint8_t *dptr1, *dptr2; 6933 uint32_t chksum; 6934 uint16_t cnt; 6935 struct qla_hw_data *ha = vha->hw; 6936 6937 rval = QLA_SUCCESS; 6938 icb = (struct init_cb_81xx *)ha->init_cb; 6939 nv = ha->nvram; 6940 6941 /* Determine NVRAM starting address. */ 6942 ha->nvram_size = sizeof(struct nvram_81xx); 6943 ha->vpd_size = FA_NVRAM_VPD_SIZE; 6944 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 6945 ha->vpd_size = FA_VPD_SIZE_82XX; 6946 6947 /* Get VPD data into cache */ 6948 ha->vpd = ha->nvram + VPD_OFFSET; 6949 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2, 6950 ha->vpd_size); 6951 6952 /* Get NVRAM data into cache and calculate checksum. */ 6953 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2, 6954 ha->nvram_size); 6955 dptr = (uint32_t *)nv; 6956 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 6957 chksum += le32_to_cpu(*dptr); 6958 6959 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111, 6960 "Contents of NVRAM:\n"); 6961 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112, 6962 (uint8_t *)nv, ha->nvram_size); 6963 6964 /* Bad NVRAM data, set defaults parameters. */ 6965 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' 6966 || nv->id[3] != ' ' || 6967 nv->nvram_version < cpu_to_le16(ICB_VERSION)) { 6968 /* Reset NVRAM data. */ 6969 ql_log(ql_log_info, vha, 0x0073, 6970 "Inconsistent NVRAM detected: checksum=0x%x id=%c " 6971 "version=0x%x.\n", chksum, nv->id[0], 6972 le16_to_cpu(nv->nvram_version)); 6973 ql_log(ql_log_info, vha, 0x0074, 6974 "Falling back to functioning (yet invalid -- WWPN) " 6975 "defaults.\n"); 6976 6977 /* 6978 * Set default initialization control block. 6979 */ 6980 memset(nv, 0, ha->nvram_size); 6981 nv->nvram_version = cpu_to_le16(ICB_VERSION); 6982 nv->version = cpu_to_le16(ICB_VERSION); 6983 nv->frame_payload_size = 2048; 6984 nv->execution_throttle = cpu_to_le16(0xFFFF); 6985 nv->exchange_count = cpu_to_le16(0); 6986 nv->port_name[0] = 0x21; 6987 nv->port_name[1] = 0x00 + ha->port_no + 1; 6988 nv->port_name[2] = 0x00; 6989 nv->port_name[3] = 0xe0; 6990 nv->port_name[4] = 0x8b; 6991 nv->port_name[5] = 0x1c; 6992 nv->port_name[6] = 0x55; 6993 nv->port_name[7] = 0x86; 6994 nv->node_name[0] = 0x20; 6995 nv->node_name[1] = 0x00; 6996 nv->node_name[2] = 0x00; 6997 nv->node_name[3] = 0xe0; 6998 nv->node_name[4] = 0x8b; 6999 nv->node_name[5] = 0x1c; 7000 nv->node_name[6] = 0x55; 7001 nv->node_name[7] = 0x86; 7002 nv->login_retry_count = cpu_to_le16(8); 7003 nv->interrupt_delay_timer = cpu_to_le16(0); 7004 nv->login_timeout = cpu_to_le16(0); 7005 nv->firmware_options_1 = 7006 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 7007 nv->firmware_options_2 = cpu_to_le32(2 << 4); 7008 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 7009 nv->firmware_options_3 = cpu_to_le32(2 << 13); 7010 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 7011 nv->efi_parameters = cpu_to_le32(0); 7012 nv->reset_delay = 5; 7013 nv->max_luns_per_target = cpu_to_le16(128); 7014 nv->port_down_retry_count = cpu_to_le16(30); 7015 nv->link_down_timeout = cpu_to_le16(180); 7016 nv->enode_mac[0] = 0x00; 7017 nv->enode_mac[1] = 0xC0; 7018 nv->enode_mac[2] = 0xDD; 7019 nv->enode_mac[3] = 0x04; 7020 nv->enode_mac[4] = 0x05; 7021 nv->enode_mac[5] = 0x06 + ha->port_no + 1; 7022 7023 rval = 1; 7024 } 7025 7026 if (IS_T10_PI_CAPABLE(ha)) 7027 nv->frame_payload_size &= ~7; 7028 7029 qlt_81xx_config_nvram_stage1(vha, nv); 7030 7031 /* Reset Initialization control block */ 7032 memset(icb, 0, ha->init_cb_size); 7033 7034 /* Copy 1st segment. */ 7035 dptr1 = (uint8_t *)icb; 7036 dptr2 = (uint8_t *)&nv->version; 7037 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 7038 while (cnt--) 7039 *dptr1++ = *dptr2++; 7040 7041 icb->login_retry_count = nv->login_retry_count; 7042 7043 /* Copy 2nd segment. */ 7044 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 7045 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 7046 cnt = (uint8_t *)&icb->reserved_5 - 7047 (uint8_t *)&icb->interrupt_delay_timer; 7048 while (cnt--) 7049 *dptr1++ = *dptr2++; 7050 7051 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac)); 7052 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */ 7053 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) { 7054 icb->enode_mac[0] = 0x00; 7055 icb->enode_mac[1] = 0xC0; 7056 icb->enode_mac[2] = 0xDD; 7057 icb->enode_mac[3] = 0x04; 7058 icb->enode_mac[4] = 0x05; 7059 icb->enode_mac[5] = 0x06 + ha->port_no + 1; 7060 } 7061 7062 /* Use extended-initialization control block. */ 7063 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb)); 7064 7065 /* 7066 * Setup driver NVRAM options. 7067 */ 7068 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 7069 "QLE8XXX"); 7070 7071 qlt_81xx_config_nvram_stage2(vha, icb); 7072 7073 /* Use alternate WWN? */ 7074 if (nv->host_p & cpu_to_le32(BIT_15)) { 7075 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 7076 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 7077 } 7078 7079 /* Prepare nodename */ 7080 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 7081 /* 7082 * Firmware will apply the following mask if the nodename was 7083 * not provided. 7084 */ 7085 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 7086 icb->node_name[0] &= 0xF0; 7087 } 7088 7089 /* Set host adapter parameters. */ 7090 ha->flags.disable_risc_code_load = 0; 7091 ha->flags.enable_lip_reset = 0; 7092 ha->flags.enable_lip_full_login = 7093 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; 7094 ha->flags.enable_target_reset = 7095 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; 7096 ha->flags.enable_led_scheme = 0; 7097 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; 7098 7099 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 7100 (BIT_6 | BIT_5 | BIT_4)) >> 4; 7101 7102 /* save HBA serial number */ 7103 ha->serial0 = icb->port_name[5]; 7104 ha->serial1 = icb->port_name[6]; 7105 ha->serial2 = icb->port_name[7]; 7106 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 7107 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 7108 7109 icb->execution_throttle = cpu_to_le16(0xFFFF); 7110 7111 ha->retry_count = le16_to_cpu(nv->login_retry_count); 7112 7113 /* Set minimum login_timeout to 4 seconds. */ 7114 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 7115 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 7116 if (le16_to_cpu(nv->login_timeout) < 4) 7117 nv->login_timeout = cpu_to_le16(4); 7118 ha->login_timeout = le16_to_cpu(nv->login_timeout); 7119 7120 /* Set minimum RATOV to 100 tenths of a second. */ 7121 ha->r_a_tov = 100; 7122 7123 ha->loop_reset_delay = nv->reset_delay; 7124 7125 /* Link Down Timeout = 0: 7126 * 7127 * When Port Down timer expires we will start returning 7128 * I/O's to OS with "DID_NO_CONNECT". 7129 * 7130 * Link Down Timeout != 0: 7131 * 7132 * The driver waits for the link to come up after link down 7133 * before returning I/Os to OS with "DID_NO_CONNECT". 7134 */ 7135 if (le16_to_cpu(nv->link_down_timeout) == 0) { 7136 ha->loop_down_abort_time = 7137 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 7138 } else { 7139 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 7140 ha->loop_down_abort_time = 7141 (LOOP_DOWN_TIME - ha->link_down_timeout); 7142 } 7143 7144 /* Need enough time to try and get the port back. */ 7145 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 7146 if (qlport_down_retry) 7147 ha->port_down_retry_count = qlport_down_retry; 7148 7149 /* Set login_retry_count */ 7150 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 7151 if (ha->port_down_retry_count == 7152 le16_to_cpu(nv->port_down_retry_count) && 7153 ha->port_down_retry_count > 3) 7154 ha->login_retry_count = ha->port_down_retry_count; 7155 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 7156 ha->login_retry_count = ha->port_down_retry_count; 7157 if (ql2xloginretrycount) 7158 ha->login_retry_count = ql2xloginretrycount; 7159 7160 /* if not running MSI-X we need handshaking on interrupts */ 7161 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha))) 7162 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 7163 7164 /* Enable ZIO. */ 7165 if (!vha->flags.init_done) { 7166 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 7167 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 7168 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 7169 le16_to_cpu(icb->interrupt_delay_timer): 2; 7170 } 7171 icb->firmware_options_2 &= cpu_to_le32( 7172 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 7173 vha->flags.process_response_queue = 0; 7174 if (ha->zio_mode != QLA_ZIO_DISABLED) { 7175 ha->zio_mode = QLA_ZIO_MODE_6; 7176 7177 ql_log(ql_log_info, vha, 0x0075, 7178 "ZIO mode %d enabled; timer delay (%d us).\n", 7179 ha->zio_mode, 7180 ha->zio_timer * 100); 7181 7182 icb->firmware_options_2 |= cpu_to_le32( 7183 (uint32_t)ha->zio_mode); 7184 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 7185 vha->flags.process_response_queue = 1; 7186 } 7187 7188 /* enable RIDA Format2 */ 7189 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) 7190 icb->firmware_options_3 |= BIT_0; 7191 7192 if (rval) { 7193 ql_log(ql_log_warn, vha, 0x0076, 7194 "NVRAM configuration failed.\n"); 7195 } 7196 return (rval); 7197 } 7198 7199 int 7200 qla82xx_restart_isp(scsi_qla_host_t *vha) 7201 { 7202 int status, rval; 7203 struct qla_hw_data *ha = vha->hw; 7204 struct req_que *req = ha->req_q_map[0]; 7205 struct rsp_que *rsp = ha->rsp_q_map[0]; 7206 struct scsi_qla_host *vp; 7207 unsigned long flags; 7208 7209 status = qla2x00_init_rings(vha); 7210 if (!status) { 7211 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7212 ha->flags.chip_reset_done = 1; 7213 7214 status = qla2x00_fw_ready(vha); 7215 if (!status) { 7216 /* Issue a marker after FW becomes ready. */ 7217 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); 7218 vha->flags.online = 1; 7219 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 7220 } 7221 7222 /* if no cable then assume it's good */ 7223 if ((vha->device_flags & DFLG_NO_CABLE)) 7224 status = 0; 7225 } 7226 7227 if (!status) { 7228 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7229 7230 if (!atomic_read(&vha->loop_down_timer)) { 7231 /* 7232 * Issue marker command only when we are going 7233 * to start the I/O . 7234 */ 7235 vha->marker_needed = 1; 7236 } 7237 7238 ha->isp_ops->enable_intrs(ha); 7239 7240 ha->isp_abort_cnt = 0; 7241 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7242 7243 /* Update the firmware version */ 7244 status = qla82xx_check_md_needed(vha); 7245 7246 if (ha->fce) { 7247 ha->flags.fce_enabled = 1; 7248 memset(ha->fce, 0, 7249 fce_calc_size(ha->fce_bufs)); 7250 rval = qla2x00_enable_fce_trace(vha, 7251 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 7252 &ha->fce_bufs); 7253 if (rval) { 7254 ql_log(ql_log_warn, vha, 0x8001, 7255 "Unable to reinitialize FCE (%d).\n", 7256 rval); 7257 ha->flags.fce_enabled = 0; 7258 } 7259 } 7260 7261 if (ha->eft) { 7262 memset(ha->eft, 0, EFT_SIZE); 7263 rval = qla2x00_enable_eft_trace(vha, 7264 ha->eft_dma, EFT_NUM_BUFFERS); 7265 if (rval) { 7266 ql_log(ql_log_warn, vha, 0x8010, 7267 "Unable to reinitialize EFT (%d).\n", 7268 rval); 7269 } 7270 } 7271 } 7272 7273 if (!status) { 7274 ql_dbg(ql_dbg_taskm, vha, 0x8011, 7275 "qla82xx_restart_isp succeeded.\n"); 7276 7277 spin_lock_irqsave(&ha->vport_slock, flags); 7278 list_for_each_entry(vp, &ha->vp_list, list) { 7279 if (vp->vp_idx) { 7280 atomic_inc(&vp->vref_count); 7281 spin_unlock_irqrestore(&ha->vport_slock, flags); 7282 7283 qla2x00_vp_abort_isp(vp); 7284 7285 spin_lock_irqsave(&ha->vport_slock, flags); 7286 atomic_dec(&vp->vref_count); 7287 } 7288 } 7289 spin_unlock_irqrestore(&ha->vport_slock, flags); 7290 7291 } else { 7292 ql_log(ql_log_warn, vha, 0x8016, 7293 "qla82xx_restart_isp **** FAILED ****.\n"); 7294 } 7295 7296 return status; 7297 } 7298 7299 void 7300 qla81xx_update_fw_options(scsi_qla_host_t *vha) 7301 { 7302 struct qla_hw_data *ha = vha->hw; 7303 7304 /* Hold status IOCBs until ABTS response received. */ 7305 if (ql2xfwholdabts) 7306 ha->fw_options[3] |= BIT_12; 7307 7308 /* Set Retry FLOGI in case of P2P connection */ 7309 if (ha->operating_mode == P2P) { 7310 ha->fw_options[2] |= BIT_3; 7311 ql_dbg(ql_dbg_disc, vha, 0x2103, 7312 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 7313 __func__, ha->fw_options[2]); 7314 } 7315 7316 /* Move PUREX, ABTS RX & RIDA to ATIOQ */ 7317 if (ql2xmvasynctoatio) { 7318 if (qla_tgt_mode_enabled(vha) || 7319 qla_dual_mode_enabled(vha)) 7320 ha->fw_options[2] |= BIT_11; 7321 else 7322 ha->fw_options[2] &= ~BIT_11; 7323 } 7324 7325 if (ql2xetsenable) { 7326 /* Enable ETS Burst. */ 7327 memset(ha->fw_options, 0, sizeof(ha->fw_options)); 7328 ha->fw_options[2] |= BIT_9; 7329 } 7330 7331 ql_dbg(ql_dbg_init, vha, 0xffff, 7332 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n", 7333 __func__, ha->fw_options[1], ha->fw_options[2], 7334 ha->fw_options[3], vha->host->active_mode); 7335 7336 qla2x00_set_fw_options(vha, ha->fw_options); 7337 } 7338 7339 /* 7340 * qla24xx_get_fcp_prio 7341 * Gets the fcp cmd priority value for the logged in port. 7342 * Looks for a match of the port descriptors within 7343 * each of the fcp prio config entries. If a match is found, 7344 * the tag (priority) value is returned. 7345 * 7346 * Input: 7347 * vha = scsi host structure pointer. 7348 * fcport = port structure pointer. 7349 * 7350 * Return: 7351 * non-zero (if found) 7352 * -1 (if not found) 7353 * 7354 * Context: 7355 * Kernel context 7356 */ 7357 static int 7358 qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 7359 { 7360 int i, entries; 7361 uint8_t pid_match, wwn_match; 7362 int priority; 7363 uint32_t pid1, pid2; 7364 uint64_t wwn1, wwn2; 7365 struct qla_fcp_prio_entry *pri_entry; 7366 struct qla_hw_data *ha = vha->hw; 7367 7368 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled) 7369 return -1; 7370 7371 priority = -1; 7372 entries = ha->fcp_prio_cfg->num_entries; 7373 pri_entry = &ha->fcp_prio_cfg->entry[0]; 7374 7375 for (i = 0; i < entries; i++) { 7376 pid_match = wwn_match = 0; 7377 7378 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) { 7379 pri_entry++; 7380 continue; 7381 } 7382 7383 /* check source pid for a match */ 7384 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) { 7385 pid1 = pri_entry->src_pid & INVALID_PORT_ID; 7386 pid2 = vha->d_id.b24 & INVALID_PORT_ID; 7387 if (pid1 == INVALID_PORT_ID) 7388 pid_match++; 7389 else if (pid1 == pid2) 7390 pid_match++; 7391 } 7392 7393 /* check destination pid for a match */ 7394 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) { 7395 pid1 = pri_entry->dst_pid & INVALID_PORT_ID; 7396 pid2 = fcport->d_id.b24 & INVALID_PORT_ID; 7397 if (pid1 == INVALID_PORT_ID) 7398 pid_match++; 7399 else if (pid1 == pid2) 7400 pid_match++; 7401 } 7402 7403 /* check source WWN for a match */ 7404 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) { 7405 wwn1 = wwn_to_u64(vha->port_name); 7406 wwn2 = wwn_to_u64(pri_entry->src_wwpn); 7407 if (wwn2 == (uint64_t)-1) 7408 wwn_match++; 7409 else if (wwn1 == wwn2) 7410 wwn_match++; 7411 } 7412 7413 /* check destination WWN for a match */ 7414 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) { 7415 wwn1 = wwn_to_u64(fcport->port_name); 7416 wwn2 = wwn_to_u64(pri_entry->dst_wwpn); 7417 if (wwn2 == (uint64_t)-1) 7418 wwn_match++; 7419 else if (wwn1 == wwn2) 7420 wwn_match++; 7421 } 7422 7423 if (pid_match == 2 || wwn_match == 2) { 7424 /* Found a matching entry */ 7425 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID) 7426 priority = pri_entry->tag; 7427 break; 7428 } 7429 7430 pri_entry++; 7431 } 7432 7433 return priority; 7434 } 7435 7436 /* 7437 * qla24xx_update_fcport_fcp_prio 7438 * Activates fcp priority for the logged in fc port 7439 * 7440 * Input: 7441 * vha = scsi host structure pointer. 7442 * fcp = port structure pointer. 7443 * 7444 * Return: 7445 * QLA_SUCCESS or QLA_FUNCTION_FAILED 7446 * 7447 * Context: 7448 * Kernel context. 7449 */ 7450 int 7451 qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 7452 { 7453 int ret; 7454 int priority; 7455 uint16_t mb[5]; 7456 7457 if (fcport->port_type != FCT_TARGET || 7458 fcport->loop_id == FC_NO_LOOP_ID) 7459 return QLA_FUNCTION_FAILED; 7460 7461 priority = qla24xx_get_fcp_prio(vha, fcport); 7462 if (priority < 0) 7463 return QLA_FUNCTION_FAILED; 7464 7465 if (IS_P3P_TYPE(vha->hw)) { 7466 fcport->fcp_prio = priority & 0xf; 7467 return QLA_SUCCESS; 7468 } 7469 7470 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb); 7471 if (ret == QLA_SUCCESS) { 7472 if (fcport->fcp_prio != priority) 7473 ql_dbg(ql_dbg_user, vha, 0x709e, 7474 "Updated FCP_CMND priority - value=%d loop_id=%d " 7475 "port_id=%02x%02x%02x.\n", priority, 7476 fcport->loop_id, fcport->d_id.b.domain, 7477 fcport->d_id.b.area, fcport->d_id.b.al_pa); 7478 fcport->fcp_prio = priority & 0xf; 7479 } else 7480 ql_dbg(ql_dbg_user, vha, 0x704f, 7481 "Unable to update FCP_CMND priority - ret=0x%x for " 7482 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id, 7483 fcport->d_id.b.domain, fcport->d_id.b.area, 7484 fcport->d_id.b.al_pa); 7485 return ret; 7486 } 7487 7488 /* 7489 * qla24xx_update_all_fcp_prio 7490 * Activates fcp priority for all the logged in ports 7491 * 7492 * Input: 7493 * ha = adapter block pointer. 7494 * 7495 * Return: 7496 * QLA_SUCCESS or QLA_FUNCTION_FAILED 7497 * 7498 * Context: 7499 * Kernel context. 7500 */ 7501 int 7502 qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha) 7503 { 7504 int ret; 7505 fc_port_t *fcport; 7506 7507 ret = QLA_FUNCTION_FAILED; 7508 /* We need to set priority for all logged in ports */ 7509 list_for_each_entry(fcport, &vha->vp_fcports, list) 7510 ret = qla24xx_update_fcport_fcp_prio(vha, fcport); 7511 7512 return ret; 7513 } 7514 7515 struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, int vp_idx) 7516 { 7517 int rsp_id = 0; 7518 int req_id = 0; 7519 int i; 7520 struct qla_hw_data *ha = vha->hw; 7521 uint16_t qpair_id = 0; 7522 struct qla_qpair *qpair = NULL; 7523 struct qla_msix_entry *msix; 7524 7525 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) { 7526 ql_log(ql_log_warn, vha, 0x00181, 7527 "FW/Driver is not multi-queue capable.\n"); 7528 return NULL; 7529 } 7530 7531 if (ql2xmqsupport) { 7532 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 7533 if (qpair == NULL) { 7534 ql_log(ql_log_warn, vha, 0x0182, 7535 "Failed to allocate memory for queue pair.\n"); 7536 return NULL; 7537 } 7538 memset(qpair, 0, sizeof(struct qla_qpair)); 7539 7540 qpair->hw = vha->hw; 7541 qpair->vha = vha; 7542 7543 /* Assign available que pair id */ 7544 mutex_lock(&ha->mq_lock); 7545 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs); 7546 if (qpair_id >= ha->max_qpairs) { 7547 mutex_unlock(&ha->mq_lock); 7548 ql_log(ql_log_warn, vha, 0x0183, 7549 "No resources to create additional q pair.\n"); 7550 goto fail_qid_map; 7551 } 7552 set_bit(qpair_id, ha->qpair_qid_map); 7553 ha->queue_pair_map[qpair_id] = qpair; 7554 qpair->id = qpair_id; 7555 qpair->vp_idx = vp_idx; 7556 7557 for (i = 0; i < ha->msix_count; i++) { 7558 msix = &ha->msix_entries[i]; 7559 if (msix->in_use) 7560 continue; 7561 qpair->msix = msix; 7562 ql_log(ql_dbg_multiq, vha, 0xc00f, 7563 "Vector %x selected for qpair\n", msix->vector); 7564 break; 7565 } 7566 if (!qpair->msix) { 7567 ql_log(ql_log_warn, vha, 0x0184, 7568 "Out of MSI-X vectors!.\n"); 7569 goto fail_msix; 7570 } 7571 7572 qpair->msix->in_use = 1; 7573 list_add_tail(&qpair->qp_list_elem, &vha->qp_list); 7574 7575 mutex_unlock(&ha->mq_lock); 7576 7577 /* Create response queue first */ 7578 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair); 7579 if (!rsp_id) { 7580 ql_log(ql_log_warn, vha, 0x0185, 7581 "Failed to create response queue.\n"); 7582 goto fail_rsp; 7583 } 7584 7585 qpair->rsp = ha->rsp_q_map[rsp_id]; 7586 7587 /* Create request queue */ 7588 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos); 7589 if (!req_id) { 7590 ql_log(ql_log_warn, vha, 0x0186, 7591 "Failed to create request queue.\n"); 7592 goto fail_req; 7593 } 7594 7595 qpair->req = ha->req_q_map[req_id]; 7596 qpair->rsp->req = qpair->req; 7597 7598 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 7599 if (ha->fw_attributes & BIT_4) 7600 qpair->difdix_supported = 1; 7601 } 7602 7603 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 7604 if (!qpair->srb_mempool) { 7605 ql_log(ql_log_warn, vha, 0x0191, 7606 "Failed to create srb mempool for qpair %d\n", 7607 qpair->id); 7608 goto fail_mempool; 7609 } 7610 7611 /* Mark as online */ 7612 qpair->online = 1; 7613 7614 if (!vha->flags.qpairs_available) 7615 vha->flags.qpairs_available = 1; 7616 7617 ql_dbg(ql_dbg_multiq, vha, 0xc00d, 7618 "Request/Response queue pair created, id %d\n", 7619 qpair->id); 7620 ql_dbg(ql_dbg_init, vha, 0x0187, 7621 "Request/Response queue pair created, id %d\n", 7622 qpair->id); 7623 } 7624 return qpair; 7625 7626 fail_mempool: 7627 fail_req: 7628 qla25xx_delete_rsp_que(vha, qpair->rsp); 7629 fail_rsp: 7630 mutex_lock(&ha->mq_lock); 7631 qpair->msix->in_use = 0; 7632 list_del(&qpair->qp_list_elem); 7633 if (list_empty(&vha->qp_list)) 7634 vha->flags.qpairs_available = 0; 7635 fail_msix: 7636 ha->queue_pair_map[qpair_id] = NULL; 7637 clear_bit(qpair_id, ha->qpair_qid_map); 7638 mutex_unlock(&ha->mq_lock); 7639 fail_qid_map: 7640 kfree(qpair); 7641 return NULL; 7642 } 7643 7644 int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair) 7645 { 7646 int ret; 7647 struct qla_hw_data *ha = qpair->hw; 7648 7649 qpair->delete_in_progress = 1; 7650 while (atomic_read(&qpair->ref_count)) 7651 msleep(500); 7652 7653 ret = qla25xx_delete_req_que(vha, qpair->req); 7654 if (ret != QLA_SUCCESS) 7655 goto fail; 7656 ret = qla25xx_delete_rsp_que(vha, qpair->rsp); 7657 if (ret != QLA_SUCCESS) 7658 goto fail; 7659 7660 mutex_lock(&ha->mq_lock); 7661 ha->queue_pair_map[qpair->id] = NULL; 7662 clear_bit(qpair->id, ha->qpair_qid_map); 7663 list_del(&qpair->qp_list_elem); 7664 if (list_empty(&vha->qp_list)) 7665 vha->flags.qpairs_available = 0; 7666 mempool_destroy(qpair->srb_mempool); 7667 kfree(qpair); 7668 mutex_unlock(&ha->mq_lock); 7669 7670 return QLA_SUCCESS; 7671 fail: 7672 return ret; 7673 } 7674