1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_gbl.h" 9 10 #include <linux/delay.h> 11 #include <linux/slab.h> 12 #include <linux/vmalloc.h> 13 14 #include "qla_devtbl.h" 15 16 #ifdef CONFIG_SPARC 17 #include <asm/prom.h> 18 #endif 19 20 #include <target/target_core_base.h> 21 #include "qla_target.h" 22 23 /* 24 * QLogic ISP2x00 Hardware Support Function Prototypes. 25 */ 26 static int qla2x00_isp_firmware(scsi_qla_host_t *); 27 static int qla2x00_setup_chip(scsi_qla_host_t *); 28 static int qla2x00_fw_ready(scsi_qla_host_t *); 29 static int qla2x00_configure_hba(scsi_qla_host_t *); 30 static int qla2x00_configure_loop(scsi_qla_host_t *); 31 static int qla2x00_configure_local_loop(scsi_qla_host_t *); 32 static int qla2x00_configure_fabric(scsi_qla_host_t *); 33 static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *); 34 static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *, 35 uint16_t *); 36 37 static int qla2x00_restart_isp(scsi_qla_host_t *); 38 39 static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *); 40 static int qla84xx_init_chip(scsi_qla_host_t *); 41 static int qla25xx_init_queues(struct qla_hw_data *); 42 43 /* SRB Extensions ---------------------------------------------------------- */ 44 45 void 46 qla2x00_sp_timeout(unsigned long __data) 47 { 48 srb_t *sp = (srb_t *)__data; 49 struct srb_iocb *iocb; 50 fc_port_t *fcport = sp->fcport; 51 struct qla_hw_data *ha = fcport->vha->hw; 52 struct req_que *req; 53 unsigned long flags; 54 55 spin_lock_irqsave(&ha->hardware_lock, flags); 56 req = ha->req_q_map[0]; 57 req->outstanding_cmds[sp->handle] = NULL; 58 iocb = &sp->u.iocb_cmd; 59 iocb->timeout(sp); 60 sp->free(fcport->vha, sp); 61 spin_unlock_irqrestore(&ha->hardware_lock, flags); 62 } 63 64 void 65 qla2x00_sp_free(void *data, void *ptr) 66 { 67 srb_t *sp = (srb_t *)ptr; 68 struct srb_iocb *iocb = &sp->u.iocb_cmd; 69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data; 70 71 del_timer(&iocb->timer); 72 qla2x00_rel_sp(vha, sp); 73 } 74 75 /* Asynchronous Login/Logout Routines -------------------------------------- */ 76 77 unsigned long 78 qla2x00_get_async_timeout(struct scsi_qla_host *vha) 79 { 80 unsigned long tmo; 81 struct qla_hw_data *ha = vha->hw; 82 83 /* Firmware should use switch negotiated r_a_tov for timeout. */ 84 tmo = ha->r_a_tov / 10 * 2; 85 if (IS_QLAFX00(ha)) { 86 tmo = FX00_DEF_RATOV * 2; 87 } else if (!IS_FWI2_CAPABLE(ha)) { 88 /* 89 * Except for earlier ISPs where the timeout is seeded from the 90 * initialization control block. 91 */ 92 tmo = ha->login_timeout; 93 } 94 return tmo; 95 } 96 97 static void 98 qla2x00_async_iocb_timeout(void *data) 99 { 100 srb_t *sp = (srb_t *)data; 101 fc_port_t *fcport = sp->fcport; 102 103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, 104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n", 105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area, 106 fcport->d_id.b.al_pa); 107 108 fcport->flags &= ~FCF_ASYNC_SENT; 109 if (sp->type == SRB_LOGIN_CMD) { 110 struct srb_iocb *lio = &sp->u.iocb_cmd; 111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL); 112 /* Retry as needed. */ 113 lio->u.logio.data[0] = MBS_COMMAND_ERROR; 114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ? 115 QLA_LOGIO_LOGIN_RETRIED : 0; 116 qla2x00_post_async_login_done_work(fcport->vha, fcport, 117 lio->u.logio.data); 118 } 119 } 120 121 static void 122 qla2x00_async_login_sp_done(void *data, void *ptr, int res) 123 { 124 srb_t *sp = (srb_t *)ptr; 125 struct srb_iocb *lio = &sp->u.iocb_cmd; 126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data; 127 128 if (!test_bit(UNLOADING, &vha->dpc_flags)) 129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport, 130 lio->u.logio.data); 131 sp->free(sp->fcport->vha, sp); 132 } 133 134 int 135 qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport, 136 uint16_t *data) 137 { 138 srb_t *sp; 139 struct srb_iocb *lio; 140 int rval; 141 142 rval = QLA_FUNCTION_FAILED; 143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 144 if (!sp) 145 goto done; 146 147 sp->type = SRB_LOGIN_CMD; 148 sp->name = "login"; 149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 150 151 lio = &sp->u.iocb_cmd; 152 lio->timeout = qla2x00_async_iocb_timeout; 153 sp->done = qla2x00_async_login_sp_done; 154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI; 155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 156 lio->u.logio.flags |= SRB_LOGIN_RETRIED; 157 rval = qla2x00_start_sp(sp); 158 if (rval != QLA_SUCCESS) 159 goto done_free_sp; 160 161 ql_dbg(ql_dbg_disc, vha, 0x2072, 162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x " 163 "retries=%d.\n", sp->handle, fcport->loop_id, 164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa, 165 fcport->login_retry); 166 return rval; 167 168 done_free_sp: 169 sp->free(fcport->vha, sp); 170 done: 171 return rval; 172 } 173 174 static void 175 qla2x00_async_logout_sp_done(void *data, void *ptr, int res) 176 { 177 srb_t *sp = (srb_t *)ptr; 178 struct srb_iocb *lio = &sp->u.iocb_cmd; 179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data; 180 181 if (!test_bit(UNLOADING, &vha->dpc_flags)) 182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport, 183 lio->u.logio.data); 184 sp->free(sp->fcport->vha, sp); 185 } 186 187 int 188 qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport) 189 { 190 srb_t *sp; 191 struct srb_iocb *lio; 192 int rval; 193 194 rval = QLA_FUNCTION_FAILED; 195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 196 if (!sp) 197 goto done; 198 199 sp->type = SRB_LOGOUT_CMD; 200 sp->name = "logout"; 201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 202 203 lio = &sp->u.iocb_cmd; 204 lio->timeout = qla2x00_async_iocb_timeout; 205 sp->done = qla2x00_async_logout_sp_done; 206 rval = qla2x00_start_sp(sp); 207 if (rval != QLA_SUCCESS) 208 goto done_free_sp; 209 210 ql_dbg(ql_dbg_disc, vha, 0x2070, 211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 212 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 213 fcport->d_id.b.area, fcport->d_id.b.al_pa); 214 return rval; 215 216 done_free_sp: 217 sp->free(fcport->vha, sp); 218 done: 219 return rval; 220 } 221 222 static void 223 qla2x00_async_adisc_sp_done(void *data, void *ptr, int res) 224 { 225 srb_t *sp = (srb_t *)ptr; 226 struct srb_iocb *lio = &sp->u.iocb_cmd; 227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data; 228 229 if (!test_bit(UNLOADING, &vha->dpc_flags)) 230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport, 231 lio->u.logio.data); 232 sp->free(sp->fcport->vha, sp); 233 } 234 235 int 236 qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport, 237 uint16_t *data) 238 { 239 srb_t *sp; 240 struct srb_iocb *lio; 241 int rval; 242 243 rval = QLA_FUNCTION_FAILED; 244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 245 if (!sp) 246 goto done; 247 248 sp->type = SRB_ADISC_CMD; 249 sp->name = "adisc"; 250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 251 252 lio = &sp->u.iocb_cmd; 253 lio->timeout = qla2x00_async_iocb_timeout; 254 sp->done = qla2x00_async_adisc_sp_done; 255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 256 lio->u.logio.flags |= SRB_LOGIN_RETRIED; 257 rval = qla2x00_start_sp(sp); 258 if (rval != QLA_SUCCESS) 259 goto done_free_sp; 260 261 ql_dbg(ql_dbg_disc, vha, 0x206f, 262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n", 263 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 264 fcport->d_id.b.area, fcport->d_id.b.al_pa); 265 return rval; 266 267 done_free_sp: 268 sp->free(fcport->vha, sp); 269 done: 270 return rval; 271 } 272 273 static void 274 qla2x00_tmf_iocb_timeout(void *data) 275 { 276 srb_t *sp = (srb_t *)data; 277 struct srb_iocb *tmf = &sp->u.iocb_cmd; 278 279 tmf->u.tmf.comp_status = CS_TIMEOUT; 280 complete(&tmf->u.tmf.comp); 281 } 282 283 static void 284 qla2x00_tmf_sp_done(void *data, void *ptr, int res) 285 { 286 srb_t *sp = (srb_t *)ptr; 287 struct srb_iocb *tmf = &sp->u.iocb_cmd; 288 complete(&tmf->u.tmf.comp); 289 } 290 291 int 292 qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun, 293 uint32_t tag) 294 { 295 struct scsi_qla_host *vha = fcport->vha; 296 struct srb_iocb *tm_iocb; 297 srb_t *sp; 298 int rval = QLA_FUNCTION_FAILED; 299 300 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 301 if (!sp) 302 goto done; 303 304 tm_iocb = &sp->u.iocb_cmd; 305 sp->type = SRB_TM_CMD; 306 sp->name = "tmf"; 307 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)); 308 tm_iocb->u.tmf.flags = flags; 309 tm_iocb->u.tmf.lun = lun; 310 tm_iocb->u.tmf.data = tag; 311 sp->done = qla2x00_tmf_sp_done; 312 tm_iocb->timeout = qla2x00_tmf_iocb_timeout; 313 init_completion(&tm_iocb->u.tmf.comp); 314 315 rval = qla2x00_start_sp(sp); 316 if (rval != QLA_SUCCESS) 317 goto done_free_sp; 318 319 ql_dbg(ql_dbg_taskm, vha, 0x802f, 320 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 321 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 322 fcport->d_id.b.area, fcport->d_id.b.al_pa); 323 324 wait_for_completion(&tm_iocb->u.tmf.comp); 325 326 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ? 327 QLA_SUCCESS : QLA_FUNCTION_FAILED; 328 329 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) { 330 ql_dbg(ql_dbg_taskm, vha, 0x8030, 331 "TM IOCB failed (%x).\n", rval); 332 } 333 334 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) { 335 flags = tm_iocb->u.tmf.flags; 336 lun = (uint16_t)tm_iocb->u.tmf.lun; 337 338 /* Issue Marker IOCB */ 339 qla2x00_marker(vha, vha->hw->req_q_map[0], 340 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun, 341 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID); 342 } 343 344 done_free_sp: 345 sp->free(vha, sp); 346 done: 347 return rval; 348 } 349 350 static void 351 qla24xx_abort_iocb_timeout(void *data) 352 { 353 srb_t *sp = (srb_t *)data; 354 struct srb_iocb *abt = &sp->u.iocb_cmd; 355 356 abt->u.abt.comp_status = CS_TIMEOUT; 357 complete(&abt->u.abt.comp); 358 } 359 360 static void 361 qla24xx_abort_sp_done(void *data, void *ptr, int res) 362 { 363 srb_t *sp = (srb_t *)ptr; 364 struct srb_iocb *abt = &sp->u.iocb_cmd; 365 366 complete(&abt->u.abt.comp); 367 } 368 369 static int 370 qla24xx_async_abort_cmd(srb_t *cmd_sp) 371 { 372 scsi_qla_host_t *vha = cmd_sp->fcport->vha; 373 fc_port_t *fcport = cmd_sp->fcport; 374 struct srb_iocb *abt_iocb; 375 srb_t *sp; 376 int rval = QLA_FUNCTION_FAILED; 377 378 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 379 if (!sp) 380 goto done; 381 382 abt_iocb = &sp->u.iocb_cmd; 383 sp->type = SRB_ABT_CMD; 384 sp->name = "abort"; 385 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)); 386 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle; 387 sp->done = qla24xx_abort_sp_done; 388 abt_iocb->timeout = qla24xx_abort_iocb_timeout; 389 init_completion(&abt_iocb->u.abt.comp); 390 391 rval = qla2x00_start_sp(sp); 392 if (rval != QLA_SUCCESS) 393 goto done_free_sp; 394 395 ql_dbg(ql_dbg_async, vha, 0x507c, 396 "Abort command issued - hdl=%x, target_id=%x\n", 397 cmd_sp->handle, fcport->tgt_id); 398 399 wait_for_completion(&abt_iocb->u.abt.comp); 400 401 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ? 402 QLA_SUCCESS : QLA_FUNCTION_FAILED; 403 404 done_free_sp: 405 sp->free(vha, sp); 406 done: 407 return rval; 408 } 409 410 int 411 qla24xx_async_abort_command(srb_t *sp) 412 { 413 unsigned long flags = 0; 414 415 uint32_t handle; 416 fc_port_t *fcport = sp->fcport; 417 struct scsi_qla_host *vha = fcport->vha; 418 struct qla_hw_data *ha = vha->hw; 419 struct req_que *req = vha->req; 420 421 spin_lock_irqsave(&ha->hardware_lock, flags); 422 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 423 if (req->outstanding_cmds[handle] == sp) 424 break; 425 } 426 spin_unlock_irqrestore(&ha->hardware_lock, flags); 427 if (handle == req->num_outstanding_cmds) { 428 /* Command not found. */ 429 return QLA_FUNCTION_FAILED; 430 } 431 if (sp->type == SRB_FXIOCB_DCMD) 432 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport, 433 FXDISC_ABORT_IOCTL); 434 435 return qla24xx_async_abort_cmd(sp); 436 } 437 438 void 439 qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport, 440 uint16_t *data) 441 { 442 int rval; 443 444 switch (data[0]) { 445 case MBS_COMMAND_COMPLETE: 446 /* 447 * Driver must validate login state - If PRLI not complete, 448 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI 449 * requests. 450 */ 451 rval = qla2x00_get_port_database(vha, fcport, 0); 452 if (rval == QLA_NOT_LOGGED_IN) { 453 fcport->flags &= ~FCF_ASYNC_SENT; 454 fcport->flags |= FCF_LOGIN_NEEDED; 455 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 456 break; 457 } 458 459 if (rval != QLA_SUCCESS) { 460 qla2x00_post_async_logout_work(vha, fcport, NULL); 461 qla2x00_post_async_login_work(vha, fcport, NULL); 462 break; 463 } 464 if (fcport->flags & FCF_FCP2_DEVICE) { 465 qla2x00_post_async_adisc_work(vha, fcport, data); 466 break; 467 } 468 qla2x00_update_fcport(vha, fcport); 469 break; 470 case MBS_COMMAND_ERROR: 471 fcport->flags &= ~FCF_ASYNC_SENT; 472 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 473 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 474 else 475 qla2x00_mark_device_lost(vha, fcport, 1, 0); 476 break; 477 case MBS_PORT_ID_USED: 478 fcport->loop_id = data[1]; 479 qla2x00_post_async_logout_work(vha, fcport, NULL); 480 qla2x00_post_async_login_work(vha, fcport, NULL); 481 break; 482 case MBS_LOOP_ID_USED: 483 fcport->loop_id++; 484 rval = qla2x00_find_new_loop_id(vha, fcport); 485 if (rval != QLA_SUCCESS) { 486 fcport->flags &= ~FCF_ASYNC_SENT; 487 qla2x00_mark_device_lost(vha, fcport, 1, 0); 488 break; 489 } 490 qla2x00_post_async_login_work(vha, fcport, NULL); 491 break; 492 } 493 return; 494 } 495 496 void 497 qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport, 498 uint16_t *data) 499 { 500 qla2x00_mark_device_lost(vha, fcport, 1, 0); 501 return; 502 } 503 504 void 505 qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport, 506 uint16_t *data) 507 { 508 if (data[0] == MBS_COMMAND_COMPLETE) { 509 qla2x00_update_fcport(vha, fcport); 510 511 return; 512 } 513 514 /* Retry login. */ 515 fcport->flags &= ~FCF_ASYNC_SENT; 516 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 517 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 518 else 519 qla2x00_mark_device_lost(vha, fcport, 1, 0); 520 521 return; 522 } 523 524 /****************************************************************************/ 525 /* QLogic ISP2x00 Hardware Support Functions. */ 526 /****************************************************************************/ 527 528 static int 529 qla83xx_nic_core_fw_load(scsi_qla_host_t *vha) 530 { 531 int rval = QLA_SUCCESS; 532 struct qla_hw_data *ha = vha->hw; 533 uint32_t idc_major_ver, idc_minor_ver; 534 uint16_t config[4]; 535 536 qla83xx_idc_lock(vha, 0); 537 538 /* SV: TODO: Assign initialization timeout from 539 * flash-info / other param 540 */ 541 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT; 542 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT; 543 544 /* Set our fcoe function presence */ 545 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) { 546 ql_dbg(ql_dbg_p3p, vha, 0xb077, 547 "Error while setting DRV-Presence.\n"); 548 rval = QLA_FUNCTION_FAILED; 549 goto exit; 550 } 551 552 /* Decide the reset ownership */ 553 qla83xx_reset_ownership(vha); 554 555 /* 556 * On first protocol driver load: 557 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery 558 * register. 559 * Others: Check compatibility with current IDC Major version. 560 */ 561 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver); 562 if (ha->flags.nic_core_reset_owner) { 563 /* Set IDC Major version */ 564 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION; 565 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver); 566 567 /* Clearing IDC-Lock-Recovery register */ 568 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0); 569 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) { 570 /* 571 * Clear further IDC participation if we are not compatible with 572 * the current IDC Major Version. 573 */ 574 ql_log(ql_log_warn, vha, 0xb07d, 575 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n", 576 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION); 577 __qla83xx_clear_drv_presence(vha); 578 rval = QLA_FUNCTION_FAILED; 579 goto exit; 580 } 581 /* Each function sets its supported Minor version. */ 582 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver); 583 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2)); 584 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver); 585 586 if (ha->flags.nic_core_reset_owner) { 587 memset(config, 0, sizeof(config)); 588 if (!qla81xx_get_port_config(vha, config)) 589 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 590 QLA8XXX_DEV_READY); 591 } 592 593 rval = qla83xx_idc_state_handler(vha); 594 595 exit: 596 qla83xx_idc_unlock(vha, 0); 597 598 return rval; 599 } 600 601 /* 602 * qla2x00_initialize_adapter 603 * Initialize board. 604 * 605 * Input: 606 * ha = adapter block pointer. 607 * 608 * Returns: 609 * 0 = success 610 */ 611 int 612 qla2x00_initialize_adapter(scsi_qla_host_t *vha) 613 { 614 int rval; 615 struct qla_hw_data *ha = vha->hw; 616 struct req_que *req = ha->req_q_map[0]; 617 618 /* Clear adapter flags. */ 619 vha->flags.online = 0; 620 ha->flags.chip_reset_done = 0; 621 vha->flags.reset_active = 0; 622 ha->flags.pci_channel_io_perm_failure = 0; 623 ha->flags.eeh_busy = 0; 624 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64(); 625 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 626 atomic_set(&vha->loop_state, LOOP_DOWN); 627 vha->device_flags = DFLG_NO_CABLE; 628 vha->dpc_flags = 0; 629 vha->flags.management_server_logged_in = 0; 630 vha->marker_needed = 0; 631 ha->isp_abort_cnt = 0; 632 ha->beacon_blink_led = 0; 633 634 set_bit(0, ha->req_qid_map); 635 set_bit(0, ha->rsp_qid_map); 636 637 ql_dbg(ql_dbg_init, vha, 0x0040, 638 "Configuring PCI space...\n"); 639 rval = ha->isp_ops->pci_config(vha); 640 if (rval) { 641 ql_log(ql_log_warn, vha, 0x0044, 642 "Unable to configure PCI space.\n"); 643 return (rval); 644 } 645 646 ha->isp_ops->reset_chip(vha); 647 648 rval = qla2xxx_get_flash_info(vha); 649 if (rval) { 650 ql_log(ql_log_fatal, vha, 0x004f, 651 "Unable to validate FLASH data.\n"); 652 return rval; 653 } 654 655 if (IS_QLA8044(ha)) { 656 qla8044_read_reset_template(vha); 657 658 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0. 659 * If DONRESET_BIT0 is set, drivers should not set dev_state 660 * to NEED_RESET. But if NEED_RESET is set, drivers should 661 * should honor the reset. */ 662 if (ql2xdontresethba == 1) 663 qla8044_set_idc_dontreset(vha); 664 } 665 666 ha->isp_ops->get_flash_version(vha, req->ring); 667 ql_dbg(ql_dbg_init, vha, 0x0061, 668 "Configure NVRAM parameters...\n"); 669 670 ha->isp_ops->nvram_config(vha); 671 672 if (ha->flags.disable_serdes) { 673 /* Mask HBA via NVRAM settings? */ 674 ql_log(ql_log_info, vha, 0x0077, 675 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name); 676 return QLA_FUNCTION_FAILED; 677 } 678 679 ql_dbg(ql_dbg_init, vha, 0x0078, 680 "Verifying loaded RISC code...\n"); 681 682 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) { 683 rval = ha->isp_ops->chip_diag(vha); 684 if (rval) 685 return (rval); 686 rval = qla2x00_setup_chip(vha); 687 if (rval) 688 return (rval); 689 } 690 691 if (IS_QLA84XX(ha)) { 692 ha->cs84xx = qla84xx_get_chip(vha); 693 if (!ha->cs84xx) { 694 ql_log(ql_log_warn, vha, 0x00d0, 695 "Unable to configure ISP84XX.\n"); 696 return QLA_FUNCTION_FAILED; 697 } 698 } 699 700 if (qla_ini_mode_enabled(vha)) 701 rval = qla2x00_init_rings(vha); 702 703 ha->flags.chip_reset_done = 1; 704 705 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) { 706 /* Issue verify 84xx FW IOCB to complete 84xx initialization */ 707 rval = qla84xx_init_chip(vha); 708 if (rval != QLA_SUCCESS) { 709 ql_log(ql_log_warn, vha, 0x00d4, 710 "Unable to initialize ISP84XX.\n"); 711 qla84xx_put_chip(vha); 712 } 713 } 714 715 /* Load the NIC Core f/w if we are the first protocol driver. */ 716 if (IS_QLA8031(ha)) { 717 rval = qla83xx_nic_core_fw_load(vha); 718 if (rval) 719 ql_log(ql_log_warn, vha, 0x0124, 720 "Error in initializing NIC Core f/w.\n"); 721 } 722 723 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)) 724 qla24xx_read_fcp_prio_cfg(vha); 725 726 if (IS_P3P_TYPE(ha)) 727 qla82xx_set_driver_version(vha, QLA2XXX_VERSION); 728 else 729 qla25xx_set_driver_version(vha, QLA2XXX_VERSION); 730 731 return (rval); 732 } 733 734 /** 735 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers. 736 * @ha: HA context 737 * 738 * Returns 0 on success. 739 */ 740 int 741 qla2100_pci_config(scsi_qla_host_t *vha) 742 { 743 uint16_t w; 744 unsigned long flags; 745 struct qla_hw_data *ha = vha->hw; 746 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 747 748 pci_set_master(ha->pdev); 749 pci_try_set_mwi(ha->pdev); 750 751 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 752 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 753 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 754 755 pci_disable_rom(ha->pdev); 756 757 /* Get PCI bus information. */ 758 spin_lock_irqsave(&ha->hardware_lock, flags); 759 ha->pci_attr = RD_REG_WORD(®->ctrl_status); 760 spin_unlock_irqrestore(&ha->hardware_lock, flags); 761 762 return QLA_SUCCESS; 763 } 764 765 /** 766 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers. 767 * @ha: HA context 768 * 769 * Returns 0 on success. 770 */ 771 int 772 qla2300_pci_config(scsi_qla_host_t *vha) 773 { 774 uint16_t w; 775 unsigned long flags = 0; 776 uint32_t cnt; 777 struct qla_hw_data *ha = vha->hw; 778 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 779 780 pci_set_master(ha->pdev); 781 pci_try_set_mwi(ha->pdev); 782 783 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 784 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 785 786 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 787 w &= ~PCI_COMMAND_INTX_DISABLE; 788 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 789 790 /* 791 * If this is a 2300 card and not 2312, reset the 792 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately, 793 * the 2310 also reports itself as a 2300 so we need to get the 794 * fb revision level -- a 6 indicates it really is a 2300 and 795 * not a 2310. 796 */ 797 if (IS_QLA2300(ha)) { 798 spin_lock_irqsave(&ha->hardware_lock, flags); 799 800 /* Pause RISC. */ 801 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 802 for (cnt = 0; cnt < 30000; cnt++) { 803 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) 804 break; 805 806 udelay(10); 807 } 808 809 /* Select FPM registers. */ 810 WRT_REG_WORD(®->ctrl_status, 0x20); 811 RD_REG_WORD(®->ctrl_status); 812 813 /* Get the fb rev level */ 814 ha->fb_rev = RD_FB_CMD_REG(ha, reg); 815 816 if (ha->fb_rev == FPM_2300) 817 pci_clear_mwi(ha->pdev); 818 819 /* Deselect FPM registers. */ 820 WRT_REG_WORD(®->ctrl_status, 0x0); 821 RD_REG_WORD(®->ctrl_status); 822 823 /* Release RISC module. */ 824 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 825 for (cnt = 0; cnt < 30000; cnt++) { 826 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0) 827 break; 828 829 udelay(10); 830 } 831 832 spin_unlock_irqrestore(&ha->hardware_lock, flags); 833 } 834 835 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 836 837 pci_disable_rom(ha->pdev); 838 839 /* Get PCI bus information. */ 840 spin_lock_irqsave(&ha->hardware_lock, flags); 841 ha->pci_attr = RD_REG_WORD(®->ctrl_status); 842 spin_unlock_irqrestore(&ha->hardware_lock, flags); 843 844 return QLA_SUCCESS; 845 } 846 847 /** 848 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers. 849 * @ha: HA context 850 * 851 * Returns 0 on success. 852 */ 853 int 854 qla24xx_pci_config(scsi_qla_host_t *vha) 855 { 856 uint16_t w; 857 unsigned long flags = 0; 858 struct qla_hw_data *ha = vha->hw; 859 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 860 861 pci_set_master(ha->pdev); 862 pci_try_set_mwi(ha->pdev); 863 864 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 865 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 866 w &= ~PCI_COMMAND_INTX_DISABLE; 867 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 868 869 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 870 871 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ 872 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) 873 pcix_set_mmrbc(ha->pdev, 2048); 874 875 /* PCIe -- adjust Maximum Read Request Size (2048). */ 876 if (pci_is_pcie(ha->pdev)) 877 pcie_set_readrq(ha->pdev, 4096); 878 879 pci_disable_rom(ha->pdev); 880 881 ha->chip_revision = ha->pdev->revision; 882 883 /* Get PCI bus information. */ 884 spin_lock_irqsave(&ha->hardware_lock, flags); 885 ha->pci_attr = RD_REG_DWORD(®->ctrl_status); 886 spin_unlock_irqrestore(&ha->hardware_lock, flags); 887 888 return QLA_SUCCESS; 889 } 890 891 /** 892 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. 893 * @ha: HA context 894 * 895 * Returns 0 on success. 896 */ 897 int 898 qla25xx_pci_config(scsi_qla_host_t *vha) 899 { 900 uint16_t w; 901 struct qla_hw_data *ha = vha->hw; 902 903 pci_set_master(ha->pdev); 904 pci_try_set_mwi(ha->pdev); 905 906 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 907 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 908 w &= ~PCI_COMMAND_INTX_DISABLE; 909 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 910 911 /* PCIe -- adjust Maximum Read Request Size (2048). */ 912 if (pci_is_pcie(ha->pdev)) 913 pcie_set_readrq(ha->pdev, 4096); 914 915 pci_disable_rom(ha->pdev); 916 917 ha->chip_revision = ha->pdev->revision; 918 919 return QLA_SUCCESS; 920 } 921 922 /** 923 * qla2x00_isp_firmware() - Choose firmware image. 924 * @ha: HA context 925 * 926 * Returns 0 on success. 927 */ 928 static int 929 qla2x00_isp_firmware(scsi_qla_host_t *vha) 930 { 931 int rval; 932 uint16_t loop_id, topo, sw_cap; 933 uint8_t domain, area, al_pa; 934 struct qla_hw_data *ha = vha->hw; 935 936 /* Assume loading risc code */ 937 rval = QLA_FUNCTION_FAILED; 938 939 if (ha->flags.disable_risc_code_load) { 940 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n"); 941 942 /* Verify checksum of loaded RISC code. */ 943 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address); 944 if (rval == QLA_SUCCESS) { 945 /* And, verify we are not in ROM code. */ 946 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa, 947 &area, &domain, &topo, &sw_cap); 948 } 949 } 950 951 if (rval) 952 ql_dbg(ql_dbg_init, vha, 0x007a, 953 "**** Load RISC code ****.\n"); 954 955 return (rval); 956 } 957 958 /** 959 * qla2x00_reset_chip() - Reset ISP chip. 960 * @ha: HA context 961 * 962 * Returns 0 on success. 963 */ 964 void 965 qla2x00_reset_chip(scsi_qla_host_t *vha) 966 { 967 unsigned long flags = 0; 968 struct qla_hw_data *ha = vha->hw; 969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 970 uint32_t cnt; 971 uint16_t cmd; 972 973 if (unlikely(pci_channel_offline(ha->pdev))) 974 return; 975 976 ha->isp_ops->disable_intrs(ha); 977 978 spin_lock_irqsave(&ha->hardware_lock, flags); 979 980 /* Turn off master enable */ 981 cmd = 0; 982 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd); 983 cmd &= ~PCI_COMMAND_MASTER; 984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 985 986 if (!IS_QLA2100(ha)) { 987 /* Pause RISC. */ 988 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 989 if (IS_QLA2200(ha) || IS_QLA2300(ha)) { 990 for (cnt = 0; cnt < 30000; cnt++) { 991 if ((RD_REG_WORD(®->hccr) & 992 HCCR_RISC_PAUSE) != 0) 993 break; 994 udelay(100); 995 } 996 } else { 997 RD_REG_WORD(®->hccr); /* PCI Posting. */ 998 udelay(10); 999 } 1000 1001 /* Select FPM registers. */ 1002 WRT_REG_WORD(®->ctrl_status, 0x20); 1003 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1004 1005 /* FPM Soft Reset. */ 1006 WRT_REG_WORD(®->fpm_diag_config, 0x100); 1007 RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ 1008 1009 /* Toggle Fpm Reset. */ 1010 if (!IS_QLA2200(ha)) { 1011 WRT_REG_WORD(®->fpm_diag_config, 0x0); 1012 RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ 1013 } 1014 1015 /* Select frame buffer registers. */ 1016 WRT_REG_WORD(®->ctrl_status, 0x10); 1017 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1018 1019 /* Reset frame buffer FIFOs. */ 1020 if (IS_QLA2200(ha)) { 1021 WRT_FB_CMD_REG(ha, reg, 0xa000); 1022 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ 1023 } else { 1024 WRT_FB_CMD_REG(ha, reg, 0x00fc); 1025 1026 /* Read back fb_cmd until zero or 3 seconds max */ 1027 for (cnt = 0; cnt < 3000; cnt++) { 1028 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) 1029 break; 1030 udelay(100); 1031 } 1032 } 1033 1034 /* Select RISC module registers. */ 1035 WRT_REG_WORD(®->ctrl_status, 0); 1036 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1037 1038 /* Reset RISC processor. */ 1039 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 1040 RD_REG_WORD(®->hccr); /* PCI Posting. */ 1041 1042 /* Release RISC processor. */ 1043 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 1044 RD_REG_WORD(®->hccr); /* PCI Posting. */ 1045 } 1046 1047 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 1048 WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT); 1049 1050 /* Reset ISP chip. */ 1051 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 1052 1053 /* Wait for RISC to recover from reset. */ 1054 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 1055 /* 1056 * It is necessary to for a delay here since the card doesn't 1057 * respond to PCI reads during a reset. On some architectures 1058 * this will result in an MCA. 1059 */ 1060 udelay(20); 1061 for (cnt = 30000; cnt; cnt--) { 1062 if ((RD_REG_WORD(®->ctrl_status) & 1063 CSR_ISP_SOFT_RESET) == 0) 1064 break; 1065 udelay(100); 1066 } 1067 } else 1068 udelay(10); 1069 1070 /* Reset RISC processor. */ 1071 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 1072 1073 WRT_REG_WORD(®->semaphore, 0); 1074 1075 /* Release RISC processor. */ 1076 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 1077 RD_REG_WORD(®->hccr); /* PCI Posting. */ 1078 1079 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 1080 for (cnt = 0; cnt < 30000; cnt++) { 1081 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) 1082 break; 1083 1084 udelay(100); 1085 } 1086 } else 1087 udelay(100); 1088 1089 /* Turn on master enable */ 1090 cmd |= PCI_COMMAND_MASTER; 1091 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 1092 1093 /* Disable RISC pause on FPM parity error. */ 1094 if (!IS_QLA2100(ha)) { 1095 WRT_REG_WORD(®->hccr, HCCR_DISABLE_PARITY_PAUSE); 1096 RD_REG_WORD(®->hccr); /* PCI Posting. */ 1097 } 1098 1099 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1100 } 1101 1102 /** 1103 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC. 1104 * 1105 * Returns 0 on success. 1106 */ 1107 static int 1108 qla81xx_reset_mpi(scsi_qla_host_t *vha) 1109 { 1110 uint16_t mb[4] = {0x1010, 0, 1, 0}; 1111 1112 if (!IS_QLA81XX(vha->hw)) 1113 return QLA_SUCCESS; 1114 1115 return qla81xx_write_mpi_register(vha, mb); 1116 } 1117 1118 /** 1119 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. 1120 * @ha: HA context 1121 * 1122 * Returns 0 on success. 1123 */ 1124 static inline void 1125 qla24xx_reset_risc(scsi_qla_host_t *vha) 1126 { 1127 unsigned long flags = 0; 1128 struct qla_hw_data *ha = vha->hw; 1129 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1130 uint32_t cnt, d2; 1131 uint16_t wd; 1132 static int abts_cnt; /* ISP abort retry counts */ 1133 1134 spin_lock_irqsave(&ha->hardware_lock, flags); 1135 1136 /* Reset RISC. */ 1137 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 1138 for (cnt = 0; cnt < 30000; cnt++) { 1139 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 1140 break; 1141 1142 udelay(10); 1143 } 1144 1145 WRT_REG_DWORD(®->ctrl_status, 1146 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 1147 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 1148 1149 udelay(100); 1150 /* Wait for firmware to complete NVRAM accesses. */ 1151 d2 = (uint32_t) RD_REG_WORD(®->mailbox0); 1152 for (cnt = 10000 ; cnt && d2; cnt--) { 1153 udelay(5); 1154 d2 = (uint32_t) RD_REG_WORD(®->mailbox0); 1155 barrier(); 1156 } 1157 1158 /* Wait for soft-reset to complete. */ 1159 d2 = RD_REG_DWORD(®->ctrl_status); 1160 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) { 1161 udelay(5); 1162 d2 = RD_REG_DWORD(®->ctrl_status); 1163 barrier(); 1164 } 1165 1166 /* If required, do an MPI FW reset now */ 1167 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) { 1168 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) { 1169 if (++abts_cnt < 5) { 1170 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 1171 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags); 1172 } else { 1173 /* 1174 * We exhausted the ISP abort retries. We have to 1175 * set the board offline. 1176 */ 1177 abts_cnt = 0; 1178 vha->flags.online = 0; 1179 } 1180 } 1181 } 1182 1183 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); 1184 RD_REG_DWORD(®->hccr); 1185 1186 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); 1187 RD_REG_DWORD(®->hccr); 1188 1189 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 1190 RD_REG_DWORD(®->hccr); 1191 1192 d2 = (uint32_t) RD_REG_WORD(®->mailbox0); 1193 for (cnt = 6000000 ; cnt && d2; cnt--) { 1194 udelay(5); 1195 d2 = (uint32_t) RD_REG_WORD(®->mailbox0); 1196 barrier(); 1197 } 1198 1199 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1200 1201 if (IS_NOPOLLING_TYPE(ha)) 1202 ha->isp_ops->enable_intrs(ha); 1203 } 1204 1205 static void 1206 qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) 1207 { 1208 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 1209 1210 WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 1211 *data = RD_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET); 1212 1213 } 1214 1215 static void 1216 qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) 1217 { 1218 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 1219 1220 WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 1221 WRT_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET, data); 1222 } 1223 1224 static void 1225 qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) 1226 { 1227 struct qla_hw_data *ha = vha->hw; 1228 uint32_t wd32 = 0; 1229 uint delta_msec = 100; 1230 uint elapsed_msec = 0; 1231 uint timeout_msec; 1232 ulong n; 1233 1234 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha)) 1235 return; 1236 1237 attempt: 1238 timeout_msec = TIMEOUT_SEMAPHORE; 1239 n = timeout_msec / delta_msec; 1240 while (n--) { 1241 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET); 1242 qla25xx_read_risc_sema_reg(vha, &wd32); 1243 if (wd32 & RISC_SEMAPHORE) 1244 break; 1245 msleep(delta_msec); 1246 elapsed_msec += delta_msec; 1247 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 1248 goto force; 1249 } 1250 1251 if (!(wd32 & RISC_SEMAPHORE)) 1252 goto force; 1253 1254 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 1255 goto acquired; 1256 1257 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR); 1258 timeout_msec = TIMEOUT_SEMAPHORE_FORCE; 1259 n = timeout_msec / delta_msec; 1260 while (n--) { 1261 qla25xx_read_risc_sema_reg(vha, &wd32); 1262 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 1263 break; 1264 msleep(delta_msec); 1265 elapsed_msec += delta_msec; 1266 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 1267 goto force; 1268 } 1269 1270 if (wd32 & RISC_SEMAPHORE_FORCE) 1271 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR); 1272 1273 goto attempt; 1274 1275 force: 1276 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET); 1277 1278 acquired: 1279 return; 1280 } 1281 1282 /** 1283 * qla24xx_reset_chip() - Reset ISP24xx chip. 1284 * @ha: HA context 1285 * 1286 * Returns 0 on success. 1287 */ 1288 void 1289 qla24xx_reset_chip(scsi_qla_host_t *vha) 1290 { 1291 struct qla_hw_data *ha = vha->hw; 1292 1293 if (pci_channel_offline(ha->pdev) && 1294 ha->flags.pci_channel_io_perm_failure) { 1295 return; 1296 } 1297 1298 ha->isp_ops->disable_intrs(ha); 1299 1300 qla25xx_manipulate_risc_semaphore(vha); 1301 1302 /* Perform RISC reset. */ 1303 qla24xx_reset_risc(vha); 1304 } 1305 1306 /** 1307 * qla2x00_chip_diag() - Test chip for proper operation. 1308 * @ha: HA context 1309 * 1310 * Returns 0 on success. 1311 */ 1312 int 1313 qla2x00_chip_diag(scsi_qla_host_t *vha) 1314 { 1315 int rval; 1316 struct qla_hw_data *ha = vha->hw; 1317 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1318 unsigned long flags = 0; 1319 uint16_t data; 1320 uint32_t cnt; 1321 uint16_t mb[5]; 1322 struct req_que *req = ha->req_q_map[0]; 1323 1324 /* Assume a failed state */ 1325 rval = QLA_FUNCTION_FAILED; 1326 1327 ql_dbg(ql_dbg_init, vha, 0x007b, 1328 "Testing device at %lx.\n", (u_long)®->flash_address); 1329 1330 spin_lock_irqsave(&ha->hardware_lock, flags); 1331 1332 /* Reset ISP chip. */ 1333 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 1334 1335 /* 1336 * We need to have a delay here since the card will not respond while 1337 * in reset causing an MCA on some architectures. 1338 */ 1339 udelay(20); 1340 data = qla2x00_debounce_register(®->ctrl_status); 1341 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) { 1342 udelay(5); 1343 data = RD_REG_WORD(®->ctrl_status); 1344 barrier(); 1345 } 1346 1347 if (!cnt) 1348 goto chip_diag_failed; 1349 1350 ql_dbg(ql_dbg_init, vha, 0x007c, 1351 "Reset register cleared by chip reset.\n"); 1352 1353 /* Reset RISC processor. */ 1354 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 1355 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 1356 1357 /* Workaround for QLA2312 PCI parity error */ 1358 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 1359 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); 1360 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) { 1361 udelay(5); 1362 data = RD_MAILBOX_REG(ha, reg, 0); 1363 barrier(); 1364 } 1365 } else 1366 udelay(10); 1367 1368 if (!cnt) 1369 goto chip_diag_failed; 1370 1371 /* Check product ID of chip */ 1372 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n"); 1373 1374 mb[1] = RD_MAILBOX_REG(ha, reg, 1); 1375 mb[2] = RD_MAILBOX_REG(ha, reg, 2); 1376 mb[3] = RD_MAILBOX_REG(ha, reg, 3); 1377 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); 1378 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) || 1379 mb[3] != PROD_ID_3) { 1380 ql_log(ql_log_warn, vha, 0x0062, 1381 "Wrong product ID = 0x%x,0x%x,0x%x.\n", 1382 mb[1], mb[2], mb[3]); 1383 1384 goto chip_diag_failed; 1385 } 1386 ha->product_id[0] = mb[1]; 1387 ha->product_id[1] = mb[2]; 1388 ha->product_id[2] = mb[3]; 1389 ha->product_id[3] = mb[4]; 1390 1391 /* Adjust fw RISC transfer size */ 1392 if (req->length > 1024) 1393 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; 1394 else 1395 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1396 req->length; 1397 1398 if (IS_QLA2200(ha) && 1399 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { 1400 /* Limit firmware transfer size with a 2200A */ 1401 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n"); 1402 1403 ha->device_type |= DT_ISP2200A; 1404 ha->fw_transfer_size = 128; 1405 } 1406 1407 /* Wrap Incoming Mailboxes Test. */ 1408 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1409 1410 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n"); 1411 rval = qla2x00_mbx_reg_test(vha); 1412 if (rval) 1413 ql_log(ql_log_warn, vha, 0x0080, 1414 "Failed mailbox send register test.\n"); 1415 else 1416 /* Flag a successful rval */ 1417 rval = QLA_SUCCESS; 1418 spin_lock_irqsave(&ha->hardware_lock, flags); 1419 1420 chip_diag_failed: 1421 if (rval) 1422 ql_log(ql_log_info, vha, 0x0081, 1423 "Chip diagnostics **** FAILED ****.\n"); 1424 1425 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1426 1427 return (rval); 1428 } 1429 1430 /** 1431 * qla24xx_chip_diag() - Test ISP24xx for proper operation. 1432 * @ha: HA context 1433 * 1434 * Returns 0 on success. 1435 */ 1436 int 1437 qla24xx_chip_diag(scsi_qla_host_t *vha) 1438 { 1439 int rval; 1440 struct qla_hw_data *ha = vha->hw; 1441 struct req_que *req = ha->req_q_map[0]; 1442 1443 if (IS_P3P_TYPE(ha)) 1444 return QLA_SUCCESS; 1445 1446 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; 1447 1448 rval = qla2x00_mbx_reg_test(vha); 1449 if (rval) { 1450 ql_log(ql_log_warn, vha, 0x0082, 1451 "Failed mailbox send register test.\n"); 1452 } else { 1453 /* Flag a successful rval */ 1454 rval = QLA_SUCCESS; 1455 } 1456 1457 return rval; 1458 } 1459 1460 void 1461 qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) 1462 { 1463 int rval; 1464 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, 1465 eft_size, fce_size, mq_size; 1466 dma_addr_t tc_dma; 1467 void *tc; 1468 struct qla_hw_data *ha = vha->hw; 1469 struct req_que *req = ha->req_q_map[0]; 1470 struct rsp_que *rsp = ha->rsp_q_map[0]; 1471 1472 if (ha->fw_dump) { 1473 ql_dbg(ql_dbg_init, vha, 0x00bd, 1474 "Firmware dump already allocated.\n"); 1475 return; 1476 } 1477 1478 ha->fw_dumped = 0; 1479 ha->fw_dump_cap_flags = 0; 1480 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; 1481 req_q_size = rsp_q_size = 0; 1482 1483 if (IS_QLA27XX(ha)) 1484 goto try_fce; 1485 1486 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 1487 fixed_size = sizeof(struct qla2100_fw_dump); 1488 } else if (IS_QLA23XX(ha)) { 1489 fixed_size = offsetof(struct qla2300_fw_dump, data_ram); 1490 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 1491 sizeof(uint16_t); 1492 } else if (IS_FWI2_CAPABLE(ha)) { 1493 if (IS_QLA83XX(ha)) 1494 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem); 1495 else if (IS_QLA81XX(ha)) 1496 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); 1497 else if (IS_QLA25XX(ha)) 1498 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); 1499 else 1500 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); 1501 1502 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 1503 sizeof(uint32_t); 1504 if (ha->mqenable) { 1505 if (!IS_QLA83XX(ha)) 1506 mq_size = sizeof(struct qla2xxx_mq_chain); 1507 /* 1508 * Allocate maximum buffer size for all queues. 1509 * Resizing must be done at end-of-dump processing. 1510 */ 1511 mq_size += ha->max_req_queues * 1512 (req->length * sizeof(request_t)); 1513 mq_size += ha->max_rsp_queues * 1514 (rsp->length * sizeof(response_t)); 1515 } 1516 if (ha->tgt.atio_ring) 1517 mq_size += ha->tgt.atio_q_length * sizeof(request_t); 1518 /* Allocate memory for Fibre Channel Event Buffer. */ 1519 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 1520 !IS_QLA27XX(ha)) 1521 goto try_eft; 1522 1523 try_fce: 1524 if (ha->fce) 1525 dma_free_coherent(&ha->pdev->dev, 1526 FCE_SIZE, ha->fce, ha->fce_dma); 1527 1528 /* Allocate memory for Fibre Channel Event Buffer. */ 1529 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, 1530 GFP_KERNEL); 1531 if (!tc) { 1532 ql_log(ql_log_warn, vha, 0x00be, 1533 "Unable to allocate (%d KB) for FCE.\n", 1534 FCE_SIZE / 1024); 1535 goto try_eft; 1536 } 1537 1538 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS, 1539 ha->fce_mb, &ha->fce_bufs); 1540 if (rval) { 1541 ql_log(ql_log_warn, vha, 0x00bf, 1542 "Unable to initialize FCE (%d).\n", rval); 1543 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc, 1544 tc_dma); 1545 ha->flags.fce_enabled = 0; 1546 goto try_eft; 1547 } 1548 ql_dbg(ql_dbg_init, vha, 0x00c0, 1549 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024); 1550 1551 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE; 1552 ha->flags.fce_enabled = 1; 1553 ha->fce_dma = tc_dma; 1554 ha->fce = tc; 1555 1556 try_eft: 1557 if (ha->eft) 1558 dma_free_coherent(&ha->pdev->dev, 1559 EFT_SIZE, ha->eft, ha->eft_dma); 1560 1561 /* Allocate memory for Extended Trace Buffer. */ 1562 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma, 1563 GFP_KERNEL); 1564 if (!tc) { 1565 ql_log(ql_log_warn, vha, 0x00c1, 1566 "Unable to allocate (%d KB) for EFT.\n", 1567 EFT_SIZE / 1024); 1568 goto cont_alloc; 1569 } 1570 1571 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS); 1572 if (rval) { 1573 ql_log(ql_log_warn, vha, 0x00c2, 1574 "Unable to initialize EFT (%d).\n", rval); 1575 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc, 1576 tc_dma); 1577 goto cont_alloc; 1578 } 1579 ql_dbg(ql_dbg_init, vha, 0x00c3, 1580 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024); 1581 1582 eft_size = EFT_SIZE; 1583 ha->eft_dma = tc_dma; 1584 ha->eft = tc; 1585 } 1586 1587 cont_alloc: 1588 if (IS_QLA27XX(ha)) { 1589 if (!ha->fw_dump_template) { 1590 ql_log(ql_log_warn, vha, 0x00ba, 1591 "Failed missing fwdump template\n"); 1592 return; 1593 } 1594 dump_size = qla27xx_fwdt_calculate_dump_size(vha); 1595 ql_dbg(ql_dbg_init, vha, 0x00fa, 1596 "-> allocating fwdump (%x bytes)...\n", dump_size); 1597 goto allocate; 1598 } 1599 1600 req_q_size = req->length * sizeof(request_t); 1601 rsp_q_size = rsp->length * sizeof(response_t); 1602 dump_size = offsetof(struct qla2xxx_fw_dump, isp); 1603 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size; 1604 ha->chain_offset = dump_size; 1605 dump_size += mq_size + fce_size; 1606 1607 allocate: 1608 ha->fw_dump = vmalloc(dump_size); 1609 if (!ha->fw_dump) { 1610 ql_log(ql_log_warn, vha, 0x00c4, 1611 "Unable to allocate (%d KB) for firmware dump.\n", 1612 dump_size / 1024); 1613 1614 if (ha->fce) { 1615 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, 1616 ha->fce_dma); 1617 ha->fce = NULL; 1618 ha->fce_dma = 0; 1619 } 1620 1621 if (ha->eft) { 1622 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft, 1623 ha->eft_dma); 1624 ha->eft = NULL; 1625 ha->eft_dma = 0; 1626 } 1627 return; 1628 } 1629 ha->fw_dump_len = dump_size; 1630 ql_dbg(ql_dbg_init, vha, 0x00c5, 1631 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024); 1632 1633 if (IS_QLA27XX(ha)) 1634 return; 1635 1636 ha->fw_dump->signature[0] = 'Q'; 1637 ha->fw_dump->signature[1] = 'L'; 1638 ha->fw_dump->signature[2] = 'G'; 1639 ha->fw_dump->signature[3] = 'C'; 1640 ha->fw_dump->version = __constant_htonl(1); 1641 1642 ha->fw_dump->fixed_size = htonl(fixed_size); 1643 ha->fw_dump->mem_size = htonl(mem_size); 1644 ha->fw_dump->req_q_size = htonl(req_q_size); 1645 ha->fw_dump->rsp_q_size = htonl(rsp_q_size); 1646 1647 ha->fw_dump->eft_size = htonl(eft_size); 1648 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma)); 1649 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma)); 1650 1651 ha->fw_dump->header_size = 1652 htonl(offsetof(struct qla2xxx_fw_dump, isp)); 1653 } 1654 1655 static int 1656 qla81xx_mpi_sync(scsi_qla_host_t *vha) 1657 { 1658 #define MPS_MASK 0xe0 1659 int rval; 1660 uint16_t dc; 1661 uint32_t dw; 1662 1663 if (!IS_QLA81XX(vha->hw)) 1664 return QLA_SUCCESS; 1665 1666 rval = qla2x00_write_ram_word(vha, 0x7c00, 1); 1667 if (rval != QLA_SUCCESS) { 1668 ql_log(ql_log_warn, vha, 0x0105, 1669 "Unable to acquire semaphore.\n"); 1670 goto done; 1671 } 1672 1673 pci_read_config_word(vha->hw->pdev, 0x54, &dc); 1674 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw); 1675 if (rval != QLA_SUCCESS) { 1676 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n"); 1677 goto done_release; 1678 } 1679 1680 dc &= MPS_MASK; 1681 if (dc == (dw & MPS_MASK)) 1682 goto done_release; 1683 1684 dw &= ~MPS_MASK; 1685 dw |= dc; 1686 rval = qla2x00_write_ram_word(vha, 0x7a15, dw); 1687 if (rval != QLA_SUCCESS) { 1688 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n"); 1689 } 1690 1691 done_release: 1692 rval = qla2x00_write_ram_word(vha, 0x7c00, 0); 1693 if (rval != QLA_SUCCESS) { 1694 ql_log(ql_log_warn, vha, 0x006d, 1695 "Unable to release semaphore.\n"); 1696 } 1697 1698 done: 1699 return rval; 1700 } 1701 1702 int 1703 qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req) 1704 { 1705 /* Don't try to reallocate the array */ 1706 if (req->outstanding_cmds) 1707 return QLA_SUCCESS; 1708 1709 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase && 1710 (ql2xmultique_tag || ql2xmaxqueues > 1))) 1711 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS; 1712 else { 1713 if (ha->fw_xcb_count <= ha->fw_iocb_count) 1714 req->num_outstanding_cmds = ha->fw_xcb_count; 1715 else 1716 req->num_outstanding_cmds = ha->fw_iocb_count; 1717 } 1718 1719 req->outstanding_cmds = kzalloc(sizeof(srb_t *) * 1720 req->num_outstanding_cmds, GFP_KERNEL); 1721 1722 if (!req->outstanding_cmds) { 1723 /* 1724 * Try to allocate a minimal size just so we can get through 1725 * initialization. 1726 */ 1727 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS; 1728 req->outstanding_cmds = kzalloc(sizeof(srb_t *) * 1729 req->num_outstanding_cmds, GFP_KERNEL); 1730 1731 if (!req->outstanding_cmds) { 1732 ql_log(ql_log_fatal, NULL, 0x0126, 1733 "Failed to allocate memory for " 1734 "outstanding_cmds for req_que %p.\n", req); 1735 req->num_outstanding_cmds = 0; 1736 return QLA_FUNCTION_FAILED; 1737 } 1738 } 1739 1740 return QLA_SUCCESS; 1741 } 1742 1743 /** 1744 * qla2x00_setup_chip() - Load and start RISC firmware. 1745 * @ha: HA context 1746 * 1747 * Returns 0 on success. 1748 */ 1749 static int 1750 qla2x00_setup_chip(scsi_qla_host_t *vha) 1751 { 1752 int rval; 1753 uint32_t srisc_address = 0; 1754 struct qla_hw_data *ha = vha->hw; 1755 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1756 unsigned long flags; 1757 uint16_t fw_major_version; 1758 1759 if (IS_P3P_TYPE(ha)) { 1760 rval = ha->isp_ops->load_risc(vha, &srisc_address); 1761 if (rval == QLA_SUCCESS) { 1762 qla2x00_stop_firmware(vha); 1763 goto enable_82xx_npiv; 1764 } else 1765 goto failed; 1766 } 1767 1768 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 1769 /* Disable SRAM, Instruction RAM and GP RAM parity. */ 1770 spin_lock_irqsave(&ha->hardware_lock, flags); 1771 WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); 1772 RD_REG_WORD(®->hccr); 1773 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1774 } 1775 1776 qla81xx_mpi_sync(vha); 1777 1778 /* Load firmware sequences */ 1779 rval = ha->isp_ops->load_risc(vha, &srisc_address); 1780 if (rval == QLA_SUCCESS) { 1781 ql_dbg(ql_dbg_init, vha, 0x00c9, 1782 "Verifying Checksum of loaded RISC code.\n"); 1783 1784 rval = qla2x00_verify_checksum(vha, srisc_address); 1785 if (rval == QLA_SUCCESS) { 1786 /* Start firmware execution. */ 1787 ql_dbg(ql_dbg_init, vha, 0x00ca, 1788 "Starting firmware.\n"); 1789 1790 rval = qla2x00_execute_fw(vha, srisc_address); 1791 /* Retrieve firmware information. */ 1792 if (rval == QLA_SUCCESS) { 1793 enable_82xx_npiv: 1794 fw_major_version = ha->fw_major_version; 1795 if (IS_P3P_TYPE(ha)) 1796 qla82xx_check_md_needed(vha); 1797 else 1798 rval = qla2x00_get_fw_version(vha); 1799 if (rval != QLA_SUCCESS) 1800 goto failed; 1801 ha->flags.npiv_supported = 0; 1802 if (IS_QLA2XXX_MIDTYPE(ha) && 1803 (ha->fw_attributes & BIT_2)) { 1804 ha->flags.npiv_supported = 1; 1805 if ((!ha->max_npiv_vports) || 1806 ((ha->max_npiv_vports + 1) % 1807 MIN_MULTI_ID_FABRIC)) 1808 ha->max_npiv_vports = 1809 MIN_MULTI_ID_FABRIC - 1; 1810 } 1811 qla2x00_get_resource_cnts(vha, NULL, 1812 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count, 1813 &ha->max_npiv_vports, NULL); 1814 1815 /* 1816 * Allocate the array of outstanding commands 1817 * now that we know the firmware resources. 1818 */ 1819 rval = qla2x00_alloc_outstanding_cmds(ha, 1820 vha->req); 1821 if (rval != QLA_SUCCESS) 1822 goto failed; 1823 1824 if (!fw_major_version && ql2xallocfwdump 1825 && !(IS_P3P_TYPE(ha))) 1826 qla2x00_alloc_fw_dump(vha); 1827 } else { 1828 goto failed; 1829 } 1830 } else { 1831 ql_log(ql_log_fatal, vha, 0x00cd, 1832 "ISP Firmware failed checksum.\n"); 1833 goto failed; 1834 } 1835 } else 1836 goto failed; 1837 1838 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 1839 /* Enable proper parity. */ 1840 spin_lock_irqsave(&ha->hardware_lock, flags); 1841 if (IS_QLA2300(ha)) 1842 /* SRAM parity */ 1843 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1); 1844 else 1845 /* SRAM, Instruction RAM and GP RAM parity */ 1846 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7); 1847 RD_REG_WORD(®->hccr); 1848 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1849 } 1850 1851 if (IS_QLA27XX(ha)) 1852 ha->flags.fac_supported = 1; 1853 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { 1854 uint32_t size; 1855 1856 rval = qla81xx_fac_get_sector_size(vha, &size); 1857 if (rval == QLA_SUCCESS) { 1858 ha->flags.fac_supported = 1; 1859 ha->fdt_block_size = size << 2; 1860 } else { 1861 ql_log(ql_log_warn, vha, 0x00ce, 1862 "Unsupported FAC firmware (%d.%02d.%02d).\n", 1863 ha->fw_major_version, ha->fw_minor_version, 1864 ha->fw_subminor_version); 1865 1866 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 1867 ha->flags.fac_supported = 0; 1868 rval = QLA_SUCCESS; 1869 } 1870 } 1871 } 1872 failed: 1873 if (rval) { 1874 ql_log(ql_log_fatal, vha, 0x00cf, 1875 "Setup chip ****FAILED****.\n"); 1876 } 1877 1878 return (rval); 1879 } 1880 1881 /** 1882 * qla2x00_init_response_q_entries() - Initializes response queue entries. 1883 * @ha: HA context 1884 * 1885 * Beginning of request ring has initialization control block already built 1886 * by nvram config routine. 1887 * 1888 * Returns 0 on success. 1889 */ 1890 void 1891 qla2x00_init_response_q_entries(struct rsp_que *rsp) 1892 { 1893 uint16_t cnt; 1894 response_t *pkt; 1895 1896 rsp->ring_ptr = rsp->ring; 1897 rsp->ring_index = 0; 1898 rsp->status_srb = NULL; 1899 pkt = rsp->ring_ptr; 1900 for (cnt = 0; cnt < rsp->length; cnt++) { 1901 pkt->signature = RESPONSE_PROCESSED; 1902 pkt++; 1903 } 1904 } 1905 1906 /** 1907 * qla2x00_update_fw_options() - Read and process firmware options. 1908 * @ha: HA context 1909 * 1910 * Returns 0 on success. 1911 */ 1912 void 1913 qla2x00_update_fw_options(scsi_qla_host_t *vha) 1914 { 1915 uint16_t swing, emphasis, tx_sens, rx_sens; 1916 struct qla_hw_data *ha = vha->hw; 1917 1918 memset(ha->fw_options, 0, sizeof(ha->fw_options)); 1919 qla2x00_get_fw_options(vha, ha->fw_options); 1920 1921 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 1922 return; 1923 1924 /* Serial Link options. */ 1925 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115, 1926 "Serial link options.\n"); 1927 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109, 1928 (uint8_t *)&ha->fw_seriallink_options, 1929 sizeof(ha->fw_seriallink_options)); 1930 1931 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1932 if (ha->fw_seriallink_options[3] & BIT_2) { 1933 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING; 1934 1935 /* 1G settings */ 1936 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); 1937 emphasis = (ha->fw_seriallink_options[2] & 1938 (BIT_4 | BIT_3)) >> 3; 1939 tx_sens = ha->fw_seriallink_options[0] & 1940 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 1941 rx_sens = (ha->fw_seriallink_options[0] & 1942 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 1943 ha->fw_options[10] = (emphasis << 14) | (swing << 8); 1944 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 1945 if (rx_sens == 0x0) 1946 rx_sens = 0x3; 1947 ha->fw_options[10] |= (tx_sens << 4) | rx_sens; 1948 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 1949 ha->fw_options[10] |= BIT_5 | 1950 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 1951 (tx_sens & (BIT_1 | BIT_0)); 1952 1953 /* 2G settings */ 1954 swing = (ha->fw_seriallink_options[2] & 1955 (BIT_7 | BIT_6 | BIT_5)) >> 5; 1956 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); 1957 tx_sens = ha->fw_seriallink_options[1] & 1958 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 1959 rx_sens = (ha->fw_seriallink_options[1] & 1960 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 1961 ha->fw_options[11] = (emphasis << 14) | (swing << 8); 1962 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 1963 if (rx_sens == 0x0) 1964 rx_sens = 0x3; 1965 ha->fw_options[11] |= (tx_sens << 4) | rx_sens; 1966 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 1967 ha->fw_options[11] |= BIT_5 | 1968 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 1969 (tx_sens & (BIT_1 | BIT_0)); 1970 } 1971 1972 /* FCP2 options. */ 1973 /* Return command IOCBs without waiting for an ABTS to complete. */ 1974 ha->fw_options[3] |= BIT_13; 1975 1976 /* LED scheme. */ 1977 if (ha->flags.enable_led_scheme) 1978 ha->fw_options[2] |= BIT_12; 1979 1980 /* Detect ISP6312. */ 1981 if (IS_QLA6312(ha)) 1982 ha->fw_options[2] |= BIT_13; 1983 1984 /* Update firmware options. */ 1985 qla2x00_set_fw_options(vha, ha->fw_options); 1986 } 1987 1988 void 1989 qla24xx_update_fw_options(scsi_qla_host_t *vha) 1990 { 1991 int rval; 1992 struct qla_hw_data *ha = vha->hw; 1993 1994 if (IS_P3P_TYPE(ha)) 1995 return; 1996 1997 /* Update Serial Link options. */ 1998 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) 1999 return; 2000 2001 rval = qla2x00_set_serdes_params(vha, 2002 le16_to_cpu(ha->fw_seriallink_options24[1]), 2003 le16_to_cpu(ha->fw_seriallink_options24[2]), 2004 le16_to_cpu(ha->fw_seriallink_options24[3])); 2005 if (rval != QLA_SUCCESS) { 2006 ql_log(ql_log_warn, vha, 0x0104, 2007 "Unable to update Serial Link options (%x).\n", rval); 2008 } 2009 } 2010 2011 void 2012 qla2x00_config_rings(struct scsi_qla_host *vha) 2013 { 2014 struct qla_hw_data *ha = vha->hw; 2015 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2016 struct req_que *req = ha->req_q_map[0]; 2017 struct rsp_que *rsp = ha->rsp_q_map[0]; 2018 2019 /* Setup ring parameters in initialization control block. */ 2020 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0); 2021 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0); 2022 ha->init_cb->request_q_length = cpu_to_le16(req->length); 2023 ha->init_cb->response_q_length = cpu_to_le16(rsp->length); 2024 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 2025 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 2026 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 2027 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 2028 2029 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0); 2030 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0); 2031 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0); 2032 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0); 2033 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ 2034 } 2035 2036 void 2037 qla24xx_config_rings(struct scsi_qla_host *vha) 2038 { 2039 struct qla_hw_data *ha = vha->hw; 2040 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0); 2041 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; 2042 struct qla_msix_entry *msix; 2043 struct init_cb_24xx *icb; 2044 uint16_t rid = 0; 2045 struct req_que *req = ha->req_q_map[0]; 2046 struct rsp_que *rsp = ha->rsp_q_map[0]; 2047 2048 /* Setup ring parameters in initialization control block. */ 2049 icb = (struct init_cb_24xx *)ha->init_cb; 2050 icb->request_q_outpointer = __constant_cpu_to_le16(0); 2051 icb->response_q_inpointer = __constant_cpu_to_le16(0); 2052 icb->request_q_length = cpu_to_le16(req->length); 2053 icb->response_q_length = cpu_to_le16(rsp->length); 2054 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); 2055 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); 2056 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 2057 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 2058 2059 /* Setup ATIO queue dma pointers for target mode */ 2060 icb->atio_q_inpointer = __constant_cpu_to_le16(0); 2061 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length); 2062 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma)); 2063 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma)); 2064 2065 if (IS_SHADOW_REG_CAPABLE(ha)) 2066 icb->firmware_options_2 |= 2067 __constant_cpu_to_le32(BIT_30|BIT_29); 2068 2069 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 2070 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS); 2071 icb->rid = __constant_cpu_to_le16(rid); 2072 if (ha->flags.msix_enabled) { 2073 msix = &ha->msix_entries[1]; 2074 ql_dbg(ql_dbg_init, vha, 0x00fd, 2075 "Registering vector 0x%x for base que.\n", 2076 msix->entry); 2077 icb->msix = cpu_to_le16(msix->entry); 2078 } 2079 /* Use alternate PCI bus number */ 2080 if (MSB(rid)) 2081 icb->firmware_options_2 |= 2082 __constant_cpu_to_le32(BIT_19); 2083 /* Use alternate PCI devfn */ 2084 if (LSB(rid)) 2085 icb->firmware_options_2 |= 2086 __constant_cpu_to_le32(BIT_18); 2087 2088 /* Use Disable MSIX Handshake mode for capable adapters */ 2089 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) && 2090 (ha->flags.msix_enabled)) { 2091 icb->firmware_options_2 &= 2092 __constant_cpu_to_le32(~BIT_22); 2093 ha->flags.disable_msix_handshake = 1; 2094 ql_dbg(ql_dbg_init, vha, 0x00fe, 2095 "MSIX Handshake Disable Mode turned on.\n"); 2096 } else { 2097 icb->firmware_options_2 |= 2098 __constant_cpu_to_le32(BIT_22); 2099 } 2100 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23); 2101 2102 WRT_REG_DWORD(®->isp25mq.req_q_in, 0); 2103 WRT_REG_DWORD(®->isp25mq.req_q_out, 0); 2104 WRT_REG_DWORD(®->isp25mq.rsp_q_in, 0); 2105 WRT_REG_DWORD(®->isp25mq.rsp_q_out, 0); 2106 } else { 2107 WRT_REG_DWORD(®->isp24.req_q_in, 0); 2108 WRT_REG_DWORD(®->isp24.req_q_out, 0); 2109 WRT_REG_DWORD(®->isp24.rsp_q_in, 0); 2110 WRT_REG_DWORD(®->isp24.rsp_q_out, 0); 2111 } 2112 qlt_24xx_config_rings(vha); 2113 2114 /* PCI posting */ 2115 RD_REG_DWORD(&ioreg->hccr); 2116 } 2117 2118 /** 2119 * qla2x00_init_rings() - Initializes firmware. 2120 * @ha: HA context 2121 * 2122 * Beginning of request ring has initialization control block already built 2123 * by nvram config routine. 2124 * 2125 * Returns 0 on success. 2126 */ 2127 int 2128 qla2x00_init_rings(scsi_qla_host_t *vha) 2129 { 2130 int rval; 2131 unsigned long flags = 0; 2132 int cnt, que; 2133 struct qla_hw_data *ha = vha->hw; 2134 struct req_que *req; 2135 struct rsp_que *rsp; 2136 struct mid_init_cb_24xx *mid_init_cb = 2137 (struct mid_init_cb_24xx *) ha->init_cb; 2138 2139 spin_lock_irqsave(&ha->hardware_lock, flags); 2140 2141 /* Clear outstanding commands array. */ 2142 for (que = 0; que < ha->max_req_queues; que++) { 2143 req = ha->req_q_map[que]; 2144 if (!req) 2145 continue; 2146 req->out_ptr = (void *)(req->ring + req->length); 2147 *req->out_ptr = 0; 2148 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) 2149 req->outstanding_cmds[cnt] = NULL; 2150 2151 req->current_outstanding_cmd = 1; 2152 2153 /* Initialize firmware. */ 2154 req->ring_ptr = req->ring; 2155 req->ring_index = 0; 2156 req->cnt = req->length; 2157 } 2158 2159 for (que = 0; que < ha->max_rsp_queues; que++) { 2160 rsp = ha->rsp_q_map[que]; 2161 if (!rsp) 2162 continue; 2163 rsp->in_ptr = (void *)(rsp->ring + rsp->length); 2164 *rsp->in_ptr = 0; 2165 /* Initialize response queue entries */ 2166 if (IS_QLAFX00(ha)) 2167 qlafx00_init_response_q_entries(rsp); 2168 else 2169 qla2x00_init_response_q_entries(rsp); 2170 } 2171 2172 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring; 2173 ha->tgt.atio_ring_index = 0; 2174 /* Initialize ATIO queue entries */ 2175 qlt_init_atio_q_entries(vha); 2176 2177 ha->isp_ops->config_rings(vha); 2178 2179 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2180 2181 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n"); 2182 2183 if (IS_QLAFX00(ha)) { 2184 rval = qlafx00_init_firmware(vha, ha->init_cb_size); 2185 goto next_check; 2186 } 2187 2188 /* Update any ISP specific firmware options before initialization. */ 2189 ha->isp_ops->update_fw_options(vha); 2190 2191 if (ha->flags.npiv_supported) { 2192 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha)) 2193 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; 2194 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); 2195 } 2196 2197 if (IS_FWI2_CAPABLE(ha)) { 2198 mid_init_cb->options = __constant_cpu_to_le16(BIT_1); 2199 mid_init_cb->init_cb.execution_throttle = 2200 cpu_to_le16(ha->fw_xcb_count); 2201 /* D-Port Status */ 2202 if (IS_DPORT_CAPABLE(ha)) 2203 mid_init_cb->init_cb.firmware_options_1 |= 2204 cpu_to_le16(BIT_7); 2205 /* Enable FA-WWPN */ 2206 ha->flags.fawwpn_enabled = 2207 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) ? 1 : 0; 2208 ql_dbg(ql_dbg_init, vha, 0x0141, "FA-WWPN Support: %s.\n", 2209 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled"); 2210 } 2211 2212 rval = qla2x00_init_firmware(vha, ha->init_cb_size); 2213 next_check: 2214 if (rval) { 2215 ql_log(ql_log_fatal, vha, 0x00d2, 2216 "Init Firmware **** FAILED ****.\n"); 2217 } else { 2218 ql_dbg(ql_dbg_init, vha, 0x00d3, 2219 "Init Firmware -- success.\n"); 2220 } 2221 2222 return (rval); 2223 } 2224 2225 /** 2226 * qla2x00_fw_ready() - Waits for firmware ready. 2227 * @ha: HA context 2228 * 2229 * Returns 0 on success. 2230 */ 2231 static int 2232 qla2x00_fw_ready(scsi_qla_host_t *vha) 2233 { 2234 int rval; 2235 unsigned long wtime, mtime, cs84xx_time; 2236 uint16_t min_wait; /* Minimum wait time if loop is down */ 2237 uint16_t wait_time; /* Wait time if loop is coming ready */ 2238 uint16_t state[6]; 2239 struct qla_hw_data *ha = vha->hw; 2240 2241 if (IS_QLAFX00(vha->hw)) 2242 return qlafx00_fw_ready(vha); 2243 2244 rval = QLA_SUCCESS; 2245 2246 /* 20 seconds for loop down. */ 2247 min_wait = 20; 2248 2249 /* 2250 * Firmware should take at most one RATOV to login, plus 5 seconds for 2251 * our own processing. 2252 */ 2253 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) { 2254 wait_time = min_wait; 2255 } 2256 2257 /* Min wait time if loop down */ 2258 mtime = jiffies + (min_wait * HZ); 2259 2260 /* wait time before firmware ready */ 2261 wtime = jiffies + (wait_time * HZ); 2262 2263 /* Wait for ISP to finish LIP */ 2264 if (!vha->flags.init_done) 2265 ql_log(ql_log_info, vha, 0x801e, 2266 "Waiting for LIP to complete.\n"); 2267 2268 do { 2269 memset(state, -1, sizeof(state)); 2270 rval = qla2x00_get_firmware_state(vha, state); 2271 if (rval == QLA_SUCCESS) { 2272 if (state[0] < FSTATE_LOSS_OF_SYNC) { 2273 vha->device_flags &= ~DFLG_NO_CABLE; 2274 } 2275 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) { 2276 ql_dbg(ql_dbg_taskm, vha, 0x801f, 2277 "fw_state=%x 84xx=%x.\n", state[0], 2278 state[2]); 2279 if ((state[2] & FSTATE_LOGGED_IN) && 2280 (state[2] & FSTATE_WAITING_FOR_VERIFY)) { 2281 ql_dbg(ql_dbg_taskm, vha, 0x8028, 2282 "Sending verify iocb.\n"); 2283 2284 cs84xx_time = jiffies; 2285 rval = qla84xx_init_chip(vha); 2286 if (rval != QLA_SUCCESS) { 2287 ql_log(ql_log_warn, 2288 vha, 0x8007, 2289 "Init chip failed.\n"); 2290 break; 2291 } 2292 2293 /* Add time taken to initialize. */ 2294 cs84xx_time = jiffies - cs84xx_time; 2295 wtime += cs84xx_time; 2296 mtime += cs84xx_time; 2297 ql_dbg(ql_dbg_taskm, vha, 0x8008, 2298 "Increasing wait time by %ld. " 2299 "New time %ld.\n", cs84xx_time, 2300 wtime); 2301 } 2302 } else if (state[0] == FSTATE_READY) { 2303 ql_dbg(ql_dbg_taskm, vha, 0x8037, 2304 "F/W Ready - OK.\n"); 2305 2306 qla2x00_get_retry_cnt(vha, &ha->retry_count, 2307 &ha->login_timeout, &ha->r_a_tov); 2308 2309 rval = QLA_SUCCESS; 2310 break; 2311 } 2312 2313 rval = QLA_FUNCTION_FAILED; 2314 2315 if (atomic_read(&vha->loop_down_timer) && 2316 state[0] != FSTATE_READY) { 2317 /* Loop down. Timeout on min_wait for states 2318 * other than Wait for Login. 2319 */ 2320 if (time_after_eq(jiffies, mtime)) { 2321 ql_log(ql_log_info, vha, 0x8038, 2322 "Cable is unplugged...\n"); 2323 2324 vha->device_flags |= DFLG_NO_CABLE; 2325 break; 2326 } 2327 } 2328 } else { 2329 /* Mailbox cmd failed. Timeout on min_wait. */ 2330 if (time_after_eq(jiffies, mtime) || 2331 ha->flags.isp82xx_fw_hung) 2332 break; 2333 } 2334 2335 if (time_after_eq(jiffies, wtime)) 2336 break; 2337 2338 /* Delay for a while */ 2339 msleep(500); 2340 } while (1); 2341 2342 ql_dbg(ql_dbg_taskm, vha, 0x803a, 2343 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0], 2344 state[1], state[2], state[3], state[4], state[5], jiffies); 2345 2346 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) { 2347 ql_log(ql_log_warn, vha, 0x803b, 2348 "Firmware ready **** FAILED ****.\n"); 2349 } 2350 2351 return (rval); 2352 } 2353 2354 /* 2355 * qla2x00_configure_hba 2356 * Setup adapter context. 2357 * 2358 * Input: 2359 * ha = adapter state pointer. 2360 * 2361 * Returns: 2362 * 0 = success 2363 * 2364 * Context: 2365 * Kernel context. 2366 */ 2367 static int 2368 qla2x00_configure_hba(scsi_qla_host_t *vha) 2369 { 2370 int rval; 2371 uint16_t loop_id; 2372 uint16_t topo; 2373 uint16_t sw_cap; 2374 uint8_t al_pa; 2375 uint8_t area; 2376 uint8_t domain; 2377 char connect_type[22]; 2378 struct qla_hw_data *ha = vha->hw; 2379 unsigned long flags; 2380 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 2381 2382 /* Get host addresses. */ 2383 rval = qla2x00_get_adapter_id(vha, 2384 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); 2385 if (rval != QLA_SUCCESS) { 2386 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || 2387 IS_CNA_CAPABLE(ha) || 2388 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { 2389 ql_dbg(ql_dbg_disc, vha, 0x2008, 2390 "Loop is in a transition state.\n"); 2391 } else { 2392 ql_log(ql_log_warn, vha, 0x2009, 2393 "Unable to get host loop ID.\n"); 2394 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) && 2395 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) { 2396 ql_log(ql_log_warn, vha, 0x1151, 2397 "Doing link init.\n"); 2398 if (qla24xx_link_initialize(vha) == QLA_SUCCESS) 2399 return rval; 2400 } 2401 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2402 } 2403 return (rval); 2404 } 2405 2406 if (topo == 4) { 2407 ql_log(ql_log_info, vha, 0x200a, 2408 "Cannot get topology - retrying.\n"); 2409 return (QLA_FUNCTION_FAILED); 2410 } 2411 2412 vha->loop_id = loop_id; 2413 2414 /* initialize */ 2415 ha->min_external_loopid = SNS_FIRST_LOOP_ID; 2416 ha->operating_mode = LOOP; 2417 ha->switch_cap = 0; 2418 2419 switch (topo) { 2420 case 0: 2421 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n"); 2422 ha->current_topology = ISP_CFG_NL; 2423 strcpy(connect_type, "(Loop)"); 2424 break; 2425 2426 case 1: 2427 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n"); 2428 ha->switch_cap = sw_cap; 2429 ha->current_topology = ISP_CFG_FL; 2430 strcpy(connect_type, "(FL_Port)"); 2431 break; 2432 2433 case 2: 2434 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n"); 2435 ha->operating_mode = P2P; 2436 ha->current_topology = ISP_CFG_N; 2437 strcpy(connect_type, "(N_Port-to-N_Port)"); 2438 break; 2439 2440 case 3: 2441 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n"); 2442 ha->switch_cap = sw_cap; 2443 ha->operating_mode = P2P; 2444 ha->current_topology = ISP_CFG_F; 2445 strcpy(connect_type, "(F_Port)"); 2446 break; 2447 2448 default: 2449 ql_dbg(ql_dbg_disc, vha, 0x200f, 2450 "HBA in unknown topology %x, using NL.\n", topo); 2451 ha->current_topology = ISP_CFG_NL; 2452 strcpy(connect_type, "(Loop)"); 2453 break; 2454 } 2455 2456 /* Save Host port and loop ID. */ 2457 /* byte order - Big Endian */ 2458 vha->d_id.b.domain = domain; 2459 vha->d_id.b.area = area; 2460 vha->d_id.b.al_pa = al_pa; 2461 2462 spin_lock_irqsave(&ha->vport_slock, flags); 2463 qlt_update_vp_map(vha, SET_AL_PA); 2464 spin_unlock_irqrestore(&ha->vport_slock, flags); 2465 2466 if (!vha->flags.init_done) 2467 ql_log(ql_log_info, vha, 0x2010, 2468 "Topology - %s, Host Loop address 0x%x.\n", 2469 connect_type, vha->loop_id); 2470 2471 return(rval); 2472 } 2473 2474 inline void 2475 qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, 2476 char *def) 2477 { 2478 char *st, *en; 2479 uint16_t index; 2480 struct qla_hw_data *ha = vha->hw; 2481 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 2482 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha); 2483 2484 if (memcmp(model, BINZERO, len) != 0) { 2485 strncpy(ha->model_number, model, len); 2486 st = en = ha->model_number; 2487 en += len - 1; 2488 while (en > st) { 2489 if (*en != 0x20 && *en != 0x00) 2490 break; 2491 *en-- = '\0'; 2492 } 2493 2494 index = (ha->pdev->subsystem_device & 0xff); 2495 if (use_tbl && 2496 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 2497 index < QLA_MODEL_NAMES) 2498 strncpy(ha->model_desc, 2499 qla2x00_model_name[index * 2 + 1], 2500 sizeof(ha->model_desc) - 1); 2501 } else { 2502 index = (ha->pdev->subsystem_device & 0xff); 2503 if (use_tbl && 2504 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 2505 index < QLA_MODEL_NAMES) { 2506 strcpy(ha->model_number, 2507 qla2x00_model_name[index * 2]); 2508 strncpy(ha->model_desc, 2509 qla2x00_model_name[index * 2 + 1], 2510 sizeof(ha->model_desc) - 1); 2511 } else { 2512 strcpy(ha->model_number, def); 2513 } 2514 } 2515 if (IS_FWI2_CAPABLE(ha)) 2516 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc, 2517 sizeof(ha->model_desc)); 2518 } 2519 2520 /* On sparc systems, obtain port and node WWN from firmware 2521 * properties. 2522 */ 2523 static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv) 2524 { 2525 #ifdef CONFIG_SPARC 2526 struct qla_hw_data *ha = vha->hw; 2527 struct pci_dev *pdev = ha->pdev; 2528 struct device_node *dp = pci_device_to_OF_node(pdev); 2529 const u8 *val; 2530 int len; 2531 2532 val = of_get_property(dp, "port-wwn", &len); 2533 if (val && len >= WWN_SIZE) 2534 memcpy(nv->port_name, val, WWN_SIZE); 2535 2536 val = of_get_property(dp, "node-wwn", &len); 2537 if (val && len >= WWN_SIZE) 2538 memcpy(nv->node_name, val, WWN_SIZE); 2539 #endif 2540 } 2541 2542 /* 2543 * NVRAM configuration for ISP 2xxx 2544 * 2545 * Input: 2546 * ha = adapter block pointer. 2547 * 2548 * Output: 2549 * initialization control block in response_ring 2550 * host adapters parameters in host adapter block 2551 * 2552 * Returns: 2553 * 0 = success. 2554 */ 2555 int 2556 qla2x00_nvram_config(scsi_qla_host_t *vha) 2557 { 2558 int rval; 2559 uint8_t chksum = 0; 2560 uint16_t cnt; 2561 uint8_t *dptr1, *dptr2; 2562 struct qla_hw_data *ha = vha->hw; 2563 init_cb_t *icb = ha->init_cb; 2564 nvram_t *nv = ha->nvram; 2565 uint8_t *ptr = ha->nvram; 2566 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2567 2568 rval = QLA_SUCCESS; 2569 2570 /* Determine NVRAM starting address. */ 2571 ha->nvram_size = sizeof(nvram_t); 2572 ha->nvram_base = 0; 2573 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) 2574 if ((RD_REG_WORD(®->ctrl_status) >> 14) == 1) 2575 ha->nvram_base = 0x80; 2576 2577 /* Get NVRAM data and calculate checksum. */ 2578 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size); 2579 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) 2580 chksum += *ptr++; 2581 2582 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f, 2583 "Contents of NVRAM.\n"); 2584 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110, 2585 (uint8_t *)nv, ha->nvram_size); 2586 2587 /* Bad NVRAM data, set defaults parameters. */ 2588 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || 2589 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) { 2590 /* Reset NVRAM data. */ 2591 ql_log(ql_log_warn, vha, 0x0064, 2592 "Inconsistent NVRAM " 2593 "detected: checksum=0x%x id=%c version=0x%x.\n", 2594 chksum, nv->id[0], nv->nvram_version); 2595 ql_log(ql_log_warn, vha, 0x0065, 2596 "Falling back to " 2597 "functioning (yet invalid -- WWPN) defaults.\n"); 2598 2599 /* 2600 * Set default initialization control block. 2601 */ 2602 memset(nv, 0, ha->nvram_size); 2603 nv->parameter_block_version = ICB_VERSION; 2604 2605 if (IS_QLA23XX(ha)) { 2606 nv->firmware_options[0] = BIT_2 | BIT_1; 2607 nv->firmware_options[1] = BIT_7 | BIT_5; 2608 nv->add_firmware_options[0] = BIT_5; 2609 nv->add_firmware_options[1] = BIT_5 | BIT_4; 2610 nv->frame_payload_size = 2048; 2611 nv->special_options[1] = BIT_7; 2612 } else if (IS_QLA2200(ha)) { 2613 nv->firmware_options[0] = BIT_2 | BIT_1; 2614 nv->firmware_options[1] = BIT_7 | BIT_5; 2615 nv->add_firmware_options[0] = BIT_5; 2616 nv->add_firmware_options[1] = BIT_5 | BIT_4; 2617 nv->frame_payload_size = 1024; 2618 } else if (IS_QLA2100(ha)) { 2619 nv->firmware_options[0] = BIT_3 | BIT_1; 2620 nv->firmware_options[1] = BIT_5; 2621 nv->frame_payload_size = 1024; 2622 } 2623 2624 nv->max_iocb_allocation = __constant_cpu_to_le16(256); 2625 nv->execution_throttle = __constant_cpu_to_le16(16); 2626 nv->retry_count = 8; 2627 nv->retry_delay = 1; 2628 2629 nv->port_name[0] = 33; 2630 nv->port_name[3] = 224; 2631 nv->port_name[4] = 139; 2632 2633 qla2xxx_nvram_wwn_from_ofw(vha, nv); 2634 2635 nv->login_timeout = 4; 2636 2637 /* 2638 * Set default host adapter parameters 2639 */ 2640 nv->host_p[1] = BIT_2; 2641 nv->reset_delay = 5; 2642 nv->port_down_retry_count = 8; 2643 nv->max_luns_per_target = __constant_cpu_to_le16(8); 2644 nv->link_down_timeout = 60; 2645 2646 rval = 1; 2647 } 2648 2649 #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) 2650 /* 2651 * The SN2 does not provide BIOS emulation which means you can't change 2652 * potentially bogus BIOS settings. Force the use of default settings 2653 * for link rate and frame size. Hope that the rest of the settings 2654 * are valid. 2655 */ 2656 if (ia64_platform_is("sn2")) { 2657 nv->frame_payload_size = 2048; 2658 if (IS_QLA23XX(ha)) 2659 nv->special_options[1] = BIT_7; 2660 } 2661 #endif 2662 2663 /* Reset Initialization control block */ 2664 memset(icb, 0, ha->init_cb_size); 2665 2666 /* 2667 * Setup driver NVRAM options. 2668 */ 2669 nv->firmware_options[0] |= (BIT_6 | BIT_1); 2670 nv->firmware_options[0] &= ~(BIT_5 | BIT_4); 2671 nv->firmware_options[1] |= (BIT_5 | BIT_0); 2672 nv->firmware_options[1] &= ~BIT_4; 2673 2674 if (IS_QLA23XX(ha)) { 2675 nv->firmware_options[0] |= BIT_2; 2676 nv->firmware_options[0] &= ~BIT_3; 2677 nv->special_options[0] &= ~BIT_6; 2678 nv->add_firmware_options[1] |= BIT_5 | BIT_4; 2679 2680 if (IS_QLA2300(ha)) { 2681 if (ha->fb_rev == FPM_2310) { 2682 strcpy(ha->model_number, "QLA2310"); 2683 } else { 2684 strcpy(ha->model_number, "QLA2300"); 2685 } 2686 } else { 2687 qla2x00_set_model_info(vha, nv->model_number, 2688 sizeof(nv->model_number), "QLA23xx"); 2689 } 2690 } else if (IS_QLA2200(ha)) { 2691 nv->firmware_options[0] |= BIT_2; 2692 /* 2693 * 'Point-to-point preferred, else loop' is not a safe 2694 * connection mode setting. 2695 */ 2696 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == 2697 (BIT_5 | BIT_4)) { 2698 /* Force 'loop preferred, else point-to-point'. */ 2699 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); 2700 nv->add_firmware_options[0] |= BIT_5; 2701 } 2702 strcpy(ha->model_number, "QLA22xx"); 2703 } else /*if (IS_QLA2100(ha))*/ { 2704 strcpy(ha->model_number, "QLA2100"); 2705 } 2706 2707 /* 2708 * Copy over NVRAM RISC parameter block to initialization control block. 2709 */ 2710 dptr1 = (uint8_t *)icb; 2711 dptr2 = (uint8_t *)&nv->parameter_block_version; 2712 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version; 2713 while (cnt--) 2714 *dptr1++ = *dptr2++; 2715 2716 /* Copy 2nd half. */ 2717 dptr1 = (uint8_t *)icb->add_firmware_options; 2718 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options; 2719 while (cnt--) 2720 *dptr1++ = *dptr2++; 2721 2722 /* Use alternate WWN? */ 2723 if (nv->host_p[1] & BIT_7) { 2724 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 2725 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 2726 } 2727 2728 /* Prepare nodename */ 2729 if ((icb->firmware_options[1] & BIT_6) == 0) { 2730 /* 2731 * Firmware will apply the following mask if the nodename was 2732 * not provided. 2733 */ 2734 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 2735 icb->node_name[0] &= 0xF0; 2736 } 2737 2738 /* 2739 * Set host adapter parameters. 2740 */ 2741 2742 /* 2743 * BIT_7 in the host-parameters section allows for modification to 2744 * internal driver logging. 2745 */ 2746 if (nv->host_p[0] & BIT_7) 2747 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 2748 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); 2749 /* Always load RISC code on non ISP2[12]00 chips. */ 2750 if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) 2751 ha->flags.disable_risc_code_load = 0; 2752 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0); 2753 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); 2754 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); 2755 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; 2756 ha->flags.disable_serdes = 0; 2757 2758 ha->operating_mode = 2759 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; 2760 2761 memcpy(ha->fw_seriallink_options, nv->seriallink_options, 2762 sizeof(ha->fw_seriallink_options)); 2763 2764 /* save HBA serial number */ 2765 ha->serial0 = icb->port_name[5]; 2766 ha->serial1 = icb->port_name[6]; 2767 ha->serial2 = icb->port_name[7]; 2768 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 2769 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 2770 2771 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); 2772 2773 ha->retry_count = nv->retry_count; 2774 2775 /* Set minimum login_timeout to 4 seconds. */ 2776 if (nv->login_timeout != ql2xlogintimeout) 2777 nv->login_timeout = ql2xlogintimeout; 2778 if (nv->login_timeout < 4) 2779 nv->login_timeout = 4; 2780 ha->login_timeout = nv->login_timeout; 2781 icb->login_timeout = nv->login_timeout; 2782 2783 /* Set minimum RATOV to 100 tenths of a second. */ 2784 ha->r_a_tov = 100; 2785 2786 ha->loop_reset_delay = nv->reset_delay; 2787 2788 /* Link Down Timeout = 0: 2789 * 2790 * When Port Down timer expires we will start returning 2791 * I/O's to OS with "DID_NO_CONNECT". 2792 * 2793 * Link Down Timeout != 0: 2794 * 2795 * The driver waits for the link to come up after link down 2796 * before returning I/Os to OS with "DID_NO_CONNECT". 2797 */ 2798 if (nv->link_down_timeout == 0) { 2799 ha->loop_down_abort_time = 2800 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 2801 } else { 2802 ha->link_down_timeout = nv->link_down_timeout; 2803 ha->loop_down_abort_time = 2804 (LOOP_DOWN_TIME - ha->link_down_timeout); 2805 } 2806 2807 /* 2808 * Need enough time to try and get the port back. 2809 */ 2810 ha->port_down_retry_count = nv->port_down_retry_count; 2811 if (qlport_down_retry) 2812 ha->port_down_retry_count = qlport_down_retry; 2813 /* Set login_retry_count */ 2814 ha->login_retry_count = nv->retry_count; 2815 if (ha->port_down_retry_count == nv->port_down_retry_count && 2816 ha->port_down_retry_count > 3) 2817 ha->login_retry_count = ha->port_down_retry_count; 2818 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 2819 ha->login_retry_count = ha->port_down_retry_count; 2820 if (ql2xloginretrycount) 2821 ha->login_retry_count = ql2xloginretrycount; 2822 2823 icb->lun_enables = __constant_cpu_to_le16(0); 2824 icb->command_resource_count = 0; 2825 icb->immediate_notify_resource_count = 0; 2826 icb->timeout = __constant_cpu_to_le16(0); 2827 2828 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 2829 /* Enable RIO */ 2830 icb->firmware_options[0] &= ~BIT_3; 2831 icb->add_firmware_options[0] &= 2832 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 2833 icb->add_firmware_options[0] |= BIT_2; 2834 icb->response_accumulation_timer = 3; 2835 icb->interrupt_delay_timer = 5; 2836 2837 vha->flags.process_response_queue = 1; 2838 } else { 2839 /* Enable ZIO. */ 2840 if (!vha->flags.init_done) { 2841 ha->zio_mode = icb->add_firmware_options[0] & 2842 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 2843 ha->zio_timer = icb->interrupt_delay_timer ? 2844 icb->interrupt_delay_timer: 2; 2845 } 2846 icb->add_firmware_options[0] &= 2847 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 2848 vha->flags.process_response_queue = 0; 2849 if (ha->zio_mode != QLA_ZIO_DISABLED) { 2850 ha->zio_mode = QLA_ZIO_MODE_6; 2851 2852 ql_log(ql_log_info, vha, 0x0068, 2853 "ZIO mode %d enabled; timer delay (%d us).\n", 2854 ha->zio_mode, ha->zio_timer * 100); 2855 2856 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode; 2857 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer; 2858 vha->flags.process_response_queue = 1; 2859 } 2860 } 2861 2862 if (rval) { 2863 ql_log(ql_log_warn, vha, 0x0069, 2864 "NVRAM configuration failed.\n"); 2865 } 2866 return (rval); 2867 } 2868 2869 static void 2870 qla2x00_rport_del(void *data) 2871 { 2872 fc_port_t *fcport = data; 2873 struct fc_rport *rport; 2874 scsi_qla_host_t *vha = fcport->vha; 2875 unsigned long flags; 2876 2877 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 2878 rport = fcport->drport ? fcport->drport: fcport->rport; 2879 fcport->drport = NULL; 2880 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 2881 if (rport) { 2882 fc_remote_port_delete(rport); 2883 /* 2884 * Release the target mode FC NEXUS in qla_target.c code 2885 * if target mod is enabled. 2886 */ 2887 qlt_fc_port_deleted(vha, fcport); 2888 } 2889 } 2890 2891 /** 2892 * qla2x00_alloc_fcport() - Allocate a generic fcport. 2893 * @ha: HA context 2894 * @flags: allocation flags 2895 * 2896 * Returns a pointer to the allocated fcport, or NULL, if none available. 2897 */ 2898 fc_port_t * 2899 qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags) 2900 { 2901 fc_port_t *fcport; 2902 2903 fcport = kzalloc(sizeof(fc_port_t), flags); 2904 if (!fcport) 2905 return NULL; 2906 2907 /* Setup fcport template structure. */ 2908 fcport->vha = vha; 2909 fcport->port_type = FCT_UNKNOWN; 2910 fcport->loop_id = FC_NO_LOOP_ID; 2911 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED); 2912 fcport->supported_classes = FC_COS_UNSPECIFIED; 2913 2914 return fcport; 2915 } 2916 2917 /* 2918 * qla2x00_configure_loop 2919 * Updates Fibre Channel Device Database with what is actually on loop. 2920 * 2921 * Input: 2922 * ha = adapter block pointer. 2923 * 2924 * Returns: 2925 * 0 = success. 2926 * 1 = error. 2927 * 2 = database was full and device was not configured. 2928 */ 2929 static int 2930 qla2x00_configure_loop(scsi_qla_host_t *vha) 2931 { 2932 int rval; 2933 unsigned long flags, save_flags; 2934 struct qla_hw_data *ha = vha->hw; 2935 rval = QLA_SUCCESS; 2936 2937 /* Get Initiator ID */ 2938 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) { 2939 rval = qla2x00_configure_hba(vha); 2940 if (rval != QLA_SUCCESS) { 2941 ql_dbg(ql_dbg_disc, vha, 0x2013, 2942 "Unable to configure HBA.\n"); 2943 return (rval); 2944 } 2945 } 2946 2947 save_flags = flags = vha->dpc_flags; 2948 ql_dbg(ql_dbg_disc, vha, 0x2014, 2949 "Configure loop -- dpc flags = 0x%lx.\n", flags); 2950 2951 /* 2952 * If we have both an RSCN and PORT UPDATE pending then handle them 2953 * both at the same time. 2954 */ 2955 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2956 clear_bit(RSCN_UPDATE, &vha->dpc_flags); 2957 2958 qla2x00_get_data_rate(vha); 2959 2960 /* Determine what we need to do */ 2961 if (ha->current_topology == ISP_CFG_FL && 2962 (test_bit(LOCAL_LOOP_UPDATE, &flags))) { 2963 2964 set_bit(RSCN_UPDATE, &flags); 2965 2966 } else if (ha->current_topology == ISP_CFG_F && 2967 (test_bit(LOCAL_LOOP_UPDATE, &flags))) { 2968 2969 set_bit(RSCN_UPDATE, &flags); 2970 clear_bit(LOCAL_LOOP_UPDATE, &flags); 2971 2972 } else if (ha->current_topology == ISP_CFG_N) { 2973 clear_bit(RSCN_UPDATE, &flags); 2974 2975 } else if (!vha->flags.online || 2976 (test_bit(ABORT_ISP_ACTIVE, &flags))) { 2977 2978 set_bit(RSCN_UPDATE, &flags); 2979 set_bit(LOCAL_LOOP_UPDATE, &flags); 2980 } 2981 2982 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) { 2983 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 2984 ql_dbg(ql_dbg_disc, vha, 0x2015, 2985 "Loop resync needed, failing.\n"); 2986 rval = QLA_FUNCTION_FAILED; 2987 } else 2988 rval = qla2x00_configure_local_loop(vha); 2989 } 2990 2991 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) { 2992 if (LOOP_TRANSITION(vha)) { 2993 ql_dbg(ql_dbg_disc, vha, 0x201e, 2994 "Needs RSCN update and loop transition.\n"); 2995 rval = QLA_FUNCTION_FAILED; 2996 } 2997 else 2998 rval = qla2x00_configure_fabric(vha); 2999 } 3000 3001 if (rval == QLA_SUCCESS) { 3002 if (atomic_read(&vha->loop_down_timer) || 3003 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 3004 rval = QLA_FUNCTION_FAILED; 3005 } else { 3006 atomic_set(&vha->loop_state, LOOP_READY); 3007 ql_dbg(ql_dbg_disc, vha, 0x2069, 3008 "LOOP READY.\n"); 3009 } 3010 } 3011 3012 if (rval) { 3013 ql_dbg(ql_dbg_disc, vha, 0x206a, 3014 "%s *** FAILED ***.\n", __func__); 3015 } else { 3016 ql_dbg(ql_dbg_disc, vha, 0x206b, 3017 "%s: exiting normally.\n", __func__); 3018 } 3019 3020 /* Restore state if a resync event occurred during processing */ 3021 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 3022 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags)) 3023 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 3024 if (test_bit(RSCN_UPDATE, &save_flags)) { 3025 set_bit(RSCN_UPDATE, &vha->dpc_flags); 3026 } 3027 } 3028 3029 return (rval); 3030 } 3031 3032 3033 3034 /* 3035 * qla2x00_configure_local_loop 3036 * Updates Fibre Channel Device Database with local loop devices. 3037 * 3038 * Input: 3039 * ha = adapter block pointer. 3040 * 3041 * Returns: 3042 * 0 = success. 3043 */ 3044 static int 3045 qla2x00_configure_local_loop(scsi_qla_host_t *vha) 3046 { 3047 int rval, rval2; 3048 int found_devs; 3049 int found; 3050 fc_port_t *fcport, *new_fcport; 3051 3052 uint16_t index; 3053 uint16_t entries; 3054 char *id_iter; 3055 uint16_t loop_id; 3056 uint8_t domain, area, al_pa; 3057 struct qla_hw_data *ha = vha->hw; 3058 3059 found_devs = 0; 3060 new_fcport = NULL; 3061 entries = MAX_FIBRE_DEVICES_LOOP; 3062 3063 /* Get list of logged in devices. */ 3064 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha)); 3065 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma, 3066 &entries); 3067 if (rval != QLA_SUCCESS) 3068 goto cleanup_allocation; 3069 3070 ql_dbg(ql_dbg_disc, vha, 0x2017, 3071 "Entries in ID list (%d).\n", entries); 3072 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075, 3073 (uint8_t *)ha->gid_list, 3074 entries * sizeof(struct gid_list_info)); 3075 3076 /* Allocate temporary fcport for any new fcports discovered. */ 3077 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 3078 if (new_fcport == NULL) { 3079 ql_log(ql_log_warn, vha, 0x2018, 3080 "Memory allocation failed for fcport.\n"); 3081 rval = QLA_MEMORY_ALLOC_FAILED; 3082 goto cleanup_allocation; 3083 } 3084 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 3085 3086 /* 3087 * Mark local devices that were present with FCF_DEVICE_LOST for now. 3088 */ 3089 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3090 if (atomic_read(&fcport->state) == FCS_ONLINE && 3091 fcport->port_type != FCT_BROADCAST && 3092 (fcport->flags & FCF_FABRIC_DEVICE) == 0) { 3093 3094 ql_dbg(ql_dbg_disc, vha, 0x2019, 3095 "Marking port lost loop_id=0x%04x.\n", 3096 fcport->loop_id); 3097 3098 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3099 } 3100 } 3101 3102 /* Add devices to port list. */ 3103 id_iter = (char *)ha->gid_list; 3104 for (index = 0; index < entries; index++) { 3105 domain = ((struct gid_list_info *)id_iter)->domain; 3106 area = ((struct gid_list_info *)id_iter)->area; 3107 al_pa = ((struct gid_list_info *)id_iter)->al_pa; 3108 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 3109 loop_id = (uint16_t) 3110 ((struct gid_list_info *)id_iter)->loop_id_2100; 3111 else 3112 loop_id = le16_to_cpu( 3113 ((struct gid_list_info *)id_iter)->loop_id); 3114 id_iter += ha->gid_list_info_size; 3115 3116 /* Bypass reserved domain fields. */ 3117 if ((domain & 0xf0) == 0xf0) 3118 continue; 3119 3120 /* Bypass if not same domain and area of adapter. */ 3121 if (area && domain && 3122 (area != vha->d_id.b.area || domain != vha->d_id.b.domain)) 3123 continue; 3124 3125 /* Bypass invalid local loop ID. */ 3126 if (loop_id > LAST_LOCAL_LOOP_ID) 3127 continue; 3128 3129 memset(new_fcport, 0, sizeof(fc_port_t)); 3130 3131 /* Fill in member data. */ 3132 new_fcport->d_id.b.domain = domain; 3133 new_fcport->d_id.b.area = area; 3134 new_fcport->d_id.b.al_pa = al_pa; 3135 new_fcport->loop_id = loop_id; 3136 rval2 = qla2x00_get_port_database(vha, new_fcport, 0); 3137 if (rval2 != QLA_SUCCESS) { 3138 ql_dbg(ql_dbg_disc, vha, 0x201a, 3139 "Failed to retrieve fcport information " 3140 "-- get_port_database=%x, loop_id=0x%04x.\n", 3141 rval2, new_fcport->loop_id); 3142 ql_dbg(ql_dbg_disc, vha, 0x201b, 3143 "Scheduling resync.\n"); 3144 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 3145 continue; 3146 } 3147 3148 /* Check for matching device in port list. */ 3149 found = 0; 3150 fcport = NULL; 3151 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3152 if (memcmp(new_fcport->port_name, fcport->port_name, 3153 WWN_SIZE)) 3154 continue; 3155 3156 fcport->flags &= ~FCF_FABRIC_DEVICE; 3157 fcport->loop_id = new_fcport->loop_id; 3158 fcport->port_type = new_fcport->port_type; 3159 fcport->d_id.b24 = new_fcport->d_id.b24; 3160 memcpy(fcport->node_name, new_fcport->node_name, 3161 WWN_SIZE); 3162 3163 found++; 3164 break; 3165 } 3166 3167 if (!found) { 3168 /* New device, add to fcports list. */ 3169 list_add_tail(&new_fcport->list, &vha->vp_fcports); 3170 3171 /* Allocate a new replacement fcport. */ 3172 fcport = new_fcport; 3173 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 3174 if (new_fcport == NULL) { 3175 ql_log(ql_log_warn, vha, 0x201c, 3176 "Failed to allocate memory for fcport.\n"); 3177 rval = QLA_MEMORY_ALLOC_FAILED; 3178 goto cleanup_allocation; 3179 } 3180 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 3181 } 3182 3183 /* Base iIDMA settings on HBA port speed. */ 3184 fcport->fp_speed = ha->link_data_rate; 3185 3186 qla2x00_update_fcport(vha, fcport); 3187 3188 found_devs++; 3189 } 3190 3191 cleanup_allocation: 3192 kfree(new_fcport); 3193 3194 if (rval != QLA_SUCCESS) { 3195 ql_dbg(ql_dbg_disc, vha, 0x201d, 3196 "Configure local loop error exit: rval=%x.\n", rval); 3197 } 3198 3199 return (rval); 3200 } 3201 3202 static void 3203 qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 3204 { 3205 int rval; 3206 uint16_t mb[MAILBOX_REGISTER_COUNT]; 3207 struct qla_hw_data *ha = vha->hw; 3208 3209 if (!IS_IIDMA_CAPABLE(ha)) 3210 return; 3211 3212 if (atomic_read(&fcport->state) != FCS_ONLINE) 3213 return; 3214 3215 if (fcport->fp_speed == PORT_SPEED_UNKNOWN || 3216 fcport->fp_speed > ha->link_data_rate) 3217 return; 3218 3219 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed, 3220 mb); 3221 if (rval != QLA_SUCCESS) { 3222 ql_dbg(ql_dbg_disc, vha, 0x2004, 3223 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n", 3224 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]); 3225 } else { 3226 ql_dbg(ql_dbg_disc, vha, 0x2005, 3227 "iIDMA adjusted to %s GB/s on %8phN.\n", 3228 qla2x00_get_link_speed_str(ha, fcport->fp_speed), 3229 fcport->port_name); 3230 } 3231 } 3232 3233 static void 3234 qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport) 3235 { 3236 struct fc_rport_identifiers rport_ids; 3237 struct fc_rport *rport; 3238 unsigned long flags; 3239 3240 qla2x00_rport_del(fcport); 3241 3242 rport_ids.node_name = wwn_to_u64(fcport->node_name); 3243 rport_ids.port_name = wwn_to_u64(fcport->port_name); 3244 rport_ids.port_id = fcport->d_id.b.domain << 16 | 3245 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa; 3246 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; 3247 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids); 3248 if (!rport) { 3249 ql_log(ql_log_warn, vha, 0x2006, 3250 "Unable to allocate fc remote port.\n"); 3251 return; 3252 } 3253 /* 3254 * Create target mode FC NEXUS in qla_target.c if target mode is 3255 * enabled.. 3256 */ 3257 qlt_fc_port_added(vha, fcport); 3258 3259 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 3260 *((fc_port_t **)rport->dd_data) = fcport; 3261 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 3262 3263 rport->supported_classes = fcport->supported_classes; 3264 3265 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; 3266 if (fcport->port_type == FCT_INITIATOR) 3267 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR; 3268 if (fcport->port_type == FCT_TARGET) 3269 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET; 3270 fc_remote_port_rolechg(rport, rport_ids.roles); 3271 } 3272 3273 /* 3274 * qla2x00_update_fcport 3275 * Updates device on list. 3276 * 3277 * Input: 3278 * ha = adapter block pointer. 3279 * fcport = port structure pointer. 3280 * 3281 * Return: 3282 * 0 - Success 3283 * BIT_0 - error 3284 * 3285 * Context: 3286 * Kernel context. 3287 */ 3288 void 3289 qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 3290 { 3291 fcport->vha = vha; 3292 3293 if (IS_QLAFX00(vha->hw)) { 3294 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 3295 qla2x00_reg_remote_port(vha, fcport); 3296 return; 3297 } 3298 fcport->login_retry = 0; 3299 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 3300 3301 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 3302 qla2x00_iidma_fcport(vha, fcport); 3303 qla24xx_update_fcport_fcp_prio(vha, fcport); 3304 qla2x00_reg_remote_port(vha, fcport); 3305 } 3306 3307 /* 3308 * qla2x00_configure_fabric 3309 * Setup SNS devices with loop ID's. 3310 * 3311 * Input: 3312 * ha = adapter block pointer. 3313 * 3314 * Returns: 3315 * 0 = success. 3316 * BIT_0 = error 3317 */ 3318 static int 3319 qla2x00_configure_fabric(scsi_qla_host_t *vha) 3320 { 3321 int rval; 3322 fc_port_t *fcport, *fcptemp; 3323 uint16_t next_loopid; 3324 uint16_t mb[MAILBOX_REGISTER_COUNT]; 3325 uint16_t loop_id; 3326 LIST_HEAD(new_fcports); 3327 struct qla_hw_data *ha = vha->hw; 3328 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3329 3330 /* If FL port exists, then SNS is present */ 3331 if (IS_FWI2_CAPABLE(ha)) 3332 loop_id = NPH_F_PORT; 3333 else 3334 loop_id = SNS_FL_PORT; 3335 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1); 3336 if (rval != QLA_SUCCESS) { 3337 ql_dbg(ql_dbg_disc, vha, 0x201f, 3338 "MBX_GET_PORT_NAME failed, No FL Port.\n"); 3339 3340 vha->device_flags &= ~SWITCH_FOUND; 3341 return (QLA_SUCCESS); 3342 } 3343 vha->device_flags |= SWITCH_FOUND; 3344 3345 do { 3346 /* FDMI support. */ 3347 if (ql2xfdmienable && 3348 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags)) 3349 qla2x00_fdmi_register(vha); 3350 3351 /* Ensure we are logged into the SNS. */ 3352 if (IS_FWI2_CAPABLE(ha)) 3353 loop_id = NPH_SNS; 3354 else 3355 loop_id = SIMPLE_NAME_SERVER; 3356 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff, 3357 0xfc, mb, BIT_1|BIT_0); 3358 if (rval != QLA_SUCCESS) { 3359 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 3360 return rval; 3361 } 3362 if (mb[0] != MBS_COMMAND_COMPLETE) { 3363 ql_dbg(ql_dbg_disc, vha, 0x2042, 3364 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x " 3365 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1], 3366 mb[2], mb[6], mb[7]); 3367 return (QLA_SUCCESS); 3368 } 3369 3370 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) { 3371 if (qla2x00_rft_id(vha)) { 3372 /* EMPTY */ 3373 ql_dbg(ql_dbg_disc, vha, 0x2045, 3374 "Register FC-4 TYPE failed.\n"); 3375 } 3376 if (qla2x00_rff_id(vha)) { 3377 /* EMPTY */ 3378 ql_dbg(ql_dbg_disc, vha, 0x2049, 3379 "Register FC-4 Features failed.\n"); 3380 } 3381 if (qla2x00_rnn_id(vha)) { 3382 /* EMPTY */ 3383 ql_dbg(ql_dbg_disc, vha, 0x204f, 3384 "Register Node Name failed.\n"); 3385 } else if (qla2x00_rsnn_nn(vha)) { 3386 /* EMPTY */ 3387 ql_dbg(ql_dbg_disc, vha, 0x2053, 3388 "Register Symobilic Node Name failed.\n"); 3389 } 3390 } 3391 3392 #define QLA_FCPORT_SCAN 1 3393 #define QLA_FCPORT_FOUND 2 3394 3395 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3396 fcport->scan_state = QLA_FCPORT_SCAN; 3397 } 3398 3399 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports); 3400 if (rval != QLA_SUCCESS) 3401 break; 3402 3403 /* 3404 * Logout all previous fabric devices marked lost, except 3405 * FCP2 devices. 3406 */ 3407 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3408 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 3409 break; 3410 3411 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) 3412 continue; 3413 3414 if (fcport->scan_state == QLA_FCPORT_SCAN && 3415 atomic_read(&fcport->state) == FCS_ONLINE) { 3416 qla2x00_mark_device_lost(vha, fcport, 3417 ql2xplogiabsentdevice, 0); 3418 if (fcport->loop_id != FC_NO_LOOP_ID && 3419 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 3420 fcport->port_type != FCT_INITIATOR && 3421 fcport->port_type != FCT_BROADCAST) { 3422 ha->isp_ops->fabric_logout(vha, 3423 fcport->loop_id, 3424 fcport->d_id.b.domain, 3425 fcport->d_id.b.area, 3426 fcport->d_id.b.al_pa); 3427 qla2x00_clear_loop_id(fcport); 3428 } 3429 } 3430 } 3431 3432 /* Starting free loop ID. */ 3433 next_loopid = ha->min_external_loopid; 3434 3435 /* 3436 * Scan through our port list and login entries that need to be 3437 * logged in. 3438 */ 3439 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3440 if (atomic_read(&vha->loop_down_timer) || 3441 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 3442 break; 3443 3444 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 || 3445 (fcport->flags & FCF_LOGIN_NEEDED) == 0) 3446 continue; 3447 3448 if (fcport->loop_id == FC_NO_LOOP_ID) { 3449 fcport->loop_id = next_loopid; 3450 rval = qla2x00_find_new_loop_id( 3451 base_vha, fcport); 3452 if (rval != QLA_SUCCESS) { 3453 /* Ran out of IDs to use */ 3454 break; 3455 } 3456 } 3457 /* Login and update database */ 3458 qla2x00_fabric_dev_login(vha, fcport, &next_loopid); 3459 } 3460 3461 /* Exit if out of loop IDs. */ 3462 if (rval != QLA_SUCCESS) { 3463 break; 3464 } 3465 3466 /* 3467 * Login and add the new devices to our port list. 3468 */ 3469 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) { 3470 if (atomic_read(&vha->loop_down_timer) || 3471 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 3472 break; 3473 3474 /* Find a new loop ID to use. */ 3475 fcport->loop_id = next_loopid; 3476 rval = qla2x00_find_new_loop_id(base_vha, fcport); 3477 if (rval != QLA_SUCCESS) { 3478 /* Ran out of IDs to use */ 3479 break; 3480 } 3481 3482 /* Login and update database */ 3483 qla2x00_fabric_dev_login(vha, fcport, &next_loopid); 3484 3485 list_move_tail(&fcport->list, &vha->vp_fcports); 3486 } 3487 } while (0); 3488 3489 /* Free all new device structures not processed. */ 3490 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) { 3491 list_del(&fcport->list); 3492 kfree(fcport); 3493 } 3494 3495 if (rval) { 3496 ql_dbg(ql_dbg_disc, vha, 0x2068, 3497 "Configure fabric error exit rval=%d.\n", rval); 3498 } 3499 3500 return (rval); 3501 } 3502 3503 /* 3504 * qla2x00_find_all_fabric_devs 3505 * 3506 * Input: 3507 * ha = adapter block pointer. 3508 * dev = database device entry pointer. 3509 * 3510 * Returns: 3511 * 0 = success. 3512 * 3513 * Context: 3514 * Kernel context. 3515 */ 3516 static int 3517 qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha, 3518 struct list_head *new_fcports) 3519 { 3520 int rval; 3521 uint16_t loop_id; 3522 fc_port_t *fcport, *new_fcport, *fcptemp; 3523 int found; 3524 3525 sw_info_t *swl; 3526 int swl_idx; 3527 int first_dev, last_dev; 3528 port_id_t wrap = {}, nxt_d_id; 3529 struct qla_hw_data *ha = vha->hw; 3530 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 3531 3532 rval = QLA_SUCCESS; 3533 3534 /* Try GID_PT to get device list, else GAN. */ 3535 if (!ha->swl) 3536 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t), 3537 GFP_KERNEL); 3538 swl = ha->swl; 3539 if (!swl) { 3540 /*EMPTY*/ 3541 ql_dbg(ql_dbg_disc, vha, 0x2054, 3542 "GID_PT allocations failed, fallback on GA_NXT.\n"); 3543 } else { 3544 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t)); 3545 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) { 3546 swl = NULL; 3547 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) { 3548 swl = NULL; 3549 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) { 3550 swl = NULL; 3551 } else if (ql2xiidmaenable && 3552 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) { 3553 qla2x00_gpsc(vha, swl); 3554 } 3555 3556 /* If other queries succeeded probe for FC-4 type */ 3557 if (swl) 3558 qla2x00_gff_id(vha, swl); 3559 } 3560 swl_idx = 0; 3561 3562 /* Allocate temporary fcport for any new fcports discovered. */ 3563 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 3564 if (new_fcport == NULL) { 3565 ql_log(ql_log_warn, vha, 0x205e, 3566 "Failed to allocate memory for fcport.\n"); 3567 return (QLA_MEMORY_ALLOC_FAILED); 3568 } 3569 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 3570 /* Set start port ID scan at adapter ID. */ 3571 first_dev = 1; 3572 last_dev = 0; 3573 3574 /* Starting free loop ID. */ 3575 loop_id = ha->min_external_loopid; 3576 for (; loop_id <= ha->max_loop_id; loop_id++) { 3577 if (qla2x00_is_reserved_id(vha, loop_id)) 3578 continue; 3579 3580 if (ha->current_topology == ISP_CFG_FL && 3581 (atomic_read(&vha->loop_down_timer) || 3582 LOOP_TRANSITION(vha))) { 3583 atomic_set(&vha->loop_down_timer, 0); 3584 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 3585 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 3586 break; 3587 } 3588 3589 if (swl != NULL) { 3590 if (last_dev) { 3591 wrap.b24 = new_fcport->d_id.b24; 3592 } else { 3593 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24; 3594 memcpy(new_fcport->node_name, 3595 swl[swl_idx].node_name, WWN_SIZE); 3596 memcpy(new_fcport->port_name, 3597 swl[swl_idx].port_name, WWN_SIZE); 3598 memcpy(new_fcport->fabric_port_name, 3599 swl[swl_idx].fabric_port_name, WWN_SIZE); 3600 new_fcport->fp_speed = swl[swl_idx].fp_speed; 3601 new_fcport->fc4_type = swl[swl_idx].fc4_type; 3602 3603 if (swl[swl_idx].d_id.b.rsvd_1 != 0) { 3604 last_dev = 1; 3605 } 3606 swl_idx++; 3607 } 3608 } else { 3609 /* Send GA_NXT to the switch */ 3610 rval = qla2x00_ga_nxt(vha, new_fcport); 3611 if (rval != QLA_SUCCESS) { 3612 ql_log(ql_log_warn, vha, 0x2064, 3613 "SNS scan failed -- assuming " 3614 "zero-entry result.\n"); 3615 list_for_each_entry_safe(fcport, fcptemp, 3616 new_fcports, list) { 3617 list_del(&fcport->list); 3618 kfree(fcport); 3619 } 3620 rval = QLA_SUCCESS; 3621 break; 3622 } 3623 } 3624 3625 /* If wrap on switch device list, exit. */ 3626 if (first_dev) { 3627 wrap.b24 = new_fcport->d_id.b24; 3628 first_dev = 0; 3629 } else if (new_fcport->d_id.b24 == wrap.b24) { 3630 ql_dbg(ql_dbg_disc, vha, 0x2065, 3631 "Device wrap (%02x%02x%02x).\n", 3632 new_fcport->d_id.b.domain, 3633 new_fcport->d_id.b.area, 3634 new_fcport->d_id.b.al_pa); 3635 break; 3636 } 3637 3638 /* Bypass if same physical adapter. */ 3639 if (new_fcport->d_id.b24 == base_vha->d_id.b24) 3640 continue; 3641 3642 /* Bypass virtual ports of the same host. */ 3643 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24)) 3644 continue; 3645 3646 /* Bypass if same domain and area of adapter. */ 3647 if (((new_fcport->d_id.b24 & 0xffff00) == 3648 (vha->d_id.b24 & 0xffff00)) && ha->current_topology == 3649 ISP_CFG_FL) 3650 continue; 3651 3652 /* Bypass reserved domain fields. */ 3653 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0) 3654 continue; 3655 3656 /* Bypass ports whose FCP-4 type is not FCP_SCSI */ 3657 if (ql2xgffidenable && 3658 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI && 3659 new_fcport->fc4_type != FC4_TYPE_UNKNOWN)) 3660 continue; 3661 3662 /* Locate matching device in database. */ 3663 found = 0; 3664 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3665 if (memcmp(new_fcport->port_name, fcport->port_name, 3666 WWN_SIZE)) 3667 continue; 3668 3669 fcport->scan_state = QLA_FCPORT_FOUND; 3670 3671 found++; 3672 3673 /* Update port state. */ 3674 memcpy(fcport->fabric_port_name, 3675 new_fcport->fabric_port_name, WWN_SIZE); 3676 fcport->fp_speed = new_fcport->fp_speed; 3677 3678 /* 3679 * If address the same and state FCS_ONLINE, nothing 3680 * changed. 3681 */ 3682 if (fcport->d_id.b24 == new_fcport->d_id.b24 && 3683 atomic_read(&fcport->state) == FCS_ONLINE) { 3684 break; 3685 } 3686 3687 /* 3688 * If device was not a fabric device before. 3689 */ 3690 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) { 3691 fcport->d_id.b24 = new_fcport->d_id.b24; 3692 qla2x00_clear_loop_id(fcport); 3693 fcport->flags |= (FCF_FABRIC_DEVICE | 3694 FCF_LOGIN_NEEDED); 3695 break; 3696 } 3697 3698 /* 3699 * Port ID changed or device was marked to be updated; 3700 * Log it out if still logged in and mark it for 3701 * relogin later. 3702 */ 3703 fcport->d_id.b24 = new_fcport->d_id.b24; 3704 fcport->flags |= FCF_LOGIN_NEEDED; 3705 if (fcport->loop_id != FC_NO_LOOP_ID && 3706 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 3707 (fcport->flags & FCF_ASYNC_SENT) == 0 && 3708 fcport->port_type != FCT_INITIATOR && 3709 fcport->port_type != FCT_BROADCAST) { 3710 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 3711 fcport->d_id.b.domain, fcport->d_id.b.area, 3712 fcport->d_id.b.al_pa); 3713 qla2x00_clear_loop_id(fcport); 3714 } 3715 3716 break; 3717 } 3718 3719 if (found) 3720 continue; 3721 /* If device was not in our fcports list, then add it. */ 3722 list_add_tail(&new_fcport->list, new_fcports); 3723 3724 /* Allocate a new replacement fcport. */ 3725 nxt_d_id.b24 = new_fcport->d_id.b24; 3726 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 3727 if (new_fcport == NULL) { 3728 ql_log(ql_log_warn, vha, 0x2066, 3729 "Memory allocation failed for fcport.\n"); 3730 return (QLA_MEMORY_ALLOC_FAILED); 3731 } 3732 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 3733 new_fcport->d_id.b24 = nxt_d_id.b24; 3734 } 3735 3736 kfree(new_fcport); 3737 3738 return (rval); 3739 } 3740 3741 /* 3742 * qla2x00_find_new_loop_id 3743 * Scan through our port list and find a new usable loop ID. 3744 * 3745 * Input: 3746 * ha: adapter state pointer. 3747 * dev: port structure pointer. 3748 * 3749 * Returns: 3750 * qla2x00 local function return status code. 3751 * 3752 * Context: 3753 * Kernel context. 3754 */ 3755 int 3756 qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) 3757 { 3758 int rval; 3759 struct qla_hw_data *ha = vha->hw; 3760 unsigned long flags = 0; 3761 3762 rval = QLA_SUCCESS; 3763 3764 spin_lock_irqsave(&ha->vport_slock, flags); 3765 3766 dev->loop_id = find_first_zero_bit(ha->loop_id_map, 3767 LOOPID_MAP_SIZE); 3768 if (dev->loop_id >= LOOPID_MAP_SIZE || 3769 qla2x00_is_reserved_id(vha, dev->loop_id)) { 3770 dev->loop_id = FC_NO_LOOP_ID; 3771 rval = QLA_FUNCTION_FAILED; 3772 } else 3773 set_bit(dev->loop_id, ha->loop_id_map); 3774 3775 spin_unlock_irqrestore(&ha->vport_slock, flags); 3776 3777 if (rval == QLA_SUCCESS) 3778 ql_dbg(ql_dbg_disc, dev->vha, 0x2086, 3779 "Assigning new loopid=%x, portid=%x.\n", 3780 dev->loop_id, dev->d_id.b24); 3781 else 3782 ql_log(ql_log_warn, dev->vha, 0x2087, 3783 "No loop_id's available, portid=%x.\n", 3784 dev->d_id.b24); 3785 3786 return (rval); 3787 } 3788 3789 /* 3790 * qla2x00_fabric_dev_login 3791 * Login fabric target device and update FC port database. 3792 * 3793 * Input: 3794 * ha: adapter state pointer. 3795 * fcport: port structure list pointer. 3796 * next_loopid: contains value of a new loop ID that can be used 3797 * by the next login attempt. 3798 * 3799 * Returns: 3800 * qla2x00 local function return status code. 3801 * 3802 * Context: 3803 * Kernel context. 3804 */ 3805 static int 3806 qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport, 3807 uint16_t *next_loopid) 3808 { 3809 int rval; 3810 int retry; 3811 uint8_t opts; 3812 struct qla_hw_data *ha = vha->hw; 3813 3814 rval = QLA_SUCCESS; 3815 retry = 0; 3816 3817 if (IS_ALOGIO_CAPABLE(ha)) { 3818 if (fcport->flags & FCF_ASYNC_SENT) 3819 return rval; 3820 fcport->flags |= FCF_ASYNC_SENT; 3821 rval = qla2x00_post_async_login_work(vha, fcport, NULL); 3822 if (!rval) 3823 return rval; 3824 } 3825 3826 fcport->flags &= ~FCF_ASYNC_SENT; 3827 rval = qla2x00_fabric_login(vha, fcport, next_loopid); 3828 if (rval == QLA_SUCCESS) { 3829 /* Send an ADISC to FCP2 devices.*/ 3830 opts = 0; 3831 if (fcport->flags & FCF_FCP2_DEVICE) 3832 opts |= BIT_1; 3833 rval = qla2x00_get_port_database(vha, fcport, opts); 3834 if (rval != QLA_SUCCESS) { 3835 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 3836 fcport->d_id.b.domain, fcport->d_id.b.area, 3837 fcport->d_id.b.al_pa); 3838 qla2x00_mark_device_lost(vha, fcport, 1, 0); 3839 } else { 3840 qla2x00_update_fcport(vha, fcport); 3841 } 3842 } else { 3843 /* Retry Login. */ 3844 qla2x00_mark_device_lost(vha, fcport, 1, 0); 3845 } 3846 3847 return (rval); 3848 } 3849 3850 /* 3851 * qla2x00_fabric_login 3852 * Issue fabric login command. 3853 * 3854 * Input: 3855 * ha = adapter block pointer. 3856 * device = pointer to FC device type structure. 3857 * 3858 * Returns: 3859 * 0 - Login successfully 3860 * 1 - Login failed 3861 * 2 - Initiator device 3862 * 3 - Fatal error 3863 */ 3864 int 3865 qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport, 3866 uint16_t *next_loopid) 3867 { 3868 int rval; 3869 int retry; 3870 uint16_t tmp_loopid; 3871 uint16_t mb[MAILBOX_REGISTER_COUNT]; 3872 struct qla_hw_data *ha = vha->hw; 3873 3874 retry = 0; 3875 tmp_loopid = 0; 3876 3877 for (;;) { 3878 ql_dbg(ql_dbg_disc, vha, 0x2000, 3879 "Trying Fabric Login w/loop id 0x%04x for port " 3880 "%02x%02x%02x.\n", 3881 fcport->loop_id, fcport->d_id.b.domain, 3882 fcport->d_id.b.area, fcport->d_id.b.al_pa); 3883 3884 /* Login fcport on switch. */ 3885 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id, 3886 fcport->d_id.b.domain, fcport->d_id.b.area, 3887 fcport->d_id.b.al_pa, mb, BIT_0); 3888 if (rval != QLA_SUCCESS) { 3889 return rval; 3890 } 3891 if (mb[0] == MBS_PORT_ID_USED) { 3892 /* 3893 * Device has another loop ID. The firmware team 3894 * recommends the driver perform an implicit login with 3895 * the specified ID again. The ID we just used is save 3896 * here so we return with an ID that can be tried by 3897 * the next login. 3898 */ 3899 retry++; 3900 tmp_loopid = fcport->loop_id; 3901 fcport->loop_id = mb[1]; 3902 3903 ql_dbg(ql_dbg_disc, vha, 0x2001, 3904 "Fabric Login: port in use - next loop " 3905 "id=0x%04x, port id= %02x%02x%02x.\n", 3906 fcport->loop_id, fcport->d_id.b.domain, 3907 fcport->d_id.b.area, fcport->d_id.b.al_pa); 3908 3909 } else if (mb[0] == MBS_COMMAND_COMPLETE) { 3910 /* 3911 * Login succeeded. 3912 */ 3913 if (retry) { 3914 /* A retry occurred before. */ 3915 *next_loopid = tmp_loopid; 3916 } else { 3917 /* 3918 * No retry occurred before. Just increment the 3919 * ID value for next login. 3920 */ 3921 *next_loopid = (fcport->loop_id + 1); 3922 } 3923 3924 if (mb[1] & BIT_0) { 3925 fcport->port_type = FCT_INITIATOR; 3926 } else { 3927 fcport->port_type = FCT_TARGET; 3928 if (mb[1] & BIT_1) { 3929 fcport->flags |= FCF_FCP2_DEVICE; 3930 } 3931 } 3932 3933 if (mb[10] & BIT_0) 3934 fcport->supported_classes |= FC_COS_CLASS2; 3935 if (mb[10] & BIT_1) 3936 fcport->supported_classes |= FC_COS_CLASS3; 3937 3938 if (IS_FWI2_CAPABLE(ha)) { 3939 if (mb[10] & BIT_7) 3940 fcport->flags |= 3941 FCF_CONF_COMP_SUPPORTED; 3942 } 3943 3944 rval = QLA_SUCCESS; 3945 break; 3946 } else if (mb[0] == MBS_LOOP_ID_USED) { 3947 /* 3948 * Loop ID already used, try next loop ID. 3949 */ 3950 fcport->loop_id++; 3951 rval = qla2x00_find_new_loop_id(vha, fcport); 3952 if (rval != QLA_SUCCESS) { 3953 /* Ran out of loop IDs to use */ 3954 break; 3955 } 3956 } else if (mb[0] == MBS_COMMAND_ERROR) { 3957 /* 3958 * Firmware possibly timed out during login. If NO 3959 * retries are left to do then the device is declared 3960 * dead. 3961 */ 3962 *next_loopid = fcport->loop_id; 3963 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 3964 fcport->d_id.b.domain, fcport->d_id.b.area, 3965 fcport->d_id.b.al_pa); 3966 qla2x00_mark_device_lost(vha, fcport, 1, 0); 3967 3968 rval = 1; 3969 break; 3970 } else { 3971 /* 3972 * unrecoverable / not handled error 3973 */ 3974 ql_dbg(ql_dbg_disc, vha, 0x2002, 3975 "Failed=%x port_id=%02x%02x%02x loop_id=%x " 3976 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain, 3977 fcport->d_id.b.area, fcport->d_id.b.al_pa, 3978 fcport->loop_id, jiffies); 3979 3980 *next_loopid = fcport->loop_id; 3981 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 3982 fcport->d_id.b.domain, fcport->d_id.b.area, 3983 fcport->d_id.b.al_pa); 3984 qla2x00_clear_loop_id(fcport); 3985 fcport->login_retry = 0; 3986 3987 rval = 3; 3988 break; 3989 } 3990 } 3991 3992 return (rval); 3993 } 3994 3995 /* 3996 * qla2x00_local_device_login 3997 * Issue local device login command. 3998 * 3999 * Input: 4000 * ha = adapter block pointer. 4001 * loop_id = loop id of device to login to. 4002 * 4003 * Returns (Where's the #define!!!!): 4004 * 0 - Login successfully 4005 * 1 - Login failed 4006 * 3 - Fatal error 4007 */ 4008 int 4009 qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport) 4010 { 4011 int rval; 4012 uint16_t mb[MAILBOX_REGISTER_COUNT]; 4013 4014 memset(mb, 0, sizeof(mb)); 4015 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0); 4016 if (rval == QLA_SUCCESS) { 4017 /* Interrogate mailbox registers for any errors */ 4018 if (mb[0] == MBS_COMMAND_ERROR) 4019 rval = 1; 4020 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR) 4021 /* device not in PCB table */ 4022 rval = 3; 4023 } 4024 4025 return (rval); 4026 } 4027 4028 /* 4029 * qla2x00_loop_resync 4030 * Resync with fibre channel devices. 4031 * 4032 * Input: 4033 * ha = adapter block pointer. 4034 * 4035 * Returns: 4036 * 0 = success 4037 */ 4038 int 4039 qla2x00_loop_resync(scsi_qla_host_t *vha) 4040 { 4041 int rval = QLA_SUCCESS; 4042 uint32_t wait_time; 4043 struct req_que *req; 4044 struct rsp_que *rsp; 4045 4046 if (vha->hw->flags.cpu_affinity_enabled) 4047 req = vha->hw->req_q_map[0]; 4048 else 4049 req = vha->req; 4050 rsp = req->rsp; 4051 4052 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 4053 if (vha->flags.online) { 4054 if (!(rval = qla2x00_fw_ready(vha))) { 4055 /* Wait at most MAX_TARGET RSCNs for a stable link. */ 4056 wait_time = 256; 4057 do { 4058 if (!IS_QLAFX00(vha->hw)) { 4059 /* 4060 * Issue a marker after FW becomes 4061 * ready. 4062 */ 4063 qla2x00_marker(vha, req, rsp, 0, 0, 4064 MK_SYNC_ALL); 4065 vha->marker_needed = 0; 4066 } 4067 4068 /* Remap devices on Loop. */ 4069 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 4070 4071 if (IS_QLAFX00(vha->hw)) 4072 qlafx00_configure_devices(vha); 4073 else 4074 qla2x00_configure_loop(vha); 4075 4076 wait_time--; 4077 } while (!atomic_read(&vha->loop_down_timer) && 4078 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 4079 && wait_time && (test_bit(LOOP_RESYNC_NEEDED, 4080 &vha->dpc_flags))); 4081 } 4082 } 4083 4084 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 4085 return (QLA_FUNCTION_FAILED); 4086 4087 if (rval) 4088 ql_dbg(ql_dbg_disc, vha, 0x206c, 4089 "%s *** FAILED ***.\n", __func__); 4090 4091 return (rval); 4092 } 4093 4094 /* 4095 * qla2x00_perform_loop_resync 4096 * Description: This function will set the appropriate flags and call 4097 * qla2x00_loop_resync. If successful loop will be resynced 4098 * Arguments : scsi_qla_host_t pointer 4099 * returm : Success or Failure 4100 */ 4101 4102 int qla2x00_perform_loop_resync(scsi_qla_host_t *ha) 4103 { 4104 int32_t rval = 0; 4105 4106 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) { 4107 /*Configure the flags so that resync happens properly*/ 4108 atomic_set(&ha->loop_down_timer, 0); 4109 if (!(ha->device_flags & DFLG_NO_CABLE)) { 4110 atomic_set(&ha->loop_state, LOOP_UP); 4111 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); 4112 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); 4113 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); 4114 4115 rval = qla2x00_loop_resync(ha); 4116 } else 4117 atomic_set(&ha->loop_state, LOOP_DEAD); 4118 4119 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags); 4120 } 4121 4122 return rval; 4123 } 4124 4125 void 4126 qla2x00_update_fcports(scsi_qla_host_t *base_vha) 4127 { 4128 fc_port_t *fcport; 4129 struct scsi_qla_host *vha; 4130 struct qla_hw_data *ha = base_vha->hw; 4131 unsigned long flags; 4132 4133 spin_lock_irqsave(&ha->vport_slock, flags); 4134 /* Go with deferred removal of rport references. */ 4135 list_for_each_entry(vha, &base_vha->hw->vp_list, list) { 4136 atomic_inc(&vha->vref_count); 4137 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4138 if (fcport->drport && 4139 atomic_read(&fcport->state) != FCS_UNCONFIGURED) { 4140 spin_unlock_irqrestore(&ha->vport_slock, flags); 4141 qla2x00_rport_del(fcport); 4142 spin_lock_irqsave(&ha->vport_slock, flags); 4143 } 4144 } 4145 atomic_dec(&vha->vref_count); 4146 } 4147 spin_unlock_irqrestore(&ha->vport_slock, flags); 4148 } 4149 4150 /* Assumes idc_lock always held on entry */ 4151 void 4152 qla83xx_reset_ownership(scsi_qla_host_t *vha) 4153 { 4154 struct qla_hw_data *ha = vha->hw; 4155 uint32_t drv_presence, drv_presence_mask; 4156 uint32_t dev_part_info1, dev_part_info2, class_type; 4157 uint32_t class_type_mask = 0x3; 4158 uint16_t fcoe_other_function = 0xffff, i; 4159 4160 if (IS_QLA8044(ha)) { 4161 drv_presence = qla8044_rd_direct(vha, 4162 QLA8044_CRB_DRV_ACTIVE_INDEX); 4163 dev_part_info1 = qla8044_rd_direct(vha, 4164 QLA8044_CRB_DEV_PART_INFO_INDEX); 4165 dev_part_info2 = qla8044_rd_direct(vha, 4166 QLA8044_CRB_DEV_PART_INFO2); 4167 } else { 4168 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4169 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1); 4170 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2); 4171 } 4172 for (i = 0; i < 8; i++) { 4173 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask); 4174 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 4175 (i != ha->portnum)) { 4176 fcoe_other_function = i; 4177 break; 4178 } 4179 } 4180 if (fcoe_other_function == 0xffff) { 4181 for (i = 0; i < 8; i++) { 4182 class_type = ((dev_part_info2 >> (i * 4)) & 4183 class_type_mask); 4184 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 4185 ((i + 8) != ha->portnum)) { 4186 fcoe_other_function = i + 8; 4187 break; 4188 } 4189 } 4190 } 4191 /* 4192 * Prepare drv-presence mask based on fcoe functions present. 4193 * However consider only valid physical fcoe function numbers (0-15). 4194 */ 4195 drv_presence_mask = ~((1 << (ha->portnum)) | 4196 ((fcoe_other_function == 0xffff) ? 4197 0 : (1 << (fcoe_other_function)))); 4198 4199 /* We are the reset owner iff: 4200 * - No other protocol drivers present. 4201 * - This is the lowest among fcoe functions. */ 4202 if (!(drv_presence & drv_presence_mask) && 4203 (ha->portnum < fcoe_other_function)) { 4204 ql_dbg(ql_dbg_p3p, vha, 0xb07f, 4205 "This host is Reset owner.\n"); 4206 ha->flags.nic_core_reset_owner = 1; 4207 } 4208 } 4209 4210 static int 4211 __qla83xx_set_drv_ack(scsi_qla_host_t *vha) 4212 { 4213 int rval = QLA_SUCCESS; 4214 struct qla_hw_data *ha = vha->hw; 4215 uint32_t drv_ack; 4216 4217 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4218 if (rval == QLA_SUCCESS) { 4219 drv_ack |= (1 << ha->portnum); 4220 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 4221 } 4222 4223 return rval; 4224 } 4225 4226 static int 4227 __qla83xx_clear_drv_ack(scsi_qla_host_t *vha) 4228 { 4229 int rval = QLA_SUCCESS; 4230 struct qla_hw_data *ha = vha->hw; 4231 uint32_t drv_ack; 4232 4233 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 4234 if (rval == QLA_SUCCESS) { 4235 drv_ack &= ~(1 << ha->portnum); 4236 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 4237 } 4238 4239 return rval; 4240 } 4241 4242 static const char * 4243 qla83xx_dev_state_to_string(uint32_t dev_state) 4244 { 4245 switch (dev_state) { 4246 case QLA8XXX_DEV_COLD: 4247 return "COLD/RE-INIT"; 4248 case QLA8XXX_DEV_INITIALIZING: 4249 return "INITIALIZING"; 4250 case QLA8XXX_DEV_READY: 4251 return "READY"; 4252 case QLA8XXX_DEV_NEED_RESET: 4253 return "NEED RESET"; 4254 case QLA8XXX_DEV_NEED_QUIESCENT: 4255 return "NEED QUIESCENT"; 4256 case QLA8XXX_DEV_FAILED: 4257 return "FAILED"; 4258 case QLA8XXX_DEV_QUIESCENT: 4259 return "QUIESCENT"; 4260 default: 4261 return "Unknown"; 4262 } 4263 } 4264 4265 /* Assumes idc-lock always held on entry */ 4266 void 4267 qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type) 4268 { 4269 struct qla_hw_data *ha = vha->hw; 4270 uint32_t idc_audit_reg = 0, duration_secs = 0; 4271 4272 switch (audit_type) { 4273 case IDC_AUDIT_TIMESTAMP: 4274 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000); 4275 idc_audit_reg = (ha->portnum) | 4276 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8); 4277 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 4278 break; 4279 4280 case IDC_AUDIT_COMPLETION: 4281 duration_secs = ((jiffies_to_msecs(jiffies) - 4282 jiffies_to_msecs(ha->idc_audit_ts)) / 1000); 4283 idc_audit_reg = (ha->portnum) | 4284 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8); 4285 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 4286 break; 4287 4288 default: 4289 ql_log(ql_log_warn, vha, 0xb078, 4290 "Invalid audit type specified.\n"); 4291 break; 4292 } 4293 } 4294 4295 /* Assumes idc_lock always held on entry */ 4296 static int 4297 qla83xx_initiating_reset(scsi_qla_host_t *vha) 4298 { 4299 struct qla_hw_data *ha = vha->hw; 4300 uint32_t idc_control, dev_state; 4301 4302 __qla83xx_get_idc_control(vha, &idc_control); 4303 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) { 4304 ql_log(ql_log_info, vha, 0xb080, 4305 "NIC Core reset has been disabled. idc-control=0x%x\n", 4306 idc_control); 4307 return QLA_FUNCTION_FAILED; 4308 } 4309 4310 /* Set NEED-RESET iff in READY state and we are the reset-owner */ 4311 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4312 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) { 4313 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 4314 QLA8XXX_DEV_NEED_RESET); 4315 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n"); 4316 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP); 4317 } else { 4318 const char *state = qla83xx_dev_state_to_string(dev_state); 4319 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state); 4320 4321 /* SV: XXX: Is timeout required here? */ 4322 /* Wait for IDC state change READY -> NEED_RESET */ 4323 while (dev_state == QLA8XXX_DEV_READY) { 4324 qla83xx_idc_unlock(vha, 0); 4325 msleep(200); 4326 qla83xx_idc_lock(vha, 0); 4327 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 4328 } 4329 } 4330 4331 /* Send IDC ack by writing to drv-ack register */ 4332 __qla83xx_set_drv_ack(vha); 4333 4334 return QLA_SUCCESS; 4335 } 4336 4337 int 4338 __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) 4339 { 4340 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 4341 } 4342 4343 int 4344 __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) 4345 { 4346 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 4347 } 4348 4349 static int 4350 qla83xx_check_driver_presence(scsi_qla_host_t *vha) 4351 { 4352 uint32_t drv_presence = 0; 4353 struct qla_hw_data *ha = vha->hw; 4354 4355 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 4356 if (drv_presence & (1 << ha->portnum)) 4357 return QLA_SUCCESS; 4358 else 4359 return QLA_TEST_FAILED; 4360 } 4361 4362 int 4363 qla83xx_nic_core_reset(scsi_qla_host_t *vha) 4364 { 4365 int rval = QLA_SUCCESS; 4366 struct qla_hw_data *ha = vha->hw; 4367 4368 ql_dbg(ql_dbg_p3p, vha, 0xb058, 4369 "Entered %s().\n", __func__); 4370 4371 if (vha->device_flags & DFLG_DEV_FAILED) { 4372 ql_log(ql_log_warn, vha, 0xb059, 4373 "Device in unrecoverable FAILED state.\n"); 4374 return QLA_FUNCTION_FAILED; 4375 } 4376 4377 qla83xx_idc_lock(vha, 0); 4378 4379 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) { 4380 ql_log(ql_log_warn, vha, 0xb05a, 4381 "Function=0x%x has been removed from IDC participation.\n", 4382 ha->portnum); 4383 rval = QLA_FUNCTION_FAILED; 4384 goto exit; 4385 } 4386 4387 qla83xx_reset_ownership(vha); 4388 4389 rval = qla83xx_initiating_reset(vha); 4390 4391 /* 4392 * Perform reset if we are the reset-owner, 4393 * else wait till IDC state changes to READY/FAILED. 4394 */ 4395 if (rval == QLA_SUCCESS) { 4396 rval = qla83xx_idc_state_handler(vha); 4397 4398 if (rval == QLA_SUCCESS) 4399 ha->flags.nic_core_hung = 0; 4400 __qla83xx_clear_drv_ack(vha); 4401 } 4402 4403 exit: 4404 qla83xx_idc_unlock(vha, 0); 4405 4406 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__); 4407 4408 return rval; 4409 } 4410 4411 int 4412 qla2xxx_mctp_dump(scsi_qla_host_t *vha) 4413 { 4414 struct qla_hw_data *ha = vha->hw; 4415 int rval = QLA_FUNCTION_FAILED; 4416 4417 if (!IS_MCTP_CAPABLE(ha)) { 4418 /* This message can be removed from the final version */ 4419 ql_log(ql_log_info, vha, 0x506d, 4420 "This board is not MCTP capable\n"); 4421 return rval; 4422 } 4423 4424 if (!ha->mctp_dump) { 4425 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev, 4426 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL); 4427 4428 if (!ha->mctp_dump) { 4429 ql_log(ql_log_warn, vha, 0x506e, 4430 "Failed to allocate memory for mctp dump\n"); 4431 return rval; 4432 } 4433 } 4434 4435 #define MCTP_DUMP_STR_ADDR 0x00000000 4436 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma, 4437 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4); 4438 if (rval != QLA_SUCCESS) { 4439 ql_log(ql_log_warn, vha, 0x506f, 4440 "Failed to capture mctp dump\n"); 4441 } else { 4442 ql_log(ql_log_info, vha, 0x5070, 4443 "Mctp dump capture for host (%ld/%p).\n", 4444 vha->host_no, ha->mctp_dump); 4445 ha->mctp_dumped = 1; 4446 } 4447 4448 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) { 4449 ha->flags.nic_core_reset_hdlr_active = 1; 4450 rval = qla83xx_restart_nic_firmware(vha); 4451 if (rval) 4452 /* NIC Core reset failed. */ 4453 ql_log(ql_log_warn, vha, 0x5071, 4454 "Failed to restart nic firmware\n"); 4455 else 4456 ql_dbg(ql_dbg_p3p, vha, 0xb084, 4457 "Restarted NIC firmware successfully.\n"); 4458 ha->flags.nic_core_reset_hdlr_active = 0; 4459 } 4460 4461 return rval; 4462 4463 } 4464 4465 /* 4466 * qla2x00_quiesce_io 4467 * Description: This function will block the new I/Os 4468 * Its not aborting any I/Os as context 4469 * is not destroyed during quiescence 4470 * Arguments: scsi_qla_host_t 4471 * return : void 4472 */ 4473 void 4474 qla2x00_quiesce_io(scsi_qla_host_t *vha) 4475 { 4476 struct qla_hw_data *ha = vha->hw; 4477 struct scsi_qla_host *vp; 4478 4479 ql_dbg(ql_dbg_dpc, vha, 0x401d, 4480 "Quiescing I/O - ha=%p.\n", ha); 4481 4482 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); 4483 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 4484 atomic_set(&vha->loop_state, LOOP_DOWN); 4485 qla2x00_mark_all_devices_lost(vha, 0); 4486 list_for_each_entry(vp, &ha->vp_list, list) 4487 qla2x00_mark_all_devices_lost(vp, 0); 4488 } else { 4489 if (!atomic_read(&vha->loop_down_timer)) 4490 atomic_set(&vha->loop_down_timer, 4491 LOOP_DOWN_TIME); 4492 } 4493 /* Wait for pending cmds to complete */ 4494 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST); 4495 } 4496 4497 void 4498 qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) 4499 { 4500 struct qla_hw_data *ha = vha->hw; 4501 struct scsi_qla_host *vp; 4502 unsigned long flags; 4503 fc_port_t *fcport; 4504 4505 /* For ISP82XX, driver waits for completion of the commands. 4506 * online flag should be set. 4507 */ 4508 if (!(IS_P3P_TYPE(ha))) 4509 vha->flags.online = 0; 4510 ha->flags.chip_reset_done = 0; 4511 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 4512 vha->qla_stats.total_isp_aborts++; 4513 4514 ql_log(ql_log_info, vha, 0x00af, 4515 "Performing ISP error recovery - ha=%p.\n", ha); 4516 4517 /* For ISP82XX, reset_chip is just disabling interrupts. 4518 * Driver waits for the completion of the commands. 4519 * the interrupts need to be enabled. 4520 */ 4521 if (!(IS_P3P_TYPE(ha))) 4522 ha->isp_ops->reset_chip(vha); 4523 4524 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 4525 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 4526 atomic_set(&vha->loop_state, LOOP_DOWN); 4527 qla2x00_mark_all_devices_lost(vha, 0); 4528 4529 spin_lock_irqsave(&ha->vport_slock, flags); 4530 list_for_each_entry(vp, &ha->vp_list, list) { 4531 atomic_inc(&vp->vref_count); 4532 spin_unlock_irqrestore(&ha->vport_slock, flags); 4533 4534 qla2x00_mark_all_devices_lost(vp, 0); 4535 4536 spin_lock_irqsave(&ha->vport_slock, flags); 4537 atomic_dec(&vp->vref_count); 4538 } 4539 spin_unlock_irqrestore(&ha->vport_slock, flags); 4540 } else { 4541 if (!atomic_read(&vha->loop_down_timer)) 4542 atomic_set(&vha->loop_down_timer, 4543 LOOP_DOWN_TIME); 4544 } 4545 4546 /* Clear all async request states across all VPs. */ 4547 list_for_each_entry(fcport, &vha->vp_fcports, list) 4548 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 4549 spin_lock_irqsave(&ha->vport_slock, flags); 4550 list_for_each_entry(vp, &ha->vp_list, list) { 4551 atomic_inc(&vp->vref_count); 4552 spin_unlock_irqrestore(&ha->vport_slock, flags); 4553 4554 list_for_each_entry(fcport, &vp->vp_fcports, list) 4555 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 4556 4557 spin_lock_irqsave(&ha->vport_slock, flags); 4558 atomic_dec(&vp->vref_count); 4559 } 4560 spin_unlock_irqrestore(&ha->vport_slock, flags); 4561 4562 if (!ha->flags.eeh_busy) { 4563 /* Make sure for ISP 82XX IO DMA is complete */ 4564 if (IS_P3P_TYPE(ha)) { 4565 qla82xx_chip_reset_cleanup(vha); 4566 ql_log(ql_log_info, vha, 0x00b4, 4567 "Done chip reset cleanup.\n"); 4568 4569 /* Done waiting for pending commands. 4570 * Reset the online flag. 4571 */ 4572 vha->flags.online = 0; 4573 } 4574 4575 /* Requeue all commands in outstanding command list. */ 4576 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 4577 } 4578 4579 ha->chip_reset++; 4580 /* memory barrier */ 4581 wmb(); 4582 } 4583 4584 /* 4585 * qla2x00_abort_isp 4586 * Resets ISP and aborts all outstanding commands. 4587 * 4588 * Input: 4589 * ha = adapter block pointer. 4590 * 4591 * Returns: 4592 * 0 = success 4593 */ 4594 int 4595 qla2x00_abort_isp(scsi_qla_host_t *vha) 4596 { 4597 int rval; 4598 uint8_t status = 0; 4599 struct qla_hw_data *ha = vha->hw; 4600 struct scsi_qla_host *vp; 4601 struct req_que *req = ha->req_q_map[0]; 4602 unsigned long flags; 4603 4604 if (vha->flags.online) { 4605 qla2x00_abort_isp_cleanup(vha); 4606 4607 if (IS_QLA8031(ha)) { 4608 ql_dbg(ql_dbg_p3p, vha, 0xb05c, 4609 "Clearing fcoe driver presence.\n"); 4610 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS) 4611 ql_dbg(ql_dbg_p3p, vha, 0xb073, 4612 "Error while clearing DRV-Presence.\n"); 4613 } 4614 4615 if (unlikely(pci_channel_offline(ha->pdev) && 4616 ha->flags.pci_channel_io_perm_failure)) { 4617 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 4618 status = 0; 4619 return status; 4620 } 4621 4622 ha->isp_ops->get_flash_version(vha, req->ring); 4623 4624 ha->isp_ops->nvram_config(vha); 4625 4626 if (!qla2x00_restart_isp(vha)) { 4627 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 4628 4629 if (!atomic_read(&vha->loop_down_timer)) { 4630 /* 4631 * Issue marker command only when we are going 4632 * to start the I/O . 4633 */ 4634 vha->marker_needed = 1; 4635 } 4636 4637 vha->flags.online = 1; 4638 4639 ha->isp_ops->enable_intrs(ha); 4640 4641 ha->isp_abort_cnt = 0; 4642 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 4643 4644 if (IS_QLA81XX(ha) || IS_QLA8031(ha)) 4645 qla2x00_get_fw_version(vha); 4646 if (ha->fce) { 4647 ha->flags.fce_enabled = 1; 4648 memset(ha->fce, 0, 4649 fce_calc_size(ha->fce_bufs)); 4650 rval = qla2x00_enable_fce_trace(vha, 4651 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 4652 &ha->fce_bufs); 4653 if (rval) { 4654 ql_log(ql_log_warn, vha, 0x8033, 4655 "Unable to reinitialize FCE " 4656 "(%d).\n", rval); 4657 ha->flags.fce_enabled = 0; 4658 } 4659 } 4660 4661 if (ha->eft) { 4662 memset(ha->eft, 0, EFT_SIZE); 4663 rval = qla2x00_enable_eft_trace(vha, 4664 ha->eft_dma, EFT_NUM_BUFFERS); 4665 if (rval) { 4666 ql_log(ql_log_warn, vha, 0x8034, 4667 "Unable to reinitialize EFT " 4668 "(%d).\n", rval); 4669 } 4670 } 4671 } else { /* failed the ISP abort */ 4672 vha->flags.online = 1; 4673 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 4674 if (ha->isp_abort_cnt == 0) { 4675 ql_log(ql_log_fatal, vha, 0x8035, 4676 "ISP error recover failed - " 4677 "board disabled.\n"); 4678 /* 4679 * The next call disables the board 4680 * completely. 4681 */ 4682 ha->isp_ops->reset_adapter(vha); 4683 vha->flags.online = 0; 4684 clear_bit(ISP_ABORT_RETRY, 4685 &vha->dpc_flags); 4686 status = 0; 4687 } else { /* schedule another ISP abort */ 4688 ha->isp_abort_cnt--; 4689 ql_dbg(ql_dbg_taskm, vha, 0x8020, 4690 "ISP abort - retry remaining %d.\n", 4691 ha->isp_abort_cnt); 4692 status = 1; 4693 } 4694 } else { 4695 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 4696 ql_dbg(ql_dbg_taskm, vha, 0x8021, 4697 "ISP error recovery - retrying (%d) " 4698 "more times.\n", ha->isp_abort_cnt); 4699 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 4700 status = 1; 4701 } 4702 } 4703 4704 } 4705 4706 if (!status) { 4707 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__); 4708 4709 spin_lock_irqsave(&ha->vport_slock, flags); 4710 list_for_each_entry(vp, &ha->vp_list, list) { 4711 if (vp->vp_idx) { 4712 atomic_inc(&vp->vref_count); 4713 spin_unlock_irqrestore(&ha->vport_slock, flags); 4714 4715 qla2x00_vp_abort_isp(vp); 4716 4717 spin_lock_irqsave(&ha->vport_slock, flags); 4718 atomic_dec(&vp->vref_count); 4719 } 4720 } 4721 spin_unlock_irqrestore(&ha->vport_slock, flags); 4722 4723 if (IS_QLA8031(ha)) { 4724 ql_dbg(ql_dbg_p3p, vha, 0xb05d, 4725 "Setting back fcoe driver presence.\n"); 4726 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS) 4727 ql_dbg(ql_dbg_p3p, vha, 0xb074, 4728 "Error while setting DRV-Presence.\n"); 4729 } 4730 } else { 4731 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n", 4732 __func__); 4733 } 4734 4735 return(status); 4736 } 4737 4738 /* 4739 * qla2x00_restart_isp 4740 * restarts the ISP after a reset 4741 * 4742 * Input: 4743 * ha = adapter block pointer. 4744 * 4745 * Returns: 4746 * 0 = success 4747 */ 4748 static int 4749 qla2x00_restart_isp(scsi_qla_host_t *vha) 4750 { 4751 int status = 0; 4752 struct qla_hw_data *ha = vha->hw; 4753 struct req_que *req = ha->req_q_map[0]; 4754 struct rsp_que *rsp = ha->rsp_q_map[0]; 4755 unsigned long flags; 4756 4757 /* If firmware needs to be loaded */ 4758 if (qla2x00_isp_firmware(vha)) { 4759 vha->flags.online = 0; 4760 status = ha->isp_ops->chip_diag(vha); 4761 if (!status) 4762 status = qla2x00_setup_chip(vha); 4763 } 4764 4765 if (!status && !(status = qla2x00_init_rings(vha))) { 4766 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 4767 ha->flags.chip_reset_done = 1; 4768 4769 /* Initialize the queues in use */ 4770 qla25xx_init_queues(ha); 4771 4772 status = qla2x00_fw_ready(vha); 4773 if (!status) { 4774 /* Issue a marker after FW becomes ready. */ 4775 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); 4776 4777 vha->flags.online = 1; 4778 4779 /* 4780 * Process any ATIO queue entries that came in 4781 * while we weren't online. 4782 */ 4783 spin_lock_irqsave(&ha->hardware_lock, flags); 4784 if (qla_tgt_mode_enabled(vha)) 4785 qlt_24xx_process_atio_queue(vha); 4786 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4787 4788 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 4789 } 4790 4791 /* if no cable then assume it's good */ 4792 if ((vha->device_flags & DFLG_NO_CABLE)) 4793 status = 0; 4794 } 4795 return (status); 4796 } 4797 4798 static int 4799 qla25xx_init_queues(struct qla_hw_data *ha) 4800 { 4801 struct rsp_que *rsp = NULL; 4802 struct req_que *req = NULL; 4803 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 4804 int ret = -1; 4805 int i; 4806 4807 for (i = 1; i < ha->max_rsp_queues; i++) { 4808 rsp = ha->rsp_q_map[i]; 4809 if (rsp) { 4810 rsp->options &= ~BIT_0; 4811 ret = qla25xx_init_rsp_que(base_vha, rsp); 4812 if (ret != QLA_SUCCESS) 4813 ql_dbg(ql_dbg_init, base_vha, 0x00ff, 4814 "%s Rsp que: %d init failed.\n", 4815 __func__, rsp->id); 4816 else 4817 ql_dbg(ql_dbg_init, base_vha, 0x0100, 4818 "%s Rsp que: %d inited.\n", 4819 __func__, rsp->id); 4820 } 4821 } 4822 for (i = 1; i < ha->max_req_queues; i++) { 4823 req = ha->req_q_map[i]; 4824 if (req) { 4825 /* Clear outstanding commands array. */ 4826 req->options &= ~BIT_0; 4827 ret = qla25xx_init_req_que(base_vha, req); 4828 if (ret != QLA_SUCCESS) 4829 ql_dbg(ql_dbg_init, base_vha, 0x0101, 4830 "%s Req que: %d init failed.\n", 4831 __func__, req->id); 4832 else 4833 ql_dbg(ql_dbg_init, base_vha, 0x0102, 4834 "%s Req que: %d inited.\n", 4835 __func__, req->id); 4836 } 4837 } 4838 return ret; 4839 } 4840 4841 /* 4842 * qla2x00_reset_adapter 4843 * Reset adapter. 4844 * 4845 * Input: 4846 * ha = adapter block pointer. 4847 */ 4848 void 4849 qla2x00_reset_adapter(scsi_qla_host_t *vha) 4850 { 4851 unsigned long flags = 0; 4852 struct qla_hw_data *ha = vha->hw; 4853 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4854 4855 vha->flags.online = 0; 4856 ha->isp_ops->disable_intrs(ha); 4857 4858 spin_lock_irqsave(&ha->hardware_lock, flags); 4859 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); 4860 RD_REG_WORD(®->hccr); /* PCI Posting. */ 4861 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 4862 RD_REG_WORD(®->hccr); /* PCI Posting. */ 4863 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4864 } 4865 4866 void 4867 qla24xx_reset_adapter(scsi_qla_host_t *vha) 4868 { 4869 unsigned long flags = 0; 4870 struct qla_hw_data *ha = vha->hw; 4871 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 4872 4873 if (IS_P3P_TYPE(ha)) 4874 return; 4875 4876 vha->flags.online = 0; 4877 ha->isp_ops->disable_intrs(ha); 4878 4879 spin_lock_irqsave(&ha->hardware_lock, flags); 4880 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); 4881 RD_REG_DWORD(®->hccr); 4882 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); 4883 RD_REG_DWORD(®->hccr); 4884 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4885 4886 if (IS_NOPOLLING_TYPE(ha)) 4887 ha->isp_ops->enable_intrs(ha); 4888 } 4889 4890 /* On sparc systems, obtain port and node WWN from firmware 4891 * properties. 4892 */ 4893 static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, 4894 struct nvram_24xx *nv) 4895 { 4896 #ifdef CONFIG_SPARC 4897 struct qla_hw_data *ha = vha->hw; 4898 struct pci_dev *pdev = ha->pdev; 4899 struct device_node *dp = pci_device_to_OF_node(pdev); 4900 const u8 *val; 4901 int len; 4902 4903 val = of_get_property(dp, "port-wwn", &len); 4904 if (val && len >= WWN_SIZE) 4905 memcpy(nv->port_name, val, WWN_SIZE); 4906 4907 val = of_get_property(dp, "node-wwn", &len); 4908 if (val && len >= WWN_SIZE) 4909 memcpy(nv->node_name, val, WWN_SIZE); 4910 #endif 4911 } 4912 4913 int 4914 qla24xx_nvram_config(scsi_qla_host_t *vha) 4915 { 4916 int rval; 4917 struct init_cb_24xx *icb; 4918 struct nvram_24xx *nv; 4919 uint32_t *dptr; 4920 uint8_t *dptr1, *dptr2; 4921 uint32_t chksum; 4922 uint16_t cnt; 4923 struct qla_hw_data *ha = vha->hw; 4924 4925 rval = QLA_SUCCESS; 4926 icb = (struct init_cb_24xx *)ha->init_cb; 4927 nv = ha->nvram; 4928 4929 /* Determine NVRAM starting address. */ 4930 if (ha->port_no == 0) { 4931 ha->nvram_base = FA_NVRAM_FUNC0_ADDR; 4932 ha->vpd_base = FA_NVRAM_VPD0_ADDR; 4933 } else { 4934 ha->nvram_base = FA_NVRAM_FUNC1_ADDR; 4935 ha->vpd_base = FA_NVRAM_VPD1_ADDR; 4936 } 4937 4938 ha->nvram_size = sizeof(struct nvram_24xx); 4939 ha->vpd_size = FA_NVRAM_VPD_SIZE; 4940 4941 /* Get VPD data into cache */ 4942 ha->vpd = ha->nvram + VPD_OFFSET; 4943 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd, 4944 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4); 4945 4946 /* Get NVRAM data into cache and calculate checksum. */ 4947 dptr = (uint32_t *)nv; 4948 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base, 4949 ha->nvram_size); 4950 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) 4951 chksum += le32_to_cpu(*dptr++); 4952 4953 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a, 4954 "Contents of NVRAM\n"); 4955 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d, 4956 (uint8_t *)nv, ha->nvram_size); 4957 4958 /* Bad NVRAM data, set defaults parameters. */ 4959 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' 4960 || nv->id[3] != ' ' || 4961 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) { 4962 /* Reset NVRAM data. */ 4963 ql_log(ql_log_warn, vha, 0x006b, 4964 "Inconsistent NVRAM detected: checksum=0x%x id=%c " 4965 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version); 4966 ql_log(ql_log_warn, vha, 0x006c, 4967 "Falling back to functioning (yet invalid -- WWPN) " 4968 "defaults.\n"); 4969 4970 /* 4971 * Set default initialization control block. 4972 */ 4973 memset(nv, 0, ha->nvram_size); 4974 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION); 4975 nv->version = __constant_cpu_to_le16(ICB_VERSION); 4976 nv->frame_payload_size = 2048; 4977 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF); 4978 nv->exchange_count = __constant_cpu_to_le16(0); 4979 nv->hard_address = __constant_cpu_to_le16(124); 4980 nv->port_name[0] = 0x21; 4981 nv->port_name[1] = 0x00 + ha->port_no + 1; 4982 nv->port_name[2] = 0x00; 4983 nv->port_name[3] = 0xe0; 4984 nv->port_name[4] = 0x8b; 4985 nv->port_name[5] = 0x1c; 4986 nv->port_name[6] = 0x55; 4987 nv->port_name[7] = 0x86; 4988 nv->node_name[0] = 0x20; 4989 nv->node_name[1] = 0x00; 4990 nv->node_name[2] = 0x00; 4991 nv->node_name[3] = 0xe0; 4992 nv->node_name[4] = 0x8b; 4993 nv->node_name[5] = 0x1c; 4994 nv->node_name[6] = 0x55; 4995 nv->node_name[7] = 0x86; 4996 qla24xx_nvram_wwn_from_ofw(vha, nv); 4997 nv->login_retry_count = __constant_cpu_to_le16(8); 4998 nv->interrupt_delay_timer = __constant_cpu_to_le16(0); 4999 nv->login_timeout = __constant_cpu_to_le16(0); 5000 nv->firmware_options_1 = 5001 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 5002 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4); 5003 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12); 5004 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13); 5005 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10); 5006 nv->efi_parameters = __constant_cpu_to_le32(0); 5007 nv->reset_delay = 5; 5008 nv->max_luns_per_target = __constant_cpu_to_le16(128); 5009 nv->port_down_retry_count = __constant_cpu_to_le16(30); 5010 nv->link_down_timeout = __constant_cpu_to_le16(30); 5011 5012 rval = 1; 5013 } 5014 5015 if (!qla_ini_mode_enabled(vha)) { 5016 /* Don't enable full login after initial LIP */ 5017 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13); 5018 /* Don't enable LIP full login for initiator */ 5019 nv->host_p &= __constant_cpu_to_le32(~BIT_10); 5020 } 5021 5022 qlt_24xx_config_nvram_stage1(vha, nv); 5023 5024 /* Reset Initialization control block */ 5025 memset(icb, 0, ha->init_cb_size); 5026 5027 /* Copy 1st segment. */ 5028 dptr1 = (uint8_t *)icb; 5029 dptr2 = (uint8_t *)&nv->version; 5030 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 5031 while (cnt--) 5032 *dptr1++ = *dptr2++; 5033 5034 icb->login_retry_count = nv->login_retry_count; 5035 icb->link_down_on_nos = nv->link_down_on_nos; 5036 5037 /* Copy 2nd segment. */ 5038 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 5039 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 5040 cnt = (uint8_t *)&icb->reserved_3 - 5041 (uint8_t *)&icb->interrupt_delay_timer; 5042 while (cnt--) 5043 *dptr1++ = *dptr2++; 5044 5045 /* 5046 * Setup driver NVRAM options. 5047 */ 5048 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 5049 "QLA2462"); 5050 5051 qlt_24xx_config_nvram_stage2(vha, icb); 5052 5053 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) { 5054 /* Use alternate WWN? */ 5055 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 5056 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 5057 } 5058 5059 /* Prepare nodename */ 5060 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) { 5061 /* 5062 * Firmware will apply the following mask if the nodename was 5063 * not provided. 5064 */ 5065 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 5066 icb->node_name[0] &= 0xF0; 5067 } 5068 5069 /* Set host adapter parameters. */ 5070 ha->flags.disable_risc_code_load = 0; 5071 ha->flags.enable_lip_reset = 0; 5072 ha->flags.enable_lip_full_login = 5073 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; 5074 ha->flags.enable_target_reset = 5075 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; 5076 ha->flags.enable_led_scheme = 0; 5077 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; 5078 5079 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 5080 (BIT_6 | BIT_5 | BIT_4)) >> 4; 5081 5082 memcpy(ha->fw_seriallink_options24, nv->seriallink_options, 5083 sizeof(ha->fw_seriallink_options24)); 5084 5085 /* save HBA serial number */ 5086 ha->serial0 = icb->port_name[5]; 5087 ha->serial1 = icb->port_name[6]; 5088 ha->serial2 = icb->port_name[7]; 5089 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 5090 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 5091 5092 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); 5093 5094 ha->retry_count = le16_to_cpu(nv->login_retry_count); 5095 5096 /* Set minimum login_timeout to 4 seconds. */ 5097 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 5098 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 5099 if (le16_to_cpu(nv->login_timeout) < 4) 5100 nv->login_timeout = __constant_cpu_to_le16(4); 5101 ha->login_timeout = le16_to_cpu(nv->login_timeout); 5102 icb->login_timeout = nv->login_timeout; 5103 5104 /* Set minimum RATOV to 100 tenths of a second. */ 5105 ha->r_a_tov = 100; 5106 5107 ha->loop_reset_delay = nv->reset_delay; 5108 5109 /* Link Down Timeout = 0: 5110 * 5111 * When Port Down timer expires we will start returning 5112 * I/O's to OS with "DID_NO_CONNECT". 5113 * 5114 * Link Down Timeout != 0: 5115 * 5116 * The driver waits for the link to come up after link down 5117 * before returning I/Os to OS with "DID_NO_CONNECT". 5118 */ 5119 if (le16_to_cpu(nv->link_down_timeout) == 0) { 5120 ha->loop_down_abort_time = 5121 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 5122 } else { 5123 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 5124 ha->loop_down_abort_time = 5125 (LOOP_DOWN_TIME - ha->link_down_timeout); 5126 } 5127 5128 /* Need enough time to try and get the port back. */ 5129 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 5130 if (qlport_down_retry) 5131 ha->port_down_retry_count = qlport_down_retry; 5132 5133 /* Set login_retry_count */ 5134 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 5135 if (ha->port_down_retry_count == 5136 le16_to_cpu(nv->port_down_retry_count) && 5137 ha->port_down_retry_count > 3) 5138 ha->login_retry_count = ha->port_down_retry_count; 5139 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 5140 ha->login_retry_count = ha->port_down_retry_count; 5141 if (ql2xloginretrycount) 5142 ha->login_retry_count = ql2xloginretrycount; 5143 5144 /* Enable ZIO. */ 5145 if (!vha->flags.init_done) { 5146 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 5147 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 5148 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 5149 le16_to_cpu(icb->interrupt_delay_timer): 2; 5150 } 5151 icb->firmware_options_2 &= __constant_cpu_to_le32( 5152 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 5153 vha->flags.process_response_queue = 0; 5154 if (ha->zio_mode != QLA_ZIO_DISABLED) { 5155 ha->zio_mode = QLA_ZIO_MODE_6; 5156 5157 ql_log(ql_log_info, vha, 0x006f, 5158 "ZIO mode %d enabled; timer delay (%d us).\n", 5159 ha->zio_mode, ha->zio_timer * 100); 5160 5161 icb->firmware_options_2 |= cpu_to_le32( 5162 (uint32_t)ha->zio_mode); 5163 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 5164 vha->flags.process_response_queue = 1; 5165 } 5166 5167 if (rval) { 5168 ql_log(ql_log_warn, vha, 0x0070, 5169 "NVRAM configuration failed.\n"); 5170 } 5171 return (rval); 5172 } 5173 5174 static int 5175 qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, 5176 uint32_t faddr) 5177 { 5178 int rval = QLA_SUCCESS; 5179 int segments, fragment; 5180 uint32_t *dcode, dlen; 5181 uint32_t risc_addr; 5182 uint32_t risc_size; 5183 uint32_t i; 5184 struct qla_hw_data *ha = vha->hw; 5185 struct req_que *req = ha->req_q_map[0]; 5186 5187 ql_dbg(ql_dbg_init, vha, 0x008b, 5188 "FW: Loading firmware from flash (%x).\n", faddr); 5189 5190 rval = QLA_SUCCESS; 5191 5192 segments = FA_RISC_CODE_SEGMENTS; 5193 dcode = (uint32_t *)req->ring; 5194 *srisc_addr = 0; 5195 5196 /* Validate firmware image by checking version. */ 5197 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4); 5198 for (i = 0; i < 4; i++) 5199 dcode[i] = be32_to_cpu(dcode[i]); 5200 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 5201 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 5202 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 5203 dcode[3] == 0)) { 5204 ql_log(ql_log_fatal, vha, 0x008c, 5205 "Unable to verify the integrity of flash firmware " 5206 "image.\n"); 5207 ql_log(ql_log_fatal, vha, 0x008d, 5208 "Firmware data: %08x %08x %08x %08x.\n", 5209 dcode[0], dcode[1], dcode[2], dcode[3]); 5210 5211 return QLA_FUNCTION_FAILED; 5212 } 5213 5214 while (segments && rval == QLA_SUCCESS) { 5215 /* Read segment's load information. */ 5216 qla24xx_read_flash_data(vha, dcode, faddr, 4); 5217 5218 risc_addr = be32_to_cpu(dcode[2]); 5219 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; 5220 risc_size = be32_to_cpu(dcode[3]); 5221 5222 fragment = 0; 5223 while (risc_size > 0 && rval == QLA_SUCCESS) { 5224 dlen = (uint32_t)(ha->fw_transfer_size >> 2); 5225 if (dlen > risc_size) 5226 dlen = risc_size; 5227 5228 ql_dbg(ql_dbg_init, vha, 0x008e, 5229 "Loading risc segment@ risc addr %x " 5230 "number of dwords 0x%x offset 0x%x.\n", 5231 risc_addr, dlen, faddr); 5232 5233 qla24xx_read_flash_data(vha, dcode, faddr, dlen); 5234 for (i = 0; i < dlen; i++) 5235 dcode[i] = swab32(dcode[i]); 5236 5237 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 5238 dlen); 5239 if (rval) { 5240 ql_log(ql_log_fatal, vha, 0x008f, 5241 "Failed to load segment %d of firmware.\n", 5242 fragment); 5243 return QLA_FUNCTION_FAILED; 5244 } 5245 5246 faddr += dlen; 5247 risc_addr += dlen; 5248 risc_size -= dlen; 5249 fragment++; 5250 } 5251 5252 /* Next segment. */ 5253 segments--; 5254 } 5255 5256 if (!IS_QLA27XX(ha)) 5257 return rval; 5258 5259 if (ha->fw_dump_template) 5260 vfree(ha->fw_dump_template); 5261 ha->fw_dump_template = NULL; 5262 ha->fw_dump_template_len = 0; 5263 5264 ql_dbg(ql_dbg_init, vha, 0x0161, 5265 "Loading fwdump template from %x\n", faddr); 5266 qla24xx_read_flash_data(vha, dcode, faddr, 7); 5267 risc_size = be32_to_cpu(dcode[2]); 5268 ql_dbg(ql_dbg_init, vha, 0x0162, 5269 "-> array size %x dwords\n", risc_size); 5270 if (risc_size == 0 || risc_size == ~0) 5271 goto default_template; 5272 5273 dlen = (risc_size - 8) * sizeof(*dcode); 5274 ql_dbg(ql_dbg_init, vha, 0x0163, 5275 "-> template allocating %x bytes...\n", dlen); 5276 ha->fw_dump_template = vmalloc(dlen); 5277 if (!ha->fw_dump_template) { 5278 ql_log(ql_log_warn, vha, 0x0164, 5279 "Failed fwdump template allocate %x bytes.\n", risc_size); 5280 goto default_template; 5281 } 5282 5283 faddr += 7; 5284 risc_size -= 8; 5285 dcode = ha->fw_dump_template; 5286 qla24xx_read_flash_data(vha, dcode, faddr, risc_size); 5287 for (i = 0; i < risc_size; i++) 5288 dcode[i] = le32_to_cpu(dcode[i]); 5289 5290 if (!qla27xx_fwdt_template_valid(dcode)) { 5291 ql_log(ql_log_warn, vha, 0x0165, 5292 "Failed fwdump template validate\n"); 5293 goto default_template; 5294 } 5295 5296 dlen = qla27xx_fwdt_template_size(dcode); 5297 ql_dbg(ql_dbg_init, vha, 0x0166, 5298 "-> template size %x bytes\n", dlen); 5299 if (dlen > risc_size * sizeof(*dcode)) { 5300 ql_log(ql_log_warn, vha, 0x0167, 5301 "Failed fwdump template exceeds array by %x bytes\n", 5302 (uint32_t)(dlen - risc_size * sizeof(*dcode))); 5303 goto default_template; 5304 } 5305 ha->fw_dump_template_len = dlen; 5306 return rval; 5307 5308 default_template: 5309 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n"); 5310 if (ha->fw_dump_template) 5311 vfree(ha->fw_dump_template); 5312 ha->fw_dump_template = NULL; 5313 ha->fw_dump_template_len = 0; 5314 5315 dlen = qla27xx_fwdt_template_default_size(); 5316 ql_dbg(ql_dbg_init, vha, 0x0169, 5317 "-> template allocating %x bytes...\n", dlen); 5318 ha->fw_dump_template = vmalloc(dlen); 5319 if (!ha->fw_dump_template) { 5320 ql_log(ql_log_warn, vha, 0x016a, 5321 "Failed fwdump template allocate %x bytes.\n", risc_size); 5322 goto failed_template; 5323 } 5324 5325 dcode = ha->fw_dump_template; 5326 risc_size = dlen / sizeof(*dcode); 5327 memcpy(dcode, qla27xx_fwdt_template_default(), dlen); 5328 for (i = 0; i < risc_size; i++) 5329 dcode[i] = be32_to_cpu(dcode[i]); 5330 5331 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) { 5332 ql_log(ql_log_warn, vha, 0x016b, 5333 "Failed fwdump template validate\n"); 5334 goto failed_template; 5335 } 5336 5337 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template); 5338 ql_dbg(ql_dbg_init, vha, 0x016c, 5339 "-> template size %x bytes\n", dlen); 5340 ha->fw_dump_template_len = dlen; 5341 return rval; 5342 5343 failed_template: 5344 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n"); 5345 if (ha->fw_dump_template) 5346 vfree(ha->fw_dump_template); 5347 ha->fw_dump_template = NULL; 5348 ha->fw_dump_template_len = 0; 5349 return rval; 5350 } 5351 5352 #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/" 5353 5354 int 5355 qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 5356 { 5357 int rval; 5358 int i, fragment; 5359 uint16_t *wcode, *fwcode; 5360 uint32_t risc_addr, risc_size, fwclen, wlen, *seg; 5361 struct fw_blob *blob; 5362 struct qla_hw_data *ha = vha->hw; 5363 struct req_que *req = ha->req_q_map[0]; 5364 5365 /* Load firmware blob. */ 5366 blob = qla2x00_request_firmware(vha); 5367 if (!blob) { 5368 ql_log(ql_log_info, vha, 0x0083, 5369 "Fimware image unavailable.\n"); 5370 ql_log(ql_log_info, vha, 0x0084, 5371 "Firmware images can be retrieved from: "QLA_FW_URL ".\n"); 5372 return QLA_FUNCTION_FAILED; 5373 } 5374 5375 rval = QLA_SUCCESS; 5376 5377 wcode = (uint16_t *)req->ring; 5378 *srisc_addr = 0; 5379 fwcode = (uint16_t *)blob->fw->data; 5380 fwclen = 0; 5381 5382 /* Validate firmware image by checking version. */ 5383 if (blob->fw->size < 8 * sizeof(uint16_t)) { 5384 ql_log(ql_log_fatal, vha, 0x0085, 5385 "Unable to verify integrity of firmware image (%Zd).\n", 5386 blob->fw->size); 5387 goto fail_fw_integrity; 5388 } 5389 for (i = 0; i < 4; i++) 5390 wcode[i] = be16_to_cpu(fwcode[i + 4]); 5391 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff && 5392 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 && 5393 wcode[2] == 0 && wcode[3] == 0)) { 5394 ql_log(ql_log_fatal, vha, 0x0086, 5395 "Unable to verify integrity of firmware image.\n"); 5396 ql_log(ql_log_fatal, vha, 0x0087, 5397 "Firmware data: %04x %04x %04x %04x.\n", 5398 wcode[0], wcode[1], wcode[2], wcode[3]); 5399 goto fail_fw_integrity; 5400 } 5401 5402 seg = blob->segs; 5403 while (*seg && rval == QLA_SUCCESS) { 5404 risc_addr = *seg; 5405 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr; 5406 risc_size = be16_to_cpu(fwcode[3]); 5407 5408 /* Validate firmware image size. */ 5409 fwclen += risc_size * sizeof(uint16_t); 5410 if (blob->fw->size < fwclen) { 5411 ql_log(ql_log_fatal, vha, 0x0088, 5412 "Unable to verify integrity of firmware image " 5413 "(%Zd).\n", blob->fw->size); 5414 goto fail_fw_integrity; 5415 } 5416 5417 fragment = 0; 5418 while (risc_size > 0 && rval == QLA_SUCCESS) { 5419 wlen = (uint16_t)(ha->fw_transfer_size >> 1); 5420 if (wlen > risc_size) 5421 wlen = risc_size; 5422 ql_dbg(ql_dbg_init, vha, 0x0089, 5423 "Loading risc segment@ risc addr %x number of " 5424 "words 0x%x.\n", risc_addr, wlen); 5425 5426 for (i = 0; i < wlen; i++) 5427 wcode[i] = swab16(fwcode[i]); 5428 5429 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 5430 wlen); 5431 if (rval) { 5432 ql_log(ql_log_fatal, vha, 0x008a, 5433 "Failed to load segment %d of firmware.\n", 5434 fragment); 5435 break; 5436 } 5437 5438 fwcode += wlen; 5439 risc_addr += wlen; 5440 risc_size -= wlen; 5441 fragment++; 5442 } 5443 5444 /* Next segment. */ 5445 seg++; 5446 } 5447 return rval; 5448 5449 fail_fw_integrity: 5450 return QLA_FUNCTION_FAILED; 5451 } 5452 5453 static int 5454 qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) 5455 { 5456 int rval; 5457 int segments, fragment; 5458 uint32_t *dcode, dlen; 5459 uint32_t risc_addr; 5460 uint32_t risc_size; 5461 uint32_t i; 5462 struct fw_blob *blob; 5463 const uint32_t *fwcode; 5464 uint32_t fwclen; 5465 struct qla_hw_data *ha = vha->hw; 5466 struct req_que *req = ha->req_q_map[0]; 5467 5468 /* Load firmware blob. */ 5469 blob = qla2x00_request_firmware(vha); 5470 if (!blob) { 5471 ql_log(ql_log_warn, vha, 0x0090, 5472 "Fimware image unavailable.\n"); 5473 ql_log(ql_log_warn, vha, 0x0091, 5474 "Firmware images can be retrieved from: " 5475 QLA_FW_URL ".\n"); 5476 5477 return QLA_FUNCTION_FAILED; 5478 } 5479 5480 ql_dbg(ql_dbg_init, vha, 0x0092, 5481 "FW: Loading via request-firmware.\n"); 5482 5483 rval = QLA_SUCCESS; 5484 5485 segments = FA_RISC_CODE_SEGMENTS; 5486 dcode = (uint32_t *)req->ring; 5487 *srisc_addr = 0; 5488 fwcode = (uint32_t *)blob->fw->data; 5489 fwclen = 0; 5490 5491 /* Validate firmware image by checking version. */ 5492 if (blob->fw->size < 8 * sizeof(uint32_t)) { 5493 ql_log(ql_log_fatal, vha, 0x0093, 5494 "Unable to verify integrity of firmware image (%Zd).\n", 5495 blob->fw->size); 5496 return QLA_FUNCTION_FAILED; 5497 } 5498 for (i = 0; i < 4; i++) 5499 dcode[i] = be32_to_cpu(fwcode[i + 4]); 5500 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 5501 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 5502 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 5503 dcode[3] == 0)) { 5504 ql_log(ql_log_fatal, vha, 0x0094, 5505 "Unable to verify integrity of firmware image (%Zd).\n", 5506 blob->fw->size); 5507 ql_log(ql_log_fatal, vha, 0x0095, 5508 "Firmware data: %08x %08x %08x %08x.\n", 5509 dcode[0], dcode[1], dcode[2], dcode[3]); 5510 return QLA_FUNCTION_FAILED; 5511 } 5512 5513 while (segments && rval == QLA_SUCCESS) { 5514 risc_addr = be32_to_cpu(fwcode[2]); 5515 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr; 5516 risc_size = be32_to_cpu(fwcode[3]); 5517 5518 /* Validate firmware image size. */ 5519 fwclen += risc_size * sizeof(uint32_t); 5520 if (blob->fw->size < fwclen) { 5521 ql_log(ql_log_fatal, vha, 0x0096, 5522 "Unable to verify integrity of firmware image " 5523 "(%Zd).\n", blob->fw->size); 5524 return QLA_FUNCTION_FAILED; 5525 } 5526 5527 fragment = 0; 5528 while (risc_size > 0 && rval == QLA_SUCCESS) { 5529 dlen = (uint32_t)(ha->fw_transfer_size >> 2); 5530 if (dlen > risc_size) 5531 dlen = risc_size; 5532 5533 ql_dbg(ql_dbg_init, vha, 0x0097, 5534 "Loading risc segment@ risc addr %x " 5535 "number of dwords 0x%x.\n", risc_addr, dlen); 5536 5537 for (i = 0; i < dlen; i++) 5538 dcode[i] = swab32(fwcode[i]); 5539 5540 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 5541 dlen); 5542 if (rval) { 5543 ql_log(ql_log_fatal, vha, 0x0098, 5544 "Failed to load segment %d of firmware.\n", 5545 fragment); 5546 return QLA_FUNCTION_FAILED; 5547 } 5548 5549 fwcode += dlen; 5550 risc_addr += dlen; 5551 risc_size -= dlen; 5552 fragment++; 5553 } 5554 5555 /* Next segment. */ 5556 segments--; 5557 } 5558 5559 if (!IS_QLA27XX(ha)) 5560 return rval; 5561 5562 if (ha->fw_dump_template) 5563 vfree(ha->fw_dump_template); 5564 ha->fw_dump_template = NULL; 5565 ha->fw_dump_template_len = 0; 5566 5567 ql_dbg(ql_dbg_init, vha, 0x171, 5568 "Loading fwdump template from %x\n", 5569 (uint32_t)((void *)fwcode - (void *)blob->fw->data)); 5570 risc_size = be32_to_cpu(fwcode[2]); 5571 ql_dbg(ql_dbg_init, vha, 0x172, 5572 "-> array size %x dwords\n", risc_size); 5573 if (risc_size == 0 || risc_size == ~0) 5574 goto default_template; 5575 5576 dlen = (risc_size - 8) * sizeof(*fwcode); 5577 ql_dbg(ql_dbg_init, vha, 0x0173, 5578 "-> template allocating %x bytes...\n", dlen); 5579 ha->fw_dump_template = vmalloc(dlen); 5580 if (!ha->fw_dump_template) { 5581 ql_log(ql_log_warn, vha, 0x0174, 5582 "Failed fwdump template allocate %x bytes.\n", risc_size); 5583 goto default_template; 5584 } 5585 5586 fwcode += 7; 5587 risc_size -= 8; 5588 dcode = ha->fw_dump_template; 5589 for (i = 0; i < risc_size; i++) 5590 dcode[i] = le32_to_cpu(fwcode[i]); 5591 5592 if (!qla27xx_fwdt_template_valid(dcode)) { 5593 ql_log(ql_log_warn, vha, 0x0175, 5594 "Failed fwdump template validate\n"); 5595 goto default_template; 5596 } 5597 5598 dlen = qla27xx_fwdt_template_size(dcode); 5599 ql_dbg(ql_dbg_init, vha, 0x0176, 5600 "-> template size %x bytes\n", dlen); 5601 if (dlen > risc_size * sizeof(*fwcode)) { 5602 ql_log(ql_log_warn, vha, 0x0177, 5603 "Failed fwdump template exceeds array by %x bytes\n", 5604 (uint32_t)(dlen - risc_size * sizeof(*fwcode))); 5605 goto default_template; 5606 } 5607 ha->fw_dump_template_len = dlen; 5608 return rval; 5609 5610 default_template: 5611 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n"); 5612 if (ha->fw_dump_template) 5613 vfree(ha->fw_dump_template); 5614 ha->fw_dump_template = NULL; 5615 ha->fw_dump_template_len = 0; 5616 5617 dlen = qla27xx_fwdt_template_default_size(); 5618 ql_dbg(ql_dbg_init, vha, 0x0179, 5619 "-> template allocating %x bytes...\n", dlen); 5620 ha->fw_dump_template = vmalloc(dlen); 5621 if (!ha->fw_dump_template) { 5622 ql_log(ql_log_warn, vha, 0x017a, 5623 "Failed fwdump template allocate %x bytes.\n", risc_size); 5624 goto failed_template; 5625 } 5626 5627 dcode = ha->fw_dump_template; 5628 risc_size = dlen / sizeof(*fwcode); 5629 fwcode = qla27xx_fwdt_template_default(); 5630 for (i = 0; i < risc_size; i++) 5631 dcode[i] = be32_to_cpu(fwcode[i]); 5632 5633 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) { 5634 ql_log(ql_log_warn, vha, 0x017b, 5635 "Failed fwdump template validate\n"); 5636 goto failed_template; 5637 } 5638 5639 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template); 5640 ql_dbg(ql_dbg_init, vha, 0x017c, 5641 "-> template size %x bytes\n", dlen); 5642 ha->fw_dump_template_len = dlen; 5643 return rval; 5644 5645 failed_template: 5646 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n"); 5647 if (ha->fw_dump_template) 5648 vfree(ha->fw_dump_template); 5649 ha->fw_dump_template = NULL; 5650 ha->fw_dump_template_len = 0; 5651 return rval; 5652 } 5653 5654 int 5655 qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 5656 { 5657 int rval; 5658 5659 if (ql2xfwloadbin == 1) 5660 return qla81xx_load_risc(vha, srisc_addr); 5661 5662 /* 5663 * FW Load priority: 5664 * 1) Firmware via request-firmware interface (.bin file). 5665 * 2) Firmware residing in flash. 5666 */ 5667 rval = qla24xx_load_risc_blob(vha, srisc_addr); 5668 if (rval == QLA_SUCCESS) 5669 return rval; 5670 5671 return qla24xx_load_risc_flash(vha, srisc_addr, 5672 vha->hw->flt_region_fw); 5673 } 5674 5675 int 5676 qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 5677 { 5678 int rval; 5679 struct qla_hw_data *ha = vha->hw; 5680 5681 if (ql2xfwloadbin == 2) 5682 goto try_blob_fw; 5683 5684 /* 5685 * FW Load priority: 5686 * 1) Firmware residing in flash. 5687 * 2) Firmware via request-firmware interface (.bin file). 5688 * 3) Golden-Firmware residing in flash -- limited operation. 5689 */ 5690 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw); 5691 if (rval == QLA_SUCCESS) 5692 return rval; 5693 5694 try_blob_fw: 5695 rval = qla24xx_load_risc_blob(vha, srisc_addr); 5696 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw) 5697 return rval; 5698 5699 ql_log(ql_log_info, vha, 0x0099, 5700 "Attempting to fallback to golden firmware.\n"); 5701 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw); 5702 if (rval != QLA_SUCCESS) 5703 return rval; 5704 5705 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n"); 5706 ha->flags.running_gold_fw = 1; 5707 return rval; 5708 } 5709 5710 void 5711 qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) 5712 { 5713 int ret, retries; 5714 struct qla_hw_data *ha = vha->hw; 5715 5716 if (ha->flags.pci_channel_io_perm_failure) 5717 return; 5718 if (!IS_FWI2_CAPABLE(ha)) 5719 return; 5720 if (!ha->fw_major_version) 5721 return; 5722 5723 ret = qla2x00_stop_firmware(vha); 5724 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT && 5725 ret != QLA_INVALID_COMMAND && retries ; retries--) { 5726 ha->isp_ops->reset_chip(vha); 5727 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS) 5728 continue; 5729 if (qla2x00_setup_chip(vha) != QLA_SUCCESS) 5730 continue; 5731 ql_log(ql_log_info, vha, 0x8015, 5732 "Attempting retry of stop-firmware command.\n"); 5733 ret = qla2x00_stop_firmware(vha); 5734 } 5735 } 5736 5737 int 5738 qla24xx_configure_vhba(scsi_qla_host_t *vha) 5739 { 5740 int rval = QLA_SUCCESS; 5741 int rval2; 5742 uint16_t mb[MAILBOX_REGISTER_COUNT]; 5743 struct qla_hw_data *ha = vha->hw; 5744 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 5745 struct req_que *req; 5746 struct rsp_que *rsp; 5747 5748 if (!vha->vp_idx) 5749 return -EINVAL; 5750 5751 rval = qla2x00_fw_ready(base_vha); 5752 if (ha->flags.cpu_affinity_enabled) 5753 req = ha->req_q_map[0]; 5754 else 5755 req = vha->req; 5756 rsp = req->rsp; 5757 5758 if (rval == QLA_SUCCESS) { 5759 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 5760 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); 5761 } 5762 5763 vha->flags.management_server_logged_in = 0; 5764 5765 /* Login to SNS first */ 5766 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, 5767 BIT_1); 5768 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 5769 if (rval2 == QLA_MEMORY_ALLOC_FAILED) 5770 ql_dbg(ql_dbg_init, vha, 0x0120, 5771 "Failed SNS login: loop_id=%x, rval2=%d\n", 5772 NPH_SNS, rval2); 5773 else 5774 ql_dbg(ql_dbg_init, vha, 0x0103, 5775 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x " 5776 "mb[2]=%x mb[6]=%x mb[7]=%x.\n", 5777 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]); 5778 return (QLA_FUNCTION_FAILED); 5779 } 5780 5781 atomic_set(&vha->loop_down_timer, 0); 5782 atomic_set(&vha->loop_state, LOOP_UP); 5783 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5784 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5785 rval = qla2x00_loop_resync(base_vha); 5786 5787 return rval; 5788 } 5789 5790 /* 84XX Support **************************************************************/ 5791 5792 static LIST_HEAD(qla_cs84xx_list); 5793 static DEFINE_MUTEX(qla_cs84xx_mutex); 5794 5795 static struct qla_chip_state_84xx * 5796 qla84xx_get_chip(struct scsi_qla_host *vha) 5797 { 5798 struct qla_chip_state_84xx *cs84xx; 5799 struct qla_hw_data *ha = vha->hw; 5800 5801 mutex_lock(&qla_cs84xx_mutex); 5802 5803 /* Find any shared 84xx chip. */ 5804 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) { 5805 if (cs84xx->bus == ha->pdev->bus) { 5806 kref_get(&cs84xx->kref); 5807 goto done; 5808 } 5809 } 5810 5811 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL); 5812 if (!cs84xx) 5813 goto done; 5814 5815 kref_init(&cs84xx->kref); 5816 spin_lock_init(&cs84xx->access_lock); 5817 mutex_init(&cs84xx->fw_update_mutex); 5818 cs84xx->bus = ha->pdev->bus; 5819 5820 list_add_tail(&cs84xx->list, &qla_cs84xx_list); 5821 done: 5822 mutex_unlock(&qla_cs84xx_mutex); 5823 return cs84xx; 5824 } 5825 5826 static void 5827 __qla84xx_chip_release(struct kref *kref) 5828 { 5829 struct qla_chip_state_84xx *cs84xx = 5830 container_of(kref, struct qla_chip_state_84xx, kref); 5831 5832 mutex_lock(&qla_cs84xx_mutex); 5833 list_del(&cs84xx->list); 5834 mutex_unlock(&qla_cs84xx_mutex); 5835 kfree(cs84xx); 5836 } 5837 5838 void 5839 qla84xx_put_chip(struct scsi_qla_host *vha) 5840 { 5841 struct qla_hw_data *ha = vha->hw; 5842 if (ha->cs84xx) 5843 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release); 5844 } 5845 5846 static int 5847 qla84xx_init_chip(scsi_qla_host_t *vha) 5848 { 5849 int rval; 5850 uint16_t status[2]; 5851 struct qla_hw_data *ha = vha->hw; 5852 5853 mutex_lock(&ha->cs84xx->fw_update_mutex); 5854 5855 rval = qla84xx_verify_chip(vha, status); 5856 5857 mutex_unlock(&ha->cs84xx->fw_update_mutex); 5858 5859 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED: 5860 QLA_SUCCESS; 5861 } 5862 5863 /* 81XX Support **************************************************************/ 5864 5865 int 5866 qla81xx_nvram_config(scsi_qla_host_t *vha) 5867 { 5868 int rval; 5869 struct init_cb_81xx *icb; 5870 struct nvram_81xx *nv; 5871 uint32_t *dptr; 5872 uint8_t *dptr1, *dptr2; 5873 uint32_t chksum; 5874 uint16_t cnt; 5875 struct qla_hw_data *ha = vha->hw; 5876 5877 rval = QLA_SUCCESS; 5878 icb = (struct init_cb_81xx *)ha->init_cb; 5879 nv = ha->nvram; 5880 5881 /* Determine NVRAM starting address. */ 5882 ha->nvram_size = sizeof(struct nvram_81xx); 5883 ha->vpd_size = FA_NVRAM_VPD_SIZE; 5884 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 5885 ha->vpd_size = FA_VPD_SIZE_82XX; 5886 5887 /* Get VPD data into cache */ 5888 ha->vpd = ha->nvram + VPD_OFFSET; 5889 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2, 5890 ha->vpd_size); 5891 5892 /* Get NVRAM data into cache and calculate checksum. */ 5893 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2, 5894 ha->nvram_size); 5895 dptr = (uint32_t *)nv; 5896 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) 5897 chksum += le32_to_cpu(*dptr++); 5898 5899 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111, 5900 "Contents of NVRAM:\n"); 5901 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112, 5902 (uint8_t *)nv, ha->nvram_size); 5903 5904 /* Bad NVRAM data, set defaults parameters. */ 5905 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P' 5906 || nv->id[3] != ' ' || 5907 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) { 5908 /* Reset NVRAM data. */ 5909 ql_log(ql_log_info, vha, 0x0073, 5910 "Inconsistent NVRAM detected: checksum=0x%x id=%c " 5911 "version=0x%x.\n", chksum, nv->id[0], 5912 le16_to_cpu(nv->nvram_version)); 5913 ql_log(ql_log_info, vha, 0x0074, 5914 "Falling back to functioning (yet invalid -- WWPN) " 5915 "defaults.\n"); 5916 5917 /* 5918 * Set default initialization control block. 5919 */ 5920 memset(nv, 0, ha->nvram_size); 5921 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION); 5922 nv->version = __constant_cpu_to_le16(ICB_VERSION); 5923 nv->frame_payload_size = 2048; 5924 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF); 5925 nv->exchange_count = __constant_cpu_to_le16(0); 5926 nv->port_name[0] = 0x21; 5927 nv->port_name[1] = 0x00 + ha->port_no + 1; 5928 nv->port_name[2] = 0x00; 5929 nv->port_name[3] = 0xe0; 5930 nv->port_name[4] = 0x8b; 5931 nv->port_name[5] = 0x1c; 5932 nv->port_name[6] = 0x55; 5933 nv->port_name[7] = 0x86; 5934 nv->node_name[0] = 0x20; 5935 nv->node_name[1] = 0x00; 5936 nv->node_name[2] = 0x00; 5937 nv->node_name[3] = 0xe0; 5938 nv->node_name[4] = 0x8b; 5939 nv->node_name[5] = 0x1c; 5940 nv->node_name[6] = 0x55; 5941 nv->node_name[7] = 0x86; 5942 nv->login_retry_count = __constant_cpu_to_le16(8); 5943 nv->interrupt_delay_timer = __constant_cpu_to_le16(0); 5944 nv->login_timeout = __constant_cpu_to_le16(0); 5945 nv->firmware_options_1 = 5946 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 5947 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4); 5948 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12); 5949 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13); 5950 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10); 5951 nv->efi_parameters = __constant_cpu_to_le32(0); 5952 nv->reset_delay = 5; 5953 nv->max_luns_per_target = __constant_cpu_to_le16(128); 5954 nv->port_down_retry_count = __constant_cpu_to_le16(30); 5955 nv->link_down_timeout = __constant_cpu_to_le16(180); 5956 nv->enode_mac[0] = 0x00; 5957 nv->enode_mac[1] = 0xC0; 5958 nv->enode_mac[2] = 0xDD; 5959 nv->enode_mac[3] = 0x04; 5960 nv->enode_mac[4] = 0x05; 5961 nv->enode_mac[5] = 0x06 + ha->port_no + 1; 5962 5963 rval = 1; 5964 } 5965 5966 if (IS_T10_PI_CAPABLE(ha)) 5967 nv->frame_payload_size &= ~7; 5968 5969 qlt_81xx_config_nvram_stage1(vha, nv); 5970 5971 /* Reset Initialization control block */ 5972 memset(icb, 0, ha->init_cb_size); 5973 5974 /* Copy 1st segment. */ 5975 dptr1 = (uint8_t *)icb; 5976 dptr2 = (uint8_t *)&nv->version; 5977 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 5978 while (cnt--) 5979 *dptr1++ = *dptr2++; 5980 5981 icb->login_retry_count = nv->login_retry_count; 5982 5983 /* Copy 2nd segment. */ 5984 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 5985 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 5986 cnt = (uint8_t *)&icb->reserved_5 - 5987 (uint8_t *)&icb->interrupt_delay_timer; 5988 while (cnt--) 5989 *dptr1++ = *dptr2++; 5990 5991 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac)); 5992 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */ 5993 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) { 5994 icb->enode_mac[0] = 0x00; 5995 icb->enode_mac[1] = 0xC0; 5996 icb->enode_mac[2] = 0xDD; 5997 icb->enode_mac[3] = 0x04; 5998 icb->enode_mac[4] = 0x05; 5999 icb->enode_mac[5] = 0x06 + ha->port_no + 1; 6000 } 6001 6002 /* Use extended-initialization control block. */ 6003 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb)); 6004 6005 /* 6006 * Setup driver NVRAM options. 6007 */ 6008 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 6009 "QLE8XXX"); 6010 6011 qlt_81xx_config_nvram_stage2(vha, icb); 6012 6013 /* Use alternate WWN? */ 6014 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) { 6015 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 6016 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 6017 } 6018 6019 /* Prepare nodename */ 6020 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) { 6021 /* 6022 * Firmware will apply the following mask if the nodename was 6023 * not provided. 6024 */ 6025 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 6026 icb->node_name[0] &= 0xF0; 6027 } 6028 6029 /* Set host adapter parameters. */ 6030 ha->flags.disable_risc_code_load = 0; 6031 ha->flags.enable_lip_reset = 0; 6032 ha->flags.enable_lip_full_login = 6033 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0; 6034 ha->flags.enable_target_reset = 6035 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0; 6036 ha->flags.enable_led_scheme = 0; 6037 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0; 6038 6039 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 6040 (BIT_6 | BIT_5 | BIT_4)) >> 4; 6041 6042 /* save HBA serial number */ 6043 ha->serial0 = icb->port_name[5]; 6044 ha->serial1 = icb->port_name[6]; 6045 ha->serial2 = icb->port_name[7]; 6046 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 6047 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 6048 6049 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF); 6050 6051 ha->retry_count = le16_to_cpu(nv->login_retry_count); 6052 6053 /* Set minimum login_timeout to 4 seconds. */ 6054 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 6055 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 6056 if (le16_to_cpu(nv->login_timeout) < 4) 6057 nv->login_timeout = __constant_cpu_to_le16(4); 6058 ha->login_timeout = le16_to_cpu(nv->login_timeout); 6059 icb->login_timeout = nv->login_timeout; 6060 6061 /* Set minimum RATOV to 100 tenths of a second. */ 6062 ha->r_a_tov = 100; 6063 6064 ha->loop_reset_delay = nv->reset_delay; 6065 6066 /* Link Down Timeout = 0: 6067 * 6068 * When Port Down timer expires we will start returning 6069 * I/O's to OS with "DID_NO_CONNECT". 6070 * 6071 * Link Down Timeout != 0: 6072 * 6073 * The driver waits for the link to come up after link down 6074 * before returning I/Os to OS with "DID_NO_CONNECT". 6075 */ 6076 if (le16_to_cpu(nv->link_down_timeout) == 0) { 6077 ha->loop_down_abort_time = 6078 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 6079 } else { 6080 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 6081 ha->loop_down_abort_time = 6082 (LOOP_DOWN_TIME - ha->link_down_timeout); 6083 } 6084 6085 /* Need enough time to try and get the port back. */ 6086 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 6087 if (qlport_down_retry) 6088 ha->port_down_retry_count = qlport_down_retry; 6089 6090 /* Set login_retry_count */ 6091 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 6092 if (ha->port_down_retry_count == 6093 le16_to_cpu(nv->port_down_retry_count) && 6094 ha->port_down_retry_count > 3) 6095 ha->login_retry_count = ha->port_down_retry_count; 6096 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 6097 ha->login_retry_count = ha->port_down_retry_count; 6098 if (ql2xloginretrycount) 6099 ha->login_retry_count = ql2xloginretrycount; 6100 6101 /* if not running MSI-X we need handshaking on interrupts */ 6102 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha))) 6103 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22); 6104 6105 /* Enable ZIO. */ 6106 if (!vha->flags.init_done) { 6107 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 6108 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 6109 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 6110 le16_to_cpu(icb->interrupt_delay_timer): 2; 6111 } 6112 icb->firmware_options_2 &= __constant_cpu_to_le32( 6113 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 6114 vha->flags.process_response_queue = 0; 6115 if (ha->zio_mode != QLA_ZIO_DISABLED) { 6116 ha->zio_mode = QLA_ZIO_MODE_6; 6117 6118 ql_log(ql_log_info, vha, 0x0075, 6119 "ZIO mode %d enabled; timer delay (%d us).\n", 6120 ha->zio_mode, 6121 ha->zio_timer * 100); 6122 6123 icb->firmware_options_2 |= cpu_to_le32( 6124 (uint32_t)ha->zio_mode); 6125 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 6126 vha->flags.process_response_queue = 1; 6127 } 6128 6129 if (rval) { 6130 ql_log(ql_log_warn, vha, 0x0076, 6131 "NVRAM configuration failed.\n"); 6132 } 6133 return (rval); 6134 } 6135 6136 int 6137 qla82xx_restart_isp(scsi_qla_host_t *vha) 6138 { 6139 int status, rval; 6140 struct qla_hw_data *ha = vha->hw; 6141 struct req_que *req = ha->req_q_map[0]; 6142 struct rsp_que *rsp = ha->rsp_q_map[0]; 6143 struct scsi_qla_host *vp; 6144 unsigned long flags; 6145 6146 status = qla2x00_init_rings(vha); 6147 if (!status) { 6148 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6149 ha->flags.chip_reset_done = 1; 6150 6151 status = qla2x00_fw_ready(vha); 6152 if (!status) { 6153 /* Issue a marker after FW becomes ready. */ 6154 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); 6155 vha->flags.online = 1; 6156 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 6157 } 6158 6159 /* if no cable then assume it's good */ 6160 if ((vha->device_flags & DFLG_NO_CABLE)) 6161 status = 0; 6162 } 6163 6164 if (!status) { 6165 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6166 6167 if (!atomic_read(&vha->loop_down_timer)) { 6168 /* 6169 * Issue marker command only when we are going 6170 * to start the I/O . 6171 */ 6172 vha->marker_needed = 1; 6173 } 6174 6175 ha->isp_ops->enable_intrs(ha); 6176 6177 ha->isp_abort_cnt = 0; 6178 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 6179 6180 /* Update the firmware version */ 6181 status = qla82xx_check_md_needed(vha); 6182 6183 if (ha->fce) { 6184 ha->flags.fce_enabled = 1; 6185 memset(ha->fce, 0, 6186 fce_calc_size(ha->fce_bufs)); 6187 rval = qla2x00_enable_fce_trace(vha, 6188 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 6189 &ha->fce_bufs); 6190 if (rval) { 6191 ql_log(ql_log_warn, vha, 0x8001, 6192 "Unable to reinitialize FCE (%d).\n", 6193 rval); 6194 ha->flags.fce_enabled = 0; 6195 } 6196 } 6197 6198 if (ha->eft) { 6199 memset(ha->eft, 0, EFT_SIZE); 6200 rval = qla2x00_enable_eft_trace(vha, 6201 ha->eft_dma, EFT_NUM_BUFFERS); 6202 if (rval) { 6203 ql_log(ql_log_warn, vha, 0x8010, 6204 "Unable to reinitialize EFT (%d).\n", 6205 rval); 6206 } 6207 } 6208 } 6209 6210 if (!status) { 6211 ql_dbg(ql_dbg_taskm, vha, 0x8011, 6212 "qla82xx_restart_isp succeeded.\n"); 6213 6214 spin_lock_irqsave(&ha->vport_slock, flags); 6215 list_for_each_entry(vp, &ha->vp_list, list) { 6216 if (vp->vp_idx) { 6217 atomic_inc(&vp->vref_count); 6218 spin_unlock_irqrestore(&ha->vport_slock, flags); 6219 6220 qla2x00_vp_abort_isp(vp); 6221 6222 spin_lock_irqsave(&ha->vport_slock, flags); 6223 atomic_dec(&vp->vref_count); 6224 } 6225 } 6226 spin_unlock_irqrestore(&ha->vport_slock, flags); 6227 6228 } else { 6229 ql_log(ql_log_warn, vha, 0x8016, 6230 "qla82xx_restart_isp **** FAILED ****.\n"); 6231 } 6232 6233 return status; 6234 } 6235 6236 void 6237 qla81xx_update_fw_options(scsi_qla_host_t *vha) 6238 { 6239 struct qla_hw_data *ha = vha->hw; 6240 6241 if (!ql2xetsenable) 6242 return; 6243 6244 /* Enable ETS Burst. */ 6245 memset(ha->fw_options, 0, sizeof(ha->fw_options)); 6246 ha->fw_options[2] |= BIT_9; 6247 qla2x00_set_fw_options(vha, ha->fw_options); 6248 } 6249 6250 /* 6251 * qla24xx_get_fcp_prio 6252 * Gets the fcp cmd priority value for the logged in port. 6253 * Looks for a match of the port descriptors within 6254 * each of the fcp prio config entries. If a match is found, 6255 * the tag (priority) value is returned. 6256 * 6257 * Input: 6258 * vha = scsi host structure pointer. 6259 * fcport = port structure pointer. 6260 * 6261 * Return: 6262 * non-zero (if found) 6263 * -1 (if not found) 6264 * 6265 * Context: 6266 * Kernel context 6267 */ 6268 static int 6269 qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 6270 { 6271 int i, entries; 6272 uint8_t pid_match, wwn_match; 6273 int priority; 6274 uint32_t pid1, pid2; 6275 uint64_t wwn1, wwn2; 6276 struct qla_fcp_prio_entry *pri_entry; 6277 struct qla_hw_data *ha = vha->hw; 6278 6279 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled) 6280 return -1; 6281 6282 priority = -1; 6283 entries = ha->fcp_prio_cfg->num_entries; 6284 pri_entry = &ha->fcp_prio_cfg->entry[0]; 6285 6286 for (i = 0; i < entries; i++) { 6287 pid_match = wwn_match = 0; 6288 6289 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) { 6290 pri_entry++; 6291 continue; 6292 } 6293 6294 /* check source pid for a match */ 6295 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) { 6296 pid1 = pri_entry->src_pid & INVALID_PORT_ID; 6297 pid2 = vha->d_id.b24 & INVALID_PORT_ID; 6298 if (pid1 == INVALID_PORT_ID) 6299 pid_match++; 6300 else if (pid1 == pid2) 6301 pid_match++; 6302 } 6303 6304 /* check destination pid for a match */ 6305 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) { 6306 pid1 = pri_entry->dst_pid & INVALID_PORT_ID; 6307 pid2 = fcport->d_id.b24 & INVALID_PORT_ID; 6308 if (pid1 == INVALID_PORT_ID) 6309 pid_match++; 6310 else if (pid1 == pid2) 6311 pid_match++; 6312 } 6313 6314 /* check source WWN for a match */ 6315 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) { 6316 wwn1 = wwn_to_u64(vha->port_name); 6317 wwn2 = wwn_to_u64(pri_entry->src_wwpn); 6318 if (wwn2 == (uint64_t)-1) 6319 wwn_match++; 6320 else if (wwn1 == wwn2) 6321 wwn_match++; 6322 } 6323 6324 /* check destination WWN for a match */ 6325 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) { 6326 wwn1 = wwn_to_u64(fcport->port_name); 6327 wwn2 = wwn_to_u64(pri_entry->dst_wwpn); 6328 if (wwn2 == (uint64_t)-1) 6329 wwn_match++; 6330 else if (wwn1 == wwn2) 6331 wwn_match++; 6332 } 6333 6334 if (pid_match == 2 || wwn_match == 2) { 6335 /* Found a matching entry */ 6336 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID) 6337 priority = pri_entry->tag; 6338 break; 6339 } 6340 6341 pri_entry++; 6342 } 6343 6344 return priority; 6345 } 6346 6347 /* 6348 * qla24xx_update_fcport_fcp_prio 6349 * Activates fcp priority for the logged in fc port 6350 * 6351 * Input: 6352 * vha = scsi host structure pointer. 6353 * fcp = port structure pointer. 6354 * 6355 * Return: 6356 * QLA_SUCCESS or QLA_FUNCTION_FAILED 6357 * 6358 * Context: 6359 * Kernel context. 6360 */ 6361 int 6362 qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 6363 { 6364 int ret; 6365 int priority; 6366 uint16_t mb[5]; 6367 6368 if (fcport->port_type != FCT_TARGET || 6369 fcport->loop_id == FC_NO_LOOP_ID) 6370 return QLA_FUNCTION_FAILED; 6371 6372 priority = qla24xx_get_fcp_prio(vha, fcport); 6373 if (priority < 0) 6374 return QLA_FUNCTION_FAILED; 6375 6376 if (IS_P3P_TYPE(vha->hw)) { 6377 fcport->fcp_prio = priority & 0xf; 6378 return QLA_SUCCESS; 6379 } 6380 6381 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb); 6382 if (ret == QLA_SUCCESS) { 6383 if (fcport->fcp_prio != priority) 6384 ql_dbg(ql_dbg_user, vha, 0x709e, 6385 "Updated FCP_CMND priority - value=%d loop_id=%d " 6386 "port_id=%02x%02x%02x.\n", priority, 6387 fcport->loop_id, fcport->d_id.b.domain, 6388 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6389 fcport->fcp_prio = priority & 0xf; 6390 } else 6391 ql_dbg(ql_dbg_user, vha, 0x704f, 6392 "Unable to update FCP_CMND priority - ret=0x%x for " 6393 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id, 6394 fcport->d_id.b.domain, fcport->d_id.b.area, 6395 fcport->d_id.b.al_pa); 6396 return ret; 6397 } 6398 6399 /* 6400 * qla24xx_update_all_fcp_prio 6401 * Activates fcp priority for all the logged in ports 6402 * 6403 * Input: 6404 * ha = adapter block pointer. 6405 * 6406 * Return: 6407 * QLA_SUCCESS or QLA_FUNCTION_FAILED 6408 * 6409 * Context: 6410 * Kernel context. 6411 */ 6412 int 6413 qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha) 6414 { 6415 int ret; 6416 fc_port_t *fcport; 6417 6418 ret = QLA_FUNCTION_FAILED; 6419 /* We need to set priority for all logged in ports */ 6420 list_for_each_entry(fcport, &vha->vp_fcports, list) 6421 ret = qla24xx_update_fcport_fcp_prio(vha, fcport); 6422 6423 return ret; 6424 } 6425