1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 #include "qla_gbl.h" 8 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/vmalloc.h> 12 13 #include "qla_devtbl.h" 14 15 #ifdef CONFIG_SPARC 16 #include <asm/prom.h> 17 #endif 18 19 #include "qla_target.h" 20 21 /* 22 * QLogic ISP2x00 Hardware Support Function Prototypes. 23 */ 24 static int qla2x00_isp_firmware(scsi_qla_host_t *); 25 static int qla2x00_setup_chip(scsi_qla_host_t *); 26 static int qla2x00_fw_ready(scsi_qla_host_t *); 27 static int qla2x00_configure_hba(scsi_qla_host_t *); 28 static int qla2x00_configure_loop(scsi_qla_host_t *); 29 static int qla2x00_configure_local_loop(scsi_qla_host_t *); 30 static int qla2x00_configure_fabric(scsi_qla_host_t *); 31 static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *); 32 static int qla2x00_restart_isp(scsi_qla_host_t *); 33 34 static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *); 35 static int qla84xx_init_chip(scsi_qla_host_t *); 36 static int qla25xx_init_queues(struct qla_hw_data *); 37 static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *); 38 static void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, 39 struct event_arg *ea); 40 static void qla24xx_handle_prli_done_event(struct scsi_qla_host *, 41 struct event_arg *); 42 static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *); 43 44 /* SRB Extensions ---------------------------------------------------------- */ 45 46 void 47 qla2x00_sp_timeout(struct timer_list *t) 48 { 49 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer); 50 struct srb_iocb *iocb; 51 52 WARN_ON(irqs_disabled()); 53 iocb = &sp->u.iocb_cmd; 54 iocb->timeout(sp); 55 } 56 57 void qla2x00_sp_free(srb_t *sp) 58 { 59 struct srb_iocb *iocb = &sp->u.iocb_cmd; 60 61 del_timer(&iocb->timer); 62 qla2x00_rel_sp(sp); 63 } 64 65 void qla2xxx_rel_done_warning(srb_t *sp, int res) 66 { 67 WARN_ONCE(1, "Calling done() of an already freed srb %p object\n", sp); 68 } 69 70 void qla2xxx_rel_free_warning(srb_t *sp) 71 { 72 WARN_ONCE(1, "Calling free() of an already freed srb %p object\n", sp); 73 } 74 75 /* Asynchronous Login/Logout Routines -------------------------------------- */ 76 77 unsigned long 78 qla2x00_get_async_timeout(struct scsi_qla_host *vha) 79 { 80 unsigned long tmo; 81 struct qla_hw_data *ha = vha->hw; 82 83 /* Firmware should use switch negotiated r_a_tov for timeout. */ 84 tmo = ha->r_a_tov / 10 * 2; 85 if (IS_QLAFX00(ha)) { 86 tmo = FX00_DEF_RATOV * 2; 87 } else if (!IS_FWI2_CAPABLE(ha)) { 88 /* 89 * Except for earlier ISPs where the timeout is seeded from the 90 * initialization control block. 91 */ 92 tmo = ha->login_timeout; 93 } 94 return tmo; 95 } 96 97 static void qla24xx_abort_iocb_timeout(void *data) 98 { 99 srb_t *sp = data; 100 struct srb_iocb *abt = &sp->u.iocb_cmd; 101 struct qla_qpair *qpair = sp->qpair; 102 u32 handle; 103 unsigned long flags; 104 105 if (sp->cmd_sp) 106 ql_dbg(ql_dbg_async, sp->vha, 0x507c, 107 "Abort timeout - cmd hdl=%x, cmd type=%x hdl=%x, type=%x\n", 108 sp->cmd_sp->handle, sp->cmd_sp->type, 109 sp->handle, sp->type); 110 else 111 ql_dbg(ql_dbg_async, sp->vha, 0x507c, 112 "Abort timeout 2 - hdl=%x, type=%x\n", 113 sp->handle, sp->type); 114 115 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 116 for (handle = 1; handle < qpair->req->num_outstanding_cmds; handle++) { 117 if (sp->cmd_sp && (qpair->req->outstanding_cmds[handle] == 118 sp->cmd_sp)) 119 qpair->req->outstanding_cmds[handle] = NULL; 120 121 /* removing the abort */ 122 if (qpair->req->outstanding_cmds[handle] == sp) { 123 qpair->req->outstanding_cmds[handle] = NULL; 124 break; 125 } 126 } 127 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 128 129 if (sp->cmd_sp) 130 sp->cmd_sp->done(sp->cmd_sp, QLA_OS_TIMER_EXPIRED); 131 132 abt->u.abt.comp_status = cpu_to_le16(CS_TIMEOUT); 133 sp->done(sp, QLA_OS_TIMER_EXPIRED); 134 } 135 136 static void qla24xx_abort_sp_done(srb_t *sp, int res) 137 { 138 struct srb_iocb *abt = &sp->u.iocb_cmd; 139 srb_t *orig_sp = sp->cmd_sp; 140 141 if (orig_sp) 142 qla_wait_nvme_release_cmd_kref(orig_sp); 143 144 del_timer(&sp->u.iocb_cmd.timer); 145 if (sp->flags & SRB_WAKEUP_ON_COMP) 146 complete(&abt->u.abt.comp); 147 else 148 sp->free(sp); 149 } 150 151 int qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait) 152 { 153 scsi_qla_host_t *vha = cmd_sp->vha; 154 struct srb_iocb *abt_iocb; 155 srb_t *sp; 156 int rval = QLA_FUNCTION_FAILED; 157 158 sp = qla2xxx_get_qpair_sp(cmd_sp->vha, cmd_sp->qpair, cmd_sp->fcport, 159 GFP_ATOMIC); 160 if (!sp) 161 return rval; 162 163 abt_iocb = &sp->u.iocb_cmd; 164 sp->type = SRB_ABT_CMD; 165 sp->name = "abort"; 166 sp->qpair = cmd_sp->qpair; 167 sp->cmd_sp = cmd_sp; 168 if (wait) 169 sp->flags = SRB_WAKEUP_ON_COMP; 170 171 abt_iocb->timeout = qla24xx_abort_iocb_timeout; 172 init_completion(&abt_iocb->u.abt.comp); 173 /* FW can send 2 x ABTS's timeout/20s */ 174 qla2x00_init_timer(sp, 42); 175 176 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle; 177 abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id); 178 179 sp->done = qla24xx_abort_sp_done; 180 181 ql_dbg(ql_dbg_async, vha, 0x507c, 182 "Abort command issued - hdl=%x, type=%x\n", cmd_sp->handle, 183 cmd_sp->type); 184 185 rval = qla2x00_start_sp(sp); 186 if (rval != QLA_SUCCESS) { 187 sp->free(sp); 188 return rval; 189 } 190 191 if (wait) { 192 wait_for_completion(&abt_iocb->u.abt.comp); 193 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ? 194 QLA_SUCCESS : QLA_FUNCTION_FAILED; 195 sp->free(sp); 196 } 197 198 return rval; 199 } 200 201 void 202 qla2x00_async_iocb_timeout(void *data) 203 { 204 srb_t *sp = data; 205 fc_port_t *fcport = sp->fcport; 206 struct srb_iocb *lio = &sp->u.iocb_cmd; 207 int rc, h; 208 unsigned long flags; 209 210 if (fcport) { 211 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, 212 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n", 213 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name); 214 215 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 216 } else { 217 pr_info("Async-%s timeout - hdl=%x.\n", 218 sp->name, sp->handle); 219 } 220 221 switch (sp->type) { 222 case SRB_LOGIN_CMD: 223 rc = qla24xx_async_abort_cmd(sp, false); 224 if (rc) { 225 /* Retry as needed. */ 226 lio->u.logio.data[0] = MBS_COMMAND_ERROR; 227 lio->u.logio.data[1] = 228 lio->u.logio.flags & SRB_LOGIN_RETRIED ? 229 QLA_LOGIO_LOGIN_RETRIED : 0; 230 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 231 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; 232 h++) { 233 if (sp->qpair->req->outstanding_cmds[h] == 234 sp) { 235 sp->qpair->req->outstanding_cmds[h] = 236 NULL; 237 break; 238 } 239 } 240 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 241 sp->done(sp, QLA_FUNCTION_TIMEOUT); 242 } 243 break; 244 case SRB_LOGOUT_CMD: 245 case SRB_CT_PTHRU_CMD: 246 case SRB_MB_IOCB: 247 case SRB_NACK_PLOGI: 248 case SRB_NACK_PRLI: 249 case SRB_NACK_LOGO: 250 case SRB_CTRL_VP: 251 default: 252 rc = qla24xx_async_abort_cmd(sp, false); 253 if (rc) { 254 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 255 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; 256 h++) { 257 if (sp->qpair->req->outstanding_cmds[h] == 258 sp) { 259 sp->qpair->req->outstanding_cmds[h] = 260 NULL; 261 break; 262 } 263 } 264 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 265 sp->done(sp, QLA_FUNCTION_TIMEOUT); 266 } 267 break; 268 } 269 } 270 271 static void qla2x00_async_login_sp_done(srb_t *sp, int res) 272 { 273 struct scsi_qla_host *vha = sp->vha; 274 struct srb_iocb *lio = &sp->u.iocb_cmd; 275 struct event_arg ea; 276 277 ql_dbg(ql_dbg_disc, vha, 0x20dd, 278 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res); 279 280 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 281 282 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 283 memset(&ea, 0, sizeof(ea)); 284 ea.fcport = sp->fcport; 285 ea.data[0] = lio->u.logio.data[0]; 286 ea.data[1] = lio->u.logio.data[1]; 287 ea.iop[0] = lio->u.logio.iop[0]; 288 ea.iop[1] = lio->u.logio.iop[1]; 289 ea.sp = sp; 290 qla24xx_handle_plogi_done_event(vha, &ea); 291 } 292 293 sp->free(sp); 294 } 295 296 static inline bool 297 fcport_is_smaller(fc_port_t *fcport) 298 { 299 if (wwn_to_u64(fcport->port_name) < 300 wwn_to_u64(fcport->vha->port_name)) 301 return true; 302 else 303 return false; 304 } 305 306 static inline bool 307 fcport_is_bigger(fc_port_t *fcport) 308 { 309 return !fcport_is_smaller(fcport); 310 } 311 312 int 313 qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport, 314 uint16_t *data) 315 { 316 srb_t *sp; 317 struct srb_iocb *lio; 318 int rval = QLA_FUNCTION_FAILED; 319 320 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) || 321 fcport->loop_id == FC_NO_LOOP_ID) { 322 ql_log(ql_log_warn, vha, 0xffff, 323 "%s: %8phC - not sending command.\n", 324 __func__, fcport->port_name); 325 return rval; 326 } 327 328 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 329 if (!sp) 330 goto done; 331 332 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND); 333 fcport->flags |= FCF_ASYNC_SENT; 334 fcport->logout_completed = 0; 335 336 sp->type = SRB_LOGIN_CMD; 337 sp->name = "login"; 338 sp->gen1 = fcport->rscn_gen; 339 sp->gen2 = fcport->login_gen; 340 341 lio = &sp->u.iocb_cmd; 342 lio->timeout = qla2x00_async_iocb_timeout; 343 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 344 345 sp->done = qla2x00_async_login_sp_done; 346 if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport)) 347 lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY; 348 else 349 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI; 350 351 if (NVME_TARGET(vha->hw, fcport)) 352 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI; 353 354 ql_log(ql_log_warn, vha, 0x2072, 355 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x retries=%d.\n", 356 fcport->port_name, sp->handle, fcport->loop_id, 357 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa, 358 fcport->login_retry); 359 360 rval = qla2x00_start_sp(sp); 361 if (rval != QLA_SUCCESS) { 362 fcport->flags |= FCF_LOGIN_NEEDED; 363 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 364 goto done_free_sp; 365 } 366 367 return rval; 368 369 done_free_sp: 370 sp->free(sp); 371 fcport->flags &= ~FCF_ASYNC_SENT; 372 done: 373 fcport->flags &= ~FCF_ASYNC_ACTIVE; 374 return rval; 375 } 376 377 static void qla2x00_async_logout_sp_done(srb_t *sp, int res) 378 { 379 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 380 sp->fcport->login_gen++; 381 qlt_logo_completion_handler(sp->fcport, res); 382 sp->free(sp); 383 } 384 385 int 386 qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport) 387 { 388 srb_t *sp; 389 struct srb_iocb *lio; 390 int rval = QLA_FUNCTION_FAILED; 391 392 fcport->flags |= FCF_ASYNC_SENT; 393 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 394 if (!sp) 395 goto done; 396 397 sp->type = SRB_LOGOUT_CMD; 398 sp->name = "logout"; 399 400 lio = &sp->u.iocb_cmd; 401 lio->timeout = qla2x00_async_iocb_timeout; 402 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 403 404 sp->done = qla2x00_async_logout_sp_done; 405 406 ql_dbg(ql_dbg_disc, vha, 0x2070, 407 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n", 408 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 409 fcport->d_id.b.area, fcport->d_id.b.al_pa, 410 fcport->port_name); 411 412 rval = qla2x00_start_sp(sp); 413 if (rval != QLA_SUCCESS) 414 goto done_free_sp; 415 return rval; 416 417 done_free_sp: 418 sp->free(sp); 419 done: 420 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 421 return rval; 422 } 423 424 void 425 qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport, 426 uint16_t *data) 427 { 428 fcport->flags &= ~FCF_ASYNC_ACTIVE; 429 /* Don't re-login in target mode */ 430 if (!fcport->tgt_session) 431 qla2x00_mark_device_lost(vha, fcport, 1); 432 qlt_logo_completion_handler(fcport, data[0]); 433 } 434 435 static void qla2x00_async_prlo_sp_done(srb_t *sp, int res) 436 { 437 struct srb_iocb *lio = &sp->u.iocb_cmd; 438 struct scsi_qla_host *vha = sp->vha; 439 440 sp->fcport->flags &= ~FCF_ASYNC_ACTIVE; 441 if (!test_bit(UNLOADING, &vha->dpc_flags)) 442 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport, 443 lio->u.logio.data); 444 sp->free(sp); 445 } 446 447 int 448 qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport) 449 { 450 srb_t *sp; 451 struct srb_iocb *lio; 452 int rval; 453 454 rval = QLA_FUNCTION_FAILED; 455 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 456 if (!sp) 457 goto done; 458 459 sp->type = SRB_PRLO_CMD; 460 sp->name = "prlo"; 461 462 lio = &sp->u.iocb_cmd; 463 lio->timeout = qla2x00_async_iocb_timeout; 464 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 465 466 sp->done = qla2x00_async_prlo_sp_done; 467 468 ql_dbg(ql_dbg_disc, vha, 0x2070, 469 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 470 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 471 fcport->d_id.b.area, fcport->d_id.b.al_pa); 472 473 rval = qla2x00_start_sp(sp); 474 if (rval != QLA_SUCCESS) 475 goto done_free_sp; 476 477 return rval; 478 479 done_free_sp: 480 sp->free(sp); 481 done: 482 fcport->flags &= ~FCF_ASYNC_ACTIVE; 483 return rval; 484 } 485 486 static 487 void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea) 488 { 489 struct fc_port *fcport = ea->fcport; 490 491 ql_dbg(ql_dbg_disc, vha, 0x20d2, 492 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n", 493 __func__, fcport->port_name, fcport->disc_state, 494 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2, 495 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id); 496 497 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 498 ea->data[0]); 499 500 if (ea->data[0] != MBS_COMMAND_COMPLETE) { 501 ql_dbg(ql_dbg_disc, vha, 0x2066, 502 "%s %8phC: adisc fail: post delete\n", 503 __func__, ea->fcport->port_name); 504 /* deleted = 0 & logout_on_delete = force fw cleanup */ 505 fcport->deleted = 0; 506 fcport->logout_on_delete = 1; 507 qlt_schedule_sess_for_deletion(ea->fcport); 508 return; 509 } 510 511 if (ea->fcport->disc_state == DSC_DELETE_PEND) 512 return; 513 514 if (ea->sp->gen2 != ea->fcport->login_gen) { 515 /* target side must have changed it. */ 516 ql_dbg(ql_dbg_disc, vha, 0x20d3, 517 "%s %8phC generation changed\n", 518 __func__, ea->fcport->port_name); 519 return; 520 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) { 521 qla_rscn_replay(fcport); 522 qlt_schedule_sess_for_deletion(fcport); 523 return; 524 } 525 526 __qla24xx_handle_gpdb_event(vha, ea); 527 } 528 529 static int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport) 530 { 531 struct qla_work_evt *e; 532 533 e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI); 534 if (!e) 535 return QLA_FUNCTION_FAILED; 536 537 e->u.fcport.fcport = fcport; 538 fcport->flags |= FCF_ASYNC_ACTIVE; 539 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND); 540 return qla2x00_post_work(vha, e); 541 } 542 543 static void qla2x00_async_adisc_sp_done(srb_t *sp, int res) 544 { 545 struct scsi_qla_host *vha = sp->vha; 546 struct event_arg ea; 547 struct srb_iocb *lio = &sp->u.iocb_cmd; 548 549 ql_dbg(ql_dbg_disc, vha, 0x2066, 550 "Async done-%s res %x %8phC\n", 551 sp->name, res, sp->fcport->port_name); 552 553 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 554 555 memset(&ea, 0, sizeof(ea)); 556 ea.rc = res; 557 ea.data[0] = lio->u.logio.data[0]; 558 ea.data[1] = lio->u.logio.data[1]; 559 ea.iop[0] = lio->u.logio.iop[0]; 560 ea.iop[1] = lio->u.logio.iop[1]; 561 ea.fcport = sp->fcport; 562 ea.sp = sp; 563 564 qla24xx_handle_adisc_event(vha, &ea); 565 566 sp->free(sp); 567 } 568 569 int 570 qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport, 571 uint16_t *data) 572 { 573 srb_t *sp; 574 struct srb_iocb *lio; 575 int rval = QLA_FUNCTION_FAILED; 576 577 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT)) 578 return rval; 579 580 fcport->flags |= FCF_ASYNC_SENT; 581 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 582 if (!sp) 583 goto done; 584 585 sp->type = SRB_ADISC_CMD; 586 sp->name = "adisc"; 587 588 lio = &sp->u.iocb_cmd; 589 lio->timeout = qla2x00_async_iocb_timeout; 590 sp->gen1 = fcport->rscn_gen; 591 sp->gen2 = fcport->login_gen; 592 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 593 594 sp->done = qla2x00_async_adisc_sp_done; 595 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) 596 lio->u.logio.flags |= SRB_LOGIN_RETRIED; 597 598 ql_dbg(ql_dbg_disc, vha, 0x206f, 599 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n", 600 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name); 601 602 rval = qla2x00_start_sp(sp); 603 if (rval != QLA_SUCCESS) 604 goto done_free_sp; 605 606 return rval; 607 608 done_free_sp: 609 sp->free(sp); 610 done: 611 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 612 qla2x00_post_async_adisc_work(vha, fcport, data); 613 return rval; 614 } 615 616 static bool qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id) 617 { 618 struct qla_hw_data *ha = vha->hw; 619 620 if (IS_FWI2_CAPABLE(ha)) 621 return loop_id > NPH_LAST_HANDLE; 622 623 return (loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) || 624 loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST; 625 } 626 627 /** 628 * qla2x00_find_new_loop_id - scan through our port list and find a new usable loop ID 629 * @vha: adapter state pointer. 630 * @dev: port structure pointer. 631 * 632 * Returns: 633 * qla2x00 local function return status code. 634 * 635 * Context: 636 * Kernel context. 637 */ 638 static int qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) 639 { 640 int rval; 641 struct qla_hw_data *ha = vha->hw; 642 unsigned long flags = 0; 643 644 rval = QLA_SUCCESS; 645 646 spin_lock_irqsave(&ha->vport_slock, flags); 647 648 dev->loop_id = find_first_zero_bit(ha->loop_id_map, LOOPID_MAP_SIZE); 649 if (dev->loop_id >= LOOPID_MAP_SIZE || 650 qla2x00_is_reserved_id(vha, dev->loop_id)) { 651 dev->loop_id = FC_NO_LOOP_ID; 652 rval = QLA_FUNCTION_FAILED; 653 } else { 654 set_bit(dev->loop_id, ha->loop_id_map); 655 } 656 spin_unlock_irqrestore(&ha->vport_slock, flags); 657 658 if (rval == QLA_SUCCESS) 659 ql_dbg(ql_dbg_disc, dev->vha, 0x2086, 660 "Assigning new loopid=%x, portid=%x.\n", 661 dev->loop_id, dev->d_id.b24); 662 else 663 ql_log(ql_log_warn, dev->vha, 0x2087, 664 "No loop_id's available, portid=%x.\n", 665 dev->d_id.b24); 666 667 return rval; 668 } 669 670 void qla2x00_clear_loop_id(fc_port_t *fcport) 671 { 672 struct qla_hw_data *ha = fcport->vha->hw; 673 674 if (fcport->loop_id == FC_NO_LOOP_ID || 675 qla2x00_is_reserved_id(fcport->vha, fcport->loop_id)) 676 return; 677 678 clear_bit(fcport->loop_id, ha->loop_id_map); 679 fcport->loop_id = FC_NO_LOOP_ID; 680 } 681 682 static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha, 683 struct event_arg *ea) 684 { 685 fc_port_t *fcport, *conflict_fcport; 686 struct get_name_list_extended *e; 687 u16 i, n, found = 0, loop_id; 688 port_id_t id; 689 u64 wwn; 690 u16 data[2]; 691 u8 current_login_state, nvme_cls; 692 693 fcport = ea->fcport; 694 ql_dbg(ql_dbg_disc, vha, 0xffff, 695 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n", 696 __func__, fcport->port_name, fcport->disc_state, 697 fcport->fw_login_state, ea->rc, 698 fcport->login_gen, fcport->last_login_gen, 699 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id); 700 701 if (fcport->disc_state == DSC_DELETE_PEND) 702 return; 703 704 if (ea->rc) { /* rval */ 705 if (fcport->login_retry == 0) { 706 ql_dbg(ql_dbg_disc, vha, 0x20de, 707 "GNL failed Port login retry %8phN, retry cnt=%d.\n", 708 fcport->port_name, fcport->login_retry); 709 } 710 return; 711 } 712 713 if (fcport->last_rscn_gen != fcport->rscn_gen) { 714 qla_rscn_replay(fcport); 715 qlt_schedule_sess_for_deletion(fcport); 716 return; 717 } else if (fcport->last_login_gen != fcport->login_gen) { 718 ql_dbg(ql_dbg_disc, vha, 0x20e0, 719 "%s %8phC login gen changed\n", 720 __func__, fcport->port_name); 721 return; 722 } 723 724 n = ea->data[0] / sizeof(struct get_name_list_extended); 725 726 ql_dbg(ql_dbg_disc, vha, 0x20e1, 727 "%s %d %8phC n %d %02x%02x%02x lid %d \n", 728 __func__, __LINE__, fcport->port_name, n, 729 fcport->d_id.b.domain, fcport->d_id.b.area, 730 fcport->d_id.b.al_pa, fcport->loop_id); 731 732 for (i = 0; i < n; i++) { 733 e = &vha->gnl.l[i]; 734 wwn = wwn_to_u64(e->port_name); 735 id.b.domain = e->port_id[2]; 736 id.b.area = e->port_id[1]; 737 id.b.al_pa = e->port_id[0]; 738 id.b.rsvd_1 = 0; 739 740 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE)) 741 continue; 742 743 if (IS_SW_RESV_ADDR(id)) 744 continue; 745 746 found = 1; 747 748 loop_id = le16_to_cpu(e->nport_handle); 749 loop_id = (loop_id & 0x7fff); 750 nvme_cls = e->current_login_state >> 4; 751 current_login_state = e->current_login_state & 0xf; 752 753 if (PRLI_PHASE(nvme_cls)) { 754 current_login_state = nvme_cls; 755 fcport->fc4_type &= ~FS_FC4TYPE_FCP; 756 fcport->fc4_type |= FS_FC4TYPE_NVME; 757 } else if (PRLI_PHASE(current_login_state)) { 758 fcport->fc4_type |= FS_FC4TYPE_FCP; 759 fcport->fc4_type &= ~FS_FC4TYPE_NVME; 760 } 761 762 ql_dbg(ql_dbg_disc, vha, 0x20e2, 763 "%s found %8phC CLS [%x|%x] fc4_type %d ID[%06x|%06x] lid[%d|%d]\n", 764 __func__, fcport->port_name, 765 e->current_login_state, fcport->fw_login_state, 766 fcport->fc4_type, id.b24, fcport->d_id.b24, 767 loop_id, fcport->loop_id); 768 769 switch (fcport->disc_state) { 770 case DSC_DELETE_PEND: 771 case DSC_DELETED: 772 break; 773 default: 774 if ((id.b24 != fcport->d_id.b24 && 775 fcport->d_id.b24 && 776 fcport->loop_id != FC_NO_LOOP_ID) || 777 (fcport->loop_id != FC_NO_LOOP_ID && 778 fcport->loop_id != loop_id)) { 779 ql_dbg(ql_dbg_disc, vha, 0x20e3, 780 "%s %d %8phC post del sess\n", 781 __func__, __LINE__, fcport->port_name); 782 if (fcport->n2n_flag) 783 fcport->d_id.b24 = 0; 784 qlt_schedule_sess_for_deletion(fcport); 785 return; 786 } 787 break; 788 } 789 790 fcport->loop_id = loop_id; 791 if (fcport->n2n_flag) 792 fcport->d_id.b24 = id.b24; 793 794 wwn = wwn_to_u64(fcport->port_name); 795 qlt_find_sess_invalidate_other(vha, wwn, 796 id, loop_id, &conflict_fcport); 797 798 if (conflict_fcport) { 799 /* 800 * Another share fcport share the same loop_id & 801 * nport id. Conflict fcport needs to finish 802 * cleanup before this fcport can proceed to login. 803 */ 804 conflict_fcport->conflict = fcport; 805 fcport->login_pause = 1; 806 } 807 808 switch (vha->hw->current_topology) { 809 default: 810 switch (current_login_state) { 811 case DSC_LS_PRLI_COMP: 812 ql_dbg(ql_dbg_disc + ql_dbg_verbose, 813 vha, 0x20e4, "%s %d %8phC post gpdb\n", 814 __func__, __LINE__, fcport->port_name); 815 816 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0) 817 fcport->port_type = FCT_INITIATOR; 818 else 819 fcport->port_type = FCT_TARGET; 820 data[0] = data[1] = 0; 821 qla2x00_post_async_adisc_work(vha, fcport, 822 data); 823 break; 824 case DSC_LS_PORT_UNAVAIL: 825 default: 826 if (fcport->loop_id == FC_NO_LOOP_ID) { 827 qla2x00_find_new_loop_id(vha, fcport); 828 fcport->fw_login_state = 829 DSC_LS_PORT_UNAVAIL; 830 } 831 ql_dbg(ql_dbg_disc, vha, 0x20e5, 832 "%s %d %8phC\n", __func__, __LINE__, 833 fcport->port_name); 834 qla24xx_fcport_handle_login(vha, fcport); 835 break; 836 } 837 break; 838 case ISP_CFG_N: 839 fcport->fw_login_state = current_login_state; 840 fcport->d_id = id; 841 switch (current_login_state) { 842 case DSC_LS_PRLI_PEND: 843 /* 844 * In the middle of PRLI. Let it finish. 845 * Allow relogin code to recheck state again 846 * with GNL. Push disc_state back to DELETED 847 * so GNL can go out again 848 */ 849 qla2x00_set_fcport_disc_state(fcport, 850 DSC_DELETED); 851 break; 852 case DSC_LS_PRLI_COMP: 853 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0) 854 fcport->port_type = FCT_INITIATOR; 855 else 856 fcport->port_type = FCT_TARGET; 857 858 data[0] = data[1] = 0; 859 qla2x00_post_async_adisc_work(vha, fcport, 860 data); 861 break; 862 case DSC_LS_PLOGI_COMP: 863 if (fcport_is_bigger(fcport)) { 864 /* local adapter is smaller */ 865 if (fcport->loop_id != FC_NO_LOOP_ID) 866 qla2x00_clear_loop_id(fcport); 867 868 fcport->loop_id = loop_id; 869 qla24xx_fcport_handle_login(vha, 870 fcport); 871 break; 872 } 873 fallthrough; 874 default: 875 if (fcport_is_smaller(fcport)) { 876 /* local adapter is bigger */ 877 if (fcport->loop_id != FC_NO_LOOP_ID) 878 qla2x00_clear_loop_id(fcport); 879 880 fcport->loop_id = loop_id; 881 qla24xx_fcport_handle_login(vha, 882 fcport); 883 } 884 break; 885 } 886 break; 887 } /* switch (ha->current_topology) */ 888 } 889 890 if (!found) { 891 switch (vha->hw->current_topology) { 892 case ISP_CFG_F: 893 case ISP_CFG_FL: 894 for (i = 0; i < n; i++) { 895 e = &vha->gnl.l[i]; 896 id.b.domain = e->port_id[0]; 897 id.b.area = e->port_id[1]; 898 id.b.al_pa = e->port_id[2]; 899 id.b.rsvd_1 = 0; 900 loop_id = le16_to_cpu(e->nport_handle); 901 902 if (fcport->d_id.b24 == id.b24) { 903 conflict_fcport = 904 qla2x00_find_fcport_by_wwpn(vha, 905 e->port_name, 0); 906 if (conflict_fcport) { 907 ql_dbg(ql_dbg_disc + ql_dbg_verbose, 908 vha, 0x20e5, 909 "%s %d %8phC post del sess\n", 910 __func__, __LINE__, 911 conflict_fcport->port_name); 912 qlt_schedule_sess_for_deletion 913 (conflict_fcport); 914 } 915 } 916 /* 917 * FW already picked this loop id for 918 * another fcport 919 */ 920 if (fcport->loop_id == loop_id) 921 fcport->loop_id = FC_NO_LOOP_ID; 922 } 923 qla24xx_fcport_handle_login(vha, fcport); 924 break; 925 case ISP_CFG_N: 926 qla2x00_set_fcport_disc_state(fcport, DSC_DELETED); 927 if (time_after_eq(jiffies, fcport->dm_login_expire)) { 928 if (fcport->n2n_link_reset_cnt < 2) { 929 fcport->n2n_link_reset_cnt++; 930 /* 931 * remote port is not sending PLOGI. 932 * Reset link to kick start his state 933 * machine 934 */ 935 set_bit(N2N_LINK_RESET, 936 &vha->dpc_flags); 937 } else { 938 if (fcport->n2n_chip_reset < 1) { 939 ql_log(ql_log_info, vha, 0x705d, 940 "Chip reset to bring laser down"); 941 set_bit(ISP_ABORT_NEEDED, 942 &vha->dpc_flags); 943 fcport->n2n_chip_reset++; 944 } else { 945 ql_log(ql_log_info, vha, 0x705d, 946 "Remote port %8ph is not coming back\n", 947 fcport->port_name); 948 fcport->scan_state = 0; 949 } 950 } 951 qla2xxx_wake_dpc(vha); 952 } else { 953 /* 954 * report port suppose to do PLOGI. Give him 955 * more time. FW will catch it. 956 */ 957 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 958 } 959 break; 960 default: 961 break; 962 } 963 } 964 } /* gnl_event */ 965 966 static void qla24xx_async_gnl_sp_done(srb_t *sp, int res) 967 { 968 struct scsi_qla_host *vha = sp->vha; 969 unsigned long flags; 970 struct fc_port *fcport = NULL, *tf; 971 u16 i, n = 0, loop_id; 972 struct event_arg ea; 973 struct get_name_list_extended *e; 974 u64 wwn; 975 struct list_head h; 976 bool found = false; 977 978 ql_dbg(ql_dbg_disc, vha, 0x20e7, 979 "Async done-%s res %x mb[1]=%x mb[2]=%x \n", 980 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1], 981 sp->u.iocb_cmd.u.mbx.in_mb[2]); 982 983 if (res == QLA_FUNCTION_TIMEOUT) 984 return; 985 986 sp->fcport->flags &= ~(FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE); 987 memset(&ea, 0, sizeof(ea)); 988 ea.sp = sp; 989 ea.rc = res; 990 991 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >= 992 sizeof(struct get_name_list_extended)) { 993 n = sp->u.iocb_cmd.u.mbx.in_mb[1] / 994 sizeof(struct get_name_list_extended); 995 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */ 996 } 997 998 for (i = 0; i < n; i++) { 999 e = &vha->gnl.l[i]; 1000 loop_id = le16_to_cpu(e->nport_handle); 1001 /* mask out reserve bit */ 1002 loop_id = (loop_id & 0x7fff); 1003 set_bit(loop_id, vha->hw->loop_id_map); 1004 wwn = wwn_to_u64(e->port_name); 1005 1006 ql_dbg(ql_dbg_disc, vha, 0x20e8, 1007 "%s %8phC %02x:%02x:%02x CLS %x/%x lid %x \n", 1008 __func__, &wwn, e->port_id[2], e->port_id[1], 1009 e->port_id[0], e->current_login_state, e->last_login_state, 1010 (loop_id & 0x7fff)); 1011 } 1012 1013 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1014 1015 INIT_LIST_HEAD(&h); 1016 fcport = tf = NULL; 1017 if (!list_empty(&vha->gnl.fcports)) 1018 list_splice_init(&vha->gnl.fcports, &h); 1019 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1020 1021 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) { 1022 list_del_init(&fcport->gnl_entry); 1023 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1024 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1025 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1026 ea.fcport = fcport; 1027 1028 qla24xx_handle_gnl_done_event(vha, &ea); 1029 } 1030 1031 /* create new fcport if fw has knowledge of new sessions */ 1032 for (i = 0; i < n; i++) { 1033 port_id_t id; 1034 u64 wwnn; 1035 1036 e = &vha->gnl.l[i]; 1037 wwn = wwn_to_u64(e->port_name); 1038 1039 found = false; 1040 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) { 1041 if (!memcmp((u8 *)&wwn, fcport->port_name, 1042 WWN_SIZE)) { 1043 found = true; 1044 break; 1045 } 1046 } 1047 1048 id.b.domain = e->port_id[2]; 1049 id.b.area = e->port_id[1]; 1050 id.b.al_pa = e->port_id[0]; 1051 id.b.rsvd_1 = 0; 1052 1053 if (!found && wwn && !IS_SW_RESV_ADDR(id)) { 1054 ql_dbg(ql_dbg_disc, vha, 0x2065, 1055 "%s %d %8phC %06x post new sess\n", 1056 __func__, __LINE__, (u8 *)&wwn, id.b24); 1057 wwnn = wwn_to_u64(e->node_name); 1058 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn, 1059 (u8 *)&wwnn, NULL, 0); 1060 } 1061 } 1062 1063 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1064 vha->gnl.sent = 0; 1065 if (!list_empty(&vha->gnl.fcports)) { 1066 /* retrigger gnl */ 1067 list_for_each_entry_safe(fcport, tf, &vha->gnl.fcports, 1068 gnl_entry) { 1069 list_del_init(&fcport->gnl_entry); 1070 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1071 if (qla24xx_post_gnl_work(vha, fcport) == QLA_SUCCESS) 1072 break; 1073 } 1074 } 1075 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1076 1077 sp->free(sp); 1078 } 1079 1080 int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport) 1081 { 1082 srb_t *sp; 1083 struct srb_iocb *mbx; 1084 int rval = QLA_FUNCTION_FAILED; 1085 unsigned long flags; 1086 u16 *mb; 1087 1088 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT)) 1089 return rval; 1090 1091 ql_dbg(ql_dbg_disc, vha, 0x20d9, 1092 "Async-gnlist WWPN %8phC \n", fcport->port_name); 1093 1094 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1095 fcport->flags |= FCF_ASYNC_SENT; 1096 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 1097 fcport->last_rscn_gen = fcport->rscn_gen; 1098 fcport->last_login_gen = fcport->login_gen; 1099 1100 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports); 1101 if (vha->gnl.sent) { 1102 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1103 return QLA_SUCCESS; 1104 } 1105 vha->gnl.sent = 1; 1106 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1107 1108 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1109 if (!sp) 1110 goto done; 1111 1112 sp->type = SRB_MB_IOCB; 1113 sp->name = "gnlist"; 1114 sp->gen1 = fcport->rscn_gen; 1115 sp->gen2 = fcport->login_gen; 1116 1117 mbx = &sp->u.iocb_cmd; 1118 mbx->timeout = qla2x00_async_iocb_timeout; 1119 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2); 1120 1121 mb = sp->u.iocb_cmd.u.mbx.out_mb; 1122 mb[0] = MBC_PORT_NODE_NAME_LIST; 1123 mb[1] = BIT_2 | BIT_3; 1124 mb[2] = MSW(vha->gnl.ldma); 1125 mb[3] = LSW(vha->gnl.ldma); 1126 mb[6] = MSW(MSD(vha->gnl.ldma)); 1127 mb[7] = LSW(MSD(vha->gnl.ldma)); 1128 mb[8] = vha->gnl.size; 1129 mb[9] = vha->vp_idx; 1130 1131 sp->done = qla24xx_async_gnl_sp_done; 1132 1133 ql_dbg(ql_dbg_disc, vha, 0x20da, 1134 "Async-%s - OUT WWPN %8phC hndl %x\n", 1135 sp->name, fcport->port_name, sp->handle); 1136 1137 rval = qla2x00_start_sp(sp); 1138 if (rval != QLA_SUCCESS) 1139 goto done_free_sp; 1140 1141 return rval; 1142 1143 done_free_sp: 1144 sp->free(sp); 1145 done: 1146 fcport->flags &= ~(FCF_ASYNC_ACTIVE | FCF_ASYNC_SENT); 1147 return rval; 1148 } 1149 1150 int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport) 1151 { 1152 struct qla_work_evt *e; 1153 1154 e = qla2x00_alloc_work(vha, QLA_EVT_GNL); 1155 if (!e) 1156 return QLA_FUNCTION_FAILED; 1157 1158 e->u.fcport.fcport = fcport; 1159 fcport->flags |= FCF_ASYNC_ACTIVE; 1160 return qla2x00_post_work(vha, e); 1161 } 1162 1163 static void qla24xx_async_gpdb_sp_done(srb_t *sp, int res) 1164 { 1165 struct scsi_qla_host *vha = sp->vha; 1166 struct qla_hw_data *ha = vha->hw; 1167 fc_port_t *fcport = sp->fcport; 1168 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb; 1169 struct event_arg ea; 1170 1171 ql_dbg(ql_dbg_disc, vha, 0x20db, 1172 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n", 1173 sp->name, res, fcport->port_name, mb[1], mb[2]); 1174 1175 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1176 1177 if (res == QLA_FUNCTION_TIMEOUT) 1178 goto done; 1179 1180 memset(&ea, 0, sizeof(ea)); 1181 ea.fcport = fcport; 1182 ea.sp = sp; 1183 1184 qla24xx_handle_gpdb_event(vha, &ea); 1185 1186 done: 1187 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in, 1188 sp->u.iocb_cmd.u.mbx.in_dma); 1189 1190 sp->free(sp); 1191 } 1192 1193 static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport) 1194 { 1195 struct qla_work_evt *e; 1196 1197 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI); 1198 if (!e) 1199 return QLA_FUNCTION_FAILED; 1200 1201 e->u.fcport.fcport = fcport; 1202 1203 return qla2x00_post_work(vha, e); 1204 } 1205 1206 static void qla2x00_async_prli_sp_done(srb_t *sp, int res) 1207 { 1208 struct scsi_qla_host *vha = sp->vha; 1209 struct srb_iocb *lio = &sp->u.iocb_cmd; 1210 struct event_arg ea; 1211 1212 ql_dbg(ql_dbg_disc, vha, 0x2129, 1213 "%s %8phC res %d \n", __func__, 1214 sp->fcport->port_name, res); 1215 1216 sp->fcport->flags &= ~FCF_ASYNC_SENT; 1217 1218 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 1219 memset(&ea, 0, sizeof(ea)); 1220 ea.fcport = sp->fcport; 1221 ea.data[0] = lio->u.logio.data[0]; 1222 ea.data[1] = lio->u.logio.data[1]; 1223 ea.iop[0] = lio->u.logio.iop[0]; 1224 ea.iop[1] = lio->u.logio.iop[1]; 1225 ea.sp = sp; 1226 1227 qla24xx_handle_prli_done_event(vha, &ea); 1228 } 1229 1230 sp->free(sp); 1231 } 1232 1233 int 1234 qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport) 1235 { 1236 srb_t *sp; 1237 struct srb_iocb *lio; 1238 int rval = QLA_FUNCTION_FAILED; 1239 1240 if (!vha->flags.online) { 1241 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n", 1242 __func__, __LINE__, fcport->port_name); 1243 return rval; 1244 } 1245 1246 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND || 1247 fcport->fw_login_state == DSC_LS_PRLI_PEND) && 1248 qla_dual_mode_enabled(vha)) { 1249 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n", 1250 __func__, __LINE__, fcport->port_name); 1251 return rval; 1252 } 1253 1254 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1255 if (!sp) 1256 return rval; 1257 1258 fcport->flags |= FCF_ASYNC_SENT; 1259 fcport->logout_completed = 0; 1260 1261 sp->type = SRB_PRLI_CMD; 1262 sp->name = "prli"; 1263 1264 lio = &sp->u.iocb_cmd; 1265 lio->timeout = qla2x00_async_iocb_timeout; 1266 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 1267 1268 sp->done = qla2x00_async_prli_sp_done; 1269 lio->u.logio.flags = 0; 1270 1271 if (NVME_TARGET(vha->hw, fcport)) 1272 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI; 1273 1274 ql_dbg(ql_dbg_disc, vha, 0x211b, 1275 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d fc4type %x priority %x %s.\n", 1276 fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24, 1277 fcport->login_retry, fcport->fc4_type, vha->hw->fc4_type_priority, 1278 NVME_TARGET(vha->hw, fcport) ? "nvme" : "fcp"); 1279 1280 rval = qla2x00_start_sp(sp); 1281 if (rval != QLA_SUCCESS) { 1282 fcport->flags |= FCF_LOGIN_NEEDED; 1283 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1284 goto done_free_sp; 1285 } 1286 1287 return rval; 1288 1289 done_free_sp: 1290 sp->free(sp); 1291 fcport->flags &= ~FCF_ASYNC_SENT; 1292 return rval; 1293 } 1294 1295 int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 1296 { 1297 struct qla_work_evt *e; 1298 1299 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB); 1300 if (!e) 1301 return QLA_FUNCTION_FAILED; 1302 1303 e->u.fcport.fcport = fcport; 1304 e->u.fcport.opt = opt; 1305 fcport->flags |= FCF_ASYNC_ACTIVE; 1306 return qla2x00_post_work(vha, e); 1307 } 1308 1309 int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 1310 { 1311 srb_t *sp; 1312 struct srb_iocb *mbx; 1313 int rval = QLA_FUNCTION_FAILED; 1314 u16 *mb; 1315 dma_addr_t pd_dma; 1316 struct port_database_24xx *pd; 1317 struct qla_hw_data *ha = vha->hw; 1318 1319 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) || 1320 fcport->loop_id == FC_NO_LOOP_ID) { 1321 ql_log(ql_log_warn, vha, 0xffff, 1322 "%s: %8phC - not sending command.\n", 1323 __func__, fcport->port_name); 1324 return rval; 1325 } 1326 1327 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1328 if (!sp) 1329 goto done; 1330 1331 qla2x00_set_fcport_disc_state(fcport, DSC_GPDB); 1332 1333 fcport->flags |= FCF_ASYNC_SENT; 1334 sp->type = SRB_MB_IOCB; 1335 sp->name = "gpdb"; 1336 sp->gen1 = fcport->rscn_gen; 1337 sp->gen2 = fcport->login_gen; 1338 1339 mbx = &sp->u.iocb_cmd; 1340 mbx->timeout = qla2x00_async_iocb_timeout; 1341 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2); 1342 1343 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1344 if (pd == NULL) { 1345 ql_log(ql_log_warn, vha, 0xd043, 1346 "Failed to allocate port database structure.\n"); 1347 goto done_free_sp; 1348 } 1349 1350 mb = sp->u.iocb_cmd.u.mbx.out_mb; 1351 mb[0] = MBC_GET_PORT_DATABASE; 1352 mb[1] = fcport->loop_id; 1353 mb[2] = MSW(pd_dma); 1354 mb[3] = LSW(pd_dma); 1355 mb[6] = MSW(MSD(pd_dma)); 1356 mb[7] = LSW(MSD(pd_dma)); 1357 mb[9] = vha->vp_idx; 1358 mb[10] = opt; 1359 1360 mbx->u.mbx.in = pd; 1361 mbx->u.mbx.in_dma = pd_dma; 1362 1363 sp->done = qla24xx_async_gpdb_sp_done; 1364 1365 ql_dbg(ql_dbg_disc, vha, 0x20dc, 1366 "Async-%s %8phC hndl %x opt %x\n", 1367 sp->name, fcport->port_name, sp->handle, opt); 1368 1369 rval = qla2x00_start_sp(sp); 1370 if (rval != QLA_SUCCESS) 1371 goto done_free_sp; 1372 return rval; 1373 1374 done_free_sp: 1375 if (pd) 1376 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1377 1378 sp->free(sp); 1379 fcport->flags &= ~FCF_ASYNC_SENT; 1380 done: 1381 fcport->flags &= ~FCF_ASYNC_ACTIVE; 1382 qla24xx_post_gpdb_work(vha, fcport, opt); 1383 return rval; 1384 } 1385 1386 static 1387 void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea) 1388 { 1389 unsigned long flags; 1390 1391 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1392 ea->fcport->login_gen++; 1393 ea->fcport->deleted = 0; 1394 ea->fcport->logout_on_delete = 1; 1395 1396 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) { 1397 vha->fcport_count++; 1398 ea->fcport->login_succ = 1; 1399 1400 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1401 qla24xx_sched_upd_fcport(ea->fcport); 1402 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1403 } else if (ea->fcport->login_succ) { 1404 /* 1405 * We have an existing session. A late RSCN delivery 1406 * must have triggered the session to be re-validate. 1407 * Session is still valid. 1408 */ 1409 ql_dbg(ql_dbg_disc, vha, 0x20d6, 1410 "%s %d %8phC session revalidate success\n", 1411 __func__, __LINE__, ea->fcport->port_name); 1412 qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_COMPLETE); 1413 } 1414 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1415 } 1416 1417 static 1418 void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea) 1419 { 1420 fc_port_t *fcport = ea->fcport; 1421 struct port_database_24xx *pd; 1422 struct srb *sp = ea->sp; 1423 uint8_t ls; 1424 1425 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in; 1426 1427 fcport->flags &= ~FCF_ASYNC_SENT; 1428 1429 ql_dbg(ql_dbg_disc, vha, 0x20d2, 1430 "%s %8phC DS %d LS %d fc4_type %x rc %d\n", __func__, 1431 fcport->port_name, fcport->disc_state, pd->current_login_state, 1432 fcport->fc4_type, ea->rc); 1433 1434 if (fcport->disc_state == DSC_DELETE_PEND) 1435 return; 1436 1437 if (NVME_TARGET(vha->hw, fcport)) 1438 ls = pd->current_login_state >> 4; 1439 else 1440 ls = pd->current_login_state & 0xf; 1441 1442 if (ea->sp->gen2 != fcport->login_gen) { 1443 /* target side must have changed it. */ 1444 1445 ql_dbg(ql_dbg_disc, vha, 0x20d3, 1446 "%s %8phC generation changed\n", 1447 __func__, fcport->port_name); 1448 return; 1449 } else if (ea->sp->gen1 != fcport->rscn_gen) { 1450 qla_rscn_replay(fcport); 1451 qlt_schedule_sess_for_deletion(fcport); 1452 return; 1453 } 1454 1455 switch (ls) { 1456 case PDS_PRLI_COMPLETE: 1457 __qla24xx_parse_gpdb(vha, fcport, pd); 1458 break; 1459 case PDS_PLOGI_PENDING: 1460 case PDS_PLOGI_COMPLETE: 1461 case PDS_PRLI_PENDING: 1462 case PDS_PRLI2_PENDING: 1463 /* Set discovery state back to GNL to Relogin attempt */ 1464 if (qla_dual_mode_enabled(vha) || 1465 qla_ini_mode_enabled(vha)) { 1466 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 1467 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1468 } 1469 return; 1470 case PDS_LOGO_PENDING: 1471 case PDS_PORT_UNAVAILABLE: 1472 default: 1473 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n", 1474 __func__, __LINE__, fcport->port_name); 1475 qlt_schedule_sess_for_deletion(fcport); 1476 return; 1477 } 1478 __qla24xx_handle_gpdb_event(vha, ea); 1479 } /* gpdb event */ 1480 1481 static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport) 1482 { 1483 u8 login = 0; 1484 int rc; 1485 1486 if (qla_tgt_mode_enabled(vha)) 1487 return; 1488 1489 if (qla_dual_mode_enabled(vha)) { 1490 if (N2N_TOPO(vha->hw)) { 1491 u64 mywwn, wwn; 1492 1493 mywwn = wwn_to_u64(vha->port_name); 1494 wwn = wwn_to_u64(fcport->port_name); 1495 if (mywwn > wwn) 1496 login = 1; 1497 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP) 1498 && time_after_eq(jiffies, 1499 fcport->plogi_nack_done_deadline)) 1500 login = 1; 1501 } else { 1502 login = 1; 1503 } 1504 } else { 1505 /* initiator mode */ 1506 login = 1; 1507 } 1508 1509 if (login && fcport->login_retry) { 1510 fcport->login_retry--; 1511 if (fcport->loop_id == FC_NO_LOOP_ID) { 1512 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 1513 rc = qla2x00_find_new_loop_id(vha, fcport); 1514 if (rc) { 1515 ql_dbg(ql_dbg_disc, vha, 0x20e6, 1516 "%s %d %8phC post del sess - out of loopid\n", 1517 __func__, __LINE__, fcport->port_name); 1518 fcport->scan_state = 0; 1519 qlt_schedule_sess_for_deletion(fcport); 1520 return; 1521 } 1522 } 1523 ql_dbg(ql_dbg_disc, vha, 0x20bf, 1524 "%s %d %8phC post login\n", 1525 __func__, __LINE__, fcport->port_name); 1526 qla2x00_post_async_login_work(vha, fcport, NULL); 1527 } 1528 } 1529 1530 int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport) 1531 { 1532 u16 data[2]; 1533 u64 wwn; 1534 u16 sec; 1535 1536 ql_dbg(ql_dbg_disc, vha, 0x20d8, 1537 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d\n", 1538 __func__, fcport->port_name, fcport->disc_state, 1539 fcport->fw_login_state, fcport->login_pause, fcport->flags, 1540 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen, 1541 fcport->login_gen, fcport->loop_id, fcport->scan_state); 1542 1543 if (fcport->scan_state != QLA_FCPORT_FOUND) 1544 return 0; 1545 1546 if ((fcport->loop_id != FC_NO_LOOP_ID) && 1547 qla_dual_mode_enabled(vha) && 1548 ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) || 1549 (fcport->fw_login_state == DSC_LS_PRLI_PEND))) 1550 return 0; 1551 1552 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP && 1553 !N2N_TOPO(vha->hw)) { 1554 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) { 1555 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1556 return 0; 1557 } 1558 } 1559 1560 /* Target won't initiate port login if fabric is present */ 1561 if (vha->host->active_mode == MODE_TARGET && !N2N_TOPO(vha->hw)) 1562 return 0; 1563 1564 if (fcport->flags & FCF_ASYNC_SENT) { 1565 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1566 return 0; 1567 } 1568 1569 switch (fcport->disc_state) { 1570 case DSC_DELETED: 1571 wwn = wwn_to_u64(fcport->node_name); 1572 switch (vha->hw->current_topology) { 1573 case ISP_CFG_N: 1574 if (fcport_is_smaller(fcport)) { 1575 /* this adapter is bigger */ 1576 if (fcport->login_retry) { 1577 if (fcport->loop_id == FC_NO_LOOP_ID) { 1578 qla2x00_find_new_loop_id(vha, 1579 fcport); 1580 fcport->fw_login_state = 1581 DSC_LS_PORT_UNAVAIL; 1582 } 1583 fcport->login_retry--; 1584 qla_post_els_plogi_work(vha, fcport); 1585 } else { 1586 ql_log(ql_log_info, vha, 0x705d, 1587 "Unable to reach remote port %8phC", 1588 fcport->port_name); 1589 } 1590 } else { 1591 qla24xx_post_gnl_work(vha, fcport); 1592 } 1593 break; 1594 default: 1595 if (wwn == 0) { 1596 ql_dbg(ql_dbg_disc, vha, 0xffff, 1597 "%s %d %8phC post GNNID\n", 1598 __func__, __LINE__, fcport->port_name); 1599 qla24xx_post_gnnid_work(vha, fcport); 1600 } else if (fcport->loop_id == FC_NO_LOOP_ID) { 1601 ql_dbg(ql_dbg_disc, vha, 0x20bd, 1602 "%s %d %8phC post gnl\n", 1603 __func__, __LINE__, fcport->port_name); 1604 qla24xx_post_gnl_work(vha, fcport); 1605 } else { 1606 qla_chk_n2n_b4_login(vha, fcport); 1607 } 1608 break; 1609 } 1610 break; 1611 1612 case DSC_GNL: 1613 switch (vha->hw->current_topology) { 1614 case ISP_CFG_N: 1615 if ((fcport->current_login_state & 0xf) == 0x6) { 1616 ql_dbg(ql_dbg_disc, vha, 0x2118, 1617 "%s %d %8phC post GPDB work\n", 1618 __func__, __LINE__, fcport->port_name); 1619 fcport->chip_reset = 1620 vha->hw->base_qpair->chip_reset; 1621 qla24xx_post_gpdb_work(vha, fcport, 0); 1622 } else { 1623 ql_dbg(ql_dbg_disc, vha, 0x2118, 1624 "%s %d %8phC post %s PRLI\n", 1625 __func__, __LINE__, fcport->port_name, 1626 NVME_TARGET(vha->hw, fcport) ? "NVME" : 1627 "FC"); 1628 qla24xx_post_prli_work(vha, fcport); 1629 } 1630 break; 1631 default: 1632 if (fcport->login_pause) { 1633 ql_dbg(ql_dbg_disc, vha, 0x20d8, 1634 "%s %d %8phC exit\n", 1635 __func__, __LINE__, 1636 fcport->port_name); 1637 fcport->last_rscn_gen = fcport->rscn_gen; 1638 fcport->last_login_gen = fcport->login_gen; 1639 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1640 break; 1641 } 1642 qla_chk_n2n_b4_login(vha, fcport); 1643 break; 1644 } 1645 break; 1646 1647 case DSC_LOGIN_FAILED: 1648 if (N2N_TOPO(vha->hw)) 1649 qla_chk_n2n_b4_login(vha, fcport); 1650 else 1651 qlt_schedule_sess_for_deletion(fcport); 1652 break; 1653 1654 case DSC_LOGIN_COMPLETE: 1655 /* recheck login state */ 1656 data[0] = data[1] = 0; 1657 qla2x00_post_async_adisc_work(vha, fcport, data); 1658 break; 1659 1660 case DSC_LOGIN_PEND: 1661 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) 1662 qla24xx_post_prli_work(vha, fcport); 1663 break; 1664 1665 case DSC_UPD_FCPORT: 1666 sec = jiffies_to_msecs(jiffies - 1667 fcport->jiffies_at_registration)/1000; 1668 if (fcport->sec_since_registration < sec && sec && 1669 !(sec % 60)) { 1670 fcport->sec_since_registration = sec; 1671 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff, 1672 "%s %8phC - Slow Rport registration(%d Sec)\n", 1673 __func__, fcport->port_name, sec); 1674 } 1675 1676 if (fcport->next_disc_state != DSC_DELETE_PEND) 1677 fcport->next_disc_state = DSC_ADISC; 1678 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1679 break; 1680 1681 default: 1682 break; 1683 } 1684 1685 return 0; 1686 } 1687 1688 int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id, 1689 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type) 1690 { 1691 struct qla_work_evt *e; 1692 1693 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS); 1694 if (!e) 1695 return QLA_FUNCTION_FAILED; 1696 1697 e->u.new_sess.id = *id; 1698 e->u.new_sess.pla = pla; 1699 e->u.new_sess.fc4_type = fc4_type; 1700 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE); 1701 if (node_name) 1702 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE); 1703 1704 return qla2x00_post_work(vha, e); 1705 } 1706 1707 void qla2x00_handle_rscn(scsi_qla_host_t *vha, struct event_arg *ea) 1708 { 1709 fc_port_t *fcport; 1710 unsigned long flags; 1711 1712 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1); 1713 if (fcport) { 1714 fcport->scan_needed = 1; 1715 fcport->rscn_gen++; 1716 } 1717 1718 spin_lock_irqsave(&vha->work_lock, flags); 1719 if (vha->scan.scan_flags == 0) { 1720 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s: schedule\n", __func__); 1721 vha->scan.scan_flags |= SF_QUEUED; 1722 schedule_delayed_work(&vha->scan.scan_work, 5); 1723 } 1724 spin_unlock_irqrestore(&vha->work_lock, flags); 1725 } 1726 1727 void qla24xx_handle_relogin_event(scsi_qla_host_t *vha, 1728 struct event_arg *ea) 1729 { 1730 fc_port_t *fcport = ea->fcport; 1731 1732 if (test_bit(UNLOADING, &vha->dpc_flags)) 1733 return; 1734 1735 ql_dbg(ql_dbg_disc, vha, 0x2102, 1736 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n", 1737 __func__, fcport->port_name, fcport->disc_state, 1738 fcport->fw_login_state, fcport->login_pause, 1739 fcport->deleted, fcport->conflict, 1740 fcport->last_rscn_gen, fcport->rscn_gen, 1741 fcport->last_login_gen, fcport->login_gen, 1742 fcport->flags); 1743 1744 if (fcport->last_rscn_gen != fcport->rscn_gen) { 1745 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gnl\n", 1746 __func__, __LINE__, fcport->port_name); 1747 qla24xx_post_gnl_work(vha, fcport); 1748 return; 1749 } 1750 1751 qla24xx_fcport_handle_login(vha, fcport); 1752 } 1753 1754 void qla_handle_els_plogi_done(scsi_qla_host_t *vha, 1755 struct event_arg *ea) 1756 { 1757 /* for pure Target Mode, PRLI will not be initiated */ 1758 if (vha->host->active_mode == MODE_TARGET) 1759 return; 1760 1761 ql_dbg(ql_dbg_disc, vha, 0x2118, 1762 "%s %d %8phC post PRLI\n", 1763 __func__, __LINE__, ea->fcport->port_name); 1764 qla24xx_post_prli_work(vha, ea->fcport); 1765 } 1766 1767 /* 1768 * RSCN(s) came in for this fcport, but the RSCN(s) was not able 1769 * to be consumed by the fcport 1770 */ 1771 void qla_rscn_replay(fc_port_t *fcport) 1772 { 1773 struct event_arg ea; 1774 1775 switch (fcport->disc_state) { 1776 case DSC_DELETE_PEND: 1777 return; 1778 default: 1779 break; 1780 } 1781 1782 if (fcport->scan_needed) { 1783 memset(&ea, 0, sizeof(ea)); 1784 ea.id = fcport->d_id; 1785 ea.id.b.rsvd_1 = RSCN_PORT_ADDR; 1786 qla2x00_handle_rscn(fcport->vha, &ea); 1787 } 1788 } 1789 1790 static void 1791 qla2x00_tmf_iocb_timeout(void *data) 1792 { 1793 srb_t *sp = data; 1794 struct srb_iocb *tmf = &sp->u.iocb_cmd; 1795 int rc, h; 1796 unsigned long flags; 1797 1798 rc = qla24xx_async_abort_cmd(sp, false); 1799 if (rc) { 1800 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 1801 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; h++) { 1802 if (sp->qpair->req->outstanding_cmds[h] == sp) { 1803 sp->qpair->req->outstanding_cmds[h] = NULL; 1804 break; 1805 } 1806 } 1807 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 1808 tmf->u.tmf.comp_status = cpu_to_le16(CS_TIMEOUT); 1809 tmf->u.tmf.data = QLA_FUNCTION_FAILED; 1810 complete(&tmf->u.tmf.comp); 1811 } 1812 } 1813 1814 static void qla2x00_tmf_sp_done(srb_t *sp, int res) 1815 { 1816 struct srb_iocb *tmf = &sp->u.iocb_cmd; 1817 1818 complete(&tmf->u.tmf.comp); 1819 } 1820 1821 int 1822 qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun, 1823 uint32_t tag) 1824 { 1825 struct scsi_qla_host *vha = fcport->vha; 1826 struct srb_iocb *tm_iocb; 1827 srb_t *sp; 1828 int rval = QLA_FUNCTION_FAILED; 1829 1830 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1831 if (!sp) 1832 goto done; 1833 1834 tm_iocb = &sp->u.iocb_cmd; 1835 sp->type = SRB_TM_CMD; 1836 sp->name = "tmf"; 1837 1838 tm_iocb->timeout = qla2x00_tmf_iocb_timeout; 1839 init_completion(&tm_iocb->u.tmf.comp); 1840 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)); 1841 1842 tm_iocb->u.tmf.flags = flags; 1843 tm_iocb->u.tmf.lun = lun; 1844 tm_iocb->u.tmf.data = tag; 1845 sp->done = qla2x00_tmf_sp_done; 1846 1847 ql_dbg(ql_dbg_taskm, vha, 0x802f, 1848 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 1849 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 1850 fcport->d_id.b.area, fcport->d_id.b.al_pa); 1851 1852 rval = qla2x00_start_sp(sp); 1853 if (rval != QLA_SUCCESS) 1854 goto done_free_sp; 1855 wait_for_completion(&tm_iocb->u.tmf.comp); 1856 1857 rval = tm_iocb->u.tmf.data; 1858 1859 if (rval != QLA_SUCCESS) { 1860 ql_log(ql_log_warn, vha, 0x8030, 1861 "TM IOCB failed (%x).\n", rval); 1862 } 1863 1864 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) { 1865 flags = tm_iocb->u.tmf.flags; 1866 lun = (uint16_t)tm_iocb->u.tmf.lun; 1867 1868 /* Issue Marker IOCB */ 1869 qla2x00_marker(vha, vha->hw->base_qpair, 1870 fcport->loop_id, lun, 1871 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID); 1872 } 1873 1874 done_free_sp: 1875 sp->free(sp); 1876 fcport->flags &= ~FCF_ASYNC_SENT; 1877 done: 1878 return rval; 1879 } 1880 1881 int 1882 qla24xx_async_abort_command(srb_t *sp) 1883 { 1884 unsigned long flags = 0; 1885 1886 uint32_t handle; 1887 fc_port_t *fcport = sp->fcport; 1888 struct qla_qpair *qpair = sp->qpair; 1889 struct scsi_qla_host *vha = fcport->vha; 1890 struct req_que *req = qpair->req; 1891 1892 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1893 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 1894 if (req->outstanding_cmds[handle] == sp) 1895 break; 1896 } 1897 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1898 1899 if (handle == req->num_outstanding_cmds) { 1900 /* Command not found. */ 1901 return QLA_FUNCTION_FAILED; 1902 } 1903 if (sp->type == SRB_FXIOCB_DCMD) 1904 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport, 1905 FXDISC_ABORT_IOCTL); 1906 1907 return qla24xx_async_abort_cmd(sp, true); 1908 } 1909 1910 static void 1911 qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea) 1912 { 1913 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 1914 ea->data[0]); 1915 1916 switch (ea->data[0]) { 1917 case MBS_COMMAND_COMPLETE: 1918 ql_dbg(ql_dbg_disc, vha, 0x2118, 1919 "%s %d %8phC post gpdb\n", 1920 __func__, __LINE__, ea->fcport->port_name); 1921 1922 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset; 1923 ea->fcport->logout_on_delete = 1; 1924 ea->fcport->nvme_prli_service_param = ea->iop[0]; 1925 if (ea->iop[0] & NVME_PRLI_SP_FIRST_BURST) 1926 ea->fcport->nvme_first_burst_size = 1927 (ea->iop[1] & 0xffff) * 512; 1928 else 1929 ea->fcport->nvme_first_burst_size = 0; 1930 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 1931 break; 1932 default: 1933 if ((ea->iop[0] == LSC_SCODE_ELS_REJECT) && 1934 (ea->iop[1] == 0x50000)) { /* reson 5=busy expl:0x0 */ 1935 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1936 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP; 1937 break; 1938 } 1939 1940 ql_dbg(ql_dbg_disc, vha, 0x2118, 1941 "%s %d %8phC priority %s, fc4type %x\n", 1942 __func__, __LINE__, ea->fcport->port_name, 1943 vha->hw->fc4_type_priority == FC4_PRIORITY_FCP ? 1944 "FCP" : "NVMe", ea->fcport->fc4_type); 1945 1946 if (N2N_TOPO(vha->hw)) { 1947 if (vha->hw->fc4_type_priority == FC4_PRIORITY_NVME) { 1948 ea->fcport->fc4_type &= ~FS_FC4TYPE_NVME; 1949 ea->fcport->fc4_type |= FS_FC4TYPE_FCP; 1950 } else { 1951 ea->fcport->fc4_type &= ~FS_FC4TYPE_FCP; 1952 ea->fcport->fc4_type |= FS_FC4TYPE_NVME; 1953 } 1954 1955 if (ea->fcport->n2n_link_reset_cnt < 3) { 1956 ea->fcport->n2n_link_reset_cnt++; 1957 vha->relogin_jif = jiffies + 2 * HZ; 1958 /* 1959 * PRLI failed. Reset link to kick start 1960 * state machine 1961 */ 1962 set_bit(N2N_LINK_RESET, &vha->dpc_flags); 1963 } else { 1964 ql_log(ql_log_warn, vha, 0x2119, 1965 "%s %d %8phC Unable to reconnect\n", 1966 __func__, __LINE__, 1967 ea->fcport->port_name); 1968 } 1969 } else { 1970 /* 1971 * switch connect. login failed. Take connection down 1972 * and allow relogin to retrigger 1973 */ 1974 if (NVME_FCP_TARGET(ea->fcport)) { 1975 ql_dbg(ql_dbg_disc, vha, 0x2118, 1976 "%s %d %8phC post %s prli\n", 1977 __func__, __LINE__, 1978 ea->fcport->port_name, 1979 (ea->fcport->fc4_type & FS_FC4TYPE_NVME) 1980 ? "NVMe" : "FCP"); 1981 if (vha->hw->fc4_type_priority == FC4_PRIORITY_NVME) 1982 ea->fcport->fc4_type &= ~FS_FC4TYPE_NVME; 1983 else 1984 ea->fcport->fc4_type &= ~FS_FC4TYPE_FCP; 1985 } 1986 1987 ea->fcport->flags &= ~FCF_ASYNC_SENT; 1988 ea->fcport->keep_nport_handle = 0; 1989 ea->fcport->logout_on_delete = 1; 1990 qlt_schedule_sess_for_deletion(ea->fcport); 1991 } 1992 break; 1993 } 1994 } 1995 1996 void 1997 qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea) 1998 { 1999 port_id_t cid; /* conflict Nport id */ 2000 u16 lid; 2001 struct fc_port *conflict_fcport; 2002 unsigned long flags; 2003 struct fc_port *fcport = ea->fcport; 2004 2005 ql_dbg(ql_dbg_disc, vha, 0xffff, 2006 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n", 2007 __func__, fcport->port_name, fcport->disc_state, 2008 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen, 2009 ea->sp->gen1, fcport->rscn_gen, 2010 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]); 2011 2012 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) || 2013 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) { 2014 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2015 "%s %d %8phC Remote is trying to login\n", 2016 __func__, __LINE__, fcport->port_name); 2017 return; 2018 } 2019 2020 if ((fcport->disc_state == DSC_DELETE_PEND) || 2021 (fcport->disc_state == DSC_DELETED)) { 2022 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2023 return; 2024 } 2025 2026 if (ea->sp->gen2 != fcport->login_gen) { 2027 /* target side must have changed it. */ 2028 ql_dbg(ql_dbg_disc, vha, 0x20d3, 2029 "%s %8phC generation changed\n", 2030 __func__, fcport->port_name); 2031 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2032 return; 2033 } else if (ea->sp->gen1 != fcport->rscn_gen) { 2034 ql_dbg(ql_dbg_disc, vha, 0x20d3, 2035 "%s %8phC RSCN generation changed\n", 2036 __func__, fcport->port_name); 2037 qla_rscn_replay(fcport); 2038 qlt_schedule_sess_for_deletion(fcport); 2039 return; 2040 } 2041 2042 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 2043 ea->data[0]); 2044 2045 switch (ea->data[0]) { 2046 case MBS_COMMAND_COMPLETE: 2047 /* 2048 * Driver must validate login state - If PRLI not complete, 2049 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI 2050 * requests. 2051 */ 2052 if (NVME_TARGET(vha->hw, ea->fcport)) { 2053 ql_dbg(ql_dbg_disc, vha, 0x2117, 2054 "%s %d %8phC post prli\n", 2055 __func__, __LINE__, ea->fcport->port_name); 2056 qla24xx_post_prli_work(vha, ea->fcport); 2057 } else { 2058 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2059 "%s %d %8phC LoopID 0x%x in use with %06x. post gpdb\n", 2060 __func__, __LINE__, ea->fcport->port_name, 2061 ea->fcport->loop_id, ea->fcport->d_id.b24); 2062 2063 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map); 2064 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 2065 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset; 2066 ea->fcport->logout_on_delete = 1; 2067 ea->fcport->send_els_logo = 0; 2068 ea->fcport->fw_login_state = DSC_LS_PRLI_COMP; 2069 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 2070 2071 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 2072 } 2073 break; 2074 case MBS_COMMAND_ERROR: 2075 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n", 2076 __func__, __LINE__, ea->fcport->port_name, ea->data[1]); 2077 2078 ea->fcport->flags &= ~FCF_ASYNC_SENT; 2079 qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_FAILED); 2080 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED) 2081 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2082 else 2083 qla2x00_mark_device_lost(vha, ea->fcport, 1); 2084 break; 2085 case MBS_LOOP_ID_USED: 2086 /* data[1] = IO PARAM 1 = nport ID */ 2087 cid.b.domain = (ea->iop[1] >> 16) & 0xff; 2088 cid.b.area = (ea->iop[1] >> 8) & 0xff; 2089 cid.b.al_pa = ea->iop[1] & 0xff; 2090 cid.b.rsvd_1 = 0; 2091 2092 ql_dbg(ql_dbg_disc, vha, 0x20ec, 2093 "%s %d %8phC lid %#x in use with pid %06x post gnl\n", 2094 __func__, __LINE__, ea->fcport->port_name, 2095 ea->fcport->loop_id, cid.b24); 2096 2097 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map); 2098 ea->fcport->loop_id = FC_NO_LOOP_ID; 2099 qla24xx_post_gnl_work(vha, ea->fcport); 2100 break; 2101 case MBS_PORT_ID_USED: 2102 lid = ea->iop[1] & 0xffff; 2103 qlt_find_sess_invalidate_other(vha, 2104 wwn_to_u64(ea->fcport->port_name), 2105 ea->fcport->d_id, lid, &conflict_fcport); 2106 2107 if (conflict_fcport) { 2108 /* 2109 * Another fcport share the same loop_id/nport id. 2110 * Conflict fcport needs to finish cleanup before this 2111 * fcport can proceed to login. 2112 */ 2113 conflict_fcport->conflict = ea->fcport; 2114 ea->fcport->login_pause = 1; 2115 2116 ql_dbg(ql_dbg_disc, vha, 0x20ed, 2117 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n", 2118 __func__, __LINE__, ea->fcport->port_name, 2119 ea->fcport->d_id.b24, lid); 2120 } else { 2121 ql_dbg(ql_dbg_disc, vha, 0x20ed, 2122 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n", 2123 __func__, __LINE__, ea->fcport->port_name, 2124 ea->fcport->d_id.b24, lid); 2125 2126 qla2x00_clear_loop_id(ea->fcport); 2127 set_bit(lid, vha->hw->loop_id_map); 2128 ea->fcport->loop_id = lid; 2129 ea->fcport->keep_nport_handle = 0; 2130 ea->fcport->logout_on_delete = 1; 2131 qlt_schedule_sess_for_deletion(ea->fcport); 2132 } 2133 break; 2134 } 2135 return; 2136 } 2137 2138 /****************************************************************************/ 2139 /* QLogic ISP2x00 Hardware Support Functions. */ 2140 /****************************************************************************/ 2141 2142 static int 2143 qla83xx_nic_core_fw_load(scsi_qla_host_t *vha) 2144 { 2145 int rval = QLA_SUCCESS; 2146 struct qla_hw_data *ha = vha->hw; 2147 uint32_t idc_major_ver, idc_minor_ver; 2148 uint16_t config[4]; 2149 2150 qla83xx_idc_lock(vha, 0); 2151 2152 /* SV: TODO: Assign initialization timeout from 2153 * flash-info / other param 2154 */ 2155 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT; 2156 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT; 2157 2158 /* Set our fcoe function presence */ 2159 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) { 2160 ql_dbg(ql_dbg_p3p, vha, 0xb077, 2161 "Error while setting DRV-Presence.\n"); 2162 rval = QLA_FUNCTION_FAILED; 2163 goto exit; 2164 } 2165 2166 /* Decide the reset ownership */ 2167 qla83xx_reset_ownership(vha); 2168 2169 /* 2170 * On first protocol driver load: 2171 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery 2172 * register. 2173 * Others: Check compatibility with current IDC Major version. 2174 */ 2175 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver); 2176 if (ha->flags.nic_core_reset_owner) { 2177 /* Set IDC Major version */ 2178 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION; 2179 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver); 2180 2181 /* Clearing IDC-Lock-Recovery register */ 2182 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0); 2183 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) { 2184 /* 2185 * Clear further IDC participation if we are not compatible with 2186 * the current IDC Major Version. 2187 */ 2188 ql_log(ql_log_warn, vha, 0xb07d, 2189 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n", 2190 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION); 2191 __qla83xx_clear_drv_presence(vha); 2192 rval = QLA_FUNCTION_FAILED; 2193 goto exit; 2194 } 2195 /* Each function sets its supported Minor version. */ 2196 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver); 2197 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2)); 2198 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver); 2199 2200 if (ha->flags.nic_core_reset_owner) { 2201 memset(config, 0, sizeof(config)); 2202 if (!qla81xx_get_port_config(vha, config)) 2203 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 2204 QLA8XXX_DEV_READY); 2205 } 2206 2207 rval = qla83xx_idc_state_handler(vha); 2208 2209 exit: 2210 qla83xx_idc_unlock(vha, 0); 2211 2212 return rval; 2213 } 2214 2215 /* 2216 * qla2x00_initialize_adapter 2217 * Initialize board. 2218 * 2219 * Input: 2220 * ha = adapter block pointer. 2221 * 2222 * Returns: 2223 * 0 = success 2224 */ 2225 int 2226 qla2x00_initialize_adapter(scsi_qla_host_t *vha) 2227 { 2228 int rval; 2229 struct qla_hw_data *ha = vha->hw; 2230 struct req_que *req = ha->req_q_map[0]; 2231 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2232 2233 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats)); 2234 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat)); 2235 2236 /* Clear adapter flags. */ 2237 vha->flags.online = 0; 2238 ha->flags.chip_reset_done = 0; 2239 vha->flags.reset_active = 0; 2240 ha->flags.pci_channel_io_perm_failure = 0; 2241 ha->flags.eeh_busy = 0; 2242 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64(); 2243 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 2244 atomic_set(&vha->loop_state, LOOP_DOWN); 2245 vha->device_flags = DFLG_NO_CABLE; 2246 vha->dpc_flags = 0; 2247 vha->flags.management_server_logged_in = 0; 2248 vha->marker_needed = 0; 2249 ha->isp_abort_cnt = 0; 2250 ha->beacon_blink_led = 0; 2251 2252 set_bit(0, ha->req_qid_map); 2253 set_bit(0, ha->rsp_qid_map); 2254 2255 ql_dbg(ql_dbg_init, vha, 0x0040, 2256 "Configuring PCI space...\n"); 2257 rval = ha->isp_ops->pci_config(vha); 2258 if (rval) { 2259 ql_log(ql_log_warn, vha, 0x0044, 2260 "Unable to configure PCI space.\n"); 2261 return (rval); 2262 } 2263 2264 ha->isp_ops->reset_chip(vha); 2265 2266 /* Check for secure flash support */ 2267 if (IS_QLA28XX(ha)) { 2268 if (rd_reg_word(®->mailbox12) & BIT_0) 2269 ha->flags.secure_adapter = 1; 2270 ql_log(ql_log_info, vha, 0xffff, "Secure Adapter: %s\n", 2271 (ha->flags.secure_adapter) ? "Yes" : "No"); 2272 } 2273 2274 2275 rval = qla2xxx_get_flash_info(vha); 2276 if (rval) { 2277 ql_log(ql_log_fatal, vha, 0x004f, 2278 "Unable to validate FLASH data.\n"); 2279 return rval; 2280 } 2281 2282 if (IS_QLA8044(ha)) { 2283 qla8044_read_reset_template(vha); 2284 2285 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0. 2286 * If DONRESET_BIT0 is set, drivers should not set dev_state 2287 * to NEED_RESET. But if NEED_RESET is set, drivers should 2288 * should honor the reset. */ 2289 if (ql2xdontresethba == 1) 2290 qla8044_set_idc_dontreset(vha); 2291 } 2292 2293 ha->isp_ops->get_flash_version(vha, req->ring); 2294 ql_dbg(ql_dbg_init, vha, 0x0061, 2295 "Configure NVRAM parameters...\n"); 2296 2297 /* Let priority default to FCP, can be overridden by nvram_config */ 2298 ha->fc4_type_priority = FC4_PRIORITY_FCP; 2299 2300 ha->isp_ops->nvram_config(vha); 2301 2302 if (ha->fc4_type_priority != FC4_PRIORITY_FCP && 2303 ha->fc4_type_priority != FC4_PRIORITY_NVME) 2304 ha->fc4_type_priority = FC4_PRIORITY_FCP; 2305 2306 ql_log(ql_log_info, vha, 0xffff, "FC4 priority set to %s\n", 2307 ha->fc4_type_priority == FC4_PRIORITY_FCP ? "FCP" : "NVMe"); 2308 2309 if (ha->flags.disable_serdes) { 2310 /* Mask HBA via NVRAM settings? */ 2311 ql_log(ql_log_info, vha, 0x0077, 2312 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name); 2313 return QLA_FUNCTION_FAILED; 2314 } 2315 2316 ql_dbg(ql_dbg_init, vha, 0x0078, 2317 "Verifying loaded RISC code...\n"); 2318 2319 /* If smartsan enabled then require fdmi and rdp enabled */ 2320 if (ql2xsmartsan) { 2321 ql2xfdmienable = 1; 2322 ql2xrdpenable = 1; 2323 } 2324 2325 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) { 2326 rval = ha->isp_ops->chip_diag(vha); 2327 if (rval) 2328 return (rval); 2329 rval = qla2x00_setup_chip(vha); 2330 if (rval) 2331 return (rval); 2332 } 2333 2334 if (IS_QLA84XX(ha)) { 2335 ha->cs84xx = qla84xx_get_chip(vha); 2336 if (!ha->cs84xx) { 2337 ql_log(ql_log_warn, vha, 0x00d0, 2338 "Unable to configure ISP84XX.\n"); 2339 return QLA_FUNCTION_FAILED; 2340 } 2341 } 2342 2343 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha)) 2344 rval = qla2x00_init_rings(vha); 2345 2346 /* No point in continuing if firmware initialization failed. */ 2347 if (rval != QLA_SUCCESS) 2348 return rval; 2349 2350 ha->flags.chip_reset_done = 1; 2351 2352 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) { 2353 /* Issue verify 84xx FW IOCB to complete 84xx initialization */ 2354 rval = qla84xx_init_chip(vha); 2355 if (rval != QLA_SUCCESS) { 2356 ql_log(ql_log_warn, vha, 0x00d4, 2357 "Unable to initialize ISP84XX.\n"); 2358 qla84xx_put_chip(vha); 2359 } 2360 } 2361 2362 /* Load the NIC Core f/w if we are the first protocol driver. */ 2363 if (IS_QLA8031(ha)) { 2364 rval = qla83xx_nic_core_fw_load(vha); 2365 if (rval) 2366 ql_log(ql_log_warn, vha, 0x0124, 2367 "Error in initializing NIC Core f/w.\n"); 2368 } 2369 2370 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)) 2371 qla24xx_read_fcp_prio_cfg(vha); 2372 2373 if (IS_P3P_TYPE(ha)) 2374 qla82xx_set_driver_version(vha, QLA2XXX_VERSION); 2375 else 2376 qla25xx_set_driver_version(vha, QLA2XXX_VERSION); 2377 2378 return (rval); 2379 } 2380 2381 /** 2382 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers. 2383 * @vha: HA context 2384 * 2385 * Returns 0 on success. 2386 */ 2387 int 2388 qla2100_pci_config(scsi_qla_host_t *vha) 2389 { 2390 uint16_t w; 2391 unsigned long flags; 2392 struct qla_hw_data *ha = vha->hw; 2393 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2394 2395 pci_set_master(ha->pdev); 2396 pci_try_set_mwi(ha->pdev); 2397 2398 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2399 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2400 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2401 2402 pci_disable_rom(ha->pdev); 2403 2404 /* Get PCI bus information. */ 2405 spin_lock_irqsave(&ha->hardware_lock, flags); 2406 ha->pci_attr = rd_reg_word(®->ctrl_status); 2407 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2408 2409 return QLA_SUCCESS; 2410 } 2411 2412 /** 2413 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers. 2414 * @vha: HA context 2415 * 2416 * Returns 0 on success. 2417 */ 2418 int 2419 qla2300_pci_config(scsi_qla_host_t *vha) 2420 { 2421 uint16_t w; 2422 unsigned long flags = 0; 2423 uint32_t cnt; 2424 struct qla_hw_data *ha = vha->hw; 2425 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2426 2427 pci_set_master(ha->pdev); 2428 pci_try_set_mwi(ha->pdev); 2429 2430 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2431 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2432 2433 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2434 w &= ~PCI_COMMAND_INTX_DISABLE; 2435 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2436 2437 /* 2438 * If this is a 2300 card and not 2312, reset the 2439 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately, 2440 * the 2310 also reports itself as a 2300 so we need to get the 2441 * fb revision level -- a 6 indicates it really is a 2300 and 2442 * not a 2310. 2443 */ 2444 if (IS_QLA2300(ha)) { 2445 spin_lock_irqsave(&ha->hardware_lock, flags); 2446 2447 /* Pause RISC. */ 2448 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2449 for (cnt = 0; cnt < 30000; cnt++) { 2450 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) 2451 break; 2452 2453 udelay(10); 2454 } 2455 2456 /* Select FPM registers. */ 2457 wrt_reg_word(®->ctrl_status, 0x20); 2458 rd_reg_word(®->ctrl_status); 2459 2460 /* Get the fb rev level */ 2461 ha->fb_rev = RD_FB_CMD_REG(ha, reg); 2462 2463 if (ha->fb_rev == FPM_2300) 2464 pci_clear_mwi(ha->pdev); 2465 2466 /* Deselect FPM registers. */ 2467 wrt_reg_word(®->ctrl_status, 0x0); 2468 rd_reg_word(®->ctrl_status); 2469 2470 /* Release RISC module. */ 2471 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 2472 for (cnt = 0; cnt < 30000; cnt++) { 2473 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0) 2474 break; 2475 2476 udelay(10); 2477 } 2478 2479 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2480 } 2481 2482 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 2483 2484 pci_disable_rom(ha->pdev); 2485 2486 /* Get PCI bus information. */ 2487 spin_lock_irqsave(&ha->hardware_lock, flags); 2488 ha->pci_attr = rd_reg_word(®->ctrl_status); 2489 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2490 2491 return QLA_SUCCESS; 2492 } 2493 2494 /** 2495 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers. 2496 * @vha: HA context 2497 * 2498 * Returns 0 on success. 2499 */ 2500 int 2501 qla24xx_pci_config(scsi_qla_host_t *vha) 2502 { 2503 uint16_t w; 2504 unsigned long flags = 0; 2505 struct qla_hw_data *ha = vha->hw; 2506 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2507 2508 pci_set_master(ha->pdev); 2509 pci_try_set_mwi(ha->pdev); 2510 2511 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2512 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2513 w &= ~PCI_COMMAND_INTX_DISABLE; 2514 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2515 2516 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 2517 2518 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ 2519 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) 2520 pcix_set_mmrbc(ha->pdev, 2048); 2521 2522 /* PCIe -- adjust Maximum Read Request Size (2048). */ 2523 if (pci_is_pcie(ha->pdev)) 2524 pcie_set_readrq(ha->pdev, 4096); 2525 2526 pci_disable_rom(ha->pdev); 2527 2528 ha->chip_revision = ha->pdev->revision; 2529 2530 /* Get PCI bus information. */ 2531 spin_lock_irqsave(&ha->hardware_lock, flags); 2532 ha->pci_attr = rd_reg_dword(®->ctrl_status); 2533 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2534 2535 return QLA_SUCCESS; 2536 } 2537 2538 /** 2539 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. 2540 * @vha: HA context 2541 * 2542 * Returns 0 on success. 2543 */ 2544 int 2545 qla25xx_pci_config(scsi_qla_host_t *vha) 2546 { 2547 uint16_t w; 2548 struct qla_hw_data *ha = vha->hw; 2549 2550 pci_set_master(ha->pdev); 2551 pci_try_set_mwi(ha->pdev); 2552 2553 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2554 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2555 w &= ~PCI_COMMAND_INTX_DISABLE; 2556 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2557 2558 /* PCIe -- adjust Maximum Read Request Size (2048). */ 2559 if (pci_is_pcie(ha->pdev)) 2560 pcie_set_readrq(ha->pdev, 4096); 2561 2562 pci_disable_rom(ha->pdev); 2563 2564 ha->chip_revision = ha->pdev->revision; 2565 2566 return QLA_SUCCESS; 2567 } 2568 2569 /** 2570 * qla2x00_isp_firmware() - Choose firmware image. 2571 * @vha: HA context 2572 * 2573 * Returns 0 on success. 2574 */ 2575 static int 2576 qla2x00_isp_firmware(scsi_qla_host_t *vha) 2577 { 2578 int rval; 2579 uint16_t loop_id, topo, sw_cap; 2580 uint8_t domain, area, al_pa; 2581 struct qla_hw_data *ha = vha->hw; 2582 2583 /* Assume loading risc code */ 2584 rval = QLA_FUNCTION_FAILED; 2585 2586 if (ha->flags.disable_risc_code_load) { 2587 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n"); 2588 2589 /* Verify checksum of loaded RISC code. */ 2590 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address); 2591 if (rval == QLA_SUCCESS) { 2592 /* And, verify we are not in ROM code. */ 2593 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa, 2594 &area, &domain, &topo, &sw_cap); 2595 } 2596 } 2597 2598 if (rval) 2599 ql_dbg(ql_dbg_init, vha, 0x007a, 2600 "**** Load RISC code ****.\n"); 2601 2602 return (rval); 2603 } 2604 2605 /** 2606 * qla2x00_reset_chip() - Reset ISP chip. 2607 * @vha: HA context 2608 * 2609 * Returns 0 on success. 2610 */ 2611 int 2612 qla2x00_reset_chip(scsi_qla_host_t *vha) 2613 { 2614 unsigned long flags = 0; 2615 struct qla_hw_data *ha = vha->hw; 2616 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2617 uint32_t cnt; 2618 uint16_t cmd; 2619 int rval = QLA_FUNCTION_FAILED; 2620 2621 if (unlikely(pci_channel_offline(ha->pdev))) 2622 return rval; 2623 2624 ha->isp_ops->disable_intrs(ha); 2625 2626 spin_lock_irqsave(&ha->hardware_lock, flags); 2627 2628 /* Turn off master enable */ 2629 cmd = 0; 2630 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd); 2631 cmd &= ~PCI_COMMAND_MASTER; 2632 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 2633 2634 if (!IS_QLA2100(ha)) { 2635 /* Pause RISC. */ 2636 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2637 if (IS_QLA2200(ha) || IS_QLA2300(ha)) { 2638 for (cnt = 0; cnt < 30000; cnt++) { 2639 if ((rd_reg_word(®->hccr) & 2640 HCCR_RISC_PAUSE) != 0) 2641 break; 2642 udelay(100); 2643 } 2644 } else { 2645 rd_reg_word(®->hccr); /* PCI Posting. */ 2646 udelay(10); 2647 } 2648 2649 /* Select FPM registers. */ 2650 wrt_reg_word(®->ctrl_status, 0x20); 2651 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2652 2653 /* FPM Soft Reset. */ 2654 wrt_reg_word(®->fpm_diag_config, 0x100); 2655 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */ 2656 2657 /* Toggle Fpm Reset. */ 2658 if (!IS_QLA2200(ha)) { 2659 wrt_reg_word(®->fpm_diag_config, 0x0); 2660 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */ 2661 } 2662 2663 /* Select frame buffer registers. */ 2664 wrt_reg_word(®->ctrl_status, 0x10); 2665 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2666 2667 /* Reset frame buffer FIFOs. */ 2668 if (IS_QLA2200(ha)) { 2669 WRT_FB_CMD_REG(ha, reg, 0xa000); 2670 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ 2671 } else { 2672 WRT_FB_CMD_REG(ha, reg, 0x00fc); 2673 2674 /* Read back fb_cmd until zero or 3 seconds max */ 2675 for (cnt = 0; cnt < 3000; cnt++) { 2676 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) 2677 break; 2678 udelay(100); 2679 } 2680 } 2681 2682 /* Select RISC module registers. */ 2683 wrt_reg_word(®->ctrl_status, 0); 2684 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2685 2686 /* Reset RISC processor. */ 2687 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 2688 rd_reg_word(®->hccr); /* PCI Posting. */ 2689 2690 /* Release RISC processor. */ 2691 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 2692 rd_reg_word(®->hccr); /* PCI Posting. */ 2693 } 2694 2695 wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT); 2696 wrt_reg_word(®->hccr, HCCR_CLR_HOST_INT); 2697 2698 /* Reset ISP chip. */ 2699 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 2700 2701 /* Wait for RISC to recover from reset. */ 2702 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2703 /* 2704 * It is necessary to for a delay here since the card doesn't 2705 * respond to PCI reads during a reset. On some architectures 2706 * this will result in an MCA. 2707 */ 2708 udelay(20); 2709 for (cnt = 30000; cnt; cnt--) { 2710 if ((rd_reg_word(®->ctrl_status) & 2711 CSR_ISP_SOFT_RESET) == 0) 2712 break; 2713 udelay(100); 2714 } 2715 } else 2716 udelay(10); 2717 2718 /* Reset RISC processor. */ 2719 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 2720 2721 wrt_reg_word(®->semaphore, 0); 2722 2723 /* Release RISC processor. */ 2724 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 2725 rd_reg_word(®->hccr); /* PCI Posting. */ 2726 2727 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2728 for (cnt = 0; cnt < 30000; cnt++) { 2729 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) 2730 break; 2731 2732 udelay(100); 2733 } 2734 } else 2735 udelay(100); 2736 2737 /* Turn on master enable */ 2738 cmd |= PCI_COMMAND_MASTER; 2739 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 2740 2741 /* Disable RISC pause on FPM parity error. */ 2742 if (!IS_QLA2100(ha)) { 2743 wrt_reg_word(®->hccr, HCCR_DISABLE_PARITY_PAUSE); 2744 rd_reg_word(®->hccr); /* PCI Posting. */ 2745 } 2746 2747 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2748 2749 return QLA_SUCCESS; 2750 } 2751 2752 /** 2753 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC. 2754 * @vha: HA context 2755 * 2756 * Returns 0 on success. 2757 */ 2758 static int 2759 qla81xx_reset_mpi(scsi_qla_host_t *vha) 2760 { 2761 uint16_t mb[4] = {0x1010, 0, 1, 0}; 2762 2763 if (!IS_QLA81XX(vha->hw)) 2764 return QLA_SUCCESS; 2765 2766 return qla81xx_write_mpi_register(vha, mb); 2767 } 2768 2769 /** 2770 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. 2771 * @vha: HA context 2772 * 2773 * Returns 0 on success. 2774 */ 2775 static inline int 2776 qla24xx_reset_risc(scsi_qla_host_t *vha) 2777 { 2778 unsigned long flags = 0; 2779 struct qla_hw_data *ha = vha->hw; 2780 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2781 uint32_t cnt; 2782 uint16_t wd; 2783 static int abts_cnt; /* ISP abort retry counts */ 2784 int rval = QLA_SUCCESS; 2785 2786 spin_lock_irqsave(&ha->hardware_lock, flags); 2787 2788 /* Reset RISC. */ 2789 wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 2790 for (cnt = 0; cnt < 30000; cnt++) { 2791 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 2792 break; 2793 2794 udelay(10); 2795 } 2796 2797 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)) 2798 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); 2799 2800 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e, 2801 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n", 2802 rd_reg_dword(®->hccr), 2803 rd_reg_dword(®->ctrl_status), 2804 (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)); 2805 2806 wrt_reg_dword(®->ctrl_status, 2807 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 2808 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2809 2810 udelay(100); 2811 2812 /* Wait for firmware to complete NVRAM accesses. */ 2813 rd_reg_word(®->mailbox0); 2814 for (cnt = 10000; rd_reg_word(®->mailbox0) != 0 && 2815 rval == QLA_SUCCESS; cnt--) { 2816 barrier(); 2817 if (cnt) 2818 udelay(5); 2819 else 2820 rval = QLA_FUNCTION_TIMEOUT; 2821 } 2822 2823 if (rval == QLA_SUCCESS) 2824 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags); 2825 2826 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f, 2827 "HCCR: 0x%x, MailBox0 Status 0x%x\n", 2828 rd_reg_dword(®->hccr), 2829 rd_reg_word(®->mailbox0)); 2830 2831 /* Wait for soft-reset to complete. */ 2832 rd_reg_dword(®->ctrl_status); 2833 for (cnt = 0; cnt < 60; cnt++) { 2834 barrier(); 2835 if ((rd_reg_dword(®->ctrl_status) & 2836 CSRX_ISP_SOFT_RESET) == 0) 2837 break; 2838 2839 udelay(5); 2840 } 2841 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) 2842 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags); 2843 2844 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d, 2845 "HCCR: 0x%x, Soft Reset status: 0x%x\n", 2846 rd_reg_dword(®->hccr), 2847 rd_reg_dword(®->ctrl_status)); 2848 2849 /* If required, do an MPI FW reset now */ 2850 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) { 2851 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) { 2852 if (++abts_cnt < 5) { 2853 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2854 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags); 2855 } else { 2856 /* 2857 * We exhausted the ISP abort retries. We have to 2858 * set the board offline. 2859 */ 2860 abts_cnt = 0; 2861 vha->flags.online = 0; 2862 } 2863 } 2864 } 2865 2866 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET); 2867 rd_reg_dword(®->hccr); 2868 2869 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE); 2870 rd_reg_dword(®->hccr); 2871 2872 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET); 2873 rd_reg_dword(®->hccr); 2874 2875 rd_reg_word(®->mailbox0); 2876 for (cnt = 60; rd_reg_word(®->mailbox0) != 0 && 2877 rval == QLA_SUCCESS; cnt--) { 2878 barrier(); 2879 if (cnt) 2880 udelay(5); 2881 else 2882 rval = QLA_FUNCTION_TIMEOUT; 2883 } 2884 if (rval == QLA_SUCCESS) 2885 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); 2886 2887 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e, 2888 "Host Risc 0x%x, mailbox0 0x%x\n", 2889 rd_reg_dword(®->hccr), 2890 rd_reg_word(®->mailbox0)); 2891 2892 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2893 2894 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f, 2895 "Driver in %s mode\n", 2896 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling"); 2897 2898 if (IS_NOPOLLING_TYPE(ha)) 2899 ha->isp_ops->enable_intrs(ha); 2900 2901 return rval; 2902 } 2903 2904 static void 2905 qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) 2906 { 2907 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 2908 2909 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 2910 *data = rd_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET); 2911 } 2912 2913 static void 2914 qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) 2915 { 2916 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 2917 2918 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 2919 wrt_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET, data); 2920 } 2921 2922 static void 2923 qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) 2924 { 2925 uint32_t wd32 = 0; 2926 uint delta_msec = 100; 2927 uint elapsed_msec = 0; 2928 uint timeout_msec; 2929 ulong n; 2930 2931 if (vha->hw->pdev->subsystem_device != 0x0175 && 2932 vha->hw->pdev->subsystem_device != 0x0240) 2933 return; 2934 2935 wrt_reg_dword(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE); 2936 udelay(100); 2937 2938 attempt: 2939 timeout_msec = TIMEOUT_SEMAPHORE; 2940 n = timeout_msec / delta_msec; 2941 while (n--) { 2942 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET); 2943 qla25xx_read_risc_sema_reg(vha, &wd32); 2944 if (wd32 & RISC_SEMAPHORE) 2945 break; 2946 msleep(delta_msec); 2947 elapsed_msec += delta_msec; 2948 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 2949 goto force; 2950 } 2951 2952 if (!(wd32 & RISC_SEMAPHORE)) 2953 goto force; 2954 2955 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 2956 goto acquired; 2957 2958 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR); 2959 timeout_msec = TIMEOUT_SEMAPHORE_FORCE; 2960 n = timeout_msec / delta_msec; 2961 while (n--) { 2962 qla25xx_read_risc_sema_reg(vha, &wd32); 2963 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 2964 break; 2965 msleep(delta_msec); 2966 elapsed_msec += delta_msec; 2967 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 2968 goto force; 2969 } 2970 2971 if (wd32 & RISC_SEMAPHORE_FORCE) 2972 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR); 2973 2974 goto attempt; 2975 2976 force: 2977 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET); 2978 2979 acquired: 2980 return; 2981 } 2982 2983 /** 2984 * qla24xx_reset_chip() - Reset ISP24xx chip. 2985 * @vha: HA context 2986 * 2987 * Returns 0 on success. 2988 */ 2989 int 2990 qla24xx_reset_chip(scsi_qla_host_t *vha) 2991 { 2992 struct qla_hw_data *ha = vha->hw; 2993 int rval = QLA_FUNCTION_FAILED; 2994 2995 if (pci_channel_offline(ha->pdev) && 2996 ha->flags.pci_channel_io_perm_failure) { 2997 return rval; 2998 } 2999 3000 ha->isp_ops->disable_intrs(ha); 3001 3002 qla25xx_manipulate_risc_semaphore(vha); 3003 3004 /* Perform RISC reset. */ 3005 rval = qla24xx_reset_risc(vha); 3006 3007 return rval; 3008 } 3009 3010 /** 3011 * qla2x00_chip_diag() - Test chip for proper operation. 3012 * @vha: HA context 3013 * 3014 * Returns 0 on success. 3015 */ 3016 int 3017 qla2x00_chip_diag(scsi_qla_host_t *vha) 3018 { 3019 int rval; 3020 struct qla_hw_data *ha = vha->hw; 3021 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3022 unsigned long flags = 0; 3023 uint16_t data; 3024 uint32_t cnt; 3025 uint16_t mb[5]; 3026 struct req_que *req = ha->req_q_map[0]; 3027 3028 /* Assume a failed state */ 3029 rval = QLA_FUNCTION_FAILED; 3030 3031 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n", 3032 ®->flash_address); 3033 3034 spin_lock_irqsave(&ha->hardware_lock, flags); 3035 3036 /* Reset ISP chip. */ 3037 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 3038 3039 /* 3040 * We need to have a delay here since the card will not respond while 3041 * in reset causing an MCA on some architectures. 3042 */ 3043 udelay(20); 3044 data = qla2x00_debounce_register(®->ctrl_status); 3045 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) { 3046 udelay(5); 3047 data = rd_reg_word(®->ctrl_status); 3048 barrier(); 3049 } 3050 3051 if (!cnt) 3052 goto chip_diag_failed; 3053 3054 ql_dbg(ql_dbg_init, vha, 0x007c, 3055 "Reset register cleared by chip reset.\n"); 3056 3057 /* Reset RISC processor. */ 3058 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 3059 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 3060 3061 /* Workaround for QLA2312 PCI parity error */ 3062 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 3063 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); 3064 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) { 3065 udelay(5); 3066 data = RD_MAILBOX_REG(ha, reg, 0); 3067 barrier(); 3068 } 3069 } else 3070 udelay(10); 3071 3072 if (!cnt) 3073 goto chip_diag_failed; 3074 3075 /* Check product ID of chip */ 3076 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n"); 3077 3078 mb[1] = RD_MAILBOX_REG(ha, reg, 1); 3079 mb[2] = RD_MAILBOX_REG(ha, reg, 2); 3080 mb[3] = RD_MAILBOX_REG(ha, reg, 3); 3081 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); 3082 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) || 3083 mb[3] != PROD_ID_3) { 3084 ql_log(ql_log_warn, vha, 0x0062, 3085 "Wrong product ID = 0x%x,0x%x,0x%x.\n", 3086 mb[1], mb[2], mb[3]); 3087 3088 goto chip_diag_failed; 3089 } 3090 ha->product_id[0] = mb[1]; 3091 ha->product_id[1] = mb[2]; 3092 ha->product_id[2] = mb[3]; 3093 ha->product_id[3] = mb[4]; 3094 3095 /* Adjust fw RISC transfer size */ 3096 if (req->length > 1024) 3097 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; 3098 else 3099 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 3100 req->length; 3101 3102 if (IS_QLA2200(ha) && 3103 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { 3104 /* Limit firmware transfer size with a 2200A */ 3105 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n"); 3106 3107 ha->device_type |= DT_ISP2200A; 3108 ha->fw_transfer_size = 128; 3109 } 3110 3111 /* Wrap Incoming Mailboxes Test. */ 3112 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3113 3114 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n"); 3115 rval = qla2x00_mbx_reg_test(vha); 3116 if (rval) 3117 ql_log(ql_log_warn, vha, 0x0080, 3118 "Failed mailbox send register test.\n"); 3119 else 3120 /* Flag a successful rval */ 3121 rval = QLA_SUCCESS; 3122 spin_lock_irqsave(&ha->hardware_lock, flags); 3123 3124 chip_diag_failed: 3125 if (rval) 3126 ql_log(ql_log_info, vha, 0x0081, 3127 "Chip diagnostics **** FAILED ****.\n"); 3128 3129 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3130 3131 return (rval); 3132 } 3133 3134 /** 3135 * qla24xx_chip_diag() - Test ISP24xx for proper operation. 3136 * @vha: HA context 3137 * 3138 * Returns 0 on success. 3139 */ 3140 int 3141 qla24xx_chip_diag(scsi_qla_host_t *vha) 3142 { 3143 int rval; 3144 struct qla_hw_data *ha = vha->hw; 3145 struct req_que *req = ha->req_q_map[0]; 3146 3147 if (IS_P3P_TYPE(ha)) 3148 return QLA_SUCCESS; 3149 3150 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; 3151 3152 rval = qla2x00_mbx_reg_test(vha); 3153 if (rval) { 3154 ql_log(ql_log_warn, vha, 0x0082, 3155 "Failed mailbox send register test.\n"); 3156 } else { 3157 /* Flag a successful rval */ 3158 rval = QLA_SUCCESS; 3159 } 3160 3161 return rval; 3162 } 3163 3164 static void 3165 qla2x00_init_fce_trace(scsi_qla_host_t *vha) 3166 { 3167 int rval; 3168 dma_addr_t tc_dma; 3169 void *tc; 3170 struct qla_hw_data *ha = vha->hw; 3171 3172 if (!IS_FWI2_CAPABLE(ha)) 3173 return; 3174 3175 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 3176 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 3177 return; 3178 3179 if (ha->fce) { 3180 ql_dbg(ql_dbg_init, vha, 0x00bd, 3181 "%s: FCE Mem is already allocated.\n", 3182 __func__); 3183 return; 3184 } 3185 3186 /* Allocate memory for Fibre Channel Event Buffer. */ 3187 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, 3188 GFP_KERNEL); 3189 if (!tc) { 3190 ql_log(ql_log_warn, vha, 0x00be, 3191 "Unable to allocate (%d KB) for FCE.\n", 3192 FCE_SIZE / 1024); 3193 return; 3194 } 3195 3196 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS, 3197 ha->fce_mb, &ha->fce_bufs); 3198 if (rval) { 3199 ql_log(ql_log_warn, vha, 0x00bf, 3200 "Unable to initialize FCE (%d).\n", rval); 3201 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc, tc_dma); 3202 return; 3203 } 3204 3205 ql_dbg(ql_dbg_init, vha, 0x00c0, 3206 "Allocated (%d KB) for FCE...\n", FCE_SIZE / 1024); 3207 3208 ha->flags.fce_enabled = 1; 3209 ha->fce_dma = tc_dma; 3210 ha->fce = tc; 3211 } 3212 3213 static void 3214 qla2x00_init_eft_trace(scsi_qla_host_t *vha) 3215 { 3216 int rval; 3217 dma_addr_t tc_dma; 3218 void *tc; 3219 struct qla_hw_data *ha = vha->hw; 3220 3221 if (!IS_FWI2_CAPABLE(ha)) 3222 return; 3223 3224 if (ha->eft) { 3225 ql_dbg(ql_dbg_init, vha, 0x00bd, 3226 "%s: EFT Mem is already allocated.\n", 3227 __func__); 3228 return; 3229 } 3230 3231 /* Allocate memory for Extended Trace Buffer. */ 3232 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma, 3233 GFP_KERNEL); 3234 if (!tc) { 3235 ql_log(ql_log_warn, vha, 0x00c1, 3236 "Unable to allocate (%d KB) for EFT.\n", 3237 EFT_SIZE / 1024); 3238 return; 3239 } 3240 3241 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS); 3242 if (rval) { 3243 ql_log(ql_log_warn, vha, 0x00c2, 3244 "Unable to initialize EFT (%d).\n", rval); 3245 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc, tc_dma); 3246 return; 3247 } 3248 3249 ql_dbg(ql_dbg_init, vha, 0x00c3, 3250 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024); 3251 3252 ha->eft_dma = tc_dma; 3253 ha->eft = tc; 3254 } 3255 3256 static void 3257 qla2x00_alloc_offload_mem(scsi_qla_host_t *vha) 3258 { 3259 qla2x00_init_fce_trace(vha); 3260 qla2x00_init_eft_trace(vha); 3261 } 3262 3263 void 3264 qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) 3265 { 3266 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, 3267 eft_size, fce_size, mq_size; 3268 struct qla_hw_data *ha = vha->hw; 3269 struct req_que *req = ha->req_q_map[0]; 3270 struct rsp_que *rsp = ha->rsp_q_map[0]; 3271 struct qla2xxx_fw_dump *fw_dump; 3272 3273 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; 3274 req_q_size = rsp_q_size = 0; 3275 3276 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3277 fixed_size = sizeof(struct qla2100_fw_dump); 3278 } else if (IS_QLA23XX(ha)) { 3279 fixed_size = offsetof(struct qla2300_fw_dump, data_ram); 3280 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 3281 sizeof(uint16_t); 3282 } else if (IS_FWI2_CAPABLE(ha)) { 3283 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3284 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem); 3285 else if (IS_QLA81XX(ha)) 3286 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); 3287 else if (IS_QLA25XX(ha)) 3288 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); 3289 else 3290 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); 3291 3292 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 3293 sizeof(uint32_t); 3294 if (ha->mqenable) { 3295 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && 3296 !IS_QLA28XX(ha)) 3297 mq_size = sizeof(struct qla2xxx_mq_chain); 3298 /* 3299 * Allocate maximum buffer size for all queues - Q0. 3300 * Resizing must be done at end-of-dump processing. 3301 */ 3302 mq_size += (ha->max_req_queues - 1) * 3303 (req->length * sizeof(request_t)); 3304 mq_size += (ha->max_rsp_queues - 1) * 3305 (rsp->length * sizeof(response_t)); 3306 } 3307 if (ha->tgt.atio_ring) 3308 mq_size += ha->tgt.atio_q_length * sizeof(request_t); 3309 3310 qla2x00_init_fce_trace(vha); 3311 if (ha->fce) 3312 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE; 3313 qla2x00_init_eft_trace(vha); 3314 if (ha->eft) 3315 eft_size = EFT_SIZE; 3316 } 3317 3318 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3319 struct fwdt *fwdt = ha->fwdt; 3320 uint j; 3321 3322 for (j = 0; j < 2; j++, fwdt++) { 3323 if (!fwdt->template) { 3324 ql_dbg(ql_dbg_init, vha, 0x00ba, 3325 "-> fwdt%u no template\n", j); 3326 continue; 3327 } 3328 ql_dbg(ql_dbg_init, vha, 0x00fa, 3329 "-> fwdt%u calculating fwdump size...\n", j); 3330 fwdt->dump_size = qla27xx_fwdt_calculate_dump_size( 3331 vha, fwdt->template); 3332 ql_dbg(ql_dbg_init, vha, 0x00fa, 3333 "-> fwdt%u calculated fwdump size = %#lx bytes\n", 3334 j, fwdt->dump_size); 3335 dump_size += fwdt->dump_size; 3336 } 3337 /* Add space for spare MPI fw dump. */ 3338 dump_size += ha->fwdt[1].dump_size; 3339 } else { 3340 req_q_size = req->length * sizeof(request_t); 3341 rsp_q_size = rsp->length * sizeof(response_t); 3342 dump_size = offsetof(struct qla2xxx_fw_dump, isp); 3343 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size 3344 + eft_size; 3345 ha->chain_offset = dump_size; 3346 dump_size += mq_size + fce_size; 3347 if (ha->exchoffld_buf) 3348 dump_size += sizeof(struct qla2xxx_offld_chain) + 3349 ha->exchoffld_size; 3350 if (ha->exlogin_buf) 3351 dump_size += sizeof(struct qla2xxx_offld_chain) + 3352 ha->exlogin_size; 3353 } 3354 3355 if (!ha->fw_dump_len || dump_size > ha->fw_dump_alloc_len) { 3356 3357 ql_dbg(ql_dbg_init, vha, 0x00c5, 3358 "%s dump_size %d fw_dump_len %d fw_dump_alloc_len %d\n", 3359 __func__, dump_size, ha->fw_dump_len, 3360 ha->fw_dump_alloc_len); 3361 3362 fw_dump = vmalloc(dump_size); 3363 if (!fw_dump) { 3364 ql_log(ql_log_warn, vha, 0x00c4, 3365 "Unable to allocate (%d KB) for firmware dump.\n", 3366 dump_size / 1024); 3367 } else { 3368 mutex_lock(&ha->optrom_mutex); 3369 if (ha->fw_dumped) { 3370 memcpy(fw_dump, ha->fw_dump, ha->fw_dump_len); 3371 vfree(ha->fw_dump); 3372 ha->fw_dump = fw_dump; 3373 ha->fw_dump_alloc_len = dump_size; 3374 ql_dbg(ql_dbg_init, vha, 0x00c5, 3375 "Re-Allocated (%d KB) and save firmware dump.\n", 3376 dump_size / 1024); 3377 } else { 3378 vfree(ha->fw_dump); 3379 ha->fw_dump = fw_dump; 3380 3381 ha->fw_dump_len = ha->fw_dump_alloc_len = 3382 dump_size; 3383 ql_dbg(ql_dbg_init, vha, 0x00c5, 3384 "Allocated (%d KB) for firmware dump.\n", 3385 dump_size / 1024); 3386 3387 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3388 ha->mpi_fw_dump = (char *)fw_dump + 3389 ha->fwdt[1].dump_size; 3390 mutex_unlock(&ha->optrom_mutex); 3391 return; 3392 } 3393 3394 ha->fw_dump->signature[0] = 'Q'; 3395 ha->fw_dump->signature[1] = 'L'; 3396 ha->fw_dump->signature[2] = 'G'; 3397 ha->fw_dump->signature[3] = 'C'; 3398 ha->fw_dump->version = htonl(1); 3399 3400 ha->fw_dump->fixed_size = htonl(fixed_size); 3401 ha->fw_dump->mem_size = htonl(mem_size); 3402 ha->fw_dump->req_q_size = htonl(req_q_size); 3403 ha->fw_dump->rsp_q_size = htonl(rsp_q_size); 3404 3405 ha->fw_dump->eft_size = htonl(eft_size); 3406 ha->fw_dump->eft_addr_l = 3407 htonl(LSD(ha->eft_dma)); 3408 ha->fw_dump->eft_addr_h = 3409 htonl(MSD(ha->eft_dma)); 3410 3411 ha->fw_dump->header_size = 3412 htonl(offsetof 3413 (struct qla2xxx_fw_dump, isp)); 3414 } 3415 mutex_unlock(&ha->optrom_mutex); 3416 } 3417 } 3418 } 3419 3420 static int 3421 qla81xx_mpi_sync(scsi_qla_host_t *vha) 3422 { 3423 #define MPS_MASK 0xe0 3424 int rval; 3425 uint16_t dc; 3426 uint32_t dw; 3427 3428 if (!IS_QLA81XX(vha->hw)) 3429 return QLA_SUCCESS; 3430 3431 rval = qla2x00_write_ram_word(vha, 0x7c00, 1); 3432 if (rval != QLA_SUCCESS) { 3433 ql_log(ql_log_warn, vha, 0x0105, 3434 "Unable to acquire semaphore.\n"); 3435 goto done; 3436 } 3437 3438 pci_read_config_word(vha->hw->pdev, 0x54, &dc); 3439 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw); 3440 if (rval != QLA_SUCCESS) { 3441 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n"); 3442 goto done_release; 3443 } 3444 3445 dc &= MPS_MASK; 3446 if (dc == (dw & MPS_MASK)) 3447 goto done_release; 3448 3449 dw &= ~MPS_MASK; 3450 dw |= dc; 3451 rval = qla2x00_write_ram_word(vha, 0x7a15, dw); 3452 if (rval != QLA_SUCCESS) { 3453 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n"); 3454 } 3455 3456 done_release: 3457 rval = qla2x00_write_ram_word(vha, 0x7c00, 0); 3458 if (rval != QLA_SUCCESS) { 3459 ql_log(ql_log_warn, vha, 0x006d, 3460 "Unable to release semaphore.\n"); 3461 } 3462 3463 done: 3464 return rval; 3465 } 3466 3467 int 3468 qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req) 3469 { 3470 /* Don't try to reallocate the array */ 3471 if (req->outstanding_cmds) 3472 return QLA_SUCCESS; 3473 3474 if (!IS_FWI2_CAPABLE(ha)) 3475 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS; 3476 else { 3477 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count) 3478 req->num_outstanding_cmds = ha->cur_fw_xcb_count; 3479 else 3480 req->num_outstanding_cmds = ha->cur_fw_iocb_count; 3481 } 3482 3483 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds, 3484 sizeof(srb_t *), 3485 GFP_KERNEL); 3486 3487 if (!req->outstanding_cmds) { 3488 /* 3489 * Try to allocate a minimal size just so we can get through 3490 * initialization. 3491 */ 3492 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS; 3493 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds, 3494 sizeof(srb_t *), 3495 GFP_KERNEL); 3496 3497 if (!req->outstanding_cmds) { 3498 ql_log(ql_log_fatal, NULL, 0x0126, 3499 "Failed to allocate memory for " 3500 "outstanding_cmds for req_que %p.\n", req); 3501 req->num_outstanding_cmds = 0; 3502 return QLA_FUNCTION_FAILED; 3503 } 3504 } 3505 3506 return QLA_SUCCESS; 3507 } 3508 3509 #define PRINT_FIELD(_field, _flag, _str) { \ 3510 if (a0->_field & _flag) {\ 3511 if (p) {\ 3512 strcat(ptr, "|");\ 3513 ptr++;\ 3514 leftover--;\ 3515 } \ 3516 len = snprintf(ptr, leftover, "%s", _str); \ 3517 p = 1;\ 3518 leftover -= len;\ 3519 ptr += len; \ 3520 } \ 3521 } 3522 3523 static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha) 3524 { 3525 #define STR_LEN 64 3526 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data; 3527 u8 str[STR_LEN], *ptr, p; 3528 int leftover, len; 3529 3530 memset(str, 0, STR_LEN); 3531 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name); 3532 ql_dbg(ql_dbg_init, vha, 0x015a, 3533 "SFP MFG Name: %s\n", str); 3534 3535 memset(str, 0, STR_LEN); 3536 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn); 3537 ql_dbg(ql_dbg_init, vha, 0x015c, 3538 "SFP Part Name: %s\n", str); 3539 3540 /* media */ 3541 memset(str, 0, STR_LEN); 3542 ptr = str; 3543 leftover = STR_LEN; 3544 p = len = 0; 3545 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX"); 3546 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair"); 3547 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax"); 3548 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax"); 3549 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um"); 3550 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um"); 3551 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode"); 3552 ql_dbg(ql_dbg_init, vha, 0x0160, 3553 "SFP Media: %s\n", str); 3554 3555 /* link length */ 3556 memset(str, 0, STR_LEN); 3557 ptr = str; 3558 leftover = STR_LEN; 3559 p = len = 0; 3560 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long"); 3561 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short"); 3562 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate"); 3563 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long"); 3564 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium"); 3565 ql_dbg(ql_dbg_init, vha, 0x0196, 3566 "SFP Link Length: %s\n", str); 3567 3568 memset(str, 0, STR_LEN); 3569 ptr = str; 3570 leftover = STR_LEN; 3571 p = len = 0; 3572 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)"); 3573 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)"); 3574 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)"); 3575 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)"); 3576 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)"); 3577 ql_dbg(ql_dbg_init, vha, 0x016e, 3578 "SFP FC Link Tech: %s\n", str); 3579 3580 if (a0->length_km) 3581 ql_dbg(ql_dbg_init, vha, 0x016f, 3582 "SFP Distant: %d km\n", a0->length_km); 3583 if (a0->length_100m) 3584 ql_dbg(ql_dbg_init, vha, 0x0170, 3585 "SFP Distant: %d m\n", a0->length_100m*100); 3586 if (a0->length_50um_10m) 3587 ql_dbg(ql_dbg_init, vha, 0x0189, 3588 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10); 3589 if (a0->length_62um_10m) 3590 ql_dbg(ql_dbg_init, vha, 0x018a, 3591 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10); 3592 if (a0->length_om4_10m) 3593 ql_dbg(ql_dbg_init, vha, 0x0194, 3594 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10); 3595 if (a0->length_om3_10m) 3596 ql_dbg(ql_dbg_init, vha, 0x0195, 3597 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10); 3598 } 3599 3600 3601 /** 3602 * qla24xx_detect_sfp() 3603 * 3604 * @vha: adapter state pointer. 3605 * 3606 * @return 3607 * 0 -- Configure firmware to use short-range settings -- normal 3608 * buffer-to-buffer credits. 3609 * 3610 * 1 -- Configure firmware to use long-range settings -- extra 3611 * buffer-to-buffer credits should be allocated with 3612 * ha->lr_distance containing distance settings from NVRAM or SFP 3613 * (if supported). 3614 */ 3615 int 3616 qla24xx_detect_sfp(scsi_qla_host_t *vha) 3617 { 3618 int rc, used_nvram; 3619 struct sff_8247_a0 *a; 3620 struct qla_hw_data *ha = vha->hw; 3621 struct nvram_81xx *nv = ha->nvram; 3622 #define LR_DISTANCE_UNKNOWN 2 3623 static const char * const types[] = { "Short", "Long" }; 3624 static const char * const lengths[] = { "(10km)", "(5km)", "" }; 3625 u8 ll = 0; 3626 3627 /* Seed with NVRAM settings. */ 3628 used_nvram = 0; 3629 ha->flags.lr_detected = 0; 3630 if (IS_BPM_RANGE_CAPABLE(ha) && 3631 (nv->enhanced_features & NEF_LR_DIST_ENABLE)) { 3632 used_nvram = 1; 3633 ha->flags.lr_detected = 1; 3634 ha->lr_distance = 3635 (nv->enhanced_features >> LR_DIST_NV_POS) 3636 & LR_DIST_NV_MASK; 3637 } 3638 3639 if (!IS_BPM_ENABLED(vha)) 3640 goto out; 3641 /* Determine SR/LR capabilities of SFP/Transceiver. */ 3642 rc = qla2x00_read_sfp_dev(vha, NULL, 0); 3643 if (rc) 3644 goto out; 3645 3646 used_nvram = 0; 3647 a = (struct sff_8247_a0 *)vha->hw->sfp_data; 3648 qla2xxx_print_sfp_info(vha); 3649 3650 ha->flags.lr_detected = 0; 3651 ll = a->fc_ll_cc7; 3652 if (ll & FC_LL_VL || ll & FC_LL_L) { 3653 /* Long range, track length. */ 3654 ha->flags.lr_detected = 1; 3655 3656 if (a->length_km > 5 || a->length_100m > 50) 3657 ha->lr_distance = LR_DISTANCE_10K; 3658 else 3659 ha->lr_distance = LR_DISTANCE_5K; 3660 } 3661 3662 out: 3663 ql_dbg(ql_dbg_async, vha, 0x507b, 3664 "SFP detect: %s-Range SFP %s (nvr=%x ll=%x lr=%x lrd=%x).\n", 3665 types[ha->flags.lr_detected], 3666 ha->flags.lr_detected ? lengths[ha->lr_distance] : 3667 lengths[LR_DISTANCE_UNKNOWN], 3668 used_nvram, ll, ha->flags.lr_detected, ha->lr_distance); 3669 return ha->flags.lr_detected; 3670 } 3671 3672 void qla_init_iocb_limit(scsi_qla_host_t *vha) 3673 { 3674 u16 i, num_qps; 3675 u32 limit; 3676 struct qla_hw_data *ha = vha->hw; 3677 3678 num_qps = ha->num_qpairs + 1; 3679 limit = (ha->orig_fw_iocb_count * QLA_IOCB_PCT_LIMIT) / 100; 3680 3681 ha->base_qpair->fwres.iocbs_total = ha->orig_fw_iocb_count; 3682 ha->base_qpair->fwres.iocbs_limit = limit; 3683 ha->base_qpair->fwres.iocbs_qp_limit = limit / num_qps; 3684 ha->base_qpair->fwres.iocbs_used = 0; 3685 for (i = 0; i < ha->max_qpairs; i++) { 3686 if (ha->queue_pair_map[i]) { 3687 ha->queue_pair_map[i]->fwres.iocbs_total = 3688 ha->orig_fw_iocb_count; 3689 ha->queue_pair_map[i]->fwres.iocbs_limit = limit; 3690 ha->queue_pair_map[i]->fwres.iocbs_qp_limit = 3691 limit / num_qps; 3692 ha->queue_pair_map[i]->fwres.iocbs_used = 0; 3693 } 3694 } 3695 } 3696 3697 /** 3698 * qla2x00_setup_chip() - Load and start RISC firmware. 3699 * @vha: HA context 3700 * 3701 * Returns 0 on success. 3702 */ 3703 static int 3704 qla2x00_setup_chip(scsi_qla_host_t *vha) 3705 { 3706 int rval; 3707 uint32_t srisc_address = 0; 3708 struct qla_hw_data *ha = vha->hw; 3709 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3710 unsigned long flags; 3711 uint16_t fw_major_version; 3712 int done_once = 0; 3713 3714 if (IS_P3P_TYPE(ha)) { 3715 rval = ha->isp_ops->load_risc(vha, &srisc_address); 3716 if (rval == QLA_SUCCESS) { 3717 qla2x00_stop_firmware(vha); 3718 goto enable_82xx_npiv; 3719 } else 3720 goto failed; 3721 } 3722 3723 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 3724 /* Disable SRAM, Instruction RAM and GP RAM parity. */ 3725 spin_lock_irqsave(&ha->hardware_lock, flags); 3726 wrt_reg_word(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); 3727 rd_reg_word(®->hccr); 3728 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3729 } 3730 3731 qla81xx_mpi_sync(vha); 3732 3733 execute_fw_with_lr: 3734 /* Load firmware sequences */ 3735 rval = ha->isp_ops->load_risc(vha, &srisc_address); 3736 if (rval == QLA_SUCCESS) { 3737 ql_dbg(ql_dbg_init, vha, 0x00c9, 3738 "Verifying Checksum of loaded RISC code.\n"); 3739 3740 rval = qla2x00_verify_checksum(vha, srisc_address); 3741 if (rval == QLA_SUCCESS) { 3742 /* Start firmware execution. */ 3743 ql_dbg(ql_dbg_init, vha, 0x00ca, 3744 "Starting firmware.\n"); 3745 3746 if (ql2xexlogins) 3747 ha->flags.exlogins_enabled = 1; 3748 3749 if (qla_is_exch_offld_enabled(vha)) 3750 ha->flags.exchoffld_enabled = 1; 3751 3752 rval = qla2x00_execute_fw(vha, srisc_address); 3753 /* Retrieve firmware information. */ 3754 if (rval == QLA_SUCCESS) { 3755 /* Enable BPM support? */ 3756 if (!done_once++ && qla24xx_detect_sfp(vha)) { 3757 ql_dbg(ql_dbg_init, vha, 0x00ca, 3758 "Re-starting firmware -- BPM.\n"); 3759 /* Best-effort - re-init. */ 3760 ha->isp_ops->reset_chip(vha); 3761 ha->isp_ops->chip_diag(vha); 3762 goto execute_fw_with_lr; 3763 } 3764 3765 if (IS_ZIO_THRESHOLD_CAPABLE(ha)) 3766 qla27xx_set_zio_threshold(vha, 3767 ha->last_zio_threshold); 3768 3769 rval = qla2x00_set_exlogins_buffer(vha); 3770 if (rval != QLA_SUCCESS) 3771 goto failed; 3772 3773 rval = qla2x00_set_exchoffld_buffer(vha); 3774 if (rval != QLA_SUCCESS) 3775 goto failed; 3776 3777 enable_82xx_npiv: 3778 fw_major_version = ha->fw_major_version; 3779 if (IS_P3P_TYPE(ha)) 3780 qla82xx_check_md_needed(vha); 3781 else 3782 rval = qla2x00_get_fw_version(vha); 3783 if (rval != QLA_SUCCESS) 3784 goto failed; 3785 ha->flags.npiv_supported = 0; 3786 if (IS_QLA2XXX_MIDTYPE(ha) && 3787 (ha->fw_attributes & BIT_2)) { 3788 ha->flags.npiv_supported = 1; 3789 if ((!ha->max_npiv_vports) || 3790 ((ha->max_npiv_vports + 1) % 3791 MIN_MULTI_ID_FABRIC)) 3792 ha->max_npiv_vports = 3793 MIN_MULTI_ID_FABRIC - 1; 3794 } 3795 qla2x00_get_resource_cnts(vha); 3796 qla_init_iocb_limit(vha); 3797 3798 /* 3799 * Allocate the array of outstanding commands 3800 * now that we know the firmware resources. 3801 */ 3802 rval = qla2x00_alloc_outstanding_cmds(ha, 3803 vha->req); 3804 if (rval != QLA_SUCCESS) 3805 goto failed; 3806 3807 if (!fw_major_version && !(IS_P3P_TYPE(ha))) 3808 qla2x00_alloc_offload_mem(vha); 3809 3810 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha))) 3811 qla2x00_alloc_fw_dump(vha); 3812 3813 } else { 3814 goto failed; 3815 } 3816 } else { 3817 ql_log(ql_log_fatal, vha, 0x00cd, 3818 "ISP Firmware failed checksum.\n"); 3819 goto failed; 3820 } 3821 3822 /* Enable PUREX PASSTHRU */ 3823 if (ql2xrdpenable || ha->flags.scm_supported_f) 3824 qla25xx_set_els_cmds_supported(vha); 3825 } else 3826 goto failed; 3827 3828 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 3829 /* Enable proper parity. */ 3830 spin_lock_irqsave(&ha->hardware_lock, flags); 3831 if (IS_QLA2300(ha)) 3832 /* SRAM parity */ 3833 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x1); 3834 else 3835 /* SRAM, Instruction RAM and GP RAM parity */ 3836 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x7); 3837 rd_reg_word(®->hccr); 3838 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3839 } 3840 3841 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3842 ha->flags.fac_supported = 1; 3843 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { 3844 uint32_t size; 3845 3846 rval = qla81xx_fac_get_sector_size(vha, &size); 3847 if (rval == QLA_SUCCESS) { 3848 ha->flags.fac_supported = 1; 3849 ha->fdt_block_size = size << 2; 3850 } else { 3851 ql_log(ql_log_warn, vha, 0x00ce, 3852 "Unsupported FAC firmware (%d.%02d.%02d).\n", 3853 ha->fw_major_version, ha->fw_minor_version, 3854 ha->fw_subminor_version); 3855 3856 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3857 IS_QLA28XX(ha)) { 3858 ha->flags.fac_supported = 0; 3859 rval = QLA_SUCCESS; 3860 } 3861 } 3862 } 3863 failed: 3864 if (rval) { 3865 ql_log(ql_log_fatal, vha, 0x00cf, 3866 "Setup chip ****FAILED****.\n"); 3867 } 3868 3869 return (rval); 3870 } 3871 3872 /** 3873 * qla2x00_init_response_q_entries() - Initializes response queue entries. 3874 * @rsp: response queue 3875 * 3876 * Beginning of request ring has initialization control block already built 3877 * by nvram config routine. 3878 * 3879 * Returns 0 on success. 3880 */ 3881 void 3882 qla2x00_init_response_q_entries(struct rsp_que *rsp) 3883 { 3884 uint16_t cnt; 3885 response_t *pkt; 3886 3887 rsp->ring_ptr = rsp->ring; 3888 rsp->ring_index = 0; 3889 rsp->status_srb = NULL; 3890 pkt = rsp->ring_ptr; 3891 for (cnt = 0; cnt < rsp->length; cnt++) { 3892 pkt->signature = RESPONSE_PROCESSED; 3893 pkt++; 3894 } 3895 } 3896 3897 /** 3898 * qla2x00_update_fw_options() - Read and process firmware options. 3899 * @vha: HA context 3900 * 3901 * Returns 0 on success. 3902 */ 3903 void 3904 qla2x00_update_fw_options(scsi_qla_host_t *vha) 3905 { 3906 uint16_t swing, emphasis, tx_sens, rx_sens; 3907 struct qla_hw_data *ha = vha->hw; 3908 3909 memset(ha->fw_options, 0, sizeof(ha->fw_options)); 3910 qla2x00_get_fw_options(vha, ha->fw_options); 3911 3912 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 3913 return; 3914 3915 /* Serial Link options. */ 3916 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115, 3917 "Serial link options.\n"); 3918 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109, 3919 ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options)); 3920 3921 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 3922 if (ha->fw_seriallink_options[3] & BIT_2) { 3923 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING; 3924 3925 /* 1G settings */ 3926 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); 3927 emphasis = (ha->fw_seriallink_options[2] & 3928 (BIT_4 | BIT_3)) >> 3; 3929 tx_sens = ha->fw_seriallink_options[0] & 3930 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 3931 rx_sens = (ha->fw_seriallink_options[0] & 3932 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 3933 ha->fw_options[10] = (emphasis << 14) | (swing << 8); 3934 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 3935 if (rx_sens == 0x0) 3936 rx_sens = 0x3; 3937 ha->fw_options[10] |= (tx_sens << 4) | rx_sens; 3938 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3939 ha->fw_options[10] |= BIT_5 | 3940 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 3941 (tx_sens & (BIT_1 | BIT_0)); 3942 3943 /* 2G settings */ 3944 swing = (ha->fw_seriallink_options[2] & 3945 (BIT_7 | BIT_6 | BIT_5)) >> 5; 3946 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); 3947 tx_sens = ha->fw_seriallink_options[1] & 3948 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 3949 rx_sens = (ha->fw_seriallink_options[1] & 3950 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 3951 ha->fw_options[11] = (emphasis << 14) | (swing << 8); 3952 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 3953 if (rx_sens == 0x0) 3954 rx_sens = 0x3; 3955 ha->fw_options[11] |= (tx_sens << 4) | rx_sens; 3956 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3957 ha->fw_options[11] |= BIT_5 | 3958 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 3959 (tx_sens & (BIT_1 | BIT_0)); 3960 } 3961 3962 /* FCP2 options. */ 3963 /* Return command IOCBs without waiting for an ABTS to complete. */ 3964 ha->fw_options[3] |= BIT_13; 3965 3966 /* LED scheme. */ 3967 if (ha->flags.enable_led_scheme) 3968 ha->fw_options[2] |= BIT_12; 3969 3970 /* Detect ISP6312. */ 3971 if (IS_QLA6312(ha)) 3972 ha->fw_options[2] |= BIT_13; 3973 3974 /* Set Retry FLOGI in case of P2P connection */ 3975 if (ha->operating_mode == P2P) { 3976 ha->fw_options[2] |= BIT_3; 3977 ql_dbg(ql_dbg_disc, vha, 0x2100, 3978 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 3979 __func__, ha->fw_options[2]); 3980 } 3981 3982 /* Update firmware options. */ 3983 qla2x00_set_fw_options(vha, ha->fw_options); 3984 } 3985 3986 void 3987 qla24xx_update_fw_options(scsi_qla_host_t *vha) 3988 { 3989 int rval; 3990 struct qla_hw_data *ha = vha->hw; 3991 3992 if (IS_P3P_TYPE(ha)) 3993 return; 3994 3995 /* Hold status IOCBs until ABTS response received. */ 3996 if (ql2xfwholdabts) 3997 ha->fw_options[3] |= BIT_12; 3998 3999 /* Set Retry FLOGI in case of P2P connection */ 4000 if (ha->operating_mode == P2P) { 4001 ha->fw_options[2] |= BIT_3; 4002 ql_dbg(ql_dbg_disc, vha, 0x2101, 4003 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 4004 __func__, ha->fw_options[2]); 4005 } 4006 4007 /* Move PUREX, ABTS RX & RIDA to ATIOQ */ 4008 if (ql2xmvasynctoatio && 4009 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) { 4010 if (qla_tgt_mode_enabled(vha) || 4011 qla_dual_mode_enabled(vha)) 4012 ha->fw_options[2] |= BIT_11; 4013 else 4014 ha->fw_options[2] &= ~BIT_11; 4015 } 4016 4017 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 4018 IS_QLA28XX(ha)) { 4019 /* 4020 * Tell FW to track each exchange to prevent 4021 * driver from using stale exchange. 4022 */ 4023 if (qla_tgt_mode_enabled(vha) || 4024 qla_dual_mode_enabled(vha)) 4025 ha->fw_options[2] |= BIT_4; 4026 else 4027 ha->fw_options[2] &= ~BIT_4; 4028 4029 /* Reserve 1/2 of emergency exchanges for ELS.*/ 4030 if (qla2xuseresexchforels) 4031 ha->fw_options[2] |= BIT_8; 4032 else 4033 ha->fw_options[2] &= ~BIT_8; 4034 } 4035 4036 if (ql2xrdpenable || ha->flags.scm_supported_f) 4037 ha->fw_options[1] |= ADD_FO1_ENABLE_PUREX_IOCB; 4038 4039 /* Enable Async 8130/8131 events -- transceiver insertion/removal */ 4040 if (IS_BPM_RANGE_CAPABLE(ha)) 4041 ha->fw_options[3] |= BIT_10; 4042 4043 ql_dbg(ql_dbg_init, vha, 0x00e8, 4044 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n", 4045 __func__, ha->fw_options[1], ha->fw_options[2], 4046 ha->fw_options[3], vha->host->active_mode); 4047 4048 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3]) 4049 qla2x00_set_fw_options(vha, ha->fw_options); 4050 4051 /* Update Serial Link options. */ 4052 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) 4053 return; 4054 4055 rval = qla2x00_set_serdes_params(vha, 4056 le16_to_cpu(ha->fw_seriallink_options24[1]), 4057 le16_to_cpu(ha->fw_seriallink_options24[2]), 4058 le16_to_cpu(ha->fw_seriallink_options24[3])); 4059 if (rval != QLA_SUCCESS) { 4060 ql_log(ql_log_warn, vha, 0x0104, 4061 "Unable to update Serial Link options (%x).\n", rval); 4062 } 4063 } 4064 4065 void 4066 qla2x00_config_rings(struct scsi_qla_host *vha) 4067 { 4068 struct qla_hw_data *ha = vha->hw; 4069 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4070 struct req_que *req = ha->req_q_map[0]; 4071 struct rsp_que *rsp = ha->rsp_q_map[0]; 4072 4073 /* Setup ring parameters in initialization control block. */ 4074 ha->init_cb->request_q_outpointer = cpu_to_le16(0); 4075 ha->init_cb->response_q_inpointer = cpu_to_le16(0); 4076 ha->init_cb->request_q_length = cpu_to_le16(req->length); 4077 ha->init_cb->response_q_length = cpu_to_le16(rsp->length); 4078 put_unaligned_le64(req->dma, &ha->init_cb->request_q_address); 4079 put_unaligned_le64(rsp->dma, &ha->init_cb->response_q_address); 4080 4081 wrt_reg_word(ISP_REQ_Q_IN(ha, reg), 0); 4082 wrt_reg_word(ISP_REQ_Q_OUT(ha, reg), 0); 4083 wrt_reg_word(ISP_RSP_Q_IN(ha, reg), 0); 4084 wrt_reg_word(ISP_RSP_Q_OUT(ha, reg), 0); 4085 rd_reg_word(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ 4086 } 4087 4088 void 4089 qla24xx_config_rings(struct scsi_qla_host *vha) 4090 { 4091 struct qla_hw_data *ha = vha->hw; 4092 device_reg_t *reg = ISP_QUE_REG(ha, 0); 4093 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; 4094 struct qla_msix_entry *msix; 4095 struct init_cb_24xx *icb; 4096 uint16_t rid = 0; 4097 struct req_que *req = ha->req_q_map[0]; 4098 struct rsp_que *rsp = ha->rsp_q_map[0]; 4099 4100 /* Setup ring parameters in initialization control block. */ 4101 icb = (struct init_cb_24xx *)ha->init_cb; 4102 icb->request_q_outpointer = cpu_to_le16(0); 4103 icb->response_q_inpointer = cpu_to_le16(0); 4104 icb->request_q_length = cpu_to_le16(req->length); 4105 icb->response_q_length = cpu_to_le16(rsp->length); 4106 put_unaligned_le64(req->dma, &icb->request_q_address); 4107 put_unaligned_le64(rsp->dma, &icb->response_q_address); 4108 4109 /* Setup ATIO queue dma pointers for target mode */ 4110 icb->atio_q_inpointer = cpu_to_le16(0); 4111 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length); 4112 put_unaligned_le64(ha->tgt.atio_dma, &icb->atio_q_address); 4113 4114 if (IS_SHADOW_REG_CAPABLE(ha)) 4115 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29); 4116 4117 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 4118 IS_QLA28XX(ha)) { 4119 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS); 4120 icb->rid = cpu_to_le16(rid); 4121 if (ha->flags.msix_enabled) { 4122 msix = &ha->msix_entries[1]; 4123 ql_dbg(ql_dbg_init, vha, 0x0019, 4124 "Registering vector 0x%x for base que.\n", 4125 msix->entry); 4126 icb->msix = cpu_to_le16(msix->entry); 4127 } 4128 /* Use alternate PCI bus number */ 4129 if (MSB(rid)) 4130 icb->firmware_options_2 |= cpu_to_le32(BIT_19); 4131 /* Use alternate PCI devfn */ 4132 if (LSB(rid)) 4133 icb->firmware_options_2 |= cpu_to_le32(BIT_18); 4134 4135 /* Use Disable MSIX Handshake mode for capable adapters */ 4136 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) && 4137 (ha->flags.msix_enabled)) { 4138 icb->firmware_options_2 &= cpu_to_le32(~BIT_22); 4139 ha->flags.disable_msix_handshake = 1; 4140 ql_dbg(ql_dbg_init, vha, 0x00fe, 4141 "MSIX Handshake Disable Mode turned on.\n"); 4142 } else { 4143 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 4144 } 4145 icb->firmware_options_2 |= cpu_to_le32(BIT_23); 4146 4147 wrt_reg_dword(®->isp25mq.req_q_in, 0); 4148 wrt_reg_dword(®->isp25mq.req_q_out, 0); 4149 wrt_reg_dword(®->isp25mq.rsp_q_in, 0); 4150 wrt_reg_dword(®->isp25mq.rsp_q_out, 0); 4151 } else { 4152 wrt_reg_dword(®->isp24.req_q_in, 0); 4153 wrt_reg_dword(®->isp24.req_q_out, 0); 4154 wrt_reg_dword(®->isp24.rsp_q_in, 0); 4155 wrt_reg_dword(®->isp24.rsp_q_out, 0); 4156 } 4157 4158 qlt_24xx_config_rings(vha); 4159 4160 /* If the user has configured the speed, set it here */ 4161 if (ha->set_data_rate) { 4162 ql_dbg(ql_dbg_init, vha, 0x00fd, 4163 "Speed set by user : %s Gbps \n", 4164 qla2x00_get_link_speed_str(ha, ha->set_data_rate)); 4165 icb->firmware_options_3 = cpu_to_le32(ha->set_data_rate << 13); 4166 } 4167 4168 /* PCI posting */ 4169 rd_reg_word(&ioreg->hccr); 4170 } 4171 4172 /** 4173 * qla2x00_init_rings() - Initializes firmware. 4174 * @vha: HA context 4175 * 4176 * Beginning of request ring has initialization control block already built 4177 * by nvram config routine. 4178 * 4179 * Returns 0 on success. 4180 */ 4181 int 4182 qla2x00_init_rings(scsi_qla_host_t *vha) 4183 { 4184 int rval; 4185 unsigned long flags = 0; 4186 int cnt, que; 4187 struct qla_hw_data *ha = vha->hw; 4188 struct req_que *req; 4189 struct rsp_que *rsp; 4190 struct mid_init_cb_24xx *mid_init_cb = 4191 (struct mid_init_cb_24xx *) ha->init_cb; 4192 4193 spin_lock_irqsave(&ha->hardware_lock, flags); 4194 4195 /* Clear outstanding commands array. */ 4196 for (que = 0; que < ha->max_req_queues; que++) { 4197 req = ha->req_q_map[que]; 4198 if (!req || !test_bit(que, ha->req_qid_map)) 4199 continue; 4200 req->out_ptr = (uint16_t *)(req->ring + req->length); 4201 *req->out_ptr = 0; 4202 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) 4203 req->outstanding_cmds[cnt] = NULL; 4204 4205 req->current_outstanding_cmd = 1; 4206 4207 /* Initialize firmware. */ 4208 req->ring_ptr = req->ring; 4209 req->ring_index = 0; 4210 req->cnt = req->length; 4211 } 4212 4213 for (que = 0; que < ha->max_rsp_queues; que++) { 4214 rsp = ha->rsp_q_map[que]; 4215 if (!rsp || !test_bit(que, ha->rsp_qid_map)) 4216 continue; 4217 rsp->in_ptr = (uint16_t *)(rsp->ring + rsp->length); 4218 *rsp->in_ptr = 0; 4219 /* Initialize response queue entries */ 4220 if (IS_QLAFX00(ha)) 4221 qlafx00_init_response_q_entries(rsp); 4222 else 4223 qla2x00_init_response_q_entries(rsp); 4224 } 4225 4226 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring; 4227 ha->tgt.atio_ring_index = 0; 4228 /* Initialize ATIO queue entries */ 4229 qlt_init_atio_q_entries(vha); 4230 4231 ha->isp_ops->config_rings(vha); 4232 4233 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4234 4235 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n"); 4236 4237 if (IS_QLAFX00(ha)) { 4238 rval = qlafx00_init_firmware(vha, ha->init_cb_size); 4239 goto next_check; 4240 } 4241 4242 /* Update any ISP specific firmware options before initialization. */ 4243 ha->isp_ops->update_fw_options(vha); 4244 4245 if (ha->flags.npiv_supported) { 4246 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha)) 4247 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; 4248 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); 4249 } 4250 4251 if (IS_FWI2_CAPABLE(ha)) { 4252 mid_init_cb->options = cpu_to_le16(BIT_1); 4253 mid_init_cb->init_cb.execution_throttle = 4254 cpu_to_le16(ha->cur_fw_xcb_count); 4255 ha->flags.dport_enabled = 4256 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) & 4257 BIT_7) != 0; 4258 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n", 4259 (ha->flags.dport_enabled) ? "enabled" : "disabled"); 4260 /* FA-WWPN Status */ 4261 ha->flags.fawwpn_enabled = 4262 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) & 4263 BIT_6) != 0; 4264 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n", 4265 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled"); 4266 } 4267 4268 rval = qla2x00_init_firmware(vha, ha->init_cb_size); 4269 next_check: 4270 if (rval) { 4271 ql_log(ql_log_fatal, vha, 0x00d2, 4272 "Init Firmware **** FAILED ****.\n"); 4273 } else { 4274 ql_dbg(ql_dbg_init, vha, 0x00d3, 4275 "Init Firmware -- success.\n"); 4276 QLA_FW_STARTED(ha); 4277 vha->u_ql2xexchoffld = vha->u_ql2xiniexchg = 0; 4278 } 4279 4280 return (rval); 4281 } 4282 4283 /** 4284 * qla2x00_fw_ready() - Waits for firmware ready. 4285 * @vha: HA context 4286 * 4287 * Returns 0 on success. 4288 */ 4289 static int 4290 qla2x00_fw_ready(scsi_qla_host_t *vha) 4291 { 4292 int rval; 4293 unsigned long wtime, mtime, cs84xx_time; 4294 uint16_t min_wait; /* Minimum wait time if loop is down */ 4295 uint16_t wait_time; /* Wait time if loop is coming ready */ 4296 uint16_t state[6]; 4297 struct qla_hw_data *ha = vha->hw; 4298 4299 if (IS_QLAFX00(vha->hw)) 4300 return qlafx00_fw_ready(vha); 4301 4302 rval = QLA_SUCCESS; 4303 4304 /* Time to wait for loop down */ 4305 if (IS_P3P_TYPE(ha)) 4306 min_wait = 30; 4307 else 4308 min_wait = 20; 4309 4310 /* 4311 * Firmware should take at most one RATOV to login, plus 5 seconds for 4312 * our own processing. 4313 */ 4314 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) { 4315 wait_time = min_wait; 4316 } 4317 4318 /* Min wait time if loop down */ 4319 mtime = jiffies + (min_wait * HZ); 4320 4321 /* wait time before firmware ready */ 4322 wtime = jiffies + (wait_time * HZ); 4323 4324 /* Wait for ISP to finish LIP */ 4325 if (!vha->flags.init_done) 4326 ql_log(ql_log_info, vha, 0x801e, 4327 "Waiting for LIP to complete.\n"); 4328 4329 do { 4330 memset(state, -1, sizeof(state)); 4331 rval = qla2x00_get_firmware_state(vha, state); 4332 if (rval == QLA_SUCCESS) { 4333 if (state[0] < FSTATE_LOSS_OF_SYNC) { 4334 vha->device_flags &= ~DFLG_NO_CABLE; 4335 } 4336 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) { 4337 ql_dbg(ql_dbg_taskm, vha, 0x801f, 4338 "fw_state=%x 84xx=%x.\n", state[0], 4339 state[2]); 4340 if ((state[2] & FSTATE_LOGGED_IN) && 4341 (state[2] & FSTATE_WAITING_FOR_VERIFY)) { 4342 ql_dbg(ql_dbg_taskm, vha, 0x8028, 4343 "Sending verify iocb.\n"); 4344 4345 cs84xx_time = jiffies; 4346 rval = qla84xx_init_chip(vha); 4347 if (rval != QLA_SUCCESS) { 4348 ql_log(ql_log_warn, 4349 vha, 0x8007, 4350 "Init chip failed.\n"); 4351 break; 4352 } 4353 4354 /* Add time taken to initialize. */ 4355 cs84xx_time = jiffies - cs84xx_time; 4356 wtime += cs84xx_time; 4357 mtime += cs84xx_time; 4358 ql_dbg(ql_dbg_taskm, vha, 0x8008, 4359 "Increasing wait time by %ld. " 4360 "New time %ld.\n", cs84xx_time, 4361 wtime); 4362 } 4363 } else if (state[0] == FSTATE_READY) { 4364 ql_dbg(ql_dbg_taskm, vha, 0x8037, 4365 "F/W Ready - OK.\n"); 4366 4367 qla2x00_get_retry_cnt(vha, &ha->retry_count, 4368 &ha->login_timeout, &ha->r_a_tov); 4369 4370 rval = QLA_SUCCESS; 4371 break; 4372 } 4373 4374 rval = QLA_FUNCTION_FAILED; 4375 4376 if (atomic_read(&vha->loop_down_timer) && 4377 state[0] != FSTATE_READY) { 4378 /* Loop down. Timeout on min_wait for states 4379 * other than Wait for Login. 4380 */ 4381 if (time_after_eq(jiffies, mtime)) { 4382 ql_log(ql_log_info, vha, 0x8038, 4383 "Cable is unplugged...\n"); 4384 4385 vha->device_flags |= DFLG_NO_CABLE; 4386 break; 4387 } 4388 } 4389 } else { 4390 /* Mailbox cmd failed. Timeout on min_wait. */ 4391 if (time_after_eq(jiffies, mtime) || 4392 ha->flags.isp82xx_fw_hung) 4393 break; 4394 } 4395 4396 if (time_after_eq(jiffies, wtime)) 4397 break; 4398 4399 /* Delay for a while */ 4400 msleep(500); 4401 } while (1); 4402 4403 ql_dbg(ql_dbg_taskm, vha, 0x803a, 4404 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0], 4405 state[1], state[2], state[3], state[4], state[5], jiffies); 4406 4407 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) { 4408 ql_log(ql_log_warn, vha, 0x803b, 4409 "Firmware ready **** FAILED ****.\n"); 4410 } 4411 4412 return (rval); 4413 } 4414 4415 /* 4416 * qla2x00_configure_hba 4417 * Setup adapter context. 4418 * 4419 * Input: 4420 * ha = adapter state pointer. 4421 * 4422 * Returns: 4423 * 0 = success 4424 * 4425 * Context: 4426 * Kernel context. 4427 */ 4428 static int 4429 qla2x00_configure_hba(scsi_qla_host_t *vha) 4430 { 4431 int rval; 4432 uint16_t loop_id; 4433 uint16_t topo; 4434 uint16_t sw_cap; 4435 uint8_t al_pa; 4436 uint8_t area; 4437 uint8_t domain; 4438 char connect_type[22]; 4439 struct qla_hw_data *ha = vha->hw; 4440 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 4441 port_id_t id; 4442 unsigned long flags; 4443 4444 /* Get host addresses. */ 4445 rval = qla2x00_get_adapter_id(vha, 4446 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); 4447 if (rval != QLA_SUCCESS) { 4448 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || 4449 IS_CNA_CAPABLE(ha) || 4450 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { 4451 ql_dbg(ql_dbg_disc, vha, 0x2008, 4452 "Loop is in a transition state.\n"); 4453 } else { 4454 ql_log(ql_log_warn, vha, 0x2009, 4455 "Unable to get host loop ID.\n"); 4456 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) && 4457 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) { 4458 ql_log(ql_log_warn, vha, 0x1151, 4459 "Doing link init.\n"); 4460 if (qla24xx_link_initialize(vha) == QLA_SUCCESS) 4461 return rval; 4462 } 4463 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 4464 } 4465 return (rval); 4466 } 4467 4468 if (topo == 4) { 4469 ql_log(ql_log_info, vha, 0x200a, 4470 "Cannot get topology - retrying.\n"); 4471 return (QLA_FUNCTION_FAILED); 4472 } 4473 4474 vha->loop_id = loop_id; 4475 4476 /* initialize */ 4477 ha->min_external_loopid = SNS_FIRST_LOOP_ID; 4478 ha->operating_mode = LOOP; 4479 ha->switch_cap = 0; 4480 4481 switch (topo) { 4482 case 0: 4483 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n"); 4484 ha->current_topology = ISP_CFG_NL; 4485 strcpy(connect_type, "(Loop)"); 4486 break; 4487 4488 case 1: 4489 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n"); 4490 ha->switch_cap = sw_cap; 4491 ha->current_topology = ISP_CFG_FL; 4492 strcpy(connect_type, "(FL_Port)"); 4493 break; 4494 4495 case 2: 4496 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n"); 4497 ha->operating_mode = P2P; 4498 ha->current_topology = ISP_CFG_N; 4499 strcpy(connect_type, "(N_Port-to-N_Port)"); 4500 break; 4501 4502 case 3: 4503 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n"); 4504 ha->switch_cap = sw_cap; 4505 ha->operating_mode = P2P; 4506 ha->current_topology = ISP_CFG_F; 4507 strcpy(connect_type, "(F_Port)"); 4508 break; 4509 4510 default: 4511 ql_dbg(ql_dbg_disc, vha, 0x200f, 4512 "HBA in unknown topology %x, using NL.\n", topo); 4513 ha->current_topology = ISP_CFG_NL; 4514 strcpy(connect_type, "(Loop)"); 4515 break; 4516 } 4517 4518 /* Save Host port and loop ID. */ 4519 /* byte order - Big Endian */ 4520 id.b.domain = domain; 4521 id.b.area = area; 4522 id.b.al_pa = al_pa; 4523 id.b.rsvd_1 = 0; 4524 spin_lock_irqsave(&ha->hardware_lock, flags); 4525 if (!(topo == 2 && ha->flags.n2n_bigger)) 4526 qlt_update_host_map(vha, id); 4527 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4528 4529 if (!vha->flags.init_done) 4530 ql_log(ql_log_info, vha, 0x2010, 4531 "Topology - %s, Host Loop address 0x%x.\n", 4532 connect_type, vha->loop_id); 4533 4534 return(rval); 4535 } 4536 4537 inline void 4538 qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, 4539 const char *def) 4540 { 4541 char *st, *en; 4542 uint16_t index; 4543 uint64_t zero[2] = { 0 }; 4544 struct qla_hw_data *ha = vha->hw; 4545 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 4546 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha); 4547 4548 if (len > sizeof(zero)) 4549 len = sizeof(zero); 4550 if (memcmp(model, &zero, len) != 0) { 4551 memcpy(ha->model_number, model, len); 4552 st = en = ha->model_number; 4553 en += len - 1; 4554 while (en > st) { 4555 if (*en != 0x20 && *en != 0x00) 4556 break; 4557 *en-- = '\0'; 4558 } 4559 4560 index = (ha->pdev->subsystem_device & 0xff); 4561 if (use_tbl && 4562 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 4563 index < QLA_MODEL_NAMES) 4564 strlcpy(ha->model_desc, 4565 qla2x00_model_name[index * 2 + 1], 4566 sizeof(ha->model_desc)); 4567 } else { 4568 index = (ha->pdev->subsystem_device & 0xff); 4569 if (use_tbl && 4570 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 4571 index < QLA_MODEL_NAMES) { 4572 strlcpy(ha->model_number, 4573 qla2x00_model_name[index * 2], 4574 sizeof(ha->model_number)); 4575 strlcpy(ha->model_desc, 4576 qla2x00_model_name[index * 2 + 1], 4577 sizeof(ha->model_desc)); 4578 } else { 4579 strlcpy(ha->model_number, def, 4580 sizeof(ha->model_number)); 4581 } 4582 } 4583 if (IS_FWI2_CAPABLE(ha)) 4584 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc, 4585 sizeof(ha->model_desc)); 4586 } 4587 4588 /* On sparc systems, obtain port and node WWN from firmware 4589 * properties. 4590 */ 4591 static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv) 4592 { 4593 #ifdef CONFIG_SPARC 4594 struct qla_hw_data *ha = vha->hw; 4595 struct pci_dev *pdev = ha->pdev; 4596 struct device_node *dp = pci_device_to_OF_node(pdev); 4597 const u8 *val; 4598 int len; 4599 4600 val = of_get_property(dp, "port-wwn", &len); 4601 if (val && len >= WWN_SIZE) 4602 memcpy(nv->port_name, val, WWN_SIZE); 4603 4604 val = of_get_property(dp, "node-wwn", &len); 4605 if (val && len >= WWN_SIZE) 4606 memcpy(nv->node_name, val, WWN_SIZE); 4607 #endif 4608 } 4609 4610 /* 4611 * NVRAM configuration for ISP 2xxx 4612 * 4613 * Input: 4614 * ha = adapter block pointer. 4615 * 4616 * Output: 4617 * initialization control block in response_ring 4618 * host adapters parameters in host adapter block 4619 * 4620 * Returns: 4621 * 0 = success. 4622 */ 4623 int 4624 qla2x00_nvram_config(scsi_qla_host_t *vha) 4625 { 4626 int rval; 4627 uint8_t chksum = 0; 4628 uint16_t cnt; 4629 uint8_t *dptr1, *dptr2; 4630 struct qla_hw_data *ha = vha->hw; 4631 init_cb_t *icb = ha->init_cb; 4632 nvram_t *nv = ha->nvram; 4633 uint8_t *ptr = ha->nvram; 4634 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4635 4636 rval = QLA_SUCCESS; 4637 4638 /* Determine NVRAM starting address. */ 4639 ha->nvram_size = sizeof(*nv); 4640 ha->nvram_base = 0; 4641 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) 4642 if ((rd_reg_word(®->ctrl_status) >> 14) == 1) 4643 ha->nvram_base = 0x80; 4644 4645 /* Get NVRAM data and calculate checksum. */ 4646 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size); 4647 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) 4648 chksum += *ptr++; 4649 4650 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f, 4651 "Contents of NVRAM.\n"); 4652 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110, 4653 nv, ha->nvram_size); 4654 4655 /* Bad NVRAM data, set defaults parameters. */ 4656 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 4657 nv->nvram_version < 1) { 4658 /* Reset NVRAM data. */ 4659 ql_log(ql_log_warn, vha, 0x0064, 4660 "Inconsistent NVRAM detected: checksum=%#x id=%.4s version=%#x.\n", 4661 chksum, nv->id, nv->nvram_version); 4662 ql_log(ql_log_warn, vha, 0x0065, 4663 "Falling back to " 4664 "functioning (yet invalid -- WWPN) defaults.\n"); 4665 4666 /* 4667 * Set default initialization control block. 4668 */ 4669 memset(nv, 0, ha->nvram_size); 4670 nv->parameter_block_version = ICB_VERSION; 4671 4672 if (IS_QLA23XX(ha)) { 4673 nv->firmware_options[0] = BIT_2 | BIT_1; 4674 nv->firmware_options[1] = BIT_7 | BIT_5; 4675 nv->add_firmware_options[0] = BIT_5; 4676 nv->add_firmware_options[1] = BIT_5 | BIT_4; 4677 nv->frame_payload_size = cpu_to_le16(2048); 4678 nv->special_options[1] = BIT_7; 4679 } else if (IS_QLA2200(ha)) { 4680 nv->firmware_options[0] = BIT_2 | BIT_1; 4681 nv->firmware_options[1] = BIT_7 | BIT_5; 4682 nv->add_firmware_options[0] = BIT_5; 4683 nv->add_firmware_options[1] = BIT_5 | BIT_4; 4684 nv->frame_payload_size = cpu_to_le16(1024); 4685 } else if (IS_QLA2100(ha)) { 4686 nv->firmware_options[0] = BIT_3 | BIT_1; 4687 nv->firmware_options[1] = BIT_5; 4688 nv->frame_payload_size = cpu_to_le16(1024); 4689 } 4690 4691 nv->max_iocb_allocation = cpu_to_le16(256); 4692 nv->execution_throttle = cpu_to_le16(16); 4693 nv->retry_count = 8; 4694 nv->retry_delay = 1; 4695 4696 nv->port_name[0] = 33; 4697 nv->port_name[3] = 224; 4698 nv->port_name[4] = 139; 4699 4700 qla2xxx_nvram_wwn_from_ofw(vha, nv); 4701 4702 nv->login_timeout = 4; 4703 4704 /* 4705 * Set default host adapter parameters 4706 */ 4707 nv->host_p[1] = BIT_2; 4708 nv->reset_delay = 5; 4709 nv->port_down_retry_count = 8; 4710 nv->max_luns_per_target = cpu_to_le16(8); 4711 nv->link_down_timeout = 60; 4712 4713 rval = 1; 4714 } 4715 4716 /* Reset Initialization control block */ 4717 memset(icb, 0, ha->init_cb_size); 4718 4719 /* 4720 * Setup driver NVRAM options. 4721 */ 4722 nv->firmware_options[0] |= (BIT_6 | BIT_1); 4723 nv->firmware_options[0] &= ~(BIT_5 | BIT_4); 4724 nv->firmware_options[1] |= (BIT_5 | BIT_0); 4725 nv->firmware_options[1] &= ~BIT_4; 4726 4727 if (IS_QLA23XX(ha)) { 4728 nv->firmware_options[0] |= BIT_2; 4729 nv->firmware_options[0] &= ~BIT_3; 4730 nv->special_options[0] &= ~BIT_6; 4731 nv->add_firmware_options[1] |= BIT_5 | BIT_4; 4732 4733 if (IS_QLA2300(ha)) { 4734 if (ha->fb_rev == FPM_2310) { 4735 strcpy(ha->model_number, "QLA2310"); 4736 } else { 4737 strcpy(ha->model_number, "QLA2300"); 4738 } 4739 } else { 4740 qla2x00_set_model_info(vha, nv->model_number, 4741 sizeof(nv->model_number), "QLA23xx"); 4742 } 4743 } else if (IS_QLA2200(ha)) { 4744 nv->firmware_options[0] |= BIT_2; 4745 /* 4746 * 'Point-to-point preferred, else loop' is not a safe 4747 * connection mode setting. 4748 */ 4749 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == 4750 (BIT_5 | BIT_4)) { 4751 /* Force 'loop preferred, else point-to-point'. */ 4752 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); 4753 nv->add_firmware_options[0] |= BIT_5; 4754 } 4755 strcpy(ha->model_number, "QLA22xx"); 4756 } else /*if (IS_QLA2100(ha))*/ { 4757 strcpy(ha->model_number, "QLA2100"); 4758 } 4759 4760 /* 4761 * Copy over NVRAM RISC parameter block to initialization control block. 4762 */ 4763 dptr1 = (uint8_t *)icb; 4764 dptr2 = (uint8_t *)&nv->parameter_block_version; 4765 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version; 4766 while (cnt--) 4767 *dptr1++ = *dptr2++; 4768 4769 /* Copy 2nd half. */ 4770 dptr1 = (uint8_t *)icb->add_firmware_options; 4771 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options; 4772 while (cnt--) 4773 *dptr1++ = *dptr2++; 4774 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 4775 /* Use alternate WWN? */ 4776 if (nv->host_p[1] & BIT_7) { 4777 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 4778 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 4779 } 4780 4781 /* Prepare nodename */ 4782 if ((icb->firmware_options[1] & BIT_6) == 0) { 4783 /* 4784 * Firmware will apply the following mask if the nodename was 4785 * not provided. 4786 */ 4787 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 4788 icb->node_name[0] &= 0xF0; 4789 } 4790 4791 /* 4792 * Set host adapter parameters. 4793 */ 4794 4795 /* 4796 * BIT_7 in the host-parameters section allows for modification to 4797 * internal driver logging. 4798 */ 4799 if (nv->host_p[0] & BIT_7) 4800 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 4801 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); 4802 /* Always load RISC code on non ISP2[12]00 chips. */ 4803 if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) 4804 ha->flags.disable_risc_code_load = 0; 4805 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0); 4806 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); 4807 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); 4808 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; 4809 ha->flags.disable_serdes = 0; 4810 4811 ha->operating_mode = 4812 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; 4813 4814 memcpy(ha->fw_seriallink_options, nv->seriallink_options, 4815 sizeof(ha->fw_seriallink_options)); 4816 4817 /* save HBA serial number */ 4818 ha->serial0 = icb->port_name[5]; 4819 ha->serial1 = icb->port_name[6]; 4820 ha->serial2 = icb->port_name[7]; 4821 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 4822 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 4823 4824 icb->execution_throttle = cpu_to_le16(0xFFFF); 4825 4826 ha->retry_count = nv->retry_count; 4827 4828 /* Set minimum login_timeout to 4 seconds. */ 4829 if (nv->login_timeout != ql2xlogintimeout) 4830 nv->login_timeout = ql2xlogintimeout; 4831 if (nv->login_timeout < 4) 4832 nv->login_timeout = 4; 4833 ha->login_timeout = nv->login_timeout; 4834 4835 /* Set minimum RATOV to 100 tenths of a second. */ 4836 ha->r_a_tov = 100; 4837 4838 ha->loop_reset_delay = nv->reset_delay; 4839 4840 /* Link Down Timeout = 0: 4841 * 4842 * When Port Down timer expires we will start returning 4843 * I/O's to OS with "DID_NO_CONNECT". 4844 * 4845 * Link Down Timeout != 0: 4846 * 4847 * The driver waits for the link to come up after link down 4848 * before returning I/Os to OS with "DID_NO_CONNECT". 4849 */ 4850 if (nv->link_down_timeout == 0) { 4851 ha->loop_down_abort_time = 4852 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 4853 } else { 4854 ha->link_down_timeout = nv->link_down_timeout; 4855 ha->loop_down_abort_time = 4856 (LOOP_DOWN_TIME - ha->link_down_timeout); 4857 } 4858 4859 /* 4860 * Need enough time to try and get the port back. 4861 */ 4862 ha->port_down_retry_count = nv->port_down_retry_count; 4863 if (qlport_down_retry) 4864 ha->port_down_retry_count = qlport_down_retry; 4865 /* Set login_retry_count */ 4866 ha->login_retry_count = nv->retry_count; 4867 if (ha->port_down_retry_count == nv->port_down_retry_count && 4868 ha->port_down_retry_count > 3) 4869 ha->login_retry_count = ha->port_down_retry_count; 4870 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 4871 ha->login_retry_count = ha->port_down_retry_count; 4872 if (ql2xloginretrycount) 4873 ha->login_retry_count = ql2xloginretrycount; 4874 4875 icb->lun_enables = cpu_to_le16(0); 4876 icb->command_resource_count = 0; 4877 icb->immediate_notify_resource_count = 0; 4878 icb->timeout = cpu_to_le16(0); 4879 4880 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4881 /* Enable RIO */ 4882 icb->firmware_options[0] &= ~BIT_3; 4883 icb->add_firmware_options[0] &= 4884 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 4885 icb->add_firmware_options[0] |= BIT_2; 4886 icb->response_accumulation_timer = 3; 4887 icb->interrupt_delay_timer = 5; 4888 4889 vha->flags.process_response_queue = 1; 4890 } else { 4891 /* Enable ZIO. */ 4892 if (!vha->flags.init_done) { 4893 ha->zio_mode = icb->add_firmware_options[0] & 4894 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 4895 ha->zio_timer = icb->interrupt_delay_timer ? 4896 icb->interrupt_delay_timer : 2; 4897 } 4898 icb->add_firmware_options[0] &= 4899 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 4900 vha->flags.process_response_queue = 0; 4901 if (ha->zio_mode != QLA_ZIO_DISABLED) { 4902 ha->zio_mode = QLA_ZIO_MODE_6; 4903 4904 ql_log(ql_log_info, vha, 0x0068, 4905 "ZIO mode %d enabled; timer delay (%d us).\n", 4906 ha->zio_mode, ha->zio_timer * 100); 4907 4908 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode; 4909 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer; 4910 vha->flags.process_response_queue = 1; 4911 } 4912 } 4913 4914 if (rval) { 4915 ql_log(ql_log_warn, vha, 0x0069, 4916 "NVRAM configuration failed.\n"); 4917 } 4918 return (rval); 4919 } 4920 4921 static void 4922 qla2x00_rport_del(void *data) 4923 { 4924 fc_port_t *fcport = data; 4925 struct fc_rport *rport; 4926 unsigned long flags; 4927 4928 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 4929 rport = fcport->drport ? fcport->drport : fcport->rport; 4930 fcport->drport = NULL; 4931 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 4932 if (rport) { 4933 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b, 4934 "%s %8phN. rport %p roles %x\n", 4935 __func__, fcport->port_name, rport, 4936 rport->roles); 4937 4938 fc_remote_port_delete(rport); 4939 } 4940 } 4941 4942 void qla2x00_set_fcport_state(fc_port_t *fcport, int state) 4943 { 4944 int old_state; 4945 4946 old_state = atomic_read(&fcport->state); 4947 atomic_set(&fcport->state, state); 4948 4949 /* Don't print state transitions during initial allocation of fcport */ 4950 if (old_state && old_state != state) { 4951 ql_dbg(ql_dbg_disc, fcport->vha, 0x207d, 4952 "FCPort %8phC state transitioned from %s to %s - portid=%02x%02x%02x.\n", 4953 fcport->port_name, port_state_str[old_state], 4954 port_state_str[state], fcport->d_id.b.domain, 4955 fcport->d_id.b.area, fcport->d_id.b.al_pa); 4956 } 4957 } 4958 4959 /** 4960 * qla2x00_alloc_fcport() - Allocate a generic fcport. 4961 * @vha: HA context 4962 * @flags: allocation flags 4963 * 4964 * Returns a pointer to the allocated fcport, or NULL, if none available. 4965 */ 4966 fc_port_t * 4967 qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags) 4968 { 4969 fc_port_t *fcport; 4970 4971 fcport = kzalloc(sizeof(fc_port_t), flags); 4972 if (!fcport) 4973 return NULL; 4974 4975 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev, 4976 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma, 4977 flags); 4978 if (!fcport->ct_desc.ct_sns) { 4979 ql_log(ql_log_warn, vha, 0xd049, 4980 "Failed to allocate ct_sns request.\n"); 4981 kfree(fcport); 4982 return NULL; 4983 } 4984 4985 /* Setup fcport template structure. */ 4986 fcport->vha = vha; 4987 fcport->port_type = FCT_UNKNOWN; 4988 fcport->loop_id = FC_NO_LOOP_ID; 4989 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED); 4990 fcport->supported_classes = FC_COS_UNSPECIFIED; 4991 fcport->fp_speed = PORT_SPEED_UNKNOWN; 4992 4993 fcport->disc_state = DSC_DELETED; 4994 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 4995 fcport->deleted = QLA_SESS_DELETED; 4996 fcport->login_retry = vha->hw->login_retry_count; 4997 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 4998 fcport->logout_on_delete = 1; 4999 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 5000 fcport->tgt_short_link_down_cnt = 0; 5001 fcport->dev_loss_tmo = 0; 5002 5003 if (!fcport->ct_desc.ct_sns) { 5004 ql_log(ql_log_warn, vha, 0xd049, 5005 "Failed to allocate ct_sns request.\n"); 5006 kfree(fcport); 5007 return NULL; 5008 } 5009 5010 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn); 5011 INIT_WORK(&fcport->free_work, qlt_free_session_done); 5012 INIT_WORK(&fcport->reg_work, qla_register_fcport_fn); 5013 INIT_LIST_HEAD(&fcport->gnl_entry); 5014 INIT_LIST_HEAD(&fcport->list); 5015 5016 INIT_LIST_HEAD(&fcport->sess_cmd_list); 5017 spin_lock_init(&fcport->sess_cmd_lock); 5018 5019 return fcport; 5020 } 5021 5022 void 5023 qla2x00_free_fcport(fc_port_t *fcport) 5024 { 5025 if (fcport->ct_desc.ct_sns) { 5026 dma_free_coherent(&fcport->vha->hw->pdev->dev, 5027 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns, 5028 fcport->ct_desc.ct_sns_dma); 5029 5030 fcport->ct_desc.ct_sns = NULL; 5031 } 5032 list_del(&fcport->list); 5033 qla2x00_clear_loop_id(fcport); 5034 kfree(fcport); 5035 } 5036 5037 static void qla_get_login_template(scsi_qla_host_t *vha) 5038 { 5039 struct qla_hw_data *ha = vha->hw; 5040 int rval; 5041 u32 *bp, sz; 5042 __be32 *q; 5043 5044 memset(ha->init_cb, 0, ha->init_cb_size); 5045 sz = min_t(int, sizeof(struct fc_els_flogi), ha->init_cb_size); 5046 rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma, 5047 ha->init_cb, sz); 5048 if (rval != QLA_SUCCESS) { 5049 ql_dbg(ql_dbg_init, vha, 0x00d1, 5050 "PLOGI ELS param read fail.\n"); 5051 return; 5052 } 5053 q = (__be32 *)&ha->plogi_els_payld.fl_csp; 5054 5055 bp = (uint32_t *)ha->init_cb; 5056 cpu_to_be32_array(q, bp, sz / 4); 5057 ha->flags.plogi_template_valid = 1; 5058 } 5059 5060 /* 5061 * qla2x00_configure_loop 5062 * Updates Fibre Channel Device Database with what is actually on loop. 5063 * 5064 * Input: 5065 * ha = adapter block pointer. 5066 * 5067 * Returns: 5068 * 0 = success. 5069 * 1 = error. 5070 * 2 = database was full and device was not configured. 5071 */ 5072 static int 5073 qla2x00_configure_loop(scsi_qla_host_t *vha) 5074 { 5075 int rval; 5076 unsigned long flags, save_flags; 5077 struct qla_hw_data *ha = vha->hw; 5078 5079 rval = QLA_SUCCESS; 5080 5081 /* Get Initiator ID */ 5082 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) { 5083 rval = qla2x00_configure_hba(vha); 5084 if (rval != QLA_SUCCESS) { 5085 ql_dbg(ql_dbg_disc, vha, 0x2013, 5086 "Unable to configure HBA.\n"); 5087 return (rval); 5088 } 5089 } 5090 5091 save_flags = flags = vha->dpc_flags; 5092 ql_dbg(ql_dbg_disc, vha, 0x2014, 5093 "Configure loop -- dpc flags = 0x%lx.\n", flags); 5094 5095 /* 5096 * If we have both an RSCN and PORT UPDATE pending then handle them 5097 * both at the same time. 5098 */ 5099 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5100 clear_bit(RSCN_UPDATE, &vha->dpc_flags); 5101 5102 qla2x00_get_data_rate(vha); 5103 qla_get_login_template(vha); 5104 5105 /* Determine what we need to do */ 5106 if ((ha->current_topology == ISP_CFG_FL || 5107 ha->current_topology == ISP_CFG_F) && 5108 (test_bit(LOCAL_LOOP_UPDATE, &flags))) { 5109 5110 set_bit(RSCN_UPDATE, &flags); 5111 clear_bit(LOCAL_LOOP_UPDATE, &flags); 5112 5113 } else if (ha->current_topology == ISP_CFG_NL || 5114 ha->current_topology == ISP_CFG_N) { 5115 clear_bit(RSCN_UPDATE, &flags); 5116 set_bit(LOCAL_LOOP_UPDATE, &flags); 5117 } else if (!vha->flags.online || 5118 (test_bit(ABORT_ISP_ACTIVE, &flags))) { 5119 set_bit(RSCN_UPDATE, &flags); 5120 set_bit(LOCAL_LOOP_UPDATE, &flags); 5121 } 5122 5123 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) { 5124 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5125 ql_dbg(ql_dbg_disc, vha, 0x2015, 5126 "Loop resync needed, failing.\n"); 5127 rval = QLA_FUNCTION_FAILED; 5128 } else 5129 rval = qla2x00_configure_local_loop(vha); 5130 } 5131 5132 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) { 5133 if (LOOP_TRANSITION(vha)) { 5134 ql_dbg(ql_dbg_disc, vha, 0x2099, 5135 "Needs RSCN update and loop transition.\n"); 5136 rval = QLA_FUNCTION_FAILED; 5137 } 5138 else 5139 rval = qla2x00_configure_fabric(vha); 5140 } 5141 5142 if (rval == QLA_SUCCESS) { 5143 if (atomic_read(&vha->loop_down_timer) || 5144 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5145 rval = QLA_FUNCTION_FAILED; 5146 } else { 5147 atomic_set(&vha->loop_state, LOOP_READY); 5148 ql_dbg(ql_dbg_disc, vha, 0x2069, 5149 "LOOP READY.\n"); 5150 ha->flags.fw_init_done = 1; 5151 5152 /* 5153 * Process any ATIO queue entries that came in 5154 * while we weren't online. 5155 */ 5156 if (qla_tgt_mode_enabled(vha) || 5157 qla_dual_mode_enabled(vha)) { 5158 spin_lock_irqsave(&ha->tgt.atio_lock, flags); 5159 qlt_24xx_process_atio_queue(vha, 0); 5160 spin_unlock_irqrestore(&ha->tgt.atio_lock, 5161 flags); 5162 } 5163 } 5164 } 5165 5166 if (rval) { 5167 ql_dbg(ql_dbg_disc, vha, 0x206a, 5168 "%s *** FAILED ***.\n", __func__); 5169 } else { 5170 ql_dbg(ql_dbg_disc, vha, 0x206b, 5171 "%s: exiting normally.\n", __func__); 5172 } 5173 5174 /* Restore state if a resync event occurred during processing */ 5175 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5176 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags)) 5177 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5178 if (test_bit(RSCN_UPDATE, &save_flags)) { 5179 set_bit(RSCN_UPDATE, &vha->dpc_flags); 5180 } 5181 } 5182 5183 return (rval); 5184 } 5185 5186 static int qla2x00_configure_n2n_loop(scsi_qla_host_t *vha) 5187 { 5188 unsigned long flags; 5189 fc_port_t *fcport; 5190 5191 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) 5192 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5193 5194 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5195 if (fcport->n2n_flag) { 5196 qla24xx_fcport_handle_login(vha, fcport); 5197 return QLA_SUCCESS; 5198 } 5199 } 5200 5201 spin_lock_irqsave(&vha->work_lock, flags); 5202 vha->scan.scan_retry++; 5203 spin_unlock_irqrestore(&vha->work_lock, flags); 5204 5205 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) { 5206 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5207 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5208 } 5209 return QLA_FUNCTION_FAILED; 5210 } 5211 5212 /* 5213 * qla2x00_configure_local_loop 5214 * Updates Fibre Channel Device Database with local loop devices. 5215 * 5216 * Input: 5217 * ha = adapter block pointer. 5218 * 5219 * Returns: 5220 * 0 = success. 5221 */ 5222 static int 5223 qla2x00_configure_local_loop(scsi_qla_host_t *vha) 5224 { 5225 int rval, rval2; 5226 int found_devs; 5227 int found; 5228 fc_port_t *fcport, *new_fcport; 5229 uint16_t index; 5230 uint16_t entries; 5231 struct gid_list_info *gid; 5232 uint16_t loop_id; 5233 uint8_t domain, area, al_pa; 5234 struct qla_hw_data *ha = vha->hw; 5235 unsigned long flags; 5236 5237 /* Inititae N2N login. */ 5238 if (N2N_TOPO(ha)) 5239 return qla2x00_configure_n2n_loop(vha); 5240 5241 found_devs = 0; 5242 new_fcport = NULL; 5243 entries = MAX_FIBRE_DEVICES_LOOP; 5244 5245 /* Get list of logged in devices. */ 5246 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha)); 5247 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma, 5248 &entries); 5249 if (rval != QLA_SUCCESS) 5250 goto err; 5251 5252 ql_dbg(ql_dbg_disc, vha, 0x2011, 5253 "Entries in ID list (%d).\n", entries); 5254 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075, 5255 ha->gid_list, entries * sizeof(*ha->gid_list)); 5256 5257 if (entries == 0) { 5258 spin_lock_irqsave(&vha->work_lock, flags); 5259 vha->scan.scan_retry++; 5260 spin_unlock_irqrestore(&vha->work_lock, flags); 5261 5262 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) { 5263 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5264 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5265 } 5266 } else { 5267 vha->scan.scan_retry = 0; 5268 } 5269 5270 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5271 fcport->scan_state = QLA_FCPORT_SCAN; 5272 } 5273 5274 /* Allocate temporary fcport for any new fcports discovered. */ 5275 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5276 if (new_fcport == NULL) { 5277 ql_log(ql_log_warn, vha, 0x2012, 5278 "Memory allocation failed for fcport.\n"); 5279 rval = QLA_MEMORY_ALLOC_FAILED; 5280 goto err; 5281 } 5282 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 5283 5284 /* Add devices to port list. */ 5285 gid = ha->gid_list; 5286 for (index = 0; index < entries; index++) { 5287 domain = gid->domain; 5288 area = gid->area; 5289 al_pa = gid->al_pa; 5290 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 5291 loop_id = gid->loop_id_2100; 5292 else 5293 loop_id = le16_to_cpu(gid->loop_id); 5294 gid = (void *)gid + ha->gid_list_info_size; 5295 5296 /* Bypass reserved domain fields. */ 5297 if ((domain & 0xf0) == 0xf0) 5298 continue; 5299 5300 /* Bypass if not same domain and area of adapter. */ 5301 if (area && domain && ((area != vha->d_id.b.area) || 5302 (domain != vha->d_id.b.domain)) && 5303 (ha->current_topology == ISP_CFG_NL)) 5304 continue; 5305 5306 5307 /* Bypass invalid local loop ID. */ 5308 if (loop_id > LAST_LOCAL_LOOP_ID) 5309 continue; 5310 5311 memset(new_fcport->port_name, 0, WWN_SIZE); 5312 5313 /* Fill in member data. */ 5314 new_fcport->d_id.b.domain = domain; 5315 new_fcport->d_id.b.area = area; 5316 new_fcport->d_id.b.al_pa = al_pa; 5317 new_fcport->loop_id = loop_id; 5318 new_fcport->scan_state = QLA_FCPORT_FOUND; 5319 5320 rval2 = qla2x00_get_port_database(vha, new_fcport, 0); 5321 if (rval2 != QLA_SUCCESS) { 5322 ql_dbg(ql_dbg_disc, vha, 0x2097, 5323 "Failed to retrieve fcport information " 5324 "-- get_port_database=%x, loop_id=0x%04x.\n", 5325 rval2, new_fcport->loop_id); 5326 /* Skip retry if N2N */ 5327 if (ha->current_topology != ISP_CFG_N) { 5328 ql_dbg(ql_dbg_disc, vha, 0x2105, 5329 "Scheduling resync.\n"); 5330 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5331 continue; 5332 } 5333 } 5334 5335 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5336 /* Check for matching device in port list. */ 5337 found = 0; 5338 fcport = NULL; 5339 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5340 if (memcmp(new_fcport->port_name, fcport->port_name, 5341 WWN_SIZE)) 5342 continue; 5343 5344 fcport->flags &= ~FCF_FABRIC_DEVICE; 5345 fcport->loop_id = new_fcport->loop_id; 5346 fcport->port_type = new_fcport->port_type; 5347 fcport->d_id.b24 = new_fcport->d_id.b24; 5348 memcpy(fcport->node_name, new_fcport->node_name, 5349 WWN_SIZE); 5350 fcport->scan_state = QLA_FCPORT_FOUND; 5351 found++; 5352 break; 5353 } 5354 5355 if (!found) { 5356 /* New device, add to fcports list. */ 5357 list_add_tail(&new_fcport->list, &vha->vp_fcports); 5358 5359 /* Allocate a new replacement fcport. */ 5360 fcport = new_fcport; 5361 5362 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5363 5364 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5365 5366 if (new_fcport == NULL) { 5367 ql_log(ql_log_warn, vha, 0xd031, 5368 "Failed to allocate memory for fcport.\n"); 5369 rval = QLA_MEMORY_ALLOC_FAILED; 5370 goto err; 5371 } 5372 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5373 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 5374 } 5375 5376 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5377 5378 /* Base iIDMA settings on HBA port speed. */ 5379 fcport->fp_speed = ha->link_data_rate; 5380 5381 found_devs++; 5382 } 5383 5384 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5385 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5386 break; 5387 5388 if (fcport->scan_state == QLA_FCPORT_SCAN) { 5389 if ((qla_dual_mode_enabled(vha) || 5390 qla_ini_mode_enabled(vha)) && 5391 atomic_read(&fcport->state) == FCS_ONLINE) { 5392 qla2x00_mark_device_lost(vha, fcport, 5393 ql2xplogiabsentdevice); 5394 if (fcport->loop_id != FC_NO_LOOP_ID && 5395 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 5396 fcport->port_type != FCT_INITIATOR && 5397 fcport->port_type != FCT_BROADCAST) { 5398 ql_dbg(ql_dbg_disc, vha, 0x20f0, 5399 "%s %d %8phC post del sess\n", 5400 __func__, __LINE__, 5401 fcport->port_name); 5402 5403 qlt_schedule_sess_for_deletion(fcport); 5404 continue; 5405 } 5406 } 5407 } 5408 5409 if (fcport->scan_state == QLA_FCPORT_FOUND) 5410 qla24xx_fcport_handle_login(vha, fcport); 5411 } 5412 5413 qla2x00_free_fcport(new_fcport); 5414 5415 return rval; 5416 5417 err: 5418 ql_dbg(ql_dbg_disc, vha, 0x2098, 5419 "Configure local loop error exit: rval=%x.\n", rval); 5420 return rval; 5421 } 5422 5423 static void 5424 qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 5425 { 5426 int rval; 5427 uint16_t mb[MAILBOX_REGISTER_COUNT]; 5428 struct qla_hw_data *ha = vha->hw; 5429 5430 if (!IS_IIDMA_CAPABLE(ha)) 5431 return; 5432 5433 if (atomic_read(&fcport->state) != FCS_ONLINE) 5434 return; 5435 5436 if (fcport->fp_speed == PORT_SPEED_UNKNOWN || 5437 fcport->fp_speed > ha->link_data_rate || 5438 !ha->flags.gpsc_supported) 5439 return; 5440 5441 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed, 5442 mb); 5443 if (rval != QLA_SUCCESS) { 5444 ql_dbg(ql_dbg_disc, vha, 0x2004, 5445 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n", 5446 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]); 5447 } else { 5448 ql_dbg(ql_dbg_disc, vha, 0x2005, 5449 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n", 5450 qla2x00_get_link_speed_str(ha, fcport->fp_speed), 5451 fcport->fp_speed, fcport->port_name); 5452 } 5453 } 5454 5455 void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport) 5456 { 5457 qla2x00_iidma_fcport(vha, fcport); 5458 qla24xx_update_fcport_fcp_prio(vha, fcport); 5459 } 5460 5461 int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport) 5462 { 5463 struct qla_work_evt *e; 5464 5465 e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA); 5466 if (!e) 5467 return QLA_FUNCTION_FAILED; 5468 5469 e->u.fcport.fcport = fcport; 5470 return qla2x00_post_work(vha, e); 5471 } 5472 5473 /* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/ 5474 static void 5475 qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport) 5476 { 5477 struct fc_rport_identifiers rport_ids; 5478 struct fc_rport *rport; 5479 unsigned long flags; 5480 5481 if (atomic_read(&fcport->state) == FCS_ONLINE) 5482 return; 5483 5484 rport_ids.node_name = wwn_to_u64(fcport->node_name); 5485 rport_ids.port_name = wwn_to_u64(fcport->port_name); 5486 rport_ids.port_id = fcport->d_id.b.domain << 16 | 5487 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa; 5488 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; 5489 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids); 5490 if (!rport) { 5491 ql_log(ql_log_warn, vha, 0x2006, 5492 "Unable to allocate fc remote port.\n"); 5493 return; 5494 } 5495 5496 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 5497 *((fc_port_t **)rport->dd_data) = fcport; 5498 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 5499 fcport->dev_loss_tmo = rport->dev_loss_tmo; 5500 5501 rport->supported_classes = fcport->supported_classes; 5502 5503 rport_ids.roles = FC_PORT_ROLE_UNKNOWN; 5504 if (fcport->port_type == FCT_INITIATOR) 5505 rport_ids.roles |= FC_PORT_ROLE_FCP_INITIATOR; 5506 if (fcport->port_type == FCT_TARGET) 5507 rport_ids.roles |= FC_PORT_ROLE_FCP_TARGET; 5508 if (fcport->port_type & FCT_NVME_INITIATOR) 5509 rport_ids.roles |= FC_PORT_ROLE_NVME_INITIATOR; 5510 if (fcport->port_type & FCT_NVME_TARGET) 5511 rport_ids.roles |= FC_PORT_ROLE_NVME_TARGET; 5512 if (fcport->port_type & FCT_NVME_DISCOVERY) 5513 rport_ids.roles |= FC_PORT_ROLE_NVME_DISCOVERY; 5514 5515 ql_dbg(ql_dbg_disc, vha, 0x20ee, 5516 "%s %8phN. rport %p is %s mode\n", 5517 __func__, fcport->port_name, rport, 5518 (fcport->port_type == FCT_TARGET) ? "tgt" : 5519 ((fcport->port_type & FCT_NVME) ? "nvme" : "ini")); 5520 5521 fc_remote_port_rolechg(rport, rport_ids.roles); 5522 } 5523 5524 /* 5525 * qla2x00_update_fcport 5526 * Updates device on list. 5527 * 5528 * Input: 5529 * ha = adapter block pointer. 5530 * fcport = port structure pointer. 5531 * 5532 * Return: 5533 * 0 - Success 5534 * BIT_0 - error 5535 * 5536 * Context: 5537 * Kernel context. 5538 */ 5539 void 5540 qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 5541 { 5542 if (IS_SW_RESV_ADDR(fcport->d_id)) 5543 return; 5544 5545 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n", 5546 __func__, fcport->port_name); 5547 5548 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5549 fcport->login_retry = vha->hw->login_retry_count; 5550 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 5551 fcport->deleted = 0; 5552 if (vha->hw->current_topology == ISP_CFG_NL) 5553 fcport->logout_on_delete = 0; 5554 else 5555 fcport->logout_on_delete = 1; 5556 fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0; 5557 5558 if (fcport->tgt_link_down_time < fcport->dev_loss_tmo) { 5559 fcport->tgt_short_link_down_cnt++; 5560 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 5561 } 5562 5563 switch (vha->hw->current_topology) { 5564 case ISP_CFG_N: 5565 case ISP_CFG_NL: 5566 fcport->keep_nport_handle = 1; 5567 break; 5568 default: 5569 break; 5570 } 5571 5572 qla2x00_iidma_fcport(vha, fcport); 5573 5574 qla2x00_dfs_create_rport(vha, fcport); 5575 5576 if (NVME_TARGET(vha->hw, fcport)) { 5577 qla_nvme_register_remote(vha, fcport); 5578 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE); 5579 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 5580 return; 5581 } 5582 5583 qla24xx_update_fcport_fcp_prio(vha, fcport); 5584 5585 switch (vha->host->active_mode) { 5586 case MODE_INITIATOR: 5587 qla2x00_reg_remote_port(vha, fcport); 5588 break; 5589 case MODE_TARGET: 5590 if (!vha->vha_tgt.qla_tgt->tgt_stop && 5591 !vha->vha_tgt.qla_tgt->tgt_stopped) 5592 qlt_fc_port_added(vha, fcport); 5593 break; 5594 case MODE_DUAL: 5595 qla2x00_reg_remote_port(vha, fcport); 5596 if (!vha->vha_tgt.qla_tgt->tgt_stop && 5597 !vha->vha_tgt.qla_tgt->tgt_stopped) 5598 qlt_fc_port_added(vha, fcport); 5599 break; 5600 default: 5601 break; 5602 } 5603 5604 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 5605 5606 if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) { 5607 if (fcport->id_changed) { 5608 fcport->id_changed = 0; 5609 ql_dbg(ql_dbg_disc, vha, 0x20d7, 5610 "%s %d %8phC post gfpnid fcp_cnt %d\n", 5611 __func__, __LINE__, fcport->port_name, 5612 vha->fcport_count); 5613 qla24xx_post_gfpnid_work(vha, fcport); 5614 } else { 5615 ql_dbg(ql_dbg_disc, vha, 0x20d7, 5616 "%s %d %8phC post gpsc fcp_cnt %d\n", 5617 __func__, __LINE__, fcport->port_name, 5618 vha->fcport_count); 5619 qla24xx_post_gpsc_work(vha, fcport); 5620 } 5621 } 5622 5623 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE); 5624 } 5625 5626 void qla_register_fcport_fn(struct work_struct *work) 5627 { 5628 fc_port_t *fcport = container_of(work, struct fc_port, reg_work); 5629 u32 rscn_gen = fcport->rscn_gen; 5630 u16 data[2]; 5631 5632 if (IS_SW_RESV_ADDR(fcport->d_id)) 5633 return; 5634 5635 qla2x00_update_fcport(fcport->vha, fcport); 5636 5637 if (rscn_gen != fcport->rscn_gen) { 5638 /* RSCN(s) came in while registration */ 5639 switch (fcport->next_disc_state) { 5640 case DSC_DELETE_PEND: 5641 qlt_schedule_sess_for_deletion(fcport); 5642 break; 5643 case DSC_ADISC: 5644 data[0] = data[1] = 0; 5645 qla2x00_post_async_adisc_work(fcport->vha, fcport, 5646 data); 5647 break; 5648 default: 5649 break; 5650 } 5651 } 5652 } 5653 5654 /* 5655 * qla2x00_configure_fabric 5656 * Setup SNS devices with loop ID's. 5657 * 5658 * Input: 5659 * ha = adapter block pointer. 5660 * 5661 * Returns: 5662 * 0 = success. 5663 * BIT_0 = error 5664 */ 5665 static int 5666 qla2x00_configure_fabric(scsi_qla_host_t *vha) 5667 { 5668 int rval; 5669 fc_port_t *fcport; 5670 uint16_t mb[MAILBOX_REGISTER_COUNT]; 5671 uint16_t loop_id; 5672 LIST_HEAD(new_fcports); 5673 struct qla_hw_data *ha = vha->hw; 5674 int discovery_gen; 5675 5676 /* If FL port exists, then SNS is present */ 5677 if (IS_FWI2_CAPABLE(ha)) 5678 loop_id = NPH_F_PORT; 5679 else 5680 loop_id = SNS_FL_PORT; 5681 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1); 5682 if (rval != QLA_SUCCESS) { 5683 ql_dbg(ql_dbg_disc, vha, 0x20a0, 5684 "MBX_GET_PORT_NAME failed, No FL Port.\n"); 5685 5686 vha->device_flags &= ~SWITCH_FOUND; 5687 return (QLA_SUCCESS); 5688 } 5689 vha->device_flags |= SWITCH_FOUND; 5690 5691 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_port_name, 0); 5692 if (rval != QLA_SUCCESS) 5693 ql_dbg(ql_dbg_disc, vha, 0x20ff, 5694 "Failed to get Fabric Port Name\n"); 5695 5696 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) { 5697 rval = qla2x00_send_change_request(vha, 0x3, 0); 5698 if (rval != QLA_SUCCESS) 5699 ql_log(ql_log_warn, vha, 0x121, 5700 "Failed to enable receiving of RSCN requests: 0x%x.\n", 5701 rval); 5702 } 5703 5704 do { 5705 qla2x00_mgmt_svr_login(vha); 5706 5707 /* Ensure we are logged into the SNS. */ 5708 loop_id = NPH_SNS_LID(ha); 5709 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff, 5710 0xfc, mb, BIT_1|BIT_0); 5711 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 5712 ql_dbg(ql_dbg_disc, vha, 0x20a1, 5713 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n", 5714 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval); 5715 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5716 return rval; 5717 } 5718 5719 /* FDMI support. */ 5720 if (ql2xfdmienable && 5721 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags)) 5722 qla2x00_fdmi_register(vha); 5723 5724 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) { 5725 if (qla2x00_rft_id(vha)) { 5726 /* EMPTY */ 5727 ql_dbg(ql_dbg_disc, vha, 0x20a2, 5728 "Register FC-4 TYPE failed.\n"); 5729 if (test_bit(LOOP_RESYNC_NEEDED, 5730 &vha->dpc_flags)) 5731 break; 5732 } 5733 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) { 5734 /* EMPTY */ 5735 ql_dbg(ql_dbg_disc, vha, 0x209a, 5736 "Register FC-4 Features failed.\n"); 5737 if (test_bit(LOOP_RESYNC_NEEDED, 5738 &vha->dpc_flags)) 5739 break; 5740 } 5741 if (vha->flags.nvme_enabled) { 5742 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) { 5743 ql_dbg(ql_dbg_disc, vha, 0x2049, 5744 "Register NVME FC Type Features failed.\n"); 5745 } 5746 } 5747 if (qla2x00_rnn_id(vha)) { 5748 /* EMPTY */ 5749 ql_dbg(ql_dbg_disc, vha, 0x2104, 5750 "Register Node Name failed.\n"); 5751 if (test_bit(LOOP_RESYNC_NEEDED, 5752 &vha->dpc_flags)) 5753 break; 5754 } else if (qla2x00_rsnn_nn(vha)) { 5755 /* EMPTY */ 5756 ql_dbg(ql_dbg_disc, vha, 0x209b, 5757 "Register Symbolic Node Name failed.\n"); 5758 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5759 break; 5760 } 5761 } 5762 5763 5764 /* Mark the time right before querying FW for connected ports. 5765 * This process is long, asynchronous and by the time it's done, 5766 * collected information might not be accurate anymore. E.g. 5767 * disconnected port might have re-connected and a brand new 5768 * session has been created. In this case session's generation 5769 * will be newer than discovery_gen. */ 5770 qlt_do_generation_tick(vha, &discovery_gen); 5771 5772 if (USE_ASYNC_SCAN(ha)) { 5773 rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI, 5774 NULL); 5775 if (rval) 5776 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5777 } else { 5778 list_for_each_entry(fcport, &vha->vp_fcports, list) 5779 fcport->scan_state = QLA_FCPORT_SCAN; 5780 5781 rval = qla2x00_find_all_fabric_devs(vha); 5782 } 5783 if (rval != QLA_SUCCESS) 5784 break; 5785 } while (0); 5786 5787 if (!vha->nvme_local_port && vha->flags.nvme_enabled) 5788 qla_nvme_register_hba(vha); 5789 5790 if (rval) 5791 ql_dbg(ql_dbg_disc, vha, 0x2068, 5792 "Configure fabric error exit rval=%d.\n", rval); 5793 5794 return (rval); 5795 } 5796 5797 /* 5798 * qla2x00_find_all_fabric_devs 5799 * 5800 * Input: 5801 * ha = adapter block pointer. 5802 * dev = database device entry pointer. 5803 * 5804 * Returns: 5805 * 0 = success. 5806 * 5807 * Context: 5808 * Kernel context. 5809 */ 5810 static int 5811 qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha) 5812 { 5813 int rval; 5814 uint16_t loop_id; 5815 fc_port_t *fcport, *new_fcport; 5816 int found; 5817 5818 sw_info_t *swl; 5819 int swl_idx; 5820 int first_dev, last_dev; 5821 port_id_t wrap = {}, nxt_d_id; 5822 struct qla_hw_data *ha = vha->hw; 5823 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 5824 unsigned long flags; 5825 5826 rval = QLA_SUCCESS; 5827 5828 /* Try GID_PT to get device list, else GAN. */ 5829 if (!ha->swl) 5830 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t), 5831 GFP_KERNEL); 5832 swl = ha->swl; 5833 if (!swl) { 5834 /*EMPTY*/ 5835 ql_dbg(ql_dbg_disc, vha, 0x209c, 5836 "GID_PT allocations failed, fallback on GA_NXT.\n"); 5837 } else { 5838 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t)); 5839 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) { 5840 swl = NULL; 5841 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5842 return rval; 5843 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) { 5844 swl = NULL; 5845 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5846 return rval; 5847 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) { 5848 swl = NULL; 5849 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5850 return rval; 5851 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) { 5852 swl = NULL; 5853 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5854 return rval; 5855 } 5856 5857 /* If other queries succeeded probe for FC-4 type */ 5858 if (swl) { 5859 qla2x00_gff_id(vha, swl); 5860 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5861 return rval; 5862 } 5863 } 5864 swl_idx = 0; 5865 5866 /* Allocate temporary fcport for any new fcports discovered. */ 5867 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5868 if (new_fcport == NULL) { 5869 ql_log(ql_log_warn, vha, 0x209d, 5870 "Failed to allocate memory for fcport.\n"); 5871 return (QLA_MEMORY_ALLOC_FAILED); 5872 } 5873 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 5874 /* Set start port ID scan at adapter ID. */ 5875 first_dev = 1; 5876 last_dev = 0; 5877 5878 /* Starting free loop ID. */ 5879 loop_id = ha->min_external_loopid; 5880 for (; loop_id <= ha->max_loop_id; loop_id++) { 5881 if (qla2x00_is_reserved_id(vha, loop_id)) 5882 continue; 5883 5884 if (ha->current_topology == ISP_CFG_FL && 5885 (atomic_read(&vha->loop_down_timer) || 5886 LOOP_TRANSITION(vha))) { 5887 atomic_set(&vha->loop_down_timer, 0); 5888 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5889 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5890 break; 5891 } 5892 5893 if (swl != NULL) { 5894 if (last_dev) { 5895 wrap.b24 = new_fcport->d_id.b24; 5896 } else { 5897 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24; 5898 memcpy(new_fcport->node_name, 5899 swl[swl_idx].node_name, WWN_SIZE); 5900 memcpy(new_fcport->port_name, 5901 swl[swl_idx].port_name, WWN_SIZE); 5902 memcpy(new_fcport->fabric_port_name, 5903 swl[swl_idx].fabric_port_name, WWN_SIZE); 5904 new_fcport->fp_speed = swl[swl_idx].fp_speed; 5905 new_fcport->fc4_type = swl[swl_idx].fc4_type; 5906 5907 new_fcport->nvme_flag = 0; 5908 if (vha->flags.nvme_enabled && 5909 swl[swl_idx].fc4_type & FS_FC4TYPE_NVME) { 5910 ql_log(ql_log_info, vha, 0x2131, 5911 "FOUND: NVME port %8phC as FC Type 28h\n", 5912 new_fcport->port_name); 5913 } 5914 5915 if (swl[swl_idx].d_id.b.rsvd_1 != 0) { 5916 last_dev = 1; 5917 } 5918 swl_idx++; 5919 } 5920 } else { 5921 /* Send GA_NXT to the switch */ 5922 rval = qla2x00_ga_nxt(vha, new_fcport); 5923 if (rval != QLA_SUCCESS) { 5924 ql_log(ql_log_warn, vha, 0x209e, 5925 "SNS scan failed -- assuming " 5926 "zero-entry result.\n"); 5927 rval = QLA_SUCCESS; 5928 break; 5929 } 5930 } 5931 5932 /* If wrap on switch device list, exit. */ 5933 if (first_dev) { 5934 wrap.b24 = new_fcport->d_id.b24; 5935 first_dev = 0; 5936 } else if (new_fcport->d_id.b24 == wrap.b24) { 5937 ql_dbg(ql_dbg_disc, vha, 0x209f, 5938 "Device wrap (%02x%02x%02x).\n", 5939 new_fcport->d_id.b.domain, 5940 new_fcport->d_id.b.area, 5941 new_fcport->d_id.b.al_pa); 5942 break; 5943 } 5944 5945 /* Bypass if same physical adapter. */ 5946 if (new_fcport->d_id.b24 == base_vha->d_id.b24) 5947 continue; 5948 5949 /* Bypass virtual ports of the same host. */ 5950 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24)) 5951 continue; 5952 5953 /* Bypass if same domain and area of adapter. */ 5954 if (((new_fcport->d_id.b24 & 0xffff00) == 5955 (vha->d_id.b24 & 0xffff00)) && ha->current_topology == 5956 ISP_CFG_FL) 5957 continue; 5958 5959 /* Bypass reserved domain fields. */ 5960 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0) 5961 continue; 5962 5963 /* Bypass ports whose FCP-4 type is not FCP_SCSI */ 5964 if (ql2xgffidenable && 5965 (!(new_fcport->fc4_type & FS_FC4TYPE_FCP) && 5966 new_fcport->fc4_type != 0)) 5967 continue; 5968 5969 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5970 5971 /* Locate matching device in database. */ 5972 found = 0; 5973 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5974 if (memcmp(new_fcport->port_name, fcport->port_name, 5975 WWN_SIZE)) 5976 continue; 5977 5978 fcport->scan_state = QLA_FCPORT_FOUND; 5979 5980 found++; 5981 5982 /* Update port state. */ 5983 memcpy(fcport->fabric_port_name, 5984 new_fcport->fabric_port_name, WWN_SIZE); 5985 fcport->fp_speed = new_fcport->fp_speed; 5986 5987 /* 5988 * If address the same and state FCS_ONLINE 5989 * (or in target mode), nothing changed. 5990 */ 5991 if (fcport->d_id.b24 == new_fcport->d_id.b24 && 5992 (atomic_read(&fcport->state) == FCS_ONLINE || 5993 (vha->host->active_mode == MODE_TARGET))) { 5994 break; 5995 } 5996 5997 if (fcport->login_retry == 0) 5998 fcport->login_retry = 5999 vha->hw->login_retry_count; 6000 /* 6001 * If device was not a fabric device before. 6002 */ 6003 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) { 6004 fcport->d_id.b24 = new_fcport->d_id.b24; 6005 qla2x00_clear_loop_id(fcport); 6006 fcport->flags |= (FCF_FABRIC_DEVICE | 6007 FCF_LOGIN_NEEDED); 6008 break; 6009 } 6010 6011 /* 6012 * Port ID changed or device was marked to be updated; 6013 * Log it out if still logged in and mark it for 6014 * relogin later. 6015 */ 6016 if (qla_tgt_mode_enabled(base_vha)) { 6017 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080, 6018 "port changed FC ID, %8phC" 6019 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n", 6020 fcport->port_name, 6021 fcport->d_id.b.domain, 6022 fcport->d_id.b.area, 6023 fcport->d_id.b.al_pa, 6024 fcport->loop_id, 6025 new_fcport->d_id.b.domain, 6026 new_fcport->d_id.b.area, 6027 new_fcport->d_id.b.al_pa); 6028 fcport->d_id.b24 = new_fcport->d_id.b24; 6029 break; 6030 } 6031 6032 fcport->d_id.b24 = new_fcport->d_id.b24; 6033 fcport->flags |= FCF_LOGIN_NEEDED; 6034 break; 6035 } 6036 6037 if (found && NVME_TARGET(vha->hw, fcport)) { 6038 if (fcport->disc_state == DSC_DELETE_PEND) { 6039 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 6040 vha->fcport_count--; 6041 fcport->login_succ = 0; 6042 } 6043 } 6044 6045 if (found) { 6046 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6047 continue; 6048 } 6049 /* If device was not in our fcports list, then add it. */ 6050 new_fcport->scan_state = QLA_FCPORT_FOUND; 6051 list_add_tail(&new_fcport->list, &vha->vp_fcports); 6052 6053 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6054 6055 6056 /* Allocate a new replacement fcport. */ 6057 nxt_d_id.b24 = new_fcport->d_id.b24; 6058 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 6059 if (new_fcport == NULL) { 6060 ql_log(ql_log_warn, vha, 0xd032, 6061 "Memory allocation failed for fcport.\n"); 6062 return (QLA_MEMORY_ALLOC_FAILED); 6063 } 6064 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 6065 new_fcport->d_id.b24 = nxt_d_id.b24; 6066 } 6067 6068 qla2x00_free_fcport(new_fcport); 6069 6070 /* 6071 * Logout all previous fabric dev marked lost, except FCP2 devices. 6072 */ 6073 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6074 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6075 break; 6076 6077 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) 6078 continue; 6079 6080 if (fcport->scan_state == QLA_FCPORT_SCAN) { 6081 if ((qla_dual_mode_enabled(vha) || 6082 qla_ini_mode_enabled(vha)) && 6083 atomic_read(&fcport->state) == FCS_ONLINE) { 6084 qla2x00_mark_device_lost(vha, fcport, 6085 ql2xplogiabsentdevice); 6086 if (fcport->loop_id != FC_NO_LOOP_ID && 6087 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 6088 fcport->port_type != FCT_INITIATOR && 6089 fcport->port_type != FCT_BROADCAST) { 6090 ql_dbg(ql_dbg_disc, vha, 0x20f0, 6091 "%s %d %8phC post del sess\n", 6092 __func__, __LINE__, 6093 fcport->port_name); 6094 qlt_schedule_sess_for_deletion(fcport); 6095 continue; 6096 } 6097 } 6098 } 6099 6100 if (fcport->scan_state == QLA_FCPORT_FOUND && 6101 (fcport->flags & FCF_LOGIN_NEEDED) != 0) 6102 qla24xx_fcport_handle_login(vha, fcport); 6103 } 6104 return (rval); 6105 } 6106 6107 /* FW does not set aside Loop id for MGMT Server/FFFFFAh */ 6108 int 6109 qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha) 6110 { 6111 int loop_id = FC_NO_LOOP_ID; 6112 int lid = NPH_MGMT_SERVER - vha->vp_idx; 6113 unsigned long flags; 6114 struct qla_hw_data *ha = vha->hw; 6115 6116 if (vha->vp_idx == 0) { 6117 set_bit(NPH_MGMT_SERVER, ha->loop_id_map); 6118 return NPH_MGMT_SERVER; 6119 } 6120 6121 /* pick id from high and work down to low */ 6122 spin_lock_irqsave(&ha->vport_slock, flags); 6123 for (; lid > 0; lid--) { 6124 if (!test_bit(lid, vha->hw->loop_id_map)) { 6125 set_bit(lid, vha->hw->loop_id_map); 6126 loop_id = lid; 6127 break; 6128 } 6129 } 6130 spin_unlock_irqrestore(&ha->vport_slock, flags); 6131 6132 return loop_id; 6133 } 6134 6135 /* 6136 * qla2x00_fabric_login 6137 * Issue fabric login command. 6138 * 6139 * Input: 6140 * ha = adapter block pointer. 6141 * device = pointer to FC device type structure. 6142 * 6143 * Returns: 6144 * 0 - Login successfully 6145 * 1 - Login failed 6146 * 2 - Initiator device 6147 * 3 - Fatal error 6148 */ 6149 int 6150 qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport, 6151 uint16_t *next_loopid) 6152 { 6153 int rval; 6154 int retry; 6155 uint16_t tmp_loopid; 6156 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6157 struct qla_hw_data *ha = vha->hw; 6158 6159 retry = 0; 6160 tmp_loopid = 0; 6161 6162 for (;;) { 6163 ql_dbg(ql_dbg_disc, vha, 0x2000, 6164 "Trying Fabric Login w/loop id 0x%04x for port " 6165 "%02x%02x%02x.\n", 6166 fcport->loop_id, fcport->d_id.b.domain, 6167 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6168 6169 /* Login fcport on switch. */ 6170 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id, 6171 fcport->d_id.b.domain, fcport->d_id.b.area, 6172 fcport->d_id.b.al_pa, mb, BIT_0); 6173 if (rval != QLA_SUCCESS) { 6174 return rval; 6175 } 6176 if (mb[0] == MBS_PORT_ID_USED) { 6177 /* 6178 * Device has another loop ID. The firmware team 6179 * recommends the driver perform an implicit login with 6180 * the specified ID again. The ID we just used is save 6181 * here so we return with an ID that can be tried by 6182 * the next login. 6183 */ 6184 retry++; 6185 tmp_loopid = fcport->loop_id; 6186 fcport->loop_id = mb[1]; 6187 6188 ql_dbg(ql_dbg_disc, vha, 0x2001, 6189 "Fabric Login: port in use - next loop " 6190 "id=0x%04x, port id= %02x%02x%02x.\n", 6191 fcport->loop_id, fcport->d_id.b.domain, 6192 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6193 6194 } else if (mb[0] == MBS_COMMAND_COMPLETE) { 6195 /* 6196 * Login succeeded. 6197 */ 6198 if (retry) { 6199 /* A retry occurred before. */ 6200 *next_loopid = tmp_loopid; 6201 } else { 6202 /* 6203 * No retry occurred before. Just increment the 6204 * ID value for next login. 6205 */ 6206 *next_loopid = (fcport->loop_id + 1); 6207 } 6208 6209 if (mb[1] & BIT_0) { 6210 fcport->port_type = FCT_INITIATOR; 6211 } else { 6212 fcport->port_type = FCT_TARGET; 6213 if (mb[1] & BIT_1) { 6214 fcport->flags |= FCF_FCP2_DEVICE; 6215 } 6216 } 6217 6218 if (mb[10] & BIT_0) 6219 fcport->supported_classes |= FC_COS_CLASS2; 6220 if (mb[10] & BIT_1) 6221 fcport->supported_classes |= FC_COS_CLASS3; 6222 6223 if (IS_FWI2_CAPABLE(ha)) { 6224 if (mb[10] & BIT_7) 6225 fcport->flags |= 6226 FCF_CONF_COMP_SUPPORTED; 6227 } 6228 6229 rval = QLA_SUCCESS; 6230 break; 6231 } else if (mb[0] == MBS_LOOP_ID_USED) { 6232 /* 6233 * Loop ID already used, try next loop ID. 6234 */ 6235 fcport->loop_id++; 6236 rval = qla2x00_find_new_loop_id(vha, fcport); 6237 if (rval != QLA_SUCCESS) { 6238 /* Ran out of loop IDs to use */ 6239 break; 6240 } 6241 } else if (mb[0] == MBS_COMMAND_ERROR) { 6242 /* 6243 * Firmware possibly timed out during login. If NO 6244 * retries are left to do then the device is declared 6245 * dead. 6246 */ 6247 *next_loopid = fcport->loop_id; 6248 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 6249 fcport->d_id.b.domain, fcport->d_id.b.area, 6250 fcport->d_id.b.al_pa); 6251 qla2x00_mark_device_lost(vha, fcport, 1); 6252 6253 rval = 1; 6254 break; 6255 } else { 6256 /* 6257 * unrecoverable / not handled error 6258 */ 6259 ql_dbg(ql_dbg_disc, vha, 0x2002, 6260 "Failed=%x port_id=%02x%02x%02x loop_id=%x " 6261 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain, 6262 fcport->d_id.b.area, fcport->d_id.b.al_pa, 6263 fcport->loop_id, jiffies); 6264 6265 *next_loopid = fcport->loop_id; 6266 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 6267 fcport->d_id.b.domain, fcport->d_id.b.area, 6268 fcport->d_id.b.al_pa); 6269 qla2x00_clear_loop_id(fcport); 6270 fcport->login_retry = 0; 6271 6272 rval = 3; 6273 break; 6274 } 6275 } 6276 6277 return (rval); 6278 } 6279 6280 /* 6281 * qla2x00_local_device_login 6282 * Issue local device login command. 6283 * 6284 * Input: 6285 * ha = adapter block pointer. 6286 * loop_id = loop id of device to login to. 6287 * 6288 * Returns (Where's the #define!!!!): 6289 * 0 - Login successfully 6290 * 1 - Login failed 6291 * 3 - Fatal error 6292 */ 6293 int 6294 qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport) 6295 { 6296 int rval; 6297 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6298 6299 memset(mb, 0, sizeof(mb)); 6300 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0); 6301 if (rval == QLA_SUCCESS) { 6302 /* Interrogate mailbox registers for any errors */ 6303 if (mb[0] == MBS_COMMAND_ERROR) 6304 rval = 1; 6305 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR) 6306 /* device not in PCB table */ 6307 rval = 3; 6308 } 6309 6310 return (rval); 6311 } 6312 6313 /* 6314 * qla2x00_loop_resync 6315 * Resync with fibre channel devices. 6316 * 6317 * Input: 6318 * ha = adapter block pointer. 6319 * 6320 * Returns: 6321 * 0 = success 6322 */ 6323 int 6324 qla2x00_loop_resync(scsi_qla_host_t *vha) 6325 { 6326 int rval = QLA_SUCCESS; 6327 uint32_t wait_time; 6328 6329 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 6330 if (vha->flags.online) { 6331 if (!(rval = qla2x00_fw_ready(vha))) { 6332 /* Wait at most MAX_TARGET RSCNs for a stable link. */ 6333 wait_time = 256; 6334 do { 6335 if (!IS_QLAFX00(vha->hw)) { 6336 /* 6337 * Issue a marker after FW becomes 6338 * ready. 6339 */ 6340 qla2x00_marker(vha, vha->hw->base_qpair, 6341 0, 0, MK_SYNC_ALL); 6342 vha->marker_needed = 0; 6343 } 6344 6345 /* Remap devices on Loop. */ 6346 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 6347 6348 if (IS_QLAFX00(vha->hw)) 6349 qlafx00_configure_devices(vha); 6350 else 6351 qla2x00_configure_loop(vha); 6352 6353 wait_time--; 6354 } while (!atomic_read(&vha->loop_down_timer) && 6355 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 6356 && wait_time && (test_bit(LOOP_RESYNC_NEEDED, 6357 &vha->dpc_flags))); 6358 } 6359 } 6360 6361 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 6362 return (QLA_FUNCTION_FAILED); 6363 6364 if (rval) 6365 ql_dbg(ql_dbg_disc, vha, 0x206c, 6366 "%s *** FAILED ***.\n", __func__); 6367 6368 return (rval); 6369 } 6370 6371 /* 6372 * qla2x00_perform_loop_resync 6373 * Description: This function will set the appropriate flags and call 6374 * qla2x00_loop_resync. If successful loop will be resynced 6375 * Arguments : scsi_qla_host_t pointer 6376 * returm : Success or Failure 6377 */ 6378 6379 int qla2x00_perform_loop_resync(scsi_qla_host_t *ha) 6380 { 6381 int32_t rval = 0; 6382 6383 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) { 6384 /*Configure the flags so that resync happens properly*/ 6385 atomic_set(&ha->loop_down_timer, 0); 6386 if (!(ha->device_flags & DFLG_NO_CABLE)) { 6387 atomic_set(&ha->loop_state, LOOP_UP); 6388 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); 6389 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); 6390 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); 6391 6392 rval = qla2x00_loop_resync(ha); 6393 } else 6394 atomic_set(&ha->loop_state, LOOP_DEAD); 6395 6396 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags); 6397 } 6398 6399 return rval; 6400 } 6401 6402 void 6403 qla2x00_update_fcports(scsi_qla_host_t *base_vha) 6404 { 6405 fc_port_t *fcport; 6406 struct scsi_qla_host *vha; 6407 struct qla_hw_data *ha = base_vha->hw; 6408 unsigned long flags; 6409 6410 spin_lock_irqsave(&ha->vport_slock, flags); 6411 /* Go with deferred removal of rport references. */ 6412 list_for_each_entry(vha, &base_vha->hw->vp_list, list) { 6413 atomic_inc(&vha->vref_count); 6414 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6415 if (fcport->drport && 6416 atomic_read(&fcport->state) != FCS_UNCONFIGURED) { 6417 spin_unlock_irqrestore(&ha->vport_slock, flags); 6418 qla2x00_rport_del(fcport); 6419 6420 spin_lock_irqsave(&ha->vport_slock, flags); 6421 } 6422 } 6423 atomic_dec(&vha->vref_count); 6424 wake_up(&vha->vref_waitq); 6425 } 6426 spin_unlock_irqrestore(&ha->vport_slock, flags); 6427 } 6428 6429 /* Assumes idc_lock always held on entry */ 6430 void 6431 qla83xx_reset_ownership(scsi_qla_host_t *vha) 6432 { 6433 struct qla_hw_data *ha = vha->hw; 6434 uint32_t drv_presence, drv_presence_mask; 6435 uint32_t dev_part_info1, dev_part_info2, class_type; 6436 uint32_t class_type_mask = 0x3; 6437 uint16_t fcoe_other_function = 0xffff, i; 6438 6439 if (IS_QLA8044(ha)) { 6440 drv_presence = qla8044_rd_direct(vha, 6441 QLA8044_CRB_DRV_ACTIVE_INDEX); 6442 dev_part_info1 = qla8044_rd_direct(vha, 6443 QLA8044_CRB_DEV_PART_INFO_INDEX); 6444 dev_part_info2 = qla8044_rd_direct(vha, 6445 QLA8044_CRB_DEV_PART_INFO2); 6446 } else { 6447 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6448 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1); 6449 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2); 6450 } 6451 for (i = 0; i < 8; i++) { 6452 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask); 6453 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 6454 (i != ha->portnum)) { 6455 fcoe_other_function = i; 6456 break; 6457 } 6458 } 6459 if (fcoe_other_function == 0xffff) { 6460 for (i = 0; i < 8; i++) { 6461 class_type = ((dev_part_info2 >> (i * 4)) & 6462 class_type_mask); 6463 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 6464 ((i + 8) != ha->portnum)) { 6465 fcoe_other_function = i + 8; 6466 break; 6467 } 6468 } 6469 } 6470 /* 6471 * Prepare drv-presence mask based on fcoe functions present. 6472 * However consider only valid physical fcoe function numbers (0-15). 6473 */ 6474 drv_presence_mask = ~((1 << (ha->portnum)) | 6475 ((fcoe_other_function == 0xffff) ? 6476 0 : (1 << (fcoe_other_function)))); 6477 6478 /* We are the reset owner iff: 6479 * - No other protocol drivers present. 6480 * - This is the lowest among fcoe functions. */ 6481 if (!(drv_presence & drv_presence_mask) && 6482 (ha->portnum < fcoe_other_function)) { 6483 ql_dbg(ql_dbg_p3p, vha, 0xb07f, 6484 "This host is Reset owner.\n"); 6485 ha->flags.nic_core_reset_owner = 1; 6486 } 6487 } 6488 6489 static int 6490 __qla83xx_set_drv_ack(scsi_qla_host_t *vha) 6491 { 6492 int rval = QLA_SUCCESS; 6493 struct qla_hw_data *ha = vha->hw; 6494 uint32_t drv_ack; 6495 6496 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6497 if (rval == QLA_SUCCESS) { 6498 drv_ack |= (1 << ha->portnum); 6499 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 6500 } 6501 6502 return rval; 6503 } 6504 6505 static int 6506 __qla83xx_clear_drv_ack(scsi_qla_host_t *vha) 6507 { 6508 int rval = QLA_SUCCESS; 6509 struct qla_hw_data *ha = vha->hw; 6510 uint32_t drv_ack; 6511 6512 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6513 if (rval == QLA_SUCCESS) { 6514 drv_ack &= ~(1 << ha->portnum); 6515 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 6516 } 6517 6518 return rval; 6519 } 6520 6521 static const char * 6522 qla83xx_dev_state_to_string(uint32_t dev_state) 6523 { 6524 switch (dev_state) { 6525 case QLA8XXX_DEV_COLD: 6526 return "COLD/RE-INIT"; 6527 case QLA8XXX_DEV_INITIALIZING: 6528 return "INITIALIZING"; 6529 case QLA8XXX_DEV_READY: 6530 return "READY"; 6531 case QLA8XXX_DEV_NEED_RESET: 6532 return "NEED RESET"; 6533 case QLA8XXX_DEV_NEED_QUIESCENT: 6534 return "NEED QUIESCENT"; 6535 case QLA8XXX_DEV_FAILED: 6536 return "FAILED"; 6537 case QLA8XXX_DEV_QUIESCENT: 6538 return "QUIESCENT"; 6539 default: 6540 return "Unknown"; 6541 } 6542 } 6543 6544 /* Assumes idc-lock always held on entry */ 6545 void 6546 qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type) 6547 { 6548 struct qla_hw_data *ha = vha->hw; 6549 uint32_t idc_audit_reg = 0, duration_secs = 0; 6550 6551 switch (audit_type) { 6552 case IDC_AUDIT_TIMESTAMP: 6553 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000); 6554 idc_audit_reg = (ha->portnum) | 6555 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8); 6556 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 6557 break; 6558 6559 case IDC_AUDIT_COMPLETION: 6560 duration_secs = ((jiffies_to_msecs(jiffies) - 6561 jiffies_to_msecs(ha->idc_audit_ts)) / 1000); 6562 idc_audit_reg = (ha->portnum) | 6563 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8); 6564 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 6565 break; 6566 6567 default: 6568 ql_log(ql_log_warn, vha, 0xb078, 6569 "Invalid audit type specified.\n"); 6570 break; 6571 } 6572 } 6573 6574 /* Assumes idc_lock always held on entry */ 6575 static int 6576 qla83xx_initiating_reset(scsi_qla_host_t *vha) 6577 { 6578 struct qla_hw_data *ha = vha->hw; 6579 uint32_t idc_control, dev_state; 6580 6581 __qla83xx_get_idc_control(vha, &idc_control); 6582 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) { 6583 ql_log(ql_log_info, vha, 0xb080, 6584 "NIC Core reset has been disabled. idc-control=0x%x\n", 6585 idc_control); 6586 return QLA_FUNCTION_FAILED; 6587 } 6588 6589 /* Set NEED-RESET iff in READY state and we are the reset-owner */ 6590 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6591 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) { 6592 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 6593 QLA8XXX_DEV_NEED_RESET); 6594 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n"); 6595 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP); 6596 } else { 6597 const char *state = qla83xx_dev_state_to_string(dev_state); 6598 6599 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state); 6600 6601 /* SV: XXX: Is timeout required here? */ 6602 /* Wait for IDC state change READY -> NEED_RESET */ 6603 while (dev_state == QLA8XXX_DEV_READY) { 6604 qla83xx_idc_unlock(vha, 0); 6605 msleep(200); 6606 qla83xx_idc_lock(vha, 0); 6607 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6608 } 6609 } 6610 6611 /* Send IDC ack by writing to drv-ack register */ 6612 __qla83xx_set_drv_ack(vha); 6613 6614 return QLA_SUCCESS; 6615 } 6616 6617 int 6618 __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) 6619 { 6620 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 6621 } 6622 6623 int 6624 __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) 6625 { 6626 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 6627 } 6628 6629 static int 6630 qla83xx_check_driver_presence(scsi_qla_host_t *vha) 6631 { 6632 uint32_t drv_presence = 0; 6633 struct qla_hw_data *ha = vha->hw; 6634 6635 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6636 if (drv_presence & (1 << ha->portnum)) 6637 return QLA_SUCCESS; 6638 else 6639 return QLA_TEST_FAILED; 6640 } 6641 6642 int 6643 qla83xx_nic_core_reset(scsi_qla_host_t *vha) 6644 { 6645 int rval = QLA_SUCCESS; 6646 struct qla_hw_data *ha = vha->hw; 6647 6648 ql_dbg(ql_dbg_p3p, vha, 0xb058, 6649 "Entered %s().\n", __func__); 6650 6651 if (vha->device_flags & DFLG_DEV_FAILED) { 6652 ql_log(ql_log_warn, vha, 0xb059, 6653 "Device in unrecoverable FAILED state.\n"); 6654 return QLA_FUNCTION_FAILED; 6655 } 6656 6657 qla83xx_idc_lock(vha, 0); 6658 6659 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) { 6660 ql_log(ql_log_warn, vha, 0xb05a, 6661 "Function=0x%x has been removed from IDC participation.\n", 6662 ha->portnum); 6663 rval = QLA_FUNCTION_FAILED; 6664 goto exit; 6665 } 6666 6667 qla83xx_reset_ownership(vha); 6668 6669 rval = qla83xx_initiating_reset(vha); 6670 6671 /* 6672 * Perform reset if we are the reset-owner, 6673 * else wait till IDC state changes to READY/FAILED. 6674 */ 6675 if (rval == QLA_SUCCESS) { 6676 rval = qla83xx_idc_state_handler(vha); 6677 6678 if (rval == QLA_SUCCESS) 6679 ha->flags.nic_core_hung = 0; 6680 __qla83xx_clear_drv_ack(vha); 6681 } 6682 6683 exit: 6684 qla83xx_idc_unlock(vha, 0); 6685 6686 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__); 6687 6688 return rval; 6689 } 6690 6691 int 6692 qla2xxx_mctp_dump(scsi_qla_host_t *vha) 6693 { 6694 struct qla_hw_data *ha = vha->hw; 6695 int rval = QLA_FUNCTION_FAILED; 6696 6697 if (!IS_MCTP_CAPABLE(ha)) { 6698 /* This message can be removed from the final version */ 6699 ql_log(ql_log_info, vha, 0x506d, 6700 "This board is not MCTP capable\n"); 6701 return rval; 6702 } 6703 6704 if (!ha->mctp_dump) { 6705 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev, 6706 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL); 6707 6708 if (!ha->mctp_dump) { 6709 ql_log(ql_log_warn, vha, 0x506e, 6710 "Failed to allocate memory for mctp dump\n"); 6711 return rval; 6712 } 6713 } 6714 6715 #define MCTP_DUMP_STR_ADDR 0x00000000 6716 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma, 6717 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4); 6718 if (rval != QLA_SUCCESS) { 6719 ql_log(ql_log_warn, vha, 0x506f, 6720 "Failed to capture mctp dump\n"); 6721 } else { 6722 ql_log(ql_log_info, vha, 0x5070, 6723 "Mctp dump capture for host (%ld/%p).\n", 6724 vha->host_no, ha->mctp_dump); 6725 ha->mctp_dumped = 1; 6726 } 6727 6728 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) { 6729 ha->flags.nic_core_reset_hdlr_active = 1; 6730 rval = qla83xx_restart_nic_firmware(vha); 6731 if (rval) 6732 /* NIC Core reset failed. */ 6733 ql_log(ql_log_warn, vha, 0x5071, 6734 "Failed to restart nic firmware\n"); 6735 else 6736 ql_dbg(ql_dbg_p3p, vha, 0xb084, 6737 "Restarted NIC firmware successfully.\n"); 6738 ha->flags.nic_core_reset_hdlr_active = 0; 6739 } 6740 6741 return rval; 6742 6743 } 6744 6745 /* 6746 * qla2x00_quiesce_io 6747 * Description: This function will block the new I/Os 6748 * Its not aborting any I/Os as context 6749 * is not destroyed during quiescence 6750 * Arguments: scsi_qla_host_t 6751 * return : void 6752 */ 6753 void 6754 qla2x00_quiesce_io(scsi_qla_host_t *vha) 6755 { 6756 struct qla_hw_data *ha = vha->hw; 6757 struct scsi_qla_host *vp; 6758 6759 ql_dbg(ql_dbg_dpc, vha, 0x401d, 6760 "Quiescing I/O - ha=%p.\n", ha); 6761 6762 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); 6763 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 6764 atomic_set(&vha->loop_state, LOOP_DOWN); 6765 qla2x00_mark_all_devices_lost(vha); 6766 list_for_each_entry(vp, &ha->vp_list, list) 6767 qla2x00_mark_all_devices_lost(vp); 6768 } else { 6769 if (!atomic_read(&vha->loop_down_timer)) 6770 atomic_set(&vha->loop_down_timer, 6771 LOOP_DOWN_TIME); 6772 } 6773 /* Wait for pending cmds to complete */ 6774 WARN_ON_ONCE(qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) 6775 != QLA_SUCCESS); 6776 } 6777 6778 void 6779 qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) 6780 { 6781 struct qla_hw_data *ha = vha->hw; 6782 struct scsi_qla_host *vp; 6783 unsigned long flags; 6784 fc_port_t *fcport; 6785 u16 i; 6786 6787 /* For ISP82XX, driver waits for completion of the commands. 6788 * online flag should be set. 6789 */ 6790 if (!(IS_P3P_TYPE(ha))) 6791 vha->flags.online = 0; 6792 ha->flags.chip_reset_done = 0; 6793 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 6794 vha->qla_stats.total_isp_aborts++; 6795 6796 ql_log(ql_log_info, vha, 0x00af, 6797 "Performing ISP error recovery - ha=%p.\n", ha); 6798 6799 ha->flags.purge_mbox = 1; 6800 /* For ISP82XX, reset_chip is just disabling interrupts. 6801 * Driver waits for the completion of the commands. 6802 * the interrupts need to be enabled. 6803 */ 6804 if (!(IS_P3P_TYPE(ha))) 6805 ha->isp_ops->reset_chip(vha); 6806 6807 ha->link_data_rate = PORT_SPEED_UNKNOWN; 6808 SAVE_TOPO(ha); 6809 ha->flags.rida_fmt2 = 0; 6810 ha->flags.n2n_ae = 0; 6811 ha->flags.lip_ae = 0; 6812 ha->current_topology = 0; 6813 QLA_FW_STOPPED(ha); 6814 ha->flags.fw_init_done = 0; 6815 ha->chip_reset++; 6816 ha->base_qpair->chip_reset = ha->chip_reset; 6817 for (i = 0; i < ha->max_qpairs; i++) { 6818 if (ha->queue_pair_map[i]) 6819 ha->queue_pair_map[i]->chip_reset = 6820 ha->base_qpair->chip_reset; 6821 } 6822 6823 /* purge MBox commands */ 6824 if (atomic_read(&ha->num_pend_mbx_stage3)) { 6825 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 6826 complete(&ha->mbx_intr_comp); 6827 } 6828 6829 i = 0; 6830 while (atomic_read(&ha->num_pend_mbx_stage3) || 6831 atomic_read(&ha->num_pend_mbx_stage2) || 6832 atomic_read(&ha->num_pend_mbx_stage1)) { 6833 msleep(20); 6834 i++; 6835 if (i > 50) 6836 break; 6837 } 6838 ha->flags.purge_mbox = 0; 6839 6840 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 6841 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 6842 atomic_set(&vha->loop_state, LOOP_DOWN); 6843 qla2x00_mark_all_devices_lost(vha); 6844 6845 spin_lock_irqsave(&ha->vport_slock, flags); 6846 list_for_each_entry(vp, &ha->vp_list, list) { 6847 atomic_inc(&vp->vref_count); 6848 spin_unlock_irqrestore(&ha->vport_slock, flags); 6849 6850 qla2x00_mark_all_devices_lost(vp); 6851 6852 spin_lock_irqsave(&ha->vport_slock, flags); 6853 atomic_dec(&vp->vref_count); 6854 } 6855 spin_unlock_irqrestore(&ha->vport_slock, flags); 6856 } else { 6857 if (!atomic_read(&vha->loop_down_timer)) 6858 atomic_set(&vha->loop_down_timer, 6859 LOOP_DOWN_TIME); 6860 } 6861 6862 /* Clear all async request states across all VPs. */ 6863 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6864 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6865 fcport->scan_state = 0; 6866 } 6867 spin_lock_irqsave(&ha->vport_slock, flags); 6868 list_for_each_entry(vp, &ha->vp_list, list) { 6869 atomic_inc(&vp->vref_count); 6870 spin_unlock_irqrestore(&ha->vport_slock, flags); 6871 6872 list_for_each_entry(fcport, &vp->vp_fcports, list) 6873 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6874 6875 spin_lock_irqsave(&ha->vport_slock, flags); 6876 atomic_dec(&vp->vref_count); 6877 } 6878 spin_unlock_irqrestore(&ha->vport_slock, flags); 6879 6880 if (!ha->flags.eeh_busy) { 6881 /* Make sure for ISP 82XX IO DMA is complete */ 6882 if (IS_P3P_TYPE(ha)) { 6883 qla82xx_chip_reset_cleanup(vha); 6884 ql_log(ql_log_info, vha, 0x00b4, 6885 "Done chip reset cleanup.\n"); 6886 6887 /* Done waiting for pending commands. 6888 * Reset the online flag. 6889 */ 6890 vha->flags.online = 0; 6891 } 6892 6893 /* Requeue all commands in outstanding command list. */ 6894 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6895 } 6896 /* memory barrier */ 6897 wmb(); 6898 } 6899 6900 /* 6901 * qla2x00_abort_isp 6902 * Resets ISP and aborts all outstanding commands. 6903 * 6904 * Input: 6905 * ha = adapter block pointer. 6906 * 6907 * Returns: 6908 * 0 = success 6909 */ 6910 int 6911 qla2x00_abort_isp(scsi_qla_host_t *vha) 6912 { 6913 int rval; 6914 uint8_t status = 0; 6915 struct qla_hw_data *ha = vha->hw; 6916 struct scsi_qla_host *vp; 6917 struct req_que *req = ha->req_q_map[0]; 6918 unsigned long flags; 6919 6920 if (vha->flags.online) { 6921 qla2x00_abort_isp_cleanup(vha); 6922 6923 if (vha->hw->flags.port_isolated) 6924 return status; 6925 6926 if (test_and_clear_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags)) { 6927 ha->flags.chip_reset_done = 1; 6928 vha->flags.online = 1; 6929 status = 0; 6930 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 6931 return status; 6932 } 6933 6934 if (IS_QLA8031(ha)) { 6935 ql_dbg(ql_dbg_p3p, vha, 0xb05c, 6936 "Clearing fcoe driver presence.\n"); 6937 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS) 6938 ql_dbg(ql_dbg_p3p, vha, 0xb073, 6939 "Error while clearing DRV-Presence.\n"); 6940 } 6941 6942 if (unlikely(pci_channel_offline(ha->pdev) && 6943 ha->flags.pci_channel_io_perm_failure)) { 6944 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 6945 status = 0; 6946 return status; 6947 } 6948 6949 switch (vha->qlini_mode) { 6950 case QLA2XXX_INI_MODE_DISABLED: 6951 if (!qla_tgt_mode_enabled(vha)) 6952 return 0; 6953 break; 6954 case QLA2XXX_INI_MODE_DUAL: 6955 if (!qla_dual_mode_enabled(vha)) 6956 return 0; 6957 break; 6958 case QLA2XXX_INI_MODE_ENABLED: 6959 default: 6960 break; 6961 } 6962 6963 ha->isp_ops->get_flash_version(vha, req->ring); 6964 6965 ha->isp_ops->nvram_config(vha); 6966 6967 if (!qla2x00_restart_isp(vha)) { 6968 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6969 6970 if (!atomic_read(&vha->loop_down_timer)) { 6971 /* 6972 * Issue marker command only when we are going 6973 * to start the I/O . 6974 */ 6975 vha->marker_needed = 1; 6976 } 6977 6978 vha->flags.online = 1; 6979 6980 ha->isp_ops->enable_intrs(ha); 6981 6982 ha->isp_abort_cnt = 0; 6983 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 6984 6985 if (IS_QLA81XX(ha) || IS_QLA8031(ha)) 6986 qla2x00_get_fw_version(vha); 6987 if (ha->fce) { 6988 ha->flags.fce_enabled = 1; 6989 memset(ha->fce, 0, 6990 fce_calc_size(ha->fce_bufs)); 6991 rval = qla2x00_enable_fce_trace(vha, 6992 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 6993 &ha->fce_bufs); 6994 if (rval) { 6995 ql_log(ql_log_warn, vha, 0x8033, 6996 "Unable to reinitialize FCE " 6997 "(%d).\n", rval); 6998 ha->flags.fce_enabled = 0; 6999 } 7000 } 7001 7002 if (ha->eft) { 7003 memset(ha->eft, 0, EFT_SIZE); 7004 rval = qla2x00_enable_eft_trace(vha, 7005 ha->eft_dma, EFT_NUM_BUFFERS); 7006 if (rval) { 7007 ql_log(ql_log_warn, vha, 0x8034, 7008 "Unable to reinitialize EFT " 7009 "(%d).\n", rval); 7010 } 7011 } 7012 } else { /* failed the ISP abort */ 7013 vha->flags.online = 1; 7014 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 7015 if (ha->isp_abort_cnt == 0) { 7016 ql_log(ql_log_fatal, vha, 0x8035, 7017 "ISP error recover failed - " 7018 "board disabled.\n"); 7019 /* 7020 * The next call disables the board 7021 * completely. 7022 */ 7023 qla2x00_abort_isp_cleanup(vha); 7024 vha->flags.online = 0; 7025 clear_bit(ISP_ABORT_RETRY, 7026 &vha->dpc_flags); 7027 status = 0; 7028 } else { /* schedule another ISP abort */ 7029 ha->isp_abort_cnt--; 7030 ql_dbg(ql_dbg_taskm, vha, 0x8020, 7031 "ISP abort - retry remaining %d.\n", 7032 ha->isp_abort_cnt); 7033 status = 1; 7034 } 7035 } else { 7036 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 7037 ql_dbg(ql_dbg_taskm, vha, 0x8021, 7038 "ISP error recovery - retrying (%d) " 7039 "more times.\n", ha->isp_abort_cnt); 7040 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7041 status = 1; 7042 } 7043 } 7044 7045 } 7046 7047 if (vha->hw->flags.port_isolated) { 7048 qla2x00_abort_isp_cleanup(vha); 7049 return status; 7050 } 7051 7052 if (!status) { 7053 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__); 7054 qla2x00_configure_hba(vha); 7055 spin_lock_irqsave(&ha->vport_slock, flags); 7056 list_for_each_entry(vp, &ha->vp_list, list) { 7057 if (vp->vp_idx) { 7058 atomic_inc(&vp->vref_count); 7059 spin_unlock_irqrestore(&ha->vport_slock, flags); 7060 7061 qla2x00_vp_abort_isp(vp); 7062 7063 spin_lock_irqsave(&ha->vport_slock, flags); 7064 atomic_dec(&vp->vref_count); 7065 } 7066 } 7067 spin_unlock_irqrestore(&ha->vport_slock, flags); 7068 7069 if (IS_QLA8031(ha)) { 7070 ql_dbg(ql_dbg_p3p, vha, 0xb05d, 7071 "Setting back fcoe driver presence.\n"); 7072 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS) 7073 ql_dbg(ql_dbg_p3p, vha, 0xb074, 7074 "Error while setting DRV-Presence.\n"); 7075 } 7076 } else { 7077 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n", 7078 __func__); 7079 } 7080 7081 return(status); 7082 } 7083 7084 /* 7085 * qla2x00_restart_isp 7086 * restarts the ISP after a reset 7087 * 7088 * Input: 7089 * ha = adapter block pointer. 7090 * 7091 * Returns: 7092 * 0 = success 7093 */ 7094 static int 7095 qla2x00_restart_isp(scsi_qla_host_t *vha) 7096 { 7097 int status; 7098 struct qla_hw_data *ha = vha->hw; 7099 7100 /* If firmware needs to be loaded */ 7101 if (qla2x00_isp_firmware(vha)) { 7102 vha->flags.online = 0; 7103 status = ha->isp_ops->chip_diag(vha); 7104 if (status) 7105 return status; 7106 status = qla2x00_setup_chip(vha); 7107 if (status) 7108 return status; 7109 } 7110 7111 status = qla2x00_init_rings(vha); 7112 if (status) 7113 return status; 7114 7115 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7116 ha->flags.chip_reset_done = 1; 7117 7118 /* Initialize the queues in use */ 7119 qla25xx_init_queues(ha); 7120 7121 status = qla2x00_fw_ready(vha); 7122 if (status) { 7123 /* if no cable then assume it's good */ 7124 return vha->device_flags & DFLG_NO_CABLE ? 0 : status; 7125 } 7126 7127 /* Issue a marker after FW becomes ready. */ 7128 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 7129 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 7130 7131 return 0; 7132 } 7133 7134 static int 7135 qla25xx_init_queues(struct qla_hw_data *ha) 7136 { 7137 struct rsp_que *rsp = NULL; 7138 struct req_que *req = NULL; 7139 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7140 int ret = -1; 7141 int i; 7142 7143 for (i = 1; i < ha->max_rsp_queues; i++) { 7144 rsp = ha->rsp_q_map[i]; 7145 if (rsp && test_bit(i, ha->rsp_qid_map)) { 7146 rsp->options &= ~BIT_0; 7147 ret = qla25xx_init_rsp_que(base_vha, rsp); 7148 if (ret != QLA_SUCCESS) 7149 ql_dbg(ql_dbg_init, base_vha, 0x00ff, 7150 "%s Rsp que: %d init failed.\n", 7151 __func__, rsp->id); 7152 else 7153 ql_dbg(ql_dbg_init, base_vha, 0x0100, 7154 "%s Rsp que: %d inited.\n", 7155 __func__, rsp->id); 7156 } 7157 } 7158 for (i = 1; i < ha->max_req_queues; i++) { 7159 req = ha->req_q_map[i]; 7160 if (req && test_bit(i, ha->req_qid_map)) { 7161 /* Clear outstanding commands array. */ 7162 req->options &= ~BIT_0; 7163 ret = qla25xx_init_req_que(base_vha, req); 7164 if (ret != QLA_SUCCESS) 7165 ql_dbg(ql_dbg_init, base_vha, 0x0101, 7166 "%s Req que: %d init failed.\n", 7167 __func__, req->id); 7168 else 7169 ql_dbg(ql_dbg_init, base_vha, 0x0102, 7170 "%s Req que: %d inited.\n", 7171 __func__, req->id); 7172 } 7173 } 7174 return ret; 7175 } 7176 7177 /* 7178 * qla2x00_reset_adapter 7179 * Reset adapter. 7180 * 7181 * Input: 7182 * ha = adapter block pointer. 7183 */ 7184 int 7185 qla2x00_reset_adapter(scsi_qla_host_t *vha) 7186 { 7187 unsigned long flags = 0; 7188 struct qla_hw_data *ha = vha->hw; 7189 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7190 7191 vha->flags.online = 0; 7192 ha->isp_ops->disable_intrs(ha); 7193 7194 spin_lock_irqsave(&ha->hardware_lock, flags); 7195 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 7196 rd_reg_word(®->hccr); /* PCI Posting. */ 7197 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 7198 rd_reg_word(®->hccr); /* PCI Posting. */ 7199 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7200 7201 return QLA_SUCCESS; 7202 } 7203 7204 int 7205 qla24xx_reset_adapter(scsi_qla_host_t *vha) 7206 { 7207 unsigned long flags = 0; 7208 struct qla_hw_data *ha = vha->hw; 7209 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 7210 7211 if (IS_P3P_TYPE(ha)) 7212 return QLA_SUCCESS; 7213 7214 vha->flags.online = 0; 7215 ha->isp_ops->disable_intrs(ha); 7216 7217 spin_lock_irqsave(&ha->hardware_lock, flags); 7218 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET); 7219 rd_reg_dword(®->hccr); 7220 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE); 7221 rd_reg_dword(®->hccr); 7222 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7223 7224 if (IS_NOPOLLING_TYPE(ha)) 7225 ha->isp_ops->enable_intrs(ha); 7226 7227 return QLA_SUCCESS; 7228 } 7229 7230 /* On sparc systems, obtain port and node WWN from firmware 7231 * properties. 7232 */ 7233 static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, 7234 struct nvram_24xx *nv) 7235 { 7236 #ifdef CONFIG_SPARC 7237 struct qla_hw_data *ha = vha->hw; 7238 struct pci_dev *pdev = ha->pdev; 7239 struct device_node *dp = pci_device_to_OF_node(pdev); 7240 const u8 *val; 7241 int len; 7242 7243 val = of_get_property(dp, "port-wwn", &len); 7244 if (val && len >= WWN_SIZE) 7245 memcpy(nv->port_name, val, WWN_SIZE); 7246 7247 val = of_get_property(dp, "node-wwn", &len); 7248 if (val && len >= WWN_SIZE) 7249 memcpy(nv->node_name, val, WWN_SIZE); 7250 #endif 7251 } 7252 7253 int 7254 qla24xx_nvram_config(scsi_qla_host_t *vha) 7255 { 7256 int rval; 7257 struct init_cb_24xx *icb; 7258 struct nvram_24xx *nv; 7259 __le32 *dptr; 7260 uint8_t *dptr1, *dptr2; 7261 uint32_t chksum; 7262 uint16_t cnt; 7263 struct qla_hw_data *ha = vha->hw; 7264 7265 rval = QLA_SUCCESS; 7266 icb = (struct init_cb_24xx *)ha->init_cb; 7267 nv = ha->nvram; 7268 7269 /* Determine NVRAM starting address. */ 7270 if (ha->port_no == 0) { 7271 ha->nvram_base = FA_NVRAM_FUNC0_ADDR; 7272 ha->vpd_base = FA_NVRAM_VPD0_ADDR; 7273 } else { 7274 ha->nvram_base = FA_NVRAM_FUNC1_ADDR; 7275 ha->vpd_base = FA_NVRAM_VPD1_ADDR; 7276 } 7277 7278 ha->nvram_size = sizeof(*nv); 7279 ha->vpd_size = FA_NVRAM_VPD_SIZE; 7280 7281 /* Get VPD data into cache */ 7282 ha->vpd = ha->nvram + VPD_OFFSET; 7283 ha->isp_ops->read_nvram(vha, ha->vpd, 7284 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4); 7285 7286 /* Get NVRAM data into cache and calculate checksum. */ 7287 dptr = (__force __le32 *)nv; 7288 ha->isp_ops->read_nvram(vha, dptr, ha->nvram_base, ha->nvram_size); 7289 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 7290 chksum += le32_to_cpu(*dptr); 7291 7292 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a, 7293 "Contents of NVRAM\n"); 7294 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d, 7295 nv, ha->nvram_size); 7296 7297 /* Bad NVRAM data, set defaults parameters. */ 7298 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 7299 le16_to_cpu(nv->nvram_version) < ICB_VERSION) { 7300 /* Reset NVRAM data. */ 7301 ql_log(ql_log_warn, vha, 0x006b, 7302 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n", 7303 chksum, nv->id, nv->nvram_version); 7304 ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, sizeof(*nv)); 7305 ql_log(ql_log_warn, vha, 0x006c, 7306 "Falling back to functioning (yet invalid -- WWPN) " 7307 "defaults.\n"); 7308 7309 /* 7310 * Set default initialization control block. 7311 */ 7312 memset(nv, 0, ha->nvram_size); 7313 nv->nvram_version = cpu_to_le16(ICB_VERSION); 7314 nv->version = cpu_to_le16(ICB_VERSION); 7315 nv->frame_payload_size = cpu_to_le16(2048); 7316 nv->execution_throttle = cpu_to_le16(0xFFFF); 7317 nv->exchange_count = cpu_to_le16(0); 7318 nv->hard_address = cpu_to_le16(124); 7319 nv->port_name[0] = 0x21; 7320 nv->port_name[1] = 0x00 + ha->port_no + 1; 7321 nv->port_name[2] = 0x00; 7322 nv->port_name[3] = 0xe0; 7323 nv->port_name[4] = 0x8b; 7324 nv->port_name[5] = 0x1c; 7325 nv->port_name[6] = 0x55; 7326 nv->port_name[7] = 0x86; 7327 nv->node_name[0] = 0x20; 7328 nv->node_name[1] = 0x00; 7329 nv->node_name[2] = 0x00; 7330 nv->node_name[3] = 0xe0; 7331 nv->node_name[4] = 0x8b; 7332 nv->node_name[5] = 0x1c; 7333 nv->node_name[6] = 0x55; 7334 nv->node_name[7] = 0x86; 7335 qla24xx_nvram_wwn_from_ofw(vha, nv); 7336 nv->login_retry_count = cpu_to_le16(8); 7337 nv->interrupt_delay_timer = cpu_to_le16(0); 7338 nv->login_timeout = cpu_to_le16(0); 7339 nv->firmware_options_1 = 7340 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 7341 nv->firmware_options_2 = cpu_to_le32(2 << 4); 7342 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 7343 nv->firmware_options_3 = cpu_to_le32(2 << 13); 7344 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 7345 nv->efi_parameters = cpu_to_le32(0); 7346 nv->reset_delay = 5; 7347 nv->max_luns_per_target = cpu_to_le16(128); 7348 nv->port_down_retry_count = cpu_to_le16(30); 7349 nv->link_down_timeout = cpu_to_le16(30); 7350 7351 rval = 1; 7352 } 7353 7354 if (qla_tgt_mode_enabled(vha)) { 7355 /* Don't enable full login after initial LIP */ 7356 nv->firmware_options_1 &= cpu_to_le32(~BIT_13); 7357 /* Don't enable LIP full login for initiator */ 7358 nv->host_p &= cpu_to_le32(~BIT_10); 7359 } 7360 7361 qlt_24xx_config_nvram_stage1(vha, nv); 7362 7363 /* Reset Initialization control block */ 7364 memset(icb, 0, ha->init_cb_size); 7365 7366 /* Copy 1st segment. */ 7367 dptr1 = (uint8_t *)icb; 7368 dptr2 = (uint8_t *)&nv->version; 7369 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 7370 while (cnt--) 7371 *dptr1++ = *dptr2++; 7372 7373 icb->login_retry_count = nv->login_retry_count; 7374 icb->link_down_on_nos = nv->link_down_on_nos; 7375 7376 /* Copy 2nd segment. */ 7377 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 7378 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 7379 cnt = (uint8_t *)&icb->reserved_3 - 7380 (uint8_t *)&icb->interrupt_delay_timer; 7381 while (cnt--) 7382 *dptr1++ = *dptr2++; 7383 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 7384 /* 7385 * Setup driver NVRAM options. 7386 */ 7387 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 7388 "QLA2462"); 7389 7390 qlt_24xx_config_nvram_stage2(vha, icb); 7391 7392 if (nv->host_p & cpu_to_le32(BIT_15)) { 7393 /* Use alternate WWN? */ 7394 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 7395 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 7396 } 7397 7398 /* Prepare nodename */ 7399 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 7400 /* 7401 * Firmware will apply the following mask if the nodename was 7402 * not provided. 7403 */ 7404 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 7405 icb->node_name[0] &= 0xF0; 7406 } 7407 7408 /* Set host adapter parameters. */ 7409 ha->flags.disable_risc_code_load = 0; 7410 ha->flags.enable_lip_reset = 0; 7411 ha->flags.enable_lip_full_login = 7412 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0; 7413 ha->flags.enable_target_reset = 7414 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0; 7415 ha->flags.enable_led_scheme = 0; 7416 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0; 7417 7418 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 7419 (BIT_6 | BIT_5 | BIT_4)) >> 4; 7420 7421 memcpy(ha->fw_seriallink_options24, nv->seriallink_options, 7422 sizeof(ha->fw_seriallink_options24)); 7423 7424 /* save HBA serial number */ 7425 ha->serial0 = icb->port_name[5]; 7426 ha->serial1 = icb->port_name[6]; 7427 ha->serial2 = icb->port_name[7]; 7428 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 7429 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 7430 7431 icb->execution_throttle = cpu_to_le16(0xFFFF); 7432 7433 ha->retry_count = le16_to_cpu(nv->login_retry_count); 7434 7435 /* Set minimum login_timeout to 4 seconds. */ 7436 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 7437 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 7438 if (le16_to_cpu(nv->login_timeout) < 4) 7439 nv->login_timeout = cpu_to_le16(4); 7440 ha->login_timeout = le16_to_cpu(nv->login_timeout); 7441 7442 /* Set minimum RATOV to 100 tenths of a second. */ 7443 ha->r_a_tov = 100; 7444 7445 ha->loop_reset_delay = nv->reset_delay; 7446 7447 /* Link Down Timeout = 0: 7448 * 7449 * When Port Down timer expires we will start returning 7450 * I/O's to OS with "DID_NO_CONNECT". 7451 * 7452 * Link Down Timeout != 0: 7453 * 7454 * The driver waits for the link to come up after link down 7455 * before returning I/Os to OS with "DID_NO_CONNECT". 7456 */ 7457 if (le16_to_cpu(nv->link_down_timeout) == 0) { 7458 ha->loop_down_abort_time = 7459 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 7460 } else { 7461 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 7462 ha->loop_down_abort_time = 7463 (LOOP_DOWN_TIME - ha->link_down_timeout); 7464 } 7465 7466 /* Need enough time to try and get the port back. */ 7467 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 7468 if (qlport_down_retry) 7469 ha->port_down_retry_count = qlport_down_retry; 7470 7471 /* Set login_retry_count */ 7472 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 7473 if (ha->port_down_retry_count == 7474 le16_to_cpu(nv->port_down_retry_count) && 7475 ha->port_down_retry_count > 3) 7476 ha->login_retry_count = ha->port_down_retry_count; 7477 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 7478 ha->login_retry_count = ha->port_down_retry_count; 7479 if (ql2xloginretrycount) 7480 ha->login_retry_count = ql2xloginretrycount; 7481 7482 /* N2N: driver will initiate Login instead of FW */ 7483 icb->firmware_options_3 |= cpu_to_le32(BIT_8); 7484 7485 /* Enable ZIO. */ 7486 if (!vha->flags.init_done) { 7487 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 7488 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 7489 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 7490 le16_to_cpu(icb->interrupt_delay_timer) : 2; 7491 } 7492 icb->firmware_options_2 &= cpu_to_le32( 7493 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 7494 if (ha->zio_mode != QLA_ZIO_DISABLED) { 7495 ha->zio_mode = QLA_ZIO_MODE_6; 7496 7497 ql_log(ql_log_info, vha, 0x006f, 7498 "ZIO mode %d enabled; timer delay (%d us).\n", 7499 ha->zio_mode, ha->zio_timer * 100); 7500 7501 icb->firmware_options_2 |= cpu_to_le32( 7502 (uint32_t)ha->zio_mode); 7503 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 7504 } 7505 7506 if (rval) { 7507 ql_log(ql_log_warn, vha, 0x0070, 7508 "NVRAM configuration failed.\n"); 7509 } 7510 return (rval); 7511 } 7512 7513 static void 7514 qla27xx_print_image(struct scsi_qla_host *vha, char *name, 7515 struct qla27xx_image_status *image_status) 7516 { 7517 ql_dbg(ql_dbg_init, vha, 0x018b, 7518 "%s %s: mask=%#02x gen=%#04x ver=%u.%u map=%#01x sum=%#08x sig=%#08x\n", 7519 name, "status", 7520 image_status->image_status_mask, 7521 le16_to_cpu(image_status->generation), 7522 image_status->ver_major, 7523 image_status->ver_minor, 7524 image_status->bitmap, 7525 le32_to_cpu(image_status->checksum), 7526 le32_to_cpu(image_status->signature)); 7527 } 7528 7529 static bool 7530 qla28xx_check_aux_image_status_signature( 7531 struct qla27xx_image_status *image_status) 7532 { 7533 ulong signature = le32_to_cpu(image_status->signature); 7534 7535 return signature != QLA28XX_AUX_IMG_STATUS_SIGN; 7536 } 7537 7538 static bool 7539 qla27xx_check_image_status_signature(struct qla27xx_image_status *image_status) 7540 { 7541 ulong signature = le32_to_cpu(image_status->signature); 7542 7543 return 7544 signature != QLA27XX_IMG_STATUS_SIGN && 7545 signature != QLA28XX_IMG_STATUS_SIGN; 7546 } 7547 7548 static ulong 7549 qla27xx_image_status_checksum(struct qla27xx_image_status *image_status) 7550 { 7551 __le32 *p = (__force __le32 *)image_status; 7552 uint n = sizeof(*image_status) / sizeof(*p); 7553 uint32_t sum = 0; 7554 7555 for ( ; n--; p++) 7556 sum += le32_to_cpup(p); 7557 7558 return sum; 7559 } 7560 7561 static inline uint 7562 qla28xx_component_bitmask(struct qla27xx_image_status *aux, uint bitmask) 7563 { 7564 return aux->bitmap & bitmask ? 7565 QLA27XX_SECONDARY_IMAGE : QLA27XX_PRIMARY_IMAGE; 7566 } 7567 7568 static void 7569 qla28xx_component_status( 7570 struct active_regions *active_regions, struct qla27xx_image_status *aux) 7571 { 7572 active_regions->aux.board_config = 7573 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_BOARD_CONFIG); 7574 7575 active_regions->aux.vpd_nvram = 7576 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_VPD_NVRAM); 7577 7578 active_regions->aux.npiv_config_0_1 = 7579 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_0_1); 7580 7581 active_regions->aux.npiv_config_2_3 = 7582 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_2_3); 7583 } 7584 7585 static int 7586 qla27xx_compare_image_generation( 7587 struct qla27xx_image_status *pri_image_status, 7588 struct qla27xx_image_status *sec_image_status) 7589 { 7590 /* calculate generation delta as uint16 (this accounts for wrap) */ 7591 int16_t delta = 7592 le16_to_cpu(pri_image_status->generation) - 7593 le16_to_cpu(sec_image_status->generation); 7594 7595 ql_dbg(ql_dbg_init, NULL, 0x0180, "generation delta = %d\n", delta); 7596 7597 return delta; 7598 } 7599 7600 void 7601 qla28xx_get_aux_images( 7602 struct scsi_qla_host *vha, struct active_regions *active_regions) 7603 { 7604 struct qla_hw_data *ha = vha->hw; 7605 struct qla27xx_image_status pri_aux_image_status, sec_aux_image_status; 7606 bool valid_pri_image = false, valid_sec_image = false; 7607 bool active_pri_image = false, active_sec_image = false; 7608 7609 if (!ha->flt_region_aux_img_status_pri) { 7610 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary aux image not addressed\n"); 7611 goto check_sec_image; 7612 } 7613 7614 qla24xx_read_flash_data(vha, (uint32_t *)&pri_aux_image_status, 7615 ha->flt_region_aux_img_status_pri, 7616 sizeof(pri_aux_image_status) >> 2); 7617 qla27xx_print_image(vha, "Primary aux image", &pri_aux_image_status); 7618 7619 if (qla28xx_check_aux_image_status_signature(&pri_aux_image_status)) { 7620 ql_dbg(ql_dbg_init, vha, 0x018b, 7621 "Primary aux image signature (%#x) not valid\n", 7622 le32_to_cpu(pri_aux_image_status.signature)); 7623 goto check_sec_image; 7624 } 7625 7626 if (qla27xx_image_status_checksum(&pri_aux_image_status)) { 7627 ql_dbg(ql_dbg_init, vha, 0x018c, 7628 "Primary aux image checksum failed\n"); 7629 goto check_sec_image; 7630 } 7631 7632 valid_pri_image = true; 7633 7634 if (pri_aux_image_status.image_status_mask & 1) { 7635 ql_dbg(ql_dbg_init, vha, 0x018d, 7636 "Primary aux image is active\n"); 7637 active_pri_image = true; 7638 } 7639 7640 check_sec_image: 7641 if (!ha->flt_region_aux_img_status_sec) { 7642 ql_dbg(ql_dbg_init, vha, 0x018a, 7643 "Secondary aux image not addressed\n"); 7644 goto check_valid_image; 7645 } 7646 7647 qla24xx_read_flash_data(vha, (uint32_t *)&sec_aux_image_status, 7648 ha->flt_region_aux_img_status_sec, 7649 sizeof(sec_aux_image_status) >> 2); 7650 qla27xx_print_image(vha, "Secondary aux image", &sec_aux_image_status); 7651 7652 if (qla28xx_check_aux_image_status_signature(&sec_aux_image_status)) { 7653 ql_dbg(ql_dbg_init, vha, 0x018b, 7654 "Secondary aux image signature (%#x) not valid\n", 7655 le32_to_cpu(sec_aux_image_status.signature)); 7656 goto check_valid_image; 7657 } 7658 7659 if (qla27xx_image_status_checksum(&sec_aux_image_status)) { 7660 ql_dbg(ql_dbg_init, vha, 0x018c, 7661 "Secondary aux image checksum failed\n"); 7662 goto check_valid_image; 7663 } 7664 7665 valid_sec_image = true; 7666 7667 if (sec_aux_image_status.image_status_mask & 1) { 7668 ql_dbg(ql_dbg_init, vha, 0x018d, 7669 "Secondary aux image is active\n"); 7670 active_sec_image = true; 7671 } 7672 7673 check_valid_image: 7674 if (valid_pri_image && active_pri_image && 7675 valid_sec_image && active_sec_image) { 7676 if (qla27xx_compare_image_generation(&pri_aux_image_status, 7677 &sec_aux_image_status) >= 0) { 7678 qla28xx_component_status(active_regions, 7679 &pri_aux_image_status); 7680 } else { 7681 qla28xx_component_status(active_regions, 7682 &sec_aux_image_status); 7683 } 7684 } else if (valid_pri_image && active_pri_image) { 7685 qla28xx_component_status(active_regions, &pri_aux_image_status); 7686 } else if (valid_sec_image && active_sec_image) { 7687 qla28xx_component_status(active_regions, &sec_aux_image_status); 7688 } 7689 7690 ql_dbg(ql_dbg_init, vha, 0x018f, 7691 "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u\n", 7692 active_regions->aux.board_config, 7693 active_regions->aux.vpd_nvram, 7694 active_regions->aux.npiv_config_0_1, 7695 active_regions->aux.npiv_config_2_3); 7696 } 7697 7698 void 7699 qla27xx_get_active_image(struct scsi_qla_host *vha, 7700 struct active_regions *active_regions) 7701 { 7702 struct qla_hw_data *ha = vha->hw; 7703 struct qla27xx_image_status pri_image_status, sec_image_status; 7704 bool valid_pri_image = false, valid_sec_image = false; 7705 bool active_pri_image = false, active_sec_image = false; 7706 7707 if (!ha->flt_region_img_status_pri) { 7708 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary image not addressed\n"); 7709 goto check_sec_image; 7710 } 7711 7712 if (qla24xx_read_flash_data(vha, (uint32_t *)&pri_image_status, 7713 ha->flt_region_img_status_pri, sizeof(pri_image_status) >> 2) != 7714 QLA_SUCCESS) { 7715 WARN_ON_ONCE(true); 7716 goto check_sec_image; 7717 } 7718 qla27xx_print_image(vha, "Primary image", &pri_image_status); 7719 7720 if (qla27xx_check_image_status_signature(&pri_image_status)) { 7721 ql_dbg(ql_dbg_init, vha, 0x018b, 7722 "Primary image signature (%#x) not valid\n", 7723 le32_to_cpu(pri_image_status.signature)); 7724 goto check_sec_image; 7725 } 7726 7727 if (qla27xx_image_status_checksum(&pri_image_status)) { 7728 ql_dbg(ql_dbg_init, vha, 0x018c, 7729 "Primary image checksum failed\n"); 7730 goto check_sec_image; 7731 } 7732 7733 valid_pri_image = true; 7734 7735 if (pri_image_status.image_status_mask & 1) { 7736 ql_dbg(ql_dbg_init, vha, 0x018d, 7737 "Primary image is active\n"); 7738 active_pri_image = true; 7739 } 7740 7741 check_sec_image: 7742 if (!ha->flt_region_img_status_sec) { 7743 ql_dbg(ql_dbg_init, vha, 0x018a, "Secondary image not addressed\n"); 7744 goto check_valid_image; 7745 } 7746 7747 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status), 7748 ha->flt_region_img_status_sec, sizeof(sec_image_status) >> 2); 7749 qla27xx_print_image(vha, "Secondary image", &sec_image_status); 7750 7751 if (qla27xx_check_image_status_signature(&sec_image_status)) { 7752 ql_dbg(ql_dbg_init, vha, 0x018b, 7753 "Secondary image signature (%#x) not valid\n", 7754 le32_to_cpu(sec_image_status.signature)); 7755 goto check_valid_image; 7756 } 7757 7758 if (qla27xx_image_status_checksum(&sec_image_status)) { 7759 ql_dbg(ql_dbg_init, vha, 0x018c, 7760 "Secondary image checksum failed\n"); 7761 goto check_valid_image; 7762 } 7763 7764 valid_sec_image = true; 7765 7766 if (sec_image_status.image_status_mask & 1) { 7767 ql_dbg(ql_dbg_init, vha, 0x018d, 7768 "Secondary image is active\n"); 7769 active_sec_image = true; 7770 } 7771 7772 check_valid_image: 7773 if (valid_pri_image && active_pri_image) 7774 active_regions->global = QLA27XX_PRIMARY_IMAGE; 7775 7776 if (valid_sec_image && active_sec_image) { 7777 if (!active_regions->global || 7778 qla27xx_compare_image_generation( 7779 &pri_image_status, &sec_image_status) < 0) { 7780 active_regions->global = QLA27XX_SECONDARY_IMAGE; 7781 } 7782 } 7783 7784 ql_dbg(ql_dbg_init, vha, 0x018f, "active image %s (%u)\n", 7785 active_regions->global == QLA27XX_DEFAULT_IMAGE ? 7786 "default (boot/fw)" : 7787 active_regions->global == QLA27XX_PRIMARY_IMAGE ? 7788 "primary" : 7789 active_regions->global == QLA27XX_SECONDARY_IMAGE ? 7790 "secondary" : "invalid", 7791 active_regions->global); 7792 } 7793 7794 bool qla24xx_risc_firmware_invalid(uint32_t *dword) 7795 { 7796 return 7797 !(dword[4] | dword[5] | dword[6] | dword[7]) || 7798 !(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]); 7799 } 7800 7801 static int 7802 qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, 7803 uint32_t faddr) 7804 { 7805 int rval; 7806 uint templates, segments, fragment; 7807 ulong i; 7808 uint j; 7809 ulong dlen; 7810 uint32_t *dcode; 7811 uint32_t risc_addr, risc_size, risc_attr = 0; 7812 struct qla_hw_data *ha = vha->hw; 7813 struct req_que *req = ha->req_q_map[0]; 7814 struct fwdt *fwdt = ha->fwdt; 7815 7816 ql_dbg(ql_dbg_init, vha, 0x008b, 7817 "FW: Loading firmware from flash (%x).\n", faddr); 7818 7819 dcode = (uint32_t *)req->ring; 7820 qla24xx_read_flash_data(vha, dcode, faddr, 8); 7821 if (qla24xx_risc_firmware_invalid(dcode)) { 7822 ql_log(ql_log_fatal, vha, 0x008c, 7823 "Unable to verify the integrity of flash firmware " 7824 "image.\n"); 7825 ql_log(ql_log_fatal, vha, 0x008d, 7826 "Firmware data: %08x %08x %08x %08x.\n", 7827 dcode[0], dcode[1], dcode[2], dcode[3]); 7828 7829 return QLA_FUNCTION_FAILED; 7830 } 7831 7832 dcode = (uint32_t *)req->ring; 7833 *srisc_addr = 0; 7834 segments = FA_RISC_CODE_SEGMENTS; 7835 for (j = 0; j < segments; j++) { 7836 ql_dbg(ql_dbg_init, vha, 0x008d, 7837 "-> Loading segment %u...\n", j); 7838 qla24xx_read_flash_data(vha, dcode, faddr, 10); 7839 risc_addr = be32_to_cpu((__force __be32)dcode[2]); 7840 risc_size = be32_to_cpu((__force __be32)dcode[3]); 7841 if (!*srisc_addr) { 7842 *srisc_addr = risc_addr; 7843 risc_attr = be32_to_cpu((__force __be32)dcode[9]); 7844 } 7845 7846 dlen = ha->fw_transfer_size >> 2; 7847 for (fragment = 0; risc_size; fragment++) { 7848 if (dlen > risc_size) 7849 dlen = risc_size; 7850 7851 ql_dbg(ql_dbg_init, vha, 0x008e, 7852 "-> Loading fragment %u: %#x <- %#x (%#lx dwords)...\n", 7853 fragment, risc_addr, faddr, dlen); 7854 qla24xx_read_flash_data(vha, dcode, faddr, dlen); 7855 for (i = 0; i < dlen; i++) 7856 dcode[i] = swab32(dcode[i]); 7857 7858 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen); 7859 if (rval) { 7860 ql_log(ql_log_fatal, vha, 0x008f, 7861 "-> Failed load firmware fragment %u.\n", 7862 fragment); 7863 return QLA_FUNCTION_FAILED; 7864 } 7865 7866 faddr += dlen; 7867 risc_addr += dlen; 7868 risc_size -= dlen; 7869 } 7870 } 7871 7872 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 7873 return QLA_SUCCESS; 7874 7875 templates = (risc_attr & BIT_9) ? 2 : 1; 7876 ql_dbg(ql_dbg_init, vha, 0x0160, "-> templates = %u\n", templates); 7877 for (j = 0; j < templates; j++, fwdt++) { 7878 vfree(fwdt->template); 7879 fwdt->template = NULL; 7880 fwdt->length = 0; 7881 7882 dcode = (uint32_t *)req->ring; 7883 qla24xx_read_flash_data(vha, dcode, faddr, 7); 7884 risc_size = be32_to_cpu((__force __be32)dcode[2]); 7885 ql_dbg(ql_dbg_init, vha, 0x0161, 7886 "-> fwdt%u template array at %#x (%#x dwords)\n", 7887 j, faddr, risc_size); 7888 if (!risc_size || !~risc_size) { 7889 ql_dbg(ql_dbg_init, vha, 0x0162, 7890 "-> fwdt%u failed to read array\n", j); 7891 goto failed; 7892 } 7893 7894 /* skip header and ignore checksum */ 7895 faddr += 7; 7896 risc_size -= 8; 7897 7898 ql_dbg(ql_dbg_init, vha, 0x0163, 7899 "-> fwdt%u template allocate template %#x words...\n", 7900 j, risc_size); 7901 fwdt->template = vmalloc(risc_size * sizeof(*dcode)); 7902 if (!fwdt->template) { 7903 ql_log(ql_log_warn, vha, 0x0164, 7904 "-> fwdt%u failed allocate template.\n", j); 7905 goto failed; 7906 } 7907 7908 dcode = fwdt->template; 7909 qla24xx_read_flash_data(vha, dcode, faddr, risc_size); 7910 7911 if (!qla27xx_fwdt_template_valid(dcode)) { 7912 ql_log(ql_log_warn, vha, 0x0165, 7913 "-> fwdt%u failed template validate\n", j); 7914 goto failed; 7915 } 7916 7917 dlen = qla27xx_fwdt_template_size(dcode); 7918 ql_dbg(ql_dbg_init, vha, 0x0166, 7919 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 7920 j, dlen, dlen / sizeof(*dcode)); 7921 if (dlen > risc_size * sizeof(*dcode)) { 7922 ql_log(ql_log_warn, vha, 0x0167, 7923 "-> fwdt%u template exceeds array (%-lu bytes)\n", 7924 j, dlen - risc_size * sizeof(*dcode)); 7925 goto failed; 7926 } 7927 7928 fwdt->length = dlen; 7929 ql_dbg(ql_dbg_init, vha, 0x0168, 7930 "-> fwdt%u loaded template ok\n", j); 7931 7932 faddr += risc_size + 1; 7933 } 7934 7935 return QLA_SUCCESS; 7936 7937 failed: 7938 vfree(fwdt->template); 7939 fwdt->template = NULL; 7940 fwdt->length = 0; 7941 7942 return QLA_SUCCESS; 7943 } 7944 7945 #define QLA_FW_URL "http://ldriver.qlogic.com/firmware/" 7946 7947 int 7948 qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 7949 { 7950 int rval; 7951 int i, fragment; 7952 uint16_t *wcode; 7953 __be16 *fwcode; 7954 uint32_t risc_addr, risc_size, fwclen, wlen, *seg; 7955 struct fw_blob *blob; 7956 struct qla_hw_data *ha = vha->hw; 7957 struct req_que *req = ha->req_q_map[0]; 7958 7959 /* Load firmware blob. */ 7960 blob = qla2x00_request_firmware(vha); 7961 if (!blob) { 7962 ql_log(ql_log_info, vha, 0x0083, 7963 "Firmware image unavailable.\n"); 7964 ql_log(ql_log_info, vha, 0x0084, 7965 "Firmware images can be retrieved from: "QLA_FW_URL ".\n"); 7966 return QLA_FUNCTION_FAILED; 7967 } 7968 7969 rval = QLA_SUCCESS; 7970 7971 wcode = (uint16_t *)req->ring; 7972 *srisc_addr = 0; 7973 fwcode = (__force __be16 *)blob->fw->data; 7974 fwclen = 0; 7975 7976 /* Validate firmware image by checking version. */ 7977 if (blob->fw->size < 8 * sizeof(uint16_t)) { 7978 ql_log(ql_log_fatal, vha, 0x0085, 7979 "Unable to verify integrity of firmware image (%zd).\n", 7980 blob->fw->size); 7981 goto fail_fw_integrity; 7982 } 7983 for (i = 0; i < 4; i++) 7984 wcode[i] = be16_to_cpu(fwcode[i + 4]); 7985 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff && 7986 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 && 7987 wcode[2] == 0 && wcode[3] == 0)) { 7988 ql_log(ql_log_fatal, vha, 0x0086, 7989 "Unable to verify integrity of firmware image.\n"); 7990 ql_log(ql_log_fatal, vha, 0x0087, 7991 "Firmware data: %04x %04x %04x %04x.\n", 7992 wcode[0], wcode[1], wcode[2], wcode[3]); 7993 goto fail_fw_integrity; 7994 } 7995 7996 seg = blob->segs; 7997 while (*seg && rval == QLA_SUCCESS) { 7998 risc_addr = *seg; 7999 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr; 8000 risc_size = be16_to_cpu(fwcode[3]); 8001 8002 /* Validate firmware image size. */ 8003 fwclen += risc_size * sizeof(uint16_t); 8004 if (blob->fw->size < fwclen) { 8005 ql_log(ql_log_fatal, vha, 0x0088, 8006 "Unable to verify integrity of firmware image " 8007 "(%zd).\n", blob->fw->size); 8008 goto fail_fw_integrity; 8009 } 8010 8011 fragment = 0; 8012 while (risc_size > 0 && rval == QLA_SUCCESS) { 8013 wlen = (uint16_t)(ha->fw_transfer_size >> 1); 8014 if (wlen > risc_size) 8015 wlen = risc_size; 8016 ql_dbg(ql_dbg_init, vha, 0x0089, 8017 "Loading risc segment@ risc addr %x number of " 8018 "words 0x%x.\n", risc_addr, wlen); 8019 8020 for (i = 0; i < wlen; i++) 8021 wcode[i] = swab16((__force u32)fwcode[i]); 8022 8023 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 8024 wlen); 8025 if (rval) { 8026 ql_log(ql_log_fatal, vha, 0x008a, 8027 "Failed to load segment %d of firmware.\n", 8028 fragment); 8029 break; 8030 } 8031 8032 fwcode += wlen; 8033 risc_addr += wlen; 8034 risc_size -= wlen; 8035 fragment++; 8036 } 8037 8038 /* Next segment. */ 8039 seg++; 8040 } 8041 return rval; 8042 8043 fail_fw_integrity: 8044 return QLA_FUNCTION_FAILED; 8045 } 8046 8047 static int 8048 qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8049 { 8050 int rval; 8051 uint templates, segments, fragment; 8052 uint32_t *dcode; 8053 ulong dlen; 8054 uint32_t risc_addr, risc_size, risc_attr = 0; 8055 ulong i; 8056 uint j; 8057 struct fw_blob *blob; 8058 __be32 *fwcode; 8059 struct qla_hw_data *ha = vha->hw; 8060 struct req_que *req = ha->req_q_map[0]; 8061 struct fwdt *fwdt = ha->fwdt; 8062 8063 ql_dbg(ql_dbg_init, vha, 0x0090, 8064 "-> FW: Loading via request-firmware.\n"); 8065 8066 blob = qla2x00_request_firmware(vha); 8067 if (!blob) { 8068 ql_log(ql_log_warn, vha, 0x0092, 8069 "-> Firmware file not found.\n"); 8070 8071 return QLA_FUNCTION_FAILED; 8072 } 8073 8074 fwcode = (__force __be32 *)blob->fw->data; 8075 dcode = (__force uint32_t *)fwcode; 8076 if (qla24xx_risc_firmware_invalid(dcode)) { 8077 ql_log(ql_log_fatal, vha, 0x0093, 8078 "Unable to verify integrity of firmware image (%zd).\n", 8079 blob->fw->size); 8080 ql_log(ql_log_fatal, vha, 0x0095, 8081 "Firmware data: %08x %08x %08x %08x.\n", 8082 dcode[0], dcode[1], dcode[2], dcode[3]); 8083 return QLA_FUNCTION_FAILED; 8084 } 8085 8086 dcode = (uint32_t *)req->ring; 8087 *srisc_addr = 0; 8088 segments = FA_RISC_CODE_SEGMENTS; 8089 for (j = 0; j < segments; j++) { 8090 ql_dbg(ql_dbg_init, vha, 0x0096, 8091 "-> Loading segment %u...\n", j); 8092 risc_addr = be32_to_cpu(fwcode[2]); 8093 risc_size = be32_to_cpu(fwcode[3]); 8094 8095 if (!*srisc_addr) { 8096 *srisc_addr = risc_addr; 8097 risc_attr = be32_to_cpu(fwcode[9]); 8098 } 8099 8100 dlen = ha->fw_transfer_size >> 2; 8101 for (fragment = 0; risc_size; fragment++) { 8102 if (dlen > risc_size) 8103 dlen = risc_size; 8104 8105 ql_dbg(ql_dbg_init, vha, 0x0097, 8106 "-> Loading fragment %u: %#x <- %#x (%#lx words)...\n", 8107 fragment, risc_addr, 8108 (uint32_t)(fwcode - (typeof(fwcode))blob->fw->data), 8109 dlen); 8110 8111 for (i = 0; i < dlen; i++) 8112 dcode[i] = swab32((__force u32)fwcode[i]); 8113 8114 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen); 8115 if (rval) { 8116 ql_log(ql_log_fatal, vha, 0x0098, 8117 "-> Failed load firmware fragment %u.\n", 8118 fragment); 8119 return QLA_FUNCTION_FAILED; 8120 } 8121 8122 fwcode += dlen; 8123 risc_addr += dlen; 8124 risc_size -= dlen; 8125 } 8126 } 8127 8128 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 8129 return QLA_SUCCESS; 8130 8131 templates = (risc_attr & BIT_9) ? 2 : 1; 8132 ql_dbg(ql_dbg_init, vha, 0x0170, "-> templates = %u\n", templates); 8133 for (j = 0; j < templates; j++, fwdt++) { 8134 vfree(fwdt->template); 8135 fwdt->template = NULL; 8136 fwdt->length = 0; 8137 8138 risc_size = be32_to_cpu(fwcode[2]); 8139 ql_dbg(ql_dbg_init, vha, 0x0171, 8140 "-> fwdt%u template array at %#x (%#x dwords)\n", 8141 j, (uint32_t)((void *)fwcode - (void *)blob->fw->data), 8142 risc_size); 8143 if (!risc_size || !~risc_size) { 8144 ql_dbg(ql_dbg_init, vha, 0x0172, 8145 "-> fwdt%u failed to read array\n", j); 8146 goto failed; 8147 } 8148 8149 /* skip header and ignore checksum */ 8150 fwcode += 7; 8151 risc_size -= 8; 8152 8153 ql_dbg(ql_dbg_init, vha, 0x0173, 8154 "-> fwdt%u template allocate template %#x words...\n", 8155 j, risc_size); 8156 fwdt->template = vmalloc(risc_size * sizeof(*dcode)); 8157 if (!fwdt->template) { 8158 ql_log(ql_log_warn, vha, 0x0174, 8159 "-> fwdt%u failed allocate template.\n", j); 8160 goto failed; 8161 } 8162 8163 dcode = fwdt->template; 8164 for (i = 0; i < risc_size; i++) 8165 dcode[i] = (__force u32)fwcode[i]; 8166 8167 if (!qla27xx_fwdt_template_valid(dcode)) { 8168 ql_log(ql_log_warn, vha, 0x0175, 8169 "-> fwdt%u failed template validate\n", j); 8170 goto failed; 8171 } 8172 8173 dlen = qla27xx_fwdt_template_size(dcode); 8174 ql_dbg(ql_dbg_init, vha, 0x0176, 8175 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 8176 j, dlen, dlen / sizeof(*dcode)); 8177 if (dlen > risc_size * sizeof(*dcode)) { 8178 ql_log(ql_log_warn, vha, 0x0177, 8179 "-> fwdt%u template exceeds array (%-lu bytes)\n", 8180 j, dlen - risc_size * sizeof(*dcode)); 8181 goto failed; 8182 } 8183 8184 fwdt->length = dlen; 8185 ql_dbg(ql_dbg_init, vha, 0x0178, 8186 "-> fwdt%u loaded template ok\n", j); 8187 8188 fwcode += risc_size + 1; 8189 } 8190 8191 return QLA_SUCCESS; 8192 8193 failed: 8194 vfree(fwdt->template); 8195 fwdt->template = NULL; 8196 fwdt->length = 0; 8197 8198 return QLA_SUCCESS; 8199 } 8200 8201 int 8202 qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8203 { 8204 int rval; 8205 8206 if (ql2xfwloadbin == 1) 8207 return qla81xx_load_risc(vha, srisc_addr); 8208 8209 /* 8210 * FW Load priority: 8211 * 1) Firmware via request-firmware interface (.bin file). 8212 * 2) Firmware residing in flash. 8213 */ 8214 rval = qla24xx_load_risc_blob(vha, srisc_addr); 8215 if (rval == QLA_SUCCESS) 8216 return rval; 8217 8218 return qla24xx_load_risc_flash(vha, srisc_addr, 8219 vha->hw->flt_region_fw); 8220 } 8221 8222 int 8223 qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8224 { 8225 int rval; 8226 struct qla_hw_data *ha = vha->hw; 8227 struct active_regions active_regions = { }; 8228 8229 if (ql2xfwloadbin == 2) 8230 goto try_blob_fw; 8231 8232 /* FW Load priority: 8233 * 1) Firmware residing in flash. 8234 * 2) Firmware via request-firmware interface (.bin file). 8235 * 3) Golden-Firmware residing in flash -- (limited operation). 8236 */ 8237 8238 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 8239 goto try_primary_fw; 8240 8241 qla27xx_get_active_image(vha, &active_regions); 8242 8243 if (active_regions.global != QLA27XX_SECONDARY_IMAGE) 8244 goto try_primary_fw; 8245 8246 ql_dbg(ql_dbg_init, vha, 0x008b, 8247 "Loading secondary firmware image.\n"); 8248 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec); 8249 if (!rval) 8250 return rval; 8251 8252 try_primary_fw: 8253 ql_dbg(ql_dbg_init, vha, 0x008b, 8254 "Loading primary firmware image.\n"); 8255 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw); 8256 if (!rval) 8257 return rval; 8258 8259 try_blob_fw: 8260 rval = qla24xx_load_risc_blob(vha, srisc_addr); 8261 if (!rval || !ha->flt_region_gold_fw) 8262 return rval; 8263 8264 ql_log(ql_log_info, vha, 0x0099, 8265 "Attempting to fallback to golden firmware.\n"); 8266 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw); 8267 if (rval) 8268 return rval; 8269 8270 ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n"); 8271 ha->flags.running_gold_fw = 1; 8272 return rval; 8273 } 8274 8275 void 8276 qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) 8277 { 8278 int ret, retries; 8279 struct qla_hw_data *ha = vha->hw; 8280 8281 if (ha->flags.pci_channel_io_perm_failure) 8282 return; 8283 if (!IS_FWI2_CAPABLE(ha)) 8284 return; 8285 if (!ha->fw_major_version) 8286 return; 8287 if (!ha->flags.fw_started) 8288 return; 8289 8290 ret = qla2x00_stop_firmware(vha); 8291 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT && 8292 ret != QLA_INVALID_COMMAND && retries ; retries--) { 8293 ha->isp_ops->reset_chip(vha); 8294 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS) 8295 continue; 8296 if (qla2x00_setup_chip(vha) != QLA_SUCCESS) 8297 continue; 8298 ql_log(ql_log_info, vha, 0x8015, 8299 "Attempting retry of stop-firmware command.\n"); 8300 ret = qla2x00_stop_firmware(vha); 8301 } 8302 8303 QLA_FW_STOPPED(ha); 8304 ha->flags.fw_init_done = 0; 8305 } 8306 8307 int 8308 qla24xx_configure_vhba(scsi_qla_host_t *vha) 8309 { 8310 int rval = QLA_SUCCESS; 8311 int rval2; 8312 uint16_t mb[MAILBOX_REGISTER_COUNT]; 8313 struct qla_hw_data *ha = vha->hw; 8314 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 8315 8316 if (!vha->vp_idx) 8317 return -EINVAL; 8318 8319 rval = qla2x00_fw_ready(base_vha); 8320 8321 if (rval == QLA_SUCCESS) { 8322 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 8323 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 8324 } 8325 8326 vha->flags.management_server_logged_in = 0; 8327 8328 /* Login to SNS first */ 8329 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, 8330 BIT_1); 8331 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 8332 if (rval2 == QLA_MEMORY_ALLOC_FAILED) 8333 ql_dbg(ql_dbg_init, vha, 0x0120, 8334 "Failed SNS login: loop_id=%x, rval2=%d\n", 8335 NPH_SNS, rval2); 8336 else 8337 ql_dbg(ql_dbg_init, vha, 0x0103, 8338 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x " 8339 "mb[2]=%x mb[6]=%x mb[7]=%x.\n", 8340 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]); 8341 return (QLA_FUNCTION_FAILED); 8342 } 8343 8344 atomic_set(&vha->loop_down_timer, 0); 8345 atomic_set(&vha->loop_state, LOOP_UP); 8346 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 8347 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 8348 rval = qla2x00_loop_resync(base_vha); 8349 8350 return rval; 8351 } 8352 8353 /* 84XX Support **************************************************************/ 8354 8355 static LIST_HEAD(qla_cs84xx_list); 8356 static DEFINE_MUTEX(qla_cs84xx_mutex); 8357 8358 static struct qla_chip_state_84xx * 8359 qla84xx_get_chip(struct scsi_qla_host *vha) 8360 { 8361 struct qla_chip_state_84xx *cs84xx; 8362 struct qla_hw_data *ha = vha->hw; 8363 8364 mutex_lock(&qla_cs84xx_mutex); 8365 8366 /* Find any shared 84xx chip. */ 8367 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) { 8368 if (cs84xx->bus == ha->pdev->bus) { 8369 kref_get(&cs84xx->kref); 8370 goto done; 8371 } 8372 } 8373 8374 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL); 8375 if (!cs84xx) 8376 goto done; 8377 8378 kref_init(&cs84xx->kref); 8379 spin_lock_init(&cs84xx->access_lock); 8380 mutex_init(&cs84xx->fw_update_mutex); 8381 cs84xx->bus = ha->pdev->bus; 8382 8383 list_add_tail(&cs84xx->list, &qla_cs84xx_list); 8384 done: 8385 mutex_unlock(&qla_cs84xx_mutex); 8386 return cs84xx; 8387 } 8388 8389 static void 8390 __qla84xx_chip_release(struct kref *kref) 8391 { 8392 struct qla_chip_state_84xx *cs84xx = 8393 container_of(kref, struct qla_chip_state_84xx, kref); 8394 8395 mutex_lock(&qla_cs84xx_mutex); 8396 list_del(&cs84xx->list); 8397 mutex_unlock(&qla_cs84xx_mutex); 8398 kfree(cs84xx); 8399 } 8400 8401 void 8402 qla84xx_put_chip(struct scsi_qla_host *vha) 8403 { 8404 struct qla_hw_data *ha = vha->hw; 8405 8406 if (ha->cs84xx) 8407 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release); 8408 } 8409 8410 static int 8411 qla84xx_init_chip(scsi_qla_host_t *vha) 8412 { 8413 int rval; 8414 uint16_t status[2]; 8415 struct qla_hw_data *ha = vha->hw; 8416 8417 mutex_lock(&ha->cs84xx->fw_update_mutex); 8418 8419 rval = qla84xx_verify_chip(vha, status); 8420 8421 mutex_unlock(&ha->cs84xx->fw_update_mutex); 8422 8423 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED : 8424 QLA_SUCCESS; 8425 } 8426 8427 /* 81XX Support **************************************************************/ 8428 8429 int 8430 qla81xx_nvram_config(scsi_qla_host_t *vha) 8431 { 8432 int rval; 8433 struct init_cb_81xx *icb; 8434 struct nvram_81xx *nv; 8435 __le32 *dptr; 8436 uint8_t *dptr1, *dptr2; 8437 uint32_t chksum; 8438 uint16_t cnt; 8439 struct qla_hw_data *ha = vha->hw; 8440 uint32_t faddr; 8441 struct active_regions active_regions = { }; 8442 8443 rval = QLA_SUCCESS; 8444 icb = (struct init_cb_81xx *)ha->init_cb; 8445 nv = ha->nvram; 8446 8447 /* Determine NVRAM starting address. */ 8448 ha->nvram_size = sizeof(*nv); 8449 ha->vpd_size = FA_NVRAM_VPD_SIZE; 8450 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 8451 ha->vpd_size = FA_VPD_SIZE_82XX; 8452 8453 if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) 8454 qla28xx_get_aux_images(vha, &active_regions); 8455 8456 /* Get VPD data into cache */ 8457 ha->vpd = ha->nvram + VPD_OFFSET; 8458 8459 faddr = ha->flt_region_vpd; 8460 if (IS_QLA28XX(ha)) { 8461 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE) 8462 faddr = ha->flt_region_vpd_sec; 8463 ql_dbg(ql_dbg_init, vha, 0x0110, 8464 "Loading %s nvram image.\n", 8465 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ? 8466 "primary" : "secondary"); 8467 } 8468 ha->isp_ops->read_optrom(vha, ha->vpd, faddr << 2, ha->vpd_size); 8469 8470 /* Get NVRAM data into cache and calculate checksum. */ 8471 faddr = ha->flt_region_nvram; 8472 if (IS_QLA28XX(ha)) { 8473 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE) 8474 faddr = ha->flt_region_nvram_sec; 8475 } 8476 ql_dbg(ql_dbg_init, vha, 0x0110, 8477 "Loading %s nvram image.\n", 8478 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ? 8479 "primary" : "secondary"); 8480 ha->isp_ops->read_optrom(vha, ha->nvram, faddr << 2, ha->nvram_size); 8481 8482 dptr = (__force __le32 *)nv; 8483 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 8484 chksum += le32_to_cpu(*dptr); 8485 8486 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111, 8487 "Contents of NVRAM:\n"); 8488 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112, 8489 nv, ha->nvram_size); 8490 8491 /* Bad NVRAM data, set defaults parameters. */ 8492 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 8493 le16_to_cpu(nv->nvram_version) < ICB_VERSION) { 8494 /* Reset NVRAM data. */ 8495 ql_log(ql_log_info, vha, 0x0073, 8496 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n", 8497 chksum, nv->id, le16_to_cpu(nv->nvram_version)); 8498 ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, sizeof(*nv)); 8499 ql_log(ql_log_info, vha, 0x0074, 8500 "Falling back to functioning (yet invalid -- WWPN) " 8501 "defaults.\n"); 8502 8503 /* 8504 * Set default initialization control block. 8505 */ 8506 memset(nv, 0, ha->nvram_size); 8507 nv->nvram_version = cpu_to_le16(ICB_VERSION); 8508 nv->version = cpu_to_le16(ICB_VERSION); 8509 nv->frame_payload_size = cpu_to_le16(2048); 8510 nv->execution_throttle = cpu_to_le16(0xFFFF); 8511 nv->exchange_count = cpu_to_le16(0); 8512 nv->port_name[0] = 0x21; 8513 nv->port_name[1] = 0x00 + ha->port_no + 1; 8514 nv->port_name[2] = 0x00; 8515 nv->port_name[3] = 0xe0; 8516 nv->port_name[4] = 0x8b; 8517 nv->port_name[5] = 0x1c; 8518 nv->port_name[6] = 0x55; 8519 nv->port_name[7] = 0x86; 8520 nv->node_name[0] = 0x20; 8521 nv->node_name[1] = 0x00; 8522 nv->node_name[2] = 0x00; 8523 nv->node_name[3] = 0xe0; 8524 nv->node_name[4] = 0x8b; 8525 nv->node_name[5] = 0x1c; 8526 nv->node_name[6] = 0x55; 8527 nv->node_name[7] = 0x86; 8528 nv->login_retry_count = cpu_to_le16(8); 8529 nv->interrupt_delay_timer = cpu_to_le16(0); 8530 nv->login_timeout = cpu_to_le16(0); 8531 nv->firmware_options_1 = 8532 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 8533 nv->firmware_options_2 = cpu_to_le32(2 << 4); 8534 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 8535 nv->firmware_options_3 = cpu_to_le32(2 << 13); 8536 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 8537 nv->efi_parameters = cpu_to_le32(0); 8538 nv->reset_delay = 5; 8539 nv->max_luns_per_target = cpu_to_le16(128); 8540 nv->port_down_retry_count = cpu_to_le16(30); 8541 nv->link_down_timeout = cpu_to_le16(180); 8542 nv->enode_mac[0] = 0x00; 8543 nv->enode_mac[1] = 0xC0; 8544 nv->enode_mac[2] = 0xDD; 8545 nv->enode_mac[3] = 0x04; 8546 nv->enode_mac[4] = 0x05; 8547 nv->enode_mac[5] = 0x06 + ha->port_no + 1; 8548 8549 rval = 1; 8550 } 8551 8552 if (IS_T10_PI_CAPABLE(ha)) 8553 nv->frame_payload_size &= cpu_to_le16(~7); 8554 8555 qlt_81xx_config_nvram_stage1(vha, nv); 8556 8557 /* Reset Initialization control block */ 8558 memset(icb, 0, ha->init_cb_size); 8559 8560 /* Copy 1st segment. */ 8561 dptr1 = (uint8_t *)icb; 8562 dptr2 = (uint8_t *)&nv->version; 8563 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 8564 while (cnt--) 8565 *dptr1++ = *dptr2++; 8566 8567 icb->login_retry_count = nv->login_retry_count; 8568 8569 /* Copy 2nd segment. */ 8570 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 8571 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 8572 cnt = (uint8_t *)&icb->reserved_5 - 8573 (uint8_t *)&icb->interrupt_delay_timer; 8574 while (cnt--) 8575 *dptr1++ = *dptr2++; 8576 8577 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac)); 8578 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */ 8579 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) { 8580 icb->enode_mac[0] = 0x00; 8581 icb->enode_mac[1] = 0xC0; 8582 icb->enode_mac[2] = 0xDD; 8583 icb->enode_mac[3] = 0x04; 8584 icb->enode_mac[4] = 0x05; 8585 icb->enode_mac[5] = 0x06 + ha->port_no + 1; 8586 } 8587 8588 /* Use extended-initialization control block. */ 8589 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb)); 8590 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 8591 /* 8592 * Setup driver NVRAM options. 8593 */ 8594 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 8595 "QLE8XXX"); 8596 8597 qlt_81xx_config_nvram_stage2(vha, icb); 8598 8599 /* Use alternate WWN? */ 8600 if (nv->host_p & cpu_to_le32(BIT_15)) { 8601 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 8602 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 8603 } 8604 8605 /* Prepare nodename */ 8606 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 8607 /* 8608 * Firmware will apply the following mask if the nodename was 8609 * not provided. 8610 */ 8611 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 8612 icb->node_name[0] &= 0xF0; 8613 } 8614 8615 if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) { 8616 if ((nv->enhanced_features & BIT_7) == 0) 8617 ha->flags.scm_supported_a = 1; 8618 } 8619 8620 /* Set host adapter parameters. */ 8621 ha->flags.disable_risc_code_load = 0; 8622 ha->flags.enable_lip_reset = 0; 8623 ha->flags.enable_lip_full_login = 8624 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0; 8625 ha->flags.enable_target_reset = 8626 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0; 8627 ha->flags.enable_led_scheme = 0; 8628 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0; 8629 8630 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 8631 (BIT_6 | BIT_5 | BIT_4)) >> 4; 8632 8633 /* save HBA serial number */ 8634 ha->serial0 = icb->port_name[5]; 8635 ha->serial1 = icb->port_name[6]; 8636 ha->serial2 = icb->port_name[7]; 8637 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 8638 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 8639 8640 icb->execution_throttle = cpu_to_le16(0xFFFF); 8641 8642 ha->retry_count = le16_to_cpu(nv->login_retry_count); 8643 8644 /* Set minimum login_timeout to 4 seconds. */ 8645 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 8646 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 8647 if (le16_to_cpu(nv->login_timeout) < 4) 8648 nv->login_timeout = cpu_to_le16(4); 8649 ha->login_timeout = le16_to_cpu(nv->login_timeout); 8650 8651 /* Set minimum RATOV to 100 tenths of a second. */ 8652 ha->r_a_tov = 100; 8653 8654 ha->loop_reset_delay = nv->reset_delay; 8655 8656 /* Link Down Timeout = 0: 8657 * 8658 * When Port Down timer expires we will start returning 8659 * I/O's to OS with "DID_NO_CONNECT". 8660 * 8661 * Link Down Timeout != 0: 8662 * 8663 * The driver waits for the link to come up after link down 8664 * before returning I/Os to OS with "DID_NO_CONNECT". 8665 */ 8666 if (le16_to_cpu(nv->link_down_timeout) == 0) { 8667 ha->loop_down_abort_time = 8668 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 8669 } else { 8670 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 8671 ha->loop_down_abort_time = 8672 (LOOP_DOWN_TIME - ha->link_down_timeout); 8673 } 8674 8675 /* Need enough time to try and get the port back. */ 8676 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 8677 if (qlport_down_retry) 8678 ha->port_down_retry_count = qlport_down_retry; 8679 8680 /* Set login_retry_count */ 8681 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 8682 if (ha->port_down_retry_count == 8683 le16_to_cpu(nv->port_down_retry_count) && 8684 ha->port_down_retry_count > 3) 8685 ha->login_retry_count = ha->port_down_retry_count; 8686 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 8687 ha->login_retry_count = ha->port_down_retry_count; 8688 if (ql2xloginretrycount) 8689 ha->login_retry_count = ql2xloginretrycount; 8690 8691 /* if not running MSI-X we need handshaking on interrupts */ 8692 if (!vha->hw->flags.msix_enabled && 8693 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) 8694 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 8695 8696 /* Enable ZIO. */ 8697 if (!vha->flags.init_done) { 8698 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 8699 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 8700 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 8701 le16_to_cpu(icb->interrupt_delay_timer) : 2; 8702 } 8703 icb->firmware_options_2 &= cpu_to_le32( 8704 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 8705 vha->flags.process_response_queue = 0; 8706 if (ha->zio_mode != QLA_ZIO_DISABLED) { 8707 ha->zio_mode = QLA_ZIO_MODE_6; 8708 8709 ql_log(ql_log_info, vha, 0x0075, 8710 "ZIO mode %d enabled; timer delay (%d us).\n", 8711 ha->zio_mode, 8712 ha->zio_timer * 100); 8713 8714 icb->firmware_options_2 |= cpu_to_le32( 8715 (uint32_t)ha->zio_mode); 8716 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 8717 vha->flags.process_response_queue = 1; 8718 } 8719 8720 /* enable RIDA Format2 */ 8721 icb->firmware_options_3 |= cpu_to_le32(BIT_0); 8722 8723 /* N2N: driver will initiate Login instead of FW */ 8724 icb->firmware_options_3 |= cpu_to_le32(BIT_8); 8725 8726 /* Determine NVMe/FCP priority for target ports */ 8727 ha->fc4_type_priority = qla2xxx_get_fc4_priority(vha); 8728 8729 if (rval) { 8730 ql_log(ql_log_warn, vha, 0x0076, 8731 "NVRAM configuration failed.\n"); 8732 } 8733 return (rval); 8734 } 8735 8736 int 8737 qla82xx_restart_isp(scsi_qla_host_t *vha) 8738 { 8739 int status, rval; 8740 struct qla_hw_data *ha = vha->hw; 8741 struct scsi_qla_host *vp; 8742 unsigned long flags; 8743 8744 status = qla2x00_init_rings(vha); 8745 if (!status) { 8746 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 8747 ha->flags.chip_reset_done = 1; 8748 8749 status = qla2x00_fw_ready(vha); 8750 if (!status) { 8751 /* Issue a marker after FW becomes ready. */ 8752 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 8753 vha->flags.online = 1; 8754 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 8755 } 8756 8757 /* if no cable then assume it's good */ 8758 if ((vha->device_flags & DFLG_NO_CABLE)) 8759 status = 0; 8760 } 8761 8762 if (!status) { 8763 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 8764 8765 if (!atomic_read(&vha->loop_down_timer)) { 8766 /* 8767 * Issue marker command only when we are going 8768 * to start the I/O . 8769 */ 8770 vha->marker_needed = 1; 8771 } 8772 8773 ha->isp_ops->enable_intrs(ha); 8774 8775 ha->isp_abort_cnt = 0; 8776 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 8777 8778 /* Update the firmware version */ 8779 status = qla82xx_check_md_needed(vha); 8780 8781 if (ha->fce) { 8782 ha->flags.fce_enabled = 1; 8783 memset(ha->fce, 0, 8784 fce_calc_size(ha->fce_bufs)); 8785 rval = qla2x00_enable_fce_trace(vha, 8786 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 8787 &ha->fce_bufs); 8788 if (rval) { 8789 ql_log(ql_log_warn, vha, 0x8001, 8790 "Unable to reinitialize FCE (%d).\n", 8791 rval); 8792 ha->flags.fce_enabled = 0; 8793 } 8794 } 8795 8796 if (ha->eft) { 8797 memset(ha->eft, 0, EFT_SIZE); 8798 rval = qla2x00_enable_eft_trace(vha, 8799 ha->eft_dma, EFT_NUM_BUFFERS); 8800 if (rval) { 8801 ql_log(ql_log_warn, vha, 0x8010, 8802 "Unable to reinitialize EFT (%d).\n", 8803 rval); 8804 } 8805 } 8806 } 8807 8808 if (!status) { 8809 ql_dbg(ql_dbg_taskm, vha, 0x8011, 8810 "qla82xx_restart_isp succeeded.\n"); 8811 8812 spin_lock_irqsave(&ha->vport_slock, flags); 8813 list_for_each_entry(vp, &ha->vp_list, list) { 8814 if (vp->vp_idx) { 8815 atomic_inc(&vp->vref_count); 8816 spin_unlock_irqrestore(&ha->vport_slock, flags); 8817 8818 qla2x00_vp_abort_isp(vp); 8819 8820 spin_lock_irqsave(&ha->vport_slock, flags); 8821 atomic_dec(&vp->vref_count); 8822 } 8823 } 8824 spin_unlock_irqrestore(&ha->vport_slock, flags); 8825 8826 } else { 8827 ql_log(ql_log_warn, vha, 0x8016, 8828 "qla82xx_restart_isp **** FAILED ****.\n"); 8829 } 8830 8831 return status; 8832 } 8833 8834 /* 8835 * qla24xx_get_fcp_prio 8836 * Gets the fcp cmd priority value for the logged in port. 8837 * Looks for a match of the port descriptors within 8838 * each of the fcp prio config entries. If a match is found, 8839 * the tag (priority) value is returned. 8840 * 8841 * Input: 8842 * vha = scsi host structure pointer. 8843 * fcport = port structure pointer. 8844 * 8845 * Return: 8846 * non-zero (if found) 8847 * -1 (if not found) 8848 * 8849 * Context: 8850 * Kernel context 8851 */ 8852 static int 8853 qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 8854 { 8855 int i, entries; 8856 uint8_t pid_match, wwn_match; 8857 int priority; 8858 uint32_t pid1, pid2; 8859 uint64_t wwn1, wwn2; 8860 struct qla_fcp_prio_entry *pri_entry; 8861 struct qla_hw_data *ha = vha->hw; 8862 8863 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled) 8864 return -1; 8865 8866 priority = -1; 8867 entries = ha->fcp_prio_cfg->num_entries; 8868 pri_entry = &ha->fcp_prio_cfg->entry[0]; 8869 8870 for (i = 0; i < entries; i++) { 8871 pid_match = wwn_match = 0; 8872 8873 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) { 8874 pri_entry++; 8875 continue; 8876 } 8877 8878 /* check source pid for a match */ 8879 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) { 8880 pid1 = pri_entry->src_pid & INVALID_PORT_ID; 8881 pid2 = vha->d_id.b24 & INVALID_PORT_ID; 8882 if (pid1 == INVALID_PORT_ID) 8883 pid_match++; 8884 else if (pid1 == pid2) 8885 pid_match++; 8886 } 8887 8888 /* check destination pid for a match */ 8889 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) { 8890 pid1 = pri_entry->dst_pid & INVALID_PORT_ID; 8891 pid2 = fcport->d_id.b24 & INVALID_PORT_ID; 8892 if (pid1 == INVALID_PORT_ID) 8893 pid_match++; 8894 else if (pid1 == pid2) 8895 pid_match++; 8896 } 8897 8898 /* check source WWN for a match */ 8899 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) { 8900 wwn1 = wwn_to_u64(vha->port_name); 8901 wwn2 = wwn_to_u64(pri_entry->src_wwpn); 8902 if (wwn2 == (uint64_t)-1) 8903 wwn_match++; 8904 else if (wwn1 == wwn2) 8905 wwn_match++; 8906 } 8907 8908 /* check destination WWN for a match */ 8909 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) { 8910 wwn1 = wwn_to_u64(fcport->port_name); 8911 wwn2 = wwn_to_u64(pri_entry->dst_wwpn); 8912 if (wwn2 == (uint64_t)-1) 8913 wwn_match++; 8914 else if (wwn1 == wwn2) 8915 wwn_match++; 8916 } 8917 8918 if (pid_match == 2 || wwn_match == 2) { 8919 /* Found a matching entry */ 8920 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID) 8921 priority = pri_entry->tag; 8922 break; 8923 } 8924 8925 pri_entry++; 8926 } 8927 8928 return priority; 8929 } 8930 8931 /* 8932 * qla24xx_update_fcport_fcp_prio 8933 * Activates fcp priority for the logged in fc port 8934 * 8935 * Input: 8936 * vha = scsi host structure pointer. 8937 * fcp = port structure pointer. 8938 * 8939 * Return: 8940 * QLA_SUCCESS or QLA_FUNCTION_FAILED 8941 * 8942 * Context: 8943 * Kernel context. 8944 */ 8945 int 8946 qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 8947 { 8948 int ret; 8949 int priority; 8950 uint16_t mb[5]; 8951 8952 if (fcport->port_type != FCT_TARGET || 8953 fcport->loop_id == FC_NO_LOOP_ID) 8954 return QLA_FUNCTION_FAILED; 8955 8956 priority = qla24xx_get_fcp_prio(vha, fcport); 8957 if (priority < 0) 8958 return QLA_FUNCTION_FAILED; 8959 8960 if (IS_P3P_TYPE(vha->hw)) { 8961 fcport->fcp_prio = priority & 0xf; 8962 return QLA_SUCCESS; 8963 } 8964 8965 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb); 8966 if (ret == QLA_SUCCESS) { 8967 if (fcport->fcp_prio != priority) 8968 ql_dbg(ql_dbg_user, vha, 0x709e, 8969 "Updated FCP_CMND priority - value=%d loop_id=%d " 8970 "port_id=%02x%02x%02x.\n", priority, 8971 fcport->loop_id, fcport->d_id.b.domain, 8972 fcport->d_id.b.area, fcport->d_id.b.al_pa); 8973 fcport->fcp_prio = priority & 0xf; 8974 } else 8975 ql_dbg(ql_dbg_user, vha, 0x704f, 8976 "Unable to update FCP_CMND priority - ret=0x%x for " 8977 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id, 8978 fcport->d_id.b.domain, fcport->d_id.b.area, 8979 fcport->d_id.b.al_pa); 8980 return ret; 8981 } 8982 8983 /* 8984 * qla24xx_update_all_fcp_prio 8985 * Activates fcp priority for all the logged in ports 8986 * 8987 * Input: 8988 * ha = adapter block pointer. 8989 * 8990 * Return: 8991 * QLA_SUCCESS or QLA_FUNCTION_FAILED 8992 * 8993 * Context: 8994 * Kernel context. 8995 */ 8996 int 8997 qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha) 8998 { 8999 int ret; 9000 fc_port_t *fcport; 9001 9002 ret = QLA_FUNCTION_FAILED; 9003 /* We need to set priority for all logged in ports */ 9004 list_for_each_entry(fcport, &vha->vp_fcports, list) 9005 ret = qla24xx_update_fcport_fcp_prio(vha, fcport); 9006 9007 return ret; 9008 } 9009 9010 struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, 9011 int vp_idx, bool startqp) 9012 { 9013 int rsp_id = 0; 9014 int req_id = 0; 9015 int i; 9016 struct qla_hw_data *ha = vha->hw; 9017 uint16_t qpair_id = 0; 9018 struct qla_qpair *qpair = NULL; 9019 struct qla_msix_entry *msix; 9020 9021 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) { 9022 ql_log(ql_log_warn, vha, 0x00181, 9023 "FW/Driver is not multi-queue capable.\n"); 9024 return NULL; 9025 } 9026 9027 if (ql2xmqsupport || ql2xnvmeenable) { 9028 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 9029 if (qpair == NULL) { 9030 ql_log(ql_log_warn, vha, 0x0182, 9031 "Failed to allocate memory for queue pair.\n"); 9032 return NULL; 9033 } 9034 9035 qpair->hw = vha->hw; 9036 qpair->vha = vha; 9037 qpair->qp_lock_ptr = &qpair->qp_lock; 9038 spin_lock_init(&qpair->qp_lock); 9039 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 9040 9041 /* Assign available que pair id */ 9042 mutex_lock(&ha->mq_lock); 9043 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs); 9044 if (ha->num_qpairs >= ha->max_qpairs) { 9045 mutex_unlock(&ha->mq_lock); 9046 ql_log(ql_log_warn, vha, 0x0183, 9047 "No resources to create additional q pair.\n"); 9048 goto fail_qid_map; 9049 } 9050 ha->num_qpairs++; 9051 set_bit(qpair_id, ha->qpair_qid_map); 9052 ha->queue_pair_map[qpair_id] = qpair; 9053 qpair->id = qpair_id; 9054 qpair->vp_idx = vp_idx; 9055 qpair->fw_started = ha->flags.fw_started; 9056 INIT_LIST_HEAD(&qpair->hints_list); 9057 qpair->chip_reset = ha->base_qpair->chip_reset; 9058 qpair->enable_class_2 = ha->base_qpair->enable_class_2; 9059 qpair->enable_explicit_conf = 9060 ha->base_qpair->enable_explicit_conf; 9061 9062 for (i = 0; i < ha->msix_count; i++) { 9063 msix = &ha->msix_entries[i]; 9064 if (msix->in_use) 9065 continue; 9066 qpair->msix = msix; 9067 ql_dbg(ql_dbg_multiq, vha, 0xc00f, 9068 "Vector %x selected for qpair\n", msix->vector); 9069 break; 9070 } 9071 if (!qpair->msix) { 9072 ql_log(ql_log_warn, vha, 0x0184, 9073 "Out of MSI-X vectors!.\n"); 9074 goto fail_msix; 9075 } 9076 9077 qpair->msix->in_use = 1; 9078 list_add_tail(&qpair->qp_list_elem, &vha->qp_list); 9079 qpair->pdev = ha->pdev; 9080 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 9081 qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 9082 9083 mutex_unlock(&ha->mq_lock); 9084 9085 /* Create response queue first */ 9086 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp); 9087 if (!rsp_id) { 9088 ql_log(ql_log_warn, vha, 0x0185, 9089 "Failed to create response queue.\n"); 9090 goto fail_rsp; 9091 } 9092 9093 qpair->rsp = ha->rsp_q_map[rsp_id]; 9094 9095 /* Create request queue */ 9096 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos, 9097 startqp); 9098 if (!req_id) { 9099 ql_log(ql_log_warn, vha, 0x0186, 9100 "Failed to create request queue.\n"); 9101 goto fail_req; 9102 } 9103 9104 qpair->req = ha->req_q_map[req_id]; 9105 qpair->rsp->req = qpair->req; 9106 qpair->rsp->qpair = qpair; 9107 /* init qpair to this cpu. Will adjust at run time. */ 9108 qla_cpu_update(qpair, smp_processor_id()); 9109 9110 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 9111 if (ha->fw_attributes & BIT_4) 9112 qpair->difdix_supported = 1; 9113 } 9114 9115 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 9116 if (!qpair->srb_mempool) { 9117 ql_log(ql_log_warn, vha, 0xd036, 9118 "Failed to create srb mempool for qpair %d\n", 9119 qpair->id); 9120 goto fail_mempool; 9121 } 9122 9123 /* Mark as online */ 9124 qpair->online = 1; 9125 9126 if (!vha->flags.qpairs_available) 9127 vha->flags.qpairs_available = 1; 9128 9129 ql_dbg(ql_dbg_multiq, vha, 0xc00d, 9130 "Request/Response queue pair created, id %d\n", 9131 qpair->id); 9132 ql_dbg(ql_dbg_init, vha, 0x0187, 9133 "Request/Response queue pair created, id %d\n", 9134 qpair->id); 9135 } 9136 return qpair; 9137 9138 fail_mempool: 9139 fail_req: 9140 qla25xx_delete_rsp_que(vha, qpair->rsp); 9141 fail_rsp: 9142 mutex_lock(&ha->mq_lock); 9143 qpair->msix->in_use = 0; 9144 list_del(&qpair->qp_list_elem); 9145 if (list_empty(&vha->qp_list)) 9146 vha->flags.qpairs_available = 0; 9147 fail_msix: 9148 ha->queue_pair_map[qpair_id] = NULL; 9149 clear_bit(qpair_id, ha->qpair_qid_map); 9150 ha->num_qpairs--; 9151 mutex_unlock(&ha->mq_lock); 9152 fail_qid_map: 9153 kfree(qpair); 9154 return NULL; 9155 } 9156 9157 int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair) 9158 { 9159 int ret = QLA_FUNCTION_FAILED; 9160 struct qla_hw_data *ha = qpair->hw; 9161 9162 qpair->delete_in_progress = 1; 9163 9164 ret = qla25xx_delete_req_que(vha, qpair->req); 9165 if (ret != QLA_SUCCESS) 9166 goto fail; 9167 9168 ret = qla25xx_delete_rsp_que(vha, qpair->rsp); 9169 if (ret != QLA_SUCCESS) 9170 goto fail; 9171 9172 mutex_lock(&ha->mq_lock); 9173 ha->queue_pair_map[qpair->id] = NULL; 9174 clear_bit(qpair->id, ha->qpair_qid_map); 9175 ha->num_qpairs--; 9176 list_del(&qpair->qp_list_elem); 9177 if (list_empty(&vha->qp_list)) { 9178 vha->flags.qpairs_available = 0; 9179 vha->flags.qpairs_req_created = 0; 9180 vha->flags.qpairs_rsp_created = 0; 9181 } 9182 mempool_destroy(qpair->srb_mempool); 9183 kfree(qpair); 9184 mutex_unlock(&ha->mq_lock); 9185 9186 return QLA_SUCCESS; 9187 fail: 9188 return ret; 9189 } 9190 9191 uint64_t 9192 qla2x00_count_set_bits(uint32_t num) 9193 { 9194 /* Brian Kernighan's Algorithm */ 9195 u64 count = 0; 9196 9197 while (num) { 9198 num &= (num - 1); 9199 count++; 9200 } 9201 return count; 9202 } 9203 9204 uint64_t 9205 qla2x00_get_num_tgts(scsi_qla_host_t *vha) 9206 { 9207 fc_port_t *f, *tf; 9208 u64 count = 0; 9209 9210 f = NULL; 9211 tf = NULL; 9212 9213 list_for_each_entry_safe(f, tf, &vha->vp_fcports, list) { 9214 if (f->port_type != FCT_TARGET) 9215 continue; 9216 count++; 9217 } 9218 return count; 9219 } 9220 9221 int qla2xxx_reset_stats(struct Scsi_Host *host, u32 flags) 9222 { 9223 scsi_qla_host_t *vha = shost_priv(host); 9224 fc_port_t *fcport = NULL; 9225 unsigned long int_flags; 9226 9227 if (flags & QLA2XX_HW_ERROR) 9228 vha->hw_err_cnt = 0; 9229 if (flags & QLA2XX_SHT_LNK_DWN) 9230 vha->short_link_down_cnt = 0; 9231 if (flags & QLA2XX_INT_ERR) 9232 vha->interface_err_cnt = 0; 9233 if (flags & QLA2XX_CMD_TIMEOUT) 9234 vha->cmd_timeout_cnt = 0; 9235 if (flags & QLA2XX_RESET_CMD_ERR) 9236 vha->reset_cmd_err_cnt = 0; 9237 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) { 9238 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags); 9239 list_for_each_entry(fcport, &vha->vp_fcports, list) { 9240 fcport->tgt_short_link_down_cnt = 0; 9241 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 9242 } 9243 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags); 9244 } 9245 vha->link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 9246 return 0; 9247 } 9248 9249 int qla2xxx_start_stats(struct Scsi_Host *host, u32 flags) 9250 { 9251 return qla2xxx_reset_stats(host, flags); 9252 } 9253 9254 int qla2xxx_stop_stats(struct Scsi_Host *host, u32 flags) 9255 { 9256 return qla2xxx_reset_stats(host, flags); 9257 } 9258 9259 int qla2xxx_get_ini_stats(struct Scsi_Host *host, u32 flags, 9260 void *data, u64 size) 9261 { 9262 scsi_qla_host_t *vha = shost_priv(host); 9263 struct ql_vnd_host_stats_resp *resp = (struct ql_vnd_host_stats_resp *)data; 9264 struct ql_vnd_stats *rsp_data = &resp->stats; 9265 u64 ini_entry_count = 0; 9266 u64 i = 0; 9267 u64 entry_count = 0; 9268 u64 num_tgt = 0; 9269 u32 tmp_stat_type = 0; 9270 fc_port_t *fcport = NULL; 9271 unsigned long int_flags; 9272 9273 /* Copy stat type to work on it */ 9274 tmp_stat_type = flags; 9275 9276 if (tmp_stat_type & BIT_17) { 9277 num_tgt = qla2x00_get_num_tgts(vha); 9278 /* unset BIT_17 */ 9279 tmp_stat_type &= ~(1 << 17); 9280 } 9281 ini_entry_count = qla2x00_count_set_bits(tmp_stat_type); 9282 9283 entry_count = ini_entry_count + num_tgt; 9284 9285 rsp_data->entry_count = entry_count; 9286 9287 i = 0; 9288 if (flags & QLA2XX_HW_ERROR) { 9289 rsp_data->entry[i].stat_type = QLA2XX_HW_ERROR; 9290 rsp_data->entry[i].tgt_num = 0x0; 9291 rsp_data->entry[i].cnt = vha->hw_err_cnt; 9292 i++; 9293 } 9294 9295 if (flags & QLA2XX_SHT_LNK_DWN) { 9296 rsp_data->entry[i].stat_type = QLA2XX_SHT_LNK_DWN; 9297 rsp_data->entry[i].tgt_num = 0x0; 9298 rsp_data->entry[i].cnt = vha->short_link_down_cnt; 9299 i++; 9300 } 9301 9302 if (flags & QLA2XX_INT_ERR) { 9303 rsp_data->entry[i].stat_type = QLA2XX_INT_ERR; 9304 rsp_data->entry[i].tgt_num = 0x0; 9305 rsp_data->entry[i].cnt = vha->interface_err_cnt; 9306 i++; 9307 } 9308 9309 if (flags & QLA2XX_CMD_TIMEOUT) { 9310 rsp_data->entry[i].stat_type = QLA2XX_CMD_TIMEOUT; 9311 rsp_data->entry[i].tgt_num = 0x0; 9312 rsp_data->entry[i].cnt = vha->cmd_timeout_cnt; 9313 i++; 9314 } 9315 9316 if (flags & QLA2XX_RESET_CMD_ERR) { 9317 rsp_data->entry[i].stat_type = QLA2XX_RESET_CMD_ERR; 9318 rsp_data->entry[i].tgt_num = 0x0; 9319 rsp_data->entry[i].cnt = vha->reset_cmd_err_cnt; 9320 i++; 9321 } 9322 9323 /* i will continue from previous loop, as target 9324 * entries are after initiator 9325 */ 9326 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) { 9327 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags); 9328 list_for_each_entry(fcport, &vha->vp_fcports, list) { 9329 if (fcport->port_type != FCT_TARGET) 9330 continue; 9331 if (!fcport->rport) 9332 continue; 9333 rsp_data->entry[i].stat_type = QLA2XX_TGT_SHT_LNK_DOWN; 9334 rsp_data->entry[i].tgt_num = fcport->rport->number; 9335 rsp_data->entry[i].cnt = fcport->tgt_short_link_down_cnt; 9336 i++; 9337 } 9338 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags); 9339 } 9340 resp->status = EXT_STATUS_OK; 9341 9342 return 0; 9343 } 9344 9345 int qla2xxx_get_tgt_stats(struct Scsi_Host *host, u32 flags, 9346 struct fc_rport *rport, void *data, u64 size) 9347 { 9348 struct ql_vnd_tgt_stats_resp *tgt_data = data; 9349 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 9350 9351 tgt_data->status = 0; 9352 tgt_data->stats.entry_count = 1; 9353 tgt_data->stats.entry[0].stat_type = flags; 9354 tgt_data->stats.entry[0].tgt_num = rport->number; 9355 tgt_data->stats.entry[0].cnt = fcport->tgt_short_link_down_cnt; 9356 9357 return 0; 9358 } 9359 9360 int qla2xxx_disable_port(struct Scsi_Host *host) 9361 { 9362 scsi_qla_host_t *vha = shost_priv(host); 9363 9364 vha->hw->flags.port_isolated = 1; 9365 9366 if (qla2x00_chip_is_down(vha)) 9367 return 0; 9368 9369 if (vha->flags.online) { 9370 qla2x00_abort_isp_cleanup(vha); 9371 qla2x00_wait_for_sess_deletion(vha); 9372 } 9373 9374 return 0; 9375 } 9376 9377 int qla2xxx_enable_port(struct Scsi_Host *host) 9378 { 9379 scsi_qla_host_t *vha = shost_priv(host); 9380 9381 vha->hw->flags.port_isolated = 0; 9382 /* Set the flag to 1, so that isp_abort can proceed */ 9383 vha->flags.online = 1; 9384 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 9385 qla2xxx_wake_dpc(vha); 9386 9387 return 0; 9388 } 9389