1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_FW_H 8 #define __QLA_FW_H 9 10 #include <linux/nvme.h> 11 #include <linux/nvme-fc.h> 12 13 #include "qla_dsd.h" 14 15 #define MBS_CHECKSUM_ERROR 0x4010 16 #define MBS_INVALID_PRODUCT_KEY 0x4020 17 18 /* 19 * Firmware Options. 20 */ 21 #define FO1_ENABLE_PUREX BIT_10 22 #define FO1_DISABLE_LED_CTRL BIT_6 23 #define FO1_ENABLE_8016 BIT_0 24 #define FO2_ENABLE_SEL_CLASS2 BIT_5 25 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14 26 #define FO3_HOLD_STS_IOCB BIT_12 27 28 /* 29 * Port Database structure definition for ISP 24xx. 30 */ 31 #define PDO_FORCE_ADISC BIT_1 32 #define PDO_FORCE_PLOGI BIT_0 33 34 struct buffer_credit_24xx { 35 u32 parameter[28]; 36 }; 37 38 #define PORT_DATABASE_24XX_SIZE 64 39 struct port_database_24xx { 40 uint16_t flags; 41 #define PDF_TASK_RETRY_ID BIT_14 42 #define PDF_FC_TAPE BIT_7 43 #define PDF_ACK0_CAPABLE BIT_6 44 #define PDF_FCP2_CONF BIT_5 45 #define PDF_CLASS_2 BIT_4 46 #define PDF_HARD_ADDR BIT_1 47 48 /* 49 * for NVMe, the login_state field has been 50 * split into nibbles. 51 * The lower nibble is for FCP. 52 * The upper nibble is for NVMe. 53 */ 54 uint8_t current_login_state; 55 uint8_t last_login_state; 56 #define PDS_PLOGI_PENDING 0x03 57 #define PDS_PLOGI_COMPLETE 0x04 58 #define PDS_PRLI_PENDING 0x05 59 #define PDS_PRLI_COMPLETE 0x06 60 #define PDS_PORT_UNAVAILABLE 0x07 61 #define PDS_PRLO_PENDING 0x09 62 #define PDS_LOGO_PENDING 0x11 63 #define PDS_PRLI2_PENDING 0x12 64 65 uint8_t hard_address[3]; 66 uint8_t reserved_1; 67 68 uint8_t port_id[3]; 69 uint8_t sequence_id; 70 71 uint16_t port_timer; 72 73 uint16_t nport_handle; /* N_PORT handle. */ 74 75 uint16_t receive_data_size; 76 uint16_t reserved_2; 77 78 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 79 /* Bits 15-0 of word 0 */ 80 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 81 /* Bits 15-0 of word 3 */ 82 83 uint8_t port_name[WWN_SIZE]; 84 uint8_t node_name[WWN_SIZE]; 85 86 uint8_t reserved_3[4]; 87 uint16_t prli_nvme_svc_param_word_0; /* Bits 15-0 of word 0 */ 88 uint16_t prli_nvme_svc_param_word_3; /* Bits 15-0 of word 3 */ 89 uint16_t nvme_first_burst_size; 90 uint8_t reserved_4[14]; 91 }; 92 93 /* 94 * MB 75h returns a list of DB entries similar to port_database_24xx(64B). 95 * However, in this case it returns 1st 40 bytes. 96 */ 97 struct get_name_list_extended { 98 __le16 flags; 99 u8 current_login_state; 100 u8 last_login_state; 101 u8 hard_address[3]; 102 u8 reserved_1; 103 u8 port_id[3]; 104 u8 sequence_id; 105 __le16 port_timer; 106 __le16 nport_handle; /* N_PORT handle. */ 107 __le16 receive_data_size; 108 __le16 reserved_2; 109 110 /* PRLI SVC Param are Big endian */ 111 u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */ 112 u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */ 113 u8 port_name[WWN_SIZE]; 114 u8 node_name[WWN_SIZE]; 115 }; 116 117 /* MB 75h: This is the short version of the database */ 118 struct get_name_list { 119 u8 port_node_name[WWN_SIZE]; /* B7 most sig, B0 least sig */ 120 __le16 nport_handle; 121 u8 reserved; 122 }; 123 124 struct vp_database_24xx { 125 uint16_t vp_status; 126 uint8_t options; 127 uint8_t id; 128 uint8_t port_name[WWN_SIZE]; 129 uint8_t node_name[WWN_SIZE]; 130 uint16_t port_id_low; 131 uint16_t port_id_high; 132 }; 133 134 struct nvram_24xx { 135 /* NVRAM header. */ 136 uint8_t id[4]; 137 uint16_t nvram_version; 138 uint16_t reserved_0; 139 140 /* Firmware Initialization Control Block. */ 141 uint16_t version; 142 uint16_t reserved_1; 143 __le16 frame_payload_size; 144 uint16_t execution_throttle; 145 uint16_t exchange_count; 146 uint16_t hard_address; 147 148 uint8_t port_name[WWN_SIZE]; 149 uint8_t node_name[WWN_SIZE]; 150 151 uint16_t login_retry_count; 152 uint16_t link_down_on_nos; 153 uint16_t interrupt_delay_timer; 154 uint16_t login_timeout; 155 156 uint32_t firmware_options_1; 157 uint32_t firmware_options_2; 158 uint32_t firmware_options_3; 159 160 /* Offset 56. */ 161 162 /* 163 * BIT 0 = Control Enable 164 * BIT 1-15 = 165 * 166 * BIT 0-7 = Reserved 167 * BIT 8-10 = Output Swing 1G 168 * BIT 11-13 = Output Emphasis 1G 169 * BIT 14-15 = Reserved 170 * 171 * BIT 0-7 = Reserved 172 * BIT 8-10 = Output Swing 2G 173 * BIT 11-13 = Output Emphasis 2G 174 * BIT 14-15 = Reserved 175 * 176 * BIT 0-7 = Reserved 177 * BIT 8-10 = Output Swing 4G 178 * BIT 11-13 = Output Emphasis 4G 179 * BIT 14-15 = Reserved 180 */ 181 uint16_t seriallink_options[4]; 182 183 uint16_t reserved_2[16]; 184 185 /* Offset 96. */ 186 uint16_t reserved_3[16]; 187 188 /* PCIe table entries. */ 189 uint16_t reserved_4[16]; 190 191 /* Offset 160. */ 192 uint16_t reserved_5[16]; 193 194 /* Offset 192. */ 195 uint16_t reserved_6[16]; 196 197 /* Offset 224. */ 198 uint16_t reserved_7[16]; 199 200 /* 201 * BIT 0 = Enable spinup delay 202 * BIT 1 = Disable BIOS 203 * BIT 2 = Enable Memory Map BIOS 204 * BIT 3 = Enable Selectable Boot 205 * BIT 4 = Disable RISC code load 206 * BIT 5 = Disable Serdes 207 * BIT 6 = 208 * BIT 7 = 209 * 210 * BIT 8 = 211 * BIT 9 = 212 * BIT 10 = Enable lip full login 213 * BIT 11 = Enable target reset 214 * BIT 12 = 215 * BIT 13 = 216 * BIT 14 = 217 * BIT 15 = Enable alternate WWN 218 * 219 * BIT 16-31 = 220 */ 221 uint32_t host_p; 222 223 uint8_t alternate_port_name[WWN_SIZE]; 224 uint8_t alternate_node_name[WWN_SIZE]; 225 226 uint8_t boot_port_name[WWN_SIZE]; 227 uint16_t boot_lun_number; 228 uint16_t reserved_8; 229 230 uint8_t alt1_boot_port_name[WWN_SIZE]; 231 uint16_t alt1_boot_lun_number; 232 uint16_t reserved_9; 233 234 uint8_t alt2_boot_port_name[WWN_SIZE]; 235 uint16_t alt2_boot_lun_number; 236 uint16_t reserved_10; 237 238 uint8_t alt3_boot_port_name[WWN_SIZE]; 239 uint16_t alt3_boot_lun_number; 240 uint16_t reserved_11; 241 242 /* 243 * BIT 0 = Selective Login 244 * BIT 1 = Alt-Boot Enable 245 * BIT 2 = Reserved 246 * BIT 3 = Boot Order List 247 * BIT 4 = Reserved 248 * BIT 5 = Selective LUN 249 * BIT 6 = Reserved 250 * BIT 7-31 = 251 */ 252 uint32_t efi_parameters; 253 254 uint8_t reset_delay; 255 uint8_t reserved_12; 256 uint16_t reserved_13; 257 258 uint16_t boot_id_number; 259 uint16_t reserved_14; 260 261 uint16_t max_luns_per_target; 262 uint16_t reserved_15; 263 264 uint16_t port_down_retry_count; 265 uint16_t link_down_timeout; 266 267 /* FCode parameters. */ 268 uint16_t fcode_parameter; 269 270 uint16_t reserved_16[3]; 271 272 /* Offset 352. */ 273 uint8_t prev_drv_ver_major; 274 uint8_t prev_drv_ver_submajob; 275 uint8_t prev_drv_ver_minor; 276 uint8_t prev_drv_ver_subminor; 277 278 uint16_t prev_bios_ver_major; 279 uint16_t prev_bios_ver_minor; 280 281 uint16_t prev_efi_ver_major; 282 uint16_t prev_efi_ver_minor; 283 284 uint16_t prev_fw_ver_major; 285 uint8_t prev_fw_ver_minor; 286 uint8_t prev_fw_ver_subminor; 287 288 uint16_t reserved_17[8]; 289 290 /* Offset 384. */ 291 uint16_t reserved_18[16]; 292 293 /* Offset 416. */ 294 uint16_t reserved_19[16]; 295 296 /* Offset 448. */ 297 uint16_t reserved_20[16]; 298 299 /* Offset 480. */ 300 uint8_t model_name[16]; 301 302 uint16_t reserved_21[2]; 303 304 /* Offset 500. */ 305 /* HW Parameter Block. */ 306 uint16_t pcie_table_sig; 307 uint16_t pcie_table_offset; 308 309 uint16_t subsystem_vendor_id; 310 uint16_t subsystem_device_id; 311 312 uint32_t checksum; 313 }; 314 315 /* 316 * ISP Initialization Control Block. 317 * Little endian except where noted. 318 */ 319 #define ICB_VERSION 1 320 struct init_cb_24xx { 321 uint16_t version; 322 uint16_t reserved_1; 323 324 uint16_t frame_payload_size; 325 uint16_t execution_throttle; 326 uint16_t exchange_count; 327 328 uint16_t hard_address; 329 330 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 331 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 332 333 uint16_t response_q_inpointer; 334 uint16_t request_q_outpointer; 335 336 uint16_t login_retry_count; 337 338 uint16_t prio_request_q_outpointer; 339 340 uint16_t response_q_length; 341 uint16_t request_q_length; 342 343 uint16_t link_down_on_nos; /* Milliseconds. */ 344 345 uint16_t prio_request_q_length; 346 347 __le64 request_q_address __packed; 348 __le64 response_q_address __packed; 349 __le64 prio_request_q_address __packed; 350 351 uint16_t msix; 352 uint16_t msix_atio; 353 uint8_t reserved_2[4]; 354 355 uint16_t atio_q_inpointer; 356 uint16_t atio_q_length; 357 __le64 atio_q_address __packed; 358 359 uint16_t interrupt_delay_timer; /* 100us increments. */ 360 uint16_t login_timeout; 361 362 /* 363 * BIT 0 = Enable Hard Loop Id 364 * BIT 1 = Enable Fairness 365 * BIT 2 = Enable Full-Duplex 366 * BIT 3 = Reserved 367 * BIT 4 = Enable Target Mode 368 * BIT 5 = Disable Initiator Mode 369 * BIT 6 = Acquire FA-WWN 370 * BIT 7 = Enable D-port Diagnostics 371 * 372 * BIT 8 = Reserved 373 * BIT 9 = Non Participating LIP 374 * BIT 10 = Descending Loop ID Search 375 * BIT 11 = Acquire Loop ID in LIPA 376 * BIT 12 = Reserved 377 * BIT 13 = Full Login after LIP 378 * BIT 14 = Node Name Option 379 * BIT 15-31 = Reserved 380 */ 381 uint32_t firmware_options_1; 382 383 /* 384 * BIT 0 = Operation Mode bit 0 385 * BIT 1 = Operation Mode bit 1 386 * BIT 2 = Operation Mode bit 2 387 * BIT 3 = Operation Mode bit 3 388 * BIT 4 = Connection Options bit 0 389 * BIT 5 = Connection Options bit 1 390 * BIT 6 = Connection Options bit 2 391 * BIT 7 = Enable Non part on LIHA failure 392 * 393 * BIT 8 = Enable Class 2 394 * BIT 9 = Enable ACK0 395 * BIT 10 = Reserved 396 * BIT 11 = Enable FC-SP Security 397 * BIT 12 = FC Tape Enable 398 * BIT 13 = Reserved 399 * BIT 14 = Enable Target PRLI Control 400 * BIT 15-31 = Reserved 401 */ 402 uint32_t firmware_options_2; 403 404 /* 405 * BIT 0 = Reserved 406 * BIT 1 = Soft ID only 407 * BIT 2 = Reserved 408 * BIT 3 = Reserved 409 * BIT 4 = FCP RSP Payload bit 0 410 * BIT 5 = FCP RSP Payload bit 1 411 * BIT 6 = Enable Receive Out-of-Order data frame handling 412 * BIT 7 = Disable Automatic PLOGI on Local Loop 413 * 414 * BIT 8 = Reserved 415 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 416 * BIT 10 = Reserved 417 * BIT 11 = Reserved 418 * BIT 12 = Reserved 419 * BIT 13 = Data Rate bit 0 420 * BIT 14 = Data Rate bit 1 421 * BIT 15 = Data Rate bit 2 422 * BIT 16 = Enable 75 ohm Termination Select 423 * BIT 17-28 = Reserved 424 * BIT 29 = Enable response queue 0 in index shadowing 425 * BIT 30 = Enable request queue 0 out index shadowing 426 * BIT 31 = Reserved 427 */ 428 uint32_t firmware_options_3; 429 uint16_t qos; 430 uint16_t rid; 431 uint8_t reserved_3[20]; 432 }; 433 434 /* 435 * ISP queue - command entry structure definition. 436 */ 437 #define COMMAND_BIDIRECTIONAL 0x75 438 struct cmd_bidir { 439 uint8_t entry_type; /* Entry type. */ 440 uint8_t entry_count; /* Entry count. */ 441 uint8_t sys_define; /* System defined */ 442 uint8_t entry_status; /* Entry status. */ 443 444 uint32_t handle; /* System handle. */ 445 446 uint16_t nport_handle; /* N_PORT hanlde. */ 447 448 uint16_t timeout; /* Commnad timeout. */ 449 450 uint16_t wr_dseg_count; /* Write Data segment count. */ 451 uint16_t rd_dseg_count; /* Read Data segment count. */ 452 453 struct scsi_lun lun; /* FCP LUN (BE). */ 454 455 uint16_t control_flags; /* Control flags. */ 456 #define BD_WRAP_BACK BIT_3 457 #define BD_READ_DATA BIT_1 458 #define BD_WRITE_DATA BIT_0 459 460 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 461 __le64 fcp_cmnd_dseg_address __packed;/* Data segment address. */ 462 463 uint16_t reserved[2]; /* Reserved */ 464 465 uint32_t rd_byte_count; /* Total Byte count Read. */ 466 uint32_t wr_byte_count; /* Total Byte count write. */ 467 468 uint8_t port_id[3]; /* PortID of destination port.*/ 469 uint8_t vp_index; 470 471 struct dsd64 fcp_dsd; 472 }; 473 474 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */ 475 struct cmd_type_6 { 476 uint8_t entry_type; /* Entry type. */ 477 uint8_t entry_count; /* Entry count. */ 478 uint8_t sys_define; /* System defined. */ 479 uint8_t entry_status; /* Entry Status. */ 480 481 uint32_t handle; /* System handle. */ 482 483 uint16_t nport_handle; /* N_PORT handle. */ 484 uint16_t timeout; /* Command timeout. */ 485 486 uint16_t dseg_count; /* Data segment count. */ 487 488 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */ 489 490 struct scsi_lun lun; /* FCP LUN (BE). */ 491 492 uint16_t control_flags; /* Control flags. */ 493 #define CF_DIF_SEG_DESCR_ENABLE BIT_3 494 #define CF_DATA_SEG_DESCR_ENABLE BIT_2 495 #define CF_READ_DATA BIT_1 496 #define CF_WRITE_DATA BIT_0 497 498 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 499 /* Data segment address. */ 500 __le64 fcp_cmnd_dseg_address __packed; 501 /* Data segment address. */ 502 __le64 fcp_rsp_dseg_address __packed; 503 504 uint32_t byte_count; /* Total byte count. */ 505 506 uint8_t port_id[3]; /* PortID of destination port. */ 507 uint8_t vp_index; 508 509 struct dsd64 fcp_dsd; 510 }; 511 512 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */ 513 struct cmd_type_7 { 514 uint8_t entry_type; /* Entry type. */ 515 uint8_t entry_count; /* Entry count. */ 516 uint8_t sys_define; /* System defined. */ 517 uint8_t entry_status; /* Entry Status. */ 518 519 uint32_t handle; /* System handle. */ 520 521 uint16_t nport_handle; /* N_PORT handle. */ 522 uint16_t timeout; /* Command timeout. */ 523 #define FW_MAX_TIMEOUT 0x1999 524 525 uint16_t dseg_count; /* Data segment count. */ 526 uint16_t reserved_1; 527 528 struct scsi_lun lun; /* FCP LUN (BE). */ 529 530 uint16_t task_mgmt_flags; /* Task management flags. */ 531 #define TMF_CLEAR_ACA BIT_14 532 #define TMF_TARGET_RESET BIT_13 533 #define TMF_LUN_RESET BIT_12 534 #define TMF_CLEAR_TASK_SET BIT_10 535 #define TMF_ABORT_TASK_SET BIT_9 536 #define TMF_DSD_LIST_ENABLE BIT_2 537 #define TMF_READ_DATA BIT_1 538 #define TMF_WRITE_DATA BIT_0 539 540 uint8_t task; 541 #define TSK_SIMPLE 0 542 #define TSK_HEAD_OF_QUEUE 1 543 #define TSK_ORDERED 2 544 #define TSK_ACA 4 545 #define TSK_UNTAGGED 5 546 547 uint8_t crn; 548 549 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ 550 uint32_t byte_count; /* Total byte count. */ 551 552 uint8_t port_id[3]; /* PortID of destination port. */ 553 uint8_t vp_index; 554 555 struct dsd64 dsd; 556 }; 557 558 #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6) 559 * (T10-DIF) */ 560 struct cmd_type_crc_2 { 561 uint8_t entry_type; /* Entry type. */ 562 uint8_t entry_count; /* Entry count. */ 563 uint8_t sys_define; /* System defined. */ 564 uint8_t entry_status; /* Entry Status. */ 565 566 uint32_t handle; /* System handle. */ 567 568 uint16_t nport_handle; /* N_PORT handle. */ 569 uint16_t timeout; /* Command timeout. */ 570 571 uint16_t dseg_count; /* Data segment count. */ 572 573 uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */ 574 575 struct scsi_lun lun; /* FCP LUN (BE). */ 576 577 uint16_t control_flags; /* Control flags. */ 578 579 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 580 __le64 fcp_cmnd_dseg_address __packed; 581 /* Data segment address. */ 582 __le64 fcp_rsp_dseg_address __packed; 583 584 uint32_t byte_count; /* Total byte count. */ 585 586 uint8_t port_id[3]; /* PortID of destination port. */ 587 uint8_t vp_index; 588 589 __le64 crc_context_address __packed; /* Data segment address. */ 590 uint16_t crc_context_len; /* Data segment length. */ 591 uint16_t reserved_1; /* MUST be set to 0. */ 592 }; 593 594 595 /* 596 * ISP queue - status entry structure definition. 597 */ 598 #define STATUS_TYPE 0x03 /* Status entry. */ 599 struct sts_entry_24xx { 600 uint8_t entry_type; /* Entry type. */ 601 uint8_t entry_count; /* Entry count. */ 602 uint8_t sys_define; /* System defined. */ 603 uint8_t entry_status; /* Entry Status. */ 604 605 uint32_t handle; /* System handle. */ 606 607 uint16_t comp_status; /* Completion status. */ 608 uint16_t ox_id; /* OX_ID used by the firmware. */ 609 610 uint32_t residual_len; /* FW calc residual transfer length. */ 611 612 union { 613 uint16_t reserved_1; 614 uint16_t nvme_rsp_pyld_len; 615 }; 616 617 uint16_t state_flags; /* State flags. */ 618 #define SF_TRANSFERRED_DATA BIT_11 619 #define SF_NVME_ERSP BIT_6 620 #define SF_FCP_RSP_DMA BIT_0 621 622 uint16_t retry_delay; 623 uint16_t scsi_status; /* SCSI status. */ 624 #define SS_CONFIRMATION_REQ BIT_12 625 626 uint32_t rsp_residual_count; /* FCP RSP residual count. */ 627 628 uint32_t sense_len; /* FCP SENSE length. */ 629 630 union { 631 struct { 632 uint32_t rsp_data_len; /* FCP response data length */ 633 uint8_t data[28]; /* FCP rsp/sense information */ 634 }; 635 struct nvme_fc_ersp_iu nvme_ersp; 636 uint8_t nvme_ersp_data[32]; 637 }; 638 639 /* 640 * If DIF Error is set in comp_status, these additional fields are 641 * defined: 642 * 643 * !!! NOTE: Firmware sends expected/actual DIF data in big endian 644 * format; but all of the "data" field gets swab32-d in the beginning 645 * of qla2x00_status_entry(). 646 * 647 * &data[10] : uint8_t report_runt_bg[2]; - computed guard 648 * &data[12] : uint8_t actual_dif[8]; - DIF Data received 649 * &data[20] : uint8_t expected_dif[8]; - DIF Data computed 650 */ 651 }; 652 653 654 /* 655 * Status entry completion status 656 */ 657 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */ 658 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */ 659 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */ 660 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */ 661 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */ 662 663 /* 664 * ISP queue - marker entry structure definition. 665 */ 666 #define MARKER_TYPE 0x04 /* Marker entry. */ 667 struct mrk_entry_24xx { 668 uint8_t entry_type; /* Entry type. */ 669 uint8_t entry_count; /* Entry count. */ 670 uint8_t handle_count; /* Handle count. */ 671 uint8_t entry_status; /* Entry Status. */ 672 673 uint32_t handle; /* System handle. */ 674 675 uint16_t nport_handle; /* N_PORT handle. */ 676 677 uint8_t modifier; /* Modifier (7-0). */ 678 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 679 #define MK_SYNC_ID 1 /* Synchronize ID */ 680 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 681 uint8_t reserved_1; 682 683 uint8_t reserved_2; 684 uint8_t vp_index; 685 686 uint16_t reserved_3; 687 688 uint8_t lun[8]; /* FCP LUN (BE). */ 689 uint8_t reserved_4[40]; 690 }; 691 692 /* 693 * ISP queue - CT Pass-Through entry structure definition. 694 */ 695 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */ 696 struct ct_entry_24xx { 697 uint8_t entry_type; /* Entry type. */ 698 uint8_t entry_count; /* Entry count. */ 699 uint8_t sys_define; /* System Defined. */ 700 uint8_t entry_status; /* Entry Status. */ 701 702 uint32_t handle; /* System handle. */ 703 704 uint16_t comp_status; /* Completion status. */ 705 706 uint16_t nport_handle; /* N_PORT handle. */ 707 708 uint16_t cmd_dsd_count; 709 710 uint8_t vp_index; 711 uint8_t reserved_1; 712 713 uint16_t timeout; /* Command timeout. */ 714 uint16_t reserved_2; 715 716 uint16_t rsp_dsd_count; 717 718 uint8_t reserved_3[10]; 719 720 uint32_t rsp_byte_count; 721 uint32_t cmd_byte_count; 722 723 struct dsd64 dsd[2]; 724 }; 725 726 /* 727 * ISP queue - PUREX IOCB entry structure definition 728 */ 729 #define PUREX_IOCB_TYPE 0x51 /* CT Pass Through IOCB entry */ 730 struct purex_entry_24xx { 731 uint8_t entry_type; /* Entry type. */ 732 uint8_t entry_count; /* Entry count. */ 733 uint8_t sys_define; /* System defined. */ 734 uint8_t entry_status; /* Entry Status. */ 735 736 uint16_t reserved1; 737 uint8_t vp_idx; 738 uint8_t reserved2; 739 740 uint16_t status_flags; 741 uint16_t nport_handle; 742 743 uint16_t frame_size; 744 uint16_t trunc_frame_size; 745 746 uint32_t rx_xchg_addr; 747 748 uint8_t d_id[3]; 749 uint8_t r_ctl; 750 751 uint8_t s_id[3]; 752 uint8_t cs_ctl; 753 754 uint8_t f_ctl[3]; 755 uint8_t type; 756 757 uint16_t seq_cnt; 758 uint8_t df_ctl; 759 uint8_t seq_id; 760 761 uint16_t rx_id; 762 uint16_t ox_id; 763 uint32_t param; 764 765 uint8_t els_frame_payload[20]; 766 }; 767 768 /* 769 * ISP queue - ELS Pass-Through entry structure definition. 770 */ 771 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */ 772 struct els_entry_24xx { 773 uint8_t entry_type; /* Entry type. */ 774 uint8_t entry_count; /* Entry count. */ 775 uint8_t sys_define; /* System Defined. */ 776 uint8_t entry_status; /* Entry Status. */ 777 778 uint32_t handle; /* System handle. */ 779 780 uint16_t comp_status; /* response only */ 781 uint16_t nport_handle; 782 783 uint16_t tx_dsd_count; 784 785 uint8_t vp_index; 786 uint8_t sof_type; 787 #define EST_SOFI3 (1 << 4) 788 #define EST_SOFI2 (3 << 4) 789 790 uint32_t rx_xchg_address; /* Receive exchange address. */ 791 uint16_t rx_dsd_count; 792 793 uint8_t opcode; 794 uint8_t reserved_2; 795 796 uint8_t d_id[3]; 797 uint8_t s_id[3]; 798 799 uint16_t control_flags; /* Control flags. */ 800 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13) 801 #define EPD_ELS_COMMAND (0 << 13) 802 #define EPD_ELS_ACC (1 << 13) 803 #define EPD_ELS_RJT (2 << 13) 804 #define EPD_RX_XCHG (3 << 13) 805 #define ECF_CLR_PASSTHRU_PEND BIT_12 806 #define ECF_INCL_FRAME_HDR BIT_11 807 808 union { 809 struct { 810 __le32 rx_byte_count; 811 __le32 tx_byte_count; 812 813 __le64 tx_address __packed; /* DSD 0 address. */ 814 __le32 tx_len; /* DSD 0 length. */ 815 816 __le64 rx_address __packed; /* DSD 1 address. */ 817 __le32 rx_len; /* DSD 1 length. */ 818 }; 819 struct { 820 uint32_t total_byte_count; 821 uint32_t error_subcode_1; 822 uint32_t error_subcode_2; 823 uint32_t error_subcode_3; 824 }; 825 }; 826 }; 827 828 struct els_sts_entry_24xx { 829 uint8_t entry_type; /* Entry type. */ 830 uint8_t entry_count; /* Entry count. */ 831 uint8_t sys_define; /* System Defined. */ 832 uint8_t entry_status; /* Entry Status. */ 833 834 uint32_t handle; /* System handle. */ 835 836 uint16_t comp_status; 837 838 uint16_t nport_handle; /* N_PORT handle. */ 839 840 uint16_t reserved_1; 841 842 uint8_t vp_index; 843 uint8_t sof_type; 844 845 uint32_t rx_xchg_address; /* Receive exchange address. */ 846 uint16_t reserved_2; 847 848 uint8_t opcode; 849 uint8_t reserved_3; 850 851 uint8_t d_id[3]; 852 uint8_t s_id[3]; 853 854 uint16_t control_flags; /* Control flags. */ 855 uint32_t total_byte_count; 856 uint32_t error_subcode_1; 857 uint32_t error_subcode_2; 858 uint32_t error_subcode_3; 859 860 uint32_t reserved_4[4]; 861 }; 862 /* 863 * ISP queue - Mailbox Command entry structure definition. 864 */ 865 #define MBX_IOCB_TYPE 0x39 866 struct mbx_entry_24xx { 867 uint8_t entry_type; /* Entry type. */ 868 uint8_t entry_count; /* Entry count. */ 869 uint8_t handle_count; /* Handle count. */ 870 uint8_t entry_status; /* Entry Status. */ 871 872 uint32_t handle; /* System handle. */ 873 874 uint16_t mbx[28]; 875 }; 876 877 878 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */ 879 struct logio_entry_24xx { 880 uint8_t entry_type; /* Entry type. */ 881 uint8_t entry_count; /* Entry count. */ 882 uint8_t sys_define; /* System defined. */ 883 uint8_t entry_status; /* Entry Status. */ 884 885 uint32_t handle; /* System handle. */ 886 887 uint16_t comp_status; /* Completion status. */ 888 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */ 889 890 uint16_t nport_handle; /* N_PORT handle. */ 891 892 uint16_t control_flags; /* Control flags. */ 893 /* Modifiers. */ 894 #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ 895 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ 896 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ 897 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ 898 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */ 899 #define LCF_NVME_PRLI BIT_6 /* Perform NVME FC4 PRLI */ 900 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */ 901 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */ 902 #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */ 903 #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */ 904 #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */ 905 /* Commands. */ 906 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */ 907 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */ 908 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */ 909 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */ 910 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */ 911 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */ 912 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */ 913 914 uint8_t vp_index; 915 uint8_t reserved_1; 916 917 uint8_t port_id[3]; /* PortID of destination port. */ 918 919 uint8_t rsp_size; /* Response size in 32bit words. */ 920 921 uint32_t io_parameter[11]; /* General I/O parameters. */ 922 #define LSC_SCODE_NOLINK 0x01 923 #define LSC_SCODE_NOIOCB 0x02 924 #define LSC_SCODE_NOXCB 0x03 925 #define LSC_SCODE_CMD_FAILED 0x04 926 #define LSC_SCODE_NOFABRIC 0x05 927 #define LSC_SCODE_FW_NOT_READY 0x07 928 #define LSC_SCODE_NOT_LOGGED_IN 0x09 929 #define LSC_SCODE_NOPCB 0x0A 930 931 #define LSC_SCODE_ELS_REJECT 0x18 932 #define LSC_SCODE_CMD_PARAM_ERR 0x19 933 #define LSC_SCODE_PORTID_USED 0x1A 934 #define LSC_SCODE_NPORT_USED 0x1B 935 #define LSC_SCODE_NONPORT 0x1C 936 #define LSC_SCODE_LOGGED_IN 0x1D 937 #define LSC_SCODE_NOFLOGI_ACC 0x1F 938 }; 939 940 #define TSK_MGMT_IOCB_TYPE 0x14 941 struct tsk_mgmt_entry { 942 uint8_t entry_type; /* Entry type. */ 943 uint8_t entry_count; /* Entry count. */ 944 uint8_t handle_count; /* Handle count. */ 945 uint8_t entry_status; /* Entry Status. */ 946 947 uint32_t handle; /* System handle. */ 948 949 uint16_t nport_handle; /* N_PORT handle. */ 950 951 uint16_t reserved_1; 952 953 uint16_t delay; /* Activity delay in seconds. */ 954 955 uint16_t timeout; /* Command timeout. */ 956 957 struct scsi_lun lun; /* FCP LUN (BE). */ 958 959 uint32_t control_flags; /* Control Flags. */ 960 #define TCF_NOTMCMD_TO_TARGET BIT_31 961 #define TCF_LUN_RESET BIT_4 962 #define TCF_ABORT_TASK_SET BIT_3 963 #define TCF_CLEAR_TASK_SET BIT_2 964 #define TCF_TARGET_RESET BIT_1 965 #define TCF_CLEAR_ACA BIT_0 966 967 uint8_t reserved_2[20]; 968 969 uint8_t port_id[3]; /* PortID of destination port. */ 970 uint8_t vp_index; 971 972 uint8_t reserved_3[12]; 973 }; 974 975 #define ABORT_IOCB_TYPE 0x33 976 struct abort_entry_24xx { 977 uint8_t entry_type; /* Entry type. */ 978 uint8_t entry_count; /* Entry count. */ 979 uint8_t handle_count; /* Handle count. */ 980 uint8_t entry_status; /* Entry Status. */ 981 982 uint32_t handle; /* System handle. */ 983 984 uint16_t nport_handle; /* N_PORT handle. */ 985 /* or Completion status. */ 986 987 uint16_t options; /* Options. */ 988 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ 989 990 uint32_t handle_to_abort; /* System handle to abort. */ 991 992 uint16_t req_que_no; 993 uint8_t reserved_1[30]; 994 995 uint8_t port_id[3]; /* PortID of destination port. */ 996 uint8_t vp_index; 997 998 uint8_t reserved_2[12]; 999 }; 1000 1001 #define ABTS_RCV_TYPE 0x54 1002 #define ABTS_RSP_TYPE 0x55 1003 struct abts_entry_24xx { 1004 uint8_t entry_type; 1005 uint8_t entry_count; 1006 uint8_t handle_count; 1007 uint8_t entry_status; 1008 1009 uint32_t handle; /* type 0x55 only */ 1010 1011 uint16_t comp_status; /* type 0x55 only */ 1012 uint16_t nport_handle; /* type 0x54 only */ 1013 1014 uint16_t control_flags; /* type 0x55 only */ 1015 uint8_t vp_idx; 1016 uint8_t sof_type; /* sof_type is upper nibble */ 1017 1018 uint32_t rx_xch_addr; 1019 1020 uint8_t d_id[3]; 1021 uint8_t r_ctl; 1022 1023 uint8_t s_id[3]; 1024 uint8_t cs_ctl; 1025 1026 uint8_t f_ctl[3]; 1027 uint8_t type; 1028 1029 uint16_t seq_cnt; 1030 uint8_t df_ctl; 1031 uint8_t seq_id; 1032 1033 uint16_t rx_id; 1034 uint16_t ox_id; 1035 1036 uint32_t param; 1037 1038 union { 1039 struct { 1040 uint32_t subcode3; 1041 uint32_t rsvd; 1042 uint32_t subcode1; 1043 uint32_t subcode2; 1044 } error; 1045 struct { 1046 uint16_t rsrvd1; 1047 uint8_t last_seq_id; 1048 uint8_t seq_id_valid; 1049 uint16_t aborted_rx_id; 1050 uint16_t aborted_ox_id; 1051 uint16_t high_seq_cnt; 1052 uint16_t low_seq_cnt; 1053 } ba_acc; 1054 struct { 1055 uint8_t vendor_unique; 1056 uint8_t explanation; 1057 uint8_t reason; 1058 } ba_rjt; 1059 } payload; 1060 1061 uint32_t rx_xch_addr_to_abort; 1062 } __packed; 1063 1064 /* ABTS payload explanation values */ 1065 #define BA_RJT_EXP_NO_ADDITIONAL 0 1066 #define BA_RJT_EXP_INV_OX_RX_ID 3 1067 #define BA_RJT_EXP_SEQ_ABORTED 5 1068 1069 /* ABTS payload reason values */ 1070 #define BA_RJT_RSN_INV_CMD_CODE 1 1071 #define BA_RJT_RSN_LOGICAL_ERROR 3 1072 #define BA_RJT_RSN_LOGICAL_BUSY 5 1073 #define BA_RJT_RSN_PROTOCOL_ERROR 7 1074 #define BA_RJT_RSN_UNABLE_TO_PERFORM 9 1075 #define BA_RJT_RSN_VENDOR_SPECIFIC 0xff 1076 1077 /* FC_F values */ 1078 #define FC_TYPE_BLD 0x000 /* Basic link data */ 1079 #define FC_F_CTL_RSP_CNTXT 0x800000 /* Responder of exchange */ 1080 #define FC_F_CTL_LAST_SEQ 0x100000 /* Last sequence */ 1081 #define FC_F_CTL_END_SEQ 0x80000 /* Last sequence */ 1082 #define FC_F_CTL_SEQ_INIT 0x010000 /* Sequence initiative */ 1083 #define FC_ROUTING_BLD 0x80 /* Basic link data frame */ 1084 #define FC_R_CTL_BLD_BA_ACC 0x04 /* BA_ACC (basic accept) */ 1085 1086 /* 1087 * ISP I/O Register Set structure definitions. 1088 */ 1089 struct device_reg_24xx { 1090 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */ 1091 #define FARX_DATA_FLAG BIT_31 1092 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 1093 #define FARX_ACCESS_FLASH_DATA 0x7FF00000 1094 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000 1095 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000 1096 1097 #define FA_NVRAM_FUNC0_ADDR 0x80 1098 #define FA_NVRAM_FUNC1_ADDR 0x180 1099 1100 #define FA_NVRAM_VPD_SIZE 0x200 1101 #define FA_NVRAM_VPD0_ADDR 0x00 1102 #define FA_NVRAM_VPD1_ADDR 0x100 1103 1104 #define FA_BOOT_CODE_ADDR 0x00000 1105 /* 1106 * RISC code begins at offset 512KB 1107 * within flash. Consisting of two 1108 * contiguous RISC code segments. 1109 */ 1110 #define FA_RISC_CODE_ADDR 0x20000 1111 #define FA_RISC_CODE_SEGMENTS 2 1112 1113 #define FA_FLASH_DESCR_ADDR_24 0x11000 1114 #define FA_FLASH_LAYOUT_ADDR_24 0x11400 1115 #define FA_NPIV_CONF0_ADDR_24 0x16000 1116 #define FA_NPIV_CONF1_ADDR_24 0x17000 1117 1118 #define FA_FW_AREA_ADDR 0x40000 1119 #define FA_VPD_NVRAM_ADDR 0x48000 1120 #define FA_FEATURE_ADDR 0x4C000 1121 #define FA_FLASH_DESCR_ADDR 0x50000 1122 #define FA_FLASH_LAYOUT_ADDR 0x50400 1123 #define FA_HW_EVENT0_ADDR 0x54000 1124 #define FA_HW_EVENT1_ADDR 0x54400 1125 #define FA_HW_EVENT_SIZE 0x200 1126 #define FA_HW_EVENT_ENTRY_SIZE 4 1127 #define FA_NPIV_CONF0_ADDR 0x5C000 1128 #define FA_NPIV_CONF1_ADDR 0x5D000 1129 #define FA_FCP_PRIO0_ADDR 0x10000 1130 #define FA_FCP_PRIO1_ADDR 0x12000 1131 1132 /* 1133 * Flash Error Log Event Codes. 1134 */ 1135 #define HW_EVENT_RESET_ERR 0xF00B 1136 #define HW_EVENT_ISP_ERR 0xF020 1137 #define HW_EVENT_PARITY_ERR 0xF022 1138 #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023 1139 #define HW_EVENT_FLASH_FW_ERR 0xF024 1140 1141 uint32_t flash_data; /* Flash/NVRAM BIOS data. */ 1142 1143 uint32_t ctrl_status; /* Control/Status. */ 1144 #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */ 1145 #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */ 1146 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */ 1147 #define CSRX_FUNCTION BIT_15 /* Function number. */ 1148 /* PCI-X Bus Mode. */ 1149 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8) 1150 #define PBM_PCI_33MHZ (0 << 8) 1151 #define PBM_PCIX_M1_66MHZ (1 << 8) 1152 #define PBM_PCIX_M1_100MHZ (2 << 8) 1153 #define PBM_PCIX_M1_133MHZ (3 << 8) 1154 #define PBM_PCIX_M2_66MHZ (5 << 8) 1155 #define PBM_PCIX_M2_100MHZ (6 << 8) 1156 #define PBM_PCIX_M2_133MHZ (7 << 8) 1157 #define PBM_PCI_66MHZ (8 << 8) 1158 /* Max Write Burst byte count. */ 1159 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4) 1160 #define MWB_512_BYTES (0 << 4) 1161 #define MWB_1024_BYTES (1 << 4) 1162 #define MWB_2048_BYTES (2 << 4) 1163 #define MWB_4096_BYTES (3 << 4) 1164 1165 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */ 1166 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */ 1167 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ 1168 1169 uint32_t ictrl; /* Interrupt control. */ 1170 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */ 1171 1172 uint32_t istatus; /* Interrupt status. */ 1173 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */ 1174 1175 uint32_t unused_1[2]; /* Gap. */ 1176 1177 /* Request Queue. */ 1178 uint32_t req_q_in; /* In-Pointer. */ 1179 uint32_t req_q_out; /* Out-Pointer. */ 1180 /* Response Queue. */ 1181 uint32_t rsp_q_in; /* In-Pointer. */ 1182 uint32_t rsp_q_out; /* Out-Pointer. */ 1183 /* Priority Request Queue. */ 1184 uint32_t preq_q_in; /* In-Pointer. */ 1185 uint32_t preq_q_out; /* Out-Pointer. */ 1186 1187 uint32_t unused_2[2]; /* Gap. */ 1188 1189 /* ATIO Queue. */ 1190 uint32_t atio_q_in; /* In-Pointer. */ 1191 uint32_t atio_q_out; /* Out-Pointer. */ 1192 1193 uint32_t host_status; 1194 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ 1195 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ 1196 1197 uint32_t hccr; /* Host command & control register. */ 1198 /* HCCR statuses. */ 1199 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ 1200 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 1201 /* HCCR commands. */ 1202 /* NOOP. */ 1203 #define HCCRX_NOOP 0x00000000 1204 /* Set RISC Reset. */ 1205 #define HCCRX_SET_RISC_RESET 0x10000000 1206 /* Clear RISC Reset. */ 1207 #define HCCRX_CLR_RISC_RESET 0x20000000 1208 /* Set RISC Pause. */ 1209 #define HCCRX_SET_RISC_PAUSE 0x30000000 1210 /* Releases RISC Pause. */ 1211 #define HCCRX_REL_RISC_PAUSE 0x40000000 1212 /* Set HOST to RISC interrupt. */ 1213 #define HCCRX_SET_HOST_INT 0x50000000 1214 /* Clear HOST to RISC interrupt. */ 1215 #define HCCRX_CLR_HOST_INT 0x60000000 1216 /* Clear RISC to PCI interrupt. */ 1217 #define HCCRX_CLR_RISC_INT 0xA0000000 1218 1219 uint32_t gpiod; /* GPIO Data register. */ 1220 1221 /* LED update mask. */ 1222 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) 1223 /* Data update mask. */ 1224 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) 1225 /* Data update mask. */ 1226 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 1227 /* LED control mask. */ 1228 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) 1229 /* LED bit values. Color names as 1230 * referenced in fw spec. 1231 */ 1232 #define GPDX_LED_YELLOW_ON BIT_2 1233 #define GPDX_LED_GREEN_ON BIT_3 1234 #define GPDX_LED_AMBER_ON BIT_4 1235 /* Data in/out. */ 1236 #define GPDX_DATA_INOUT (BIT_1|BIT_0) 1237 1238 uint32_t gpioe; /* GPIO Enable register. */ 1239 /* Enable update mask. */ 1240 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) 1241 /* Enable update mask. */ 1242 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 1243 /* Enable. */ 1244 #define GPEX_ENABLE (BIT_1|BIT_0) 1245 1246 uint32_t iobase_addr; /* I/O Bus Base Address register. */ 1247 1248 uint32_t unused_3[10]; /* Gap. */ 1249 1250 uint16_t mailbox0; 1251 uint16_t mailbox1; 1252 uint16_t mailbox2; 1253 uint16_t mailbox3; 1254 uint16_t mailbox4; 1255 uint16_t mailbox5; 1256 uint16_t mailbox6; 1257 uint16_t mailbox7; 1258 uint16_t mailbox8; 1259 uint16_t mailbox9; 1260 uint16_t mailbox10; 1261 uint16_t mailbox11; 1262 uint16_t mailbox12; 1263 uint16_t mailbox13; 1264 uint16_t mailbox14; 1265 uint16_t mailbox15; 1266 uint16_t mailbox16; 1267 uint16_t mailbox17; 1268 uint16_t mailbox18; 1269 uint16_t mailbox19; 1270 uint16_t mailbox20; 1271 uint16_t mailbox21; 1272 uint16_t mailbox22; 1273 uint16_t mailbox23; 1274 uint16_t mailbox24; 1275 uint16_t mailbox25; 1276 uint16_t mailbox26; 1277 uint16_t mailbox27; 1278 uint16_t mailbox28; 1279 uint16_t mailbox29; 1280 uint16_t mailbox30; 1281 uint16_t mailbox31; 1282 1283 uint32_t iobase_window; 1284 uint32_t iobase_c4; 1285 uint32_t iobase_c8; 1286 uint32_t unused_4_1[6]; /* Gap. */ 1287 uint32_t iobase_q; 1288 uint32_t unused_5[2]; /* Gap. */ 1289 uint32_t iobase_select; 1290 uint32_t unused_6[2]; /* Gap. */ 1291 uint32_t iobase_sdata; 1292 }; 1293 /* RISC-RISC semaphore register PCI offet */ 1294 #define RISC_REGISTER_BASE_OFFSET 0x7010 1295 #define RISC_REGISTER_WINDOW_OFFET 0x6 1296 1297 /* RISC-RISC semaphore/flag register (risc address 0x7016) */ 1298 1299 #define RISC_SEMAPHORE 0x1UL 1300 #define RISC_SEMAPHORE_WE (RISC_SEMAPHORE << 16) 1301 #define RISC_SEMAPHORE_CLR (RISC_SEMAPHORE_WE | 0x0UL) 1302 #define RISC_SEMAPHORE_SET (RISC_SEMAPHORE_WE | RISC_SEMAPHORE) 1303 1304 #define RISC_SEMAPHORE_FORCE 0x8000UL 1305 #define RISC_SEMAPHORE_FORCE_WE (RISC_SEMAPHORE_FORCE << 16) 1306 #define RISC_SEMAPHORE_FORCE_CLR (RISC_SEMAPHORE_FORCE_WE | 0x0UL) 1307 #define RISC_SEMAPHORE_FORCE_SET \ 1308 (RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE) 1309 1310 /* RISC semaphore timeouts (ms) */ 1311 #define TIMEOUT_SEMAPHORE 2500 1312 #define TIMEOUT_SEMAPHORE_FORCE 2000 1313 #define TIMEOUT_TOTAL_ELAPSED 4500 1314 1315 /* Trace Control *************************************************************/ 1316 1317 #define TC_AEN_DISABLE 0 1318 1319 #define TC_EFT_ENABLE 4 1320 #define TC_EFT_DISABLE 5 1321 1322 #define TC_FCE_ENABLE 8 1323 #define TC_FCE_OPTIONS 0 1324 #define TC_FCE_DEFAULT_RX_SIZE 2112 1325 #define TC_FCE_DEFAULT_TX_SIZE 2112 1326 #define TC_FCE_DISABLE 9 1327 #define TC_FCE_DISABLE_TRACE BIT_0 1328 1329 /* MID Support ***************************************************************/ 1330 1331 #define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */ 1332 #define MAX_MULTI_ID_FABRIC 256 /* ... */ 1333 1334 struct mid_conf_entry_24xx { 1335 uint16_t reserved_1; 1336 1337 /* 1338 * BIT 0 = Enable Hard Loop Id 1339 * BIT 1 = Acquire Loop ID in LIPA 1340 * BIT 2 = ID not Acquired 1341 * BIT 3 = Enable VP 1342 * BIT 4 = Enable Initiator Mode 1343 * BIT 5 = Disable Target Mode 1344 * BIT 6-7 = Reserved 1345 */ 1346 uint8_t options; 1347 1348 uint8_t hard_address; 1349 1350 uint8_t port_name[WWN_SIZE]; 1351 uint8_t node_name[WWN_SIZE]; 1352 }; 1353 1354 struct mid_init_cb_24xx { 1355 struct init_cb_24xx init_cb; 1356 1357 uint16_t count; 1358 uint16_t options; 1359 1360 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 1361 }; 1362 1363 1364 struct mid_db_entry_24xx { 1365 uint16_t status; 1366 #define MDBS_NON_PARTIC BIT_3 1367 #define MDBS_ID_ACQUIRED BIT_1 1368 #define MDBS_ENABLED BIT_0 1369 1370 uint8_t options; 1371 uint8_t hard_address; 1372 1373 uint8_t port_name[WWN_SIZE]; 1374 uint8_t node_name[WWN_SIZE]; 1375 1376 uint8_t port_id[3]; 1377 uint8_t reserved_1; 1378 }; 1379 1380 /* 1381 * Virtual Port Control IOCB 1382 */ 1383 #define VP_CTRL_IOCB_TYPE 0x30 /* Virtual Port Control entry. */ 1384 struct vp_ctrl_entry_24xx { 1385 uint8_t entry_type; /* Entry type. */ 1386 uint8_t entry_count; /* Entry count. */ 1387 uint8_t sys_define; /* System defined. */ 1388 uint8_t entry_status; /* Entry Status. */ 1389 1390 uint32_t handle; /* System handle. */ 1391 1392 uint16_t vp_idx_failed; 1393 1394 uint16_t comp_status; /* Completion status. */ 1395 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */ 1396 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */ 1397 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1398 1399 uint16_t command; 1400 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */ 1401 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */ 1402 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */ 1403 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */ 1404 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */ 1405 1406 uint16_t vp_count; 1407 1408 uint8_t vp_idx_map[16]; 1409 uint16_t flags; 1410 uint16_t id; 1411 uint16_t reserved_4; 1412 uint16_t hopct; 1413 uint8_t reserved_5[24]; 1414 }; 1415 1416 /* 1417 * Modify Virtual Port Configuration IOCB 1418 */ 1419 #define VP_CONFIG_IOCB_TYPE 0x31 /* Virtual Port Config entry. */ 1420 struct vp_config_entry_24xx { 1421 uint8_t entry_type; /* Entry type. */ 1422 uint8_t entry_count; /* Entry count. */ 1423 uint8_t handle_count; 1424 uint8_t entry_status; /* Entry Status. */ 1425 1426 uint32_t handle; /* System handle. */ 1427 1428 uint16_t flags; 1429 #define CS_VF_BIND_VPORTS_TO_VF BIT_0 1430 #define CS_VF_SET_QOS_OF_VPORTS BIT_1 1431 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2 1432 1433 uint16_t comp_status; /* Completion status. */ 1434 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */ 1435 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */ 1436 #define CS_VCT_ERROR 0x03 /* Unknown error. */ 1437 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */ 1438 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1439 1440 uint8_t command; 1441 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */ 1442 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */ 1443 1444 uint8_t vp_count; 1445 1446 uint8_t vp_index1; 1447 uint8_t vp_index2; 1448 1449 uint8_t options_idx1; 1450 uint8_t hard_address_idx1; 1451 uint16_t reserved_vp1; 1452 uint8_t port_name_idx1[WWN_SIZE]; 1453 uint8_t node_name_idx1[WWN_SIZE]; 1454 1455 uint8_t options_idx2; 1456 uint8_t hard_address_idx2; 1457 uint16_t reserved_vp2; 1458 uint8_t port_name_idx2[WWN_SIZE]; 1459 uint8_t node_name_idx2[WWN_SIZE]; 1460 uint16_t id; 1461 uint16_t reserved_4; 1462 uint16_t hopct; 1463 uint8_t reserved_5[2]; 1464 }; 1465 1466 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */ 1467 enum VP_STATUS { 1468 VP_STAT_COMPL, 1469 VP_STAT_FAIL, 1470 VP_STAT_ID_CHG, 1471 VP_STAT_SNS_TO, /* timeout */ 1472 VP_STAT_SNS_RJT, 1473 VP_STAT_SCR_TO, /* timeout */ 1474 VP_STAT_SCR_RJT, 1475 }; 1476 1477 enum VP_FLAGS { 1478 VP_FLAGS_CON_FLOOP = 1, 1479 VP_FLAGS_CON_P2P = 2, 1480 VP_FLAGS_CON_FABRIC = 3, 1481 VP_FLAGS_NAME_VALID = BIT_5, 1482 }; 1483 1484 struct vp_rpt_id_entry_24xx { 1485 uint8_t entry_type; /* Entry type. */ 1486 uint8_t entry_count; /* Entry count. */ 1487 uint8_t sys_define; /* System defined. */ 1488 uint8_t entry_status; /* Entry Status. */ 1489 uint32_t resv1; 1490 uint8_t vp_acquired; 1491 uint8_t vp_setup; 1492 uint8_t vp_idx; /* Format 0=reserved */ 1493 uint8_t vp_status; /* Format 0=reserved */ 1494 1495 uint8_t port_id[3]; 1496 uint8_t format; 1497 union { 1498 struct _f0 { 1499 /* format 0 loop */ 1500 uint8_t vp_idx_map[16]; 1501 uint8_t reserved_4[32]; 1502 } f0; 1503 struct _f1 { 1504 /* format 1 fabric */ 1505 uint8_t vpstat1_subcode; /* vp_status=1 subcode */ 1506 uint8_t flags; 1507 #define TOPO_MASK 0xE 1508 #define TOPO_FL 0x2 1509 #define TOPO_N2N 0x4 1510 #define TOPO_F 0x6 1511 1512 uint16_t fip_flags; 1513 uint8_t rsv2[12]; 1514 1515 uint8_t ls_rjt_vendor; 1516 uint8_t ls_rjt_explanation; 1517 uint8_t ls_rjt_reason; 1518 uint8_t rsv3[5]; 1519 1520 uint8_t port_name[8]; 1521 uint8_t node_name[8]; 1522 uint16_t bbcr; 1523 uint8_t reserved_5[6]; 1524 } f1; 1525 struct _f2 { /* format 2: N2N direct connect */ 1526 uint8_t vpstat1_subcode; 1527 uint8_t flags; 1528 uint16_t fip_flags; 1529 uint8_t rsv2[12]; 1530 1531 uint8_t ls_rjt_vendor; 1532 uint8_t ls_rjt_explanation; 1533 uint8_t ls_rjt_reason; 1534 uint8_t rsv3[5]; 1535 1536 uint8_t port_name[8]; 1537 uint8_t node_name[8]; 1538 uint16_t bbcr; 1539 uint8_t reserved_5[2]; 1540 uint8_t remote_nport_id[4]; 1541 } f2; 1542 } u; 1543 }; 1544 1545 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */ 1546 struct vf_evfp_entry_24xx { 1547 uint8_t entry_type; /* Entry type. */ 1548 uint8_t entry_count; /* Entry count. */ 1549 uint8_t sys_define; /* System defined. */ 1550 uint8_t entry_status; /* Entry Status. */ 1551 1552 uint32_t handle; /* System handle. */ 1553 uint16_t comp_status; /* Completion status. */ 1554 uint16_t timeout; /* timeout */ 1555 uint16_t adim_tagging_mode; 1556 1557 uint16_t vfport_id; 1558 uint32_t exch_addr; 1559 1560 uint16_t nport_handle; /* N_PORT handle. */ 1561 uint16_t control_flags; 1562 uint32_t io_parameter_0; 1563 uint32_t io_parameter_1; 1564 __le64 tx_address __packed; /* Data segment 0 address. */ 1565 uint32_t tx_len; /* Data segment 0 length. */ 1566 __le64 rx_address __packed; /* Data segment 1 address. */ 1567 uint32_t rx_len; /* Data segment 1 length. */ 1568 }; 1569 1570 /* END MID Support ***********************************************************/ 1571 1572 /* Flash Description Table ***************************************************/ 1573 1574 struct qla_fdt_layout { 1575 uint8_t sig[4]; 1576 uint16_t version; 1577 uint16_t len; 1578 uint16_t checksum; 1579 uint8_t unused1[2]; 1580 uint8_t model[16]; 1581 uint16_t man_id; 1582 uint16_t id; 1583 uint8_t flags; 1584 uint8_t erase_cmd; 1585 uint8_t alt_erase_cmd; 1586 uint8_t wrt_enable_cmd; 1587 uint8_t wrt_enable_bits; 1588 uint8_t wrt_sts_reg_cmd; 1589 uint8_t unprotect_sec_cmd; 1590 uint8_t read_man_id_cmd; 1591 uint32_t block_size; 1592 uint32_t alt_block_size; 1593 uint32_t flash_size; 1594 uint32_t wrt_enable_data; 1595 uint8_t read_id_addr_len; 1596 uint8_t wrt_disable_bits; 1597 uint8_t read_dev_id_len; 1598 uint8_t chip_erase_cmd; 1599 uint16_t read_timeout; 1600 uint8_t protect_sec_cmd; 1601 uint8_t unused2[65]; 1602 }; 1603 1604 /* Flash Layout Table ********************************************************/ 1605 1606 struct qla_flt_location { 1607 uint8_t sig[4]; 1608 uint16_t start_lo; 1609 uint16_t start_hi; 1610 uint8_t version; 1611 uint8_t unused[5]; 1612 uint16_t checksum; 1613 }; 1614 1615 #define FLT_REG_FW 0x01 1616 #define FLT_REG_BOOT_CODE 0x07 1617 #define FLT_REG_VPD_0 0x14 1618 #define FLT_REG_NVRAM_0 0x15 1619 #define FLT_REG_VPD_1 0x16 1620 #define FLT_REG_NVRAM_1 0x17 1621 #define FLT_REG_VPD_2 0xD4 1622 #define FLT_REG_NVRAM_2 0xD5 1623 #define FLT_REG_VPD_3 0xD6 1624 #define FLT_REG_NVRAM_3 0xD7 1625 #define FLT_REG_FDT 0x1a 1626 #define FLT_REG_FLT 0x1c 1627 #define FLT_REG_HW_EVENT_0 0x1d 1628 #define FLT_REG_HW_EVENT_1 0x1f 1629 #define FLT_REG_NPIV_CONF_0 0x29 1630 #define FLT_REG_NPIV_CONF_1 0x2a 1631 #define FLT_REG_GOLD_FW 0x2f 1632 #define FLT_REG_FCP_PRIO_0 0x87 1633 #define FLT_REG_FCP_PRIO_1 0x88 1634 #define FLT_REG_CNA_FW 0x97 1635 #define FLT_REG_BOOT_CODE_8044 0xA2 1636 #define FLT_REG_FCOE_FW 0xA4 1637 #define FLT_REG_FCOE_NVRAM_0 0xAA 1638 #define FLT_REG_FCOE_NVRAM_1 0xAC 1639 1640 /* 27xx */ 1641 #define FLT_REG_IMG_PRI_27XX 0x95 1642 #define FLT_REG_IMG_SEC_27XX 0x96 1643 #define FLT_REG_FW_SEC_27XX 0x02 1644 #define FLT_REG_BOOTLOAD_SEC_27XX 0x9 1645 #define FLT_REG_VPD_SEC_27XX_0 0x50 1646 #define FLT_REG_VPD_SEC_27XX_1 0x52 1647 #define FLT_REG_VPD_SEC_27XX_2 0xD8 1648 #define FLT_REG_VPD_SEC_27XX_3 0xDA 1649 1650 /* 28xx */ 1651 #define FLT_REG_AUX_IMG_PRI_28XX 0x125 1652 #define FLT_REG_AUX_IMG_SEC_28XX 0x126 1653 #define FLT_REG_VPD_SEC_28XX_0 0x10C 1654 #define FLT_REG_VPD_SEC_28XX_1 0x10E 1655 #define FLT_REG_VPD_SEC_28XX_2 0x110 1656 #define FLT_REG_VPD_SEC_28XX_3 0x112 1657 #define FLT_REG_NVRAM_SEC_28XX_0 0x10D 1658 #define FLT_REG_NVRAM_SEC_28XX_1 0x10F 1659 #define FLT_REG_NVRAM_SEC_28XX_2 0x111 1660 #define FLT_REG_NVRAM_SEC_28XX_3 0x113 1661 #define FLT_REG_MPI_PRI_28XX 0xD3 1662 #define FLT_REG_MPI_SEC_28XX 0xF0 1663 #define FLT_REG_PEP_PRI_28XX 0xD1 1664 #define FLT_REG_PEP_SEC_28XX 0xF1 1665 1666 struct qla_flt_region { 1667 uint16_t code; 1668 uint8_t attribute; 1669 uint8_t reserved; 1670 uint32_t size; 1671 uint32_t start; 1672 uint32_t end; 1673 }; 1674 1675 struct qla_flt_header { 1676 uint16_t version; 1677 uint16_t length; 1678 uint16_t checksum; 1679 uint16_t unused; 1680 struct qla_flt_region region[0]; 1681 }; 1682 1683 #define FLT_REGION_SIZE 16 1684 #define FLT_MAX_REGIONS 0xFF 1685 #define FLT_REGIONS_SIZE (FLT_REGION_SIZE * FLT_MAX_REGIONS) 1686 1687 /* Flash NPIV Configuration Table ********************************************/ 1688 1689 struct qla_npiv_header { 1690 uint8_t sig[2]; 1691 uint16_t version; 1692 uint16_t entries; 1693 uint16_t unused[4]; 1694 uint16_t checksum; 1695 }; 1696 1697 struct qla_npiv_entry { 1698 uint16_t flags; 1699 uint16_t vf_id; 1700 uint8_t q_qos; 1701 uint8_t f_qos; 1702 uint16_t unused1; 1703 uint8_t port_name[WWN_SIZE]; 1704 uint8_t node_name[WWN_SIZE]; 1705 }; 1706 1707 /* 84XX Support **************************************************************/ 1708 1709 #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */ 1710 #define A84_PANIC_RECOVERY 0x1 1711 #define A84_OP_LOGIN_COMPLETE 0x2 1712 #define A84_DIAG_LOGIN_COMPLETE 0x3 1713 #define A84_GOLD_LOGIN_COMPLETE 0x4 1714 1715 #define MBC_ISP84XX_RESET 0x3a /* Reset. */ 1716 1717 #define FSTATE_REMOTE_FC_DOWN BIT_0 1718 #define FSTATE_NSL_LINK_DOWN BIT_1 1719 #define FSTATE_IS_DIAG_FW BIT_2 1720 #define FSTATE_LOGGED_IN BIT_3 1721 #define FSTATE_WAITING_FOR_VERIFY BIT_4 1722 1723 #define VERIFY_CHIP_IOCB_TYPE 0x1B 1724 struct verify_chip_entry_84xx { 1725 uint8_t entry_type; 1726 uint8_t entry_count; 1727 uint8_t sys_defined; 1728 uint8_t entry_status; 1729 1730 uint32_t handle; 1731 1732 uint16_t options; 1733 #define VCO_DONT_UPDATE_FW BIT_0 1734 #define VCO_FORCE_UPDATE BIT_1 1735 #define VCO_DONT_RESET_UPDATE BIT_2 1736 #define VCO_DIAG_FW BIT_3 1737 #define VCO_END_OF_DATA BIT_14 1738 #define VCO_ENABLE_DSD BIT_15 1739 1740 uint16_t reserved_1; 1741 1742 uint16_t data_seg_cnt; 1743 uint16_t reserved_2[3]; 1744 1745 uint32_t fw_ver; 1746 uint32_t exchange_address; 1747 1748 uint32_t reserved_3[3]; 1749 uint32_t fw_size; 1750 uint32_t fw_seq_size; 1751 uint32_t relative_offset; 1752 1753 struct dsd64 dsd; 1754 }; 1755 1756 struct verify_chip_rsp_84xx { 1757 uint8_t entry_type; 1758 uint8_t entry_count; 1759 uint8_t sys_defined; 1760 uint8_t entry_status; 1761 1762 uint32_t handle; 1763 1764 uint16_t comp_status; 1765 #define CS_VCS_CHIP_FAILURE 0x3 1766 #define CS_VCS_BAD_EXCHANGE 0x8 1767 #define CS_VCS_SEQ_COMPLETEi 0x40 1768 1769 uint16_t failure_code; 1770 #define VFC_CHECKSUM_ERROR 0x1 1771 #define VFC_INVALID_LEN 0x2 1772 #define VFC_ALREADY_IN_PROGRESS 0x8 1773 1774 uint16_t reserved_1[4]; 1775 1776 uint32_t fw_ver; 1777 uint32_t exchange_address; 1778 1779 uint32_t reserved_2[6]; 1780 }; 1781 1782 #define ACCESS_CHIP_IOCB_TYPE 0x2B 1783 struct access_chip_84xx { 1784 uint8_t entry_type; 1785 uint8_t entry_count; 1786 uint8_t sys_defined; 1787 uint8_t entry_status; 1788 1789 uint32_t handle; 1790 1791 uint16_t options; 1792 #define ACO_DUMP_MEMORY 0x0 1793 #define ACO_LOAD_MEMORY 0x1 1794 #define ACO_CHANGE_CONFIG_PARAM 0x2 1795 #define ACO_REQUEST_INFO 0x3 1796 1797 uint16_t reserved1; 1798 1799 uint16_t dseg_count; 1800 uint16_t reserved2[3]; 1801 1802 uint32_t parameter1; 1803 uint32_t parameter2; 1804 uint32_t parameter3; 1805 1806 uint32_t reserved3[3]; 1807 uint32_t total_byte_cnt; 1808 uint32_t reserved4; 1809 1810 struct dsd64 dsd; 1811 }; 1812 1813 struct access_chip_rsp_84xx { 1814 uint8_t entry_type; 1815 uint8_t entry_count; 1816 uint8_t sys_defined; 1817 uint8_t entry_status; 1818 1819 uint32_t handle; 1820 1821 uint16_t comp_status; 1822 uint16_t failure_code; 1823 uint32_t residual_count; 1824 1825 uint32_t reserved[12]; 1826 }; 1827 1828 /* 81XX Support **************************************************************/ 1829 1830 #define MBA_DCBX_START 0x8016 1831 #define MBA_DCBX_COMPLETE 0x8030 1832 #define MBA_FCF_CONF_ERR 0x8031 1833 #define MBA_DCBX_PARAM_UPDATE 0x8032 1834 #define MBA_IDC_COMPLETE 0x8100 1835 #define MBA_IDC_NOTIFY 0x8101 1836 #define MBA_IDC_TIME_EXT 0x8102 1837 1838 #define MBC_IDC_ACK 0x101 1839 #define MBC_RESTART_MPI_FW 0x3d 1840 #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */ 1841 #define MBC_GET_XGMAC_STATS 0x7a 1842 #define MBC_GET_DCBX_PARAMS 0x51 1843 1844 /* 1845 * ISP83xx mailbox commands 1846 */ 1847 #define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */ 1848 #define MBC_READ_REMOTE_REG 0x0009 /* Read remote register */ 1849 #define MBC_RESTART_NIC_FIRMWARE 0x003d /* Restart NIC firmware */ 1850 #define MBC_SET_ACCESS_CONTROL 0x003e /* Access control command */ 1851 1852 /* Flash access control option field bit definitions */ 1853 #define FAC_OPT_FORCE_SEMAPHORE BIT_15 1854 #define FAC_OPT_REQUESTOR_ID BIT_14 1855 #define FAC_OPT_CMD_SUBCODE 0xff 1856 1857 /* Flash access control command subcodes */ 1858 #define FAC_OPT_CMD_WRITE_PROTECT 0x00 1859 #define FAC_OPT_CMD_WRITE_ENABLE 0x01 1860 #define FAC_OPT_CMD_ERASE_SECTOR 0x02 1861 #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03 1862 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04 1863 #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05 1864 1865 /* enhanced features bit definitions */ 1866 #define NEF_LR_DIST_ENABLE BIT_0 1867 1868 /* LR Distance bit positions */ 1869 #define LR_DIST_NV_POS 2 1870 #define LR_DIST_NV_MASK 0xf 1871 #define LR_DIST_FW_POS 12 1872 1873 /* FAC semaphore defines */ 1874 #define FAC_SEMAPHORE_UNLOCK 0 1875 #define FAC_SEMAPHORE_LOCK 1 1876 1877 struct nvram_81xx { 1878 /* NVRAM header. */ 1879 uint8_t id[4]; 1880 uint16_t nvram_version; 1881 uint16_t reserved_0; 1882 1883 /* Firmware Initialization Control Block. */ 1884 uint16_t version; 1885 uint16_t reserved_1; 1886 uint16_t frame_payload_size; 1887 uint16_t execution_throttle; 1888 uint16_t exchange_count; 1889 uint16_t reserved_2; 1890 1891 uint8_t port_name[WWN_SIZE]; 1892 uint8_t node_name[WWN_SIZE]; 1893 1894 uint16_t login_retry_count; 1895 uint16_t reserved_3; 1896 uint16_t interrupt_delay_timer; 1897 uint16_t login_timeout; 1898 1899 uint32_t firmware_options_1; 1900 uint32_t firmware_options_2; 1901 uint32_t firmware_options_3; 1902 1903 uint16_t reserved_4[4]; 1904 1905 /* Offset 64. */ 1906 uint8_t enode_mac[6]; 1907 uint16_t reserved_5[5]; 1908 1909 /* Offset 80. */ 1910 uint16_t reserved_6[24]; 1911 1912 /* Offset 128. */ 1913 uint16_t ex_version; 1914 uint8_t prio_fcf_matching_flags; 1915 uint8_t reserved_6_1[3]; 1916 uint16_t pri_fcf_vlan_id; 1917 uint8_t pri_fcf_fabric_name[8]; 1918 uint16_t reserved_6_2[7]; 1919 uint8_t spma_mac_addr[6]; 1920 uint16_t reserved_6_3[14]; 1921 1922 /* Offset 192. */ 1923 uint8_t min_supported_speed; 1924 uint8_t reserved_7_0; 1925 uint16_t reserved_7[31]; 1926 1927 /* 1928 * BIT 0 = Enable spinup delay 1929 * BIT 1 = Disable BIOS 1930 * BIT 2 = Enable Memory Map BIOS 1931 * BIT 3 = Enable Selectable Boot 1932 * BIT 4 = Disable RISC code load 1933 * BIT 5 = Disable Serdes 1934 * BIT 6 = Opt boot mode 1935 * BIT 7 = Interrupt enable 1936 * 1937 * BIT 8 = EV Control enable 1938 * BIT 9 = Enable lip reset 1939 * BIT 10 = Enable lip full login 1940 * BIT 11 = Enable target reset 1941 * BIT 12 = Stop firmware 1942 * BIT 13 = Enable nodename option 1943 * BIT 14 = Default WWPN valid 1944 * BIT 15 = Enable alternate WWN 1945 * 1946 * BIT 16 = CLP LUN string 1947 * BIT 17 = CLP Target string 1948 * BIT 18 = CLP BIOS enable string 1949 * BIT 19 = CLP Serdes string 1950 * BIT 20 = CLP WWPN string 1951 * BIT 21 = CLP WWNN string 1952 * BIT 22 = 1953 * BIT 23 = 1954 * BIT 24 = Keep WWPN 1955 * BIT 25 = Temp WWPN 1956 * BIT 26-31 = 1957 */ 1958 uint32_t host_p; 1959 1960 uint8_t alternate_port_name[WWN_SIZE]; 1961 uint8_t alternate_node_name[WWN_SIZE]; 1962 1963 uint8_t boot_port_name[WWN_SIZE]; 1964 uint16_t boot_lun_number; 1965 uint16_t reserved_8; 1966 1967 uint8_t alt1_boot_port_name[WWN_SIZE]; 1968 uint16_t alt1_boot_lun_number; 1969 uint16_t reserved_9; 1970 1971 uint8_t alt2_boot_port_name[WWN_SIZE]; 1972 uint16_t alt2_boot_lun_number; 1973 uint16_t reserved_10; 1974 1975 uint8_t alt3_boot_port_name[WWN_SIZE]; 1976 uint16_t alt3_boot_lun_number; 1977 uint16_t reserved_11; 1978 1979 /* 1980 * BIT 0 = Selective Login 1981 * BIT 1 = Alt-Boot Enable 1982 * BIT 2 = Reserved 1983 * BIT 3 = Boot Order List 1984 * BIT 4 = Reserved 1985 * BIT 5 = Selective LUN 1986 * BIT 6 = Reserved 1987 * BIT 7-31 = 1988 */ 1989 uint32_t efi_parameters; 1990 1991 uint8_t reset_delay; 1992 uint8_t reserved_12; 1993 uint16_t reserved_13; 1994 1995 uint16_t boot_id_number; 1996 uint16_t reserved_14; 1997 1998 uint16_t max_luns_per_target; 1999 uint16_t reserved_15; 2000 2001 uint16_t port_down_retry_count; 2002 uint16_t link_down_timeout; 2003 2004 /* FCode parameters. */ 2005 uint16_t fcode_parameter; 2006 2007 uint16_t reserved_16[3]; 2008 2009 /* Offset 352. */ 2010 uint8_t reserved_17[4]; 2011 uint16_t reserved_18[5]; 2012 uint8_t reserved_19[2]; 2013 uint16_t reserved_20[8]; 2014 2015 /* Offset 384. */ 2016 uint8_t reserved_21[16]; 2017 uint16_t reserved_22[3]; 2018 2019 /* Offset 406 (0x196) Enhanced Features 2020 * BIT 0 = Extended BB credits for LR 2021 * BIT 1 = Virtual Fabric Enable 2022 * BIT 2-5 = Distance Support if BIT 0 is on 2023 * BIT 6-15 = Unused 2024 */ 2025 uint16_t enhanced_features; 2026 2027 uint16_t reserved_24[4]; 2028 2029 /* Offset 416. */ 2030 uint16_t reserved_25[32]; 2031 2032 /* Offset 480. */ 2033 uint8_t model_name[16]; 2034 2035 /* Offset 496. */ 2036 uint16_t feature_mask_l; 2037 uint16_t feature_mask_h; 2038 uint16_t reserved_26[2]; 2039 2040 uint16_t subsystem_vendor_id; 2041 uint16_t subsystem_device_id; 2042 2043 uint32_t checksum; 2044 }; 2045 2046 /* 2047 * ISP Initialization Control Block. 2048 * Little endian except where noted. 2049 */ 2050 #define ICB_VERSION 1 2051 struct init_cb_81xx { 2052 uint16_t version; 2053 uint16_t reserved_1; 2054 2055 uint16_t frame_payload_size; 2056 uint16_t execution_throttle; 2057 uint16_t exchange_count; 2058 2059 uint16_t reserved_2; 2060 2061 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 2062 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 2063 2064 uint16_t response_q_inpointer; 2065 uint16_t request_q_outpointer; 2066 2067 uint16_t login_retry_count; 2068 2069 uint16_t prio_request_q_outpointer; 2070 2071 uint16_t response_q_length; 2072 uint16_t request_q_length; 2073 2074 uint16_t reserved_3; 2075 2076 uint16_t prio_request_q_length; 2077 2078 __le64 request_q_address __packed; 2079 __le64 response_q_address __packed; 2080 __le64 prio_request_q_address __packed; 2081 2082 uint8_t reserved_4[8]; 2083 2084 uint16_t atio_q_inpointer; 2085 uint16_t atio_q_length; 2086 __le64 atio_q_address __packed; 2087 2088 uint16_t interrupt_delay_timer; /* 100us increments. */ 2089 uint16_t login_timeout; 2090 2091 /* 2092 * BIT 0-3 = Reserved 2093 * BIT 4 = Enable Target Mode 2094 * BIT 5 = Disable Initiator Mode 2095 * BIT 6 = Reserved 2096 * BIT 7 = Reserved 2097 * 2098 * BIT 8-13 = Reserved 2099 * BIT 14 = Node Name Option 2100 * BIT 15-31 = Reserved 2101 */ 2102 uint32_t firmware_options_1; 2103 2104 /* 2105 * BIT 0 = Operation Mode bit 0 2106 * BIT 1 = Operation Mode bit 1 2107 * BIT 2 = Operation Mode bit 2 2108 * BIT 3 = Operation Mode bit 3 2109 * BIT 4-7 = Reserved 2110 * 2111 * BIT 8 = Enable Class 2 2112 * BIT 9 = Enable ACK0 2113 * BIT 10 = Reserved 2114 * BIT 11 = Enable FC-SP Security 2115 * BIT 12 = FC Tape Enable 2116 * BIT 13 = Reserved 2117 * BIT 14 = Enable Target PRLI Control 2118 * BIT 15-31 = Reserved 2119 */ 2120 uint32_t firmware_options_2; 2121 2122 /* 2123 * BIT 0-3 = Reserved 2124 * BIT 4 = FCP RSP Payload bit 0 2125 * BIT 5 = FCP RSP Payload bit 1 2126 * BIT 6 = Enable Receive Out-of-Order data frame handling 2127 * BIT 7 = Reserved 2128 * 2129 * BIT 8 = Reserved 2130 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 2131 * BIT 10-16 = Reserved 2132 * BIT 17 = Enable multiple FCFs 2133 * BIT 18-20 = MAC addressing mode 2134 * BIT 21-25 = Ethernet data rate 2135 * BIT 26 = Enable ethernet header rx IOCB for ATIO q 2136 * BIT 27 = Enable ethernet header rx IOCB for response q 2137 * BIT 28 = SPMA selection bit 0 2138 * BIT 28 = SPMA selection bit 1 2139 * BIT 30-31 = Reserved 2140 */ 2141 uint32_t firmware_options_3; 2142 2143 uint8_t reserved_5[8]; 2144 2145 uint8_t enode_mac[6]; 2146 2147 uint8_t reserved_6[10]; 2148 }; 2149 2150 struct mid_init_cb_81xx { 2151 struct init_cb_81xx init_cb; 2152 2153 uint16_t count; 2154 uint16_t options; 2155 2156 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 2157 }; 2158 2159 struct ex_init_cb_81xx { 2160 uint16_t ex_version; 2161 uint8_t prio_fcf_matching_flags; 2162 uint8_t reserved_1[3]; 2163 uint16_t pri_fcf_vlan_id; 2164 uint8_t pri_fcf_fabric_name[8]; 2165 uint16_t reserved_2[7]; 2166 uint8_t spma_mac_addr[6]; 2167 uint16_t reserved_3[14]; 2168 }; 2169 2170 #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000 2171 #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000 2172 #define FARX_ACCESS_FLASH_CONF_28XX 0x7FFD0000 2173 #define FARX_ACCESS_FLASH_DATA_28XX 0x7F7D0000 2174 2175 /* FCP priority config defines *************************************/ 2176 /* operations */ 2177 #define QLFC_FCP_PRIO_DISABLE 0x0 2178 #define QLFC_FCP_PRIO_ENABLE 0x1 2179 #define QLFC_FCP_PRIO_GET_CONFIG 0x2 2180 #define QLFC_FCP_PRIO_SET_CONFIG 0x3 2181 2182 struct qla_fcp_prio_entry { 2183 uint16_t flags; /* Describes parameter(s) in FCP */ 2184 /* priority entry that are valid */ 2185 #define FCP_PRIO_ENTRY_VALID 0x1 2186 #define FCP_PRIO_ENTRY_TAG_VALID 0x2 2187 #define FCP_PRIO_ENTRY_SPID_VALID 0x4 2188 #define FCP_PRIO_ENTRY_DPID_VALID 0x8 2189 #define FCP_PRIO_ENTRY_LUNB_VALID 0x10 2190 #define FCP_PRIO_ENTRY_LUNE_VALID 0x20 2191 #define FCP_PRIO_ENTRY_SWWN_VALID 0x40 2192 #define FCP_PRIO_ENTRY_DWWN_VALID 0x80 2193 uint8_t tag; /* Priority value */ 2194 uint8_t reserved; /* Reserved for future use */ 2195 uint32_t src_pid; /* Src port id. high order byte */ 2196 /* unused; -1 (wild card) */ 2197 uint32_t dst_pid; /* Src port id. high order byte */ 2198 /* unused; -1 (wild card) */ 2199 uint16_t lun_beg; /* 1st lun num of lun range. */ 2200 /* -1 (wild card) */ 2201 uint16_t lun_end; /* 2nd lun num of lun range. */ 2202 /* -1 (wild card) */ 2203 uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */ 2204 uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */ 2205 }; 2206 2207 struct qla_fcp_prio_cfg { 2208 uint8_t signature[4]; /* "HQOS" signature of config data */ 2209 uint16_t version; /* 1: Initial version */ 2210 uint16_t length; /* config data size in num bytes */ 2211 uint16_t checksum; /* config data bytes checksum */ 2212 uint16_t num_entries; /* Number of entries */ 2213 uint16_t size_of_entry; /* Size of each entry in num bytes */ 2214 uint8_t attributes; /* enable/disable, persistence */ 2215 #define FCP_PRIO_ATTR_DISABLE 0x0 2216 #define FCP_PRIO_ATTR_ENABLE 0x1 2217 #define FCP_PRIO_ATTR_PERSIST 0x2 2218 uint8_t reserved; /* Reserved for future use */ 2219 #define FCP_PRIO_CFG_HDR_SIZE 0x10 2220 struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */ 2221 #define FCP_PRIO_CFG_ENTRY_SIZE 0x20 2222 }; 2223 2224 #define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/ 2225 2226 /* 25XX Support ****************************************************/ 2227 #define FA_FCP_PRIO0_ADDR_25 0x3C000 2228 #define FA_FCP_PRIO1_ADDR_25 0x3E000 2229 2230 /* 81XX Flash locations -- occupies second 2MB region. */ 2231 #define FA_BOOT_CODE_ADDR_81 0x80000 2232 #define FA_RISC_CODE_ADDR_81 0xA0000 2233 #define FA_FW_AREA_ADDR_81 0xC0000 2234 #define FA_VPD_NVRAM_ADDR_81 0xD0000 2235 #define FA_VPD0_ADDR_81 0xD0000 2236 #define FA_VPD1_ADDR_81 0xD0400 2237 #define FA_NVRAM0_ADDR_81 0xD0080 2238 #define FA_NVRAM1_ADDR_81 0xD0180 2239 #define FA_FEATURE_ADDR_81 0xD4000 2240 #define FA_FLASH_DESCR_ADDR_81 0xD8000 2241 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400 2242 #define FA_HW_EVENT0_ADDR_81 0xDC000 2243 #define FA_HW_EVENT1_ADDR_81 0xDC400 2244 #define FA_NPIV_CONF0_ADDR_81 0xD1000 2245 #define FA_NPIV_CONF1_ADDR_81 0xD2000 2246 2247 /* 83XX Flash locations -- occupies second 8MB region. */ 2248 #define FA_FLASH_LAYOUT_ADDR_83 (0x3F1000/4) 2249 #define FA_FLASH_LAYOUT_ADDR_28 (0x11000/4) 2250 2251 #define NVRAM_DUAL_FCP_NVME_FLAG_OFFSET 0x196 2252 2253 #endif 2254