1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_FW_H 8 #define __QLA_FW_H 9 10 #define MBS_CHECKSUM_ERROR 0x4010 11 #define MBS_INVALID_PRODUCT_KEY 0x4020 12 13 /* 14 * Firmware Options. 15 */ 16 #define FO1_ENABLE_PUREX BIT_10 17 #define FO1_DISABLE_LED_CTRL BIT_6 18 #define FO1_ENABLE_8016 BIT_0 19 #define FO2_ENABLE_SEL_CLASS2 BIT_5 20 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14 21 #define FO3_HOLD_STS_IOCB BIT_12 22 23 /* 24 * Port Database structure definition for ISP 24xx. 25 */ 26 #define PDO_FORCE_ADISC BIT_1 27 #define PDO_FORCE_PLOGI BIT_0 28 29 30 #define PORT_DATABASE_24XX_SIZE 64 31 struct port_database_24xx { 32 uint16_t flags; 33 #define PDF_TASK_RETRY_ID BIT_14 34 #define PDF_FC_TAPE BIT_7 35 #define PDF_ACK0_CAPABLE BIT_6 36 #define PDF_FCP2_CONF BIT_5 37 #define PDF_CLASS_2 BIT_4 38 #define PDF_HARD_ADDR BIT_1 39 40 uint8_t current_login_state; 41 uint8_t last_login_state; 42 #define PDS_PLOGI_PENDING 0x03 43 #define PDS_PLOGI_COMPLETE 0x04 44 #define PDS_PRLI_PENDING 0x05 45 #define PDS_PRLI_COMPLETE 0x06 46 #define PDS_PORT_UNAVAILABLE 0x07 47 #define PDS_PRLO_PENDING 0x09 48 #define PDS_LOGO_PENDING 0x11 49 #define PDS_PRLI2_PENDING 0x12 50 51 uint8_t hard_address[3]; 52 uint8_t reserved_1; 53 54 uint8_t port_id[3]; 55 uint8_t sequence_id; 56 57 uint16_t port_timer; 58 59 uint16_t nport_handle; /* N_PORT handle. */ 60 61 uint16_t receive_data_size; 62 uint16_t reserved_2; 63 64 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 65 /* Bits 15-0 of word 0 */ 66 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 67 /* Bits 15-0 of word 3 */ 68 69 uint8_t port_name[WWN_SIZE]; 70 uint8_t node_name[WWN_SIZE]; 71 72 uint8_t reserved_3[24]; 73 }; 74 75 struct vp_database_24xx { 76 uint16_t vp_status; 77 uint8_t options; 78 uint8_t id; 79 uint8_t port_name[WWN_SIZE]; 80 uint8_t node_name[WWN_SIZE]; 81 uint16_t port_id_low; 82 uint16_t port_id_high; 83 }; 84 85 struct nvram_24xx { 86 /* NVRAM header. */ 87 uint8_t id[4]; 88 uint16_t nvram_version; 89 uint16_t reserved_0; 90 91 /* Firmware Initialization Control Block. */ 92 uint16_t version; 93 uint16_t reserved_1; 94 uint16_t frame_payload_size; 95 uint16_t execution_throttle; 96 uint16_t exchange_count; 97 uint16_t hard_address; 98 99 uint8_t port_name[WWN_SIZE]; 100 uint8_t node_name[WWN_SIZE]; 101 102 uint16_t login_retry_count; 103 uint16_t link_down_on_nos; 104 uint16_t interrupt_delay_timer; 105 uint16_t login_timeout; 106 107 uint32_t firmware_options_1; 108 uint32_t firmware_options_2; 109 uint32_t firmware_options_3; 110 111 /* Offset 56. */ 112 113 /* 114 * BIT 0 = Control Enable 115 * BIT 1-15 = 116 * 117 * BIT 0-7 = Reserved 118 * BIT 8-10 = Output Swing 1G 119 * BIT 11-13 = Output Emphasis 1G 120 * BIT 14-15 = Reserved 121 * 122 * BIT 0-7 = Reserved 123 * BIT 8-10 = Output Swing 2G 124 * BIT 11-13 = Output Emphasis 2G 125 * BIT 14-15 = Reserved 126 * 127 * BIT 0-7 = Reserved 128 * BIT 8-10 = Output Swing 4G 129 * BIT 11-13 = Output Emphasis 4G 130 * BIT 14-15 = Reserved 131 */ 132 uint16_t seriallink_options[4]; 133 134 uint16_t reserved_2[16]; 135 136 /* Offset 96. */ 137 uint16_t reserved_3[16]; 138 139 /* PCIe table entries. */ 140 uint16_t reserved_4[16]; 141 142 /* Offset 160. */ 143 uint16_t reserved_5[16]; 144 145 /* Offset 192. */ 146 uint16_t reserved_6[16]; 147 148 /* Offset 224. */ 149 uint16_t reserved_7[16]; 150 151 /* 152 * BIT 0 = Enable spinup delay 153 * BIT 1 = Disable BIOS 154 * BIT 2 = Enable Memory Map BIOS 155 * BIT 3 = Enable Selectable Boot 156 * BIT 4 = Disable RISC code load 157 * BIT 5 = Disable Serdes 158 * BIT 6 = 159 * BIT 7 = 160 * 161 * BIT 8 = 162 * BIT 9 = 163 * BIT 10 = Enable lip full login 164 * BIT 11 = Enable target reset 165 * BIT 12 = 166 * BIT 13 = 167 * BIT 14 = 168 * BIT 15 = Enable alternate WWN 169 * 170 * BIT 16-31 = 171 */ 172 uint32_t host_p; 173 174 uint8_t alternate_port_name[WWN_SIZE]; 175 uint8_t alternate_node_name[WWN_SIZE]; 176 177 uint8_t boot_port_name[WWN_SIZE]; 178 uint16_t boot_lun_number; 179 uint16_t reserved_8; 180 181 uint8_t alt1_boot_port_name[WWN_SIZE]; 182 uint16_t alt1_boot_lun_number; 183 uint16_t reserved_9; 184 185 uint8_t alt2_boot_port_name[WWN_SIZE]; 186 uint16_t alt2_boot_lun_number; 187 uint16_t reserved_10; 188 189 uint8_t alt3_boot_port_name[WWN_SIZE]; 190 uint16_t alt3_boot_lun_number; 191 uint16_t reserved_11; 192 193 /* 194 * BIT 0 = Selective Login 195 * BIT 1 = Alt-Boot Enable 196 * BIT 2 = Reserved 197 * BIT 3 = Boot Order List 198 * BIT 4 = Reserved 199 * BIT 5 = Selective LUN 200 * BIT 6 = Reserved 201 * BIT 7-31 = 202 */ 203 uint32_t efi_parameters; 204 205 uint8_t reset_delay; 206 uint8_t reserved_12; 207 uint16_t reserved_13; 208 209 uint16_t boot_id_number; 210 uint16_t reserved_14; 211 212 uint16_t max_luns_per_target; 213 uint16_t reserved_15; 214 215 uint16_t port_down_retry_count; 216 uint16_t link_down_timeout; 217 218 /* FCode parameters. */ 219 uint16_t fcode_parameter; 220 221 uint16_t reserved_16[3]; 222 223 /* Offset 352. */ 224 uint8_t prev_drv_ver_major; 225 uint8_t prev_drv_ver_submajob; 226 uint8_t prev_drv_ver_minor; 227 uint8_t prev_drv_ver_subminor; 228 229 uint16_t prev_bios_ver_major; 230 uint16_t prev_bios_ver_minor; 231 232 uint16_t prev_efi_ver_major; 233 uint16_t prev_efi_ver_minor; 234 235 uint16_t prev_fw_ver_major; 236 uint8_t prev_fw_ver_minor; 237 uint8_t prev_fw_ver_subminor; 238 239 uint16_t reserved_17[8]; 240 241 /* Offset 384. */ 242 uint16_t reserved_18[16]; 243 244 /* Offset 416. */ 245 uint16_t reserved_19[16]; 246 247 /* Offset 448. */ 248 uint16_t reserved_20[16]; 249 250 /* Offset 480. */ 251 uint8_t model_name[16]; 252 253 uint16_t reserved_21[2]; 254 255 /* Offset 500. */ 256 /* HW Parameter Block. */ 257 uint16_t pcie_table_sig; 258 uint16_t pcie_table_offset; 259 260 uint16_t subsystem_vendor_id; 261 uint16_t subsystem_device_id; 262 263 uint32_t checksum; 264 }; 265 266 /* 267 * ISP Initialization Control Block. 268 * Little endian except where noted. 269 */ 270 #define ICB_VERSION 1 271 struct init_cb_24xx { 272 uint16_t version; 273 uint16_t reserved_1; 274 275 uint16_t frame_payload_size; 276 uint16_t execution_throttle; 277 uint16_t exchange_count; 278 279 uint16_t hard_address; 280 281 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 282 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 283 284 uint16_t response_q_inpointer; 285 uint16_t request_q_outpointer; 286 287 uint16_t login_retry_count; 288 289 uint16_t prio_request_q_outpointer; 290 291 uint16_t response_q_length; 292 uint16_t request_q_length; 293 294 uint16_t link_down_on_nos; /* Milliseconds. */ 295 296 uint16_t prio_request_q_length; 297 298 uint32_t request_q_address[2]; 299 uint32_t response_q_address[2]; 300 uint32_t prio_request_q_address[2]; 301 302 uint16_t msix; 303 uint16_t msix_atio; 304 uint8_t reserved_2[4]; 305 306 uint16_t atio_q_inpointer; 307 uint16_t atio_q_length; 308 uint32_t atio_q_address[2]; 309 310 uint16_t interrupt_delay_timer; /* 100us increments. */ 311 uint16_t login_timeout; 312 313 /* 314 * BIT 0 = Enable Hard Loop Id 315 * BIT 1 = Enable Fairness 316 * BIT 2 = Enable Full-Duplex 317 * BIT 3 = Reserved 318 * BIT 4 = Enable Target Mode 319 * BIT 5 = Disable Initiator Mode 320 * BIT 6 = Reserved 321 * BIT 7 = Reserved 322 * 323 * BIT 8 = Reserved 324 * BIT 9 = Non Participating LIP 325 * BIT 10 = Descending Loop ID Search 326 * BIT 11 = Acquire Loop ID in LIPA 327 * BIT 12 = Reserved 328 * BIT 13 = Full Login after LIP 329 * BIT 14 = Node Name Option 330 * BIT 15-31 = Reserved 331 */ 332 uint32_t firmware_options_1; 333 334 /* 335 * BIT 0 = Operation Mode bit 0 336 * BIT 1 = Operation Mode bit 1 337 * BIT 2 = Operation Mode bit 2 338 * BIT 3 = Operation Mode bit 3 339 * BIT 4 = Connection Options bit 0 340 * BIT 5 = Connection Options bit 1 341 * BIT 6 = Connection Options bit 2 342 * BIT 7 = Enable Non part on LIHA failure 343 * 344 * BIT 8 = Enable Class 2 345 * BIT 9 = Enable ACK0 346 * BIT 10 = Reserved 347 * BIT 11 = Enable FC-SP Security 348 * BIT 12 = FC Tape Enable 349 * BIT 13 = Reserved 350 * BIT 14 = Enable Target PRLI Control 351 * BIT 15-31 = Reserved 352 */ 353 uint32_t firmware_options_2; 354 355 /* 356 * BIT 0 = Reserved 357 * BIT 1 = Soft ID only 358 * BIT 2 = Reserved 359 * BIT 3 = Reserved 360 * BIT 4 = FCP RSP Payload bit 0 361 * BIT 5 = FCP RSP Payload bit 1 362 * BIT 6 = Enable Receive Out-of-Order data frame handling 363 * BIT 7 = Disable Automatic PLOGI on Local Loop 364 * 365 * BIT 8 = Reserved 366 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 367 * BIT 10 = Reserved 368 * BIT 11 = Reserved 369 * BIT 12 = Reserved 370 * BIT 13 = Data Rate bit 0 371 * BIT 14 = Data Rate bit 1 372 * BIT 15 = Data Rate bit 2 373 * BIT 16 = Enable 75 ohm Termination Select 374 * BIT 17-31 = Reserved 375 */ 376 uint32_t firmware_options_3; 377 uint16_t qos; 378 uint16_t rid; 379 uint8_t reserved_3[20]; 380 }; 381 382 /* 383 * ISP queue - command entry structure definition. 384 */ 385 #define COMMAND_BIDIRECTIONAL 0x75 386 struct cmd_bidir { 387 uint8_t entry_type; /* Entry type. */ 388 uint8_t entry_count; /* Entry count. */ 389 uint8_t sys_define; /* System defined */ 390 uint8_t entry_status; /* Entry status. */ 391 392 uint32_t handle; /* System handle. */ 393 394 uint16_t nport_handle; /* N_PORT hanlde. */ 395 396 uint16_t timeout; /* Commnad timeout. */ 397 398 uint16_t wr_dseg_count; /* Write Data segment count. */ 399 uint16_t rd_dseg_count; /* Read Data segment count. */ 400 401 struct scsi_lun lun; /* FCP LUN (BE). */ 402 403 uint16_t control_flags; /* Control flags. */ 404 #define BD_WRAP_BACK BIT_3 405 #define BD_READ_DATA BIT_1 406 #define BD_WRITE_DATA BIT_0 407 408 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 409 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 410 411 uint16_t reserved[2]; /* Reserved */ 412 413 uint32_t rd_byte_count; /* Total Byte count Read. */ 414 uint32_t wr_byte_count; /* Total Byte count write. */ 415 416 uint8_t port_id[3]; /* PortID of destination port.*/ 417 uint8_t vp_index; 418 419 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ 420 uint16_t fcp_data_dseg_len; /* Data segment length. */ 421 }; 422 423 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */ 424 struct cmd_type_6 { 425 uint8_t entry_type; /* Entry type. */ 426 uint8_t entry_count; /* Entry count. */ 427 uint8_t sys_define; /* System defined. */ 428 uint8_t entry_status; /* Entry Status. */ 429 430 uint32_t handle; /* System handle. */ 431 432 uint16_t nport_handle; /* N_PORT handle. */ 433 uint16_t timeout; /* Command timeout. */ 434 435 uint16_t dseg_count; /* Data segment count. */ 436 437 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */ 438 439 struct scsi_lun lun; /* FCP LUN (BE). */ 440 441 uint16_t control_flags; /* Control flags. */ 442 #define CF_DIF_SEG_DESCR_ENABLE BIT_3 443 #define CF_DATA_SEG_DESCR_ENABLE BIT_2 444 #define CF_READ_DATA BIT_1 445 #define CF_WRITE_DATA BIT_0 446 447 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 448 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 449 450 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 451 452 uint32_t byte_count; /* Total byte count. */ 453 454 uint8_t port_id[3]; /* PortID of destination port. */ 455 uint8_t vp_index; 456 457 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ 458 uint32_t fcp_data_dseg_len; /* Data segment length. */ 459 }; 460 461 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */ 462 struct cmd_type_7 { 463 uint8_t entry_type; /* Entry type. */ 464 uint8_t entry_count; /* Entry count. */ 465 uint8_t sys_define; /* System defined. */ 466 uint8_t entry_status; /* Entry Status. */ 467 468 uint32_t handle; /* System handle. */ 469 470 uint16_t nport_handle; /* N_PORT handle. */ 471 uint16_t timeout; /* Command timeout. */ 472 #define FW_MAX_TIMEOUT 0x1999 473 474 uint16_t dseg_count; /* Data segment count. */ 475 uint16_t reserved_1; 476 477 struct scsi_lun lun; /* FCP LUN (BE). */ 478 479 uint16_t task_mgmt_flags; /* Task management flags. */ 480 #define TMF_CLEAR_ACA BIT_14 481 #define TMF_TARGET_RESET BIT_13 482 #define TMF_LUN_RESET BIT_12 483 #define TMF_CLEAR_TASK_SET BIT_10 484 #define TMF_ABORT_TASK_SET BIT_9 485 #define TMF_DSD_LIST_ENABLE BIT_2 486 #define TMF_READ_DATA BIT_1 487 #define TMF_WRITE_DATA BIT_0 488 489 uint8_t task; 490 #define TSK_SIMPLE 0 491 #define TSK_HEAD_OF_QUEUE 1 492 #define TSK_ORDERED 2 493 #define TSK_ACA 4 494 #define TSK_UNTAGGED 5 495 496 uint8_t crn; 497 498 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ 499 uint32_t byte_count; /* Total byte count. */ 500 501 uint8_t port_id[3]; /* PortID of destination port. */ 502 uint8_t vp_index; 503 504 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 505 uint32_t dseg_0_len; /* Data segment 0 length. */ 506 }; 507 508 #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6) 509 * (T10-DIF) */ 510 struct cmd_type_crc_2 { 511 uint8_t entry_type; /* Entry type. */ 512 uint8_t entry_count; /* Entry count. */ 513 uint8_t sys_define; /* System defined. */ 514 uint8_t entry_status; /* Entry Status. */ 515 516 uint32_t handle; /* System handle. */ 517 518 uint16_t nport_handle; /* N_PORT handle. */ 519 uint16_t timeout; /* Command timeout. */ 520 521 uint16_t dseg_count; /* Data segment count. */ 522 523 uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */ 524 525 struct scsi_lun lun; /* FCP LUN (BE). */ 526 527 uint16_t control_flags; /* Control flags. */ 528 529 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 530 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 531 532 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 533 534 uint32_t byte_count; /* Total byte count. */ 535 536 uint8_t port_id[3]; /* PortID of destination port. */ 537 uint8_t vp_index; 538 539 uint32_t crc_context_address[2]; /* Data segment address. */ 540 uint16_t crc_context_len; /* Data segment length. */ 541 uint16_t reserved_1; /* MUST be set to 0. */ 542 }; 543 544 545 /* 546 * ISP queue - status entry structure definition. 547 */ 548 #define STATUS_TYPE 0x03 /* Status entry. */ 549 struct sts_entry_24xx { 550 uint8_t entry_type; /* Entry type. */ 551 uint8_t entry_count; /* Entry count. */ 552 uint8_t sys_define; /* System defined. */ 553 uint8_t entry_status; /* Entry Status. */ 554 555 uint32_t handle; /* System handle. */ 556 557 uint16_t comp_status; /* Completion status. */ 558 uint16_t ox_id; /* OX_ID used by the firmware. */ 559 560 uint32_t residual_len; /* FW calc residual transfer length. */ 561 562 uint16_t reserved_1; 563 uint16_t state_flags; /* State flags. */ 564 #define SF_TRANSFERRED_DATA BIT_11 565 #define SF_FCP_RSP_DMA BIT_0 566 567 uint16_t reserved_2; 568 uint16_t scsi_status; /* SCSI status. */ 569 #define SS_CONFIRMATION_REQ BIT_12 570 571 uint32_t rsp_residual_count; /* FCP RSP residual count. */ 572 573 uint32_t sense_len; /* FCP SENSE length. */ 574 uint32_t rsp_data_len; /* FCP response data length. */ 575 uint8_t data[28]; /* FCP response/sense information. */ 576 /* 577 * If DIF Error is set in comp_status, these additional fields are 578 * defined: 579 * 580 * !!! NOTE: Firmware sends expected/actual DIF data in big endian 581 * format; but all of the "data" field gets swab32-d in the beginning 582 * of qla2x00_status_entry(). 583 * 584 * &data[10] : uint8_t report_runt_bg[2]; - computed guard 585 * &data[12] : uint8_t actual_dif[8]; - DIF Data received 586 * &data[20] : uint8_t expected_dif[8]; - DIF Data computed 587 */ 588 }; 589 590 591 /* 592 * Status entry completion status 593 */ 594 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */ 595 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */ 596 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */ 597 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */ 598 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */ 599 600 /* 601 * ISP queue - marker entry structure definition. 602 */ 603 #define MARKER_TYPE 0x04 /* Marker entry. */ 604 struct mrk_entry_24xx { 605 uint8_t entry_type; /* Entry type. */ 606 uint8_t entry_count; /* Entry count. */ 607 uint8_t handle_count; /* Handle count. */ 608 uint8_t entry_status; /* Entry Status. */ 609 610 uint32_t handle; /* System handle. */ 611 612 uint16_t nport_handle; /* N_PORT handle. */ 613 614 uint8_t modifier; /* Modifier (7-0). */ 615 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 616 #define MK_SYNC_ID 1 /* Synchronize ID */ 617 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 618 uint8_t reserved_1; 619 620 uint8_t reserved_2; 621 uint8_t vp_index; 622 623 uint16_t reserved_3; 624 625 uint8_t lun[8]; /* FCP LUN (BE). */ 626 uint8_t reserved_4[40]; 627 }; 628 629 /* 630 * ISP queue - CT Pass-Through entry structure definition. 631 */ 632 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */ 633 struct ct_entry_24xx { 634 uint8_t entry_type; /* Entry type. */ 635 uint8_t entry_count; /* Entry count. */ 636 uint8_t sys_define; /* System Defined. */ 637 uint8_t entry_status; /* Entry Status. */ 638 639 uint32_t handle; /* System handle. */ 640 641 uint16_t comp_status; /* Completion status. */ 642 643 uint16_t nport_handle; /* N_PORT handle. */ 644 645 uint16_t cmd_dsd_count; 646 647 uint8_t vp_index; 648 uint8_t reserved_1; 649 650 uint16_t timeout; /* Command timeout. */ 651 uint16_t reserved_2; 652 653 uint16_t rsp_dsd_count; 654 655 uint8_t reserved_3[10]; 656 657 uint32_t rsp_byte_count; 658 uint32_t cmd_byte_count; 659 660 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 661 uint32_t dseg_0_len; /* Data segment 0 length. */ 662 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 663 uint32_t dseg_1_len; /* Data segment 1 length. */ 664 }; 665 666 /* 667 * ISP queue - ELS Pass-Through entry structure definition. 668 */ 669 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */ 670 struct els_entry_24xx { 671 uint8_t entry_type; /* Entry type. */ 672 uint8_t entry_count; /* Entry count. */ 673 uint8_t sys_define; /* System Defined. */ 674 uint8_t entry_status; /* Entry Status. */ 675 676 uint32_t handle; /* System handle. */ 677 678 uint16_t reserved_1; 679 680 uint16_t nport_handle; /* N_PORT handle. */ 681 682 uint16_t tx_dsd_count; 683 684 uint8_t vp_index; 685 uint8_t sof_type; 686 #define EST_SOFI3 (1 << 4) 687 #define EST_SOFI2 (3 << 4) 688 689 uint32_t rx_xchg_address; /* Receive exchange address. */ 690 uint16_t rx_dsd_count; 691 692 uint8_t opcode; 693 uint8_t reserved_2; 694 695 uint8_t port_id[3]; 696 uint8_t reserved_3; 697 698 uint16_t reserved_4; 699 700 uint16_t control_flags; /* Control flags. */ 701 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13) 702 #define EPD_ELS_COMMAND (0 << 13) 703 #define EPD_ELS_ACC (1 << 13) 704 #define EPD_ELS_RJT (2 << 13) 705 #define EPD_RX_XCHG (3 << 13) 706 #define ECF_CLR_PASSTHRU_PEND BIT_12 707 #define ECF_INCL_FRAME_HDR BIT_11 708 709 uint32_t rx_byte_count; 710 uint32_t tx_byte_count; 711 712 uint32_t tx_address[2]; /* Data segment 0 address. */ 713 uint32_t tx_len; /* Data segment 0 length. */ 714 uint32_t rx_address[2]; /* Data segment 1 address. */ 715 uint32_t rx_len; /* Data segment 1 length. */ 716 }; 717 718 struct els_sts_entry_24xx { 719 uint8_t entry_type; /* Entry type. */ 720 uint8_t entry_count; /* Entry count. */ 721 uint8_t sys_define; /* System Defined. */ 722 uint8_t entry_status; /* Entry Status. */ 723 724 uint32_t handle; /* System handle. */ 725 726 uint16_t comp_status; 727 728 uint16_t nport_handle; /* N_PORT handle. */ 729 730 uint16_t reserved_1; 731 732 uint8_t vp_index; 733 uint8_t sof_type; 734 735 uint32_t rx_xchg_address; /* Receive exchange address. */ 736 uint16_t reserved_2; 737 738 uint8_t opcode; 739 uint8_t reserved_3; 740 741 uint8_t port_id[3]; 742 uint8_t reserved_4; 743 744 uint16_t reserved_5; 745 746 uint16_t control_flags; /* Control flags. */ 747 uint32_t total_byte_count; 748 uint32_t error_subcode_1; 749 uint32_t error_subcode_2; 750 }; 751 /* 752 * ISP queue - Mailbox Command entry structure definition. 753 */ 754 #define MBX_IOCB_TYPE 0x39 755 struct mbx_entry_24xx { 756 uint8_t entry_type; /* Entry type. */ 757 uint8_t entry_count; /* Entry count. */ 758 uint8_t handle_count; /* Handle count. */ 759 uint8_t entry_status; /* Entry Status. */ 760 761 uint32_t handle; /* System handle. */ 762 763 uint16_t mbx[28]; 764 }; 765 766 767 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */ 768 struct logio_entry_24xx { 769 uint8_t entry_type; /* Entry type. */ 770 uint8_t entry_count; /* Entry count. */ 771 uint8_t sys_define; /* System defined. */ 772 uint8_t entry_status; /* Entry Status. */ 773 774 uint32_t handle; /* System handle. */ 775 776 uint16_t comp_status; /* Completion status. */ 777 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */ 778 779 uint16_t nport_handle; /* N_PORT handle. */ 780 781 uint16_t control_flags; /* Control flags. */ 782 /* Modifiers. */ 783 #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ 784 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ 785 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ 786 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ 787 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */ 788 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */ 789 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */ 790 #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */ 791 #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */ 792 #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */ 793 /* Commands. */ 794 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */ 795 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */ 796 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */ 797 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */ 798 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */ 799 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */ 800 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */ 801 802 uint8_t vp_index; 803 uint8_t reserved_1; 804 805 uint8_t port_id[3]; /* PortID of destination port. */ 806 807 uint8_t rsp_size; /* Response size in 32bit words. */ 808 809 uint32_t io_parameter[11]; /* General I/O parameters. */ 810 #define LSC_SCODE_NOLINK 0x01 811 #define LSC_SCODE_NOIOCB 0x02 812 #define LSC_SCODE_NOXCB 0x03 813 #define LSC_SCODE_CMD_FAILED 0x04 814 #define LSC_SCODE_NOFABRIC 0x05 815 #define LSC_SCODE_FW_NOT_READY 0x07 816 #define LSC_SCODE_NOT_LOGGED_IN 0x09 817 #define LSC_SCODE_NOPCB 0x0A 818 819 #define LSC_SCODE_ELS_REJECT 0x18 820 #define LSC_SCODE_CMD_PARAM_ERR 0x19 821 #define LSC_SCODE_PORTID_USED 0x1A 822 #define LSC_SCODE_NPORT_USED 0x1B 823 #define LSC_SCODE_NONPORT 0x1C 824 #define LSC_SCODE_LOGGED_IN 0x1D 825 #define LSC_SCODE_NOFLOGI_ACC 0x1F 826 }; 827 828 #define TSK_MGMT_IOCB_TYPE 0x14 829 struct tsk_mgmt_entry { 830 uint8_t entry_type; /* Entry type. */ 831 uint8_t entry_count; /* Entry count. */ 832 uint8_t handle_count; /* Handle count. */ 833 uint8_t entry_status; /* Entry Status. */ 834 835 uint32_t handle; /* System handle. */ 836 837 uint16_t nport_handle; /* N_PORT handle. */ 838 839 uint16_t reserved_1; 840 841 uint16_t delay; /* Activity delay in seconds. */ 842 843 uint16_t timeout; /* Command timeout. */ 844 845 struct scsi_lun lun; /* FCP LUN (BE). */ 846 847 uint32_t control_flags; /* Control Flags. */ 848 #define TCF_NOTMCMD_TO_TARGET BIT_31 849 #define TCF_LUN_RESET BIT_4 850 #define TCF_ABORT_TASK_SET BIT_3 851 #define TCF_CLEAR_TASK_SET BIT_2 852 #define TCF_TARGET_RESET BIT_1 853 #define TCF_CLEAR_ACA BIT_0 854 855 uint8_t reserved_2[20]; 856 857 uint8_t port_id[3]; /* PortID of destination port. */ 858 uint8_t vp_index; 859 860 uint8_t reserved_3[12]; 861 }; 862 863 #define ABORT_IOCB_TYPE 0x33 864 struct abort_entry_24xx { 865 uint8_t entry_type; /* Entry type. */ 866 uint8_t entry_count; /* Entry count. */ 867 uint8_t handle_count; /* Handle count. */ 868 uint8_t entry_status; /* Entry Status. */ 869 870 uint32_t handle; /* System handle. */ 871 872 uint16_t nport_handle; /* N_PORT handle. */ 873 /* or Completion status. */ 874 875 uint16_t options; /* Options. */ 876 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ 877 878 uint32_t handle_to_abort; /* System handle to abort. */ 879 880 uint16_t req_que_no; 881 uint8_t reserved_1[30]; 882 883 uint8_t port_id[3]; /* PortID of destination port. */ 884 uint8_t vp_index; 885 886 uint8_t reserved_2[12]; 887 }; 888 889 /* 890 * ISP I/O Register Set structure definitions. 891 */ 892 struct device_reg_24xx { 893 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */ 894 #define FARX_DATA_FLAG BIT_31 895 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 896 #define FARX_ACCESS_FLASH_DATA 0x7FF00000 897 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000 898 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000 899 900 #define FA_NVRAM_FUNC0_ADDR 0x80 901 #define FA_NVRAM_FUNC1_ADDR 0x180 902 903 #define FA_NVRAM_VPD_SIZE 0x200 904 #define FA_NVRAM_VPD0_ADDR 0x00 905 #define FA_NVRAM_VPD1_ADDR 0x100 906 907 #define FA_BOOT_CODE_ADDR 0x00000 908 /* 909 * RISC code begins at offset 512KB 910 * within flash. Consisting of two 911 * contiguous RISC code segments. 912 */ 913 #define FA_RISC_CODE_ADDR 0x20000 914 #define FA_RISC_CODE_SEGMENTS 2 915 916 #define FA_FLASH_DESCR_ADDR_24 0x11000 917 #define FA_FLASH_LAYOUT_ADDR_24 0x11400 918 #define FA_NPIV_CONF0_ADDR_24 0x16000 919 #define FA_NPIV_CONF1_ADDR_24 0x17000 920 921 #define FA_FW_AREA_ADDR 0x40000 922 #define FA_VPD_NVRAM_ADDR 0x48000 923 #define FA_FEATURE_ADDR 0x4C000 924 #define FA_FLASH_DESCR_ADDR 0x50000 925 #define FA_FLASH_LAYOUT_ADDR 0x50400 926 #define FA_HW_EVENT0_ADDR 0x54000 927 #define FA_HW_EVENT1_ADDR 0x54400 928 #define FA_HW_EVENT_SIZE 0x200 929 #define FA_HW_EVENT_ENTRY_SIZE 4 930 #define FA_NPIV_CONF0_ADDR 0x5C000 931 #define FA_NPIV_CONF1_ADDR 0x5D000 932 #define FA_FCP_PRIO0_ADDR 0x10000 933 #define FA_FCP_PRIO1_ADDR 0x12000 934 935 /* 936 * Flash Error Log Event Codes. 937 */ 938 #define HW_EVENT_RESET_ERR 0xF00B 939 #define HW_EVENT_ISP_ERR 0xF020 940 #define HW_EVENT_PARITY_ERR 0xF022 941 #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023 942 #define HW_EVENT_FLASH_FW_ERR 0xF024 943 944 uint32_t flash_data; /* Flash/NVRAM BIOS data. */ 945 946 uint32_t ctrl_status; /* Control/Status. */ 947 #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */ 948 #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */ 949 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */ 950 #define CSRX_FUNCTION BIT_15 /* Function number. */ 951 /* PCI-X Bus Mode. */ 952 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8) 953 #define PBM_PCI_33MHZ (0 << 8) 954 #define PBM_PCIX_M1_66MHZ (1 << 8) 955 #define PBM_PCIX_M1_100MHZ (2 << 8) 956 #define PBM_PCIX_M1_133MHZ (3 << 8) 957 #define PBM_PCIX_M2_66MHZ (5 << 8) 958 #define PBM_PCIX_M2_100MHZ (6 << 8) 959 #define PBM_PCIX_M2_133MHZ (7 << 8) 960 #define PBM_PCI_66MHZ (8 << 8) 961 /* Max Write Burst byte count. */ 962 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4) 963 #define MWB_512_BYTES (0 << 4) 964 #define MWB_1024_BYTES (1 << 4) 965 #define MWB_2048_BYTES (2 << 4) 966 #define MWB_4096_BYTES (3 << 4) 967 968 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */ 969 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */ 970 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ 971 972 uint32_t ictrl; /* Interrupt control. */ 973 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */ 974 975 uint32_t istatus; /* Interrupt status. */ 976 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */ 977 978 uint32_t unused_1[2]; /* Gap. */ 979 980 /* Request Queue. */ 981 uint32_t req_q_in; /* In-Pointer. */ 982 uint32_t req_q_out; /* Out-Pointer. */ 983 /* Response Queue. */ 984 uint32_t rsp_q_in; /* In-Pointer. */ 985 uint32_t rsp_q_out; /* Out-Pointer. */ 986 /* Priority Request Queue. */ 987 uint32_t preq_q_in; /* In-Pointer. */ 988 uint32_t preq_q_out; /* Out-Pointer. */ 989 990 uint32_t unused_2[2]; /* Gap. */ 991 992 /* ATIO Queue. */ 993 uint32_t atio_q_in; /* In-Pointer. */ 994 uint32_t atio_q_out; /* Out-Pointer. */ 995 996 uint32_t host_status; 997 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ 998 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ 999 1000 uint32_t hccr; /* Host command & control register. */ 1001 /* HCCR statuses. */ 1002 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ 1003 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 1004 /* HCCR commands. */ 1005 /* NOOP. */ 1006 #define HCCRX_NOOP 0x00000000 1007 /* Set RISC Reset. */ 1008 #define HCCRX_SET_RISC_RESET 0x10000000 1009 /* Clear RISC Reset. */ 1010 #define HCCRX_CLR_RISC_RESET 0x20000000 1011 /* Set RISC Pause. */ 1012 #define HCCRX_SET_RISC_PAUSE 0x30000000 1013 /* Releases RISC Pause. */ 1014 #define HCCRX_REL_RISC_PAUSE 0x40000000 1015 /* Set HOST to RISC interrupt. */ 1016 #define HCCRX_SET_HOST_INT 0x50000000 1017 /* Clear HOST to RISC interrupt. */ 1018 #define HCCRX_CLR_HOST_INT 0x60000000 1019 /* Clear RISC to PCI interrupt. */ 1020 #define HCCRX_CLR_RISC_INT 0xA0000000 1021 1022 uint32_t gpiod; /* GPIO Data register. */ 1023 1024 /* LED update mask. */ 1025 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) 1026 /* Data update mask. */ 1027 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) 1028 /* Data update mask. */ 1029 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 1030 /* LED control mask. */ 1031 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) 1032 /* LED bit values. Color names as 1033 * referenced in fw spec. 1034 */ 1035 #define GPDX_LED_YELLOW_ON BIT_2 1036 #define GPDX_LED_GREEN_ON BIT_3 1037 #define GPDX_LED_AMBER_ON BIT_4 1038 /* Data in/out. */ 1039 #define GPDX_DATA_INOUT (BIT_1|BIT_0) 1040 1041 uint32_t gpioe; /* GPIO Enable register. */ 1042 /* Enable update mask. */ 1043 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) 1044 /* Enable update mask. */ 1045 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 1046 /* Enable. */ 1047 #define GPEX_ENABLE (BIT_1|BIT_0) 1048 1049 uint32_t iobase_addr; /* I/O Bus Base Address register. */ 1050 1051 uint32_t unused_3[10]; /* Gap. */ 1052 1053 uint16_t mailbox0; 1054 uint16_t mailbox1; 1055 uint16_t mailbox2; 1056 uint16_t mailbox3; 1057 uint16_t mailbox4; 1058 uint16_t mailbox5; 1059 uint16_t mailbox6; 1060 uint16_t mailbox7; 1061 uint16_t mailbox8; 1062 uint16_t mailbox9; 1063 uint16_t mailbox10; 1064 uint16_t mailbox11; 1065 uint16_t mailbox12; 1066 uint16_t mailbox13; 1067 uint16_t mailbox14; 1068 uint16_t mailbox15; 1069 uint16_t mailbox16; 1070 uint16_t mailbox17; 1071 uint16_t mailbox18; 1072 uint16_t mailbox19; 1073 uint16_t mailbox20; 1074 uint16_t mailbox21; 1075 uint16_t mailbox22; 1076 uint16_t mailbox23; 1077 uint16_t mailbox24; 1078 uint16_t mailbox25; 1079 uint16_t mailbox26; 1080 uint16_t mailbox27; 1081 uint16_t mailbox28; 1082 uint16_t mailbox29; 1083 uint16_t mailbox30; 1084 uint16_t mailbox31; 1085 1086 uint32_t iobase_window; 1087 uint32_t iobase_c4; 1088 uint32_t iobase_c8; 1089 uint32_t unused_4_1[6]; /* Gap. */ 1090 uint32_t iobase_q; 1091 uint32_t unused_5[2]; /* Gap. */ 1092 uint32_t iobase_select; 1093 uint32_t unused_6[2]; /* Gap. */ 1094 uint32_t iobase_sdata; 1095 }; 1096 /* RISC-RISC semaphore register PCI offet */ 1097 #define RISC_REGISTER_BASE_OFFSET 0x7010 1098 #define RISC_REGISTER_WINDOW_OFFET 0x6 1099 1100 /* RISC-RISC semaphore/flag register (risc address 0x7016) */ 1101 1102 #define RISC_SEMAPHORE 0x1UL 1103 #define RISC_SEMAPHORE_WE (RISC_SEMAPHORE << 16) 1104 #define RISC_SEMAPHORE_CLR (RISC_SEMAPHORE_WE | 0x0UL) 1105 #define RISC_SEMAPHORE_SET (RISC_SEMAPHORE_WE | RISC_SEMAPHORE) 1106 1107 #define RISC_SEMAPHORE_FORCE 0x8000UL 1108 #define RISC_SEMAPHORE_FORCE_WE (RISC_SEMAPHORE_FORCE << 16) 1109 #define RISC_SEMAPHORE_FORCE_CLR (RISC_SEMAPHORE_FORCE_WE | 0x0UL) 1110 #define RISC_SEMAPHORE_FORCE_SET \ 1111 (RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE) 1112 1113 /* RISC semaphore timeouts (ms) */ 1114 #define TIMEOUT_SEMAPHORE 2500 1115 #define TIMEOUT_SEMAPHORE_FORCE 2000 1116 #define TIMEOUT_TOTAL_ELAPSED 4500 1117 1118 /* Trace Control *************************************************************/ 1119 1120 #define TC_AEN_DISABLE 0 1121 1122 #define TC_EFT_ENABLE 4 1123 #define TC_EFT_DISABLE 5 1124 1125 #define TC_FCE_ENABLE 8 1126 #define TC_FCE_OPTIONS 0 1127 #define TC_FCE_DEFAULT_RX_SIZE 2112 1128 #define TC_FCE_DEFAULT_TX_SIZE 2112 1129 #define TC_FCE_DISABLE 9 1130 #define TC_FCE_DISABLE_TRACE BIT_0 1131 1132 /* MID Support ***************************************************************/ 1133 1134 #define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */ 1135 #define MAX_MULTI_ID_FABRIC 256 /* ... */ 1136 1137 #define for_each_mapped_vp_idx(_ha, _idx) \ 1138 for (_idx = find_next_bit((_ha)->vp_idx_map, \ 1139 (_ha)->max_npiv_vports + 1, 1); \ 1140 _idx <= (_ha)->max_npiv_vports; \ 1141 _idx = find_next_bit((_ha)->vp_idx_map, \ 1142 (_ha)->max_npiv_vports + 1, _idx + 1)) \ 1143 1144 struct mid_conf_entry_24xx { 1145 uint16_t reserved_1; 1146 1147 /* 1148 * BIT 0 = Enable Hard Loop Id 1149 * BIT 1 = Acquire Loop ID in LIPA 1150 * BIT 2 = ID not Acquired 1151 * BIT 3 = Enable VP 1152 * BIT 4 = Enable Initiator Mode 1153 * BIT 5 = Disable Target Mode 1154 * BIT 6-7 = Reserved 1155 */ 1156 uint8_t options; 1157 1158 uint8_t hard_address; 1159 1160 uint8_t port_name[WWN_SIZE]; 1161 uint8_t node_name[WWN_SIZE]; 1162 }; 1163 1164 struct mid_init_cb_24xx { 1165 struct init_cb_24xx init_cb; 1166 1167 uint16_t count; 1168 uint16_t options; 1169 1170 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 1171 }; 1172 1173 1174 struct mid_db_entry_24xx { 1175 uint16_t status; 1176 #define MDBS_NON_PARTIC BIT_3 1177 #define MDBS_ID_ACQUIRED BIT_1 1178 #define MDBS_ENABLED BIT_0 1179 1180 uint8_t options; 1181 uint8_t hard_address; 1182 1183 uint8_t port_name[WWN_SIZE]; 1184 uint8_t node_name[WWN_SIZE]; 1185 1186 uint8_t port_id[3]; 1187 uint8_t reserved_1; 1188 }; 1189 1190 /* 1191 * Virtual Port Control IOCB 1192 */ 1193 #define VP_CTRL_IOCB_TYPE 0x30 /* Virtual Port Control entry. */ 1194 struct vp_ctrl_entry_24xx { 1195 uint8_t entry_type; /* Entry type. */ 1196 uint8_t entry_count; /* Entry count. */ 1197 uint8_t sys_define; /* System defined. */ 1198 uint8_t entry_status; /* Entry Status. */ 1199 1200 uint32_t handle; /* System handle. */ 1201 1202 uint16_t vp_idx_failed; 1203 1204 uint16_t comp_status; /* Completion status. */ 1205 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */ 1206 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */ 1207 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1208 1209 uint16_t command; 1210 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */ 1211 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */ 1212 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */ 1213 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */ 1214 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */ 1215 1216 uint16_t vp_count; 1217 1218 uint8_t vp_idx_map[16]; 1219 uint16_t flags; 1220 uint16_t id; 1221 uint16_t reserved_4; 1222 uint16_t hopct; 1223 uint8_t reserved_5[24]; 1224 }; 1225 1226 /* 1227 * Modify Virtual Port Configuration IOCB 1228 */ 1229 #define VP_CONFIG_IOCB_TYPE 0x31 /* Virtual Port Config entry. */ 1230 struct vp_config_entry_24xx { 1231 uint8_t entry_type; /* Entry type. */ 1232 uint8_t entry_count; /* Entry count. */ 1233 uint8_t handle_count; 1234 uint8_t entry_status; /* Entry Status. */ 1235 1236 uint32_t handle; /* System handle. */ 1237 1238 uint16_t flags; 1239 #define CS_VF_BIND_VPORTS_TO_VF BIT_0 1240 #define CS_VF_SET_QOS_OF_VPORTS BIT_1 1241 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2 1242 1243 uint16_t comp_status; /* Completion status. */ 1244 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */ 1245 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */ 1246 #define CS_VCT_ERROR 0x03 /* Unknown error. */ 1247 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */ 1248 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1249 1250 uint8_t command; 1251 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */ 1252 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */ 1253 1254 uint8_t vp_count; 1255 1256 uint8_t vp_index1; 1257 uint8_t vp_index2; 1258 1259 uint8_t options_idx1; 1260 uint8_t hard_address_idx1; 1261 uint16_t reserved_vp1; 1262 uint8_t port_name_idx1[WWN_SIZE]; 1263 uint8_t node_name_idx1[WWN_SIZE]; 1264 1265 uint8_t options_idx2; 1266 uint8_t hard_address_idx2; 1267 uint16_t reserved_vp2; 1268 uint8_t port_name_idx2[WWN_SIZE]; 1269 uint8_t node_name_idx2[WWN_SIZE]; 1270 uint16_t id; 1271 uint16_t reserved_4; 1272 uint16_t hopct; 1273 uint8_t reserved_5[2]; 1274 }; 1275 1276 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */ 1277 struct vp_rpt_id_entry_24xx { 1278 uint8_t entry_type; /* Entry type. */ 1279 uint8_t entry_count; /* Entry count. */ 1280 uint8_t sys_define; /* System defined. */ 1281 uint8_t entry_status; /* Entry Status. */ 1282 1283 uint32_t handle; /* System handle. */ 1284 1285 uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */ 1286 /* Format 1 -- | VP count |. */ 1287 uint16_t vp_idx; /* Format 0 -- Reserved. */ 1288 /* Format 1 -- VP status and index. */ 1289 1290 uint8_t port_id[3]; 1291 uint8_t format; 1292 1293 uint8_t vp_idx_map[16]; 1294 1295 uint8_t reserved_4[32]; 1296 }; 1297 1298 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */ 1299 struct vf_evfp_entry_24xx { 1300 uint8_t entry_type; /* Entry type. */ 1301 uint8_t entry_count; /* Entry count. */ 1302 uint8_t sys_define; /* System defined. */ 1303 uint8_t entry_status; /* Entry Status. */ 1304 1305 uint32_t handle; /* System handle. */ 1306 uint16_t comp_status; /* Completion status. */ 1307 uint16_t timeout; /* timeout */ 1308 uint16_t adim_tagging_mode; 1309 1310 uint16_t vfport_id; 1311 uint32_t exch_addr; 1312 1313 uint16_t nport_handle; /* N_PORT handle. */ 1314 uint16_t control_flags; 1315 uint32_t io_parameter_0; 1316 uint32_t io_parameter_1; 1317 uint32_t tx_address[2]; /* Data segment 0 address. */ 1318 uint32_t tx_len; /* Data segment 0 length. */ 1319 uint32_t rx_address[2]; /* Data segment 1 address. */ 1320 uint32_t rx_len; /* Data segment 1 length. */ 1321 }; 1322 1323 /* END MID Support ***********************************************************/ 1324 1325 /* Flash Description Table ***************************************************/ 1326 1327 struct qla_fdt_layout { 1328 uint8_t sig[4]; 1329 uint16_t version; 1330 uint16_t len; 1331 uint16_t checksum; 1332 uint8_t unused1[2]; 1333 uint8_t model[16]; 1334 uint16_t man_id; 1335 uint16_t id; 1336 uint8_t flags; 1337 uint8_t erase_cmd; 1338 uint8_t alt_erase_cmd; 1339 uint8_t wrt_enable_cmd; 1340 uint8_t wrt_enable_bits; 1341 uint8_t wrt_sts_reg_cmd; 1342 uint8_t unprotect_sec_cmd; 1343 uint8_t read_man_id_cmd; 1344 uint32_t block_size; 1345 uint32_t alt_block_size; 1346 uint32_t flash_size; 1347 uint32_t wrt_enable_data; 1348 uint8_t read_id_addr_len; 1349 uint8_t wrt_disable_bits; 1350 uint8_t read_dev_id_len; 1351 uint8_t chip_erase_cmd; 1352 uint16_t read_timeout; 1353 uint8_t protect_sec_cmd; 1354 uint8_t unused2[65]; 1355 }; 1356 1357 /* Flash Layout Table ********************************************************/ 1358 1359 struct qla_flt_location { 1360 uint8_t sig[4]; 1361 uint16_t start_lo; 1362 uint16_t start_hi; 1363 uint8_t version; 1364 uint8_t unused[5]; 1365 uint16_t checksum; 1366 }; 1367 1368 struct qla_flt_header { 1369 uint16_t version; 1370 uint16_t length; 1371 uint16_t checksum; 1372 uint16_t unused; 1373 }; 1374 1375 #define FLT_REG_FW 0x01 1376 #define FLT_REG_BOOT_CODE 0x07 1377 #define FLT_REG_VPD_0 0x14 1378 #define FLT_REG_NVRAM_0 0x15 1379 #define FLT_REG_VPD_1 0x16 1380 #define FLT_REG_NVRAM_1 0x17 1381 #define FLT_REG_VPD_2 0xD4 1382 #define FLT_REG_NVRAM_2 0xD5 1383 #define FLT_REG_VPD_3 0xD6 1384 #define FLT_REG_NVRAM_3 0xD7 1385 #define FLT_REG_FDT 0x1a 1386 #define FLT_REG_FLT 0x1c 1387 #define FLT_REG_HW_EVENT_0 0x1d 1388 #define FLT_REG_HW_EVENT_1 0x1f 1389 #define FLT_REG_NPIV_CONF_0 0x29 1390 #define FLT_REG_NPIV_CONF_1 0x2a 1391 #define FLT_REG_GOLD_FW 0x2f 1392 #define FLT_REG_FCP_PRIO_0 0x87 1393 #define FLT_REG_FCP_PRIO_1 0x88 1394 #define FLT_REG_CNA_FW 0x97 1395 #define FLT_REG_BOOT_CODE_8044 0xA2 1396 #define FLT_REG_FCOE_FW 0xA4 1397 #define FLT_REG_FCOE_NVRAM_0 0xAA 1398 #define FLT_REG_FCOE_NVRAM_1 0xAC 1399 1400 struct qla_flt_region { 1401 uint32_t code; 1402 uint32_t size; 1403 uint32_t start; 1404 uint32_t end; 1405 }; 1406 1407 /* Flash NPIV Configuration Table ********************************************/ 1408 1409 struct qla_npiv_header { 1410 uint8_t sig[2]; 1411 uint16_t version; 1412 uint16_t entries; 1413 uint16_t unused[4]; 1414 uint16_t checksum; 1415 }; 1416 1417 struct qla_npiv_entry { 1418 uint16_t flags; 1419 uint16_t vf_id; 1420 uint8_t q_qos; 1421 uint8_t f_qos; 1422 uint16_t unused1; 1423 uint8_t port_name[WWN_SIZE]; 1424 uint8_t node_name[WWN_SIZE]; 1425 }; 1426 1427 /* 84XX Support **************************************************************/ 1428 1429 #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */ 1430 #define A84_PANIC_RECOVERY 0x1 1431 #define A84_OP_LOGIN_COMPLETE 0x2 1432 #define A84_DIAG_LOGIN_COMPLETE 0x3 1433 #define A84_GOLD_LOGIN_COMPLETE 0x4 1434 1435 #define MBC_ISP84XX_RESET 0x3a /* Reset. */ 1436 1437 #define FSTATE_REMOTE_FC_DOWN BIT_0 1438 #define FSTATE_NSL_LINK_DOWN BIT_1 1439 #define FSTATE_IS_DIAG_FW BIT_2 1440 #define FSTATE_LOGGED_IN BIT_3 1441 #define FSTATE_WAITING_FOR_VERIFY BIT_4 1442 1443 #define VERIFY_CHIP_IOCB_TYPE 0x1B 1444 struct verify_chip_entry_84xx { 1445 uint8_t entry_type; 1446 uint8_t entry_count; 1447 uint8_t sys_defined; 1448 uint8_t entry_status; 1449 1450 uint32_t handle; 1451 1452 uint16_t options; 1453 #define VCO_DONT_UPDATE_FW BIT_0 1454 #define VCO_FORCE_UPDATE BIT_1 1455 #define VCO_DONT_RESET_UPDATE BIT_2 1456 #define VCO_DIAG_FW BIT_3 1457 #define VCO_END_OF_DATA BIT_14 1458 #define VCO_ENABLE_DSD BIT_15 1459 1460 uint16_t reserved_1; 1461 1462 uint16_t data_seg_cnt; 1463 uint16_t reserved_2[3]; 1464 1465 uint32_t fw_ver; 1466 uint32_t exchange_address; 1467 1468 uint32_t reserved_3[3]; 1469 uint32_t fw_size; 1470 uint32_t fw_seq_size; 1471 uint32_t relative_offset; 1472 1473 uint32_t dseg_address[2]; 1474 uint32_t dseg_length; 1475 }; 1476 1477 struct verify_chip_rsp_84xx { 1478 uint8_t entry_type; 1479 uint8_t entry_count; 1480 uint8_t sys_defined; 1481 uint8_t entry_status; 1482 1483 uint32_t handle; 1484 1485 uint16_t comp_status; 1486 #define CS_VCS_CHIP_FAILURE 0x3 1487 #define CS_VCS_BAD_EXCHANGE 0x8 1488 #define CS_VCS_SEQ_COMPLETEi 0x40 1489 1490 uint16_t failure_code; 1491 #define VFC_CHECKSUM_ERROR 0x1 1492 #define VFC_INVALID_LEN 0x2 1493 #define VFC_ALREADY_IN_PROGRESS 0x8 1494 1495 uint16_t reserved_1[4]; 1496 1497 uint32_t fw_ver; 1498 uint32_t exchange_address; 1499 1500 uint32_t reserved_2[6]; 1501 }; 1502 1503 #define ACCESS_CHIP_IOCB_TYPE 0x2B 1504 struct access_chip_84xx { 1505 uint8_t entry_type; 1506 uint8_t entry_count; 1507 uint8_t sys_defined; 1508 uint8_t entry_status; 1509 1510 uint32_t handle; 1511 1512 uint16_t options; 1513 #define ACO_DUMP_MEMORY 0x0 1514 #define ACO_LOAD_MEMORY 0x1 1515 #define ACO_CHANGE_CONFIG_PARAM 0x2 1516 #define ACO_REQUEST_INFO 0x3 1517 1518 uint16_t reserved1; 1519 1520 uint16_t dseg_count; 1521 uint16_t reserved2[3]; 1522 1523 uint32_t parameter1; 1524 uint32_t parameter2; 1525 uint32_t parameter3; 1526 1527 uint32_t reserved3[3]; 1528 uint32_t total_byte_cnt; 1529 uint32_t reserved4; 1530 1531 uint32_t dseg_address[2]; 1532 uint32_t dseg_length; 1533 }; 1534 1535 struct access_chip_rsp_84xx { 1536 uint8_t entry_type; 1537 uint8_t entry_count; 1538 uint8_t sys_defined; 1539 uint8_t entry_status; 1540 1541 uint32_t handle; 1542 1543 uint16_t comp_status; 1544 uint16_t failure_code; 1545 uint32_t residual_count; 1546 1547 uint32_t reserved[12]; 1548 }; 1549 1550 /* 81XX Support **************************************************************/ 1551 1552 #define MBA_DCBX_START 0x8016 1553 #define MBA_DCBX_COMPLETE 0x8030 1554 #define MBA_FCF_CONF_ERR 0x8031 1555 #define MBA_DCBX_PARAM_UPDATE 0x8032 1556 #define MBA_IDC_COMPLETE 0x8100 1557 #define MBA_IDC_NOTIFY 0x8101 1558 #define MBA_IDC_TIME_EXT 0x8102 1559 1560 #define MBC_IDC_ACK 0x101 1561 #define MBC_RESTART_MPI_FW 0x3d 1562 #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */ 1563 #define MBC_GET_XGMAC_STATS 0x7a 1564 #define MBC_GET_DCBX_PARAMS 0x51 1565 1566 /* 1567 * ISP83xx mailbox commands 1568 */ 1569 #define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */ 1570 #define MBC_READ_REMOTE_REG 0x0009 /* Read remote register */ 1571 #define MBC_RESTART_NIC_FIRMWARE 0x003d /* Restart NIC firmware */ 1572 #define MBC_SET_ACCESS_CONTROL 0x003e /* Access control command */ 1573 1574 /* Flash access control option field bit definitions */ 1575 #define FAC_OPT_FORCE_SEMAPHORE BIT_15 1576 #define FAC_OPT_REQUESTOR_ID BIT_14 1577 #define FAC_OPT_CMD_SUBCODE 0xff 1578 1579 /* Flash access control command subcodes */ 1580 #define FAC_OPT_CMD_WRITE_PROTECT 0x00 1581 #define FAC_OPT_CMD_WRITE_ENABLE 0x01 1582 #define FAC_OPT_CMD_ERASE_SECTOR 0x02 1583 #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03 1584 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04 1585 #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05 1586 1587 struct nvram_81xx { 1588 /* NVRAM header. */ 1589 uint8_t id[4]; 1590 uint16_t nvram_version; 1591 uint16_t reserved_0; 1592 1593 /* Firmware Initialization Control Block. */ 1594 uint16_t version; 1595 uint16_t reserved_1; 1596 uint16_t frame_payload_size; 1597 uint16_t execution_throttle; 1598 uint16_t exchange_count; 1599 uint16_t reserved_2; 1600 1601 uint8_t port_name[WWN_SIZE]; 1602 uint8_t node_name[WWN_SIZE]; 1603 1604 uint16_t login_retry_count; 1605 uint16_t reserved_3; 1606 uint16_t interrupt_delay_timer; 1607 uint16_t login_timeout; 1608 1609 uint32_t firmware_options_1; 1610 uint32_t firmware_options_2; 1611 uint32_t firmware_options_3; 1612 1613 uint16_t reserved_4[4]; 1614 1615 /* Offset 64. */ 1616 uint8_t enode_mac[6]; 1617 uint16_t reserved_5[5]; 1618 1619 /* Offset 80. */ 1620 uint16_t reserved_6[24]; 1621 1622 /* Offset 128. */ 1623 uint16_t ex_version; 1624 uint8_t prio_fcf_matching_flags; 1625 uint8_t reserved_6_1[3]; 1626 uint16_t pri_fcf_vlan_id; 1627 uint8_t pri_fcf_fabric_name[8]; 1628 uint16_t reserved_6_2[7]; 1629 uint8_t spma_mac_addr[6]; 1630 uint16_t reserved_6_3[14]; 1631 1632 /* Offset 192. */ 1633 uint16_t reserved_7[32]; 1634 1635 /* 1636 * BIT 0 = Enable spinup delay 1637 * BIT 1 = Disable BIOS 1638 * BIT 2 = Enable Memory Map BIOS 1639 * BIT 3 = Enable Selectable Boot 1640 * BIT 4 = Disable RISC code load 1641 * BIT 5 = Disable Serdes 1642 * BIT 6 = Opt boot mode 1643 * BIT 7 = Interrupt enable 1644 * 1645 * BIT 8 = EV Control enable 1646 * BIT 9 = Enable lip reset 1647 * BIT 10 = Enable lip full login 1648 * BIT 11 = Enable target reset 1649 * BIT 12 = Stop firmware 1650 * BIT 13 = Enable nodename option 1651 * BIT 14 = Default WWPN valid 1652 * BIT 15 = Enable alternate WWN 1653 * 1654 * BIT 16 = CLP LUN string 1655 * BIT 17 = CLP Target string 1656 * BIT 18 = CLP BIOS enable string 1657 * BIT 19 = CLP Serdes string 1658 * BIT 20 = CLP WWPN string 1659 * BIT 21 = CLP WWNN string 1660 * BIT 22 = 1661 * BIT 23 = 1662 * BIT 24 = Keep WWPN 1663 * BIT 25 = Temp WWPN 1664 * BIT 26-31 = 1665 */ 1666 uint32_t host_p; 1667 1668 uint8_t alternate_port_name[WWN_SIZE]; 1669 uint8_t alternate_node_name[WWN_SIZE]; 1670 1671 uint8_t boot_port_name[WWN_SIZE]; 1672 uint16_t boot_lun_number; 1673 uint16_t reserved_8; 1674 1675 uint8_t alt1_boot_port_name[WWN_SIZE]; 1676 uint16_t alt1_boot_lun_number; 1677 uint16_t reserved_9; 1678 1679 uint8_t alt2_boot_port_name[WWN_SIZE]; 1680 uint16_t alt2_boot_lun_number; 1681 uint16_t reserved_10; 1682 1683 uint8_t alt3_boot_port_name[WWN_SIZE]; 1684 uint16_t alt3_boot_lun_number; 1685 uint16_t reserved_11; 1686 1687 /* 1688 * BIT 0 = Selective Login 1689 * BIT 1 = Alt-Boot Enable 1690 * BIT 2 = Reserved 1691 * BIT 3 = Boot Order List 1692 * BIT 4 = Reserved 1693 * BIT 5 = Selective LUN 1694 * BIT 6 = Reserved 1695 * BIT 7-31 = 1696 */ 1697 uint32_t efi_parameters; 1698 1699 uint8_t reset_delay; 1700 uint8_t reserved_12; 1701 uint16_t reserved_13; 1702 1703 uint16_t boot_id_number; 1704 uint16_t reserved_14; 1705 1706 uint16_t max_luns_per_target; 1707 uint16_t reserved_15; 1708 1709 uint16_t port_down_retry_count; 1710 uint16_t link_down_timeout; 1711 1712 /* FCode parameters. */ 1713 uint16_t fcode_parameter; 1714 1715 uint16_t reserved_16[3]; 1716 1717 /* Offset 352. */ 1718 uint8_t reserved_17[4]; 1719 uint16_t reserved_18[5]; 1720 uint8_t reserved_19[2]; 1721 uint16_t reserved_20[8]; 1722 1723 /* Offset 384. */ 1724 uint8_t reserved_21[16]; 1725 uint16_t reserved_22[3]; 1726 1727 /* 1728 * BIT 0 = Extended BB credits for LR 1729 * BIT 1 = Virtual Fabric Enable 1730 * BIT 2 = Enhanced Features Unused 1731 * BIT 3-7 = Enhanced Features Reserved 1732 */ 1733 /* Enhanced Features */ 1734 uint8_t enhanced_features; 1735 1736 uint8_t reserved_23; 1737 uint16_t reserved_24[4]; 1738 1739 /* Offset 416. */ 1740 uint16_t reserved_25[32]; 1741 1742 /* Offset 480. */ 1743 uint8_t model_name[16]; 1744 1745 /* Offset 496. */ 1746 uint16_t feature_mask_l; 1747 uint16_t feature_mask_h; 1748 uint16_t reserved_26[2]; 1749 1750 uint16_t subsystem_vendor_id; 1751 uint16_t subsystem_device_id; 1752 1753 uint32_t checksum; 1754 }; 1755 1756 /* 1757 * ISP Initialization Control Block. 1758 * Little endian except where noted. 1759 */ 1760 #define ICB_VERSION 1 1761 struct init_cb_81xx { 1762 uint16_t version; 1763 uint16_t reserved_1; 1764 1765 uint16_t frame_payload_size; 1766 uint16_t execution_throttle; 1767 uint16_t exchange_count; 1768 1769 uint16_t reserved_2; 1770 1771 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1772 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1773 1774 uint16_t response_q_inpointer; 1775 uint16_t request_q_outpointer; 1776 1777 uint16_t login_retry_count; 1778 1779 uint16_t prio_request_q_outpointer; 1780 1781 uint16_t response_q_length; 1782 uint16_t request_q_length; 1783 1784 uint16_t reserved_3; 1785 1786 uint16_t prio_request_q_length; 1787 1788 uint32_t request_q_address[2]; 1789 uint32_t response_q_address[2]; 1790 uint32_t prio_request_q_address[2]; 1791 1792 uint8_t reserved_4[8]; 1793 1794 uint16_t atio_q_inpointer; 1795 uint16_t atio_q_length; 1796 uint32_t atio_q_address[2]; 1797 1798 uint16_t interrupt_delay_timer; /* 100us increments. */ 1799 uint16_t login_timeout; 1800 1801 /* 1802 * BIT 0-3 = Reserved 1803 * BIT 4 = Enable Target Mode 1804 * BIT 5 = Disable Initiator Mode 1805 * BIT 6 = Reserved 1806 * BIT 7 = Reserved 1807 * 1808 * BIT 8-13 = Reserved 1809 * BIT 14 = Node Name Option 1810 * BIT 15-31 = Reserved 1811 */ 1812 uint32_t firmware_options_1; 1813 1814 /* 1815 * BIT 0 = Operation Mode bit 0 1816 * BIT 1 = Operation Mode bit 1 1817 * BIT 2 = Operation Mode bit 2 1818 * BIT 3 = Operation Mode bit 3 1819 * BIT 4-7 = Reserved 1820 * 1821 * BIT 8 = Enable Class 2 1822 * BIT 9 = Enable ACK0 1823 * BIT 10 = Reserved 1824 * BIT 11 = Enable FC-SP Security 1825 * BIT 12 = FC Tape Enable 1826 * BIT 13 = Reserved 1827 * BIT 14 = Enable Target PRLI Control 1828 * BIT 15-31 = Reserved 1829 */ 1830 uint32_t firmware_options_2; 1831 1832 /* 1833 * BIT 0-3 = Reserved 1834 * BIT 4 = FCP RSP Payload bit 0 1835 * BIT 5 = FCP RSP Payload bit 1 1836 * BIT 6 = Enable Receive Out-of-Order data frame handling 1837 * BIT 7 = Reserved 1838 * 1839 * BIT 8 = Reserved 1840 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 1841 * BIT 10-16 = Reserved 1842 * BIT 17 = Enable multiple FCFs 1843 * BIT 18-20 = MAC addressing mode 1844 * BIT 21-25 = Ethernet data rate 1845 * BIT 26 = Enable ethernet header rx IOCB for ATIO q 1846 * BIT 27 = Enable ethernet header rx IOCB for response q 1847 * BIT 28 = SPMA selection bit 0 1848 * BIT 28 = SPMA selection bit 1 1849 * BIT 30-31 = Reserved 1850 */ 1851 uint32_t firmware_options_3; 1852 1853 uint8_t reserved_5[8]; 1854 1855 uint8_t enode_mac[6]; 1856 1857 uint8_t reserved_6[10]; 1858 }; 1859 1860 struct mid_init_cb_81xx { 1861 struct init_cb_81xx init_cb; 1862 1863 uint16_t count; 1864 uint16_t options; 1865 1866 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 1867 }; 1868 1869 struct ex_init_cb_81xx { 1870 uint16_t ex_version; 1871 uint8_t prio_fcf_matching_flags; 1872 uint8_t reserved_1[3]; 1873 uint16_t pri_fcf_vlan_id; 1874 uint8_t pri_fcf_fabric_name[8]; 1875 uint16_t reserved_2[7]; 1876 uint8_t spma_mac_addr[6]; 1877 uint16_t reserved_3[14]; 1878 }; 1879 1880 #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000 1881 #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000 1882 1883 /* FCP priority config defines *************************************/ 1884 /* operations */ 1885 #define QLFC_FCP_PRIO_DISABLE 0x0 1886 #define QLFC_FCP_PRIO_ENABLE 0x1 1887 #define QLFC_FCP_PRIO_GET_CONFIG 0x2 1888 #define QLFC_FCP_PRIO_SET_CONFIG 0x3 1889 1890 struct qla_fcp_prio_entry { 1891 uint16_t flags; /* Describes parameter(s) in FCP */ 1892 /* priority entry that are valid */ 1893 #define FCP_PRIO_ENTRY_VALID 0x1 1894 #define FCP_PRIO_ENTRY_TAG_VALID 0x2 1895 #define FCP_PRIO_ENTRY_SPID_VALID 0x4 1896 #define FCP_PRIO_ENTRY_DPID_VALID 0x8 1897 #define FCP_PRIO_ENTRY_LUNB_VALID 0x10 1898 #define FCP_PRIO_ENTRY_LUNE_VALID 0x20 1899 #define FCP_PRIO_ENTRY_SWWN_VALID 0x40 1900 #define FCP_PRIO_ENTRY_DWWN_VALID 0x80 1901 uint8_t tag; /* Priority value */ 1902 uint8_t reserved; /* Reserved for future use */ 1903 uint32_t src_pid; /* Src port id. high order byte */ 1904 /* unused; -1 (wild card) */ 1905 uint32_t dst_pid; /* Src port id. high order byte */ 1906 /* unused; -1 (wild card) */ 1907 uint16_t lun_beg; /* 1st lun num of lun range. */ 1908 /* -1 (wild card) */ 1909 uint16_t lun_end; /* 2nd lun num of lun range. */ 1910 /* -1 (wild card) */ 1911 uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */ 1912 uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */ 1913 }; 1914 1915 struct qla_fcp_prio_cfg { 1916 uint8_t signature[4]; /* "HQOS" signature of config data */ 1917 uint16_t version; /* 1: Initial version */ 1918 uint16_t length; /* config data size in num bytes */ 1919 uint16_t checksum; /* config data bytes checksum */ 1920 uint16_t num_entries; /* Number of entries */ 1921 uint16_t size_of_entry; /* Size of each entry in num bytes */ 1922 uint8_t attributes; /* enable/disable, persistence */ 1923 #define FCP_PRIO_ATTR_DISABLE 0x0 1924 #define FCP_PRIO_ATTR_ENABLE 0x1 1925 #define FCP_PRIO_ATTR_PERSIST 0x2 1926 uint8_t reserved; /* Reserved for future use */ 1927 #define FCP_PRIO_CFG_HDR_SIZE 0x10 1928 struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */ 1929 #define FCP_PRIO_CFG_ENTRY_SIZE 0x20 1930 }; 1931 1932 #define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/ 1933 1934 /* 25XX Support ****************************************************/ 1935 #define FA_FCP_PRIO0_ADDR_25 0x3C000 1936 #define FA_FCP_PRIO1_ADDR_25 0x3E000 1937 1938 /* 81XX Flash locations -- occupies second 2MB region. */ 1939 #define FA_BOOT_CODE_ADDR_81 0x80000 1940 #define FA_RISC_CODE_ADDR_81 0xA0000 1941 #define FA_FW_AREA_ADDR_81 0xC0000 1942 #define FA_VPD_NVRAM_ADDR_81 0xD0000 1943 #define FA_VPD0_ADDR_81 0xD0000 1944 #define FA_VPD1_ADDR_81 0xD0400 1945 #define FA_NVRAM0_ADDR_81 0xD0080 1946 #define FA_NVRAM1_ADDR_81 0xD0180 1947 #define FA_FEATURE_ADDR_81 0xD4000 1948 #define FA_FLASH_DESCR_ADDR_81 0xD8000 1949 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400 1950 #define FA_HW_EVENT0_ADDR_81 0xDC000 1951 #define FA_HW_EVENT1_ADDR_81 0xDC400 1952 #define FA_NPIV_CONF0_ADDR_81 0xD1000 1953 #define FA_NPIV_CONF1_ADDR_81 0xD2000 1954 1955 /* 83XX Flash locations -- occupies second 8MB region. */ 1956 #define FA_FLASH_LAYOUT_ADDR_83 0xFC400 1957 1958 #endif 1959