1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2005 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_FW_H 8 #define __QLA_FW_H 9 10 #define RISC_SADDRESS 0x100000 11 #define MBS_CHECKSUM_ERROR 0x4010 12 13 /* 14 * Firmware Options. 15 */ 16 #define FO1_ENABLE_PUREX BIT_10 17 #define FO1_DISABLE_LED_CTRL BIT_6 18 #define FO2_ENABLE_SEL_CLASS2 BIT_5 19 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14 20 21 /* 22 * Port Database structure definition for ISP 24xx. 23 */ 24 #define PDO_FORCE_ADISC BIT_1 25 #define PDO_FORCE_PLOGI BIT_0 26 27 28 #define PORT_DATABASE_24XX_SIZE 64 29 struct port_database_24xx { 30 uint16_t flags; 31 #define PDF_TASK_RETRY_ID BIT_14 32 #define PDF_FC_TAPE BIT_7 33 #define PDF_ACK0_CAPABLE BIT_6 34 #define PDF_FCP2_CONF BIT_5 35 #define PDF_CLASS_2 BIT_4 36 #define PDF_HARD_ADDR BIT_1 37 38 uint8_t current_login_state; 39 uint8_t last_login_state; 40 #define PDS_PLOGI_PENDING 0x03 41 #define PDS_PLOGI_COMPLETE 0x04 42 #define PDS_PRLI_PENDING 0x05 43 #define PDS_PRLI_COMPLETE 0x06 44 #define PDS_PORT_UNAVAILABLE 0x07 45 #define PDS_PRLO_PENDING 0x09 46 #define PDS_LOGO_PENDING 0x11 47 #define PDS_PRLI2_PENDING 0x12 48 49 uint8_t hard_address[3]; 50 uint8_t reserved_1; 51 52 uint8_t port_id[3]; 53 uint8_t sequence_id; 54 55 uint16_t port_timer; 56 57 uint16_t nport_handle; /* N_PORT handle. */ 58 59 uint16_t receive_data_size; 60 uint16_t reserved_2; 61 62 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 63 /* Bits 15-0 of word 0 */ 64 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 65 /* Bits 15-0 of word 3 */ 66 67 uint8_t port_name[WWN_SIZE]; 68 uint8_t node_name[WWN_SIZE]; 69 70 uint8_t reserved_3[24]; 71 }; 72 73 struct nvram_24xx { 74 /* NVRAM header. */ 75 uint8_t id[4]; 76 uint16_t nvram_version; 77 uint16_t reserved_0; 78 79 /* Firmware Initialization Control Block. */ 80 uint16_t version; 81 uint16_t reserved_1; 82 uint16_t frame_payload_size; 83 uint16_t execution_throttle; 84 uint16_t exchange_count; 85 uint16_t hard_address; 86 87 uint8_t port_name[WWN_SIZE]; 88 uint8_t node_name[WWN_SIZE]; 89 90 uint16_t login_retry_count; 91 uint16_t link_down_on_nos; 92 uint16_t interrupt_delay_timer; 93 uint16_t login_timeout; 94 95 uint32_t firmware_options_1; 96 uint32_t firmware_options_2; 97 uint32_t firmware_options_3; 98 99 /* Offset 56. */ 100 101 /* 102 * BIT 0 = Control Enable 103 * BIT 1-15 = 104 * 105 * BIT 0-7 = Reserved 106 * BIT 8-10 = Output Swing 1G 107 * BIT 11-13 = Output Emphasis 1G 108 * BIT 14-15 = Reserved 109 * 110 * BIT 0-7 = Reserved 111 * BIT 8-10 = Output Swing 2G 112 * BIT 11-13 = Output Emphasis 2G 113 * BIT 14-15 = Reserved 114 * 115 * BIT 0-7 = Reserved 116 * BIT 8-10 = Output Swing 4G 117 * BIT 11-13 = Output Emphasis 4G 118 * BIT 14-15 = Reserved 119 */ 120 uint16_t seriallink_options[4]; 121 122 uint16_t reserved_2[16]; 123 124 /* Offset 96. */ 125 uint16_t reserved_3[16]; 126 127 /* PCIe table entries. */ 128 uint16_t reserved_4[16]; 129 130 /* Offset 160. */ 131 uint16_t reserved_5[16]; 132 133 /* Offset 192. */ 134 uint16_t reserved_6[16]; 135 136 /* Offset 224. */ 137 uint16_t reserved_7[16]; 138 139 /* 140 * BIT 0 = Enable spinup delay 141 * BIT 1 = Disable BIOS 142 * BIT 2 = Enable Memory Map BIOS 143 * BIT 3 = Enable Selectable Boot 144 * BIT 4 = Disable RISC code load 145 * BIT 5 = 146 * BIT 6 = 147 * BIT 7 = 148 * 149 * BIT 8 = 150 * BIT 9 = 151 * BIT 10 = Enable lip full login 152 * BIT 11 = Enable target reset 153 * BIT 12 = 154 * BIT 13 = 155 * BIT 14 = 156 * BIT 15 = Enable alternate WWN 157 * 158 * BIT 16-31 = 159 */ 160 uint32_t host_p; 161 162 uint8_t alternate_port_name[WWN_SIZE]; 163 uint8_t alternate_node_name[WWN_SIZE]; 164 165 uint8_t boot_port_name[WWN_SIZE]; 166 uint16_t boot_lun_number; 167 uint16_t reserved_8; 168 169 uint8_t alt1_boot_port_name[WWN_SIZE]; 170 uint16_t alt1_boot_lun_number; 171 uint16_t reserved_9; 172 173 uint8_t alt2_boot_port_name[WWN_SIZE]; 174 uint16_t alt2_boot_lun_number; 175 uint16_t reserved_10; 176 177 uint8_t alt3_boot_port_name[WWN_SIZE]; 178 uint16_t alt3_boot_lun_number; 179 uint16_t reserved_11; 180 181 /* 182 * BIT 0 = Selective Login 183 * BIT 1 = Alt-Boot Enable 184 * BIT 2 = Reserved 185 * BIT 3 = Boot Order List 186 * BIT 4 = Reserved 187 * BIT 5 = Selective LUN 188 * BIT 6 = Reserved 189 * BIT 7-31 = 190 */ 191 uint32_t efi_parameters; 192 193 uint8_t reset_delay; 194 uint8_t reserved_12; 195 uint16_t reserved_13; 196 197 uint16_t boot_id_number; 198 uint16_t reserved_14; 199 200 uint16_t max_luns_per_target; 201 uint16_t reserved_15; 202 203 uint16_t port_down_retry_count; 204 uint16_t link_down_timeout; 205 206 /* FCode parameters. */ 207 uint16_t fcode_parameter; 208 209 uint16_t reserved_16[3]; 210 211 /* Offset 352. */ 212 uint8_t prev_drv_ver_major; 213 uint8_t prev_drv_ver_submajob; 214 uint8_t prev_drv_ver_minor; 215 uint8_t prev_drv_ver_subminor; 216 217 uint16_t prev_bios_ver_major; 218 uint16_t prev_bios_ver_minor; 219 220 uint16_t prev_efi_ver_major; 221 uint16_t prev_efi_ver_minor; 222 223 uint16_t prev_fw_ver_major; 224 uint8_t prev_fw_ver_minor; 225 uint8_t prev_fw_ver_subminor; 226 227 uint16_t reserved_17[8]; 228 229 /* Offset 384. */ 230 uint16_t reserved_18[16]; 231 232 /* Offset 416. */ 233 uint16_t reserved_19[16]; 234 235 /* Offset 448. */ 236 uint16_t reserved_20[16]; 237 238 /* Offset 480. */ 239 uint8_t model_name[16]; 240 241 uint16_t reserved_21[2]; 242 243 /* Offset 500. */ 244 /* HW Parameter Block. */ 245 uint16_t pcie_table_sig; 246 uint16_t pcie_table_offset; 247 248 uint16_t subsystem_vendor_id; 249 uint16_t subsystem_device_id; 250 251 uint32_t checksum; 252 }; 253 254 /* 255 * ISP Initialization Control Block. 256 * Little endian except where noted. 257 */ 258 #define ICB_VERSION 1 259 struct init_cb_24xx { 260 uint16_t version; 261 uint16_t reserved_1; 262 263 uint16_t frame_payload_size; 264 uint16_t execution_throttle; 265 uint16_t exchange_count; 266 267 uint16_t hard_address; 268 269 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 270 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 271 272 uint16_t response_q_inpointer; 273 uint16_t request_q_outpointer; 274 275 uint16_t login_retry_count; 276 277 uint16_t prio_request_q_outpointer; 278 279 uint16_t response_q_length; 280 uint16_t request_q_length; 281 282 uint16_t link_down_timeout; /* Milliseconds. */ 283 284 uint16_t prio_request_q_length; 285 286 uint32_t request_q_address[2]; 287 uint32_t response_q_address[2]; 288 uint32_t prio_request_q_address[2]; 289 290 uint8_t reserved_2[8]; 291 292 uint16_t atio_q_inpointer; 293 uint16_t atio_q_length; 294 uint32_t atio_q_address[2]; 295 296 uint16_t interrupt_delay_timer; /* 100us increments. */ 297 uint16_t login_timeout; 298 299 /* 300 * BIT 0 = Enable Hard Loop Id 301 * BIT 1 = Enable Fairness 302 * BIT 2 = Enable Full-Duplex 303 * BIT 3 = Reserved 304 * BIT 4 = Enable Target Mode 305 * BIT 5 = Disable Initiator Mode 306 * BIT 6 = Reserved 307 * BIT 7 = Reserved 308 * 309 * BIT 8 = Reserved 310 * BIT 9 = Non Participating LIP 311 * BIT 10 = Descending Loop ID Search 312 * BIT 11 = Acquire Loop ID in LIPA 313 * BIT 12 = Reserved 314 * BIT 13 = Full Login after LIP 315 * BIT 14 = Node Name Option 316 * BIT 15-31 = Reserved 317 */ 318 uint32_t firmware_options_1; 319 320 /* 321 * BIT 0 = Operation Mode bit 0 322 * BIT 1 = Operation Mode bit 1 323 * BIT 2 = Operation Mode bit 2 324 * BIT 3 = Operation Mode bit 3 325 * BIT 4 = Connection Options bit 0 326 * BIT 5 = Connection Options bit 1 327 * BIT 6 = Connection Options bit 2 328 * BIT 7 = Enable Non part on LIHA failure 329 * 330 * BIT 8 = Enable Class 2 331 * BIT 9 = Enable ACK0 332 * BIT 10 = Reserved 333 * BIT 11 = Enable FC-SP Security 334 * BIT 12 = FC Tape Enable 335 * BIT 13-31 = Reserved 336 */ 337 uint32_t firmware_options_2; 338 339 /* 340 * BIT 0 = Reserved 341 * BIT 1 = Soft ID only 342 * BIT 2 = Reserved 343 * BIT 3 = Reserved 344 * BIT 4 = FCP RSP Payload bit 0 345 * BIT 5 = FCP RSP Payload bit 1 346 * BIT 6 = Enable Receive Out-of-Order data frame handling 347 * BIT 7 = Disable Automatic PLOGI on Local Loop 348 * 349 * BIT 8 = Reserved 350 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 351 * BIT 10 = Reserved 352 * BIT 11 = Reserved 353 * BIT 12 = Reserved 354 * BIT 13 = Data Rate bit 0 355 * BIT 14 = Data Rate bit 1 356 * BIT 15 = Data Rate bit 2 357 * BIT 16-31 = Reserved 358 */ 359 uint32_t firmware_options_3; 360 361 uint8_t reserved_3[24]; 362 }; 363 364 /* 365 * ISP queue - command entry structure definition. 366 */ 367 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */ 368 struct cmd_type_6 { 369 uint8_t entry_type; /* Entry type. */ 370 uint8_t entry_count; /* Entry count. */ 371 uint8_t sys_define; /* System defined. */ 372 uint8_t entry_status; /* Entry Status. */ 373 374 uint32_t handle; /* System handle. */ 375 376 uint16_t nport_handle; /* N_PORT handle. */ 377 uint16_t timeout; /* Command timeout. */ 378 379 uint16_t dseg_count; /* Data segment count. */ 380 381 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */ 382 383 struct scsi_lun lun; /* FCP LUN (BE). */ 384 385 uint16_t control_flags; /* Control flags. */ 386 #define CF_DATA_SEG_DESCR_ENABLE BIT_2 387 #define CF_READ_DATA BIT_1 388 #define CF_WRITE_DATA BIT_0 389 390 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 391 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 392 393 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 394 395 uint32_t byte_count; /* Total byte count. */ 396 397 uint8_t port_id[3]; /* PortID of destination port. */ 398 uint8_t vp_index; 399 400 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ 401 uint16_t fcp_data_dseg_len; /* Data segment length. */ 402 uint16_t reserved_1; /* MUST be set to 0. */ 403 }; 404 405 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */ 406 struct cmd_type_7 { 407 uint8_t entry_type; /* Entry type. */ 408 uint8_t entry_count; /* Entry count. */ 409 uint8_t sys_define; /* System defined. */ 410 uint8_t entry_status; /* Entry Status. */ 411 412 uint32_t handle; /* System handle. */ 413 414 uint16_t nport_handle; /* N_PORT handle. */ 415 uint16_t timeout; /* Command timeout. */ 416 #define FW_MAX_TIMEOUT 0x1999 417 418 uint16_t dseg_count; /* Data segment count. */ 419 uint16_t reserved_1; 420 421 struct scsi_lun lun; /* FCP LUN (BE). */ 422 423 uint16_t task_mgmt_flags; /* Task management flags. */ 424 #define TMF_CLEAR_ACA BIT_14 425 #define TMF_TARGET_RESET BIT_13 426 #define TMF_LUN_RESET BIT_12 427 #define TMF_CLEAR_TASK_SET BIT_10 428 #define TMF_ABORT_TASK_SET BIT_9 429 #define TMF_READ_DATA BIT_1 430 #define TMF_WRITE_DATA BIT_0 431 432 uint8_t task; 433 #define TSK_SIMPLE 0 434 #define TSK_HEAD_OF_QUEUE 1 435 #define TSK_ORDERED 2 436 #define TSK_ACA 4 437 #define TSK_UNTAGGED 5 438 439 uint8_t crn; 440 441 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ 442 uint32_t byte_count; /* Total byte count. */ 443 444 uint8_t port_id[3]; /* PortID of destination port. */ 445 uint8_t vp_index; 446 447 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 448 uint32_t dseg_0_len; /* Data segment 0 length. */ 449 }; 450 451 /* 452 * ISP queue - status entry structure definition. 453 */ 454 #define STATUS_TYPE 0x03 /* Status entry. */ 455 struct sts_entry_24xx { 456 uint8_t entry_type; /* Entry type. */ 457 uint8_t entry_count; /* Entry count. */ 458 uint8_t sys_define; /* System defined. */ 459 uint8_t entry_status; /* Entry Status. */ 460 461 uint32_t handle; /* System handle. */ 462 463 uint16_t comp_status; /* Completion status. */ 464 uint16_t ox_id; /* OX_ID used by the firmware. */ 465 466 uint32_t residual_len; /* Residual transfer length. */ 467 468 uint16_t reserved_1; 469 uint16_t state_flags; /* State flags. */ 470 #define SF_TRANSFERRED_DATA BIT_11 471 #define SF_FCP_RSP_DMA BIT_0 472 473 uint16_t reserved_2; 474 uint16_t scsi_status; /* SCSI status. */ 475 #define SS_CONFIRMATION_REQ BIT_12 476 477 uint32_t rsp_residual_count; /* FCP RSP residual count. */ 478 479 uint32_t sense_len; /* FCP SENSE length. */ 480 uint32_t rsp_data_len; /* FCP response data length. */ 481 482 uint8_t data[28]; /* FCP response/sense information. */ 483 }; 484 485 /* 486 * Status entry completion status 487 */ 488 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */ 489 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */ 490 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */ 491 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */ 492 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */ 493 494 /* 495 * ISP queue - marker entry structure definition. 496 */ 497 #define MARKER_TYPE 0x04 /* Marker entry. */ 498 struct mrk_entry_24xx { 499 uint8_t entry_type; /* Entry type. */ 500 uint8_t entry_count; /* Entry count. */ 501 uint8_t handle_count; /* Handle count. */ 502 uint8_t entry_status; /* Entry Status. */ 503 504 uint32_t handle; /* System handle. */ 505 506 uint16_t nport_handle; /* N_PORT handle. */ 507 508 uint8_t modifier; /* Modifier (7-0). */ 509 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 510 #define MK_SYNC_ID 1 /* Synchronize ID */ 511 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 512 uint8_t reserved_1; 513 514 uint8_t reserved_2; 515 uint8_t vp_index; 516 517 uint16_t reserved_3; 518 519 uint8_t lun[8]; /* FCP LUN (BE). */ 520 uint8_t reserved_4[40]; 521 }; 522 523 /* 524 * ISP queue - CT Pass-Through entry structure definition. 525 */ 526 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */ 527 struct ct_entry_24xx { 528 uint8_t entry_type; /* Entry type. */ 529 uint8_t entry_count; /* Entry count. */ 530 uint8_t sys_define; /* System Defined. */ 531 uint8_t entry_status; /* Entry Status. */ 532 533 uint32_t handle; /* System handle. */ 534 535 uint16_t comp_status; /* Completion status. */ 536 537 uint16_t nport_handle; /* N_PORT handle. */ 538 539 uint16_t cmd_dsd_count; 540 541 uint8_t vp_index; 542 uint8_t reserved_1; 543 544 uint16_t timeout; /* Command timeout. */ 545 uint16_t reserved_2; 546 547 uint16_t rsp_dsd_count; 548 549 uint8_t reserved_3[10]; 550 551 uint32_t rsp_byte_count; 552 uint32_t cmd_byte_count; 553 554 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 555 uint32_t dseg_0_len; /* Data segment 0 length. */ 556 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 557 uint32_t dseg_1_len; /* Data segment 1 length. */ 558 }; 559 560 /* 561 * ISP queue - ELS Pass-Through entry structure definition. 562 */ 563 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */ 564 struct els_entry_24xx { 565 uint8_t entry_type; /* Entry type. */ 566 uint8_t entry_count; /* Entry count. */ 567 uint8_t sys_define; /* System Defined. */ 568 uint8_t entry_status; /* Entry Status. */ 569 570 uint32_t handle; /* System handle. */ 571 572 uint16_t reserved_1; 573 574 uint16_t nport_handle; /* N_PORT handle. */ 575 576 uint16_t tx_dsd_count; 577 578 uint8_t vp_index; 579 uint8_t sof_type; 580 #define EST_SOFI3 (1 << 4) 581 #define EST_SOFI2 (3 << 4) 582 583 uint32_t rx_xchg_address[2]; /* Receive exchange address. */ 584 uint16_t rx_dsd_count; 585 586 uint8_t opcode; 587 uint8_t reserved_2; 588 589 uint8_t port_id[3]; 590 uint8_t reserved_3; 591 592 uint16_t reserved_4; 593 594 uint16_t control_flags; /* Control flags. */ 595 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13) 596 #define EPD_ELS_COMMAND (0 << 13) 597 #define EPD_ELS_ACC (1 << 13) 598 #define EPD_ELS_RJT (2 << 13) 599 #define EPD_RX_XCHG (3 << 13) 600 #define ECF_CLR_PASSTHRU_PEND BIT_12 601 #define ECF_INCL_FRAME_HDR BIT_11 602 603 uint32_t rx_byte_count; 604 uint32_t tx_byte_count; 605 606 uint32_t tx_address[2]; /* Data segment 0 address. */ 607 uint32_t tx_len; /* Data segment 0 length. */ 608 uint32_t rx_address[2]; /* Data segment 1 address. */ 609 uint32_t rx_len; /* Data segment 1 length. */ 610 }; 611 612 /* 613 * ISP queue - Mailbox Command entry structure definition. 614 */ 615 #define MBX_IOCB_TYPE 0x39 616 struct mbx_entry_24xx { 617 uint8_t entry_type; /* Entry type. */ 618 uint8_t entry_count; /* Entry count. */ 619 uint8_t handle_count; /* Handle count. */ 620 uint8_t entry_status; /* Entry Status. */ 621 622 uint32_t handle; /* System handle. */ 623 624 uint16_t mbx[28]; 625 }; 626 627 628 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */ 629 struct logio_entry_24xx { 630 uint8_t entry_type; /* Entry type. */ 631 uint8_t entry_count; /* Entry count. */ 632 uint8_t sys_define; /* System defined. */ 633 uint8_t entry_status; /* Entry Status. */ 634 635 uint32_t handle; /* System handle. */ 636 637 uint16_t comp_status; /* Completion status. */ 638 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */ 639 640 uint16_t nport_handle; /* N_PORT handle. */ 641 642 uint16_t control_flags; /* Control flags. */ 643 /* Modifiers. */ 644 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ 645 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ 646 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ 647 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */ 648 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */ 649 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */ 650 #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */ 651 #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */ 652 #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */ 653 /* Commands. */ 654 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */ 655 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */ 656 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */ 657 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */ 658 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */ 659 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */ 660 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */ 661 662 uint8_t vp_index; 663 uint8_t reserved_1; 664 665 uint8_t port_id[3]; /* PortID of destination port. */ 666 667 uint8_t rsp_size; /* Response size in 32bit words. */ 668 669 uint32_t io_parameter[11]; /* General I/O parameters. */ 670 #define LSC_SCODE_NOLINK 0x01 671 #define LSC_SCODE_NOIOCB 0x02 672 #define LSC_SCODE_NOXCB 0x03 673 #define LSC_SCODE_CMD_FAILED 0x04 674 #define LSC_SCODE_NOFABRIC 0x05 675 #define LSC_SCODE_FW_NOT_READY 0x07 676 #define LSC_SCODE_NOT_LOGGED_IN 0x09 677 #define LSC_SCODE_NOPCB 0x0A 678 679 #define LSC_SCODE_ELS_REJECT 0x18 680 #define LSC_SCODE_CMD_PARAM_ERR 0x19 681 #define LSC_SCODE_PORTID_USED 0x1A 682 #define LSC_SCODE_NPORT_USED 0x1B 683 #define LSC_SCODE_NONPORT 0x1C 684 #define LSC_SCODE_LOGGED_IN 0x1D 685 #define LSC_SCODE_NOFLOGI_ACC 0x1F 686 }; 687 688 #define TSK_MGMT_IOCB_TYPE 0x14 689 struct tsk_mgmt_entry { 690 uint8_t entry_type; /* Entry type. */ 691 uint8_t entry_count; /* Entry count. */ 692 uint8_t handle_count; /* Handle count. */ 693 uint8_t entry_status; /* Entry Status. */ 694 695 uint32_t handle; /* System handle. */ 696 697 uint16_t nport_handle; /* N_PORT handle. */ 698 699 uint16_t reserved_1; 700 701 uint16_t delay; /* Activity delay in seconds. */ 702 703 uint16_t timeout; /* Command timeout. */ 704 705 uint8_t lun[8]; /* FCP LUN (BE). */ 706 707 uint32_t control_flags; /* Control Flags. */ 708 #define TCF_NOTMCMD_TO_TARGET BIT_31 709 #define TCF_LUN_RESET BIT_4 710 #define TCF_ABORT_TASK_SET BIT_3 711 #define TCF_CLEAR_TASK_SET BIT_2 712 #define TCF_TARGET_RESET BIT_1 713 #define TCF_CLEAR_ACA BIT_0 714 715 uint8_t reserved_2[20]; 716 717 uint8_t port_id[3]; /* PortID of destination port. */ 718 uint8_t vp_index; 719 720 uint8_t reserved_3[12]; 721 }; 722 723 #define ABORT_IOCB_TYPE 0x33 724 struct abort_entry_24xx { 725 uint8_t entry_type; /* Entry type. */ 726 uint8_t entry_count; /* Entry count. */ 727 uint8_t handle_count; /* Handle count. */ 728 uint8_t entry_status; /* Entry Status. */ 729 730 uint32_t handle; /* System handle. */ 731 732 uint16_t nport_handle; /* N_PORT handle. */ 733 /* or Completion status. */ 734 735 uint16_t options; /* Options. */ 736 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ 737 738 uint32_t handle_to_abort; /* System handle to abort. */ 739 740 uint8_t reserved_1[32]; 741 742 uint8_t port_id[3]; /* PortID of destination port. */ 743 uint8_t vp_index; 744 745 uint8_t reserved_2[12]; 746 }; 747 748 /* 749 * ISP I/O Register Set structure definitions. 750 */ 751 struct device_reg_24xx { 752 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */ 753 #define FARX_DATA_FLAG BIT_31 754 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 755 #define FARX_ACCESS_FLASH_DATA 0x7FF00000 756 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000 757 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000 758 759 #define FA_NVRAM_FUNC0_ADDR 0x80 760 #define FA_NVRAM_FUNC1_ADDR 0x180 761 762 #define FA_NVRAM_VPD_SIZE 0x200 763 #define FA_NVRAM_VPD0_ADDR 0x00 764 #define FA_NVRAM_VPD1_ADDR 0x100 765 /* 766 * RISC code begins at offset 512KB 767 * within flash. Consisting of two 768 * contiguous RISC code segments. 769 */ 770 #define FA_RISC_CODE_ADDR 0x20000 771 #define FA_RISC_CODE_SEGMENTS 2 772 773 uint32_t flash_data; /* Flash/NVRAM BIOS data. */ 774 775 uint32_t ctrl_status; /* Control/Status. */ 776 #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */ 777 #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */ 778 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */ 779 #define CSRX_FUNCTION BIT_15 /* Function number. */ 780 /* PCI-X Bus Mode. */ 781 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8) 782 #define PBM_PCI_33MHZ (0 << 8) 783 #define PBM_PCIX_M1_66MHZ (1 << 8) 784 #define PBM_PCIX_M1_100MHZ (2 << 8) 785 #define PBM_PCIX_M1_133MHZ (3 << 8) 786 #define PBM_PCIX_M2_66MHZ (5 << 8) 787 #define PBM_PCIX_M2_100MHZ (6 << 8) 788 #define PBM_PCIX_M2_133MHZ (7 << 8) 789 #define PBM_PCI_66MHZ (8 << 8) 790 /* Max Write Burst byte count. */ 791 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4) 792 #define MWB_512_BYTES (0 << 4) 793 #define MWB_1024_BYTES (1 << 4) 794 #define MWB_2048_BYTES (2 << 4) 795 #define MWB_4096_BYTES (3 << 4) 796 797 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */ 798 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */ 799 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ 800 801 uint32_t ictrl; /* Interrupt control. */ 802 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */ 803 804 uint32_t istatus; /* Interrupt status. */ 805 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */ 806 807 uint32_t unused_1[2]; /* Gap. */ 808 809 /* Request Queue. */ 810 uint32_t req_q_in; /* In-Pointer. */ 811 uint32_t req_q_out; /* Out-Pointer. */ 812 /* Response Queue. */ 813 uint32_t rsp_q_in; /* In-Pointer. */ 814 uint32_t rsp_q_out; /* Out-Pointer. */ 815 /* Priority Request Queue. */ 816 uint32_t preq_q_in; /* In-Pointer. */ 817 uint32_t preq_q_out; /* Out-Pointer. */ 818 819 uint32_t unused_2[2]; /* Gap. */ 820 821 /* ATIO Queue. */ 822 uint32_t atio_q_in; /* In-Pointer. */ 823 uint32_t atio_q_out; /* Out-Pointer. */ 824 825 uint32_t host_status; 826 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ 827 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ 828 829 uint32_t hccr; /* Host command & control register. */ 830 /* HCCR statuses. */ 831 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ 832 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 833 #define HCCRX_RISC_PAUSE BIT_4 /* RISC Pause mode bit. */ 834 /* HCCR commands. */ 835 /* NOOP. */ 836 #define HCCRX_NOOP 0x00000000 837 /* Set RISC Reset. */ 838 #define HCCRX_SET_RISC_RESET 0x10000000 839 /* Clear RISC Reset. */ 840 #define HCCRX_CLR_RISC_RESET 0x20000000 841 /* Set RISC Pause. */ 842 #define HCCRX_SET_RISC_PAUSE 0x30000000 843 /* Releases RISC Pause. */ 844 #define HCCRX_REL_RISC_PAUSE 0x40000000 845 /* Set HOST to RISC interrupt. */ 846 #define HCCRX_SET_HOST_INT 0x50000000 847 /* Clear HOST to RISC interrupt. */ 848 #define HCCRX_CLR_HOST_INT 0x60000000 849 /* Clear RISC to PCI interrupt. */ 850 #define HCCRX_CLR_RISC_INT 0xA0000000 851 852 uint32_t gpiod; /* GPIO Data register. */ 853 /* LED update mask. */ 854 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) 855 /* Data update mask. */ 856 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) 857 /* LED control mask. */ 858 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) 859 /* LED bit values. Color names as 860 * referenced in fw spec. 861 */ 862 #define GPDX_LED_YELLOW_ON BIT_2 863 #define GPDX_LED_GREEN_ON BIT_3 864 #define GPDX_LED_AMBER_ON BIT_4 865 /* Data in/out. */ 866 #define GPDX_DATA_INOUT (BIT_1|BIT_0) 867 868 uint32_t gpioe; /* GPIO Enable register. */ 869 /* Enable update mask. */ 870 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) 871 /* Enable. */ 872 #define GPEX_ENABLE (BIT_1|BIT_0) 873 874 uint32_t iobase_addr; /* I/O Bus Base Address register. */ 875 876 uint32_t unused_3[10]; /* Gap. */ 877 878 uint16_t mailbox0; 879 uint16_t mailbox1; 880 uint16_t mailbox2; 881 uint16_t mailbox3; 882 uint16_t mailbox4; 883 uint16_t mailbox5; 884 uint16_t mailbox6; 885 uint16_t mailbox7; 886 uint16_t mailbox8; 887 uint16_t mailbox9; 888 uint16_t mailbox10; 889 uint16_t mailbox11; 890 uint16_t mailbox12; 891 uint16_t mailbox13; 892 uint16_t mailbox14; 893 uint16_t mailbox15; 894 uint16_t mailbox16; 895 uint16_t mailbox17; 896 uint16_t mailbox18; 897 uint16_t mailbox19; 898 uint16_t mailbox20; 899 uint16_t mailbox21; 900 uint16_t mailbox22; 901 uint16_t mailbox23; 902 uint16_t mailbox24; 903 uint16_t mailbox25; 904 uint16_t mailbox26; 905 uint16_t mailbox27; 906 uint16_t mailbox28; 907 uint16_t mailbox29; 908 uint16_t mailbox30; 909 uint16_t mailbox31; 910 }; 911 912 /* MID Support ***************************************************************/ 913 914 #define MAX_MID_VPS 125 915 916 struct mid_conf_entry_24xx { 917 uint16_t reserved_1; 918 919 /* 920 * BIT 0 = Enable Hard Loop Id 921 * BIT 1 = Acquire Loop ID in LIPA 922 * BIT 2 = ID not Acquired 923 * BIT 3 = Enable VP 924 * BIT 4 = Enable Initiator Mode 925 * BIT 5 = Disable Target Mode 926 * BIT 6-7 = Reserved 927 */ 928 uint8_t options; 929 930 uint8_t hard_address; 931 932 uint8_t port_name[WWN_SIZE]; 933 uint8_t node_name[WWN_SIZE]; 934 }; 935 936 struct mid_init_cb_24xx { 937 struct init_cb_24xx init_cb; 938 939 uint16_t count; 940 uint16_t options; 941 942 struct mid_conf_entry_24xx entries[MAX_MID_VPS]; 943 }; 944 945 946 struct mid_db_entry_24xx { 947 uint16_t status; 948 #define MDBS_NON_PARTIC BIT_3 949 #define MDBS_ID_ACQUIRED BIT_1 950 #define MDBS_ENABLED BIT_0 951 952 uint8_t options; 953 uint8_t hard_address; 954 955 uint8_t port_name[WWN_SIZE]; 956 uint8_t node_name[WWN_SIZE]; 957 958 uint8_t port_id[3]; 959 uint8_t reserved_1; 960 }; 961 962 struct mid_db_24xx { 963 struct mid_db_entry_24xx entries[MAX_MID_VPS]; 964 }; 965 966 #define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */ 967 struct vp_ctrl_entry_24xx { 968 uint8_t entry_type; /* Entry type. */ 969 uint8_t entry_count; /* Entry count. */ 970 uint8_t sys_define; /* System defined. */ 971 uint8_t entry_status; /* Entry Status. */ 972 973 uint32_t handle; /* System handle. */ 974 975 uint16_t vp_idx_failed; 976 977 uint16_t comp_status; /* Completion status. */ 978 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */ 979 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */ 980 981 uint16_t command; 982 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */ 983 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */ 984 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */ 985 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */ 986 987 uint16_t vp_count; 988 989 uint8_t vp_idx_map[16]; 990 991 uint8_t reserved_4[32]; 992 }; 993 994 #define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */ 995 struct vp_config_entry_24xx { 996 uint8_t entry_type; /* Entry type. */ 997 uint8_t entry_count; /* Entry count. */ 998 uint8_t sys_define; /* System defined. */ 999 uint8_t entry_status; /* Entry Status. */ 1000 1001 uint32_t handle; /* System handle. */ 1002 1003 uint16_t reserved_1; 1004 1005 uint16_t comp_status; /* Completion status. */ 1006 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */ 1007 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */ 1008 #define CS_VCT_ERROR 0x03 /* Unknown error. */ 1009 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */ 1010 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1011 1012 uint8_t command; 1013 #define VCT_COMMAND_MOD_VPS 0x00 /* Enable VPs. */ 1014 #define VCT_COMMAND_MOD_ENABLE_VPS 0x08 /* Disable VPs. */ 1015 1016 uint8_t vp_count; 1017 1018 uint8_t vp_idx1; 1019 uint8_t vp_idx2; 1020 1021 uint8_t options_idx1; 1022 uint8_t hard_address_idx1; 1023 uint16_t reserved_2; 1024 uint8_t port_name_idx1[WWN_SIZE]; 1025 uint8_t node_name_idx1[WWN_SIZE]; 1026 1027 uint8_t options_idx2; 1028 uint8_t hard_address_idx2; 1029 uint16_t reserved_3; 1030 uint8_t port_name_idx2[WWN_SIZE]; 1031 uint8_t node_name_idx2[WWN_SIZE]; 1032 1033 uint8_t reserved_4[8]; 1034 }; 1035 1036 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */ 1037 struct vp_rpt_id_entry_24xx { 1038 uint8_t entry_type; /* Entry type. */ 1039 uint8_t entry_count; /* Entry count. */ 1040 uint8_t sys_define; /* System defined. */ 1041 uint8_t entry_status; /* Entry Status. */ 1042 1043 uint32_t handle; /* System handle. */ 1044 1045 uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */ 1046 /* Format 1 -- | VP count |. */ 1047 uint16_t vp_idx; /* Format 0 -- Reserved. */ 1048 /* Format 1 -- VP status and index. */ 1049 1050 uint8_t port_id[3]; 1051 uint8_t format; 1052 1053 uint8_t vp_idx_map[16]; 1054 1055 uint8_t reserved_4[32]; 1056 }; 1057 1058 /* END MID Support ***********************************************************/ 1059 #endif 1060