xref: /openbmc/linux/drivers/scsi/qla2xxx/qla_fw.h (revision 5d0e4d78)
1 /*
2  * QLogic Fibre Channel HBA Driver
3  * Copyright (c)  2003-2014 QLogic Corporation
4  *
5  * See LICENSE.qla2xxx for copyright and licensing details.
6  */
7 #ifndef __QLA_FW_H
8 #define __QLA_FW_H
9 
10 #include <linux/nvme.h>
11 #include <linux/nvme-fc.h>
12 
13 #define MBS_CHECKSUM_ERROR	0x4010
14 #define MBS_INVALID_PRODUCT_KEY	0x4020
15 
16 /*
17  * Firmware Options.
18  */
19 #define FO1_ENABLE_PUREX	BIT_10
20 #define FO1_DISABLE_LED_CTRL	BIT_6
21 #define FO1_ENABLE_8016		BIT_0
22 #define FO2_ENABLE_SEL_CLASS2	BIT_5
23 #define FO3_NO_ABTS_ON_LINKDOWN	BIT_14
24 #define FO3_HOLD_STS_IOCB	BIT_12
25 
26 /*
27  * Port Database structure definition for ISP 24xx.
28  */
29 #define PDO_FORCE_ADISC		BIT_1
30 #define PDO_FORCE_PLOGI		BIT_0
31 
32 
33 #define	PORT_DATABASE_24XX_SIZE		64
34 struct port_database_24xx {
35 	uint16_t flags;
36 #define PDF_TASK_RETRY_ID	BIT_14
37 #define PDF_FC_TAPE		BIT_7
38 #define PDF_ACK0_CAPABLE	BIT_6
39 #define PDF_FCP2_CONF		BIT_5
40 #define PDF_CLASS_2		BIT_4
41 #define PDF_HARD_ADDR		BIT_1
42 
43 	/*
44 	 * for NVMe, the login_state field has been
45 	 * split into nibbles.
46 	 * The lower nibble is for FCP.
47 	 * The upper nibble is for NVMe.
48 	 */
49 	uint8_t current_login_state;
50 	uint8_t last_login_state;
51 #define PDS_PLOGI_PENDING	0x03
52 #define PDS_PLOGI_COMPLETE	0x04
53 #define PDS_PRLI_PENDING	0x05
54 #define PDS_PRLI_COMPLETE	0x06
55 #define PDS_PORT_UNAVAILABLE	0x07
56 #define PDS_PRLO_PENDING	0x09
57 #define PDS_LOGO_PENDING	0x11
58 #define PDS_PRLI2_PENDING	0x12
59 
60 	uint8_t hard_address[3];
61 	uint8_t reserved_1;
62 
63 	uint8_t port_id[3];
64 	uint8_t sequence_id;
65 
66 	uint16_t port_timer;
67 
68 	uint16_t nport_handle;			/* N_PORT handle. */
69 
70 	uint16_t receive_data_size;
71 	uint16_t reserved_2;
72 
73 	uint8_t prli_svc_param_word_0[2];	/* Big endian */
74 						/* Bits 15-0 of word 0 */
75 	uint8_t prli_svc_param_word_3[2];	/* Big endian */
76 						/* Bits 15-0 of word 3 */
77 
78 	uint8_t port_name[WWN_SIZE];
79 	uint8_t node_name[WWN_SIZE];
80 
81 	uint8_t reserved_3[4];
82 	uint16_t prli_nvme_svc_param_word_0;	/* Bits 15-0 of word 0 */
83 	uint16_t prli_nvme_svc_param_word_3;	/* Bits 15-0 of word 3 */
84 	uint16_t nvme_first_burst_size;
85 	uint8_t reserved_4[14];
86 };
87 
88 /*
89  * MB 75h returns a list of DB entries similar to port_database_24xx(64B).
90  * However, in this case it returns 1st 40 bytes.
91  */
92 struct get_name_list_extended {
93 	__le16 flags;
94 	u8 current_login_state;
95 	u8 last_login_state;
96 	u8 hard_address[3];
97 	u8 reserved_1;
98 	u8 port_id[3];
99 	u8 sequence_id;
100 	__le16 port_timer;
101 	__le16 nport_handle;			/* N_PORT handle. */
102 	__le16 receive_data_size;
103 	__le16 reserved_2;
104 
105 	/* PRLI SVC Param are Big endian */
106 	u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */
107 	u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */
108 	u8 port_name[WWN_SIZE];
109 	u8 node_name[WWN_SIZE];
110 };
111 
112 /* MB 75h: This is the short version of the database */
113 struct get_name_list {
114 	u8 port_node_name[WWN_SIZE]; /* B7 most sig, B0 least sig */
115 	__le16 nport_handle;
116 	u8 reserved;
117 };
118 
119 struct vp_database_24xx {
120 	uint16_t vp_status;
121 	uint8_t  options;
122 	uint8_t  id;
123 	uint8_t  port_name[WWN_SIZE];
124 	uint8_t  node_name[WWN_SIZE];
125 	uint16_t port_id_low;
126 	uint16_t port_id_high;
127 };
128 
129 struct nvram_24xx {
130 	/* NVRAM header. */
131 	uint8_t id[4];
132 	uint16_t nvram_version;
133 	uint16_t reserved_0;
134 
135 	/* Firmware Initialization Control Block. */
136 	uint16_t version;
137 	uint16_t reserved_1;
138 	__le16 frame_payload_size;
139 	uint16_t execution_throttle;
140 	uint16_t exchange_count;
141 	uint16_t hard_address;
142 
143 	uint8_t port_name[WWN_SIZE];
144 	uint8_t node_name[WWN_SIZE];
145 
146 	uint16_t login_retry_count;
147 	uint16_t link_down_on_nos;
148 	uint16_t interrupt_delay_timer;
149 	uint16_t login_timeout;
150 
151 	uint32_t firmware_options_1;
152 	uint32_t firmware_options_2;
153 	uint32_t firmware_options_3;
154 
155 	/* Offset 56. */
156 
157 	/*
158 	 * BIT 0     = Control Enable
159 	 * BIT 1-15  =
160 	 *
161 	 * BIT 0-7   = Reserved
162 	 * BIT 8-10  = Output Swing 1G
163 	 * BIT 11-13 = Output Emphasis 1G
164 	 * BIT 14-15 = Reserved
165 	 *
166 	 * BIT 0-7   = Reserved
167 	 * BIT 8-10  = Output Swing 2G
168 	 * BIT 11-13 = Output Emphasis 2G
169 	 * BIT 14-15 = Reserved
170 	 *
171 	 * BIT 0-7   = Reserved
172 	 * BIT 8-10  = Output Swing 4G
173 	 * BIT 11-13 = Output Emphasis 4G
174 	 * BIT 14-15 = Reserved
175 	 */
176 	uint16_t seriallink_options[4];
177 
178 	uint16_t reserved_2[16];
179 
180 	/* Offset 96. */
181 	uint16_t reserved_3[16];
182 
183 	/* PCIe table entries. */
184 	uint16_t reserved_4[16];
185 
186 	/* Offset 160. */
187 	uint16_t reserved_5[16];
188 
189 	/* Offset 192. */
190 	uint16_t reserved_6[16];
191 
192 	/* Offset 224. */
193 	uint16_t reserved_7[16];
194 
195 	/*
196 	 * BIT 0  = Enable spinup delay
197 	 * BIT 1  = Disable BIOS
198 	 * BIT 2  = Enable Memory Map BIOS
199 	 * BIT 3  = Enable Selectable Boot
200 	 * BIT 4  = Disable RISC code load
201 	 * BIT 5  = Disable Serdes
202 	 * BIT 6  =
203 	 * BIT 7  =
204 	 *
205 	 * BIT 8  =
206 	 * BIT 9  =
207 	 * BIT 10 = Enable lip full login
208 	 * BIT 11 = Enable target reset
209 	 * BIT 12 =
210 	 * BIT 13 =
211 	 * BIT 14 =
212 	 * BIT 15 = Enable alternate WWN
213 	 *
214 	 * BIT 16-31 =
215 	 */
216 	uint32_t host_p;
217 
218 	uint8_t alternate_port_name[WWN_SIZE];
219 	uint8_t alternate_node_name[WWN_SIZE];
220 
221 	uint8_t boot_port_name[WWN_SIZE];
222 	uint16_t boot_lun_number;
223 	uint16_t reserved_8;
224 
225 	uint8_t alt1_boot_port_name[WWN_SIZE];
226 	uint16_t alt1_boot_lun_number;
227 	uint16_t reserved_9;
228 
229 	uint8_t alt2_boot_port_name[WWN_SIZE];
230 	uint16_t alt2_boot_lun_number;
231 	uint16_t reserved_10;
232 
233 	uint8_t alt3_boot_port_name[WWN_SIZE];
234 	uint16_t alt3_boot_lun_number;
235 	uint16_t reserved_11;
236 
237 	/*
238 	 * BIT 0 = Selective Login
239 	 * BIT 1 = Alt-Boot Enable
240 	 * BIT 2 = Reserved
241 	 * BIT 3 = Boot Order List
242 	 * BIT 4 = Reserved
243 	 * BIT 5 = Selective LUN
244 	 * BIT 6 = Reserved
245 	 * BIT 7-31 =
246 	 */
247 	uint32_t efi_parameters;
248 
249 	uint8_t reset_delay;
250 	uint8_t reserved_12;
251 	uint16_t reserved_13;
252 
253 	uint16_t boot_id_number;
254 	uint16_t reserved_14;
255 
256 	uint16_t max_luns_per_target;
257 	uint16_t reserved_15;
258 
259 	uint16_t port_down_retry_count;
260 	uint16_t link_down_timeout;
261 
262 	/* FCode parameters. */
263 	uint16_t fcode_parameter;
264 
265 	uint16_t reserved_16[3];
266 
267 	/* Offset 352. */
268 	uint8_t prev_drv_ver_major;
269 	uint8_t prev_drv_ver_submajob;
270 	uint8_t prev_drv_ver_minor;
271 	uint8_t prev_drv_ver_subminor;
272 
273 	uint16_t prev_bios_ver_major;
274 	uint16_t prev_bios_ver_minor;
275 
276 	uint16_t prev_efi_ver_major;
277 	uint16_t prev_efi_ver_minor;
278 
279 	uint16_t prev_fw_ver_major;
280 	uint8_t prev_fw_ver_minor;
281 	uint8_t prev_fw_ver_subminor;
282 
283 	uint16_t reserved_17[8];
284 
285 	/* Offset 384. */
286 	uint16_t reserved_18[16];
287 
288 	/* Offset 416. */
289 	uint16_t reserved_19[16];
290 
291 	/* Offset 448. */
292 	uint16_t reserved_20[16];
293 
294 	/* Offset 480. */
295 	uint8_t model_name[16];
296 
297 	uint16_t reserved_21[2];
298 
299 	/* Offset 500. */
300 	/* HW Parameter Block. */
301 	uint16_t pcie_table_sig;
302 	uint16_t pcie_table_offset;
303 
304 	uint16_t subsystem_vendor_id;
305 	uint16_t subsystem_device_id;
306 
307 	uint32_t checksum;
308 };
309 
310 /*
311  * ISP Initialization Control Block.
312  * Little endian except where noted.
313  */
314 #define	ICB_VERSION 1
315 struct init_cb_24xx {
316 	uint16_t version;
317 	uint16_t reserved_1;
318 
319 	uint16_t frame_payload_size;
320 	uint16_t execution_throttle;
321 	uint16_t exchange_count;
322 
323 	uint16_t hard_address;
324 
325 	uint8_t port_name[WWN_SIZE];		/* Big endian. */
326 	uint8_t node_name[WWN_SIZE];		/* Big endian. */
327 
328 	uint16_t response_q_inpointer;
329 	uint16_t request_q_outpointer;
330 
331 	uint16_t login_retry_count;
332 
333 	uint16_t prio_request_q_outpointer;
334 
335 	uint16_t response_q_length;
336 	uint16_t request_q_length;
337 
338 	uint16_t link_down_on_nos;		/* Milliseconds. */
339 
340 	uint16_t prio_request_q_length;
341 
342 	uint32_t request_q_address[2];
343 	uint32_t response_q_address[2];
344 	uint32_t prio_request_q_address[2];
345 
346 	uint16_t msix;
347 	uint16_t msix_atio;
348 	uint8_t reserved_2[4];
349 
350 	uint16_t atio_q_inpointer;
351 	uint16_t atio_q_length;
352 	uint32_t atio_q_address[2];
353 
354 	uint16_t interrupt_delay_timer;		/* 100us increments. */
355 	uint16_t login_timeout;
356 
357 	/*
358 	 * BIT 0  = Enable Hard Loop Id
359 	 * BIT 1  = Enable Fairness
360 	 * BIT 2  = Enable Full-Duplex
361 	 * BIT 3  = Reserved
362 	 * BIT 4  = Enable Target Mode
363 	 * BIT 5  = Disable Initiator Mode
364 	 * BIT 6  = Acquire FA-WWN
365 	 * BIT 7  = Enable D-port Diagnostics
366 	 *
367 	 * BIT 8  = Reserved
368 	 * BIT 9  = Non Participating LIP
369 	 * BIT 10 = Descending Loop ID Search
370 	 * BIT 11 = Acquire Loop ID in LIPA
371 	 * BIT 12 = Reserved
372 	 * BIT 13 = Full Login after LIP
373 	 * BIT 14 = Node Name Option
374 	 * BIT 15-31 = Reserved
375 	 */
376 	uint32_t firmware_options_1;
377 
378 	/*
379 	 * BIT 0  = Operation Mode bit 0
380 	 * BIT 1  = Operation Mode bit 1
381 	 * BIT 2  = Operation Mode bit 2
382 	 * BIT 3  = Operation Mode bit 3
383 	 * BIT 4  = Connection Options bit 0
384 	 * BIT 5  = Connection Options bit 1
385 	 * BIT 6  = Connection Options bit 2
386 	 * BIT 7  = Enable Non part on LIHA failure
387 	 *
388 	 * BIT 8  = Enable Class 2
389 	 * BIT 9  = Enable ACK0
390 	 * BIT 10 = Reserved
391 	 * BIT 11 = Enable FC-SP Security
392 	 * BIT 12 = FC Tape Enable
393 	 * BIT 13 = Reserved
394 	 * BIT 14 = Enable Target PRLI Control
395 	 * BIT 15-31 = Reserved
396 	 */
397 	uint32_t firmware_options_2;
398 
399 	/*
400 	 * BIT 0  = Reserved
401 	 * BIT 1  = Soft ID only
402 	 * BIT 2  = Reserved
403 	 * BIT 3  = Reserved
404 	 * BIT 4  = FCP RSP Payload bit 0
405 	 * BIT 5  = FCP RSP Payload bit 1
406 	 * BIT 6  = Enable Receive Out-of-Order data frame handling
407 	 * BIT 7  = Disable Automatic PLOGI on Local Loop
408 	 *
409 	 * BIT 8  = Reserved
410 	 * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative offset handling
411 	 * BIT 10 = Reserved
412 	 * BIT 11 = Reserved
413 	 * BIT 12 = Reserved
414 	 * BIT 13 = Data Rate bit 0
415 	 * BIT 14 = Data Rate bit 1
416 	 * BIT 15 = Data Rate bit 2
417 	 * BIT 16 = Enable 75 ohm Termination Select
418 	 * BIT 17-28 = Reserved
419 	 * BIT 29 = Enable response queue 0 in index shadowing
420 	 * BIT 30 = Enable request queue 0 out index shadowing
421 	 * BIT 31 = Reserved
422 	 */
423 	uint32_t firmware_options_3;
424 	uint16_t qos;
425 	uint16_t rid;
426 	uint8_t  reserved_3[20];
427 };
428 
429 /*
430  * ISP queue - command entry structure definition.
431  */
432 #define COMMAND_BIDIRECTIONAL 0x75
433 struct cmd_bidir {
434 	uint8_t entry_type;		/* Entry type. */
435 	uint8_t entry_count;		/* Entry count. */
436 	uint8_t sys_define;		/* System defined */
437 	uint8_t entry_status;		/* Entry status. */
438 
439 	uint32_t handle;		/* System handle. */
440 
441 	uint16_t nport_handle;		/* N_PORT hanlde. */
442 
443 	uint16_t timeout;		/* Commnad timeout. */
444 
445 	uint16_t wr_dseg_count;		/* Write Data segment count. */
446 	uint16_t rd_dseg_count;		/* Read Data segment count. */
447 
448 	struct scsi_lun lun;		/* FCP LUN (BE). */
449 
450 	uint16_t control_flags;		/* Control flags. */
451 #define BD_WRAP_BACK			BIT_3
452 #define BD_READ_DATA			BIT_1
453 #define BD_WRITE_DATA			BIT_0
454 
455 	uint16_t fcp_cmnd_dseg_len;		/* Data segment length. */
456 	uint32_t fcp_cmnd_dseg_address[2];	/* Data segment address. */
457 
458 	uint16_t reserved[2];			/* Reserved */
459 
460 	uint32_t rd_byte_count;			/* Total Byte count Read. */
461 	uint32_t wr_byte_count;			/* Total Byte count write. */
462 
463 	uint8_t port_id[3];			/* PortID of destination port.*/
464 	uint8_t vp_index;
465 
466 	uint32_t fcp_data_dseg_address[2];	/* Data segment address. */
467 	uint16_t fcp_data_dseg_len;		/* Data segment length. */
468 };
469 
470 #define COMMAND_TYPE_6	0x48		/* Command Type 6 entry */
471 struct cmd_type_6 {
472 	uint8_t entry_type;		/* Entry type. */
473 	uint8_t entry_count;		/* Entry count. */
474 	uint8_t sys_define;		/* System defined. */
475 	uint8_t entry_status;		/* Entry Status. */
476 
477 	uint32_t handle;		/* System handle. */
478 
479 	uint16_t nport_handle;		/* N_PORT handle. */
480 	uint16_t timeout;		/* Command timeout. */
481 
482 	uint16_t dseg_count;		/* Data segment count. */
483 
484 	uint16_t fcp_rsp_dsd_len;	/* FCP_RSP DSD length. */
485 
486 	struct scsi_lun lun;		/* FCP LUN (BE). */
487 
488 	uint16_t control_flags;		/* Control flags. */
489 #define CF_DIF_SEG_DESCR_ENABLE		BIT_3
490 #define CF_DATA_SEG_DESCR_ENABLE	BIT_2
491 #define CF_READ_DATA			BIT_1
492 #define CF_WRITE_DATA			BIT_0
493 
494 	uint16_t fcp_cmnd_dseg_len;		/* Data segment length. */
495 	uint32_t fcp_cmnd_dseg_address[2];	/* Data segment address. */
496 
497 	uint32_t fcp_rsp_dseg_address[2];	/* Data segment address. */
498 
499 	uint32_t byte_count;		/* Total byte count. */
500 
501 	uint8_t port_id[3];		/* PortID of destination port. */
502 	uint8_t vp_index;
503 
504 	uint32_t fcp_data_dseg_address[2];	/* Data segment address. */
505 	uint32_t fcp_data_dseg_len;		/* Data segment length. */
506 };
507 
508 #define COMMAND_TYPE_7	0x18		/* Command Type 7 entry */
509 struct cmd_type_7 {
510 	uint8_t entry_type;		/* Entry type. */
511 	uint8_t entry_count;		/* Entry count. */
512 	uint8_t sys_define;		/* System defined. */
513 	uint8_t entry_status;		/* Entry Status. */
514 
515 	uint32_t handle;		/* System handle. */
516 
517 	uint16_t nport_handle;		/* N_PORT handle. */
518 	uint16_t timeout;		/* Command timeout. */
519 #define FW_MAX_TIMEOUT		0x1999
520 
521 	uint16_t dseg_count;		/* Data segment count. */
522 	uint16_t reserved_1;
523 
524 	struct scsi_lun lun;		/* FCP LUN (BE). */
525 
526 	uint16_t task_mgmt_flags;	/* Task management flags. */
527 #define TMF_CLEAR_ACA		BIT_14
528 #define TMF_TARGET_RESET	BIT_13
529 #define TMF_LUN_RESET		BIT_12
530 #define TMF_CLEAR_TASK_SET	BIT_10
531 #define TMF_ABORT_TASK_SET	BIT_9
532 #define TMF_DSD_LIST_ENABLE	BIT_2
533 #define TMF_READ_DATA		BIT_1
534 #define TMF_WRITE_DATA		BIT_0
535 
536 	uint8_t task;
537 #define TSK_SIMPLE		0
538 #define TSK_HEAD_OF_QUEUE	1
539 #define TSK_ORDERED		2
540 #define TSK_ACA			4
541 #define TSK_UNTAGGED		5
542 
543 	uint8_t crn;
544 
545 	uint8_t fcp_cdb[MAX_CMDSZ]; 	/* SCSI command words. */
546 	uint32_t byte_count;		/* Total byte count. */
547 
548 	uint8_t port_id[3];		/* PortID of destination port. */
549 	uint8_t vp_index;
550 
551 	uint32_t dseg_0_address[2];	/* Data segment 0 address. */
552 	uint32_t dseg_0_len;		/* Data segment 0 length. */
553 };
554 
555 #define COMMAND_TYPE_CRC_2	0x6A	/* Command Type CRC_2 (Type 6)
556 					 * (T10-DIF) */
557 struct cmd_type_crc_2 {
558 	uint8_t entry_type;		/* Entry type. */
559 	uint8_t entry_count;		/* Entry count. */
560 	uint8_t sys_define;		/* System defined. */
561 	uint8_t entry_status;		/* Entry Status. */
562 
563 	uint32_t handle;		/* System handle. */
564 
565 	uint16_t nport_handle;		/* N_PORT handle. */
566 	uint16_t timeout;		/* Command timeout. */
567 
568 	uint16_t dseg_count;		/* Data segment count. */
569 
570 	uint16_t fcp_rsp_dseg_len;	/* FCP_RSP DSD length. */
571 
572 	struct scsi_lun lun;		/* FCP LUN (BE). */
573 
574 	uint16_t control_flags;		/* Control flags. */
575 
576 	uint16_t fcp_cmnd_dseg_len;		/* Data segment length. */
577 	uint32_t fcp_cmnd_dseg_address[2];	/* Data segment address. */
578 
579 	uint32_t fcp_rsp_dseg_address[2];	/* Data segment address. */
580 
581 	uint32_t byte_count;		/* Total byte count. */
582 
583 	uint8_t port_id[3];		/* PortID of destination port. */
584 	uint8_t vp_index;
585 
586 	uint32_t crc_context_address[2];	/* Data segment address. */
587 	uint16_t crc_context_len;		/* Data segment length. */
588 	uint16_t reserved_1;			/* MUST be set to 0. */
589 };
590 
591 
592 /*
593  * ISP queue - status entry structure definition.
594  */
595 #define	STATUS_TYPE	0x03		/* Status entry. */
596 struct sts_entry_24xx {
597 	uint8_t entry_type;		/* Entry type. */
598 	uint8_t entry_count;		/* Entry count. */
599 	uint8_t sys_define;		/* System defined. */
600 	uint8_t entry_status;		/* Entry Status. */
601 
602 	uint32_t handle;		/* System handle. */
603 
604 	uint16_t comp_status;		/* Completion status. */
605 	uint16_t ox_id;			/* OX_ID used by the firmware. */
606 
607 	uint32_t residual_len;		/* FW calc residual transfer length. */
608 
609 	union {
610 		uint16_t reserved_1;
611 		uint16_t nvme_rsp_pyld_len;
612 	};
613 
614 	uint16_t state_flags;		/* State flags. */
615 #define SF_TRANSFERRED_DATA	BIT_11
616 #define SF_NVME_ERSP            BIT_6
617 #define SF_FCP_RSP_DMA		BIT_0
618 
619 	uint16_t retry_delay;
620 	uint16_t scsi_status;		/* SCSI status. */
621 #define SS_CONFIRMATION_REQ		BIT_12
622 
623 	uint32_t rsp_residual_count;	/* FCP RSP residual count. */
624 
625 	uint32_t sense_len;		/* FCP SENSE length. */
626 
627 	union {
628 		struct {
629 			uint32_t rsp_data_len;	/* FCP response data length  */
630 			uint8_t data[28];	/* FCP rsp/sense information */
631 		};
632 		struct nvme_fc_ersp_iu nvme_ersp;
633 		uint8_t nvme_ersp_data[32];
634 	};
635 
636 	/*
637 	 * If DIF Error is set in comp_status, these additional fields are
638 	 * defined:
639 	 *
640 	 * !!! NOTE: Firmware sends expected/actual DIF data in big endian
641 	 * format; but all of the "data" field gets swab32-d in the beginning
642 	 * of qla2x00_status_entry().
643 	 *
644 	 * &data[10] : uint8_t report_runt_bg[2];	- computed guard
645 	 * &data[12] : uint8_t actual_dif[8];		- DIF Data received
646 	 * &data[20] : uint8_t expected_dif[8];		- DIF Data computed
647 	*/
648 };
649 
650 
651 /*
652  * Status entry completion status
653  */
654 #define CS_DATA_REASSEMBLY_ERROR 0x11	/* Data Reassembly Error.. */
655 #define CS_ABTS_BY_TARGET	0x13	/* Target send ABTS to abort IOCB. */
656 #define CS_FW_RESOURCE		0x2C	/* Firmware Resource Unavailable. */
657 #define CS_TASK_MGMT_OVERRUN	0x30	/* Task management overrun (8+). */
658 #define CS_ABORT_BY_TARGET	0x47	/* Abort By Target. */
659 
660 /*
661  * ISP queue - marker entry structure definition.
662  */
663 #define MARKER_TYPE	0x04		/* Marker entry. */
664 struct mrk_entry_24xx {
665 	uint8_t entry_type;		/* Entry type. */
666 	uint8_t entry_count;		/* Entry count. */
667 	uint8_t handle_count;		/* Handle count. */
668 	uint8_t entry_status;		/* Entry Status. */
669 
670 	uint32_t handle;		/* System handle. */
671 
672 	uint16_t nport_handle;		/* N_PORT handle. */
673 
674 	uint8_t modifier;		/* Modifier (7-0). */
675 #define MK_SYNC_ID_LUN	0		/* Synchronize ID/LUN */
676 #define MK_SYNC_ID	1		/* Synchronize ID */
677 #define MK_SYNC_ALL	2		/* Synchronize all ID/LUN */
678 	uint8_t reserved_1;
679 
680 	uint8_t reserved_2;
681 	uint8_t vp_index;
682 
683 	uint16_t reserved_3;
684 
685 	uint8_t lun[8];			/* FCP LUN (BE). */
686 	uint8_t reserved_4[40];
687 };
688 
689 /*
690  * ISP queue - CT Pass-Through entry structure definition.
691  */
692 #define CT_IOCB_TYPE		0x29	/* CT Pass-Through IOCB entry */
693 struct ct_entry_24xx {
694 	uint8_t entry_type;		/* Entry type. */
695 	uint8_t entry_count;		/* Entry count. */
696 	uint8_t sys_define;		/* System Defined. */
697 	uint8_t entry_status;		/* Entry Status. */
698 
699 	uint32_t handle;		/* System handle. */
700 
701 	uint16_t comp_status;		/* Completion status. */
702 
703 	uint16_t nport_handle;		/* N_PORT handle. */
704 
705 	uint16_t cmd_dsd_count;
706 
707 	uint8_t vp_index;
708 	uint8_t reserved_1;
709 
710 	uint16_t timeout;		/* Command timeout. */
711 	uint16_t reserved_2;
712 
713 	uint16_t rsp_dsd_count;
714 
715 	uint8_t reserved_3[10];
716 
717 	uint32_t rsp_byte_count;
718 	uint32_t cmd_byte_count;
719 
720 	uint32_t dseg_0_address[2];	/* Data segment 0 address. */
721 	uint32_t dseg_0_len;		/* Data segment 0 length. */
722 	uint32_t dseg_1_address[2];	/* Data segment 1 address. */
723 	uint32_t dseg_1_len;		/* Data segment 1 length. */
724 };
725 
726 /*
727  * ISP queue - ELS Pass-Through entry structure definition.
728  */
729 #define ELS_IOCB_TYPE		0x53	/* ELS Pass-Through IOCB entry */
730 struct els_entry_24xx {
731 	uint8_t entry_type;		/* Entry type. */
732 	uint8_t entry_count;		/* Entry count. */
733 	uint8_t sys_define;		/* System Defined. */
734 	uint8_t entry_status;		/* Entry Status. */
735 
736 	uint32_t handle;		/* System handle. */
737 
738 	uint16_t reserved_1;
739 
740 	uint16_t nport_handle;		/* N_PORT handle. */
741 
742 	uint16_t tx_dsd_count;
743 
744 	uint8_t vp_index;
745 	uint8_t sof_type;
746 #define EST_SOFI3		(1 << 4)
747 #define EST_SOFI2		(3 << 4)
748 
749 	uint32_t rx_xchg_address;	/* Receive exchange address. */
750 	uint16_t rx_dsd_count;
751 
752 	uint8_t opcode;
753 	uint8_t reserved_2;
754 
755 	uint8_t port_id[3];
756 	uint8_t reserved_3;
757 
758 	uint16_t reserved_4;
759 
760 	uint16_t control_flags;		/* Control flags. */
761 #define ECF_PAYLOAD_DESCR_MASK	(BIT_15|BIT_14|BIT_13)
762 #define EPD_ELS_COMMAND		(0 << 13)
763 #define EPD_ELS_ACC		(1 << 13)
764 #define EPD_ELS_RJT		(2 << 13)
765 #define EPD_RX_XCHG		(3 << 13)
766 #define ECF_CLR_PASSTHRU_PEND	BIT_12
767 #define ECF_INCL_FRAME_HDR	BIT_11
768 
769 	uint32_t rx_byte_count;
770 	uint32_t tx_byte_count;
771 
772 	uint32_t tx_address[2];		/* Data segment 0 address. */
773 	uint32_t tx_len;		/* Data segment 0 length. */
774 	uint32_t rx_address[2];		/* Data segment 1 address. */
775 	uint32_t rx_len;		/* Data segment 1 length. */
776 };
777 
778 struct els_sts_entry_24xx {
779 	uint8_t entry_type;		/* Entry type. */
780 	uint8_t entry_count;		/* Entry count. */
781 	uint8_t sys_define;		/* System Defined. */
782 	uint8_t entry_status;		/* Entry Status. */
783 
784 	uint32_t handle;		/* System handle. */
785 
786 	uint16_t comp_status;
787 
788 	uint16_t nport_handle;		/* N_PORT handle. */
789 
790 	uint16_t reserved_1;
791 
792 	uint8_t vp_index;
793 	uint8_t sof_type;
794 
795 	uint32_t rx_xchg_address;	/* Receive exchange address. */
796 	uint16_t reserved_2;
797 
798 	uint8_t opcode;
799 	uint8_t reserved_3;
800 
801 	uint8_t port_id[3];
802 	uint8_t reserved_4;
803 
804 	uint16_t reserved_5;
805 
806 	uint16_t control_flags;		/* Control flags. */
807 	uint32_t total_byte_count;
808 	uint32_t error_subcode_1;
809 	uint32_t error_subcode_2;
810 };
811 /*
812  * ISP queue - Mailbox Command entry structure definition.
813  */
814 #define MBX_IOCB_TYPE	0x39
815 struct mbx_entry_24xx {
816 	uint8_t entry_type;		/* Entry type. */
817 	uint8_t entry_count;		/* Entry count. */
818 	uint8_t handle_count;		/* Handle count. */
819 	uint8_t entry_status;		/* Entry Status. */
820 
821 	uint32_t handle;		/* System handle. */
822 
823 	uint16_t mbx[28];
824 };
825 
826 
827 #define LOGINOUT_PORT_IOCB_TYPE	0x52	/* Login/Logout Port entry. */
828 struct logio_entry_24xx {
829 	uint8_t entry_type;		/* Entry type. */
830 	uint8_t entry_count;		/* Entry count. */
831 	uint8_t sys_define;		/* System defined. */
832 	uint8_t entry_status;		/* Entry Status. */
833 
834 	uint32_t handle;		/* System handle. */
835 
836 	uint16_t comp_status;		/* Completion status. */
837 #define CS_LOGIO_ERROR		0x31	/* Login/Logout IOCB error. */
838 
839 	uint16_t nport_handle;		/* N_PORT handle. */
840 
841 	uint16_t control_flags;		/* Control flags. */
842 					/* Modifiers. */
843 #define LCF_INCLUDE_SNS		BIT_10	/* Include SNS (FFFFFC) during LOGO. */
844 #define LCF_FCP2_OVERRIDE	BIT_9	/* Set/Reset word 3 of PRLI. */
845 #define LCF_CLASS_2		BIT_8	/* Enable class 2 during PLOGI. */
846 #define LCF_FREE_NPORT		BIT_7	/* Release NPORT handle after LOGO. */
847 #define LCF_EXPL_LOGO		BIT_6	/* Perform an explicit LOGO. */
848 #define LCF_NVME_PRLI		BIT_6   /* Perform NVME FC4 PRLI */
849 #define LCF_SKIP_PRLI		BIT_5	/* Skip PRLI after PLOGI. */
850 #define LCF_IMPL_LOGO_ALL	BIT_5	/* Implicit LOGO to all ports. */
851 #define LCF_COND_PLOGI		BIT_4	/* PLOGI only if not logged-in. */
852 #define LCF_IMPL_LOGO		BIT_4	/* Perform an implicit LOGO. */
853 #define LCF_IMPL_PRLO		BIT_4	/* Perform an implicit PRLO. */
854 					/* Commands. */
855 #define LCF_COMMAND_PLOGI	0x00	/* PLOGI. */
856 #define LCF_COMMAND_PRLI	0x01	/* PRLI. */
857 #define LCF_COMMAND_PDISC	0x02	/* PDISC. */
858 #define LCF_COMMAND_ADISC	0x03	/* ADISC. */
859 #define LCF_COMMAND_LOGO	0x08	/* LOGO. */
860 #define LCF_COMMAND_PRLO	0x09	/* PRLO. */
861 #define LCF_COMMAND_TPRLO	0x0A	/* TPRLO. */
862 
863 	uint8_t vp_index;
864 	uint8_t reserved_1;
865 
866 	uint8_t port_id[3];		/* PortID of destination port. */
867 
868 	uint8_t rsp_size;		/* Response size in 32bit words. */
869 
870 	uint32_t io_parameter[11];	/* General I/O parameters. */
871 #define LSC_SCODE_NOLINK	0x01
872 #define LSC_SCODE_NOIOCB	0x02
873 #define LSC_SCODE_NOXCB		0x03
874 #define LSC_SCODE_CMD_FAILED	0x04
875 #define LSC_SCODE_NOFABRIC	0x05
876 #define LSC_SCODE_FW_NOT_READY	0x07
877 #define LSC_SCODE_NOT_LOGGED_IN	0x09
878 #define LSC_SCODE_NOPCB		0x0A
879 
880 #define LSC_SCODE_ELS_REJECT	0x18
881 #define LSC_SCODE_CMD_PARAM_ERR	0x19
882 #define LSC_SCODE_PORTID_USED	0x1A
883 #define LSC_SCODE_NPORT_USED	0x1B
884 #define LSC_SCODE_NONPORT	0x1C
885 #define LSC_SCODE_LOGGED_IN	0x1D
886 #define LSC_SCODE_NOFLOGI_ACC	0x1F
887 };
888 
889 #define TSK_MGMT_IOCB_TYPE	0x14
890 struct tsk_mgmt_entry {
891 	uint8_t entry_type;		/* Entry type. */
892 	uint8_t entry_count;		/* Entry count. */
893 	uint8_t handle_count;		/* Handle count. */
894 	uint8_t entry_status;		/* Entry Status. */
895 
896 	uint32_t handle;		/* System handle. */
897 
898 	uint16_t nport_handle;		/* N_PORT handle. */
899 
900 	uint16_t reserved_1;
901 
902 	uint16_t delay;			/* Activity delay in seconds. */
903 
904 	uint16_t timeout;		/* Command timeout. */
905 
906 	struct scsi_lun lun;		/* FCP LUN (BE). */
907 
908 	uint32_t control_flags;		/* Control Flags. */
909 #define TCF_NOTMCMD_TO_TARGET	BIT_31
910 #define TCF_LUN_RESET		BIT_4
911 #define TCF_ABORT_TASK_SET	BIT_3
912 #define TCF_CLEAR_TASK_SET	BIT_2
913 #define TCF_TARGET_RESET	BIT_1
914 #define TCF_CLEAR_ACA		BIT_0
915 
916 	uint8_t reserved_2[20];
917 
918 	uint8_t port_id[3];		/* PortID of destination port. */
919 	uint8_t vp_index;
920 
921 	uint8_t reserved_3[12];
922 };
923 
924 #define ABORT_IOCB_TYPE	0x33
925 struct abort_entry_24xx {
926 	uint8_t entry_type;		/* Entry type. */
927 	uint8_t entry_count;		/* Entry count. */
928 	uint8_t handle_count;		/* Handle count. */
929 	uint8_t entry_status;		/* Entry Status. */
930 
931 	uint32_t handle;		/* System handle. */
932 
933 	uint16_t nport_handle;		/* N_PORT handle. */
934 					/* or Completion status. */
935 
936 	uint16_t options;		/* Options. */
937 #define AOF_NO_ABTS		BIT_0	/* Do not send any ABTS. */
938 
939 	uint32_t handle_to_abort;	/* System handle to abort. */
940 
941 	uint16_t req_que_no;
942 	uint8_t reserved_1[30];
943 
944 	uint8_t port_id[3];		/* PortID of destination port. */
945 	uint8_t vp_index;
946 
947 	uint8_t reserved_2[12];
948 };
949 
950 /*
951  * ISP I/O Register Set structure definitions.
952  */
953 struct device_reg_24xx {
954 	uint32_t flash_addr;		/* Flash/NVRAM BIOS address. */
955 #define FARX_DATA_FLAG	BIT_31
956 #define FARX_ACCESS_FLASH_CONF	0x7FFD0000
957 #define FARX_ACCESS_FLASH_DATA	0x7FF00000
958 #define FARX_ACCESS_NVRAM_CONF	0x7FFF0000
959 #define FARX_ACCESS_NVRAM_DATA	0x7FFE0000
960 
961 #define FA_NVRAM_FUNC0_ADDR	0x80
962 #define FA_NVRAM_FUNC1_ADDR	0x180
963 
964 #define FA_NVRAM_VPD_SIZE	0x200
965 #define FA_NVRAM_VPD0_ADDR	0x00
966 #define FA_NVRAM_VPD1_ADDR	0x100
967 
968 #define FA_BOOT_CODE_ADDR	0x00000
969 					/*
970 					 * RISC code begins at offset 512KB
971 					 * within flash. Consisting of two
972 					 * contiguous RISC code segments.
973 					 */
974 #define FA_RISC_CODE_ADDR	0x20000
975 #define FA_RISC_CODE_SEGMENTS	2
976 
977 #define FA_FLASH_DESCR_ADDR_24	0x11000
978 #define FA_FLASH_LAYOUT_ADDR_24	0x11400
979 #define FA_NPIV_CONF0_ADDR_24	0x16000
980 #define FA_NPIV_CONF1_ADDR_24	0x17000
981 
982 #define FA_FW_AREA_ADDR		0x40000
983 #define FA_VPD_NVRAM_ADDR	0x48000
984 #define FA_FEATURE_ADDR		0x4C000
985 #define FA_FLASH_DESCR_ADDR	0x50000
986 #define FA_FLASH_LAYOUT_ADDR	0x50400
987 #define FA_HW_EVENT0_ADDR	0x54000
988 #define FA_HW_EVENT1_ADDR	0x54400
989 #define FA_HW_EVENT_SIZE	0x200
990 #define FA_HW_EVENT_ENTRY_SIZE	4
991 #define FA_NPIV_CONF0_ADDR	0x5C000
992 #define FA_NPIV_CONF1_ADDR	0x5D000
993 #define FA_FCP_PRIO0_ADDR	0x10000
994 #define FA_FCP_PRIO1_ADDR	0x12000
995 
996 /*
997  * Flash Error Log Event Codes.
998  */
999 #define HW_EVENT_RESET_ERR	0xF00B
1000 #define HW_EVENT_ISP_ERR	0xF020
1001 #define HW_EVENT_PARITY_ERR	0xF022
1002 #define HW_EVENT_NVRAM_CHKSUM_ERR	0xF023
1003 #define HW_EVENT_FLASH_FW_ERR	0xF024
1004 
1005 	uint32_t flash_data;		/* Flash/NVRAM BIOS data. */
1006 
1007 	uint32_t ctrl_status;		/* Control/Status. */
1008 #define CSRX_FLASH_ACCESS_ERROR	BIT_18	/* Flash/NVRAM Access Error. */
1009 #define CSRX_DMA_ACTIVE		BIT_17	/* DMA Active status. */
1010 #define CSRX_DMA_SHUTDOWN	BIT_16	/* DMA Shutdown control status. */
1011 #define CSRX_FUNCTION		BIT_15	/* Function number. */
1012 					/* PCI-X Bus Mode. */
1013 #define CSRX_PCIX_BUS_MODE_MASK	(BIT_11|BIT_10|BIT_9|BIT_8)
1014 #define PBM_PCI_33MHZ		(0 << 8)
1015 #define PBM_PCIX_M1_66MHZ	(1 << 8)
1016 #define PBM_PCIX_M1_100MHZ	(2 << 8)
1017 #define PBM_PCIX_M1_133MHZ	(3 << 8)
1018 #define PBM_PCIX_M2_66MHZ	(5 << 8)
1019 #define PBM_PCIX_M2_100MHZ	(6 << 8)
1020 #define PBM_PCIX_M2_133MHZ	(7 << 8)
1021 #define PBM_PCI_66MHZ		(8 << 8)
1022 					/* Max Write Burst byte count. */
1023 #define CSRX_MAX_WRT_BURST_MASK	(BIT_5|BIT_4)
1024 #define MWB_512_BYTES		(0 << 4)
1025 #define MWB_1024_BYTES		(1 << 4)
1026 #define MWB_2048_BYTES		(2 << 4)
1027 #define MWB_4096_BYTES		(3 << 4)
1028 
1029 #define CSRX_64BIT_SLOT		BIT_2	/* PCI 64-Bit Bus Slot. */
1030 #define CSRX_FLASH_ENABLE	BIT_1	/* Flash BIOS Read/Write enable. */
1031 #define CSRX_ISP_SOFT_RESET	BIT_0	/* ISP soft reset. */
1032 
1033 	uint32_t ictrl;			/* Interrupt control. */
1034 #define ICRX_EN_RISC_INT	BIT_3	/* Enable RISC interrupts on PCI. */
1035 
1036 	uint32_t istatus;		/* Interrupt status. */
1037 #define ISRX_RISC_INT		BIT_3	/* RISC interrupt. */
1038 
1039 	uint32_t unused_1[2];		/* Gap. */
1040 
1041 					/* Request Queue. */
1042 	uint32_t req_q_in;		/*  In-Pointer. */
1043 	uint32_t req_q_out;		/*  Out-Pointer. */
1044 					/* Response Queue. */
1045 	uint32_t rsp_q_in;		/*  In-Pointer. */
1046 	uint32_t rsp_q_out;		/*  Out-Pointer. */
1047 					/* Priority Request Queue. */
1048 	uint32_t preq_q_in;		/*  In-Pointer. */
1049 	uint32_t preq_q_out;		/*  Out-Pointer. */
1050 
1051 	uint32_t unused_2[2];		/* Gap. */
1052 
1053 					/* ATIO Queue. */
1054 	uint32_t atio_q_in;		/*  In-Pointer. */
1055 	uint32_t atio_q_out;		/*  Out-Pointer. */
1056 
1057 	uint32_t host_status;
1058 #define HSRX_RISC_INT		BIT_15	/* RISC to Host interrupt. */
1059 #define HSRX_RISC_PAUSED	BIT_8	/* RISC Paused. */
1060 
1061 	uint32_t hccr;			/* Host command & control register. */
1062 					/* HCCR statuses. */
1063 #define HCCRX_HOST_INT		BIT_6	/* Host to RISC interrupt bit. */
1064 #define HCCRX_RISC_RESET	BIT_5	/* RISC Reset mode bit. */
1065 					/* HCCR commands. */
1066 					/* NOOP. */
1067 #define HCCRX_NOOP		0x00000000
1068 					/* Set RISC Reset. */
1069 #define HCCRX_SET_RISC_RESET	0x10000000
1070 					/* Clear RISC Reset. */
1071 #define HCCRX_CLR_RISC_RESET	0x20000000
1072 					/* Set RISC Pause. */
1073 #define HCCRX_SET_RISC_PAUSE	0x30000000
1074 					/* Releases RISC Pause. */
1075 #define HCCRX_REL_RISC_PAUSE	0x40000000
1076 					/* Set HOST to RISC interrupt. */
1077 #define HCCRX_SET_HOST_INT	0x50000000
1078 					/* Clear HOST to RISC interrupt. */
1079 #define HCCRX_CLR_HOST_INT	0x60000000
1080 					/* Clear RISC to PCI interrupt. */
1081 #define HCCRX_CLR_RISC_INT	0xA0000000
1082 
1083 	uint32_t gpiod;			/* GPIO Data register. */
1084 
1085 					/* LED update mask. */
1086 #define GPDX_LED_UPDATE_MASK	(BIT_20|BIT_19|BIT_18)
1087 					/* Data update mask. */
1088 #define GPDX_DATA_UPDATE_MASK	(BIT_17|BIT_16)
1089 					/* Data update mask. */
1090 #define GPDX_DATA_UPDATE_2_MASK	(BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1091 					/* LED control mask. */
1092 #define GPDX_LED_COLOR_MASK	(BIT_4|BIT_3|BIT_2)
1093 					/* LED bit values. Color names as
1094 					 * referenced in fw spec.
1095 					 */
1096 #define GPDX_LED_YELLOW_ON	BIT_2
1097 #define GPDX_LED_GREEN_ON	BIT_3
1098 #define GPDX_LED_AMBER_ON	BIT_4
1099 					/* Data in/out. */
1100 #define GPDX_DATA_INOUT		(BIT_1|BIT_0)
1101 
1102 	uint32_t gpioe;			/* GPIO Enable register. */
1103 					/* Enable update mask. */
1104 #define GPEX_ENABLE_UPDATE_MASK	(BIT_17|BIT_16)
1105 					/* Enable update mask. */
1106 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1107 					/* Enable. */
1108 #define GPEX_ENABLE		(BIT_1|BIT_0)
1109 
1110 	uint32_t iobase_addr;		/* I/O Bus Base Address register. */
1111 
1112 	uint32_t unused_3[10];		/* Gap. */
1113 
1114 	uint16_t mailbox0;
1115 	uint16_t mailbox1;
1116 	uint16_t mailbox2;
1117 	uint16_t mailbox3;
1118 	uint16_t mailbox4;
1119 	uint16_t mailbox5;
1120 	uint16_t mailbox6;
1121 	uint16_t mailbox7;
1122 	uint16_t mailbox8;
1123 	uint16_t mailbox9;
1124 	uint16_t mailbox10;
1125 	uint16_t mailbox11;
1126 	uint16_t mailbox12;
1127 	uint16_t mailbox13;
1128 	uint16_t mailbox14;
1129 	uint16_t mailbox15;
1130 	uint16_t mailbox16;
1131 	uint16_t mailbox17;
1132 	uint16_t mailbox18;
1133 	uint16_t mailbox19;
1134 	uint16_t mailbox20;
1135 	uint16_t mailbox21;
1136 	uint16_t mailbox22;
1137 	uint16_t mailbox23;
1138 	uint16_t mailbox24;
1139 	uint16_t mailbox25;
1140 	uint16_t mailbox26;
1141 	uint16_t mailbox27;
1142 	uint16_t mailbox28;
1143 	uint16_t mailbox29;
1144 	uint16_t mailbox30;
1145 	uint16_t mailbox31;
1146 
1147 	uint32_t iobase_window;
1148 	uint32_t iobase_c4;
1149 	uint32_t iobase_c8;
1150 	uint32_t unused_4_1[6];		/* Gap. */
1151 	uint32_t iobase_q;
1152 	uint32_t unused_5[2];		/* Gap. */
1153 	uint32_t iobase_select;
1154 	uint32_t unused_6[2];		/* Gap. */
1155 	uint32_t iobase_sdata;
1156 };
1157 /* RISC-RISC semaphore register PCI offet */
1158 #define RISC_REGISTER_BASE_OFFSET	0x7010
1159 #define RISC_REGISTER_WINDOW_OFFET	0x6
1160 
1161 /* RISC-RISC semaphore/flag register (risc address 0x7016) */
1162 
1163 #define RISC_SEMAPHORE		0x1UL
1164 #define RISC_SEMAPHORE_WE	(RISC_SEMAPHORE << 16)
1165 #define RISC_SEMAPHORE_CLR	(RISC_SEMAPHORE_WE | 0x0UL)
1166 #define RISC_SEMAPHORE_SET	(RISC_SEMAPHORE_WE | RISC_SEMAPHORE)
1167 
1168 #define RISC_SEMAPHORE_FORCE		0x8000UL
1169 #define RISC_SEMAPHORE_FORCE_WE		(RISC_SEMAPHORE_FORCE << 16)
1170 #define RISC_SEMAPHORE_FORCE_CLR	(RISC_SEMAPHORE_FORCE_WE | 0x0UL)
1171 #define RISC_SEMAPHORE_FORCE_SET	\
1172 		(RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE)
1173 
1174 /* RISC semaphore timeouts (ms) */
1175 #define TIMEOUT_SEMAPHORE		2500
1176 #define TIMEOUT_SEMAPHORE_FORCE		2000
1177 #define TIMEOUT_TOTAL_ELAPSED		4500
1178 
1179 /* Trace Control *************************************************************/
1180 
1181 #define TC_AEN_DISABLE		0
1182 
1183 #define TC_EFT_ENABLE		4
1184 #define TC_EFT_DISABLE		5
1185 
1186 #define TC_FCE_ENABLE		8
1187 #define TC_FCE_OPTIONS		0
1188 #define TC_FCE_DEFAULT_RX_SIZE	2112
1189 #define TC_FCE_DEFAULT_TX_SIZE	2112
1190 #define TC_FCE_DISABLE		9
1191 #define TC_FCE_DISABLE_TRACE	BIT_0
1192 
1193 /* MID Support ***************************************************************/
1194 
1195 #define MIN_MULTI_ID_FABRIC	64	/* Must be power-of-2. */
1196 #define MAX_MULTI_ID_FABRIC	256	/* ... */
1197 
1198 struct mid_conf_entry_24xx {
1199 	uint16_t reserved_1;
1200 
1201 	/*
1202 	 * BIT 0  = Enable Hard Loop Id
1203 	 * BIT 1  = Acquire Loop ID in LIPA
1204 	 * BIT 2  = ID not Acquired
1205 	 * BIT 3  = Enable VP
1206 	 * BIT 4  = Enable Initiator Mode
1207 	 * BIT 5  = Disable Target Mode
1208 	 * BIT 6-7 = Reserved
1209 	 */
1210 	uint8_t options;
1211 
1212 	uint8_t hard_address;
1213 
1214 	uint8_t port_name[WWN_SIZE];
1215 	uint8_t node_name[WWN_SIZE];
1216 };
1217 
1218 struct mid_init_cb_24xx {
1219 	struct init_cb_24xx init_cb;
1220 
1221 	uint16_t count;
1222 	uint16_t options;
1223 
1224 	struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1225 };
1226 
1227 
1228 struct mid_db_entry_24xx {
1229 	uint16_t status;
1230 #define MDBS_NON_PARTIC		BIT_3
1231 #define MDBS_ID_ACQUIRED	BIT_1
1232 #define MDBS_ENABLED		BIT_0
1233 
1234 	uint8_t options;
1235 	uint8_t hard_address;
1236 
1237 	uint8_t port_name[WWN_SIZE];
1238 	uint8_t node_name[WWN_SIZE];
1239 
1240 	uint8_t port_id[3];
1241 	uint8_t reserved_1;
1242 };
1243 
1244 /*
1245  * Virtual Port Control IOCB
1246  */
1247 #define VP_CTRL_IOCB_TYPE	0x30	/* Virtual Port Control entry. */
1248 struct vp_ctrl_entry_24xx {
1249 	uint8_t entry_type;		/* Entry type. */
1250 	uint8_t entry_count;		/* Entry count. */
1251 	uint8_t sys_define;		/* System defined. */
1252 	uint8_t entry_status;		/* Entry Status. */
1253 
1254 	uint32_t handle;		/* System handle. */
1255 
1256 	uint16_t vp_idx_failed;
1257 
1258 	uint16_t comp_status;		/* Completion status. */
1259 #define CS_VCE_IOCB_ERROR       0x01    /* Error processing IOCB */
1260 #define CS_VCE_ACQ_ID_ERROR	0x02	/* Error while acquireing ID. */
1261 #define CS_VCE_BUSY		0x05	/* Firmware not ready to accept cmd. */
1262 
1263 	uint16_t command;
1264 #define VCE_COMMAND_ENABLE_VPS	0x00	/* Enable VPs. */
1265 #define VCE_COMMAND_DISABLE_VPS	0x08	/* Disable VPs. */
1266 #define VCE_COMMAND_DISABLE_VPS_REINIT	0x09 /* Disable VPs and reinit link. */
1267 #define VCE_COMMAND_DISABLE_VPS_LOGO	0x0a /* Disable VPs and LOGO ports. */
1268 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL        0x0b /* Disable VPs and LOGO ports. */
1269 
1270 	uint16_t vp_count;
1271 
1272 	uint8_t vp_idx_map[16];
1273 	uint16_t flags;
1274 	uint16_t id;
1275 	uint16_t reserved_4;
1276 	uint16_t hopct;
1277 	uint8_t reserved_5[24];
1278 };
1279 
1280 /*
1281  * Modify Virtual Port Configuration IOCB
1282  */
1283 #define VP_CONFIG_IOCB_TYPE	0x31	/* Virtual Port Config entry. */
1284 struct vp_config_entry_24xx {
1285 	uint8_t entry_type;		/* Entry type. */
1286 	uint8_t entry_count;		/* Entry count. */
1287 	uint8_t handle_count;
1288 	uint8_t entry_status;		/* Entry Status. */
1289 
1290 	uint32_t handle;		/* System handle. */
1291 
1292 	uint16_t flags;
1293 #define CS_VF_BIND_VPORTS_TO_VF         BIT_0
1294 #define CS_VF_SET_QOS_OF_VPORTS         BIT_1
1295 #define CS_VF_SET_HOPS_OF_VPORTS        BIT_2
1296 
1297 	uint16_t comp_status;		/* Completion status. */
1298 #define CS_VCT_STS_ERROR	0x01	/* Specified VPs were not disabled. */
1299 #define CS_VCT_CNT_ERROR	0x02	/* Invalid VP count. */
1300 #define CS_VCT_ERROR		0x03	/* Unknown error. */
1301 #define CS_VCT_IDX_ERROR	0x02	/* Invalid VP index. */
1302 #define CS_VCT_BUSY		0x05	/* Firmware not ready to accept cmd. */
1303 
1304 	uint8_t command;
1305 #define VCT_COMMAND_MOD_VPS     0x00    /* Modify VP configurations. */
1306 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1307 
1308 	uint8_t vp_count;
1309 
1310 	uint8_t vp_index1;
1311 	uint8_t vp_index2;
1312 
1313 	uint8_t options_idx1;
1314 	uint8_t hard_address_idx1;
1315 	uint16_t reserved_vp1;
1316 	uint8_t port_name_idx1[WWN_SIZE];
1317 	uint8_t node_name_idx1[WWN_SIZE];
1318 
1319 	uint8_t options_idx2;
1320 	uint8_t hard_address_idx2;
1321 	uint16_t reserved_vp2;
1322 	uint8_t port_name_idx2[WWN_SIZE];
1323 	uint8_t node_name_idx2[WWN_SIZE];
1324 	uint16_t id;
1325 	uint16_t reserved_4;
1326 	uint16_t hopct;
1327 	uint8_t reserved_5[2];
1328 };
1329 
1330 #define VP_RPT_ID_IOCB_TYPE	0x32	/* Report ID Acquisition entry. */
1331 enum VP_STATUS {
1332 	VP_STAT_COMPL,
1333 	VP_STAT_FAIL,
1334 	VP_STAT_ID_CHG,
1335 	VP_STAT_SNS_TO,				/* timeout */
1336 	VP_STAT_SNS_RJT,
1337 	VP_STAT_SCR_TO,				/* timeout */
1338 	VP_STAT_SCR_RJT,
1339 };
1340 
1341 enum VP_FLAGS {
1342 	VP_FLAGS_CON_FLOOP = 1,
1343 	VP_FLAGS_CON_P2P = 2,
1344 	VP_FLAGS_CON_FABRIC = 3,
1345 	VP_FLAGS_NAME_VALID = BIT_5,
1346 };
1347 
1348 struct vp_rpt_id_entry_24xx {
1349 	uint8_t entry_type;		/* Entry type. */
1350 	uint8_t entry_count;		/* Entry count. */
1351 	uint8_t sys_define;		/* System defined. */
1352 	uint8_t entry_status;		/* Entry Status. */
1353 	uint32_t resv1;
1354 	uint8_t vp_acquired;
1355 	uint8_t vp_setup;
1356 	uint8_t vp_idx;		/* Format 0=reserved */
1357 	uint8_t vp_status;	/* Format 0=reserved */
1358 
1359 	uint8_t port_id[3];
1360 	uint8_t format;
1361 	union {
1362 		struct {
1363 			/* format 0 loop */
1364 			uint8_t vp_idx_map[16];
1365 			uint8_t reserved_4[32];
1366 		} f0;
1367 		struct {
1368 			/* format 1 fabric */
1369 			uint8_t vpstat1_subcode; /* vp_status=1 subcode */
1370 			uint8_t flags;
1371 			uint16_t fip_flags;
1372 			uint8_t rsv2[12];
1373 
1374 			uint8_t ls_rjt_vendor;
1375 			uint8_t ls_rjt_explanation;
1376 			uint8_t ls_rjt_reason;
1377 			uint8_t rsv3[5];
1378 
1379 			uint8_t port_name[8];
1380 			uint8_t node_name[8];
1381 			uint16_t bbcr;
1382 			uint8_t reserved_5[6];
1383 		} f1;
1384 		struct { /* format 2: N2N direct connect */
1385 		    uint8_t vpstat1_subcode;
1386 		    uint8_t flags;
1387 		    uint16_t rsv6;
1388 		    uint8_t rsv2[12];
1389 
1390 		    uint8_t ls_rjt_vendor;
1391 		    uint8_t ls_rjt_explanation;
1392 		    uint8_t ls_rjt_reason;
1393 		    uint8_t rsv3[5];
1394 
1395 		    uint8_t port_name[8];
1396 		    uint8_t node_name[8];
1397 		    uint32_t remote_nport_id;
1398 		    uint32_t reserved_5;
1399 		} f2;
1400 	} u;
1401 };
1402 
1403 #define VF_EVFP_IOCB_TYPE       0x26    /* Exchange Virtual Fabric Parameters entry. */
1404 struct vf_evfp_entry_24xx {
1405         uint8_t entry_type;             /* Entry type. */
1406         uint8_t entry_count;            /* Entry count. */
1407         uint8_t sys_define;             /* System defined. */
1408         uint8_t entry_status;           /* Entry Status. */
1409 
1410         uint32_t handle;                /* System handle. */
1411         uint16_t comp_status;           /* Completion status. */
1412         uint16_t timeout;               /* timeout */
1413         uint16_t adim_tagging_mode;
1414 
1415         uint16_t vfport_id;
1416         uint32_t exch_addr;
1417 
1418         uint16_t nport_handle;          /* N_PORT handle. */
1419         uint16_t control_flags;
1420         uint32_t io_parameter_0;
1421         uint32_t io_parameter_1;
1422         uint32_t tx_address[2];         /* Data segment 0 address. */
1423         uint32_t tx_len;                /* Data segment 0 length. */
1424         uint32_t rx_address[2];         /* Data segment 1 address. */
1425         uint32_t rx_len;                /* Data segment 1 length. */
1426 };
1427 
1428 /* END MID Support ***********************************************************/
1429 
1430 /* Flash Description Table ***************************************************/
1431 
1432 struct qla_fdt_layout {
1433 	uint8_t sig[4];
1434 	uint16_t version;
1435 	uint16_t len;
1436 	uint16_t checksum;
1437 	uint8_t unused1[2];
1438 	uint8_t model[16];
1439 	uint16_t man_id;
1440 	uint16_t id;
1441 	uint8_t flags;
1442 	uint8_t erase_cmd;
1443 	uint8_t alt_erase_cmd;
1444 	uint8_t wrt_enable_cmd;
1445 	uint8_t wrt_enable_bits;
1446 	uint8_t wrt_sts_reg_cmd;
1447 	uint8_t unprotect_sec_cmd;
1448 	uint8_t read_man_id_cmd;
1449 	uint32_t block_size;
1450 	uint32_t alt_block_size;
1451 	uint32_t flash_size;
1452 	uint32_t wrt_enable_data;
1453 	uint8_t read_id_addr_len;
1454 	uint8_t wrt_disable_bits;
1455 	uint8_t read_dev_id_len;
1456 	uint8_t chip_erase_cmd;
1457 	uint16_t read_timeout;
1458 	uint8_t protect_sec_cmd;
1459 	uint8_t unused2[65];
1460 };
1461 
1462 /* Flash Layout Table ********************************************************/
1463 
1464 struct qla_flt_location {
1465 	uint8_t sig[4];
1466 	uint16_t start_lo;
1467 	uint16_t start_hi;
1468 	uint8_t version;
1469 	uint8_t unused[5];
1470 	uint16_t checksum;
1471 };
1472 
1473 struct qla_flt_header {
1474 	uint16_t version;
1475 	uint16_t length;
1476 	uint16_t checksum;
1477 	uint16_t unused;
1478 };
1479 
1480 #define FLT_REG_FW		0x01
1481 #define FLT_REG_BOOT_CODE	0x07
1482 #define FLT_REG_VPD_0		0x14
1483 #define FLT_REG_NVRAM_0		0x15
1484 #define FLT_REG_VPD_1		0x16
1485 #define FLT_REG_NVRAM_1		0x17
1486 #define FLT_REG_VPD_2		0xD4
1487 #define FLT_REG_NVRAM_2		0xD5
1488 #define FLT_REG_VPD_3		0xD6
1489 #define FLT_REG_NVRAM_3		0xD7
1490 #define FLT_REG_FDT		0x1a
1491 #define FLT_REG_FLT		0x1c
1492 #define FLT_REG_HW_EVENT_0	0x1d
1493 #define FLT_REG_HW_EVENT_1	0x1f
1494 #define FLT_REG_NPIV_CONF_0	0x29
1495 #define FLT_REG_NPIV_CONF_1	0x2a
1496 #define FLT_REG_GOLD_FW		0x2f
1497 #define FLT_REG_FCP_PRIO_0	0x87
1498 #define FLT_REG_FCP_PRIO_1	0x88
1499 #define FLT_REG_CNA_FW		0x97
1500 #define FLT_REG_BOOT_CODE_8044	0xA2
1501 #define FLT_REG_FCOE_FW		0xA4
1502 #define FLT_REG_FCOE_NVRAM_0	0xAA
1503 #define FLT_REG_FCOE_NVRAM_1	0xAC
1504 
1505 /* 27xx */
1506 #define FLT_REG_IMG_PRI_27XX	0x95
1507 #define FLT_REG_IMG_SEC_27XX	0x96
1508 #define FLT_REG_FW_SEC_27XX	0x02
1509 #define FLT_REG_BOOTLOAD_SEC_27XX	0x9
1510 #define FLT_REG_VPD_SEC_27XX_0	0x50
1511 #define FLT_REG_VPD_SEC_27XX_1	0x52
1512 #define FLT_REG_VPD_SEC_27XX_2	0xD8
1513 #define FLT_REG_VPD_SEC_27XX_3	0xDA
1514 
1515 struct qla_flt_region {
1516 	uint32_t code;
1517 	uint32_t size;
1518 	uint32_t start;
1519 	uint32_t end;
1520 };
1521 
1522 /* Flash NPIV Configuration Table ********************************************/
1523 
1524 struct qla_npiv_header {
1525 	uint8_t sig[2];
1526 	uint16_t version;
1527 	uint16_t entries;
1528 	uint16_t unused[4];
1529 	uint16_t checksum;
1530 };
1531 
1532 struct qla_npiv_entry {
1533 	uint16_t flags;
1534 	uint16_t vf_id;
1535 	uint8_t q_qos;
1536 	uint8_t f_qos;
1537 	uint16_t unused1;
1538 	uint8_t port_name[WWN_SIZE];
1539 	uint8_t node_name[WWN_SIZE];
1540 };
1541 
1542 /* 84XX Support **************************************************************/
1543 
1544 #define MBA_ISP84XX_ALERT	0x800f  /* Alert Notification. */
1545 #define A84_PANIC_RECOVERY	0x1
1546 #define A84_OP_LOGIN_COMPLETE	0x2
1547 #define A84_DIAG_LOGIN_COMPLETE	0x3
1548 #define A84_GOLD_LOGIN_COMPLETE	0x4
1549 
1550 #define MBC_ISP84XX_RESET	0x3a    /* Reset. */
1551 
1552 #define FSTATE_REMOTE_FC_DOWN	BIT_0
1553 #define FSTATE_NSL_LINK_DOWN	BIT_1
1554 #define FSTATE_IS_DIAG_FW	BIT_2
1555 #define FSTATE_LOGGED_IN	BIT_3
1556 #define FSTATE_WAITING_FOR_VERIFY	BIT_4
1557 
1558 #define VERIFY_CHIP_IOCB_TYPE	0x1B
1559 struct verify_chip_entry_84xx {
1560 	uint8_t entry_type;
1561 	uint8_t entry_count;
1562 	uint8_t sys_defined;
1563 	uint8_t entry_status;
1564 
1565 	uint32_t handle;
1566 
1567 	uint16_t options;
1568 #define VCO_DONT_UPDATE_FW	BIT_0
1569 #define VCO_FORCE_UPDATE	BIT_1
1570 #define VCO_DONT_RESET_UPDATE	BIT_2
1571 #define VCO_DIAG_FW		BIT_3
1572 #define VCO_END_OF_DATA		BIT_14
1573 #define VCO_ENABLE_DSD		BIT_15
1574 
1575 	uint16_t reserved_1;
1576 
1577 	uint16_t data_seg_cnt;
1578 	uint16_t reserved_2[3];
1579 
1580 	uint32_t fw_ver;
1581 	uint32_t exchange_address;
1582 
1583 	uint32_t reserved_3[3];
1584 	uint32_t fw_size;
1585 	uint32_t fw_seq_size;
1586 	uint32_t relative_offset;
1587 
1588 	uint32_t dseg_address[2];
1589 	uint32_t dseg_length;
1590 };
1591 
1592 struct verify_chip_rsp_84xx {
1593 	uint8_t entry_type;
1594 	uint8_t entry_count;
1595 	uint8_t sys_defined;
1596 	uint8_t entry_status;
1597 
1598 	uint32_t handle;
1599 
1600 	uint16_t comp_status;
1601 #define CS_VCS_CHIP_FAILURE	0x3
1602 #define CS_VCS_BAD_EXCHANGE	0x8
1603 #define CS_VCS_SEQ_COMPLETEi	0x40
1604 
1605 	uint16_t failure_code;
1606 #define VFC_CHECKSUM_ERROR	0x1
1607 #define VFC_INVALID_LEN		0x2
1608 #define VFC_ALREADY_IN_PROGRESS	0x8
1609 
1610 	uint16_t reserved_1[4];
1611 
1612 	uint32_t fw_ver;
1613 	uint32_t exchange_address;
1614 
1615 	uint32_t reserved_2[6];
1616 };
1617 
1618 #define ACCESS_CHIP_IOCB_TYPE	0x2B
1619 struct access_chip_84xx {
1620 	uint8_t entry_type;
1621 	uint8_t entry_count;
1622 	uint8_t sys_defined;
1623 	uint8_t entry_status;
1624 
1625 	uint32_t handle;
1626 
1627 	uint16_t options;
1628 #define ACO_DUMP_MEMORY		0x0
1629 #define ACO_LOAD_MEMORY		0x1
1630 #define ACO_CHANGE_CONFIG_PARAM	0x2
1631 #define ACO_REQUEST_INFO	0x3
1632 
1633 	uint16_t reserved1;
1634 
1635 	uint16_t dseg_count;
1636 	uint16_t reserved2[3];
1637 
1638 	uint32_t parameter1;
1639 	uint32_t parameter2;
1640 	uint32_t parameter3;
1641 
1642 	uint32_t reserved3[3];
1643 	uint32_t total_byte_cnt;
1644 	uint32_t reserved4;
1645 
1646 	uint32_t dseg_address[2];
1647 	uint32_t dseg_length;
1648 };
1649 
1650 struct access_chip_rsp_84xx {
1651 	uint8_t entry_type;
1652 	uint8_t entry_count;
1653 	uint8_t sys_defined;
1654 	uint8_t entry_status;
1655 
1656 	uint32_t handle;
1657 
1658 	uint16_t comp_status;
1659 	uint16_t failure_code;
1660 	uint32_t residual_count;
1661 
1662 	uint32_t reserved[12];
1663 };
1664 
1665 /* 81XX Support **************************************************************/
1666 
1667 #define MBA_DCBX_START		0x8016
1668 #define MBA_DCBX_COMPLETE	0x8030
1669 #define MBA_FCF_CONF_ERR	0x8031
1670 #define MBA_DCBX_PARAM_UPDATE	0x8032
1671 #define MBA_IDC_COMPLETE	0x8100
1672 #define MBA_IDC_NOTIFY		0x8101
1673 #define MBA_IDC_TIME_EXT	0x8102
1674 
1675 #define MBC_IDC_ACK		0x101
1676 #define MBC_RESTART_MPI_FW	0x3d
1677 #define MBC_FLASH_ACCESS_CTRL	0x3e	/* Control flash access. */
1678 #define MBC_GET_XGMAC_STATS	0x7a
1679 #define MBC_GET_DCBX_PARAMS	0x51
1680 
1681 /*
1682  * ISP83xx mailbox commands
1683  */
1684 #define MBC_WRITE_REMOTE_REG		0x0001 /* Write remote register */
1685 #define MBC_READ_REMOTE_REG		0x0009 /* Read remote register */
1686 #define MBC_RESTART_NIC_FIRMWARE	0x003d /* Restart NIC firmware */
1687 #define MBC_SET_ACCESS_CONTROL		0x003e /* Access control command */
1688 
1689 /* Flash access control option field bit definitions */
1690 #define FAC_OPT_FORCE_SEMAPHORE		BIT_15
1691 #define FAC_OPT_REQUESTOR_ID		BIT_14
1692 #define FAC_OPT_CMD_SUBCODE		0xff
1693 
1694 /* Flash access control command subcodes */
1695 #define FAC_OPT_CMD_WRITE_PROTECT	0x00
1696 #define FAC_OPT_CMD_WRITE_ENABLE	0x01
1697 #define FAC_OPT_CMD_ERASE_SECTOR	0x02
1698 #define FAC_OPT_CMD_LOCK_SEMAPHORE	0x03
1699 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE	0x04
1700 #define FAC_OPT_CMD_GET_SECTOR_SIZE	0x05
1701 
1702 struct nvram_81xx {
1703 	/* NVRAM header. */
1704 	uint8_t id[4];
1705 	uint16_t nvram_version;
1706 	uint16_t reserved_0;
1707 
1708 	/* Firmware Initialization Control Block. */
1709 	uint16_t version;
1710 	uint16_t reserved_1;
1711 	uint16_t frame_payload_size;
1712 	uint16_t execution_throttle;
1713 	uint16_t exchange_count;
1714 	uint16_t reserved_2;
1715 
1716 	uint8_t port_name[WWN_SIZE];
1717 	uint8_t node_name[WWN_SIZE];
1718 
1719 	uint16_t login_retry_count;
1720 	uint16_t reserved_3;
1721 	uint16_t interrupt_delay_timer;
1722 	uint16_t login_timeout;
1723 
1724 	uint32_t firmware_options_1;
1725 	uint32_t firmware_options_2;
1726 	uint32_t firmware_options_3;
1727 
1728 	uint16_t reserved_4[4];
1729 
1730 	/* Offset 64. */
1731 	uint8_t enode_mac[6];
1732 	uint16_t reserved_5[5];
1733 
1734 	/* Offset 80. */
1735 	uint16_t reserved_6[24];
1736 
1737 	/* Offset 128. */
1738 	uint16_t ex_version;
1739 	uint8_t prio_fcf_matching_flags;
1740 	uint8_t reserved_6_1[3];
1741 	uint16_t pri_fcf_vlan_id;
1742 	uint8_t pri_fcf_fabric_name[8];
1743 	uint16_t reserved_6_2[7];
1744 	uint8_t spma_mac_addr[6];
1745 	uint16_t reserved_6_3[14];
1746 
1747 	/* Offset 192. */
1748 	uint16_t reserved_7[32];
1749 
1750 	/*
1751 	 * BIT 0  = Enable spinup delay
1752 	 * BIT 1  = Disable BIOS
1753 	 * BIT 2  = Enable Memory Map BIOS
1754 	 * BIT 3  = Enable Selectable Boot
1755 	 * BIT 4  = Disable RISC code load
1756 	 * BIT 5  = Disable Serdes
1757 	 * BIT 6  = Opt boot mode
1758 	 * BIT 7  = Interrupt enable
1759 	 *
1760 	 * BIT 8  = EV Control enable
1761 	 * BIT 9  = Enable lip reset
1762 	 * BIT 10 = Enable lip full login
1763 	 * BIT 11 = Enable target reset
1764 	 * BIT 12 = Stop firmware
1765 	 * BIT 13 = Enable nodename option
1766 	 * BIT 14 = Default WWPN valid
1767 	 * BIT 15 = Enable alternate WWN
1768 	 *
1769 	 * BIT 16 = CLP LUN string
1770 	 * BIT 17 = CLP Target string
1771 	 * BIT 18 = CLP BIOS enable string
1772 	 * BIT 19 = CLP Serdes string
1773 	 * BIT 20 = CLP WWPN string
1774 	 * BIT 21 = CLP WWNN string
1775 	 * BIT 22 =
1776 	 * BIT 23 =
1777 	 * BIT 24 = Keep WWPN
1778 	 * BIT 25 = Temp WWPN
1779 	 * BIT 26-31 =
1780 	 */
1781 	uint32_t host_p;
1782 
1783 	uint8_t alternate_port_name[WWN_SIZE];
1784 	uint8_t alternate_node_name[WWN_SIZE];
1785 
1786 	uint8_t boot_port_name[WWN_SIZE];
1787 	uint16_t boot_lun_number;
1788 	uint16_t reserved_8;
1789 
1790 	uint8_t alt1_boot_port_name[WWN_SIZE];
1791 	uint16_t alt1_boot_lun_number;
1792 	uint16_t reserved_9;
1793 
1794 	uint8_t alt2_boot_port_name[WWN_SIZE];
1795 	uint16_t alt2_boot_lun_number;
1796 	uint16_t reserved_10;
1797 
1798 	uint8_t alt3_boot_port_name[WWN_SIZE];
1799 	uint16_t alt3_boot_lun_number;
1800 	uint16_t reserved_11;
1801 
1802 	/*
1803 	 * BIT 0 = Selective Login
1804 	 * BIT 1 = Alt-Boot Enable
1805 	 * BIT 2 = Reserved
1806 	 * BIT 3 = Boot Order List
1807 	 * BIT 4 = Reserved
1808 	 * BIT 5 = Selective LUN
1809 	 * BIT 6 = Reserved
1810 	 * BIT 7-31 =
1811 	 */
1812 	uint32_t efi_parameters;
1813 
1814 	uint8_t reset_delay;
1815 	uint8_t reserved_12;
1816 	uint16_t reserved_13;
1817 
1818 	uint16_t boot_id_number;
1819 	uint16_t reserved_14;
1820 
1821 	uint16_t max_luns_per_target;
1822 	uint16_t reserved_15;
1823 
1824 	uint16_t port_down_retry_count;
1825 	uint16_t link_down_timeout;
1826 
1827 	/* FCode parameters. */
1828 	uint16_t fcode_parameter;
1829 
1830 	uint16_t reserved_16[3];
1831 
1832 	/* Offset 352. */
1833 	uint8_t reserved_17[4];
1834 	uint16_t reserved_18[5];
1835 	uint8_t reserved_19[2];
1836 	uint16_t reserved_20[8];
1837 
1838 	/* Offset 384. */
1839 	uint8_t reserved_21[16];
1840 	uint16_t reserved_22[3];
1841 
1842 	/*
1843 	 * BIT 0 = Extended BB credits for LR
1844 	 * BIT 1 = Virtual Fabric Enable
1845 	 * BIT 2 = Enhanced Features Unused
1846 	 * BIT 3-7 = Enhanced Features Reserved
1847 	 */
1848 	/* Enhanced Features */
1849 	uint8_t enhanced_features;
1850 
1851 	uint8_t reserved_23;
1852 	uint16_t reserved_24[4];
1853 
1854 	/* Offset 416. */
1855 	uint16_t reserved_25[32];
1856 
1857 	/* Offset 480. */
1858 	uint8_t model_name[16];
1859 
1860 	/* Offset 496. */
1861 	uint16_t feature_mask_l;
1862 	uint16_t feature_mask_h;
1863 	uint16_t reserved_26[2];
1864 
1865 	uint16_t subsystem_vendor_id;
1866 	uint16_t subsystem_device_id;
1867 
1868 	uint32_t checksum;
1869 };
1870 
1871 /*
1872  * ISP Initialization Control Block.
1873  * Little endian except where noted.
1874  */
1875 #define	ICB_VERSION 1
1876 struct init_cb_81xx {
1877 	uint16_t version;
1878 	uint16_t reserved_1;
1879 
1880 	uint16_t frame_payload_size;
1881 	uint16_t execution_throttle;
1882 	uint16_t exchange_count;
1883 
1884 	uint16_t reserved_2;
1885 
1886 	uint8_t port_name[WWN_SIZE];		/* Big endian. */
1887 	uint8_t node_name[WWN_SIZE];		/* Big endian. */
1888 
1889 	uint16_t response_q_inpointer;
1890 	uint16_t request_q_outpointer;
1891 
1892 	uint16_t login_retry_count;
1893 
1894 	uint16_t prio_request_q_outpointer;
1895 
1896 	uint16_t response_q_length;
1897 	uint16_t request_q_length;
1898 
1899 	uint16_t reserved_3;
1900 
1901 	uint16_t prio_request_q_length;
1902 
1903 	uint32_t request_q_address[2];
1904 	uint32_t response_q_address[2];
1905 	uint32_t prio_request_q_address[2];
1906 
1907 	uint8_t reserved_4[8];
1908 
1909 	uint16_t atio_q_inpointer;
1910 	uint16_t atio_q_length;
1911 	uint32_t atio_q_address[2];
1912 
1913 	uint16_t interrupt_delay_timer;		/* 100us increments. */
1914 	uint16_t login_timeout;
1915 
1916 	/*
1917 	 * BIT 0-3 = Reserved
1918 	 * BIT 4  = Enable Target Mode
1919 	 * BIT 5  = Disable Initiator Mode
1920 	 * BIT 6  = Reserved
1921 	 * BIT 7  = Reserved
1922 	 *
1923 	 * BIT 8-13 = Reserved
1924 	 * BIT 14 = Node Name Option
1925 	 * BIT 15-31 = Reserved
1926 	 */
1927 	uint32_t firmware_options_1;
1928 
1929 	/*
1930 	 * BIT 0  = Operation Mode bit 0
1931 	 * BIT 1  = Operation Mode bit 1
1932 	 * BIT 2  = Operation Mode bit 2
1933 	 * BIT 3  = Operation Mode bit 3
1934 	 * BIT 4-7 = Reserved
1935 	 *
1936 	 * BIT 8  = Enable Class 2
1937 	 * BIT 9  = Enable ACK0
1938 	 * BIT 10 = Reserved
1939 	 * BIT 11 = Enable FC-SP Security
1940 	 * BIT 12 = FC Tape Enable
1941 	 * BIT 13 = Reserved
1942 	 * BIT 14 = Enable Target PRLI Control
1943 	 * BIT 15-31 = Reserved
1944 	 */
1945 	uint32_t firmware_options_2;
1946 
1947 	/*
1948 	 * BIT 0-3 = Reserved
1949 	 * BIT 4  = FCP RSP Payload bit 0
1950 	 * BIT 5  = FCP RSP Payload bit 1
1951 	 * BIT 6  = Enable Receive Out-of-Order data frame handling
1952 	 * BIT 7  = Reserved
1953 	 *
1954 	 * BIT 8  = Reserved
1955 	 * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative offset handling
1956 	 * BIT 10-16 = Reserved
1957 	 * BIT 17 = Enable multiple FCFs
1958 	 * BIT 18-20 = MAC addressing mode
1959 	 * BIT 21-25 = Ethernet data rate
1960 	 * BIT 26 = Enable ethernet header rx IOCB for ATIO q
1961 	 * BIT 27 = Enable ethernet header rx IOCB for response q
1962 	 * BIT 28 = SPMA selection bit 0
1963 	 * BIT 28 = SPMA selection bit 1
1964 	 * BIT 30-31 = Reserved
1965 	 */
1966 	uint32_t firmware_options_3;
1967 
1968 	uint8_t  reserved_5[8];
1969 
1970 	uint8_t enode_mac[6];
1971 
1972 	uint8_t reserved_6[10];
1973 };
1974 
1975 struct mid_init_cb_81xx {
1976 	struct init_cb_81xx init_cb;
1977 
1978 	uint16_t count;
1979 	uint16_t options;
1980 
1981 	struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1982 };
1983 
1984 struct ex_init_cb_81xx {
1985 	uint16_t ex_version;
1986 	uint8_t prio_fcf_matching_flags;
1987 	uint8_t reserved_1[3];
1988 	uint16_t pri_fcf_vlan_id;
1989 	uint8_t pri_fcf_fabric_name[8];
1990 	uint16_t reserved_2[7];
1991 	uint8_t spma_mac_addr[6];
1992 	uint16_t reserved_3[14];
1993 };
1994 
1995 #define FARX_ACCESS_FLASH_CONF_81XX	0x7FFD0000
1996 #define FARX_ACCESS_FLASH_DATA_81XX	0x7F800000
1997 
1998 /* FCP priority config defines *************************************/
1999 /* operations */
2000 #define QLFC_FCP_PRIO_DISABLE           0x0
2001 #define QLFC_FCP_PRIO_ENABLE            0x1
2002 #define QLFC_FCP_PRIO_GET_CONFIG        0x2
2003 #define QLFC_FCP_PRIO_SET_CONFIG        0x3
2004 
2005 struct qla_fcp_prio_entry {
2006 	uint16_t flags;         /* Describes parameter(s) in FCP        */
2007 	/* priority entry that are valid        */
2008 #define FCP_PRIO_ENTRY_VALID            0x1
2009 #define FCP_PRIO_ENTRY_TAG_VALID        0x2
2010 #define FCP_PRIO_ENTRY_SPID_VALID       0x4
2011 #define FCP_PRIO_ENTRY_DPID_VALID       0x8
2012 #define FCP_PRIO_ENTRY_LUNB_VALID       0x10
2013 #define FCP_PRIO_ENTRY_LUNE_VALID       0x20
2014 #define FCP_PRIO_ENTRY_SWWN_VALID       0x40
2015 #define FCP_PRIO_ENTRY_DWWN_VALID       0x80
2016 	uint8_t  tag;           /* Priority value                   */
2017 	uint8_t  reserved;      /* Reserved for future use          */
2018 	uint32_t src_pid;       /* Src port id. high order byte     */
2019 				/* unused; -1 (wild card)           */
2020 	uint32_t dst_pid;       /* Src port id. high order byte     */
2021 	/* unused; -1 (wild card)           */
2022 	uint16_t lun_beg;       /* 1st lun num of lun range.        */
2023 				/* -1 (wild card)                   */
2024 	uint16_t lun_end;       /* 2nd lun num of lun range.        */
2025 				/* -1 (wild card)                   */
2026 	uint8_t  src_wwpn[8];   /* Source WWPN: -1 (wild card)      */
2027 	uint8_t  dst_wwpn[8];   /* Destination WWPN: -1 (wild card) */
2028 };
2029 
2030 struct qla_fcp_prio_cfg {
2031 	uint8_t  signature[4];  /* "HQOS" signature of config data  */
2032 	uint16_t version;       /* 1: Initial version               */
2033 	uint16_t length;        /* config data size in num bytes    */
2034 	uint16_t checksum;      /* config data bytes checksum       */
2035 	uint16_t num_entries;   /* Number of entries                */
2036 	uint16_t size_of_entry; /* Size of each entry in num bytes  */
2037 	uint8_t  attributes;    /* enable/disable, persistence      */
2038 #define FCP_PRIO_ATTR_DISABLE   0x0
2039 #define FCP_PRIO_ATTR_ENABLE    0x1
2040 #define FCP_PRIO_ATTR_PERSIST   0x2
2041 	uint8_t  reserved;      /* Reserved for future use          */
2042 #define FCP_PRIO_CFG_HDR_SIZE   0x10
2043 	struct qla_fcp_prio_entry entry[1];     /* fcp priority entries  */
2044 #define FCP_PRIO_CFG_ENTRY_SIZE 0x20
2045 };
2046 
2047 #define FCP_PRIO_CFG_SIZE       (32*1024) /* fcp prio data per port*/
2048 
2049 /* 25XX Support ****************************************************/
2050 #define FA_FCP_PRIO0_ADDR_25	0x3C000
2051 #define FA_FCP_PRIO1_ADDR_25	0x3E000
2052 
2053 /* 81XX Flash locations -- occupies second 2MB region. */
2054 #define FA_BOOT_CODE_ADDR_81	0x80000
2055 #define FA_RISC_CODE_ADDR_81	0xA0000
2056 #define FA_FW_AREA_ADDR_81	0xC0000
2057 #define FA_VPD_NVRAM_ADDR_81	0xD0000
2058 #define FA_VPD0_ADDR_81		0xD0000
2059 #define FA_VPD1_ADDR_81		0xD0400
2060 #define FA_NVRAM0_ADDR_81	0xD0080
2061 #define FA_NVRAM1_ADDR_81	0xD0180
2062 #define FA_FEATURE_ADDR_81	0xD4000
2063 #define FA_FLASH_DESCR_ADDR_81	0xD8000
2064 #define FA_FLASH_LAYOUT_ADDR_81	0xD8400
2065 #define FA_HW_EVENT0_ADDR_81	0xDC000
2066 #define FA_HW_EVENT1_ADDR_81	0xDC400
2067 #define FA_NPIV_CONF0_ADDR_81	0xD1000
2068 #define FA_NPIV_CONF1_ADDR_81	0xD2000
2069 
2070 /* 83XX Flash locations -- occupies second 8MB region. */
2071 #define FA_FLASH_LAYOUT_ADDR_83	0xFC400
2072 
2073 #endif
2074