1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_FW_H 8 #define __QLA_FW_H 9 10 #define MBS_CHECKSUM_ERROR 0x4010 11 #define MBS_INVALID_PRODUCT_KEY 0x4020 12 13 /* 14 * Firmware Options. 15 */ 16 #define FO1_ENABLE_PUREX BIT_10 17 #define FO1_DISABLE_LED_CTRL BIT_6 18 #define FO1_ENABLE_8016 BIT_0 19 #define FO2_ENABLE_SEL_CLASS2 BIT_5 20 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14 21 #define FO3_HOLD_STS_IOCB BIT_12 22 23 /* 24 * Port Database structure definition for ISP 24xx. 25 */ 26 #define PDO_FORCE_ADISC BIT_1 27 #define PDO_FORCE_PLOGI BIT_0 28 29 30 #define PORT_DATABASE_24XX_SIZE 64 31 struct port_database_24xx { 32 uint16_t flags; 33 #define PDF_TASK_RETRY_ID BIT_14 34 #define PDF_FC_TAPE BIT_7 35 #define PDF_ACK0_CAPABLE BIT_6 36 #define PDF_FCP2_CONF BIT_5 37 #define PDF_CLASS_2 BIT_4 38 #define PDF_HARD_ADDR BIT_1 39 40 uint8_t current_login_state; 41 uint8_t last_login_state; 42 #define PDS_PLOGI_PENDING 0x03 43 #define PDS_PLOGI_COMPLETE 0x04 44 #define PDS_PRLI_PENDING 0x05 45 #define PDS_PRLI_COMPLETE 0x06 46 #define PDS_PORT_UNAVAILABLE 0x07 47 #define PDS_PRLO_PENDING 0x09 48 #define PDS_LOGO_PENDING 0x11 49 #define PDS_PRLI2_PENDING 0x12 50 51 uint8_t hard_address[3]; 52 uint8_t reserved_1; 53 54 uint8_t port_id[3]; 55 uint8_t sequence_id; 56 57 uint16_t port_timer; 58 59 uint16_t nport_handle; /* N_PORT handle. */ 60 61 uint16_t receive_data_size; 62 uint16_t reserved_2; 63 64 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 65 /* Bits 15-0 of word 0 */ 66 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 67 /* Bits 15-0 of word 3 */ 68 69 uint8_t port_name[WWN_SIZE]; 70 uint8_t node_name[WWN_SIZE]; 71 72 uint8_t reserved_3[24]; 73 }; 74 75 struct vp_database_24xx { 76 uint16_t vp_status; 77 uint8_t options; 78 uint8_t id; 79 uint8_t port_name[WWN_SIZE]; 80 uint8_t node_name[WWN_SIZE]; 81 uint16_t port_id_low; 82 uint16_t port_id_high; 83 }; 84 85 struct nvram_24xx { 86 /* NVRAM header. */ 87 uint8_t id[4]; 88 uint16_t nvram_version; 89 uint16_t reserved_0; 90 91 /* Firmware Initialization Control Block. */ 92 uint16_t version; 93 uint16_t reserved_1; 94 __le16 frame_payload_size; 95 uint16_t execution_throttle; 96 uint16_t exchange_count; 97 uint16_t hard_address; 98 99 uint8_t port_name[WWN_SIZE]; 100 uint8_t node_name[WWN_SIZE]; 101 102 uint16_t login_retry_count; 103 uint16_t link_down_on_nos; 104 uint16_t interrupt_delay_timer; 105 uint16_t login_timeout; 106 107 uint32_t firmware_options_1; 108 uint32_t firmware_options_2; 109 uint32_t firmware_options_3; 110 111 /* Offset 56. */ 112 113 /* 114 * BIT 0 = Control Enable 115 * BIT 1-15 = 116 * 117 * BIT 0-7 = Reserved 118 * BIT 8-10 = Output Swing 1G 119 * BIT 11-13 = Output Emphasis 1G 120 * BIT 14-15 = Reserved 121 * 122 * BIT 0-7 = Reserved 123 * BIT 8-10 = Output Swing 2G 124 * BIT 11-13 = Output Emphasis 2G 125 * BIT 14-15 = Reserved 126 * 127 * BIT 0-7 = Reserved 128 * BIT 8-10 = Output Swing 4G 129 * BIT 11-13 = Output Emphasis 4G 130 * BIT 14-15 = Reserved 131 */ 132 uint16_t seriallink_options[4]; 133 134 uint16_t reserved_2[16]; 135 136 /* Offset 96. */ 137 uint16_t reserved_3[16]; 138 139 /* PCIe table entries. */ 140 uint16_t reserved_4[16]; 141 142 /* Offset 160. */ 143 uint16_t reserved_5[16]; 144 145 /* Offset 192. */ 146 uint16_t reserved_6[16]; 147 148 /* Offset 224. */ 149 uint16_t reserved_7[16]; 150 151 /* 152 * BIT 0 = Enable spinup delay 153 * BIT 1 = Disable BIOS 154 * BIT 2 = Enable Memory Map BIOS 155 * BIT 3 = Enable Selectable Boot 156 * BIT 4 = Disable RISC code load 157 * BIT 5 = Disable Serdes 158 * BIT 6 = 159 * BIT 7 = 160 * 161 * BIT 8 = 162 * BIT 9 = 163 * BIT 10 = Enable lip full login 164 * BIT 11 = Enable target reset 165 * BIT 12 = 166 * BIT 13 = 167 * BIT 14 = 168 * BIT 15 = Enable alternate WWN 169 * 170 * BIT 16-31 = 171 */ 172 uint32_t host_p; 173 174 uint8_t alternate_port_name[WWN_SIZE]; 175 uint8_t alternate_node_name[WWN_SIZE]; 176 177 uint8_t boot_port_name[WWN_SIZE]; 178 uint16_t boot_lun_number; 179 uint16_t reserved_8; 180 181 uint8_t alt1_boot_port_name[WWN_SIZE]; 182 uint16_t alt1_boot_lun_number; 183 uint16_t reserved_9; 184 185 uint8_t alt2_boot_port_name[WWN_SIZE]; 186 uint16_t alt2_boot_lun_number; 187 uint16_t reserved_10; 188 189 uint8_t alt3_boot_port_name[WWN_SIZE]; 190 uint16_t alt3_boot_lun_number; 191 uint16_t reserved_11; 192 193 /* 194 * BIT 0 = Selective Login 195 * BIT 1 = Alt-Boot Enable 196 * BIT 2 = Reserved 197 * BIT 3 = Boot Order List 198 * BIT 4 = Reserved 199 * BIT 5 = Selective LUN 200 * BIT 6 = Reserved 201 * BIT 7-31 = 202 */ 203 uint32_t efi_parameters; 204 205 uint8_t reset_delay; 206 uint8_t reserved_12; 207 uint16_t reserved_13; 208 209 uint16_t boot_id_number; 210 uint16_t reserved_14; 211 212 uint16_t max_luns_per_target; 213 uint16_t reserved_15; 214 215 uint16_t port_down_retry_count; 216 uint16_t link_down_timeout; 217 218 /* FCode parameters. */ 219 uint16_t fcode_parameter; 220 221 uint16_t reserved_16[3]; 222 223 /* Offset 352. */ 224 uint8_t prev_drv_ver_major; 225 uint8_t prev_drv_ver_submajob; 226 uint8_t prev_drv_ver_minor; 227 uint8_t prev_drv_ver_subminor; 228 229 uint16_t prev_bios_ver_major; 230 uint16_t prev_bios_ver_minor; 231 232 uint16_t prev_efi_ver_major; 233 uint16_t prev_efi_ver_minor; 234 235 uint16_t prev_fw_ver_major; 236 uint8_t prev_fw_ver_minor; 237 uint8_t prev_fw_ver_subminor; 238 239 uint16_t reserved_17[8]; 240 241 /* Offset 384. */ 242 uint16_t reserved_18[16]; 243 244 /* Offset 416. */ 245 uint16_t reserved_19[16]; 246 247 /* Offset 448. */ 248 uint16_t reserved_20[16]; 249 250 /* Offset 480. */ 251 uint8_t model_name[16]; 252 253 uint16_t reserved_21[2]; 254 255 /* Offset 500. */ 256 /* HW Parameter Block. */ 257 uint16_t pcie_table_sig; 258 uint16_t pcie_table_offset; 259 260 uint16_t subsystem_vendor_id; 261 uint16_t subsystem_device_id; 262 263 uint32_t checksum; 264 }; 265 266 /* 267 * ISP Initialization Control Block. 268 * Little endian except where noted. 269 */ 270 #define ICB_VERSION 1 271 struct init_cb_24xx { 272 uint16_t version; 273 uint16_t reserved_1; 274 275 uint16_t frame_payload_size; 276 uint16_t execution_throttle; 277 uint16_t exchange_count; 278 279 uint16_t hard_address; 280 281 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 282 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 283 284 uint16_t response_q_inpointer; 285 uint16_t request_q_outpointer; 286 287 uint16_t login_retry_count; 288 289 uint16_t prio_request_q_outpointer; 290 291 uint16_t response_q_length; 292 uint16_t request_q_length; 293 294 uint16_t link_down_on_nos; /* Milliseconds. */ 295 296 uint16_t prio_request_q_length; 297 298 uint32_t request_q_address[2]; 299 uint32_t response_q_address[2]; 300 uint32_t prio_request_q_address[2]; 301 302 uint16_t msix; 303 uint16_t msix_atio; 304 uint8_t reserved_2[4]; 305 306 uint16_t atio_q_inpointer; 307 uint16_t atio_q_length; 308 uint32_t atio_q_address[2]; 309 310 uint16_t interrupt_delay_timer; /* 100us increments. */ 311 uint16_t login_timeout; 312 313 /* 314 * BIT 0 = Enable Hard Loop Id 315 * BIT 1 = Enable Fairness 316 * BIT 2 = Enable Full-Duplex 317 * BIT 3 = Reserved 318 * BIT 4 = Enable Target Mode 319 * BIT 5 = Disable Initiator Mode 320 * BIT 6 = Acquire FA-WWN 321 * BIT 7 = Enable D-port Diagnostics 322 * 323 * BIT 8 = Reserved 324 * BIT 9 = Non Participating LIP 325 * BIT 10 = Descending Loop ID Search 326 * BIT 11 = Acquire Loop ID in LIPA 327 * BIT 12 = Reserved 328 * BIT 13 = Full Login after LIP 329 * BIT 14 = Node Name Option 330 * BIT 15-31 = Reserved 331 */ 332 uint32_t firmware_options_1; 333 334 /* 335 * BIT 0 = Operation Mode bit 0 336 * BIT 1 = Operation Mode bit 1 337 * BIT 2 = Operation Mode bit 2 338 * BIT 3 = Operation Mode bit 3 339 * BIT 4 = Connection Options bit 0 340 * BIT 5 = Connection Options bit 1 341 * BIT 6 = Connection Options bit 2 342 * BIT 7 = Enable Non part on LIHA failure 343 * 344 * BIT 8 = Enable Class 2 345 * BIT 9 = Enable ACK0 346 * BIT 10 = Reserved 347 * BIT 11 = Enable FC-SP Security 348 * BIT 12 = FC Tape Enable 349 * BIT 13 = Reserved 350 * BIT 14 = Enable Target PRLI Control 351 * BIT 15-31 = Reserved 352 */ 353 uint32_t firmware_options_2; 354 355 /* 356 * BIT 0 = Reserved 357 * BIT 1 = Soft ID only 358 * BIT 2 = Reserved 359 * BIT 3 = Reserved 360 * BIT 4 = FCP RSP Payload bit 0 361 * BIT 5 = FCP RSP Payload bit 1 362 * BIT 6 = Enable Receive Out-of-Order data frame handling 363 * BIT 7 = Disable Automatic PLOGI on Local Loop 364 * 365 * BIT 8 = Reserved 366 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 367 * BIT 10 = Reserved 368 * BIT 11 = Reserved 369 * BIT 12 = Reserved 370 * BIT 13 = Data Rate bit 0 371 * BIT 14 = Data Rate bit 1 372 * BIT 15 = Data Rate bit 2 373 * BIT 16 = Enable 75 ohm Termination Select 374 * BIT 17-28 = Reserved 375 * BIT 29 = Enable response queue 0 in index shadowing 376 * BIT 30 = Enable request queue 0 out index shadowing 377 * BIT 31 = Reserved 378 */ 379 uint32_t firmware_options_3; 380 uint16_t qos; 381 uint16_t rid; 382 uint8_t reserved_3[20]; 383 }; 384 385 /* 386 * ISP queue - command entry structure definition. 387 */ 388 #define COMMAND_BIDIRECTIONAL 0x75 389 struct cmd_bidir { 390 uint8_t entry_type; /* Entry type. */ 391 uint8_t entry_count; /* Entry count. */ 392 uint8_t sys_define; /* System defined */ 393 uint8_t entry_status; /* Entry status. */ 394 395 uint32_t handle; /* System handle. */ 396 397 uint16_t nport_handle; /* N_PORT hanlde. */ 398 399 uint16_t timeout; /* Commnad timeout. */ 400 401 uint16_t wr_dseg_count; /* Write Data segment count. */ 402 uint16_t rd_dseg_count; /* Read Data segment count. */ 403 404 struct scsi_lun lun; /* FCP LUN (BE). */ 405 406 uint16_t control_flags; /* Control flags. */ 407 #define BD_WRAP_BACK BIT_3 408 #define BD_READ_DATA BIT_1 409 #define BD_WRITE_DATA BIT_0 410 411 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 412 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 413 414 uint16_t reserved[2]; /* Reserved */ 415 416 uint32_t rd_byte_count; /* Total Byte count Read. */ 417 uint32_t wr_byte_count; /* Total Byte count write. */ 418 419 uint8_t port_id[3]; /* PortID of destination port.*/ 420 uint8_t vp_index; 421 422 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ 423 uint16_t fcp_data_dseg_len; /* Data segment length. */ 424 }; 425 426 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */ 427 struct cmd_type_6 { 428 uint8_t entry_type; /* Entry type. */ 429 uint8_t entry_count; /* Entry count. */ 430 uint8_t sys_define; /* System defined. */ 431 uint8_t entry_status; /* Entry Status. */ 432 433 uint32_t handle; /* System handle. */ 434 435 uint16_t nport_handle; /* N_PORT handle. */ 436 uint16_t timeout; /* Command timeout. */ 437 438 uint16_t dseg_count; /* Data segment count. */ 439 440 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */ 441 442 struct scsi_lun lun; /* FCP LUN (BE). */ 443 444 uint16_t control_flags; /* Control flags. */ 445 #define CF_DIF_SEG_DESCR_ENABLE BIT_3 446 #define CF_DATA_SEG_DESCR_ENABLE BIT_2 447 #define CF_READ_DATA BIT_1 448 #define CF_WRITE_DATA BIT_0 449 450 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 451 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 452 453 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 454 455 uint32_t byte_count; /* Total byte count. */ 456 457 uint8_t port_id[3]; /* PortID of destination port. */ 458 uint8_t vp_index; 459 460 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ 461 uint32_t fcp_data_dseg_len; /* Data segment length. */ 462 }; 463 464 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */ 465 struct cmd_type_7 { 466 uint8_t entry_type; /* Entry type. */ 467 uint8_t entry_count; /* Entry count. */ 468 uint8_t sys_define; /* System defined. */ 469 uint8_t entry_status; /* Entry Status. */ 470 471 uint32_t handle; /* System handle. */ 472 473 uint16_t nport_handle; /* N_PORT handle. */ 474 uint16_t timeout; /* Command timeout. */ 475 #define FW_MAX_TIMEOUT 0x1999 476 477 uint16_t dseg_count; /* Data segment count. */ 478 uint16_t reserved_1; 479 480 struct scsi_lun lun; /* FCP LUN (BE). */ 481 482 uint16_t task_mgmt_flags; /* Task management flags. */ 483 #define TMF_CLEAR_ACA BIT_14 484 #define TMF_TARGET_RESET BIT_13 485 #define TMF_LUN_RESET BIT_12 486 #define TMF_CLEAR_TASK_SET BIT_10 487 #define TMF_ABORT_TASK_SET BIT_9 488 #define TMF_DSD_LIST_ENABLE BIT_2 489 #define TMF_READ_DATA BIT_1 490 #define TMF_WRITE_DATA BIT_0 491 492 uint8_t task; 493 #define TSK_SIMPLE 0 494 #define TSK_HEAD_OF_QUEUE 1 495 #define TSK_ORDERED 2 496 #define TSK_ACA 4 497 #define TSK_UNTAGGED 5 498 499 uint8_t crn; 500 501 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ 502 uint32_t byte_count; /* Total byte count. */ 503 504 uint8_t port_id[3]; /* PortID of destination port. */ 505 uint8_t vp_index; 506 507 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 508 uint32_t dseg_0_len; /* Data segment 0 length. */ 509 }; 510 511 #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6) 512 * (T10-DIF) */ 513 struct cmd_type_crc_2 { 514 uint8_t entry_type; /* Entry type. */ 515 uint8_t entry_count; /* Entry count. */ 516 uint8_t sys_define; /* System defined. */ 517 uint8_t entry_status; /* Entry Status. */ 518 519 uint32_t handle; /* System handle. */ 520 521 uint16_t nport_handle; /* N_PORT handle. */ 522 uint16_t timeout; /* Command timeout. */ 523 524 uint16_t dseg_count; /* Data segment count. */ 525 526 uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */ 527 528 struct scsi_lun lun; /* FCP LUN (BE). */ 529 530 uint16_t control_flags; /* Control flags. */ 531 532 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 533 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 534 535 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 536 537 uint32_t byte_count; /* Total byte count. */ 538 539 uint8_t port_id[3]; /* PortID of destination port. */ 540 uint8_t vp_index; 541 542 uint32_t crc_context_address[2]; /* Data segment address. */ 543 uint16_t crc_context_len; /* Data segment length. */ 544 uint16_t reserved_1; /* MUST be set to 0. */ 545 }; 546 547 548 /* 549 * ISP queue - status entry structure definition. 550 */ 551 #define STATUS_TYPE 0x03 /* Status entry. */ 552 struct sts_entry_24xx { 553 uint8_t entry_type; /* Entry type. */ 554 uint8_t entry_count; /* Entry count. */ 555 uint8_t sys_define; /* System defined. */ 556 uint8_t entry_status; /* Entry Status. */ 557 558 uint32_t handle; /* System handle. */ 559 560 uint16_t comp_status; /* Completion status. */ 561 uint16_t ox_id; /* OX_ID used by the firmware. */ 562 563 uint32_t residual_len; /* FW calc residual transfer length. */ 564 565 uint16_t reserved_1; 566 uint16_t state_flags; /* State flags. */ 567 #define SF_TRANSFERRED_DATA BIT_11 568 #define SF_FCP_RSP_DMA BIT_0 569 570 uint16_t retry_delay; 571 uint16_t scsi_status; /* SCSI status. */ 572 #define SS_CONFIRMATION_REQ BIT_12 573 574 uint32_t rsp_residual_count; /* FCP RSP residual count. */ 575 576 uint32_t sense_len; /* FCP SENSE length. */ 577 uint32_t rsp_data_len; /* FCP response data length. */ 578 uint8_t data[28]; /* FCP response/sense information. */ 579 /* 580 * If DIF Error is set in comp_status, these additional fields are 581 * defined: 582 * 583 * !!! NOTE: Firmware sends expected/actual DIF data in big endian 584 * format; but all of the "data" field gets swab32-d in the beginning 585 * of qla2x00_status_entry(). 586 * 587 * &data[10] : uint8_t report_runt_bg[2]; - computed guard 588 * &data[12] : uint8_t actual_dif[8]; - DIF Data received 589 * &data[20] : uint8_t expected_dif[8]; - DIF Data computed 590 */ 591 }; 592 593 594 /* 595 * Status entry completion status 596 */ 597 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */ 598 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */ 599 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */ 600 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */ 601 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */ 602 603 /* 604 * ISP queue - marker entry structure definition. 605 */ 606 #define MARKER_TYPE 0x04 /* Marker entry. */ 607 struct mrk_entry_24xx { 608 uint8_t entry_type; /* Entry type. */ 609 uint8_t entry_count; /* Entry count. */ 610 uint8_t handle_count; /* Handle count. */ 611 uint8_t entry_status; /* Entry Status. */ 612 613 uint32_t handle; /* System handle. */ 614 615 uint16_t nport_handle; /* N_PORT handle. */ 616 617 uint8_t modifier; /* Modifier (7-0). */ 618 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 619 #define MK_SYNC_ID 1 /* Synchronize ID */ 620 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 621 uint8_t reserved_1; 622 623 uint8_t reserved_2; 624 uint8_t vp_index; 625 626 uint16_t reserved_3; 627 628 uint8_t lun[8]; /* FCP LUN (BE). */ 629 uint8_t reserved_4[40]; 630 }; 631 632 /* 633 * ISP queue - CT Pass-Through entry structure definition. 634 */ 635 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */ 636 struct ct_entry_24xx { 637 uint8_t entry_type; /* Entry type. */ 638 uint8_t entry_count; /* Entry count. */ 639 uint8_t sys_define; /* System Defined. */ 640 uint8_t entry_status; /* Entry Status. */ 641 642 uint32_t handle; /* System handle. */ 643 644 uint16_t comp_status; /* Completion status. */ 645 646 uint16_t nport_handle; /* N_PORT handle. */ 647 648 uint16_t cmd_dsd_count; 649 650 uint8_t vp_index; 651 uint8_t reserved_1; 652 653 uint16_t timeout; /* Command timeout. */ 654 uint16_t reserved_2; 655 656 uint16_t rsp_dsd_count; 657 658 uint8_t reserved_3[10]; 659 660 uint32_t rsp_byte_count; 661 uint32_t cmd_byte_count; 662 663 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 664 uint32_t dseg_0_len; /* Data segment 0 length. */ 665 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 666 uint32_t dseg_1_len; /* Data segment 1 length. */ 667 }; 668 669 /* 670 * ISP queue - ELS Pass-Through entry structure definition. 671 */ 672 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */ 673 struct els_entry_24xx { 674 uint8_t entry_type; /* Entry type. */ 675 uint8_t entry_count; /* Entry count. */ 676 uint8_t sys_define; /* System Defined. */ 677 uint8_t entry_status; /* Entry Status. */ 678 679 uint32_t handle; /* System handle. */ 680 681 uint16_t reserved_1; 682 683 uint16_t nport_handle; /* N_PORT handle. */ 684 685 uint16_t tx_dsd_count; 686 687 uint8_t vp_index; 688 uint8_t sof_type; 689 #define EST_SOFI3 (1 << 4) 690 #define EST_SOFI2 (3 << 4) 691 692 uint32_t rx_xchg_address; /* Receive exchange address. */ 693 uint16_t rx_dsd_count; 694 695 uint8_t opcode; 696 uint8_t reserved_2; 697 698 uint8_t port_id[3]; 699 uint8_t reserved_3; 700 701 uint16_t reserved_4; 702 703 uint16_t control_flags; /* Control flags. */ 704 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13) 705 #define EPD_ELS_COMMAND (0 << 13) 706 #define EPD_ELS_ACC (1 << 13) 707 #define EPD_ELS_RJT (2 << 13) 708 #define EPD_RX_XCHG (3 << 13) 709 #define ECF_CLR_PASSTHRU_PEND BIT_12 710 #define ECF_INCL_FRAME_HDR BIT_11 711 712 uint32_t rx_byte_count; 713 uint32_t tx_byte_count; 714 715 uint32_t tx_address[2]; /* Data segment 0 address. */ 716 uint32_t tx_len; /* Data segment 0 length. */ 717 uint32_t rx_address[2]; /* Data segment 1 address. */ 718 uint32_t rx_len; /* Data segment 1 length. */ 719 }; 720 721 struct els_sts_entry_24xx { 722 uint8_t entry_type; /* Entry type. */ 723 uint8_t entry_count; /* Entry count. */ 724 uint8_t sys_define; /* System Defined. */ 725 uint8_t entry_status; /* Entry Status. */ 726 727 uint32_t handle; /* System handle. */ 728 729 uint16_t comp_status; 730 731 uint16_t nport_handle; /* N_PORT handle. */ 732 733 uint16_t reserved_1; 734 735 uint8_t vp_index; 736 uint8_t sof_type; 737 738 uint32_t rx_xchg_address; /* Receive exchange address. */ 739 uint16_t reserved_2; 740 741 uint8_t opcode; 742 uint8_t reserved_3; 743 744 uint8_t port_id[3]; 745 uint8_t reserved_4; 746 747 uint16_t reserved_5; 748 749 uint16_t control_flags; /* Control flags. */ 750 uint32_t total_byte_count; 751 uint32_t error_subcode_1; 752 uint32_t error_subcode_2; 753 }; 754 /* 755 * ISP queue - Mailbox Command entry structure definition. 756 */ 757 #define MBX_IOCB_TYPE 0x39 758 struct mbx_entry_24xx { 759 uint8_t entry_type; /* Entry type. */ 760 uint8_t entry_count; /* Entry count. */ 761 uint8_t handle_count; /* Handle count. */ 762 uint8_t entry_status; /* Entry Status. */ 763 764 uint32_t handle; /* System handle. */ 765 766 uint16_t mbx[28]; 767 }; 768 769 770 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */ 771 struct logio_entry_24xx { 772 uint8_t entry_type; /* Entry type. */ 773 uint8_t entry_count; /* Entry count. */ 774 uint8_t sys_define; /* System defined. */ 775 uint8_t entry_status; /* Entry Status. */ 776 777 uint32_t handle; /* System handle. */ 778 779 uint16_t comp_status; /* Completion status. */ 780 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */ 781 782 uint16_t nport_handle; /* N_PORT handle. */ 783 784 uint16_t control_flags; /* Control flags. */ 785 /* Modifiers. */ 786 #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ 787 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ 788 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ 789 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ 790 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */ 791 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */ 792 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */ 793 #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */ 794 #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */ 795 #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */ 796 /* Commands. */ 797 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */ 798 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */ 799 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */ 800 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */ 801 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */ 802 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */ 803 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */ 804 805 uint8_t vp_index; 806 uint8_t reserved_1; 807 808 uint8_t port_id[3]; /* PortID of destination port. */ 809 810 uint8_t rsp_size; /* Response size in 32bit words. */ 811 812 uint32_t io_parameter[11]; /* General I/O parameters. */ 813 #define LSC_SCODE_NOLINK 0x01 814 #define LSC_SCODE_NOIOCB 0x02 815 #define LSC_SCODE_NOXCB 0x03 816 #define LSC_SCODE_CMD_FAILED 0x04 817 #define LSC_SCODE_NOFABRIC 0x05 818 #define LSC_SCODE_FW_NOT_READY 0x07 819 #define LSC_SCODE_NOT_LOGGED_IN 0x09 820 #define LSC_SCODE_NOPCB 0x0A 821 822 #define LSC_SCODE_ELS_REJECT 0x18 823 #define LSC_SCODE_CMD_PARAM_ERR 0x19 824 #define LSC_SCODE_PORTID_USED 0x1A 825 #define LSC_SCODE_NPORT_USED 0x1B 826 #define LSC_SCODE_NONPORT 0x1C 827 #define LSC_SCODE_LOGGED_IN 0x1D 828 #define LSC_SCODE_NOFLOGI_ACC 0x1F 829 }; 830 831 #define TSK_MGMT_IOCB_TYPE 0x14 832 struct tsk_mgmt_entry { 833 uint8_t entry_type; /* Entry type. */ 834 uint8_t entry_count; /* Entry count. */ 835 uint8_t handle_count; /* Handle count. */ 836 uint8_t entry_status; /* Entry Status. */ 837 838 uint32_t handle; /* System handle. */ 839 840 uint16_t nport_handle; /* N_PORT handle. */ 841 842 uint16_t reserved_1; 843 844 uint16_t delay; /* Activity delay in seconds. */ 845 846 uint16_t timeout; /* Command timeout. */ 847 848 struct scsi_lun lun; /* FCP LUN (BE). */ 849 850 uint32_t control_flags; /* Control Flags. */ 851 #define TCF_NOTMCMD_TO_TARGET BIT_31 852 #define TCF_LUN_RESET BIT_4 853 #define TCF_ABORT_TASK_SET BIT_3 854 #define TCF_CLEAR_TASK_SET BIT_2 855 #define TCF_TARGET_RESET BIT_1 856 #define TCF_CLEAR_ACA BIT_0 857 858 uint8_t reserved_2[20]; 859 860 uint8_t port_id[3]; /* PortID of destination port. */ 861 uint8_t vp_index; 862 863 uint8_t reserved_3[12]; 864 }; 865 866 #define ABORT_IOCB_TYPE 0x33 867 struct abort_entry_24xx { 868 uint8_t entry_type; /* Entry type. */ 869 uint8_t entry_count; /* Entry count. */ 870 uint8_t handle_count; /* Handle count. */ 871 uint8_t entry_status; /* Entry Status. */ 872 873 uint32_t handle; /* System handle. */ 874 875 uint16_t nport_handle; /* N_PORT handle. */ 876 /* or Completion status. */ 877 878 uint16_t options; /* Options. */ 879 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ 880 881 uint32_t handle_to_abort; /* System handle to abort. */ 882 883 uint16_t req_que_no; 884 uint8_t reserved_1[30]; 885 886 uint8_t port_id[3]; /* PortID of destination port. */ 887 uint8_t vp_index; 888 889 uint8_t reserved_2[12]; 890 }; 891 892 /* 893 * ISP I/O Register Set structure definitions. 894 */ 895 struct device_reg_24xx { 896 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */ 897 #define FARX_DATA_FLAG BIT_31 898 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 899 #define FARX_ACCESS_FLASH_DATA 0x7FF00000 900 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000 901 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000 902 903 #define FA_NVRAM_FUNC0_ADDR 0x80 904 #define FA_NVRAM_FUNC1_ADDR 0x180 905 906 #define FA_NVRAM_VPD_SIZE 0x200 907 #define FA_NVRAM_VPD0_ADDR 0x00 908 #define FA_NVRAM_VPD1_ADDR 0x100 909 910 #define FA_BOOT_CODE_ADDR 0x00000 911 /* 912 * RISC code begins at offset 512KB 913 * within flash. Consisting of two 914 * contiguous RISC code segments. 915 */ 916 #define FA_RISC_CODE_ADDR 0x20000 917 #define FA_RISC_CODE_SEGMENTS 2 918 919 #define FA_FLASH_DESCR_ADDR_24 0x11000 920 #define FA_FLASH_LAYOUT_ADDR_24 0x11400 921 #define FA_NPIV_CONF0_ADDR_24 0x16000 922 #define FA_NPIV_CONF1_ADDR_24 0x17000 923 924 #define FA_FW_AREA_ADDR 0x40000 925 #define FA_VPD_NVRAM_ADDR 0x48000 926 #define FA_FEATURE_ADDR 0x4C000 927 #define FA_FLASH_DESCR_ADDR 0x50000 928 #define FA_FLASH_LAYOUT_ADDR 0x50400 929 #define FA_HW_EVENT0_ADDR 0x54000 930 #define FA_HW_EVENT1_ADDR 0x54400 931 #define FA_HW_EVENT_SIZE 0x200 932 #define FA_HW_EVENT_ENTRY_SIZE 4 933 #define FA_NPIV_CONF0_ADDR 0x5C000 934 #define FA_NPIV_CONF1_ADDR 0x5D000 935 #define FA_FCP_PRIO0_ADDR 0x10000 936 #define FA_FCP_PRIO1_ADDR 0x12000 937 938 /* 939 * Flash Error Log Event Codes. 940 */ 941 #define HW_EVENT_RESET_ERR 0xF00B 942 #define HW_EVENT_ISP_ERR 0xF020 943 #define HW_EVENT_PARITY_ERR 0xF022 944 #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023 945 #define HW_EVENT_FLASH_FW_ERR 0xF024 946 947 uint32_t flash_data; /* Flash/NVRAM BIOS data. */ 948 949 uint32_t ctrl_status; /* Control/Status. */ 950 #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */ 951 #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */ 952 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */ 953 #define CSRX_FUNCTION BIT_15 /* Function number. */ 954 /* PCI-X Bus Mode. */ 955 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8) 956 #define PBM_PCI_33MHZ (0 << 8) 957 #define PBM_PCIX_M1_66MHZ (1 << 8) 958 #define PBM_PCIX_M1_100MHZ (2 << 8) 959 #define PBM_PCIX_M1_133MHZ (3 << 8) 960 #define PBM_PCIX_M2_66MHZ (5 << 8) 961 #define PBM_PCIX_M2_100MHZ (6 << 8) 962 #define PBM_PCIX_M2_133MHZ (7 << 8) 963 #define PBM_PCI_66MHZ (8 << 8) 964 /* Max Write Burst byte count. */ 965 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4) 966 #define MWB_512_BYTES (0 << 4) 967 #define MWB_1024_BYTES (1 << 4) 968 #define MWB_2048_BYTES (2 << 4) 969 #define MWB_4096_BYTES (3 << 4) 970 971 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */ 972 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */ 973 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ 974 975 uint32_t ictrl; /* Interrupt control. */ 976 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */ 977 978 uint32_t istatus; /* Interrupt status. */ 979 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */ 980 981 uint32_t unused_1[2]; /* Gap. */ 982 983 /* Request Queue. */ 984 uint32_t req_q_in; /* In-Pointer. */ 985 uint32_t req_q_out; /* Out-Pointer. */ 986 /* Response Queue. */ 987 uint32_t rsp_q_in; /* In-Pointer. */ 988 uint32_t rsp_q_out; /* Out-Pointer. */ 989 /* Priority Request Queue. */ 990 uint32_t preq_q_in; /* In-Pointer. */ 991 uint32_t preq_q_out; /* Out-Pointer. */ 992 993 uint32_t unused_2[2]; /* Gap. */ 994 995 /* ATIO Queue. */ 996 uint32_t atio_q_in; /* In-Pointer. */ 997 uint32_t atio_q_out; /* Out-Pointer. */ 998 999 uint32_t host_status; 1000 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ 1001 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ 1002 1003 uint32_t hccr; /* Host command & control register. */ 1004 /* HCCR statuses. */ 1005 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ 1006 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 1007 /* HCCR commands. */ 1008 /* NOOP. */ 1009 #define HCCRX_NOOP 0x00000000 1010 /* Set RISC Reset. */ 1011 #define HCCRX_SET_RISC_RESET 0x10000000 1012 /* Clear RISC Reset. */ 1013 #define HCCRX_CLR_RISC_RESET 0x20000000 1014 /* Set RISC Pause. */ 1015 #define HCCRX_SET_RISC_PAUSE 0x30000000 1016 /* Releases RISC Pause. */ 1017 #define HCCRX_REL_RISC_PAUSE 0x40000000 1018 /* Set HOST to RISC interrupt. */ 1019 #define HCCRX_SET_HOST_INT 0x50000000 1020 /* Clear HOST to RISC interrupt. */ 1021 #define HCCRX_CLR_HOST_INT 0x60000000 1022 /* Clear RISC to PCI interrupt. */ 1023 #define HCCRX_CLR_RISC_INT 0xA0000000 1024 1025 uint32_t gpiod; /* GPIO Data register. */ 1026 1027 /* LED update mask. */ 1028 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) 1029 /* Data update mask. */ 1030 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) 1031 /* Data update mask. */ 1032 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 1033 /* LED control mask. */ 1034 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) 1035 /* LED bit values. Color names as 1036 * referenced in fw spec. 1037 */ 1038 #define GPDX_LED_YELLOW_ON BIT_2 1039 #define GPDX_LED_GREEN_ON BIT_3 1040 #define GPDX_LED_AMBER_ON BIT_4 1041 /* Data in/out. */ 1042 #define GPDX_DATA_INOUT (BIT_1|BIT_0) 1043 1044 uint32_t gpioe; /* GPIO Enable register. */ 1045 /* Enable update mask. */ 1046 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) 1047 /* Enable update mask. */ 1048 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 1049 /* Enable. */ 1050 #define GPEX_ENABLE (BIT_1|BIT_0) 1051 1052 uint32_t iobase_addr; /* I/O Bus Base Address register. */ 1053 1054 uint32_t unused_3[10]; /* Gap. */ 1055 1056 uint16_t mailbox0; 1057 uint16_t mailbox1; 1058 uint16_t mailbox2; 1059 uint16_t mailbox3; 1060 uint16_t mailbox4; 1061 uint16_t mailbox5; 1062 uint16_t mailbox6; 1063 uint16_t mailbox7; 1064 uint16_t mailbox8; 1065 uint16_t mailbox9; 1066 uint16_t mailbox10; 1067 uint16_t mailbox11; 1068 uint16_t mailbox12; 1069 uint16_t mailbox13; 1070 uint16_t mailbox14; 1071 uint16_t mailbox15; 1072 uint16_t mailbox16; 1073 uint16_t mailbox17; 1074 uint16_t mailbox18; 1075 uint16_t mailbox19; 1076 uint16_t mailbox20; 1077 uint16_t mailbox21; 1078 uint16_t mailbox22; 1079 uint16_t mailbox23; 1080 uint16_t mailbox24; 1081 uint16_t mailbox25; 1082 uint16_t mailbox26; 1083 uint16_t mailbox27; 1084 uint16_t mailbox28; 1085 uint16_t mailbox29; 1086 uint16_t mailbox30; 1087 uint16_t mailbox31; 1088 1089 uint32_t iobase_window; 1090 uint32_t iobase_c4; 1091 uint32_t iobase_c8; 1092 uint32_t unused_4_1[6]; /* Gap. */ 1093 uint32_t iobase_q; 1094 uint32_t unused_5[2]; /* Gap. */ 1095 uint32_t iobase_select; 1096 uint32_t unused_6[2]; /* Gap. */ 1097 uint32_t iobase_sdata; 1098 }; 1099 /* RISC-RISC semaphore register PCI offet */ 1100 #define RISC_REGISTER_BASE_OFFSET 0x7010 1101 #define RISC_REGISTER_WINDOW_OFFET 0x6 1102 1103 /* RISC-RISC semaphore/flag register (risc address 0x7016) */ 1104 1105 #define RISC_SEMAPHORE 0x1UL 1106 #define RISC_SEMAPHORE_WE (RISC_SEMAPHORE << 16) 1107 #define RISC_SEMAPHORE_CLR (RISC_SEMAPHORE_WE | 0x0UL) 1108 #define RISC_SEMAPHORE_SET (RISC_SEMAPHORE_WE | RISC_SEMAPHORE) 1109 1110 #define RISC_SEMAPHORE_FORCE 0x8000UL 1111 #define RISC_SEMAPHORE_FORCE_WE (RISC_SEMAPHORE_FORCE << 16) 1112 #define RISC_SEMAPHORE_FORCE_CLR (RISC_SEMAPHORE_FORCE_WE | 0x0UL) 1113 #define RISC_SEMAPHORE_FORCE_SET \ 1114 (RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE) 1115 1116 /* RISC semaphore timeouts (ms) */ 1117 #define TIMEOUT_SEMAPHORE 2500 1118 #define TIMEOUT_SEMAPHORE_FORCE 2000 1119 #define TIMEOUT_TOTAL_ELAPSED 4500 1120 1121 /* Trace Control *************************************************************/ 1122 1123 #define TC_AEN_DISABLE 0 1124 1125 #define TC_EFT_ENABLE 4 1126 #define TC_EFT_DISABLE 5 1127 1128 #define TC_FCE_ENABLE 8 1129 #define TC_FCE_OPTIONS 0 1130 #define TC_FCE_DEFAULT_RX_SIZE 2112 1131 #define TC_FCE_DEFAULT_TX_SIZE 2112 1132 #define TC_FCE_DISABLE 9 1133 #define TC_FCE_DISABLE_TRACE BIT_0 1134 1135 /* MID Support ***************************************************************/ 1136 1137 #define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */ 1138 #define MAX_MULTI_ID_FABRIC 256 /* ... */ 1139 1140 struct mid_conf_entry_24xx { 1141 uint16_t reserved_1; 1142 1143 /* 1144 * BIT 0 = Enable Hard Loop Id 1145 * BIT 1 = Acquire Loop ID in LIPA 1146 * BIT 2 = ID not Acquired 1147 * BIT 3 = Enable VP 1148 * BIT 4 = Enable Initiator Mode 1149 * BIT 5 = Disable Target Mode 1150 * BIT 6-7 = Reserved 1151 */ 1152 uint8_t options; 1153 1154 uint8_t hard_address; 1155 1156 uint8_t port_name[WWN_SIZE]; 1157 uint8_t node_name[WWN_SIZE]; 1158 }; 1159 1160 struct mid_init_cb_24xx { 1161 struct init_cb_24xx init_cb; 1162 1163 uint16_t count; 1164 uint16_t options; 1165 1166 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 1167 }; 1168 1169 1170 struct mid_db_entry_24xx { 1171 uint16_t status; 1172 #define MDBS_NON_PARTIC BIT_3 1173 #define MDBS_ID_ACQUIRED BIT_1 1174 #define MDBS_ENABLED BIT_0 1175 1176 uint8_t options; 1177 uint8_t hard_address; 1178 1179 uint8_t port_name[WWN_SIZE]; 1180 uint8_t node_name[WWN_SIZE]; 1181 1182 uint8_t port_id[3]; 1183 uint8_t reserved_1; 1184 }; 1185 1186 /* 1187 * Virtual Port Control IOCB 1188 */ 1189 #define VP_CTRL_IOCB_TYPE 0x30 /* Virtual Port Control entry. */ 1190 struct vp_ctrl_entry_24xx { 1191 uint8_t entry_type; /* Entry type. */ 1192 uint8_t entry_count; /* Entry count. */ 1193 uint8_t sys_define; /* System defined. */ 1194 uint8_t entry_status; /* Entry Status. */ 1195 1196 uint32_t handle; /* System handle. */ 1197 1198 uint16_t vp_idx_failed; 1199 1200 uint16_t comp_status; /* Completion status. */ 1201 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */ 1202 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */ 1203 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1204 1205 uint16_t command; 1206 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */ 1207 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */ 1208 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */ 1209 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */ 1210 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */ 1211 1212 uint16_t vp_count; 1213 1214 uint8_t vp_idx_map[16]; 1215 uint16_t flags; 1216 uint16_t id; 1217 uint16_t reserved_4; 1218 uint16_t hopct; 1219 uint8_t reserved_5[24]; 1220 }; 1221 1222 /* 1223 * Modify Virtual Port Configuration IOCB 1224 */ 1225 #define VP_CONFIG_IOCB_TYPE 0x31 /* Virtual Port Config entry. */ 1226 struct vp_config_entry_24xx { 1227 uint8_t entry_type; /* Entry type. */ 1228 uint8_t entry_count; /* Entry count. */ 1229 uint8_t handle_count; 1230 uint8_t entry_status; /* Entry Status. */ 1231 1232 uint32_t handle; /* System handle. */ 1233 1234 uint16_t flags; 1235 #define CS_VF_BIND_VPORTS_TO_VF BIT_0 1236 #define CS_VF_SET_QOS_OF_VPORTS BIT_1 1237 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2 1238 1239 uint16_t comp_status; /* Completion status. */ 1240 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */ 1241 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */ 1242 #define CS_VCT_ERROR 0x03 /* Unknown error. */ 1243 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */ 1244 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1245 1246 uint8_t command; 1247 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */ 1248 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */ 1249 1250 uint8_t vp_count; 1251 1252 uint8_t vp_index1; 1253 uint8_t vp_index2; 1254 1255 uint8_t options_idx1; 1256 uint8_t hard_address_idx1; 1257 uint16_t reserved_vp1; 1258 uint8_t port_name_idx1[WWN_SIZE]; 1259 uint8_t node_name_idx1[WWN_SIZE]; 1260 1261 uint8_t options_idx2; 1262 uint8_t hard_address_idx2; 1263 uint16_t reserved_vp2; 1264 uint8_t port_name_idx2[WWN_SIZE]; 1265 uint8_t node_name_idx2[WWN_SIZE]; 1266 uint16_t id; 1267 uint16_t reserved_4; 1268 uint16_t hopct; 1269 uint8_t reserved_5[2]; 1270 }; 1271 1272 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */ 1273 struct vp_rpt_id_entry_24xx { 1274 uint8_t entry_type; /* Entry type. */ 1275 uint8_t entry_count; /* Entry count. */ 1276 uint8_t sys_define; /* System defined. */ 1277 uint8_t entry_status; /* Entry Status. */ 1278 1279 uint32_t handle; /* System handle. */ 1280 1281 uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */ 1282 /* Format 1 -- | VP count |. */ 1283 uint16_t vp_idx; /* Format 0 -- Reserved. */ 1284 /* Format 1 -- VP status and index. */ 1285 1286 uint8_t port_id[3]; 1287 uint8_t format; 1288 1289 uint8_t vp_idx_map[16]; 1290 1291 uint8_t reserved_4[28]; 1292 uint16_t bbcr; 1293 uint8_t reserved_5[6]; 1294 }; 1295 1296 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */ 1297 struct vf_evfp_entry_24xx { 1298 uint8_t entry_type; /* Entry type. */ 1299 uint8_t entry_count; /* Entry count. */ 1300 uint8_t sys_define; /* System defined. */ 1301 uint8_t entry_status; /* Entry Status. */ 1302 1303 uint32_t handle; /* System handle. */ 1304 uint16_t comp_status; /* Completion status. */ 1305 uint16_t timeout; /* timeout */ 1306 uint16_t adim_tagging_mode; 1307 1308 uint16_t vfport_id; 1309 uint32_t exch_addr; 1310 1311 uint16_t nport_handle; /* N_PORT handle. */ 1312 uint16_t control_flags; 1313 uint32_t io_parameter_0; 1314 uint32_t io_parameter_1; 1315 uint32_t tx_address[2]; /* Data segment 0 address. */ 1316 uint32_t tx_len; /* Data segment 0 length. */ 1317 uint32_t rx_address[2]; /* Data segment 1 address. */ 1318 uint32_t rx_len; /* Data segment 1 length. */ 1319 }; 1320 1321 /* END MID Support ***********************************************************/ 1322 1323 /* Flash Description Table ***************************************************/ 1324 1325 struct qla_fdt_layout { 1326 uint8_t sig[4]; 1327 uint16_t version; 1328 uint16_t len; 1329 uint16_t checksum; 1330 uint8_t unused1[2]; 1331 uint8_t model[16]; 1332 uint16_t man_id; 1333 uint16_t id; 1334 uint8_t flags; 1335 uint8_t erase_cmd; 1336 uint8_t alt_erase_cmd; 1337 uint8_t wrt_enable_cmd; 1338 uint8_t wrt_enable_bits; 1339 uint8_t wrt_sts_reg_cmd; 1340 uint8_t unprotect_sec_cmd; 1341 uint8_t read_man_id_cmd; 1342 uint32_t block_size; 1343 uint32_t alt_block_size; 1344 uint32_t flash_size; 1345 uint32_t wrt_enable_data; 1346 uint8_t read_id_addr_len; 1347 uint8_t wrt_disable_bits; 1348 uint8_t read_dev_id_len; 1349 uint8_t chip_erase_cmd; 1350 uint16_t read_timeout; 1351 uint8_t protect_sec_cmd; 1352 uint8_t unused2[65]; 1353 }; 1354 1355 /* Flash Layout Table ********************************************************/ 1356 1357 struct qla_flt_location { 1358 uint8_t sig[4]; 1359 uint16_t start_lo; 1360 uint16_t start_hi; 1361 uint8_t version; 1362 uint8_t unused[5]; 1363 uint16_t checksum; 1364 }; 1365 1366 struct qla_flt_header { 1367 uint16_t version; 1368 uint16_t length; 1369 uint16_t checksum; 1370 uint16_t unused; 1371 }; 1372 1373 #define FLT_REG_FW 0x01 1374 #define FLT_REG_BOOT_CODE 0x07 1375 #define FLT_REG_VPD_0 0x14 1376 #define FLT_REG_NVRAM_0 0x15 1377 #define FLT_REG_VPD_1 0x16 1378 #define FLT_REG_NVRAM_1 0x17 1379 #define FLT_REG_VPD_2 0xD4 1380 #define FLT_REG_NVRAM_2 0xD5 1381 #define FLT_REG_VPD_3 0xD6 1382 #define FLT_REG_NVRAM_3 0xD7 1383 #define FLT_REG_FDT 0x1a 1384 #define FLT_REG_FLT 0x1c 1385 #define FLT_REG_HW_EVENT_0 0x1d 1386 #define FLT_REG_HW_EVENT_1 0x1f 1387 #define FLT_REG_NPIV_CONF_0 0x29 1388 #define FLT_REG_NPIV_CONF_1 0x2a 1389 #define FLT_REG_GOLD_FW 0x2f 1390 #define FLT_REG_FCP_PRIO_0 0x87 1391 #define FLT_REG_FCP_PRIO_1 0x88 1392 #define FLT_REG_CNA_FW 0x97 1393 #define FLT_REG_BOOT_CODE_8044 0xA2 1394 #define FLT_REG_FCOE_FW 0xA4 1395 #define FLT_REG_FCOE_NVRAM_0 0xAA 1396 #define FLT_REG_FCOE_NVRAM_1 0xAC 1397 1398 /* 27xx */ 1399 #define FLT_REG_IMG_PRI_27XX 0x95 1400 #define FLT_REG_IMG_SEC_27XX 0x96 1401 #define FLT_REG_FW_SEC_27XX 0x02 1402 #define FLT_REG_BOOTLOAD_SEC_27XX 0x9 1403 #define FLT_REG_VPD_SEC_27XX_0 0x50 1404 #define FLT_REG_VPD_SEC_27XX_1 0x52 1405 #define FLT_REG_VPD_SEC_27XX_2 0xD8 1406 #define FLT_REG_VPD_SEC_27XX_3 0xDA 1407 1408 struct qla_flt_region { 1409 uint32_t code; 1410 uint32_t size; 1411 uint32_t start; 1412 uint32_t end; 1413 }; 1414 1415 /* Flash NPIV Configuration Table ********************************************/ 1416 1417 struct qla_npiv_header { 1418 uint8_t sig[2]; 1419 uint16_t version; 1420 uint16_t entries; 1421 uint16_t unused[4]; 1422 uint16_t checksum; 1423 }; 1424 1425 struct qla_npiv_entry { 1426 uint16_t flags; 1427 uint16_t vf_id; 1428 uint8_t q_qos; 1429 uint8_t f_qos; 1430 uint16_t unused1; 1431 uint8_t port_name[WWN_SIZE]; 1432 uint8_t node_name[WWN_SIZE]; 1433 }; 1434 1435 /* 84XX Support **************************************************************/ 1436 1437 #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */ 1438 #define A84_PANIC_RECOVERY 0x1 1439 #define A84_OP_LOGIN_COMPLETE 0x2 1440 #define A84_DIAG_LOGIN_COMPLETE 0x3 1441 #define A84_GOLD_LOGIN_COMPLETE 0x4 1442 1443 #define MBC_ISP84XX_RESET 0x3a /* Reset. */ 1444 1445 #define FSTATE_REMOTE_FC_DOWN BIT_0 1446 #define FSTATE_NSL_LINK_DOWN BIT_1 1447 #define FSTATE_IS_DIAG_FW BIT_2 1448 #define FSTATE_LOGGED_IN BIT_3 1449 #define FSTATE_WAITING_FOR_VERIFY BIT_4 1450 1451 #define VERIFY_CHIP_IOCB_TYPE 0x1B 1452 struct verify_chip_entry_84xx { 1453 uint8_t entry_type; 1454 uint8_t entry_count; 1455 uint8_t sys_defined; 1456 uint8_t entry_status; 1457 1458 uint32_t handle; 1459 1460 uint16_t options; 1461 #define VCO_DONT_UPDATE_FW BIT_0 1462 #define VCO_FORCE_UPDATE BIT_1 1463 #define VCO_DONT_RESET_UPDATE BIT_2 1464 #define VCO_DIAG_FW BIT_3 1465 #define VCO_END_OF_DATA BIT_14 1466 #define VCO_ENABLE_DSD BIT_15 1467 1468 uint16_t reserved_1; 1469 1470 uint16_t data_seg_cnt; 1471 uint16_t reserved_2[3]; 1472 1473 uint32_t fw_ver; 1474 uint32_t exchange_address; 1475 1476 uint32_t reserved_3[3]; 1477 uint32_t fw_size; 1478 uint32_t fw_seq_size; 1479 uint32_t relative_offset; 1480 1481 uint32_t dseg_address[2]; 1482 uint32_t dseg_length; 1483 }; 1484 1485 struct verify_chip_rsp_84xx { 1486 uint8_t entry_type; 1487 uint8_t entry_count; 1488 uint8_t sys_defined; 1489 uint8_t entry_status; 1490 1491 uint32_t handle; 1492 1493 uint16_t comp_status; 1494 #define CS_VCS_CHIP_FAILURE 0x3 1495 #define CS_VCS_BAD_EXCHANGE 0x8 1496 #define CS_VCS_SEQ_COMPLETEi 0x40 1497 1498 uint16_t failure_code; 1499 #define VFC_CHECKSUM_ERROR 0x1 1500 #define VFC_INVALID_LEN 0x2 1501 #define VFC_ALREADY_IN_PROGRESS 0x8 1502 1503 uint16_t reserved_1[4]; 1504 1505 uint32_t fw_ver; 1506 uint32_t exchange_address; 1507 1508 uint32_t reserved_2[6]; 1509 }; 1510 1511 #define ACCESS_CHIP_IOCB_TYPE 0x2B 1512 struct access_chip_84xx { 1513 uint8_t entry_type; 1514 uint8_t entry_count; 1515 uint8_t sys_defined; 1516 uint8_t entry_status; 1517 1518 uint32_t handle; 1519 1520 uint16_t options; 1521 #define ACO_DUMP_MEMORY 0x0 1522 #define ACO_LOAD_MEMORY 0x1 1523 #define ACO_CHANGE_CONFIG_PARAM 0x2 1524 #define ACO_REQUEST_INFO 0x3 1525 1526 uint16_t reserved1; 1527 1528 uint16_t dseg_count; 1529 uint16_t reserved2[3]; 1530 1531 uint32_t parameter1; 1532 uint32_t parameter2; 1533 uint32_t parameter3; 1534 1535 uint32_t reserved3[3]; 1536 uint32_t total_byte_cnt; 1537 uint32_t reserved4; 1538 1539 uint32_t dseg_address[2]; 1540 uint32_t dseg_length; 1541 }; 1542 1543 struct access_chip_rsp_84xx { 1544 uint8_t entry_type; 1545 uint8_t entry_count; 1546 uint8_t sys_defined; 1547 uint8_t entry_status; 1548 1549 uint32_t handle; 1550 1551 uint16_t comp_status; 1552 uint16_t failure_code; 1553 uint32_t residual_count; 1554 1555 uint32_t reserved[12]; 1556 }; 1557 1558 /* 81XX Support **************************************************************/ 1559 1560 #define MBA_DCBX_START 0x8016 1561 #define MBA_DCBX_COMPLETE 0x8030 1562 #define MBA_FCF_CONF_ERR 0x8031 1563 #define MBA_DCBX_PARAM_UPDATE 0x8032 1564 #define MBA_IDC_COMPLETE 0x8100 1565 #define MBA_IDC_NOTIFY 0x8101 1566 #define MBA_IDC_TIME_EXT 0x8102 1567 1568 #define MBC_IDC_ACK 0x101 1569 #define MBC_RESTART_MPI_FW 0x3d 1570 #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */ 1571 #define MBC_GET_XGMAC_STATS 0x7a 1572 #define MBC_GET_DCBX_PARAMS 0x51 1573 1574 /* 1575 * ISP83xx mailbox commands 1576 */ 1577 #define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */ 1578 #define MBC_READ_REMOTE_REG 0x0009 /* Read remote register */ 1579 #define MBC_RESTART_NIC_FIRMWARE 0x003d /* Restart NIC firmware */ 1580 #define MBC_SET_ACCESS_CONTROL 0x003e /* Access control command */ 1581 1582 /* Flash access control option field bit definitions */ 1583 #define FAC_OPT_FORCE_SEMAPHORE BIT_15 1584 #define FAC_OPT_REQUESTOR_ID BIT_14 1585 #define FAC_OPT_CMD_SUBCODE 0xff 1586 1587 /* Flash access control command subcodes */ 1588 #define FAC_OPT_CMD_WRITE_PROTECT 0x00 1589 #define FAC_OPT_CMD_WRITE_ENABLE 0x01 1590 #define FAC_OPT_CMD_ERASE_SECTOR 0x02 1591 #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03 1592 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04 1593 #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05 1594 1595 struct nvram_81xx { 1596 /* NVRAM header. */ 1597 uint8_t id[4]; 1598 uint16_t nvram_version; 1599 uint16_t reserved_0; 1600 1601 /* Firmware Initialization Control Block. */ 1602 uint16_t version; 1603 uint16_t reserved_1; 1604 uint16_t frame_payload_size; 1605 uint16_t execution_throttle; 1606 uint16_t exchange_count; 1607 uint16_t reserved_2; 1608 1609 uint8_t port_name[WWN_SIZE]; 1610 uint8_t node_name[WWN_SIZE]; 1611 1612 uint16_t login_retry_count; 1613 uint16_t reserved_3; 1614 uint16_t interrupt_delay_timer; 1615 uint16_t login_timeout; 1616 1617 uint32_t firmware_options_1; 1618 uint32_t firmware_options_2; 1619 uint32_t firmware_options_3; 1620 1621 uint16_t reserved_4[4]; 1622 1623 /* Offset 64. */ 1624 uint8_t enode_mac[6]; 1625 uint16_t reserved_5[5]; 1626 1627 /* Offset 80. */ 1628 uint16_t reserved_6[24]; 1629 1630 /* Offset 128. */ 1631 uint16_t ex_version; 1632 uint8_t prio_fcf_matching_flags; 1633 uint8_t reserved_6_1[3]; 1634 uint16_t pri_fcf_vlan_id; 1635 uint8_t pri_fcf_fabric_name[8]; 1636 uint16_t reserved_6_2[7]; 1637 uint8_t spma_mac_addr[6]; 1638 uint16_t reserved_6_3[14]; 1639 1640 /* Offset 192. */ 1641 uint16_t reserved_7[32]; 1642 1643 /* 1644 * BIT 0 = Enable spinup delay 1645 * BIT 1 = Disable BIOS 1646 * BIT 2 = Enable Memory Map BIOS 1647 * BIT 3 = Enable Selectable Boot 1648 * BIT 4 = Disable RISC code load 1649 * BIT 5 = Disable Serdes 1650 * BIT 6 = Opt boot mode 1651 * BIT 7 = Interrupt enable 1652 * 1653 * BIT 8 = EV Control enable 1654 * BIT 9 = Enable lip reset 1655 * BIT 10 = Enable lip full login 1656 * BIT 11 = Enable target reset 1657 * BIT 12 = Stop firmware 1658 * BIT 13 = Enable nodename option 1659 * BIT 14 = Default WWPN valid 1660 * BIT 15 = Enable alternate WWN 1661 * 1662 * BIT 16 = CLP LUN string 1663 * BIT 17 = CLP Target string 1664 * BIT 18 = CLP BIOS enable string 1665 * BIT 19 = CLP Serdes string 1666 * BIT 20 = CLP WWPN string 1667 * BIT 21 = CLP WWNN string 1668 * BIT 22 = 1669 * BIT 23 = 1670 * BIT 24 = Keep WWPN 1671 * BIT 25 = Temp WWPN 1672 * BIT 26-31 = 1673 */ 1674 uint32_t host_p; 1675 1676 uint8_t alternate_port_name[WWN_SIZE]; 1677 uint8_t alternate_node_name[WWN_SIZE]; 1678 1679 uint8_t boot_port_name[WWN_SIZE]; 1680 uint16_t boot_lun_number; 1681 uint16_t reserved_8; 1682 1683 uint8_t alt1_boot_port_name[WWN_SIZE]; 1684 uint16_t alt1_boot_lun_number; 1685 uint16_t reserved_9; 1686 1687 uint8_t alt2_boot_port_name[WWN_SIZE]; 1688 uint16_t alt2_boot_lun_number; 1689 uint16_t reserved_10; 1690 1691 uint8_t alt3_boot_port_name[WWN_SIZE]; 1692 uint16_t alt3_boot_lun_number; 1693 uint16_t reserved_11; 1694 1695 /* 1696 * BIT 0 = Selective Login 1697 * BIT 1 = Alt-Boot Enable 1698 * BIT 2 = Reserved 1699 * BIT 3 = Boot Order List 1700 * BIT 4 = Reserved 1701 * BIT 5 = Selective LUN 1702 * BIT 6 = Reserved 1703 * BIT 7-31 = 1704 */ 1705 uint32_t efi_parameters; 1706 1707 uint8_t reset_delay; 1708 uint8_t reserved_12; 1709 uint16_t reserved_13; 1710 1711 uint16_t boot_id_number; 1712 uint16_t reserved_14; 1713 1714 uint16_t max_luns_per_target; 1715 uint16_t reserved_15; 1716 1717 uint16_t port_down_retry_count; 1718 uint16_t link_down_timeout; 1719 1720 /* FCode parameters. */ 1721 uint16_t fcode_parameter; 1722 1723 uint16_t reserved_16[3]; 1724 1725 /* Offset 352. */ 1726 uint8_t reserved_17[4]; 1727 uint16_t reserved_18[5]; 1728 uint8_t reserved_19[2]; 1729 uint16_t reserved_20[8]; 1730 1731 /* Offset 384. */ 1732 uint8_t reserved_21[16]; 1733 uint16_t reserved_22[3]; 1734 1735 /* 1736 * BIT 0 = Extended BB credits for LR 1737 * BIT 1 = Virtual Fabric Enable 1738 * BIT 2 = Enhanced Features Unused 1739 * BIT 3-7 = Enhanced Features Reserved 1740 */ 1741 /* Enhanced Features */ 1742 uint8_t enhanced_features; 1743 1744 uint8_t reserved_23; 1745 uint16_t reserved_24[4]; 1746 1747 /* Offset 416. */ 1748 uint16_t reserved_25[32]; 1749 1750 /* Offset 480. */ 1751 uint8_t model_name[16]; 1752 1753 /* Offset 496. */ 1754 uint16_t feature_mask_l; 1755 uint16_t feature_mask_h; 1756 uint16_t reserved_26[2]; 1757 1758 uint16_t subsystem_vendor_id; 1759 uint16_t subsystem_device_id; 1760 1761 uint32_t checksum; 1762 }; 1763 1764 /* 1765 * ISP Initialization Control Block. 1766 * Little endian except where noted. 1767 */ 1768 #define ICB_VERSION 1 1769 struct init_cb_81xx { 1770 uint16_t version; 1771 uint16_t reserved_1; 1772 1773 uint16_t frame_payload_size; 1774 uint16_t execution_throttle; 1775 uint16_t exchange_count; 1776 1777 uint16_t reserved_2; 1778 1779 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1780 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1781 1782 uint16_t response_q_inpointer; 1783 uint16_t request_q_outpointer; 1784 1785 uint16_t login_retry_count; 1786 1787 uint16_t prio_request_q_outpointer; 1788 1789 uint16_t response_q_length; 1790 uint16_t request_q_length; 1791 1792 uint16_t reserved_3; 1793 1794 uint16_t prio_request_q_length; 1795 1796 uint32_t request_q_address[2]; 1797 uint32_t response_q_address[2]; 1798 uint32_t prio_request_q_address[2]; 1799 1800 uint8_t reserved_4[8]; 1801 1802 uint16_t atio_q_inpointer; 1803 uint16_t atio_q_length; 1804 uint32_t atio_q_address[2]; 1805 1806 uint16_t interrupt_delay_timer; /* 100us increments. */ 1807 uint16_t login_timeout; 1808 1809 /* 1810 * BIT 0-3 = Reserved 1811 * BIT 4 = Enable Target Mode 1812 * BIT 5 = Disable Initiator Mode 1813 * BIT 6 = Reserved 1814 * BIT 7 = Reserved 1815 * 1816 * BIT 8-13 = Reserved 1817 * BIT 14 = Node Name Option 1818 * BIT 15-31 = Reserved 1819 */ 1820 uint32_t firmware_options_1; 1821 1822 /* 1823 * BIT 0 = Operation Mode bit 0 1824 * BIT 1 = Operation Mode bit 1 1825 * BIT 2 = Operation Mode bit 2 1826 * BIT 3 = Operation Mode bit 3 1827 * BIT 4-7 = Reserved 1828 * 1829 * BIT 8 = Enable Class 2 1830 * BIT 9 = Enable ACK0 1831 * BIT 10 = Reserved 1832 * BIT 11 = Enable FC-SP Security 1833 * BIT 12 = FC Tape Enable 1834 * BIT 13 = Reserved 1835 * BIT 14 = Enable Target PRLI Control 1836 * BIT 15-31 = Reserved 1837 */ 1838 uint32_t firmware_options_2; 1839 1840 /* 1841 * BIT 0-3 = Reserved 1842 * BIT 4 = FCP RSP Payload bit 0 1843 * BIT 5 = FCP RSP Payload bit 1 1844 * BIT 6 = Enable Receive Out-of-Order data frame handling 1845 * BIT 7 = Reserved 1846 * 1847 * BIT 8 = Reserved 1848 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 1849 * BIT 10-16 = Reserved 1850 * BIT 17 = Enable multiple FCFs 1851 * BIT 18-20 = MAC addressing mode 1852 * BIT 21-25 = Ethernet data rate 1853 * BIT 26 = Enable ethernet header rx IOCB for ATIO q 1854 * BIT 27 = Enable ethernet header rx IOCB for response q 1855 * BIT 28 = SPMA selection bit 0 1856 * BIT 28 = SPMA selection bit 1 1857 * BIT 30-31 = Reserved 1858 */ 1859 uint32_t firmware_options_3; 1860 1861 uint8_t reserved_5[8]; 1862 1863 uint8_t enode_mac[6]; 1864 1865 uint8_t reserved_6[10]; 1866 }; 1867 1868 struct mid_init_cb_81xx { 1869 struct init_cb_81xx init_cb; 1870 1871 uint16_t count; 1872 uint16_t options; 1873 1874 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 1875 }; 1876 1877 struct ex_init_cb_81xx { 1878 uint16_t ex_version; 1879 uint8_t prio_fcf_matching_flags; 1880 uint8_t reserved_1[3]; 1881 uint16_t pri_fcf_vlan_id; 1882 uint8_t pri_fcf_fabric_name[8]; 1883 uint16_t reserved_2[7]; 1884 uint8_t spma_mac_addr[6]; 1885 uint16_t reserved_3[14]; 1886 }; 1887 1888 #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000 1889 #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000 1890 1891 /* FCP priority config defines *************************************/ 1892 /* operations */ 1893 #define QLFC_FCP_PRIO_DISABLE 0x0 1894 #define QLFC_FCP_PRIO_ENABLE 0x1 1895 #define QLFC_FCP_PRIO_GET_CONFIG 0x2 1896 #define QLFC_FCP_PRIO_SET_CONFIG 0x3 1897 1898 struct qla_fcp_prio_entry { 1899 uint16_t flags; /* Describes parameter(s) in FCP */ 1900 /* priority entry that are valid */ 1901 #define FCP_PRIO_ENTRY_VALID 0x1 1902 #define FCP_PRIO_ENTRY_TAG_VALID 0x2 1903 #define FCP_PRIO_ENTRY_SPID_VALID 0x4 1904 #define FCP_PRIO_ENTRY_DPID_VALID 0x8 1905 #define FCP_PRIO_ENTRY_LUNB_VALID 0x10 1906 #define FCP_PRIO_ENTRY_LUNE_VALID 0x20 1907 #define FCP_PRIO_ENTRY_SWWN_VALID 0x40 1908 #define FCP_PRIO_ENTRY_DWWN_VALID 0x80 1909 uint8_t tag; /* Priority value */ 1910 uint8_t reserved; /* Reserved for future use */ 1911 uint32_t src_pid; /* Src port id. high order byte */ 1912 /* unused; -1 (wild card) */ 1913 uint32_t dst_pid; /* Src port id. high order byte */ 1914 /* unused; -1 (wild card) */ 1915 uint16_t lun_beg; /* 1st lun num of lun range. */ 1916 /* -1 (wild card) */ 1917 uint16_t lun_end; /* 2nd lun num of lun range. */ 1918 /* -1 (wild card) */ 1919 uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */ 1920 uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */ 1921 }; 1922 1923 struct qla_fcp_prio_cfg { 1924 uint8_t signature[4]; /* "HQOS" signature of config data */ 1925 uint16_t version; /* 1: Initial version */ 1926 uint16_t length; /* config data size in num bytes */ 1927 uint16_t checksum; /* config data bytes checksum */ 1928 uint16_t num_entries; /* Number of entries */ 1929 uint16_t size_of_entry; /* Size of each entry in num bytes */ 1930 uint8_t attributes; /* enable/disable, persistence */ 1931 #define FCP_PRIO_ATTR_DISABLE 0x0 1932 #define FCP_PRIO_ATTR_ENABLE 0x1 1933 #define FCP_PRIO_ATTR_PERSIST 0x2 1934 uint8_t reserved; /* Reserved for future use */ 1935 #define FCP_PRIO_CFG_HDR_SIZE 0x10 1936 struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */ 1937 #define FCP_PRIO_CFG_ENTRY_SIZE 0x20 1938 }; 1939 1940 #define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/ 1941 1942 /* 25XX Support ****************************************************/ 1943 #define FA_FCP_PRIO0_ADDR_25 0x3C000 1944 #define FA_FCP_PRIO1_ADDR_25 0x3E000 1945 1946 /* 81XX Flash locations -- occupies second 2MB region. */ 1947 #define FA_BOOT_CODE_ADDR_81 0x80000 1948 #define FA_RISC_CODE_ADDR_81 0xA0000 1949 #define FA_FW_AREA_ADDR_81 0xC0000 1950 #define FA_VPD_NVRAM_ADDR_81 0xD0000 1951 #define FA_VPD0_ADDR_81 0xD0000 1952 #define FA_VPD1_ADDR_81 0xD0400 1953 #define FA_NVRAM0_ADDR_81 0xD0080 1954 #define FA_NVRAM1_ADDR_81 0xD0180 1955 #define FA_FEATURE_ADDR_81 0xD4000 1956 #define FA_FLASH_DESCR_ADDR_81 0xD8000 1957 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400 1958 #define FA_HW_EVENT0_ADDR_81 0xDC000 1959 #define FA_HW_EVENT1_ADDR_81 0xDC400 1960 #define FA_NPIV_CONF0_ADDR_81 0xD1000 1961 #define FA_NPIV_CONF1_ADDR_81 0xD2000 1962 1963 /* 83XX Flash locations -- occupies second 8MB region. */ 1964 #define FA_FLASH_LAYOUT_ADDR_83 0xFC400 1965 1966 #endif 1967