1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Marvell Fibre Channel HBA Driver 4 * Copyright (c) 2021 Marvell 5 */ 6 #ifndef __QLA_EDIF_H 7 #define __QLA_EDIF_H 8 9 struct qla_scsi_host; 10 #define EDIF_APP_ID 0x73730001 11 12 #define EDIF_MAX_INDEX 2048 13 struct edif_sa_ctl { 14 struct list_head next; 15 uint16_t del_index; 16 uint16_t index; 17 uint16_t slot; 18 uint16_t flags; 19 #define EDIF_SA_CTL_FLG_REPL BIT_0 20 #define EDIF_SA_CTL_FLG_DEL BIT_1 21 #define EDIF_SA_CTL_FLG_CLEANUP_DEL BIT_4 22 // Invalidate Index bit and mirrors QLA_SA_UPDATE_FLAGS_DELETE 23 unsigned long state; 24 #define EDIF_SA_CTL_USED 1 /* Active Sa update */ 25 #define EDIF_SA_CTL_PEND 2 /* Waiting for slot */ 26 #define EDIF_SA_CTL_REPL 3 /* Active Replace and Delete */ 27 #define EDIF_SA_CTL_DEL 4 /* Delete Pending */ 28 struct fc_port *fcport; 29 struct bsg_job *bsg_job; 30 struct qla_sa_update_frame sa_frame; 31 }; 32 33 enum enode_flags_t { 34 ENODE_ACTIVE = 0x1, 35 }; 36 37 struct pur_core { 38 enum enode_flags_t enode_flags; 39 spinlock_t pur_lock; 40 struct list_head head; 41 }; 42 43 enum db_flags_t { 44 EDB_ACTIVE = 0x1, 45 }; 46 47 struct edif_dbell { 48 enum db_flags_t db_flags; 49 spinlock_t db_lock; 50 struct list_head head; 51 struct completion dbell; 52 }; 53 54 #define SA_UPDATE_IOCB_TYPE 0x71 /* Security Association Update IOCB entry */ 55 struct sa_update_28xx { 56 uint8_t entry_type; /* Entry type. */ 57 uint8_t entry_count; /* Entry count. */ 58 uint8_t sys_define; /* System Defined. */ 59 uint8_t entry_status; /* Entry Status. */ 60 61 uint32_t handle; /* IOCB System handle. */ 62 63 union { 64 __le16 nport_handle; /* in: N_PORT handle. */ 65 __le16 comp_sts; /* out: completion status */ 66 #define CS_PORT_EDIF_UNAVAIL 0x28 67 #define CS_PORT_EDIF_LOGOUT 0x29 68 #define CS_PORT_EDIF_SUPP_NOT_RDY 0x64 69 #define CS_PORT_EDIF_INV_REQ 0x66 70 } u; 71 uint8_t vp_index; 72 uint8_t reserved_1; 73 uint8_t port_id[3]; 74 uint8_t flags; 75 #define SA_FLAG_INVALIDATE BIT_0 76 #define SA_FLAG_TX BIT_1 // 1=tx, 0=rx 77 78 uint8_t sa_key[32]; /* 256 bit key */ 79 __le32 salt; 80 __le32 spi; 81 uint8_t sa_control; 82 #define SA_CNTL_ENC_FCSP (1 << 3) 83 #define SA_CNTL_ENC_OPD (2 << 3) 84 #define SA_CNTL_ENC_MSK (3 << 3) // mask bits 4,3 85 #define SA_CNTL_AES_GMAC (1 << 2) 86 #define SA_CNTL_KEY256 (2 << 0) 87 #define SA_CNTL_KEY128 0 88 89 uint8_t reserved_2; 90 __le16 sa_index; // reserve: bit 11-15 91 __le16 old_sa_info; 92 __le16 new_sa_info; 93 }; 94 95 #define NUM_ENTRIES 256 96 #define MAX_PAYLOAD 1024 97 #define PUR_GET 1 98 99 struct dinfo { 100 int nodecnt; 101 int lstate; 102 }; 103 104 struct pur_ninfo { 105 unsigned int pur_pend:1; 106 port_id_t pur_sid; 107 port_id_t pur_did; 108 uint8_t vp_idx; 109 short pur_bytes_rcvd; 110 unsigned short pur_nphdl; 111 unsigned int pur_rx_xchg_address; 112 }; 113 114 struct purexevent { 115 struct pur_ninfo pur_info; 116 unsigned char *msgp; 117 u32 msgp_len; 118 }; 119 120 #define N_UNDEF 0 121 #define N_PUREX 1 122 struct enode { 123 struct list_head list; 124 struct dinfo dinfo; 125 uint32_t ntype; 126 union { 127 struct purexevent purexinfo; 128 } u; 129 }; 130 131 #define EDIF_SESSION_DOWN(_s) \ 132 (qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \ 133 _s->disc_state == DSC_DELETED || \ 134 !_s->edif.app_sess_online)) 135 136 #endif /* __QLA_EDIF_H */ 137