1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 #include <linux/btree.h> 29 30 #include <scsi/scsi.h> 31 #include <scsi/scsi_host.h> 32 #include <scsi/scsi_device.h> 33 #include <scsi/scsi_cmnd.h> 34 #include <scsi/scsi_transport_fc.h> 35 #include <scsi/scsi_bsg_fc.h> 36 37 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 38 typedef struct { 39 uint8_t domain; 40 uint8_t area; 41 uint8_t al_pa; 42 } be_id_t; 43 44 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 45 typedef struct { 46 uint8_t al_pa; 47 uint8_t area; 48 uint8_t domain; 49 } le_id_t; 50 51 #include "qla_bsg.h" 52 #include "qla_dsd.h" 53 #include "qla_nx.h" 54 #include "qla_nx2.h" 55 #include "qla_nvme.h" 56 #define QLA2XXX_DRIVER_NAME "qla2xxx" 57 #define QLA2XXX_APIDEV "ql2xapidev" 58 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 59 60 /* 61 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 62 * but that's fine as we don't look at the last 24 ones for 63 * ISP2100 HBAs. 64 */ 65 #define MAILBOX_REGISTER_COUNT_2100 8 66 #define MAILBOX_REGISTER_COUNT_2200 24 67 #define MAILBOX_REGISTER_COUNT 32 68 69 #define QLA2200A_RISC_ROM_VER 4 70 #define FPM_2300 6 71 #define FPM_2310 7 72 73 #include "qla_settings.h" 74 75 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 76 77 /* 78 * Data bit definitions 79 */ 80 #define BIT_0 0x1 81 #define BIT_1 0x2 82 #define BIT_2 0x4 83 #define BIT_3 0x8 84 #define BIT_4 0x10 85 #define BIT_5 0x20 86 #define BIT_6 0x40 87 #define BIT_7 0x80 88 #define BIT_8 0x100 89 #define BIT_9 0x200 90 #define BIT_10 0x400 91 #define BIT_11 0x800 92 #define BIT_12 0x1000 93 #define BIT_13 0x2000 94 #define BIT_14 0x4000 95 #define BIT_15 0x8000 96 #define BIT_16 0x10000 97 #define BIT_17 0x20000 98 #define BIT_18 0x40000 99 #define BIT_19 0x80000 100 #define BIT_20 0x100000 101 #define BIT_21 0x200000 102 #define BIT_22 0x400000 103 #define BIT_23 0x800000 104 #define BIT_24 0x1000000 105 #define BIT_25 0x2000000 106 #define BIT_26 0x4000000 107 #define BIT_27 0x8000000 108 #define BIT_28 0x10000000 109 #define BIT_29 0x20000000 110 #define BIT_30 0x40000000 111 #define BIT_31 0x80000000 112 113 #define LSB(x) ((uint8_t)(x)) 114 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 115 116 #define LSW(x) ((uint16_t)(x)) 117 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 118 119 #define LSD(x) ((uint32_t)((uint64_t)(x))) 120 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 121 122 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 123 124 /* 125 * I/O register 126 */ 127 128 #define RD_REG_BYTE(addr) readb(addr) 129 #define RD_REG_WORD(addr) readw(addr) 130 #define RD_REG_DWORD(addr) readl(addr) 131 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 132 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 133 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 134 #define WRT_REG_BYTE(addr, data) writeb(data, addr) 135 #define WRT_REG_WORD(addr, data) writew(data, addr) 136 #define WRT_REG_DWORD(addr, data) writel(data, addr) 137 138 /* 139 * ISP83XX specific remote register addresses 140 */ 141 #define QLA83XX_LED_PORT0 0x00201320 142 #define QLA83XX_LED_PORT1 0x00201328 143 #define QLA83XX_IDC_DEV_STATE 0x22102384 144 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 145 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 146 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 147 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 148 #define QLA83XX_IDC_CONTROL 0x22102390 149 #define QLA83XX_IDC_AUDIT 0x22102394 150 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 151 #define QLA83XX_DRIVER_LOCKID 0x22102104 152 #define QLA83XX_DRIVER_LOCK 0x8111c028 153 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 154 #define QLA83XX_FLASH_LOCKID 0x22102100 155 #define QLA83XX_FLASH_LOCK 0x8111c010 156 #define QLA83XX_FLASH_UNLOCK 0x8111c014 157 #define QLA83XX_DEV_PARTINFO1 0x221023e0 158 #define QLA83XX_DEV_PARTINFO2 0x221023e4 159 #define QLA83XX_FW_HEARTBEAT 0x221020b0 160 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 161 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 162 163 /* 83XX: Macros defining 8200 AEN Reason codes */ 164 #define IDC_DEVICE_STATE_CHANGE BIT_0 165 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 166 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 167 #define IDC_HEARTBEAT_FAILURE BIT_3 168 169 /* 83XX: Macros defining 8200 AEN Error-levels */ 170 #define ERR_LEVEL_NON_FATAL 0x1 171 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 172 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 173 174 /* 83XX: Macros for IDC Version */ 175 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 176 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 177 178 /* 83XX: Macros for scheduling dpc tasks */ 179 #define QLA83XX_NIC_CORE_RESET 0x1 180 #define QLA83XX_IDC_STATE_HANDLER 0x2 181 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 182 183 /* 83XX: Macros for defining IDC-Control bits */ 184 #define QLA83XX_IDC_RESET_DISABLED BIT_0 185 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 186 187 /* 83XX: Macros for different timeouts */ 188 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 189 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 190 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 191 192 /* 83XX: Macros for defining class in DEV-Partition Info register */ 193 #define QLA83XX_CLASS_TYPE_NONE 0x0 194 #define QLA83XX_CLASS_TYPE_NIC 0x1 195 #define QLA83XX_CLASS_TYPE_FCOE 0x2 196 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 197 198 /* 83XX: Macros for IDC Lock-Recovery stages */ 199 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 200 * lock-recovery 201 */ 202 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 203 204 /* 83XX: Macros for IDC Audit type */ 205 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 206 * dev-state change to NEED-RESET 207 * or NEED-QUIESCENT 208 */ 209 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 210 * reset-recovery completion is 211 * second 212 */ 213 /* ISP2031: Values for laser on/off */ 214 #define PORT_0_2031 0x00201340 215 #define PORT_1_2031 0x00201350 216 #define LASER_ON_2031 0x01800100 217 #define LASER_OFF_2031 0x01800180 218 219 /* 220 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 221 * 133Mhz slot. 222 */ 223 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 224 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr)) 225 226 /* 227 * Fibre Channel device definitions. 228 */ 229 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 230 #define MAX_FIBRE_DEVICES_2100 512 231 #define MAX_FIBRE_DEVICES_2400 2048 232 #define MAX_FIBRE_DEVICES_LOOP 128 233 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 234 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 235 #define MAX_FIBRE_LUNS 0xFFFF 236 #define MAX_HOST_COUNT 16 237 238 /* 239 * Host adapter default definitions. 240 */ 241 #define MAX_BUSES 1 /* We only have one bus today */ 242 #define MIN_LUNS 8 243 #define MAX_LUNS MAX_FIBRE_LUNS 244 #define MAX_CMDS_PER_LUN 255 245 246 /* 247 * Fibre Channel device definitions. 248 */ 249 #define SNS_LAST_LOOP_ID_2100 0xfe 250 #define SNS_LAST_LOOP_ID_2300 0x7ff 251 252 #define LAST_LOCAL_LOOP_ID 0x7d 253 #define SNS_FL_PORT 0x7e 254 #define FABRIC_CONTROLLER 0x7f 255 #define SIMPLE_NAME_SERVER 0x80 256 #define SNS_FIRST_LOOP_ID 0x81 257 #define MANAGEMENT_SERVER 0xfe 258 #define BROADCAST 0xff 259 260 /* 261 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 262 * valid range of an N-PORT id is 0 through 0x7ef. 263 */ 264 #define NPH_LAST_HANDLE 0x7ee 265 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ 266 #define NPH_SNS 0x7fc /* FFFFFC */ 267 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 268 #define NPH_F_PORT 0x7fe /* FFFFFE */ 269 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 270 271 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 272 273 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 274 #include "qla_fw.h" 275 276 struct name_list_extended { 277 struct get_name_list_extended *l; 278 dma_addr_t ldma; 279 struct list_head fcports; 280 u32 size; 281 u8 sent; 282 }; 283 /* 284 * Timeout timer counts in seconds 285 */ 286 #define PORT_RETRY_TIME 1 287 #define LOOP_DOWN_TIMEOUT 60 288 #define LOOP_DOWN_TIME 255 /* 240 */ 289 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 290 291 #define DEFAULT_OUTSTANDING_COMMANDS 4096 292 #define MIN_OUTSTANDING_COMMANDS 128 293 294 /* ISP request and response entry counts (37-65535) */ 295 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 296 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 297 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 298 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 299 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 300 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 301 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 302 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 303 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 304 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 305 #define FW_DEF_EXCHANGES_CNT 2048 306 #define FW_MAX_EXCHANGES_CNT (32 * 1024) 307 #define REDUCE_EXCHANGES_CNT (8 * 1024) 308 309 struct req_que; 310 struct qla_tgt_sess; 311 312 /* 313 * SCSI Request Block 314 */ 315 struct srb_cmd { 316 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 317 uint32_t request_sense_length; 318 uint32_t fw_sense_length; 319 uint8_t *request_sense_ptr; 320 struct ct6_dsd *ct6_ctx; 321 struct crc_context *crc_ctx; 322 }; 323 324 /* 325 * SRB flag definitions 326 */ 327 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 328 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 329 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 330 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 331 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 332 #define SRB_WAKEUP_ON_COMP BIT_6 333 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */ 334 335 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 336 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 337 338 /* 339 * 24 bit port ID type definition. 340 */ 341 typedef union { 342 uint32_t b24 : 24; 343 344 struct { 345 #ifdef __BIG_ENDIAN 346 uint8_t domain; 347 uint8_t area; 348 uint8_t al_pa; 349 #elif defined(__LITTLE_ENDIAN) 350 uint8_t al_pa; 351 uint8_t area; 352 uint8_t domain; 353 #else 354 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 355 #endif 356 uint8_t rsvd_1; 357 } b; 358 } port_id_t; 359 #define INVALID_PORT_ID 0xFFFFFF 360 361 static inline le_id_t be_id_to_le(be_id_t id) 362 { 363 le_id_t res; 364 365 res.domain = id.domain; 366 res.area = id.area; 367 res.al_pa = id.al_pa; 368 369 return res; 370 } 371 372 static inline be_id_t le_id_to_be(le_id_t id) 373 { 374 be_id_t res; 375 376 res.domain = id.domain; 377 res.area = id.area; 378 res.al_pa = id.al_pa; 379 380 return res; 381 } 382 383 static inline port_id_t be_to_port_id(be_id_t id) 384 { 385 port_id_t res; 386 387 res.b.domain = id.domain; 388 res.b.area = id.area; 389 res.b.al_pa = id.al_pa; 390 res.b.rsvd_1 = 0; 391 392 return res; 393 } 394 395 static inline be_id_t port_id_to_be_id(port_id_t port_id) 396 { 397 be_id_t res; 398 399 res.domain = port_id.b.domain; 400 res.area = port_id.b.area; 401 res.al_pa = port_id.b.al_pa; 402 403 return res; 404 } 405 406 struct els_logo_payload { 407 uint8_t opcode; 408 uint8_t rsvd[3]; 409 uint8_t s_id[3]; 410 uint8_t rsvd1[1]; 411 uint8_t wwpn[WWN_SIZE]; 412 }; 413 414 struct els_plogi_payload { 415 uint8_t opcode; 416 uint8_t rsvd[3]; 417 uint8_t data[112]; 418 }; 419 420 struct ct_arg { 421 void *iocb; 422 u16 nport_handle; 423 dma_addr_t req_dma; 424 dma_addr_t rsp_dma; 425 u32 req_size; 426 u32 rsp_size; 427 u32 req_allocated_size; 428 u32 rsp_allocated_size; 429 void *req; 430 void *rsp; 431 port_id_t id; 432 }; 433 434 /* 435 * SRB extensions. 436 */ 437 struct srb_iocb { 438 union { 439 struct { 440 uint16_t flags; 441 #define SRB_LOGIN_RETRIED BIT_0 442 #define SRB_LOGIN_COND_PLOGI BIT_1 443 #define SRB_LOGIN_SKIP_PRLI BIT_2 444 #define SRB_LOGIN_NVME_PRLI BIT_3 445 #define SRB_LOGIN_PRLI_ONLY BIT_4 446 uint16_t data[2]; 447 u32 iop[2]; 448 } logio; 449 struct { 450 #define ELS_DCMD_TIMEOUT 20 451 #define ELS_DCMD_LOGO 0x5 452 uint32_t flags; 453 uint32_t els_cmd; 454 struct completion comp; 455 struct els_logo_payload *els_logo_pyld; 456 dma_addr_t els_logo_pyld_dma; 457 } els_logo; 458 struct els_plogi { 459 #define ELS_DCMD_PLOGI 0x3 460 uint32_t flags; 461 uint32_t els_cmd; 462 struct completion comp; 463 struct els_plogi_payload *els_plogi_pyld; 464 struct els_plogi_payload *els_resp_pyld; 465 u32 tx_size; 466 u32 rx_size; 467 dma_addr_t els_plogi_pyld_dma; 468 dma_addr_t els_resp_pyld_dma; 469 uint32_t fw_status[3]; 470 __le16 comp_status; 471 __le16 len; 472 } els_plogi; 473 struct { 474 /* 475 * Values for flags field below are as 476 * defined in tsk_mgmt_entry struct 477 * for control_flags field in qla_fw.h. 478 */ 479 uint64_t lun; 480 uint32_t flags; 481 uint32_t data; 482 struct completion comp; 483 __le16 comp_status; 484 } tmf; 485 struct { 486 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 487 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 488 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 489 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 490 #define FXDISC_TIMEOUT 20 491 uint8_t flags; 492 uint32_t req_len; 493 uint32_t rsp_len; 494 void *req_addr; 495 void *rsp_addr; 496 dma_addr_t req_dma_handle; 497 dma_addr_t rsp_dma_handle; 498 __le32 adapter_id; 499 __le32 adapter_id_hi; 500 __le16 req_func_type; 501 __le32 req_data; 502 __le32 req_data_extra; 503 __le32 result; 504 __le32 seq_number; 505 __le16 fw_flags; 506 struct completion fxiocb_comp; 507 __le32 reserved_0; 508 uint8_t reserved_1; 509 } fxiocb; 510 struct { 511 uint32_t cmd_hndl; 512 __le16 comp_status; 513 __le16 req_que_no; 514 struct completion comp; 515 } abt; 516 struct ct_arg ctarg; 517 #define MAX_IOCB_MB_REG 28 518 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 519 struct { 520 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 521 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 522 void *out, *in; 523 dma_addr_t out_dma, in_dma; 524 struct completion comp; 525 int rc; 526 } mbx; 527 struct { 528 struct imm_ntfy_from_isp *ntfy; 529 } nack; 530 struct { 531 __le16 comp_status; 532 uint16_t rsp_pyld_len; 533 uint8_t aen_op; 534 void *desc; 535 536 /* These are only used with ls4 requests */ 537 int cmd_len; 538 int rsp_len; 539 dma_addr_t cmd_dma; 540 dma_addr_t rsp_dma; 541 enum nvmefc_fcp_datadir dir; 542 uint32_t dl; 543 uint32_t timeout_sec; 544 struct list_head entry; 545 } nvme; 546 struct { 547 u16 cmd; 548 u16 vp_index; 549 } ctrlvp; 550 } u; 551 552 struct timer_list timer; 553 void (*timeout)(void *); 554 }; 555 556 /* Values for srb_ctx type */ 557 #define SRB_LOGIN_CMD 1 558 #define SRB_LOGOUT_CMD 2 559 #define SRB_ELS_CMD_RPT 3 560 #define SRB_ELS_CMD_HST 4 561 #define SRB_CT_CMD 5 562 #define SRB_ADISC_CMD 6 563 #define SRB_TM_CMD 7 564 #define SRB_SCSI_CMD 8 565 #define SRB_BIDI_CMD 9 566 #define SRB_FXIOCB_DCMD 10 567 #define SRB_FXIOCB_BCMD 11 568 #define SRB_ABT_CMD 12 569 #define SRB_ELS_DCMD 13 570 #define SRB_MB_IOCB 14 571 #define SRB_CT_PTHRU_CMD 15 572 #define SRB_NACK_PLOGI 16 573 #define SRB_NACK_PRLI 17 574 #define SRB_NACK_LOGO 18 575 #define SRB_NVME_CMD 19 576 #define SRB_NVME_LS 20 577 #define SRB_PRLI_CMD 21 578 #define SRB_CTRL_VP 22 579 #define SRB_PRLO_CMD 23 580 581 enum { 582 TYPE_SRB, 583 TYPE_TGT_CMD, 584 TYPE_TGT_TMCMD, /* task management */ 585 }; 586 587 typedef struct srb { 588 /* 589 * Do not move cmd_type field, it needs to 590 * line up with qla_tgt_cmd->cmd_type 591 */ 592 uint8_t cmd_type; 593 uint8_t pad[3]; 594 atomic_t ref_count; 595 struct kref cmd_kref; /* need to migrate ref_count over to this */ 596 void *priv; 597 wait_queue_head_t nvme_ls_waitq; 598 struct fc_port *fcport; 599 struct scsi_qla_host *vha; 600 unsigned int start_timer:1; 601 uint32_t handle; 602 uint16_t flags; 603 uint16_t type; 604 const char *name; 605 int iocbs; 606 struct qla_qpair *qpair; 607 struct list_head elem; 608 u32 gen1; /* scratch */ 609 u32 gen2; /* scratch */ 610 int rc; 611 int retry_count; 612 struct completion *comp; 613 union { 614 struct srb_iocb iocb_cmd; 615 struct bsg_job *bsg_job; 616 struct srb_cmd scmd; 617 } u; 618 /* 619 * Report completion status @res and call sp_put(@sp). @res is 620 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a 621 * QLA_* status value. 622 */ 623 void (*done)(struct srb *sp, int res); 624 /* Stop the timer and free @sp. Only used by the FCP code. */ 625 void (*free)(struct srb *sp); 626 /* 627 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe 628 * code. 629 */ 630 void (*put_fn)(struct kref *kref); 631 } srb_t; 632 633 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 634 635 #define GET_CMD_SENSE_LEN(sp) \ 636 (sp->u.scmd.request_sense_length) 637 #define SET_CMD_SENSE_LEN(sp, len) \ 638 (sp->u.scmd.request_sense_length = len) 639 #define GET_CMD_SENSE_PTR(sp) \ 640 (sp->u.scmd.request_sense_ptr) 641 #define SET_CMD_SENSE_PTR(sp, ptr) \ 642 (sp->u.scmd.request_sense_ptr = ptr) 643 #define GET_FW_SENSE_LEN(sp) \ 644 (sp->u.scmd.fw_sense_length) 645 #define SET_FW_SENSE_LEN(sp, len) \ 646 (sp->u.scmd.fw_sense_length = len) 647 648 struct msg_echo_lb { 649 dma_addr_t send_dma; 650 dma_addr_t rcv_dma; 651 uint16_t req_sg_cnt; 652 uint16_t rsp_sg_cnt; 653 uint16_t options; 654 uint32_t transfer_size; 655 uint32_t iteration_count; 656 }; 657 658 /* 659 * ISP I/O Register Set structure definitions. 660 */ 661 struct device_reg_2xxx { 662 uint16_t flash_address; /* Flash BIOS address */ 663 uint16_t flash_data; /* Flash BIOS data */ 664 uint16_t unused_1[1]; /* Gap */ 665 uint16_t ctrl_status; /* Control/Status */ 666 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 667 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 668 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 669 670 uint16_t ictrl; /* Interrupt control */ 671 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 672 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 673 674 uint16_t istatus; /* Interrupt status */ 675 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 676 677 uint16_t semaphore; /* Semaphore */ 678 uint16_t nvram; /* NVRAM register. */ 679 #define NVR_DESELECT 0 680 #define NVR_BUSY BIT_15 681 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 682 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 683 #define NVR_DATA_IN BIT_3 684 #define NVR_DATA_OUT BIT_2 685 #define NVR_SELECT BIT_1 686 #define NVR_CLOCK BIT_0 687 688 #define NVR_WAIT_CNT 20000 689 690 union { 691 struct { 692 uint16_t mailbox0; 693 uint16_t mailbox1; 694 uint16_t mailbox2; 695 uint16_t mailbox3; 696 uint16_t mailbox4; 697 uint16_t mailbox5; 698 uint16_t mailbox6; 699 uint16_t mailbox7; 700 uint16_t unused_2[59]; /* Gap */ 701 } __attribute__((packed)) isp2100; 702 struct { 703 /* Request Queue */ 704 uint16_t req_q_in; /* In-Pointer */ 705 uint16_t req_q_out; /* Out-Pointer */ 706 /* Response Queue */ 707 uint16_t rsp_q_in; /* In-Pointer */ 708 uint16_t rsp_q_out; /* Out-Pointer */ 709 710 /* RISC to Host Status */ 711 uint32_t host_status; 712 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 713 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 714 715 /* Host to Host Semaphore */ 716 uint16_t host_semaphore; 717 uint16_t unused_3[17]; /* Gap */ 718 uint16_t mailbox0; 719 uint16_t mailbox1; 720 uint16_t mailbox2; 721 uint16_t mailbox3; 722 uint16_t mailbox4; 723 uint16_t mailbox5; 724 uint16_t mailbox6; 725 uint16_t mailbox7; 726 uint16_t mailbox8; 727 uint16_t mailbox9; 728 uint16_t mailbox10; 729 uint16_t mailbox11; 730 uint16_t mailbox12; 731 uint16_t mailbox13; 732 uint16_t mailbox14; 733 uint16_t mailbox15; 734 uint16_t mailbox16; 735 uint16_t mailbox17; 736 uint16_t mailbox18; 737 uint16_t mailbox19; 738 uint16_t mailbox20; 739 uint16_t mailbox21; 740 uint16_t mailbox22; 741 uint16_t mailbox23; 742 uint16_t mailbox24; 743 uint16_t mailbox25; 744 uint16_t mailbox26; 745 uint16_t mailbox27; 746 uint16_t mailbox28; 747 uint16_t mailbox29; 748 uint16_t mailbox30; 749 uint16_t mailbox31; 750 uint16_t fb_cmd; 751 uint16_t unused_4[10]; /* Gap */ 752 } __attribute__((packed)) isp2300; 753 } u; 754 755 uint16_t fpm_diag_config; 756 uint16_t unused_5[0x4]; /* Gap */ 757 uint16_t risc_hw; 758 uint16_t unused_5_1; /* Gap */ 759 uint16_t pcr; /* Processor Control Register. */ 760 uint16_t unused_6[0x5]; /* Gap */ 761 uint16_t mctr; /* Memory Configuration and Timing. */ 762 uint16_t unused_7[0x3]; /* Gap */ 763 uint16_t fb_cmd_2100; /* Unused on 23XX */ 764 uint16_t unused_8[0x3]; /* Gap */ 765 uint16_t hccr; /* Host command & control register. */ 766 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 767 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 768 /* HCCR commands */ 769 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 770 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 771 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 772 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 773 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 774 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 775 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 776 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 777 778 uint16_t unused_9[5]; /* Gap */ 779 uint16_t gpiod; /* GPIO Data register. */ 780 uint16_t gpioe; /* GPIO Enable register. */ 781 #define GPIO_LED_MASK 0x00C0 782 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 783 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 784 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 785 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 786 #define GPIO_LED_ALL_OFF 0x0000 787 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 788 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 789 790 union { 791 struct { 792 uint16_t unused_10[8]; /* Gap */ 793 uint16_t mailbox8; 794 uint16_t mailbox9; 795 uint16_t mailbox10; 796 uint16_t mailbox11; 797 uint16_t mailbox12; 798 uint16_t mailbox13; 799 uint16_t mailbox14; 800 uint16_t mailbox15; 801 uint16_t mailbox16; 802 uint16_t mailbox17; 803 uint16_t mailbox18; 804 uint16_t mailbox19; 805 uint16_t mailbox20; 806 uint16_t mailbox21; 807 uint16_t mailbox22; 808 uint16_t mailbox23; /* Also probe reg. */ 809 } __attribute__((packed)) isp2200; 810 } u_end; 811 }; 812 813 struct device_reg_25xxmq { 814 uint32_t req_q_in; 815 uint32_t req_q_out; 816 uint32_t rsp_q_in; 817 uint32_t rsp_q_out; 818 uint32_t atio_q_in; 819 uint32_t atio_q_out; 820 }; 821 822 823 struct device_reg_fx00 { 824 uint32_t mailbox0; /* 00 */ 825 uint32_t mailbox1; /* 04 */ 826 uint32_t mailbox2; /* 08 */ 827 uint32_t mailbox3; /* 0C */ 828 uint32_t mailbox4; /* 10 */ 829 uint32_t mailbox5; /* 14 */ 830 uint32_t mailbox6; /* 18 */ 831 uint32_t mailbox7; /* 1C */ 832 uint32_t mailbox8; /* 20 */ 833 uint32_t mailbox9; /* 24 */ 834 uint32_t mailbox10; /* 28 */ 835 uint32_t mailbox11; 836 uint32_t mailbox12; 837 uint32_t mailbox13; 838 uint32_t mailbox14; 839 uint32_t mailbox15; 840 uint32_t mailbox16; 841 uint32_t mailbox17; 842 uint32_t mailbox18; 843 uint32_t mailbox19; 844 uint32_t mailbox20; 845 uint32_t mailbox21; 846 uint32_t mailbox22; 847 uint32_t mailbox23; 848 uint32_t mailbox24; 849 uint32_t mailbox25; 850 uint32_t mailbox26; 851 uint32_t mailbox27; 852 uint32_t mailbox28; 853 uint32_t mailbox29; 854 uint32_t mailbox30; 855 uint32_t mailbox31; 856 uint32_t aenmailbox0; 857 uint32_t aenmailbox1; 858 uint32_t aenmailbox2; 859 uint32_t aenmailbox3; 860 uint32_t aenmailbox4; 861 uint32_t aenmailbox5; 862 uint32_t aenmailbox6; 863 uint32_t aenmailbox7; 864 /* Request Queue. */ 865 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 866 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 867 /* Response Queue. */ 868 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 869 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 870 /* Init values shadowed on FW Up Event */ 871 uint32_t initval0; /* B0 */ 872 uint32_t initval1; /* B4 */ 873 uint32_t initval2; /* B8 */ 874 uint32_t initval3; /* BC */ 875 uint32_t initval4; /* C0 */ 876 uint32_t initval5; /* C4 */ 877 uint32_t initval6; /* C8 */ 878 uint32_t initval7; /* CC */ 879 uint32_t fwheartbeat; /* D0 */ 880 uint32_t pseudoaen; /* D4 */ 881 }; 882 883 884 885 typedef union { 886 struct device_reg_2xxx isp; 887 struct device_reg_24xx isp24; 888 struct device_reg_25xxmq isp25mq; 889 struct device_reg_82xx isp82; 890 struct device_reg_fx00 ispfx00; 891 } __iomem device_reg_t; 892 893 #define ISP_REQ_Q_IN(ha, reg) \ 894 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 895 &(reg)->u.isp2100.mailbox4 : \ 896 &(reg)->u.isp2300.req_q_in) 897 #define ISP_REQ_Q_OUT(ha, reg) \ 898 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 899 &(reg)->u.isp2100.mailbox4 : \ 900 &(reg)->u.isp2300.req_q_out) 901 #define ISP_RSP_Q_IN(ha, reg) \ 902 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 903 &(reg)->u.isp2100.mailbox5 : \ 904 &(reg)->u.isp2300.rsp_q_in) 905 #define ISP_RSP_Q_OUT(ha, reg) \ 906 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 907 &(reg)->u.isp2100.mailbox5 : \ 908 &(reg)->u.isp2300.rsp_q_out) 909 910 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 911 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 912 913 #define MAILBOX_REG(ha, reg, num) \ 914 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 915 (num < 8 ? \ 916 &(reg)->u.isp2100.mailbox0 + (num) : \ 917 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 918 &(reg)->u.isp2300.mailbox0 + (num)) 919 #define RD_MAILBOX_REG(ha, reg, num) \ 920 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 921 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 922 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 923 924 #define FB_CMD_REG(ha, reg) \ 925 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 926 &(reg)->fb_cmd_2100 : \ 927 &(reg)->u.isp2300.fb_cmd) 928 #define RD_FB_CMD_REG(ha, reg) \ 929 RD_REG_WORD(FB_CMD_REG(ha, reg)) 930 #define WRT_FB_CMD_REG(ha, reg, data) \ 931 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 932 933 typedef struct { 934 uint32_t out_mb; /* outbound from driver */ 935 uint32_t in_mb; /* Incoming from RISC */ 936 uint16_t mb[MAILBOX_REGISTER_COUNT]; 937 long buf_size; 938 void *bufp; 939 uint32_t tov; 940 uint8_t flags; 941 #define MBX_DMA_IN BIT_0 942 #define MBX_DMA_OUT BIT_1 943 #define IOCTL_CMD BIT_2 944 } mbx_cmd_t; 945 946 struct mbx_cmd_32 { 947 uint32_t out_mb; /* outbound from driver */ 948 uint32_t in_mb; /* Incoming from RISC */ 949 uint32_t mb[MAILBOX_REGISTER_COUNT]; 950 long buf_size; 951 void *bufp; 952 uint32_t tov; 953 uint8_t flags; 954 #define MBX_DMA_IN BIT_0 955 #define MBX_DMA_OUT BIT_1 956 #define IOCTL_CMD BIT_2 957 }; 958 959 960 #define MBX_TOV_SECONDS 30 961 962 /* 963 * ISP product identification definitions in mailboxes after reset. 964 */ 965 #define PROD_ID_1 0x4953 966 #define PROD_ID_2 0x0000 967 #define PROD_ID_2a 0x5020 968 #define PROD_ID_3 0x2020 969 970 /* 971 * ISP mailbox Self-Test status codes 972 */ 973 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 974 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 975 #define MBS_BUSY 4 /* Busy. */ 976 977 /* 978 * ISP mailbox command complete status codes 979 */ 980 #define MBS_COMMAND_COMPLETE 0x4000 981 #define MBS_INVALID_COMMAND 0x4001 982 #define MBS_HOST_INTERFACE_ERROR 0x4002 983 #define MBS_TEST_FAILED 0x4003 984 #define MBS_COMMAND_ERROR 0x4005 985 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 986 #define MBS_PORT_ID_USED 0x4007 987 #define MBS_LOOP_ID_USED 0x4008 988 #define MBS_ALL_IDS_IN_USE 0x4009 989 #define MBS_NOT_LOGGED_IN 0x400A 990 #define MBS_LINK_DOWN_ERROR 0x400B 991 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 992 993 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs) 994 { 995 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR; 996 } 997 998 /* 999 * ISP mailbox asynchronous event status codes 1000 */ 1001 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 1002 #define MBA_RESET 0x8001 /* Reset Detected. */ 1003 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 1004 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 1005 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 1006 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 1007 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 1008 /* occurred. */ 1009 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 1010 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 1011 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 1012 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 1013 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 1014 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 1015 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 1016 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 1017 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 1018 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 1019 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 1020 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 1021 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 1022 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 1023 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 1024 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 1025 /* used. */ 1026 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 1027 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 1028 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 1029 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 1030 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 1031 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 1032 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 1033 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 1034 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 1035 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 1036 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 1037 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 1038 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 1039 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 1040 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 1041 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 1042 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 1043 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 1044 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 1045 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 1046 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 1047 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 1048 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 1049 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 1050 Notification */ 1051 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 1052 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 1053 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 1054 /* 83XX FCoE specific */ 1055 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 1056 1057 /* Interrupt type codes */ 1058 #define INTR_ROM_MB_SUCCESS 0x1 1059 #define INTR_ROM_MB_FAILED 0x2 1060 #define INTR_MB_SUCCESS 0x10 1061 #define INTR_MB_FAILED 0x11 1062 #define INTR_ASYNC_EVENT 0x12 1063 #define INTR_RSP_QUE_UPDATE 0x13 1064 #define INTR_RSP_QUE_UPDATE_83XX 0x14 1065 #define INTR_ATIO_QUE_UPDATE 0x1C 1066 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 1067 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 1068 1069 /* ISP mailbox loopback echo diagnostic error code */ 1070 #define MBS_LB_RESET 0x17 1071 /* 1072 * Firmware options 1, 2, 3. 1073 */ 1074 #define FO1_AE_ON_LIPF8 BIT_0 1075 #define FO1_AE_ALL_LIP_RESET BIT_1 1076 #define FO1_CTIO_RETRY BIT_3 1077 #define FO1_DISABLE_LIP_F7_SW BIT_4 1078 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 1079 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 1080 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 1081 #define FO1_SET_EMPHASIS_SWING BIT_8 1082 #define FO1_AE_AUTO_BYPASS BIT_9 1083 #define FO1_ENABLE_PURE_IOCB BIT_10 1084 #define FO1_AE_PLOGI_RJT BIT_11 1085 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 1086 #define FO1_AE_QUEUE_FULL BIT_13 1087 1088 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 1089 #define FO2_REV_LOOPBACK BIT_1 1090 1091 #define FO3_ENABLE_EMERG_IOCB BIT_0 1092 #define FO3_AE_RND_ERROR BIT_1 1093 1094 /* 24XX additional firmware options */ 1095 #define ADD_FO_COUNT 3 1096 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 1097 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 1098 1099 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 1100 1101 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 1102 1103 /* 1104 * ISP mailbox commands 1105 */ 1106 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1107 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1108 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 1109 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 1110 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1111 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 1112 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 1113 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 1114 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */ 1115 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 1116 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 1117 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 1118 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 1119 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 1120 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 1121 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 1122 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 1123 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1124 #define MBC_RESET 0x18 /* Reset. */ 1125 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1126 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1127 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1128 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1129 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1130 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1131 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1132 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1133 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1134 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1135 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1136 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1137 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1138 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1139 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1140 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1141 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1142 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1143 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1144 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1145 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1146 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1147 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1148 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1149 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1150 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1151 /* Initialization Procedure */ 1152 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1153 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1154 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1155 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1156 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1157 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1158 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1159 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1160 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1161 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1162 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1163 /* commandd. */ 1164 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1165 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1166 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1167 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1168 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1169 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1170 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1171 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1172 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1173 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1174 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1175 1176 /* 1177 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1178 * should be defined with MBC_MR_* 1179 */ 1180 #define MBC_MR_DRV_SHUTDOWN 0x6A 1181 1182 /* 1183 * ISP24xx mailbox commands 1184 */ 1185 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1186 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1187 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1188 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1189 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1190 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1191 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1192 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1193 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1194 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1195 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1196 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1197 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1198 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1199 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1200 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1201 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1202 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1203 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1204 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1205 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1206 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1207 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1208 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1209 1210 /* 1211 * ISP81xx mailbox commands 1212 */ 1213 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1214 1215 /* 1216 * ISP8044 mailbox commands 1217 */ 1218 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1219 #define HCS_WRITE_SERDES 0x3 1220 #define HCS_READ_SERDES 0x4 1221 1222 /* Firmware return data sizes */ 1223 #define FCAL_MAP_SIZE 128 1224 1225 /* Mailbox bit definitions for out_mb and in_mb */ 1226 #define MBX_31 BIT_31 1227 #define MBX_30 BIT_30 1228 #define MBX_29 BIT_29 1229 #define MBX_28 BIT_28 1230 #define MBX_27 BIT_27 1231 #define MBX_26 BIT_26 1232 #define MBX_25 BIT_25 1233 #define MBX_24 BIT_24 1234 #define MBX_23 BIT_23 1235 #define MBX_22 BIT_22 1236 #define MBX_21 BIT_21 1237 #define MBX_20 BIT_20 1238 #define MBX_19 BIT_19 1239 #define MBX_18 BIT_18 1240 #define MBX_17 BIT_17 1241 #define MBX_16 BIT_16 1242 #define MBX_15 BIT_15 1243 #define MBX_14 BIT_14 1244 #define MBX_13 BIT_13 1245 #define MBX_12 BIT_12 1246 #define MBX_11 BIT_11 1247 #define MBX_10 BIT_10 1248 #define MBX_9 BIT_9 1249 #define MBX_8 BIT_8 1250 #define MBX_7 BIT_7 1251 #define MBX_6 BIT_6 1252 #define MBX_5 BIT_5 1253 #define MBX_4 BIT_4 1254 #define MBX_3 BIT_3 1255 #define MBX_2 BIT_2 1256 #define MBX_1 BIT_1 1257 #define MBX_0 BIT_0 1258 1259 #define RNID_TYPE_PORT_LOGIN 0x7 1260 #define RNID_TYPE_SET_VERSION 0x9 1261 #define RNID_TYPE_ASIC_TEMP 0xC 1262 1263 /* 1264 * Firmware state codes from get firmware state mailbox command 1265 */ 1266 #define FSTATE_CONFIG_WAIT 0 1267 #define FSTATE_WAIT_AL_PA 1 1268 #define FSTATE_WAIT_LOGIN 2 1269 #define FSTATE_READY 3 1270 #define FSTATE_LOSS_OF_SYNC 4 1271 #define FSTATE_ERROR 5 1272 #define FSTATE_REINIT 6 1273 #define FSTATE_NON_PART 7 1274 1275 #define FSTATE_CONFIG_CORRECT 0 1276 #define FSTATE_P2P_RCV_LIP 1 1277 #define FSTATE_P2P_CHOOSE_LOOP 2 1278 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1279 #define FSTATE_FATAL_ERROR 4 1280 #define FSTATE_LOOP_BACK_CONN 5 1281 1282 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1283 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1284 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1285 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1286 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1287 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED 1288 #define QLA27XX_DEFAULT_IMAGE 0 1289 #define QLA27XX_PRIMARY_IMAGE 1 1290 #define QLA27XX_SECONDARY_IMAGE 2 1291 1292 /* 1293 * Port Database structure definition 1294 * Little endian except where noted. 1295 */ 1296 #define PORT_DATABASE_SIZE 128 /* bytes */ 1297 typedef struct { 1298 uint8_t options; 1299 uint8_t control; 1300 uint8_t master_state; 1301 uint8_t slave_state; 1302 uint8_t reserved[2]; 1303 uint8_t hard_address; 1304 uint8_t reserved_1; 1305 uint8_t port_id[4]; 1306 uint8_t node_name[WWN_SIZE]; 1307 uint8_t port_name[WWN_SIZE]; 1308 uint16_t execution_throttle; 1309 uint16_t execution_count; 1310 uint8_t reset_count; 1311 uint8_t reserved_2; 1312 uint16_t resource_allocation; 1313 uint16_t current_allocation; 1314 uint16_t queue_head; 1315 uint16_t queue_tail; 1316 uint16_t transmit_execution_list_next; 1317 uint16_t transmit_execution_list_previous; 1318 uint16_t common_features; 1319 uint16_t total_concurrent_sequences; 1320 uint16_t RO_by_information_category; 1321 uint8_t recipient; 1322 uint8_t initiator; 1323 uint16_t receive_data_size; 1324 uint16_t concurrent_sequences; 1325 uint16_t open_sequences_per_exchange; 1326 uint16_t lun_abort_flags; 1327 uint16_t lun_stop_flags; 1328 uint16_t stop_queue_head; 1329 uint16_t stop_queue_tail; 1330 uint16_t port_retry_timer; 1331 uint16_t next_sequence_id; 1332 uint16_t frame_count; 1333 uint16_t PRLI_payload_length; 1334 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1335 /* Bits 15-0 of word 0 */ 1336 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1337 /* Bits 15-0 of word 3 */ 1338 uint16_t loop_id; 1339 uint16_t extended_lun_info_list_pointer; 1340 uint16_t extended_lun_stop_list_pointer; 1341 } port_database_t; 1342 1343 /* 1344 * Port database slave/master states 1345 */ 1346 #define PD_STATE_DISCOVERY 0 1347 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1348 #define PD_STATE_PORT_LOGIN 2 1349 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1350 #define PD_STATE_PROCESS_LOGIN 4 1351 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1352 #define PD_STATE_PORT_LOGGED_IN 6 1353 #define PD_STATE_PORT_UNAVAILABLE 7 1354 #define PD_STATE_PROCESS_LOGOUT 8 1355 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1356 #define PD_STATE_PORT_LOGOUT 10 1357 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1358 1359 1360 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1361 #define QLA_ZIO_DISABLED 0 1362 #define QLA_ZIO_DEFAULT_TIMER 2 1363 1364 /* 1365 * ISP Initialization Control Block. 1366 * Little endian except where noted. 1367 */ 1368 #define ICB_VERSION 1 1369 typedef struct { 1370 uint8_t version; 1371 uint8_t reserved_1; 1372 1373 /* 1374 * LSB BIT 0 = Enable Hard Loop Id 1375 * LSB BIT 1 = Enable Fairness 1376 * LSB BIT 2 = Enable Full-Duplex 1377 * LSB BIT 3 = Enable Fast Posting 1378 * LSB BIT 4 = Enable Target Mode 1379 * LSB BIT 5 = Disable Initiator Mode 1380 * LSB BIT 6 = Enable ADISC 1381 * LSB BIT 7 = Enable Target Inquiry Data 1382 * 1383 * MSB BIT 0 = Enable PDBC Notify 1384 * MSB BIT 1 = Non Participating LIP 1385 * MSB BIT 2 = Descending Loop ID Search 1386 * MSB BIT 3 = Acquire Loop ID in LIPA 1387 * MSB BIT 4 = Stop PortQ on Full Status 1388 * MSB BIT 5 = Full Login after LIP 1389 * MSB BIT 6 = Node Name Option 1390 * MSB BIT 7 = Ext IFWCB enable bit 1391 */ 1392 uint8_t firmware_options[2]; 1393 1394 uint16_t frame_payload_size; 1395 uint16_t max_iocb_allocation; 1396 uint16_t execution_throttle; 1397 uint8_t retry_count; 1398 uint8_t retry_delay; /* unused */ 1399 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1400 uint16_t hard_address; 1401 uint8_t inquiry_data; 1402 uint8_t login_timeout; 1403 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1404 1405 uint16_t request_q_outpointer; 1406 uint16_t response_q_inpointer; 1407 uint16_t request_q_length; 1408 uint16_t response_q_length; 1409 __le64 request_q_address __packed; 1410 __le64 response_q_address __packed; 1411 1412 uint16_t lun_enables; 1413 uint8_t command_resource_count; 1414 uint8_t immediate_notify_resource_count; 1415 uint16_t timeout; 1416 uint8_t reserved_2[2]; 1417 1418 /* 1419 * LSB BIT 0 = Timer Operation mode bit 0 1420 * LSB BIT 1 = Timer Operation mode bit 1 1421 * LSB BIT 2 = Timer Operation mode bit 2 1422 * LSB BIT 3 = Timer Operation mode bit 3 1423 * LSB BIT 4 = Init Config Mode bit 0 1424 * LSB BIT 5 = Init Config Mode bit 1 1425 * LSB BIT 6 = Init Config Mode bit 2 1426 * LSB BIT 7 = Enable Non part on LIHA failure 1427 * 1428 * MSB BIT 0 = Enable class 2 1429 * MSB BIT 1 = Enable ACK0 1430 * MSB BIT 2 = 1431 * MSB BIT 3 = 1432 * MSB BIT 4 = FC Tape Enable 1433 * MSB BIT 5 = Enable FC Confirm 1434 * MSB BIT 6 = Enable command queuing in target mode 1435 * MSB BIT 7 = No Logo On Link Down 1436 */ 1437 uint8_t add_firmware_options[2]; 1438 1439 uint8_t response_accumulation_timer; 1440 uint8_t interrupt_delay_timer; 1441 1442 /* 1443 * LSB BIT 0 = Enable Read xfr_rdy 1444 * LSB BIT 1 = Soft ID only 1445 * LSB BIT 2 = 1446 * LSB BIT 3 = 1447 * LSB BIT 4 = FCP RSP Payload [0] 1448 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1449 * LSB BIT 6 = Enable Out-of-Order frame handling 1450 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1451 * 1452 * MSB BIT 0 = Sbus enable - 2300 1453 * MSB BIT 1 = 1454 * MSB BIT 2 = 1455 * MSB BIT 3 = 1456 * MSB BIT 4 = LED mode 1457 * MSB BIT 5 = enable 50 ohm termination 1458 * MSB BIT 6 = Data Rate (2300 only) 1459 * MSB BIT 7 = Data Rate (2300 only) 1460 */ 1461 uint8_t special_options[2]; 1462 1463 uint8_t reserved_3[26]; 1464 } init_cb_t; 1465 1466 /* 1467 * Get Link Status mailbox command return buffer. 1468 */ 1469 #define GLSO_SEND_RPS BIT_0 1470 #define GLSO_USE_DID BIT_3 1471 1472 struct link_statistics { 1473 uint32_t link_fail_cnt; 1474 uint32_t loss_sync_cnt; 1475 uint32_t loss_sig_cnt; 1476 uint32_t prim_seq_err_cnt; 1477 uint32_t inval_xmit_word_cnt; 1478 uint32_t inval_crc_cnt; 1479 uint32_t lip_cnt; 1480 uint32_t link_up_cnt; 1481 uint32_t link_down_loop_init_tmo; 1482 uint32_t link_down_los; 1483 uint32_t link_down_loss_rcv_clk; 1484 uint32_t reserved0[5]; 1485 uint32_t port_cfg_chg; 1486 uint32_t reserved1[11]; 1487 uint32_t rsp_q_full; 1488 uint32_t atio_q_full; 1489 uint32_t drop_ae; 1490 uint32_t els_proto_err; 1491 uint32_t reserved2; 1492 uint32_t tx_frames; 1493 uint32_t rx_frames; 1494 uint32_t discarded_frames; 1495 uint32_t dropped_frames; 1496 uint32_t reserved3; 1497 uint32_t nos_rcvd; 1498 uint32_t reserved4[4]; 1499 uint32_t tx_prjt; 1500 uint32_t rcv_exfail; 1501 uint32_t rcv_abts; 1502 uint32_t seq_frm_miss; 1503 uint32_t corr_err; 1504 uint32_t mb_rqst; 1505 uint32_t nport_full; 1506 uint32_t eofa; 1507 uint32_t reserved5; 1508 uint32_t fpm_recv_word_cnt_lo; 1509 uint32_t fpm_recv_word_cnt_hi; 1510 uint32_t fpm_disc_word_cnt_lo; 1511 uint32_t fpm_disc_word_cnt_hi; 1512 uint32_t fpm_xmit_word_cnt_lo; 1513 uint32_t fpm_xmit_word_cnt_hi; 1514 uint32_t reserved6[70]; 1515 }; 1516 1517 /* 1518 * NVRAM Command values. 1519 */ 1520 #define NV_START_BIT BIT_2 1521 #define NV_WRITE_OP (BIT_26+BIT_24) 1522 #define NV_READ_OP (BIT_26+BIT_25) 1523 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1524 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1525 #define NV_DELAY_COUNT 10 1526 1527 /* 1528 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1529 */ 1530 typedef struct { 1531 /* 1532 * NVRAM header 1533 */ 1534 uint8_t id[4]; 1535 uint8_t nvram_version; 1536 uint8_t reserved_0; 1537 1538 /* 1539 * NVRAM RISC parameter block 1540 */ 1541 uint8_t parameter_block_version; 1542 uint8_t reserved_1; 1543 1544 /* 1545 * LSB BIT 0 = Enable Hard Loop Id 1546 * LSB BIT 1 = Enable Fairness 1547 * LSB BIT 2 = Enable Full-Duplex 1548 * LSB BIT 3 = Enable Fast Posting 1549 * LSB BIT 4 = Enable Target Mode 1550 * LSB BIT 5 = Disable Initiator Mode 1551 * LSB BIT 6 = Enable ADISC 1552 * LSB BIT 7 = Enable Target Inquiry Data 1553 * 1554 * MSB BIT 0 = Enable PDBC Notify 1555 * MSB BIT 1 = Non Participating LIP 1556 * MSB BIT 2 = Descending Loop ID Search 1557 * MSB BIT 3 = Acquire Loop ID in LIPA 1558 * MSB BIT 4 = Stop PortQ on Full Status 1559 * MSB BIT 5 = Full Login after LIP 1560 * MSB BIT 6 = Node Name Option 1561 * MSB BIT 7 = Ext IFWCB enable bit 1562 */ 1563 uint8_t firmware_options[2]; 1564 1565 uint16_t frame_payload_size; 1566 uint16_t max_iocb_allocation; 1567 uint16_t execution_throttle; 1568 uint8_t retry_count; 1569 uint8_t retry_delay; /* unused */ 1570 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1571 uint16_t hard_address; 1572 uint8_t inquiry_data; 1573 uint8_t login_timeout; 1574 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1575 1576 /* 1577 * LSB BIT 0 = Timer Operation mode bit 0 1578 * LSB BIT 1 = Timer Operation mode bit 1 1579 * LSB BIT 2 = Timer Operation mode bit 2 1580 * LSB BIT 3 = Timer Operation mode bit 3 1581 * LSB BIT 4 = Init Config Mode bit 0 1582 * LSB BIT 5 = Init Config Mode bit 1 1583 * LSB BIT 6 = Init Config Mode bit 2 1584 * LSB BIT 7 = Enable Non part on LIHA failure 1585 * 1586 * MSB BIT 0 = Enable class 2 1587 * MSB BIT 1 = Enable ACK0 1588 * MSB BIT 2 = 1589 * MSB BIT 3 = 1590 * MSB BIT 4 = FC Tape Enable 1591 * MSB BIT 5 = Enable FC Confirm 1592 * MSB BIT 6 = Enable command queuing in target mode 1593 * MSB BIT 7 = No Logo On Link Down 1594 */ 1595 uint8_t add_firmware_options[2]; 1596 1597 uint8_t response_accumulation_timer; 1598 uint8_t interrupt_delay_timer; 1599 1600 /* 1601 * LSB BIT 0 = Enable Read xfr_rdy 1602 * LSB BIT 1 = Soft ID only 1603 * LSB BIT 2 = 1604 * LSB BIT 3 = 1605 * LSB BIT 4 = FCP RSP Payload [0] 1606 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1607 * LSB BIT 6 = Enable Out-of-Order frame handling 1608 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1609 * 1610 * MSB BIT 0 = Sbus enable - 2300 1611 * MSB BIT 1 = 1612 * MSB BIT 2 = 1613 * MSB BIT 3 = 1614 * MSB BIT 4 = LED mode 1615 * MSB BIT 5 = enable 50 ohm termination 1616 * MSB BIT 6 = Data Rate (2300 only) 1617 * MSB BIT 7 = Data Rate (2300 only) 1618 */ 1619 uint8_t special_options[2]; 1620 1621 /* Reserved for expanded RISC parameter block */ 1622 uint8_t reserved_2[22]; 1623 1624 /* 1625 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1626 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1627 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1628 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1629 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1630 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1631 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1632 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1633 * 1634 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1635 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1636 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1637 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1638 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1639 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1640 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1641 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1642 * 1643 * LSB BIT 0 = Output Swing 1G bit 0 1644 * LSB BIT 1 = Output Swing 1G bit 1 1645 * LSB BIT 2 = Output Swing 1G bit 2 1646 * LSB BIT 3 = Output Emphasis 1G bit 0 1647 * LSB BIT 4 = Output Emphasis 1G bit 1 1648 * LSB BIT 5 = Output Swing 2G bit 0 1649 * LSB BIT 6 = Output Swing 2G bit 1 1650 * LSB BIT 7 = Output Swing 2G bit 2 1651 * 1652 * MSB BIT 0 = Output Emphasis 2G bit 0 1653 * MSB BIT 1 = Output Emphasis 2G bit 1 1654 * MSB BIT 2 = Output Enable 1655 * MSB BIT 3 = 1656 * MSB BIT 4 = 1657 * MSB BIT 5 = 1658 * MSB BIT 6 = 1659 * MSB BIT 7 = 1660 */ 1661 uint8_t seriallink_options[4]; 1662 1663 /* 1664 * NVRAM host parameter block 1665 * 1666 * LSB BIT 0 = Enable spinup delay 1667 * LSB BIT 1 = Disable BIOS 1668 * LSB BIT 2 = Enable Memory Map BIOS 1669 * LSB BIT 3 = Enable Selectable Boot 1670 * LSB BIT 4 = Disable RISC code load 1671 * LSB BIT 5 = Set cache line size 1 1672 * LSB BIT 6 = PCI Parity Disable 1673 * LSB BIT 7 = Enable extended logging 1674 * 1675 * MSB BIT 0 = Enable 64bit addressing 1676 * MSB BIT 1 = Enable lip reset 1677 * MSB BIT 2 = Enable lip full login 1678 * MSB BIT 3 = Enable target reset 1679 * MSB BIT 4 = Enable database storage 1680 * MSB BIT 5 = Enable cache flush read 1681 * MSB BIT 6 = Enable database load 1682 * MSB BIT 7 = Enable alternate WWN 1683 */ 1684 uint8_t host_p[2]; 1685 1686 uint8_t boot_node_name[WWN_SIZE]; 1687 uint8_t boot_lun_number; 1688 uint8_t reset_delay; 1689 uint8_t port_down_retry_count; 1690 uint8_t boot_id_number; 1691 uint16_t max_luns_per_target; 1692 uint8_t fcode_boot_port_name[WWN_SIZE]; 1693 uint8_t alternate_port_name[WWN_SIZE]; 1694 uint8_t alternate_node_name[WWN_SIZE]; 1695 1696 /* 1697 * BIT 0 = Selective Login 1698 * BIT 1 = Alt-Boot Enable 1699 * BIT 2 = 1700 * BIT 3 = Boot Order List 1701 * BIT 4 = 1702 * BIT 5 = Selective LUN 1703 * BIT 6 = 1704 * BIT 7 = unused 1705 */ 1706 uint8_t efi_parameters; 1707 1708 uint8_t link_down_timeout; 1709 1710 uint8_t adapter_id[16]; 1711 1712 uint8_t alt1_boot_node_name[WWN_SIZE]; 1713 uint16_t alt1_boot_lun_number; 1714 uint8_t alt2_boot_node_name[WWN_SIZE]; 1715 uint16_t alt2_boot_lun_number; 1716 uint8_t alt3_boot_node_name[WWN_SIZE]; 1717 uint16_t alt3_boot_lun_number; 1718 uint8_t alt4_boot_node_name[WWN_SIZE]; 1719 uint16_t alt4_boot_lun_number; 1720 uint8_t alt5_boot_node_name[WWN_SIZE]; 1721 uint16_t alt5_boot_lun_number; 1722 uint8_t alt6_boot_node_name[WWN_SIZE]; 1723 uint16_t alt6_boot_lun_number; 1724 uint8_t alt7_boot_node_name[WWN_SIZE]; 1725 uint16_t alt7_boot_lun_number; 1726 1727 uint8_t reserved_3[2]; 1728 1729 /* Offset 200-215 : Model Number */ 1730 uint8_t model_number[16]; 1731 1732 /* OEM related items */ 1733 uint8_t oem_specific[16]; 1734 1735 /* 1736 * NVRAM Adapter Features offset 232-239 1737 * 1738 * LSB BIT 0 = External GBIC 1739 * LSB BIT 1 = Risc RAM parity 1740 * LSB BIT 2 = Buffer Plus Module 1741 * LSB BIT 3 = Multi Chip Adapter 1742 * LSB BIT 4 = Internal connector 1743 * LSB BIT 5 = 1744 * LSB BIT 6 = 1745 * LSB BIT 7 = 1746 * 1747 * MSB BIT 0 = 1748 * MSB BIT 1 = 1749 * MSB BIT 2 = 1750 * MSB BIT 3 = 1751 * MSB BIT 4 = 1752 * MSB BIT 5 = 1753 * MSB BIT 6 = 1754 * MSB BIT 7 = 1755 */ 1756 uint8_t adapter_features[2]; 1757 1758 uint8_t reserved_4[16]; 1759 1760 /* Subsystem vendor ID for ISP2200 */ 1761 uint16_t subsystem_vendor_id_2200; 1762 1763 /* Subsystem device ID for ISP2200 */ 1764 uint16_t subsystem_device_id_2200; 1765 1766 uint8_t reserved_5; 1767 uint8_t checksum; 1768 } nvram_t; 1769 1770 /* 1771 * ISP queue - response queue entry definition. 1772 */ 1773 typedef struct { 1774 uint8_t entry_type; /* Entry type. */ 1775 uint8_t entry_count; /* Entry count. */ 1776 uint8_t sys_define; /* System defined. */ 1777 uint8_t entry_status; /* Entry Status. */ 1778 uint32_t handle; /* System defined handle */ 1779 uint8_t data[52]; 1780 uint32_t signature; 1781 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1782 } response_t; 1783 1784 /* 1785 * ISP queue - ATIO queue entry definition. 1786 */ 1787 struct atio { 1788 uint8_t entry_type; /* Entry type. */ 1789 uint8_t entry_count; /* Entry count. */ 1790 __le16 attr_n_length; 1791 uint8_t data[56]; 1792 uint32_t signature; 1793 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1794 }; 1795 1796 typedef union { 1797 uint16_t extended; 1798 struct { 1799 uint8_t reserved; 1800 uint8_t standard; 1801 } id; 1802 } target_id_t; 1803 1804 #define SET_TARGET_ID(ha, to, from) \ 1805 do { \ 1806 if (HAS_EXTENDED_IDS(ha)) \ 1807 to.extended = cpu_to_le16(from); \ 1808 else \ 1809 to.id.standard = (uint8_t)from; \ 1810 } while (0) 1811 1812 /* 1813 * ISP queue - command entry structure definition. 1814 */ 1815 #define COMMAND_TYPE 0x11 /* Command entry */ 1816 typedef struct { 1817 uint8_t entry_type; /* Entry type. */ 1818 uint8_t entry_count; /* Entry count. */ 1819 uint8_t sys_define; /* System defined. */ 1820 uint8_t entry_status; /* Entry Status. */ 1821 uint32_t handle; /* System handle. */ 1822 target_id_t target; /* SCSI ID */ 1823 uint16_t lun; /* SCSI LUN */ 1824 uint16_t control_flags; /* Control flags. */ 1825 #define CF_WRITE BIT_6 1826 #define CF_READ BIT_5 1827 #define CF_SIMPLE_TAG BIT_3 1828 #define CF_ORDERED_TAG BIT_2 1829 #define CF_HEAD_TAG BIT_1 1830 uint16_t reserved_1; 1831 uint16_t timeout; /* Command timeout. */ 1832 uint16_t dseg_count; /* Data segment count. */ 1833 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1834 uint32_t byte_count; /* Total byte count. */ 1835 union { 1836 struct dsd32 dsd32[3]; 1837 struct dsd64 dsd64[2]; 1838 }; 1839 } cmd_entry_t; 1840 1841 /* 1842 * ISP queue - 64-Bit addressing, command entry structure definition. 1843 */ 1844 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1845 typedef struct { 1846 uint8_t entry_type; /* Entry type. */ 1847 uint8_t entry_count; /* Entry count. */ 1848 uint8_t sys_define; /* System defined. */ 1849 uint8_t entry_status; /* Entry Status. */ 1850 uint32_t handle; /* System handle. */ 1851 target_id_t target; /* SCSI ID */ 1852 uint16_t lun; /* SCSI LUN */ 1853 uint16_t control_flags; /* Control flags. */ 1854 uint16_t reserved_1; 1855 uint16_t timeout; /* Command timeout. */ 1856 uint16_t dseg_count; /* Data segment count. */ 1857 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1858 uint32_t byte_count; /* Total byte count. */ 1859 struct dsd64 dsd[2]; 1860 } cmd_a64_entry_t, request_t; 1861 1862 /* 1863 * ISP queue - continuation entry structure definition. 1864 */ 1865 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1866 typedef struct { 1867 uint8_t entry_type; /* Entry type. */ 1868 uint8_t entry_count; /* Entry count. */ 1869 uint8_t sys_define; /* System defined. */ 1870 uint8_t entry_status; /* Entry Status. */ 1871 uint32_t reserved; 1872 struct dsd32 dsd[7]; 1873 } cont_entry_t; 1874 1875 /* 1876 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1877 */ 1878 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1879 typedef struct { 1880 uint8_t entry_type; /* Entry type. */ 1881 uint8_t entry_count; /* Entry count. */ 1882 uint8_t sys_define; /* System defined. */ 1883 uint8_t entry_status; /* Entry Status. */ 1884 struct dsd64 dsd[5]; 1885 } cont_a64_entry_t; 1886 1887 #define PO_MODE_DIF_INSERT 0 1888 #define PO_MODE_DIF_REMOVE 1 1889 #define PO_MODE_DIF_PASS 2 1890 #define PO_MODE_DIF_REPLACE 3 1891 #define PO_MODE_DIF_TCP_CKSUM 6 1892 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1893 #define PO_DISABLE_GUARD_CHECK BIT_4 1894 #define PO_DISABLE_INCR_REF_TAG BIT_5 1895 #define PO_DIS_HEADER_MODE BIT_7 1896 #define PO_ENABLE_DIF_BUNDLING BIT_8 1897 #define PO_DIS_FRAME_MODE BIT_9 1898 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1899 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1900 1901 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1902 #define PO_DIS_REF_TAG_REPL BIT_13 1903 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1904 #define PO_DIS_REF_TAG_VALD BIT_15 1905 1906 /* 1907 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1908 */ 1909 struct crc_context { 1910 uint32_t handle; /* System handle. */ 1911 __le32 ref_tag; 1912 __le16 app_tag; 1913 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1914 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1915 __le16 guard_seed; /* Initial Guard Seed */ 1916 __le16 prot_opts; /* Requested Data Protection Mode */ 1917 __le16 blk_size; /* Data size in bytes */ 1918 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1919 * only) */ 1920 __le32 byte_count; /* Total byte count/ total data 1921 * transfer count */ 1922 union { 1923 struct { 1924 uint32_t reserved_1; 1925 uint16_t reserved_2; 1926 uint16_t reserved_3; 1927 uint32_t reserved_4; 1928 struct dsd64 data_dsd[1]; 1929 uint32_t reserved_5[2]; 1930 uint32_t reserved_6; 1931 } nobundling; 1932 struct { 1933 __le32 dif_byte_count; /* Total DIF byte 1934 * count */ 1935 uint16_t reserved_1; 1936 __le16 dseg_count; /* Data segment count */ 1937 uint32_t reserved_2; 1938 struct dsd64 data_dsd[1]; 1939 struct dsd64 dif_dsd; 1940 } bundling; 1941 } u; 1942 1943 struct fcp_cmnd fcp_cmnd; 1944 dma_addr_t crc_ctx_dma; 1945 /* List of DMA context transfers */ 1946 struct list_head dsd_list; 1947 1948 /* List of DIF Bundling context DMA address */ 1949 struct list_head ldif_dsd_list; 1950 u8 no_ldif_dsd; 1951 1952 struct list_head ldif_dma_hndl_list; 1953 u32 dif_bundl_len; 1954 u8 no_dif_bundl; 1955 /* This structure should not exceed 512 bytes */ 1956 }; 1957 1958 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1959 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1960 1961 /* 1962 * ISP queue - status entry structure definition. 1963 */ 1964 #define STATUS_TYPE 0x03 /* Status entry. */ 1965 typedef struct { 1966 uint8_t entry_type; /* Entry type. */ 1967 uint8_t entry_count; /* Entry count. */ 1968 uint8_t sys_define; /* System defined. */ 1969 uint8_t entry_status; /* Entry Status. */ 1970 uint32_t handle; /* System handle. */ 1971 uint16_t scsi_status; /* SCSI status. */ 1972 uint16_t comp_status; /* Completion status. */ 1973 uint16_t state_flags; /* State flags. */ 1974 uint16_t status_flags; /* Status flags. */ 1975 uint16_t rsp_info_len; /* Response Info Length. */ 1976 uint16_t req_sense_length; /* Request sense data length. */ 1977 uint32_t residual_length; /* Residual transfer length. */ 1978 uint8_t rsp_info[8]; /* FCP response information. */ 1979 uint8_t req_sense_data[32]; /* Request sense data. */ 1980 } sts_entry_t; 1981 1982 /* 1983 * Status entry entry status 1984 */ 1985 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1986 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1987 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1988 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1989 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1990 #define RF_BUSY BIT_1 /* Busy */ 1991 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1992 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1993 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1994 RF_INV_E_TYPE) 1995 1996 /* 1997 * Status entry SCSI status bit definitions. 1998 */ 1999 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 2000 #define SS_RESIDUAL_UNDER BIT_11 2001 #define SS_RESIDUAL_OVER BIT_10 2002 #define SS_SENSE_LEN_VALID BIT_9 2003 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 2004 #define SS_SCSI_STATUS_BYTE 0xff 2005 2006 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 2007 #define SS_BUSY_CONDITION BIT_3 2008 #define SS_CONDITION_MET BIT_2 2009 #define SS_CHECK_CONDITION BIT_1 2010 2011 /* 2012 * Status entry completion status 2013 */ 2014 #define CS_COMPLETE 0x0 /* No errors */ 2015 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 2016 #define CS_DMA 0x2 /* A DMA direction error. */ 2017 #define CS_TRANSPORT 0x3 /* Transport error. */ 2018 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 2019 #define CS_ABORTED 0x5 /* System aborted command. */ 2020 #define CS_TIMEOUT 0x6 /* Timeout error. */ 2021 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 2022 #define CS_DIF_ERROR 0xC /* DIF error detected */ 2023 2024 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 2025 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 2026 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 2027 /* (selection timeout) */ 2028 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 2029 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 2030 #define CS_PORT_BUSY 0x2B /* Port Busy */ 2031 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 2032 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 2033 failure */ 2034 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 2035 #define CS_UNKNOWN 0x81 /* Driver defined */ 2036 #define CS_RETRY 0x82 /* Driver defined */ 2037 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 2038 2039 #define CS_BIDIR_RD_OVERRUN 0x700 2040 #define CS_BIDIR_RD_WR_OVERRUN 0x707 2041 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 2042 #define CS_BIDIR_RD_UNDERRUN 0x1500 2043 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 2044 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 2045 #define CS_BIDIR_DMA 0x200 2046 /* 2047 * Status entry status flags 2048 */ 2049 #define SF_ABTS_TERMINATED BIT_10 2050 #define SF_LOGOUT_SENT BIT_13 2051 2052 /* 2053 * ISP queue - status continuation entry structure definition. 2054 */ 2055 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 2056 typedef struct { 2057 uint8_t entry_type; /* Entry type. */ 2058 uint8_t entry_count; /* Entry count. */ 2059 uint8_t sys_define; /* System defined. */ 2060 uint8_t entry_status; /* Entry Status. */ 2061 uint8_t data[60]; /* data */ 2062 } sts_cont_entry_t; 2063 2064 /* 2065 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 2066 * structure definition. 2067 */ 2068 #define STATUS_TYPE_21 0x21 /* Status entry. */ 2069 typedef struct { 2070 uint8_t entry_type; /* Entry type. */ 2071 uint8_t entry_count; /* Entry count. */ 2072 uint8_t handle_count; /* Handle count. */ 2073 uint8_t entry_status; /* Entry Status. */ 2074 uint32_t handle[15]; /* System handles. */ 2075 } sts21_entry_t; 2076 2077 /* 2078 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 2079 * structure definition. 2080 */ 2081 #define STATUS_TYPE_22 0x22 /* Status entry. */ 2082 typedef struct { 2083 uint8_t entry_type; /* Entry type. */ 2084 uint8_t entry_count; /* Entry count. */ 2085 uint8_t handle_count; /* Handle count. */ 2086 uint8_t entry_status; /* Entry Status. */ 2087 uint16_t handle[30]; /* System handles. */ 2088 } sts22_entry_t; 2089 2090 /* 2091 * ISP queue - marker entry structure definition. 2092 */ 2093 #define MARKER_TYPE 0x04 /* Marker entry. */ 2094 typedef struct { 2095 uint8_t entry_type; /* Entry type. */ 2096 uint8_t entry_count; /* Entry count. */ 2097 uint8_t handle_count; /* Handle count. */ 2098 uint8_t entry_status; /* Entry Status. */ 2099 uint32_t sys_define_2; /* System defined. */ 2100 target_id_t target; /* SCSI ID */ 2101 uint8_t modifier; /* Modifier (7-0). */ 2102 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 2103 #define MK_SYNC_ID 1 /* Synchronize ID */ 2104 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2105 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2106 /* clear port changed, */ 2107 /* use sequence number. */ 2108 uint8_t reserved_1; 2109 uint16_t sequence_number; /* Sequence number of event */ 2110 uint16_t lun; /* SCSI LUN */ 2111 uint8_t reserved_2[48]; 2112 } mrk_entry_t; 2113 2114 /* 2115 * ISP queue - Management Server entry structure definition. 2116 */ 2117 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2118 typedef struct { 2119 uint8_t entry_type; /* Entry type. */ 2120 uint8_t entry_count; /* Entry count. */ 2121 uint8_t handle_count; /* Handle count. */ 2122 uint8_t entry_status; /* Entry Status. */ 2123 uint32_t handle1; /* System handle. */ 2124 target_id_t loop_id; 2125 uint16_t status; 2126 uint16_t control_flags; /* Control flags. */ 2127 uint16_t reserved2; 2128 uint16_t timeout; 2129 uint16_t cmd_dsd_count; 2130 uint16_t total_dsd_count; 2131 uint8_t type; 2132 uint8_t r_ctl; 2133 uint16_t rx_id; 2134 uint16_t reserved3; 2135 uint32_t handle2; 2136 uint32_t rsp_bytecount; 2137 uint32_t req_bytecount; 2138 struct dsd64 req_dsd; 2139 struct dsd64 rsp_dsd; 2140 } ms_iocb_entry_t; 2141 2142 2143 /* 2144 * ISP queue - Mailbox Command entry structure definition. 2145 */ 2146 #define MBX_IOCB_TYPE 0x39 2147 struct mbx_entry { 2148 uint8_t entry_type; 2149 uint8_t entry_count; 2150 uint8_t sys_define1; 2151 /* Use sys_define1 for source type */ 2152 #define SOURCE_SCSI 0x00 2153 #define SOURCE_IP 0x01 2154 #define SOURCE_VI 0x02 2155 #define SOURCE_SCTP 0x03 2156 #define SOURCE_MP 0x04 2157 #define SOURCE_MPIOCTL 0x05 2158 #define SOURCE_ASYNC_IOCB 0x07 2159 2160 uint8_t entry_status; 2161 2162 uint32_t handle; 2163 target_id_t loop_id; 2164 2165 uint16_t status; 2166 uint16_t state_flags; 2167 uint16_t status_flags; 2168 2169 uint32_t sys_define2[2]; 2170 2171 uint16_t mb0; 2172 uint16_t mb1; 2173 uint16_t mb2; 2174 uint16_t mb3; 2175 uint16_t mb6; 2176 uint16_t mb7; 2177 uint16_t mb9; 2178 uint16_t mb10; 2179 uint32_t reserved_2[2]; 2180 uint8_t node_name[WWN_SIZE]; 2181 uint8_t port_name[WWN_SIZE]; 2182 }; 2183 2184 #ifndef IMMED_NOTIFY_TYPE 2185 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2186 /* 2187 * ISP queue - immediate notify entry structure definition. 2188 * This is sent by the ISP to the Target driver. 2189 * This IOCB would have report of events sent by the 2190 * initiator, that needs to be handled by the target 2191 * driver immediately. 2192 */ 2193 struct imm_ntfy_from_isp { 2194 uint8_t entry_type; /* Entry type. */ 2195 uint8_t entry_count; /* Entry count. */ 2196 uint8_t sys_define; /* System defined. */ 2197 uint8_t entry_status; /* Entry Status. */ 2198 union { 2199 struct { 2200 uint32_t sys_define_2; /* System defined. */ 2201 target_id_t target; 2202 uint16_t lun; 2203 uint8_t target_id; 2204 uint8_t reserved_1; 2205 uint16_t status_modifier; 2206 uint16_t status; 2207 uint16_t task_flags; 2208 uint16_t seq_id; 2209 uint16_t srr_rx_id; 2210 uint32_t srr_rel_offs; 2211 uint16_t srr_ui; 2212 #define SRR_IU_DATA_IN 0x1 2213 #define SRR_IU_DATA_OUT 0x5 2214 #define SRR_IU_STATUS 0x7 2215 uint16_t srr_ox_id; 2216 uint8_t reserved_2[28]; 2217 } isp2x; 2218 struct { 2219 uint32_t reserved; 2220 uint16_t nport_handle; 2221 uint16_t reserved_2; 2222 uint16_t flags; 2223 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2224 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2225 uint16_t srr_rx_id; 2226 uint16_t status; 2227 uint8_t status_subcode; 2228 uint8_t fw_handle; 2229 uint32_t exchange_address; 2230 uint32_t srr_rel_offs; 2231 uint16_t srr_ui; 2232 uint16_t srr_ox_id; 2233 union { 2234 struct { 2235 uint8_t node_name[8]; 2236 } plogi; /* PLOGI/ADISC/PDISC */ 2237 struct { 2238 /* PRLI word 3 bit 0-15 */ 2239 uint16_t wd3_lo; 2240 uint8_t resv0[6]; 2241 } prli; 2242 struct { 2243 uint8_t port_id[3]; 2244 uint8_t resv1; 2245 uint16_t nport_handle; 2246 uint16_t resv2; 2247 } req_els; 2248 } u; 2249 uint8_t port_name[8]; 2250 uint8_t resv3[3]; 2251 uint8_t vp_index; 2252 uint32_t reserved_5; 2253 uint8_t port_id[3]; 2254 uint8_t reserved_6; 2255 } isp24; 2256 } u; 2257 uint16_t reserved_7; 2258 uint16_t ox_id; 2259 } __packed; 2260 #endif 2261 2262 /* 2263 * ISP request and response queue entry sizes 2264 */ 2265 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2266 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2267 2268 2269 2270 /* 2271 * Switch info gathering structure. 2272 */ 2273 typedef struct { 2274 port_id_t d_id; 2275 uint8_t node_name[WWN_SIZE]; 2276 uint8_t port_name[WWN_SIZE]; 2277 uint8_t fabric_port_name[WWN_SIZE]; 2278 uint16_t fp_speed; 2279 uint8_t fc4_type; 2280 uint8_t fc4f_nvme; /* nvme fc4 feature bits */ 2281 } sw_info_t; 2282 2283 /* FCP-4 types */ 2284 #define FC4_TYPE_FCP_SCSI 0x08 2285 #define FC4_TYPE_NVME 0x28 2286 #define FC4_TYPE_OTHER 0x0 2287 #define FC4_TYPE_UNKNOWN 0xff 2288 2289 /* mailbox command 4G & above */ 2290 struct mbx_24xx_entry { 2291 uint8_t entry_type; 2292 uint8_t entry_count; 2293 uint8_t sys_define1; 2294 uint8_t entry_status; 2295 uint32_t handle; 2296 uint16_t mb[28]; 2297 }; 2298 2299 #define IOCB_SIZE 64 2300 2301 /* 2302 * Fibre channel port type. 2303 */ 2304 typedef enum { 2305 FCT_UNKNOWN, 2306 FCT_RSCN, 2307 FCT_SWITCH, 2308 FCT_BROADCAST, 2309 FCT_INITIATOR, 2310 FCT_TARGET, 2311 FCT_NVME_INITIATOR = 0x10, 2312 FCT_NVME_TARGET = 0x20, 2313 FCT_NVME_DISCOVERY = 0x40, 2314 FCT_NVME = 0xf0, 2315 } fc_port_type_t; 2316 2317 enum qla_sess_deletion { 2318 QLA_SESS_DELETION_NONE = 0, 2319 QLA_SESS_DELETION_IN_PROGRESS, 2320 QLA_SESS_DELETED, 2321 }; 2322 2323 enum qlt_plogi_link_t { 2324 QLT_PLOGI_LINK_SAME_WWN, 2325 QLT_PLOGI_LINK_CONFLICT, 2326 QLT_PLOGI_LINK_MAX 2327 }; 2328 2329 struct qlt_plogi_ack_t { 2330 struct list_head list; 2331 struct imm_ntfy_from_isp iocb; 2332 port_id_t id; 2333 int ref_count; 2334 void *fcport; 2335 }; 2336 2337 struct ct_sns_desc { 2338 struct ct_sns_pkt *ct_sns; 2339 dma_addr_t ct_sns_dma; 2340 }; 2341 2342 enum discovery_state { 2343 DSC_DELETED, 2344 DSC_GNN_ID, 2345 DSC_GNL, 2346 DSC_LOGIN_PEND, 2347 DSC_LOGIN_FAILED, 2348 DSC_GPDB, 2349 DSC_UPD_FCPORT, 2350 DSC_LOGIN_COMPLETE, 2351 DSC_ADISC, 2352 DSC_DELETE_PEND, 2353 }; 2354 2355 enum login_state { /* FW control Target side */ 2356 DSC_LS_LLIOCB_SENT = 2, 2357 DSC_LS_PLOGI_PEND, 2358 DSC_LS_PLOGI_COMP, 2359 DSC_LS_PRLI_PEND, 2360 DSC_LS_PRLI_COMP, 2361 DSC_LS_PORT_UNAVAIL, 2362 DSC_LS_PRLO_PEND = 9, 2363 DSC_LS_LOGO_PEND, 2364 }; 2365 2366 enum rscn_addr_format { 2367 RSCN_PORT_ADDR, 2368 RSCN_AREA_ADDR, 2369 RSCN_DOM_ADDR, 2370 RSCN_FAB_ADDR, 2371 }; 2372 2373 /* 2374 * Fibre channel port structure. 2375 */ 2376 typedef struct fc_port { 2377 struct list_head list; 2378 struct scsi_qla_host *vha; 2379 2380 uint8_t node_name[WWN_SIZE]; 2381 uint8_t port_name[WWN_SIZE]; 2382 port_id_t d_id; 2383 uint16_t loop_id; 2384 uint16_t old_loop_id; 2385 2386 unsigned int conf_compl_supported:1; 2387 unsigned int deleted:2; 2388 unsigned int free_pending:1; 2389 unsigned int local:1; 2390 unsigned int logout_on_delete:1; 2391 unsigned int logo_ack_needed:1; 2392 unsigned int keep_nport_handle:1; 2393 unsigned int send_els_logo:1; 2394 unsigned int login_pause:1; 2395 unsigned int login_succ:1; 2396 unsigned int query:1; 2397 unsigned int id_changed:1; 2398 unsigned int scan_needed:1; 2399 unsigned int n2n_flag:1; 2400 2401 struct completion nvme_del_done; 2402 uint32_t nvme_prli_service_param; 2403 #define NVME_PRLI_SP_CONF BIT_7 2404 #define NVME_PRLI_SP_INITIATOR BIT_5 2405 #define NVME_PRLI_SP_TARGET BIT_4 2406 #define NVME_PRLI_SP_DISCOVERY BIT_3 2407 #define NVME_PRLI_SP_FIRST_BURST BIT_0 2408 uint8_t nvme_flag; 2409 uint32_t nvme_first_burst_size; 2410 #define NVME_FLAG_REGISTERED 4 2411 #define NVME_FLAG_DELETING 2 2412 #define NVME_FLAG_RESETTING 1 2413 2414 struct fc_port *conflict; 2415 unsigned char logout_completed; 2416 int generation; 2417 2418 struct se_session *se_sess; 2419 struct kref sess_kref; 2420 struct qla_tgt *tgt; 2421 unsigned long expires; 2422 struct list_head del_list_entry; 2423 struct work_struct free_work; 2424 struct work_struct reg_work; 2425 uint64_t jiffies_at_registration; 2426 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2427 2428 uint16_t tgt_id; 2429 uint16_t old_tgt_id; 2430 uint16_t sec_since_registration; 2431 2432 uint8_t fcp_prio; 2433 2434 uint8_t fabric_port_name[WWN_SIZE]; 2435 uint16_t fp_speed; 2436 2437 fc_port_type_t port_type; 2438 2439 atomic_t state; 2440 uint32_t flags; 2441 2442 int login_retry; 2443 2444 struct fc_rport *rport, *drport; 2445 u32 supported_classes; 2446 2447 uint8_t fc4_type; 2448 uint8_t fc4f_nvme; 2449 uint8_t scan_state; 2450 2451 unsigned long last_queue_full; 2452 unsigned long last_ramp_up; 2453 2454 uint16_t port_id; 2455 2456 struct nvme_fc_remote_port *nvme_remote_port; 2457 2458 unsigned long retry_delay_timestamp; 2459 struct qla_tgt_sess *tgt_session; 2460 struct ct_sns_desc ct_desc; 2461 enum discovery_state disc_state; 2462 enum discovery_state next_disc_state; 2463 enum login_state fw_login_state; 2464 unsigned long dm_login_expire; 2465 unsigned long plogi_nack_done_deadline; 2466 2467 u32 login_gen, last_login_gen; 2468 u32 rscn_gen, last_rscn_gen; 2469 u32 chip_reset; 2470 struct list_head gnl_entry; 2471 struct work_struct del_work; 2472 u8 iocb[IOCB_SIZE]; 2473 u8 current_login_state; 2474 u8 last_login_state; 2475 u16 n2n_link_reset_cnt; 2476 u16 n2n_chip_reset; 2477 } fc_port_t; 2478 2479 #define QLA_FCPORT_SCAN 1 2480 #define QLA_FCPORT_FOUND 2 2481 2482 struct event_arg { 2483 fc_port_t *fcport; 2484 srb_t *sp; 2485 port_id_t id; 2486 u16 data[2], rc; 2487 u8 port_name[WWN_SIZE]; 2488 u32 iop[2]; 2489 }; 2490 2491 #include "qla_mr.h" 2492 2493 /* 2494 * Fibre channel port/lun states. 2495 */ 2496 #define FCS_UNCONFIGURED 1 2497 #define FCS_DEVICE_DEAD 2 2498 #define FCS_DEVICE_LOST 3 2499 #define FCS_ONLINE 4 2500 2501 extern const char *const port_state_str[5]; 2502 2503 /* 2504 * FC port flags. 2505 */ 2506 #define FCF_FABRIC_DEVICE BIT_0 2507 #define FCF_LOGIN_NEEDED BIT_1 2508 #define FCF_FCP2_DEVICE BIT_2 2509 #define FCF_ASYNC_SENT BIT_3 2510 #define FCF_CONF_COMP_SUPPORTED BIT_4 2511 #define FCF_ASYNC_ACTIVE BIT_5 2512 2513 /* No loop ID flag. */ 2514 #define FC_NO_LOOP_ID 0x1000 2515 2516 /* 2517 * FC-CT interface 2518 * 2519 * NOTE: All structures are big-endian in form. 2520 */ 2521 2522 #define CT_REJECT_RESPONSE 0x8001 2523 #define CT_ACCEPT_RESPONSE 0x8002 2524 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2525 #define CT_REASON_CANNOT_PERFORM 0x09 2526 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2527 #define CT_EXPL_ALREADY_REGISTERED 0x10 2528 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2529 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2530 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2531 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2532 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2533 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2534 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2535 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2536 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2537 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2538 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2539 2540 #define NS_N_PORT_TYPE 0x01 2541 #define NS_NL_PORT_TYPE 0x02 2542 #define NS_NX_PORT_TYPE 0x7F 2543 2544 #define GA_NXT_CMD 0x100 2545 #define GA_NXT_REQ_SIZE (16 + 4) 2546 #define GA_NXT_RSP_SIZE (16 + 620) 2547 2548 #define GPN_FT_CMD 0x172 2549 #define GPN_FT_REQ_SIZE (16 + 4) 2550 #define GNN_FT_CMD 0x173 2551 #define GNN_FT_REQ_SIZE (16 + 4) 2552 2553 #define GID_PT_CMD 0x1A1 2554 #define GID_PT_REQ_SIZE (16 + 4) 2555 2556 #define GPN_ID_CMD 0x112 2557 #define GPN_ID_REQ_SIZE (16 + 4) 2558 #define GPN_ID_RSP_SIZE (16 + 8) 2559 2560 #define GNN_ID_CMD 0x113 2561 #define GNN_ID_REQ_SIZE (16 + 4) 2562 #define GNN_ID_RSP_SIZE (16 + 8) 2563 2564 #define GFT_ID_CMD 0x117 2565 #define GFT_ID_REQ_SIZE (16 + 4) 2566 #define GFT_ID_RSP_SIZE (16 + 32) 2567 2568 #define GID_PN_CMD 0x121 2569 #define GID_PN_REQ_SIZE (16 + 8) 2570 #define GID_PN_RSP_SIZE (16 + 4) 2571 2572 #define RFT_ID_CMD 0x217 2573 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2574 #define RFT_ID_RSP_SIZE 16 2575 2576 #define RFF_ID_CMD 0x21F 2577 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2578 #define RFF_ID_RSP_SIZE 16 2579 2580 #define RNN_ID_CMD 0x213 2581 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2582 #define RNN_ID_RSP_SIZE 16 2583 2584 #define RSNN_NN_CMD 0x239 2585 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2586 #define RSNN_NN_RSP_SIZE 16 2587 2588 #define GFPN_ID_CMD 0x11C 2589 #define GFPN_ID_REQ_SIZE (16 + 4) 2590 #define GFPN_ID_RSP_SIZE (16 + 8) 2591 2592 #define GPSC_CMD 0x127 2593 #define GPSC_REQ_SIZE (16 + 8) 2594 #define GPSC_RSP_SIZE (16 + 2 + 2) 2595 2596 #define GFF_ID_CMD 0x011F 2597 #define GFF_ID_REQ_SIZE (16 + 4) 2598 #define GFF_ID_RSP_SIZE (16 + 128) 2599 2600 /* 2601 * HBA attribute types. 2602 */ 2603 #define FDMI_HBA_ATTR_COUNT 9 2604 #define FDMIV2_HBA_ATTR_COUNT 17 2605 #define FDMI_HBA_NODE_NAME 0x1 2606 #define FDMI_HBA_MANUFACTURER 0x2 2607 #define FDMI_HBA_SERIAL_NUMBER 0x3 2608 #define FDMI_HBA_MODEL 0x4 2609 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2610 #define FDMI_HBA_HARDWARE_VERSION 0x6 2611 #define FDMI_HBA_DRIVER_VERSION 0x7 2612 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2613 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2614 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2615 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2616 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2617 #define FDMI_HBA_VENDOR_ID 0xd 2618 #define FDMI_HBA_NUM_PORTS 0xe 2619 #define FDMI_HBA_FABRIC_NAME 0xf 2620 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2621 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0 2622 2623 struct ct_fdmi_hba_attr { 2624 uint16_t type; 2625 uint16_t len; 2626 union { 2627 uint8_t node_name[WWN_SIZE]; 2628 uint8_t manufacturer[64]; 2629 uint8_t serial_num[32]; 2630 uint8_t model[16+1]; 2631 uint8_t model_desc[80]; 2632 uint8_t hw_version[32]; 2633 uint8_t driver_version[32]; 2634 uint8_t orom_version[16]; 2635 uint8_t fw_version[32]; 2636 uint8_t os_version[128]; 2637 uint32_t max_ct_len; 2638 } a; 2639 }; 2640 2641 struct ct_fdmi_hba_attributes { 2642 uint32_t count; 2643 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2644 }; 2645 2646 struct ct_fdmiv2_hba_attr { 2647 uint16_t type; 2648 uint16_t len; 2649 union { 2650 uint8_t node_name[WWN_SIZE]; 2651 uint8_t manufacturer[64]; 2652 uint8_t serial_num[32]; 2653 uint8_t model[16+1]; 2654 uint8_t model_desc[80]; 2655 uint8_t hw_version[16]; 2656 uint8_t driver_version[32]; 2657 uint8_t orom_version[16]; 2658 uint8_t fw_version[32]; 2659 uint8_t os_version[128]; 2660 uint32_t max_ct_len; 2661 uint8_t sym_name[256]; 2662 uint32_t vendor_id; 2663 uint32_t num_ports; 2664 uint8_t fabric_name[WWN_SIZE]; 2665 uint8_t bios_name[32]; 2666 uint8_t vendor_identifier[8]; 2667 } a; 2668 }; 2669 2670 struct ct_fdmiv2_hba_attributes { 2671 uint32_t count; 2672 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT]; 2673 }; 2674 2675 /* 2676 * Port attribute types. 2677 */ 2678 #define FDMI_PORT_ATTR_COUNT 6 2679 #define FDMIV2_PORT_ATTR_COUNT 16 2680 #define FDMI_PORT_FC4_TYPES 0x1 2681 #define FDMI_PORT_SUPPORT_SPEED 0x2 2682 #define FDMI_PORT_CURRENT_SPEED 0x3 2683 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2684 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2685 #define FDMI_PORT_HOST_NAME 0x6 2686 #define FDMI_PORT_NODE_NAME 0x7 2687 #define FDMI_PORT_NAME 0x8 2688 #define FDMI_PORT_SYM_NAME 0x9 2689 #define FDMI_PORT_TYPE 0xa 2690 #define FDMI_PORT_SUPP_COS 0xb 2691 #define FDMI_PORT_FABRIC_NAME 0xc 2692 #define FDMI_PORT_FC4_TYPE 0xd 2693 #define FDMI_PORT_STATE 0x101 2694 #define FDMI_PORT_COUNT 0x102 2695 #define FDMI_PORT_ID 0x103 2696 2697 #define FDMI_PORT_SPEED_1GB 0x1 2698 #define FDMI_PORT_SPEED_2GB 0x2 2699 #define FDMI_PORT_SPEED_10GB 0x4 2700 #define FDMI_PORT_SPEED_4GB 0x8 2701 #define FDMI_PORT_SPEED_8GB 0x10 2702 #define FDMI_PORT_SPEED_16GB 0x20 2703 #define FDMI_PORT_SPEED_32GB 0x40 2704 #define FDMI_PORT_SPEED_64GB 0x80 2705 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2706 2707 #define FC_CLASS_2 0x04 2708 #define FC_CLASS_3 0x08 2709 #define FC_CLASS_2_3 0x0C 2710 2711 struct ct_fdmiv2_port_attr { 2712 uint16_t type; 2713 uint16_t len; 2714 union { 2715 uint8_t fc4_types[32]; 2716 uint32_t sup_speed; 2717 uint32_t cur_speed; 2718 uint32_t max_frame_size; 2719 uint8_t os_dev_name[32]; 2720 uint8_t host_name[256]; 2721 uint8_t node_name[WWN_SIZE]; 2722 uint8_t port_name[WWN_SIZE]; 2723 uint8_t port_sym_name[128]; 2724 uint32_t port_type; 2725 uint32_t port_supported_cos; 2726 uint8_t fabric_name[WWN_SIZE]; 2727 uint8_t port_fc4_type[32]; 2728 uint32_t port_state; 2729 uint32_t num_ports; 2730 uint32_t port_id; 2731 } a; 2732 }; 2733 2734 /* 2735 * Port Attribute Block. 2736 */ 2737 struct ct_fdmiv2_port_attributes { 2738 uint32_t count; 2739 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT]; 2740 }; 2741 2742 struct ct_fdmi_port_attr { 2743 uint16_t type; 2744 uint16_t len; 2745 union { 2746 uint8_t fc4_types[32]; 2747 uint32_t sup_speed; 2748 uint32_t cur_speed; 2749 uint32_t max_frame_size; 2750 uint8_t os_dev_name[32]; 2751 uint8_t host_name[256]; 2752 } a; 2753 }; 2754 2755 struct ct_fdmi_port_attributes { 2756 uint32_t count; 2757 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2758 }; 2759 2760 /* FDMI definitions. */ 2761 #define GRHL_CMD 0x100 2762 #define GHAT_CMD 0x101 2763 #define GRPL_CMD 0x102 2764 #define GPAT_CMD 0x110 2765 2766 #define RHBA_CMD 0x200 2767 #define RHBA_RSP_SIZE 16 2768 2769 #define RHAT_CMD 0x201 2770 #define RPRT_CMD 0x210 2771 2772 #define RPA_CMD 0x211 2773 #define RPA_RSP_SIZE 16 2774 2775 #define DHBA_CMD 0x300 2776 #define DHBA_REQ_SIZE (16 + 8) 2777 #define DHBA_RSP_SIZE 16 2778 2779 #define DHAT_CMD 0x301 2780 #define DPRT_CMD 0x310 2781 #define DPA_CMD 0x311 2782 2783 /* CT command header -- request/response common fields */ 2784 struct ct_cmd_hdr { 2785 uint8_t revision; 2786 uint8_t in_id[3]; 2787 uint8_t gs_type; 2788 uint8_t gs_subtype; 2789 uint8_t options; 2790 uint8_t reserved; 2791 }; 2792 2793 /* CT command request */ 2794 struct ct_sns_req { 2795 struct ct_cmd_hdr header; 2796 uint16_t command; 2797 uint16_t max_rsp_size; 2798 uint8_t fragment_id; 2799 uint8_t reserved[3]; 2800 2801 union { 2802 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2803 struct { 2804 uint8_t reserved; 2805 be_id_t port_id; 2806 } port_id; 2807 2808 struct { 2809 uint8_t reserved; 2810 uint8_t domain; 2811 uint8_t area; 2812 uint8_t port_type; 2813 } gpn_ft; 2814 2815 struct { 2816 uint8_t port_type; 2817 uint8_t domain; 2818 uint8_t area; 2819 uint8_t reserved; 2820 } gid_pt; 2821 2822 struct { 2823 uint8_t reserved; 2824 be_id_t port_id; 2825 uint8_t fc4_types[32]; 2826 } rft_id; 2827 2828 struct { 2829 uint8_t reserved; 2830 be_id_t port_id; 2831 uint16_t reserved2; 2832 uint8_t fc4_feature; 2833 uint8_t fc4_type; 2834 } rff_id; 2835 2836 struct { 2837 uint8_t reserved; 2838 be_id_t port_id; 2839 uint8_t node_name[8]; 2840 } rnn_id; 2841 2842 struct { 2843 uint8_t node_name[8]; 2844 uint8_t name_len; 2845 uint8_t sym_node_name[255]; 2846 } rsnn_nn; 2847 2848 struct { 2849 uint8_t hba_identifier[8]; 2850 } ghat; 2851 2852 struct { 2853 uint8_t hba_identifier[8]; 2854 uint32_t entry_count; 2855 uint8_t port_name[8]; 2856 struct ct_fdmi_hba_attributes attrs; 2857 } rhba; 2858 2859 struct { 2860 uint8_t hba_identifier[8]; 2861 uint32_t entry_count; 2862 uint8_t port_name[8]; 2863 struct ct_fdmiv2_hba_attributes attrs; 2864 } rhba2; 2865 2866 struct { 2867 uint8_t hba_identifier[8]; 2868 struct ct_fdmi_hba_attributes attrs; 2869 } rhat; 2870 2871 struct { 2872 uint8_t port_name[8]; 2873 struct ct_fdmi_port_attributes attrs; 2874 } rpa; 2875 2876 struct { 2877 uint8_t port_name[8]; 2878 struct ct_fdmiv2_port_attributes attrs; 2879 } rpa2; 2880 2881 struct { 2882 uint8_t port_name[8]; 2883 } dhba; 2884 2885 struct { 2886 uint8_t port_name[8]; 2887 } dhat; 2888 2889 struct { 2890 uint8_t port_name[8]; 2891 } dprt; 2892 2893 struct { 2894 uint8_t port_name[8]; 2895 } dpa; 2896 2897 struct { 2898 uint8_t port_name[8]; 2899 } gpsc; 2900 2901 struct { 2902 uint8_t reserved; 2903 uint8_t port_id[3]; 2904 } gff_id; 2905 2906 struct { 2907 uint8_t port_name[8]; 2908 } gid_pn; 2909 } req; 2910 }; 2911 2912 /* CT command response header */ 2913 struct ct_rsp_hdr { 2914 struct ct_cmd_hdr header; 2915 uint16_t response; 2916 uint16_t residual; 2917 uint8_t fragment_id; 2918 uint8_t reason_code; 2919 uint8_t explanation_code; 2920 uint8_t vendor_unique; 2921 }; 2922 2923 struct ct_sns_gid_pt_data { 2924 uint8_t control_byte; 2925 be_id_t port_id; 2926 }; 2927 2928 /* It's the same for both GPN_FT and GNN_FT */ 2929 struct ct_sns_gpnft_rsp { 2930 struct { 2931 struct ct_cmd_hdr header; 2932 uint16_t response; 2933 uint16_t residual; 2934 uint8_t fragment_id; 2935 uint8_t reason_code; 2936 uint8_t explanation_code; 2937 uint8_t vendor_unique; 2938 }; 2939 /* Assume the largest number of targets for the union */ 2940 struct ct_sns_gpn_ft_data { 2941 u8 control_byte; 2942 u8 port_id[3]; 2943 u32 reserved; 2944 u8 port_name[8]; 2945 } entries[1]; 2946 }; 2947 2948 /* CT command response */ 2949 struct ct_sns_rsp { 2950 struct ct_rsp_hdr header; 2951 2952 union { 2953 struct { 2954 uint8_t port_type; 2955 be_id_t port_id; 2956 uint8_t port_name[8]; 2957 uint8_t sym_port_name_len; 2958 uint8_t sym_port_name[255]; 2959 uint8_t node_name[8]; 2960 uint8_t sym_node_name_len; 2961 uint8_t sym_node_name[255]; 2962 uint8_t init_proc_assoc[8]; 2963 uint8_t node_ip_addr[16]; 2964 uint8_t class_of_service[4]; 2965 uint8_t fc4_types[32]; 2966 uint8_t ip_address[16]; 2967 uint8_t fabric_port_name[8]; 2968 uint8_t reserved; 2969 uint8_t hard_address[3]; 2970 } ga_nxt; 2971 2972 struct { 2973 /* Assume the largest number of targets for the union */ 2974 struct ct_sns_gid_pt_data 2975 entries[MAX_FIBRE_DEVICES_MAX]; 2976 } gid_pt; 2977 2978 struct { 2979 uint8_t port_name[8]; 2980 } gpn_id; 2981 2982 struct { 2983 uint8_t node_name[8]; 2984 } gnn_id; 2985 2986 struct { 2987 uint8_t fc4_types[32]; 2988 } gft_id; 2989 2990 struct { 2991 uint32_t entry_count; 2992 uint8_t port_name[8]; 2993 struct ct_fdmi_hba_attributes attrs; 2994 } ghat; 2995 2996 struct { 2997 uint8_t port_name[8]; 2998 } gfpn_id; 2999 3000 struct { 3001 uint16_t speeds; 3002 uint16_t speed; 3003 } gpsc; 3004 3005 #define GFF_FCP_SCSI_OFFSET 7 3006 #define GFF_NVME_OFFSET 23 /* type = 28h */ 3007 struct { 3008 uint8_t fc4_features[128]; 3009 } gff_id; 3010 struct { 3011 uint8_t reserved; 3012 uint8_t port_id[3]; 3013 } gid_pn; 3014 } rsp; 3015 }; 3016 3017 struct ct_sns_pkt { 3018 union { 3019 struct ct_sns_req req; 3020 struct ct_sns_rsp rsp; 3021 } p; 3022 }; 3023 3024 struct ct_sns_gpnft_pkt { 3025 union { 3026 struct ct_sns_req req; 3027 struct ct_sns_gpnft_rsp rsp; 3028 } p; 3029 }; 3030 3031 enum scan_flags_t { 3032 SF_SCANNING = BIT_0, 3033 SF_QUEUED = BIT_1, 3034 }; 3035 3036 enum fc4type_t { 3037 FS_FC4TYPE_FCP = BIT_0, 3038 FS_FC4TYPE_NVME = BIT_1, 3039 FS_FCP_IS_N2N = BIT_7, 3040 }; 3041 3042 struct fab_scan_rp { 3043 port_id_t id; 3044 enum fc4type_t fc4type; 3045 u8 port_name[8]; 3046 u8 node_name[8]; 3047 }; 3048 3049 struct fab_scan { 3050 struct fab_scan_rp *l; 3051 u32 size; 3052 u16 scan_retry; 3053 #define MAX_SCAN_RETRIES 5 3054 enum scan_flags_t scan_flags; 3055 struct delayed_work scan_work; 3056 }; 3057 3058 /* 3059 * SNS command structures -- for 2200 compatibility. 3060 */ 3061 #define RFT_ID_SNS_SCMD_LEN 22 3062 #define RFT_ID_SNS_CMD_SIZE 60 3063 #define RFT_ID_SNS_DATA_SIZE 16 3064 3065 #define RNN_ID_SNS_SCMD_LEN 10 3066 #define RNN_ID_SNS_CMD_SIZE 36 3067 #define RNN_ID_SNS_DATA_SIZE 16 3068 3069 #define GA_NXT_SNS_SCMD_LEN 6 3070 #define GA_NXT_SNS_CMD_SIZE 28 3071 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 3072 3073 #define GID_PT_SNS_SCMD_LEN 6 3074 #define GID_PT_SNS_CMD_SIZE 28 3075 /* 3076 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 3077 * adapters. 3078 */ 3079 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 3080 3081 #define GPN_ID_SNS_SCMD_LEN 6 3082 #define GPN_ID_SNS_CMD_SIZE 28 3083 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 3084 3085 #define GNN_ID_SNS_SCMD_LEN 6 3086 #define GNN_ID_SNS_CMD_SIZE 28 3087 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 3088 3089 struct sns_cmd_pkt { 3090 union { 3091 struct { 3092 uint16_t buffer_length; 3093 uint16_t reserved_1; 3094 __le64 buffer_address __packed; 3095 uint16_t subcommand_length; 3096 uint16_t reserved_2; 3097 uint16_t subcommand; 3098 uint16_t size; 3099 uint32_t reserved_3; 3100 uint8_t param[36]; 3101 } cmd; 3102 3103 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 3104 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 3105 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 3106 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 3107 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 3108 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 3109 } p; 3110 }; 3111 3112 struct fw_blob { 3113 char *name; 3114 uint32_t segs[4]; 3115 const struct firmware *fw; 3116 }; 3117 3118 /* Return data from MBC_GET_ID_LIST call. */ 3119 struct gid_list_info { 3120 uint8_t al_pa; 3121 uint8_t area; 3122 uint8_t domain; 3123 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 3124 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 3125 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 3126 }; 3127 3128 /* NPIV */ 3129 typedef struct vport_info { 3130 uint8_t port_name[WWN_SIZE]; 3131 uint8_t node_name[WWN_SIZE]; 3132 int vp_id; 3133 uint16_t loop_id; 3134 unsigned long host_no; 3135 uint8_t port_id[3]; 3136 int loop_state; 3137 } vport_info_t; 3138 3139 typedef struct vport_params { 3140 uint8_t port_name[WWN_SIZE]; 3141 uint8_t node_name[WWN_SIZE]; 3142 uint32_t options; 3143 #define VP_OPTS_RETRY_ENABLE BIT_0 3144 #define VP_OPTS_VP_DISABLE BIT_1 3145 } vport_params_t; 3146 3147 /* NPIV - return codes of VP create and modify */ 3148 #define VP_RET_CODE_OK 0 3149 #define VP_RET_CODE_FATAL 1 3150 #define VP_RET_CODE_WRONG_ID 2 3151 #define VP_RET_CODE_WWPN 3 3152 #define VP_RET_CODE_RESOURCES 4 3153 #define VP_RET_CODE_NO_MEM 5 3154 #define VP_RET_CODE_NOT_FOUND 6 3155 3156 struct qla_hw_data; 3157 struct rsp_que; 3158 /* 3159 * ISP operations 3160 */ 3161 struct isp_operations { 3162 3163 int (*pci_config) (struct scsi_qla_host *); 3164 int (*reset_chip)(struct scsi_qla_host *); 3165 int (*chip_diag) (struct scsi_qla_host *); 3166 void (*config_rings) (struct scsi_qla_host *); 3167 int (*reset_adapter)(struct scsi_qla_host *); 3168 int (*nvram_config) (struct scsi_qla_host *); 3169 void (*update_fw_options) (struct scsi_qla_host *); 3170 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3171 3172 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t); 3173 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3174 3175 irq_handler_t intr_handler; 3176 void (*enable_intrs) (struct qla_hw_data *); 3177 void (*disable_intrs) (struct qla_hw_data *); 3178 3179 int (*abort_command) (srb_t *); 3180 int (*target_reset) (struct fc_port *, uint64_t, int); 3181 int (*lun_reset) (struct fc_port *, uint64_t, int); 3182 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3183 uint8_t, uint8_t, uint16_t *, uint8_t); 3184 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3185 uint8_t, uint8_t); 3186 3187 uint16_t (*calc_req_entries) (uint16_t); 3188 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3189 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3190 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3191 uint32_t); 3192 3193 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *, 3194 uint32_t, uint32_t); 3195 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t, 3196 uint32_t); 3197 3198 void (*fw_dump) (struct scsi_qla_host *, int); 3199 3200 int (*beacon_on) (struct scsi_qla_host *); 3201 int (*beacon_off) (struct scsi_qla_host *); 3202 void (*beacon_blink) (struct scsi_qla_host *); 3203 3204 void *(*read_optrom)(struct scsi_qla_host *, void *, 3205 uint32_t, uint32_t); 3206 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t, 3207 uint32_t); 3208 3209 int (*get_flash_version) (struct scsi_qla_host *, void *); 3210 int (*start_scsi) (srb_t *); 3211 int (*start_scsi_mq) (srb_t *); 3212 int (*abort_isp) (struct scsi_qla_host *); 3213 int (*iospace_config)(struct qla_hw_data *); 3214 int (*initialize_adapter)(struct scsi_qla_host *); 3215 }; 3216 3217 /* MSI-X Support *************************************************************/ 3218 3219 #define QLA_MSIX_CHIP_REV_24XX 3 3220 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3221 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3222 3223 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3224 #define QLA_MSIX_RSP_Q 0x01 3225 #define QLA_ATIO_VECTOR 0x02 3226 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3227 3228 #define QLA_MIDX_DEFAULT 0 3229 #define QLA_MIDX_RSP_Q 1 3230 #define QLA_PCI_MSIX_CONTROL 0xa2 3231 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3232 3233 struct scsi_qla_host; 3234 3235 3236 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3237 3238 struct qla_msix_entry { 3239 int have_irq; 3240 int in_use; 3241 uint32_t vector; 3242 uint16_t entry; 3243 char name[30]; 3244 void *handle; 3245 int cpuid; 3246 }; 3247 3248 #define WATCH_INTERVAL 1 /* number of seconds */ 3249 3250 /* Work events. */ 3251 enum qla_work_type { 3252 QLA_EVT_AEN, 3253 QLA_EVT_IDC_ACK, 3254 QLA_EVT_ASYNC_LOGIN, 3255 QLA_EVT_ASYNC_LOGOUT, 3256 QLA_EVT_ASYNC_LOGOUT_DONE, 3257 QLA_EVT_ASYNC_ADISC, 3258 QLA_EVT_UEVENT, 3259 QLA_EVT_AENFX, 3260 QLA_EVT_GPNID, 3261 QLA_EVT_UNMAP, 3262 QLA_EVT_NEW_SESS, 3263 QLA_EVT_GPDB, 3264 QLA_EVT_PRLI, 3265 QLA_EVT_GPSC, 3266 QLA_EVT_GNL, 3267 QLA_EVT_NACK, 3268 QLA_EVT_RELOGIN, 3269 QLA_EVT_ASYNC_PRLO, 3270 QLA_EVT_ASYNC_PRLO_DONE, 3271 QLA_EVT_GPNFT, 3272 QLA_EVT_GPNFT_DONE, 3273 QLA_EVT_GNNFT_DONE, 3274 QLA_EVT_GNNID, 3275 QLA_EVT_GFPNID, 3276 QLA_EVT_SP_RETRY, 3277 QLA_EVT_IIDMA, 3278 QLA_EVT_ELS_PLOGI, 3279 }; 3280 3281 3282 struct qla_work_evt { 3283 struct list_head list; 3284 enum qla_work_type type; 3285 u32 flags; 3286 #define QLA_EVT_FLAG_FREE 0x1 3287 3288 union { 3289 struct { 3290 enum fc_host_event_code code; 3291 u32 data; 3292 } aen; 3293 struct { 3294 #define QLA_IDC_ACK_REGS 7 3295 uint16_t mb[QLA_IDC_ACK_REGS]; 3296 } idc_ack; 3297 struct { 3298 struct fc_port *fcport; 3299 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3300 u16 data[2]; 3301 } logio; 3302 struct { 3303 u32 code; 3304 #define QLA_UEVENT_CODE_FW_DUMP 0 3305 } uevent; 3306 struct { 3307 uint32_t evtcode; 3308 uint32_t mbx[8]; 3309 uint32_t count; 3310 } aenfx; 3311 struct { 3312 srb_t *sp; 3313 } iosb; 3314 struct { 3315 port_id_t id; 3316 } gpnid; 3317 struct { 3318 port_id_t id; 3319 u8 port_name[8]; 3320 u8 node_name[8]; 3321 void *pla; 3322 u8 fc4_type; 3323 } new_sess; 3324 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */ 3325 fc_port_t *fcport; 3326 u8 opt; 3327 } fcport; 3328 struct { 3329 fc_port_t *fcport; 3330 u8 iocb[IOCB_SIZE]; 3331 int type; 3332 } nack; 3333 struct { 3334 u8 fc4_type; 3335 srb_t *sp; 3336 } gpnft; 3337 } u; 3338 }; 3339 3340 struct qla_chip_state_84xx { 3341 struct list_head list; 3342 struct kref kref; 3343 3344 void *bus; 3345 spinlock_t access_lock; 3346 struct mutex fw_update_mutex; 3347 uint32_t fw_update; 3348 uint32_t op_fw_version; 3349 uint32_t op_fw_size; 3350 uint32_t op_fw_seq_size; 3351 uint32_t diag_fw_version; 3352 uint32_t gold_fw_version; 3353 }; 3354 3355 struct qla_dif_statistics { 3356 uint64_t dif_input_bytes; 3357 uint64_t dif_output_bytes; 3358 uint64_t dif_input_requests; 3359 uint64_t dif_output_requests; 3360 uint32_t dif_guard_err; 3361 uint32_t dif_ref_tag_err; 3362 uint32_t dif_app_tag_err; 3363 }; 3364 3365 struct qla_statistics { 3366 uint32_t total_isp_aborts; 3367 uint64_t input_bytes; 3368 uint64_t output_bytes; 3369 uint64_t input_requests; 3370 uint64_t output_requests; 3371 uint32_t control_requests; 3372 3373 uint64_t jiffies_at_last_reset; 3374 uint32_t stat_max_pend_cmds; 3375 uint32_t stat_max_qfull_cmds_alloc; 3376 uint32_t stat_max_qfull_cmds_dropped; 3377 3378 struct qla_dif_statistics qla_dif_stats; 3379 }; 3380 3381 struct bidi_statistics { 3382 unsigned long long io_count; 3383 unsigned long long transfer_bytes; 3384 }; 3385 3386 struct qla_tc_param { 3387 struct scsi_qla_host *vha; 3388 uint32_t blk_sz; 3389 uint32_t bufflen; 3390 struct scatterlist *sg; 3391 struct scatterlist *prot_sg; 3392 struct crc_context *ctx; 3393 uint8_t *ctx_dsd_alloced; 3394 }; 3395 3396 /* Multi queue support */ 3397 #define MBC_INITIALIZE_MULTIQ 0x1f 3398 #define QLA_QUE_PAGE 0X1000 3399 #define QLA_MQ_SIZE 32 3400 #define QLA_MAX_QUEUES 256 3401 #define ISP_QUE_REG(ha, id) \ 3402 ((ha->mqenable || IS_QLA83XX(ha) || \ 3403 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \ 3404 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3405 ((void __iomem *)ha->iobase)) 3406 #define QLA_REQ_QUE_ID(tag) \ 3407 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3408 #define QLA_DEFAULT_QUE_QOS 5 3409 #define QLA_PRECONFIG_VPORTS 32 3410 #define QLA_MAX_VPORTS_QLA24XX 128 3411 #define QLA_MAX_VPORTS_QLA25XX 256 3412 3413 struct qla_tgt_counters { 3414 uint64_t qla_core_sbt_cmd; 3415 uint64_t core_qla_que_buf; 3416 uint64_t qla_core_ret_ctio; 3417 uint64_t core_qla_snd_status; 3418 uint64_t qla_core_ret_sta_ctio; 3419 uint64_t core_qla_free_cmd; 3420 uint64_t num_q_full_sent; 3421 uint64_t num_alloc_iocb_failed; 3422 uint64_t num_term_xchg_sent; 3423 }; 3424 3425 struct qla_qpair; 3426 3427 /* Response queue data structure */ 3428 struct rsp_que { 3429 dma_addr_t dma; 3430 response_t *ring; 3431 response_t *ring_ptr; 3432 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 3433 uint32_t __iomem *rsp_q_out; 3434 uint16_t ring_index; 3435 uint16_t out_ptr; 3436 uint16_t *in_ptr; /* queue shadow in index */ 3437 uint16_t length; 3438 uint16_t options; 3439 uint16_t rid; 3440 uint16_t id; 3441 uint16_t vp_idx; 3442 struct qla_hw_data *hw; 3443 struct qla_msix_entry *msix; 3444 struct req_que *req; 3445 srb_t *status_srb; /* status continuation entry */ 3446 struct qla_qpair *qpair; 3447 3448 dma_addr_t dma_fx00; 3449 response_t *ring_fx00; 3450 uint16_t length_fx00; 3451 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3452 }; 3453 3454 /* Request queue data structure */ 3455 struct req_que { 3456 dma_addr_t dma; 3457 request_t *ring; 3458 request_t *ring_ptr; 3459 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 3460 uint32_t __iomem *req_q_out; 3461 uint16_t ring_index; 3462 uint16_t in_ptr; 3463 uint16_t *out_ptr; /* queue shadow out index */ 3464 uint16_t cnt; 3465 uint16_t length; 3466 uint16_t options; 3467 uint16_t rid; 3468 uint16_t id; 3469 uint16_t qos; 3470 uint16_t vp_idx; 3471 struct rsp_que *rsp; 3472 srb_t **outstanding_cmds; 3473 uint32_t current_outstanding_cmd; 3474 uint16_t num_outstanding_cmds; 3475 int max_q_depth; 3476 3477 dma_addr_t dma_fx00; 3478 request_t *ring_fx00; 3479 uint16_t length_fx00; 3480 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3481 }; 3482 3483 /*Queue pair data structure */ 3484 struct qla_qpair { 3485 spinlock_t qp_lock; 3486 atomic_t ref_count; 3487 uint32_t lun_cnt; 3488 /* 3489 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3490 * legacy code. For other Qpair(s), it will point at qp_lock. 3491 */ 3492 spinlock_t *qp_lock_ptr; 3493 struct scsi_qla_host *vha; 3494 u32 chip_reset; 3495 3496 /* distill these fields down to 'online=0/1' 3497 * ha->flags.eeh_busy 3498 * ha->flags.pci_channel_io_perm_failure 3499 * base_vha->loop_state 3500 */ 3501 uint32_t online:1; 3502 /* move vha->flags.difdix_supported here */ 3503 uint32_t difdix_supported:1; 3504 uint32_t delete_in_progress:1; 3505 uint32_t fw_started:1; 3506 uint32_t enable_class_2:1; 3507 uint32_t enable_explicit_conf:1; 3508 uint32_t use_shadow_reg:1; 3509 3510 uint16_t id; /* qp number used with FW */ 3511 uint16_t vp_idx; /* vport ID */ 3512 mempool_t *srb_mempool; 3513 3514 struct pci_dev *pdev; 3515 void (*reqq_start_iocbs)(struct qla_qpair *); 3516 3517 /* to do: New driver: move queues to here instead of pointers */ 3518 struct req_que *req; 3519 struct rsp_que *rsp; 3520 struct atio_que *atio; 3521 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3522 struct qla_hw_data *hw; 3523 struct work_struct q_work; 3524 struct list_head qp_list_elem; /* vha->qp_list */ 3525 struct list_head hints_list; 3526 uint16_t cpuid; 3527 uint16_t retry_term_cnt; 3528 uint32_t retry_term_exchg_addr; 3529 uint64_t retry_term_jiff; 3530 struct qla_tgt_counters tgt_counters; 3531 }; 3532 3533 /* Place holder for FW buffer parameters */ 3534 struct qlfc_fw { 3535 void *fw_buf; 3536 dma_addr_t fw_dma; 3537 uint32_t len; 3538 }; 3539 3540 struct scsi_qlt_host { 3541 void *target_lport_ptr; 3542 struct mutex tgt_mutex; 3543 struct mutex tgt_host_action_mutex; 3544 struct qla_tgt *qla_tgt; 3545 }; 3546 3547 struct qlt_hw_data { 3548 /* Protected by hw lock */ 3549 uint32_t node_name_set:1; 3550 3551 dma_addr_t atio_dma; /* Physical address. */ 3552 struct atio *atio_ring; /* Base virtual address */ 3553 struct atio *atio_ring_ptr; /* Current address. */ 3554 uint16_t atio_ring_index; /* Current index. */ 3555 uint16_t atio_q_length; 3556 uint32_t __iomem *atio_q_in; 3557 uint32_t __iomem *atio_q_out; 3558 3559 struct qla_tgt_func_tmpl *tgt_ops; 3560 struct qla_tgt_vp_map *tgt_vp_map; 3561 3562 int saved_set; 3563 uint16_t saved_exchange_count; 3564 uint32_t saved_firmware_options_1; 3565 uint32_t saved_firmware_options_2; 3566 uint32_t saved_firmware_options_3; 3567 uint8_t saved_firmware_options[2]; 3568 uint8_t saved_add_firmware_options[2]; 3569 3570 uint8_t tgt_node_name[WWN_SIZE]; 3571 3572 struct dentry *dfs_tgt_sess; 3573 struct dentry *dfs_tgt_port_database; 3574 struct dentry *dfs_naqp; 3575 3576 struct list_head q_full_list; 3577 uint32_t num_pend_cmds; 3578 uint32_t num_qfull_cmds_alloc; 3579 uint32_t num_qfull_cmds_dropped; 3580 spinlock_t q_full_lock; 3581 uint32_t leak_exchg_thresh_hold; 3582 spinlock_t sess_lock; 3583 int num_act_qpairs; 3584 #define DEFAULT_NAQP 2 3585 spinlock_t atio_lock ____cacheline_aligned; 3586 struct btree_head32 host_map; 3587 }; 3588 3589 #define MAX_QFULL_CMDS_ALLOC 8192 3590 #define Q_FULL_THRESH_HOLD_PERCENT 90 3591 #define Q_FULL_THRESH_HOLD(ha) \ 3592 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3593 3594 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3595 3596 /* 3597 * Qlogic host adapter specific data structure. 3598 */ 3599 struct qla_hw_data { 3600 struct pci_dev *pdev; 3601 /* SRB cache. */ 3602 #define SRB_MIN_REQ 128 3603 mempool_t *srb_mempool; 3604 3605 volatile struct { 3606 uint32_t mbox_int :1; 3607 uint32_t mbox_busy :1; 3608 uint32_t disable_risc_code_load :1; 3609 uint32_t enable_64bit_addressing :1; 3610 uint32_t enable_lip_reset :1; 3611 uint32_t enable_target_reset :1; 3612 uint32_t enable_lip_full_login :1; 3613 uint32_t enable_led_scheme :1; 3614 3615 uint32_t msi_enabled :1; 3616 uint32_t msix_enabled :1; 3617 uint32_t disable_serdes :1; 3618 uint32_t gpsc_supported :1; 3619 uint32_t npiv_supported :1; 3620 uint32_t pci_channel_io_perm_failure :1; 3621 uint32_t fce_enabled :1; 3622 uint32_t fac_supported :1; 3623 3624 uint32_t chip_reset_done :1; 3625 uint32_t running_gold_fw :1; 3626 uint32_t eeh_busy :1; 3627 uint32_t disable_msix_handshake :1; 3628 uint32_t fcp_prio_enabled :1; 3629 uint32_t isp82xx_fw_hung:1; 3630 uint32_t nic_core_hung:1; 3631 3632 uint32_t quiesce_owner:1; 3633 uint32_t nic_core_reset_hdlr_active:1; 3634 uint32_t nic_core_reset_owner:1; 3635 uint32_t isp82xx_no_md_cap:1; 3636 uint32_t host_shutting_down:1; 3637 uint32_t idc_compl_status:1; 3638 uint32_t mr_reset_hdlr_active:1; 3639 uint32_t mr_intr_valid:1; 3640 3641 uint32_t dport_enabled:1; 3642 uint32_t fawwpn_enabled:1; 3643 uint32_t exlogins_enabled:1; 3644 uint32_t exchoffld_enabled:1; 3645 3646 uint32_t lip_ae:1; 3647 uint32_t n2n_ae:1; 3648 uint32_t fw_started:1; 3649 uint32_t fw_init_done:1; 3650 3651 uint32_t detected_lr_sfp:1; 3652 uint32_t using_lr_setting:1; 3653 uint32_t rida_fmt2:1; 3654 uint32_t purge_mbox:1; 3655 uint32_t n2n_bigger:1; 3656 uint32_t secure_adapter:1; 3657 uint32_t secure_fw:1; 3658 } flags; 3659 3660 uint16_t max_exchg; 3661 uint16_t long_range_distance; /* 32G & above */ 3662 #define LR_DISTANCE_5K 1 3663 #define LR_DISTANCE_10K 0 3664 3665 /* This spinlock is used to protect "io transactions", you must 3666 * acquire it before doing any IO to the card, eg with RD_REG*() and 3667 * WRT_REG*() for the duration of your entire commandtransaction. 3668 * 3669 * This spinlock is of lower priority than the io request lock. 3670 */ 3671 3672 spinlock_t hardware_lock ____cacheline_aligned; 3673 int bars; 3674 int mem_only; 3675 device_reg_t *iobase; /* Base I/O address */ 3676 resource_size_t pio_address; 3677 3678 #define MIN_IOBASE_LEN 0x100 3679 dma_addr_t bar0_hdl; 3680 3681 void __iomem *cregbase; 3682 dma_addr_t bar2_hdl; 3683 #define BAR0_LEN_FX00 (1024 * 1024) 3684 #define BAR2_LEN_FX00 (128 * 1024) 3685 3686 uint32_t rqstq_intr_code; 3687 uint32_t mbx_intr_code; 3688 uint32_t req_que_len; 3689 uint32_t rsp_que_len; 3690 uint32_t req_que_off; 3691 uint32_t rsp_que_off; 3692 3693 /* Multi queue data structs */ 3694 device_reg_t *mqiobase; 3695 device_reg_t *msixbase; 3696 uint16_t msix_count; 3697 uint8_t mqenable; 3698 struct req_que **req_q_map; 3699 struct rsp_que **rsp_q_map; 3700 struct qla_qpair **queue_pair_map; 3701 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3702 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3703 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 3704 / sizeof(unsigned long)]; 3705 uint8_t max_req_queues; 3706 uint8_t max_rsp_queues; 3707 uint8_t max_qpairs; 3708 uint8_t num_qpairs; 3709 struct qla_qpair *base_qpair; 3710 struct qla_npiv_entry *npiv_info; 3711 uint16_t nvram_npiv_size; 3712 3713 uint16_t switch_cap; 3714 #define FLOGI_SEQ_DEL BIT_8 3715 #define FLOGI_MID_SUPPORT BIT_10 3716 #define FLOGI_VSAN_SUPPORT BIT_12 3717 #define FLOGI_SP_SUPPORT BIT_13 3718 3719 uint8_t port_no; /* Physical port of adapter */ 3720 uint8_t exch_starvation; 3721 3722 /* Timeout timers. */ 3723 uint8_t loop_down_abort_time; /* port down timer */ 3724 atomic_t loop_down_timer; /* loop down timer */ 3725 uint8_t link_down_timeout; /* link down timeout */ 3726 uint16_t max_loop_id; 3727 uint16_t max_fibre_devices; /* Maximum number of targets */ 3728 3729 uint16_t fb_rev; 3730 uint16_t min_external_loopid; /* First external loop Id */ 3731 3732 #define PORT_SPEED_UNKNOWN 0xFFFF 3733 #define PORT_SPEED_1GB 0x00 3734 #define PORT_SPEED_2GB 0x01 3735 #define PORT_SPEED_AUTO 0x02 3736 #define PORT_SPEED_4GB 0x03 3737 #define PORT_SPEED_8GB 0x04 3738 #define PORT_SPEED_16GB 0x05 3739 #define PORT_SPEED_32GB 0x06 3740 #define PORT_SPEED_64GB 0x07 3741 #define PORT_SPEED_10GB 0x13 3742 uint16_t link_data_rate; /* F/W operating speed */ 3743 uint16_t set_data_rate; /* Set by user */ 3744 3745 uint8_t current_topology; 3746 uint8_t prev_topology; 3747 #define ISP_CFG_NL 1 3748 #define ISP_CFG_N 2 3749 #define ISP_CFG_FL 4 3750 #define ISP_CFG_F 8 3751 3752 uint8_t operating_mode; /* F/W operating mode */ 3753 #define LOOP 0 3754 #define P2P 1 3755 #define LOOP_P2P 2 3756 #define P2P_LOOP 3 3757 uint8_t interrupts_on; 3758 uint32_t isp_abort_cnt; 3759 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 3760 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 3761 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 3762 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 3763 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 3764 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 3765 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 3766 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 3767 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061 3768 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081 3769 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089 3770 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281 3771 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289 3772 3773 uint32_t isp_type; 3774 #define DT_ISP2100 BIT_0 3775 #define DT_ISP2200 BIT_1 3776 #define DT_ISP2300 BIT_2 3777 #define DT_ISP2312 BIT_3 3778 #define DT_ISP2322 BIT_4 3779 #define DT_ISP6312 BIT_5 3780 #define DT_ISP6322 BIT_6 3781 #define DT_ISP2422 BIT_7 3782 #define DT_ISP2432 BIT_8 3783 #define DT_ISP5422 BIT_9 3784 #define DT_ISP5432 BIT_10 3785 #define DT_ISP2532 BIT_11 3786 #define DT_ISP8432 BIT_12 3787 #define DT_ISP8001 BIT_13 3788 #define DT_ISP8021 BIT_14 3789 #define DT_ISP2031 BIT_15 3790 #define DT_ISP8031 BIT_16 3791 #define DT_ISPFX00 BIT_17 3792 #define DT_ISP8044 BIT_18 3793 #define DT_ISP2071 BIT_19 3794 #define DT_ISP2271 BIT_20 3795 #define DT_ISP2261 BIT_21 3796 #define DT_ISP2061 BIT_22 3797 #define DT_ISP2081 BIT_23 3798 #define DT_ISP2089 BIT_24 3799 #define DT_ISP2281 BIT_25 3800 #define DT_ISP2289 BIT_26 3801 #define DT_ISP_LAST (DT_ISP2289 << 1) 3802 3803 uint32_t device_type; 3804 #define DT_T10_PI BIT_25 3805 #define DT_IIDMA BIT_26 3806 #define DT_FWI2 BIT_27 3807 #define DT_ZIO_SUPPORTED BIT_28 3808 #define DT_OEM_001 BIT_29 3809 #define DT_ISP2200A BIT_30 3810 #define DT_EXTENDED_IDS BIT_31 3811 3812 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 3813 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 3814 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 3815 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 3816 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 3817 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 3818 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 3819 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 3820 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 3821 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 3822 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 3823 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 3824 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 3825 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 3826 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 3827 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 3828 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 3829 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 3830 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 3831 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 3832 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 3833 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 3834 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 3835 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 3836 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081) 3837 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281) 3838 3839 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 3840 IS_QLA6312(ha) || IS_QLA6322(ha)) 3841 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 3842 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 3843 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 3844 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 3845 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 3846 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 3847 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha)) 3848 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 3849 IS_QLA84XX(ha)) 3850 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 3851 IS_QLA8031(ha) || IS_QLA8044(ha)) 3852 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 3853 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 3854 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 3855 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 3856 IS_QLA8044(ha) || IS_QLA27XX(ha) || \ 3857 IS_QLA28XX(ha)) 3858 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3859 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3860 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 3861 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3862 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3863 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3864 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3865 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 3866 3867 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 3868 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 3869 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 3870 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 3871 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 3872 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 3873 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 3874 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 3875 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3876 #define IS_BIDI_CAPABLE(ha) \ 3877 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3878 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 3879 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3880 ((ha)->fw_attributes_ext[0] & BIT_0)) 3881 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3882 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3883 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3884 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 3885 IS_QLA28XX(ha)) 3886 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3887 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3888 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 3889 IS_QLA28XX(ha)) 3890 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3891 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3892 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 3893 IS_QLA28XX(ha)) 3894 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 3895 IS_QLA28XX(ha)) 3896 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 3897 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3898 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 3899 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3900 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3901 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ 3902 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3903 3904 /* HBA serial number */ 3905 uint8_t serial0; 3906 uint8_t serial1; 3907 uint8_t serial2; 3908 3909 /* NVRAM configuration data */ 3910 #define MAX_NVRAM_SIZE 4096 3911 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2) 3912 uint16_t nvram_size; 3913 uint16_t nvram_base; 3914 void *nvram; 3915 uint16_t vpd_size; 3916 uint16_t vpd_base; 3917 void *vpd; 3918 3919 uint16_t loop_reset_delay; 3920 uint8_t retry_count; 3921 uint8_t login_timeout; 3922 uint16_t r_a_tov; 3923 int port_down_retry_count; 3924 uint8_t mbx_count; 3925 uint8_t aen_mbx_count; 3926 atomic_t num_pend_mbx_stage1; 3927 atomic_t num_pend_mbx_stage2; 3928 atomic_t num_pend_mbx_stage3; 3929 uint16_t frame_payload_size; 3930 3931 uint32_t login_retry_count; 3932 /* SNS command interfaces. */ 3933 ms_iocb_entry_t *ms_iocb; 3934 dma_addr_t ms_iocb_dma; 3935 struct ct_sns_pkt *ct_sns; 3936 dma_addr_t ct_sns_dma; 3937 /* SNS command interfaces for 2200. */ 3938 struct sns_cmd_pkt *sns_cmd; 3939 dma_addr_t sns_cmd_dma; 3940 3941 #define SFP_DEV_SIZE 512 3942 #define SFP_BLOCK_SIZE 64 3943 void *sfp_data; 3944 dma_addr_t sfp_data_dma; 3945 3946 void *flt; 3947 dma_addr_t flt_dma; 3948 3949 #define XGMAC_DATA_SIZE 4096 3950 void *xgmac_data; 3951 dma_addr_t xgmac_data_dma; 3952 3953 #define DCBX_TLV_DATA_SIZE 4096 3954 void *dcbx_tlv; 3955 dma_addr_t dcbx_tlv_dma; 3956 3957 struct task_struct *dpc_thread; 3958 uint8_t dpc_active; /* DPC routine is active */ 3959 3960 dma_addr_t gid_list_dma; 3961 struct gid_list_info *gid_list; 3962 int gid_list_info_size; 3963 3964 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3965 #define DMA_POOL_SIZE 256 3966 struct dma_pool *s_dma_pool; 3967 3968 dma_addr_t init_cb_dma; 3969 init_cb_t *init_cb; 3970 int init_cb_size; 3971 dma_addr_t ex_init_cb_dma; 3972 struct ex_init_cb_81xx *ex_init_cb; 3973 3974 void *async_pd; 3975 dma_addr_t async_pd_dma; 3976 3977 #define ENABLE_EXTENDED_LOGIN BIT_7 3978 3979 /* Extended Logins */ 3980 void *exlogin_buf; 3981 dma_addr_t exlogin_buf_dma; 3982 int exlogin_size; 3983 3984 #define ENABLE_EXCHANGE_OFFLD BIT_2 3985 3986 /* Exchange Offload */ 3987 void *exchoffld_buf; 3988 dma_addr_t exchoffld_buf_dma; 3989 int exchoffld_size; 3990 int exchoffld_count; 3991 3992 /* n2n */ 3993 struct els_plogi_payload plogi_els_payld; 3994 3995 void *swl; 3996 3997 /* These are used by mailbox operations. */ 3998 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3999 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 4000 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 4001 4002 mbx_cmd_t *mcp; 4003 struct mbx_cmd_32 *mcp32; 4004 4005 unsigned long mbx_cmd_flags; 4006 #define MBX_INTERRUPT 1 4007 #define MBX_INTR_WAIT 2 4008 #define MBX_UPDATE_FLASH_ACTIVE 3 4009 4010 struct mutex vport_lock; /* Virtual port synchronization */ 4011 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 4012 struct mutex mq_lock; /* multi-queue synchronization */ 4013 struct completion mbx_cmd_comp; /* Serialize mbx access */ 4014 struct completion mbx_intr_comp; /* Used for completion notification */ 4015 struct completion dcbx_comp; /* For set port config notification */ 4016 struct completion lb_portup_comp; /* Used to wait for link up during 4017 * loopback */ 4018 #define DCBX_COMP_TIMEOUT 20 4019 #define LB_PORTUP_COMP_TIMEOUT 10 4020 4021 int notify_dcbx_comp; 4022 int notify_lb_portup_comp; 4023 struct mutex selflogin_lock; 4024 4025 /* Basic firmware related information. */ 4026 uint16_t fw_major_version; 4027 uint16_t fw_minor_version; 4028 uint16_t fw_subminor_version; 4029 uint16_t fw_attributes; 4030 uint16_t fw_attributes_h; 4031 #define FW_ATTR_H_NVME_FBURST BIT_1 4032 #define FW_ATTR_H_NVME BIT_10 4033 #define FW_ATTR_H_NVME_UPDATED BIT_14 4034 4035 uint16_t fw_attributes_ext[2]; 4036 uint32_t fw_memory_size; 4037 uint32_t fw_transfer_size; 4038 uint32_t fw_srisc_address; 4039 #define RISC_START_ADDRESS_2100 0x1000 4040 #define RISC_START_ADDRESS_2300 0x800 4041 #define RISC_START_ADDRESS_2400 0x100000 4042 4043 uint16_t orig_fw_tgt_xcb_count; 4044 uint16_t cur_fw_tgt_xcb_count; 4045 uint16_t orig_fw_xcb_count; 4046 uint16_t cur_fw_xcb_count; 4047 uint16_t orig_fw_iocb_count; 4048 uint16_t cur_fw_iocb_count; 4049 uint16_t fw_max_fcf_count; 4050 4051 uint32_t fw_shared_ram_start; 4052 uint32_t fw_shared_ram_end; 4053 uint32_t fw_ddr_ram_start; 4054 uint32_t fw_ddr_ram_end; 4055 4056 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 4057 uint8_t fw_seriallink_options[4]; 4058 uint16_t fw_seriallink_options24[4]; 4059 4060 uint8_t serdes_version[3]; 4061 uint8_t mpi_version[3]; 4062 uint32_t mpi_capabilities; 4063 uint8_t phy_version[3]; 4064 uint8_t pep_version[3]; 4065 4066 /* Firmware dump template */ 4067 struct fwdt { 4068 void *template; 4069 ulong length; 4070 ulong dump_size; 4071 } fwdt[2]; 4072 struct qla2xxx_fw_dump *fw_dump; 4073 uint32_t fw_dump_len; 4074 u32 fw_dump_alloc_len; 4075 bool fw_dumped; 4076 bool fw_dump_mpi; 4077 unsigned long fw_dump_cap_flags; 4078 #define RISC_PAUSE_CMPL 0 4079 #define DMA_SHUTDOWN_CMPL 1 4080 #define ISP_RESET_CMPL 2 4081 #define RISC_RDY_AFT_RESET 3 4082 #define RISC_SRAM_DUMP_CMPL 4 4083 #define RISC_EXT_MEM_DUMP_CMPL 5 4084 #define ISP_MBX_RDY 6 4085 #define ISP_SOFT_RESET_CMPL 7 4086 int fw_dump_reading; 4087 int prev_minidump_failed; 4088 dma_addr_t eft_dma; 4089 void *eft; 4090 /* Current size of mctp dump is 0x086064 bytes */ 4091 #define MCTP_DUMP_SIZE 0x086064 4092 dma_addr_t mctp_dump_dma; 4093 void *mctp_dump; 4094 int mctp_dumped; 4095 int mctp_dump_reading; 4096 uint32_t chain_offset; 4097 struct dentry *dfs_dir; 4098 struct dentry *dfs_fce; 4099 struct dentry *dfs_tgt_counters; 4100 struct dentry *dfs_fw_resource_cnt; 4101 4102 dma_addr_t fce_dma; 4103 void *fce; 4104 uint32_t fce_bufs; 4105 uint16_t fce_mb[8]; 4106 uint64_t fce_wr, fce_rd; 4107 struct mutex fce_mutex; 4108 4109 uint32_t pci_attr; 4110 uint16_t chip_revision; 4111 4112 uint16_t product_id[4]; 4113 4114 uint8_t model_number[16+1]; 4115 char model_desc[80]; 4116 uint8_t adapter_id[16+1]; 4117 4118 /* Option ROM information. */ 4119 char *optrom_buffer; 4120 uint32_t optrom_size; 4121 int optrom_state; 4122 #define QLA_SWAITING 0 4123 #define QLA_SREADING 1 4124 #define QLA_SWRITING 2 4125 uint32_t optrom_region_start; 4126 uint32_t optrom_region_size; 4127 struct mutex optrom_mutex; 4128 4129 /* PCI expansion ROM image information. */ 4130 #define ROM_CODE_TYPE_BIOS 0 4131 #define ROM_CODE_TYPE_FCODE 1 4132 #define ROM_CODE_TYPE_EFI 3 4133 uint8_t bios_revision[2]; 4134 uint8_t efi_revision[2]; 4135 uint8_t fcode_revision[16]; 4136 uint32_t fw_revision[4]; 4137 4138 uint32_t gold_fw_version[4]; 4139 4140 /* Offsets for flash/nvram access (set to ~0 if not used). */ 4141 uint32_t flash_conf_off; 4142 uint32_t flash_data_off; 4143 uint32_t nvram_conf_off; 4144 uint32_t nvram_data_off; 4145 4146 uint32_t fdt_wrt_disable; 4147 uint32_t fdt_wrt_enable; 4148 uint32_t fdt_erase_cmd; 4149 uint32_t fdt_block_size; 4150 uint32_t fdt_unprotect_sec_cmd; 4151 uint32_t fdt_protect_sec_cmd; 4152 uint32_t fdt_wrt_sts_reg_cmd; 4153 4154 struct { 4155 uint32_t flt_region_flt; 4156 uint32_t flt_region_fdt; 4157 uint32_t flt_region_boot; 4158 uint32_t flt_region_boot_sec; 4159 uint32_t flt_region_fw; 4160 uint32_t flt_region_fw_sec; 4161 uint32_t flt_region_vpd_nvram; 4162 uint32_t flt_region_vpd_nvram_sec; 4163 uint32_t flt_region_vpd; 4164 uint32_t flt_region_vpd_sec; 4165 uint32_t flt_region_nvram; 4166 uint32_t flt_region_nvram_sec; 4167 uint32_t flt_region_npiv_conf; 4168 uint32_t flt_region_gold_fw; 4169 uint32_t flt_region_fcp_prio; 4170 uint32_t flt_region_bootload; 4171 uint32_t flt_region_img_status_pri; 4172 uint32_t flt_region_img_status_sec; 4173 uint32_t flt_region_aux_img_status_pri; 4174 uint32_t flt_region_aux_img_status_sec; 4175 }; 4176 uint8_t active_image; 4177 4178 /* Needed for BEACON */ 4179 uint16_t beacon_blink_led; 4180 uint8_t beacon_color_state; 4181 #define QLA_LED_GRN_ON 0x01 4182 #define QLA_LED_YLW_ON 0x02 4183 #define QLA_LED_ABR_ON 0x04 4184 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 4185 /* ISP2322: red, green, amber. */ 4186 uint16_t zio_mode; 4187 uint16_t zio_timer; 4188 4189 struct qla_msix_entry *msix_entries; 4190 4191 struct list_head vp_list; /* list of VP */ 4192 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 4193 sizeof(unsigned long)]; 4194 uint16_t num_vhosts; /* number of vports created */ 4195 uint16_t num_vsans; /* number of vsan created */ 4196 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 4197 int cur_vport_count; 4198 4199 struct qla_chip_state_84xx *cs84xx; 4200 struct isp_operations *isp_ops; 4201 struct workqueue_struct *wq; 4202 struct qlfc_fw fw_buf; 4203 4204 /* FCP_CMND priority support */ 4205 struct qla_fcp_prio_cfg *fcp_prio_cfg; 4206 4207 struct dma_pool *dl_dma_pool; 4208 #define DSD_LIST_DMA_POOL_SIZE 512 4209 4210 struct dma_pool *fcp_cmnd_dma_pool; 4211 mempool_t *ctx_mempool; 4212 #define FCP_CMND_DMA_POOL_SIZE 512 4213 4214 void __iomem *nx_pcibase; /* Base I/O address */ 4215 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4216 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4217 4218 uint32_t crb_win; 4219 uint32_t curr_window; 4220 uint32_t ddr_mn_window; 4221 unsigned long mn_win_crb; 4222 unsigned long ms_win_crb; 4223 int qdr_sn_window; 4224 uint32_t fcoe_dev_init_timeout; 4225 uint32_t fcoe_reset_timeout; 4226 rwlock_t hw_lock; 4227 uint16_t portnum; /* port number */ 4228 int link_width; 4229 struct fw_blob *hablob; 4230 struct qla82xx_legacy_intr_set nx_legacy_intr; 4231 4232 uint16_t gbl_dsd_inuse; 4233 uint16_t gbl_dsd_avail; 4234 struct list_head gbl_dsd_list; 4235 #define NUM_DSD_CHAIN 4096 4236 4237 uint8_t fw_type; 4238 __le32 file_prd_off; /* File firmware product offset */ 4239 4240 uint32_t md_template_size; 4241 void *md_tmplt_hdr; 4242 dma_addr_t md_tmplt_hdr_dma; 4243 void *md_dump; 4244 uint32_t md_dump_size; 4245 4246 void *loop_id_map; 4247 4248 /* QLA83XX IDC specific fields */ 4249 uint32_t idc_audit_ts; 4250 uint32_t idc_extend_tmo; 4251 4252 /* DPC low-priority workqueue */ 4253 struct workqueue_struct *dpc_lp_wq; 4254 struct work_struct idc_aen; 4255 /* DPC high-priority workqueue */ 4256 struct workqueue_struct *dpc_hp_wq; 4257 struct work_struct nic_core_reset; 4258 struct work_struct idc_state_handler; 4259 struct work_struct nic_core_unrecoverable; 4260 struct work_struct board_disable; 4261 4262 struct mr_data_fx00 mr; 4263 uint32_t chip_reset; 4264 4265 struct qlt_hw_data tgt; 4266 int allow_cna_fw_dump; 4267 uint32_t fw_ability_mask; 4268 uint16_t min_supported_speed; 4269 uint16_t max_supported_speed; 4270 4271 /* DMA pool for the DIF bundling buffers */ 4272 struct dma_pool *dif_bundl_pool; 4273 #define DIF_BUNDLING_DMA_POOL_SIZE 1024 4274 struct { 4275 struct { 4276 struct list_head head; 4277 uint count; 4278 } good; 4279 struct { 4280 struct list_head head; 4281 uint count; 4282 } unusable; 4283 } pool; 4284 4285 unsigned long long dif_bundle_crossed_pages; 4286 unsigned long long dif_bundle_reads; 4287 unsigned long long dif_bundle_writes; 4288 unsigned long long dif_bundle_kallocs; 4289 unsigned long long dif_bundle_dma_allocs; 4290 4291 atomic_t nvme_active_aen_cnt; 4292 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4293 4294 atomic_t zio_threshold; 4295 uint16_t last_zio_threshold; 4296 4297 #define DEFAULT_ZIO_THRESHOLD 5 4298 }; 4299 4300 struct active_regions { 4301 uint8_t global; 4302 struct { 4303 uint8_t board_config; 4304 uint8_t vpd_nvram; 4305 uint8_t npiv_config_0_1; 4306 uint8_t npiv_config_2_3; 4307 } aux; 4308 }; 4309 4310 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4311 #define FW_ABILITY_MAX_SPEED_16G 0x0 4312 #define FW_ABILITY_MAX_SPEED_32G 0x1 4313 #define FW_ABILITY_MAX_SPEED(ha) \ 4314 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4315 4316 #define QLA_GET_DATA_RATE 0 4317 #define QLA_SET_DATA_RATE_NOLR 1 4318 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */ 4319 4320 /* 4321 * Qlogic scsi host structure 4322 */ 4323 typedef struct scsi_qla_host { 4324 struct list_head list; 4325 struct list_head vp_fcports; /* list of fcports */ 4326 struct list_head work_list; 4327 spinlock_t work_lock; 4328 struct work_struct iocb_work; 4329 4330 /* Commonly used flags and state information. */ 4331 struct Scsi_Host *host; 4332 unsigned long host_no; 4333 uint8_t host_str[16]; 4334 4335 volatile struct { 4336 uint32_t init_done :1; 4337 uint32_t online :1; 4338 uint32_t reset_active :1; 4339 4340 uint32_t management_server_logged_in :1; 4341 uint32_t process_response_queue :1; 4342 uint32_t difdix_supported:1; 4343 uint32_t delete_progress:1; 4344 4345 uint32_t fw_tgt_reported:1; 4346 uint32_t bbcr_enable:1; 4347 uint32_t qpairs_available:1; 4348 uint32_t qpairs_req_created:1; 4349 uint32_t qpairs_rsp_created:1; 4350 uint32_t nvme_enabled:1; 4351 uint32_t nvme_first_burst:1; 4352 } flags; 4353 4354 atomic_t loop_state; 4355 #define LOOP_TIMEOUT 1 4356 #define LOOP_DOWN 2 4357 #define LOOP_UP 3 4358 #define LOOP_UPDATE 4 4359 #define LOOP_READY 5 4360 #define LOOP_DEAD 6 4361 4362 unsigned long relogin_jif; 4363 unsigned long dpc_flags; 4364 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4365 #define RESET_ACTIVE 1 4366 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4367 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4368 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4369 #define LOOP_RESYNC_ACTIVE 5 4370 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4371 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4372 #define RELOGIN_NEEDED 8 4373 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4374 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4375 #define BEACON_BLINK_NEEDED 11 4376 #define REGISTER_FDMI_NEEDED 12 4377 #define FCPORT_UPDATE_NEEDED 13 4378 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4379 #define UNLOADING 15 4380 #define NPIV_CONFIG_NEEDED 16 4381 #define ISP_UNRECOVERABLE 17 4382 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4383 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4384 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4385 #define N2N_LINK_RESET 21 4386 #define PORT_UPDATE_NEEDED 22 4387 #define FX00_RESET_RECOVERY 23 4388 #define FX00_TARGET_SCAN 24 4389 #define FX00_CRITEMP_RECOVERY 25 4390 #define FX00_HOST_INFO_RESEND 26 4391 #define QPAIR_ONLINE_CHECK_NEEDED 27 4392 #define SET_NVME_ZIO_THRESHOLD_NEEDED 28 4393 #define DETECT_SFP_CHANGE 29 4394 #define N2N_LOGIN_NEEDED 30 4395 #define IOCB_WORK_ACTIVE 31 4396 #define SET_ZIO_THRESHOLD_NEEDED 32 4397 #define ISP_ABORT_TO_ROM 33 4398 #define VPORT_DELETE 34 4399 4400 unsigned long pci_flags; 4401 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4402 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4403 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4404 4405 uint32_t device_flags; 4406 #define SWITCH_FOUND BIT_0 4407 #define DFLG_NO_CABLE BIT_1 4408 #define DFLG_DEV_FAILED BIT_5 4409 4410 /* ISP configuration data. */ 4411 uint16_t loop_id; /* Host adapter loop id */ 4412 uint16_t self_login_loop_id; /* host adapter loop id 4413 * get it on self login 4414 */ 4415 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4416 * no need of allocating it for 4417 * each command 4418 */ 4419 4420 port_id_t d_id; /* Host adapter port id */ 4421 uint8_t marker_needed; 4422 uint16_t mgmt_svr_loop_id; 4423 4424 4425 4426 /* Timeout timers. */ 4427 uint8_t loop_down_abort_time; /* port down timer */ 4428 atomic_t loop_down_timer; /* loop down timer */ 4429 uint8_t link_down_timeout; /* link down timeout */ 4430 4431 uint32_t timer_active; 4432 struct timer_list timer; 4433 4434 uint8_t node_name[WWN_SIZE]; 4435 uint8_t port_name[WWN_SIZE]; 4436 uint8_t fabric_node_name[WWN_SIZE]; 4437 4438 struct nvme_fc_local_port *nvme_local_port; 4439 struct completion nvme_del_done; 4440 4441 uint16_t fcoe_vlan_id; 4442 uint16_t fcoe_fcf_idx; 4443 uint8_t fcoe_vn_port_mac[6]; 4444 4445 /* list of commands waiting on workqueue */ 4446 struct list_head qla_cmd_list; 4447 struct list_head qla_sess_op_cmd_list; 4448 struct list_head unknown_atio_list; 4449 spinlock_t cmd_list_lock; 4450 struct delayed_work unknown_atio_work; 4451 4452 /* Counter to detect races between ELS and RSCN events */ 4453 atomic_t generation_tick; 4454 /* Time when global fcport update has been scheduled */ 4455 int total_fcport_update_gen; 4456 /* List of pending LOGOs, protected by tgt_mutex */ 4457 struct list_head logo_list; 4458 /* List of pending PLOGI acks, protected by hw lock */ 4459 struct list_head plogi_ack_list; 4460 4461 struct list_head qp_list; 4462 4463 uint32_t vp_abort_cnt; 4464 4465 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4466 uint16_t vp_idx; /* vport ID */ 4467 struct qla_qpair *qpair; /* base qpair */ 4468 4469 unsigned long vp_flags; 4470 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4471 #define VP_CREATE_NEEDED 1 4472 #define VP_BIND_NEEDED 2 4473 #define VP_DELETE_NEEDED 3 4474 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4475 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4476 atomic_t vp_state; 4477 #define VP_OFFLINE 0 4478 #define VP_ACTIVE 1 4479 #define VP_FAILED 2 4480 // #define VP_DISABLE 3 4481 uint16_t vp_err_state; 4482 uint16_t vp_prev_err_state; 4483 #define VP_ERR_UNKWN 0 4484 #define VP_ERR_PORTDWN 1 4485 #define VP_ERR_FAB_UNSUPPORTED 2 4486 #define VP_ERR_FAB_NORESOURCES 3 4487 #define VP_ERR_FAB_LOGOUT 4 4488 #define VP_ERR_ADAP_NORESOURCES 5 4489 struct qla_hw_data *hw; 4490 struct scsi_qlt_host vha_tgt; 4491 struct req_que *req; 4492 int fw_heartbeat_counter; 4493 int seconds_since_last_heartbeat; 4494 struct fc_host_statistics fc_host_stat; 4495 struct qla_statistics qla_stats; 4496 struct bidi_statistics bidi_stats; 4497 atomic_t vref_count; 4498 struct qla8044_reset_template reset_tmplt; 4499 uint16_t bbcr; 4500 4501 uint16_t u_ql2xexchoffld; 4502 uint16_t u_ql2xiniexchg; 4503 uint16_t qlini_mode; 4504 uint16_t ql2xexchoffld; 4505 uint16_t ql2xiniexchg; 4506 4507 struct name_list_extended gnl; 4508 /* Count of active session/fcport */ 4509 int fcport_count; 4510 wait_queue_head_t fcport_waitQ; 4511 wait_queue_head_t vref_waitq; 4512 uint8_t min_supported_speed; 4513 uint8_t n2n_node_name[WWN_SIZE]; 4514 uint8_t n2n_port_name[WWN_SIZE]; 4515 uint16_t n2n_id; 4516 struct list_head gpnid_list; 4517 struct fab_scan scan; 4518 4519 unsigned int irq_offset; 4520 } scsi_qla_host_t; 4521 4522 struct qla27xx_image_status { 4523 uint8_t image_status_mask; 4524 uint16_t generation; 4525 uint8_t ver_major; 4526 uint8_t ver_minor; 4527 uint8_t bitmap; /* 28xx only */ 4528 uint8_t reserved[2]; 4529 uint32_t checksum; 4530 uint32_t signature; 4531 } __packed; 4532 4533 /* 28xx aux image status bimap values */ 4534 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0 4535 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1 4536 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2 4537 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3 4538 4539 #define SET_VP_IDX 1 4540 #define SET_AL_PA 2 4541 #define RESET_VP_IDX 3 4542 #define RESET_AL_PA 4 4543 struct qla_tgt_vp_map { 4544 uint8_t idx; 4545 scsi_qla_host_t *vha; 4546 }; 4547 4548 struct qla2_sgx { 4549 dma_addr_t dma_addr; /* OUT */ 4550 uint32_t dma_len; /* OUT */ 4551 4552 uint32_t tot_bytes; /* IN */ 4553 struct scatterlist *cur_sg; /* IN */ 4554 4555 /* for book keeping, bzero on initial invocation */ 4556 uint32_t bytes_consumed; 4557 uint32_t num_bytes; 4558 uint32_t tot_partial; 4559 4560 /* for debugging */ 4561 uint32_t num_sg; 4562 srb_t *sp; 4563 }; 4564 4565 #define QLA_FW_STARTED(_ha) { \ 4566 int i; \ 4567 _ha->flags.fw_started = 1; \ 4568 _ha->base_qpair->fw_started = 1; \ 4569 for (i = 0; i < _ha->max_qpairs; i++) { \ 4570 if (_ha->queue_pair_map[i]) \ 4571 _ha->queue_pair_map[i]->fw_started = 1; \ 4572 } \ 4573 } 4574 4575 #define QLA_FW_STOPPED(_ha) { \ 4576 int i; \ 4577 _ha->flags.fw_started = 0; \ 4578 _ha->base_qpair->fw_started = 0; \ 4579 for (i = 0; i < _ha->max_qpairs; i++) { \ 4580 if (_ha->queue_pair_map[i]) \ 4581 _ha->queue_pair_map[i]->fw_started = 0; \ 4582 } \ 4583 } 4584 4585 4586 #define SFUB_CHECKSUM_SIZE 4 4587 4588 struct secure_flash_update_block { 4589 uint32_t block_info; 4590 uint32_t signature_lo; 4591 uint32_t signature_hi; 4592 uint32_t signature_upper[0x3e]; 4593 }; 4594 4595 struct secure_flash_update_block_pk { 4596 uint32_t block_info; 4597 uint32_t signature_lo; 4598 uint32_t signature_hi; 4599 uint32_t signature_upper[0x3e]; 4600 uint32_t public_key[0x41]; 4601 }; 4602 4603 /* 4604 * Macros to help code, maintain, etc. 4605 */ 4606 #define LOOP_TRANSITION(ha) \ 4607 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4608 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 4609 atomic_read(&ha->loop_state) == LOOP_DOWN) 4610 4611 #define STATE_TRANSITION(ha) \ 4612 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4613 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 4614 4615 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 4616 atomic_inc(&__vha->vref_count); \ 4617 mb(); \ 4618 if (__vha->flags.delete_progress) { \ 4619 atomic_dec(&__vha->vref_count); \ 4620 wake_up(&__vha->vref_waitq); \ 4621 __bail = 1; \ 4622 } else { \ 4623 __bail = 0; \ 4624 } \ 4625 } while (0) 4626 4627 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 4628 atomic_dec(&__vha->vref_count); \ 4629 wake_up(&__vha->vref_waitq); \ 4630 } while (0) \ 4631 4632 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 4633 atomic_inc(&__qpair->ref_count); \ 4634 mb(); \ 4635 if (__qpair->delete_in_progress) { \ 4636 atomic_dec(&__qpair->ref_count); \ 4637 __bail = 1; \ 4638 } else { \ 4639 __bail = 0; \ 4640 } \ 4641 } while (0) 4642 4643 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 4644 atomic_dec(&__qpair->ref_count); \ 4645 4646 4647 #define QLA_ENA_CONF(_ha) {\ 4648 int i;\ 4649 _ha->base_qpair->enable_explicit_conf = 1; \ 4650 for (i = 0; i < _ha->max_qpairs; i++) { \ 4651 if (_ha->queue_pair_map[i]) \ 4652 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 4653 } \ 4654 } 4655 4656 #define QLA_DIS_CONF(_ha) {\ 4657 int i;\ 4658 _ha->base_qpair->enable_explicit_conf = 0; \ 4659 for (i = 0; i < _ha->max_qpairs; i++) { \ 4660 if (_ha->queue_pair_map[i]) \ 4661 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 4662 } \ 4663 } 4664 4665 /* 4666 * qla2x00 local function return status codes 4667 */ 4668 #define MBS_MASK 0x3fff 4669 4670 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 4671 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 4672 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 4673 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 4674 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 4675 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 4676 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 4677 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 4678 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 4679 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 4680 4681 #define QLA_FUNCTION_TIMEOUT 0x100 4682 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 4683 #define QLA_FUNCTION_FAILED 0x102 4684 #define QLA_MEMORY_ALLOC_FAILED 0x103 4685 #define QLA_LOCK_TIMEOUT 0x104 4686 #define QLA_ABORTED 0x105 4687 #define QLA_SUSPENDED 0x106 4688 #define QLA_BUSY 0x107 4689 #define QLA_ALREADY_REGISTERED 0x109 4690 #define QLA_OS_TIMER_EXPIRED 0x10a 4691 4692 #define NVRAM_DELAY() udelay(10) 4693 4694 /* 4695 * Flash support definitions 4696 */ 4697 #define OPTROM_SIZE_2300 0x20000 4698 #define OPTROM_SIZE_2322 0x100000 4699 #define OPTROM_SIZE_24XX 0x100000 4700 #define OPTROM_SIZE_25XX 0x200000 4701 #define OPTROM_SIZE_81XX 0x400000 4702 #define OPTROM_SIZE_82XX 0x800000 4703 #define OPTROM_SIZE_83XX 0x1000000 4704 #define OPTROM_SIZE_28XX 0x2000000 4705 4706 #define OPTROM_BURST_SIZE 0x1000 4707 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 4708 4709 #define QLA_DSDS_PER_IOCB 37 4710 4711 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 4712 4713 #define QLA_SG_ALL 1024 4714 4715 enum nexus_wait_type { 4716 WAIT_HOST = 0, 4717 WAIT_TARGET, 4718 WAIT_LUN, 4719 }; 4720 4721 /* Refer to SNIA SFF 8247 */ 4722 struct sff_8247_a0 { 4723 u8 txid; /* transceiver id */ 4724 u8 ext_txid; 4725 u8 connector; 4726 /* compliance code */ 4727 u8 eth_infi_cc3; /* ethernet, inifiband */ 4728 u8 sonet_cc4[2]; 4729 u8 eth_cc6; 4730 /* link length */ 4731 #define FC_LL_VL BIT_7 /* very long */ 4732 #define FC_LL_S BIT_6 /* Short */ 4733 #define FC_LL_I BIT_5 /* Intermidiate*/ 4734 #define FC_LL_L BIT_4 /* Long */ 4735 #define FC_LL_M BIT_3 /* Medium */ 4736 #define FC_LL_SA BIT_2 /* ShortWave laser */ 4737 #define FC_LL_LC BIT_1 /* LongWave laser */ 4738 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 4739 u8 fc_ll_cc7; 4740 /* FC technology */ 4741 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 4742 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 4743 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 4744 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 4745 #define FC_TEC_ACT BIT_3 /* Active cable */ 4746 #define FC_TEC_PAS BIT_2 /* Passive cable */ 4747 u8 fc_tec_cc8; 4748 /* Transmission Media */ 4749 #define FC_MED_TW BIT_7 /* Twin Ax */ 4750 #define FC_MED_TP BIT_6 /* Twited Pair */ 4751 #define FC_MED_MI BIT_5 /* Min Coax */ 4752 #define FC_MED_TV BIT_4 /* Video Coax */ 4753 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 4754 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 4755 #define FC_MED_SM BIT_0 /* Single Mode */ 4756 u8 fc_med_cc9; 4757 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 4758 #define FC_SP_12 BIT_7 4759 #define FC_SP_8 BIT_6 4760 #define FC_SP_16 BIT_5 4761 #define FC_SP_4 BIT_4 4762 #define FC_SP_32 BIT_3 4763 #define FC_SP_2 BIT_2 4764 #define FC_SP_1 BIT_0 4765 u8 fc_sp_cc10; 4766 u8 encode; 4767 u8 bitrate; 4768 u8 rate_id; 4769 u8 length_km; /* offset 14/eh */ 4770 u8 length_100m; 4771 u8 length_50um_10m; 4772 u8 length_62um_10m; 4773 u8 length_om4_10m; 4774 u8 length_om3_10m; 4775 #define SFF_VEN_NAME_LEN 16 4776 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 4777 u8 tx_compat; 4778 u8 vendor_oui[3]; 4779 #define SFF_PART_NAME_LEN 16 4780 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 4781 u8 vendor_rev[4]; 4782 u8 wavelength[2]; 4783 u8 resv; 4784 u8 cc_base; 4785 u8 options[2]; /* offset 64 */ 4786 u8 br_max; 4787 u8 br_min; 4788 u8 vendor_sn[16]; 4789 u8 date_code[8]; 4790 u8 diag; 4791 u8 enh_options; 4792 u8 sff_revision; 4793 u8 cc_ext; 4794 u8 vendor_specific[32]; 4795 u8 resv2[128]; 4796 }; 4797 4798 #define AUTO_DETECT_SFP_SUPPORT(_vha)\ 4799 (ql2xautodetectsfp && !_vha->vp_idx && \ 4800 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\ 4801 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw) || \ 4802 IS_QLA28XX(_vha->hw))) 4803 4804 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016 4805 4806 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 4807 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha))) 4808 4809 #define SAVE_TOPO(_ha) { \ 4810 if (_ha->current_topology) \ 4811 _ha->prev_topology = _ha->current_topology; \ 4812 } 4813 4814 #define N2N_TOPO(ha) \ 4815 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ 4816 ha->current_topology == ISP_CFG_N || \ 4817 !ha->current_topology) 4818 4819 #include "qla_target.h" 4820 #include "qla_gbl.h" 4821 #include "qla_dbg.h" 4822 #include "qla_inline.h" 4823 #endif 4824