1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 #include <linux/btree.h> 29 30 #include <scsi/scsi.h> 31 #include <scsi/scsi_host.h> 32 #include <scsi/scsi_device.h> 33 #include <scsi/scsi_cmnd.h> 34 #include <scsi/scsi_transport_fc.h> 35 #include <scsi/scsi_bsg_fc.h> 36 37 #include <uapi/scsi/fc/fc_els.h> 38 39 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 40 typedef struct { 41 uint8_t domain; 42 uint8_t area; 43 uint8_t al_pa; 44 } be_id_t; 45 46 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 47 typedef struct { 48 uint8_t al_pa; 49 uint8_t area; 50 uint8_t domain; 51 } le_id_t; 52 53 #include "qla_bsg.h" 54 #include "qla_dsd.h" 55 #include "qla_nx.h" 56 #include "qla_nx2.h" 57 #include "qla_nvme.h" 58 #define QLA2XXX_DRIVER_NAME "qla2xxx" 59 #define QLA2XXX_APIDEV "ql2xapidev" 60 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 61 62 /* 63 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 64 * but that's fine as we don't look at the last 24 ones for 65 * ISP2100 HBAs. 66 */ 67 #define MAILBOX_REGISTER_COUNT_2100 8 68 #define MAILBOX_REGISTER_COUNT_2200 24 69 #define MAILBOX_REGISTER_COUNT 32 70 71 #define QLA2200A_RISC_ROM_VER 4 72 #define FPM_2300 6 73 #define FPM_2310 7 74 75 #include "qla_settings.h" 76 77 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 78 79 /* 80 * Data bit definitions 81 */ 82 #define BIT_0 0x1 83 #define BIT_1 0x2 84 #define BIT_2 0x4 85 #define BIT_3 0x8 86 #define BIT_4 0x10 87 #define BIT_5 0x20 88 #define BIT_6 0x40 89 #define BIT_7 0x80 90 #define BIT_8 0x100 91 #define BIT_9 0x200 92 #define BIT_10 0x400 93 #define BIT_11 0x800 94 #define BIT_12 0x1000 95 #define BIT_13 0x2000 96 #define BIT_14 0x4000 97 #define BIT_15 0x8000 98 #define BIT_16 0x10000 99 #define BIT_17 0x20000 100 #define BIT_18 0x40000 101 #define BIT_19 0x80000 102 #define BIT_20 0x100000 103 #define BIT_21 0x200000 104 #define BIT_22 0x400000 105 #define BIT_23 0x800000 106 #define BIT_24 0x1000000 107 #define BIT_25 0x2000000 108 #define BIT_26 0x4000000 109 #define BIT_27 0x8000000 110 #define BIT_28 0x10000000 111 #define BIT_29 0x20000000 112 #define BIT_30 0x40000000 113 #define BIT_31 0x80000000 114 115 #define LSB(x) ((uint8_t)(x)) 116 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 117 118 #define LSW(x) ((uint16_t)(x)) 119 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 120 121 #define LSD(x) ((uint32_t)((uint64_t)(x))) 122 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 123 124 static inline uint32_t make_handle(uint16_t x, uint16_t y) 125 { 126 return ((uint32_t)x << 16) | y; 127 } 128 129 /* 130 * I/O register 131 */ 132 133 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr) 134 { 135 return readb(addr); 136 } 137 138 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr) 139 { 140 return readw(addr); 141 } 142 143 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr) 144 { 145 return readl(addr); 146 } 147 148 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr) 149 { 150 return readb_relaxed(addr); 151 } 152 153 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr) 154 { 155 return readw_relaxed(addr); 156 } 157 158 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr) 159 { 160 return readl_relaxed(addr); 161 } 162 163 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data) 164 { 165 return writeb(data, addr); 166 } 167 168 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data) 169 { 170 return writew(data, addr); 171 } 172 173 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data) 174 { 175 return writel(data, addr); 176 } 177 178 /* 179 * ISP83XX specific remote register addresses 180 */ 181 #define QLA83XX_LED_PORT0 0x00201320 182 #define QLA83XX_LED_PORT1 0x00201328 183 #define QLA83XX_IDC_DEV_STATE 0x22102384 184 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 185 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 186 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 187 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 188 #define QLA83XX_IDC_CONTROL 0x22102390 189 #define QLA83XX_IDC_AUDIT 0x22102394 190 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 191 #define QLA83XX_DRIVER_LOCKID 0x22102104 192 #define QLA83XX_DRIVER_LOCK 0x8111c028 193 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 194 #define QLA83XX_FLASH_LOCKID 0x22102100 195 #define QLA83XX_FLASH_LOCK 0x8111c010 196 #define QLA83XX_FLASH_UNLOCK 0x8111c014 197 #define QLA83XX_DEV_PARTINFO1 0x221023e0 198 #define QLA83XX_DEV_PARTINFO2 0x221023e4 199 #define QLA83XX_FW_HEARTBEAT 0x221020b0 200 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 201 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 202 203 /* 83XX: Macros defining 8200 AEN Reason codes */ 204 #define IDC_DEVICE_STATE_CHANGE BIT_0 205 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 206 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 207 #define IDC_HEARTBEAT_FAILURE BIT_3 208 209 /* 83XX: Macros defining 8200 AEN Error-levels */ 210 #define ERR_LEVEL_NON_FATAL 0x1 211 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 212 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 213 214 /* 83XX: Macros for IDC Version */ 215 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 216 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 217 218 /* 83XX: Macros for scheduling dpc tasks */ 219 #define QLA83XX_NIC_CORE_RESET 0x1 220 #define QLA83XX_IDC_STATE_HANDLER 0x2 221 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 222 223 /* 83XX: Macros for defining IDC-Control bits */ 224 #define QLA83XX_IDC_RESET_DISABLED BIT_0 225 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 226 227 /* 83XX: Macros for different timeouts */ 228 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 229 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 230 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 231 232 /* 83XX: Macros for defining class in DEV-Partition Info register */ 233 #define QLA83XX_CLASS_TYPE_NONE 0x0 234 #define QLA83XX_CLASS_TYPE_NIC 0x1 235 #define QLA83XX_CLASS_TYPE_FCOE 0x2 236 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 237 238 /* 83XX: Macros for IDC Lock-Recovery stages */ 239 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 240 * lock-recovery 241 */ 242 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 243 244 /* 83XX: Macros for IDC Audit type */ 245 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 246 * dev-state change to NEED-RESET 247 * or NEED-QUIESCENT 248 */ 249 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 250 * reset-recovery completion is 251 * second 252 */ 253 /* ISP2031: Values for laser on/off */ 254 #define PORT_0_2031 0x00201340 255 #define PORT_1_2031 0x00201350 256 #define LASER_ON_2031 0x01800100 257 #define LASER_OFF_2031 0x01800180 258 259 /* 260 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 261 * 133Mhz slot. 262 */ 263 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 264 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr)) 265 266 /* 267 * Fibre Channel device definitions. 268 */ 269 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 270 #define MAX_FIBRE_DEVICES_2100 512 271 #define MAX_FIBRE_DEVICES_2400 2048 272 #define MAX_FIBRE_DEVICES_LOOP 128 273 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 274 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 275 #define MAX_FIBRE_LUNS 0xFFFF 276 #define MAX_HOST_COUNT 16 277 278 /* 279 * Host adapter default definitions. 280 */ 281 #define MAX_BUSES 1 /* We only have one bus today */ 282 #define MIN_LUNS 8 283 #define MAX_LUNS MAX_FIBRE_LUNS 284 #define MAX_CMDS_PER_LUN 255 285 286 /* 287 * Fibre Channel device definitions. 288 */ 289 #define SNS_LAST_LOOP_ID_2100 0xfe 290 #define SNS_LAST_LOOP_ID_2300 0x7ff 291 292 #define LAST_LOCAL_LOOP_ID 0x7d 293 #define SNS_FL_PORT 0x7e 294 #define FABRIC_CONTROLLER 0x7f 295 #define SIMPLE_NAME_SERVER 0x80 296 #define SNS_FIRST_LOOP_ID 0x81 297 #define MANAGEMENT_SERVER 0xfe 298 #define BROADCAST 0xff 299 300 /* 301 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 302 * valid range of an N-PORT id is 0 through 0x7ef. 303 */ 304 #define NPH_LAST_HANDLE 0x7ee 305 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ 306 #define NPH_SNS 0x7fc /* FFFFFC */ 307 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 308 #define NPH_F_PORT 0x7fe /* FFFFFE */ 309 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 310 311 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 312 313 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 314 #include "qla_fw.h" 315 316 struct name_list_extended { 317 struct get_name_list_extended *l; 318 dma_addr_t ldma; 319 struct list_head fcports; 320 u32 size; 321 u8 sent; 322 }; 323 /* 324 * Timeout timer counts in seconds 325 */ 326 #define PORT_RETRY_TIME 1 327 #define LOOP_DOWN_TIMEOUT 60 328 #define LOOP_DOWN_TIME 255 /* 240 */ 329 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 330 331 #define DEFAULT_OUTSTANDING_COMMANDS 4096 332 #define MIN_OUTSTANDING_COMMANDS 128 333 334 /* ISP request and response entry counts (37-65535) */ 335 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 336 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 337 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 338 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 339 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 340 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 341 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 342 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 343 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 344 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 345 #define FW_DEF_EXCHANGES_CNT 2048 346 #define FW_MAX_EXCHANGES_CNT (32 * 1024) 347 #define REDUCE_EXCHANGES_CNT (8 * 1024) 348 349 struct req_que; 350 struct qla_tgt_sess; 351 352 /* 353 * SCSI Request Block 354 */ 355 struct srb_cmd { 356 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 357 uint32_t request_sense_length; 358 uint32_t fw_sense_length; 359 uint8_t *request_sense_ptr; 360 struct ct6_dsd *ct6_ctx; 361 struct crc_context *crc_ctx; 362 }; 363 364 /* 365 * SRB flag definitions 366 */ 367 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 368 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 369 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 370 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 371 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 372 #define SRB_WAKEUP_ON_COMP BIT_6 373 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */ 374 375 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 376 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 377 378 /* 379 * 24 bit port ID type definition. 380 */ 381 typedef union { 382 uint32_t b24 : 24; 383 384 struct { 385 #ifdef __BIG_ENDIAN 386 uint8_t domain; 387 uint8_t area; 388 uint8_t al_pa; 389 #elif defined(__LITTLE_ENDIAN) 390 uint8_t al_pa; 391 uint8_t area; 392 uint8_t domain; 393 #else 394 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 395 #endif 396 uint8_t rsvd_1; 397 } b; 398 } port_id_t; 399 #define INVALID_PORT_ID 0xFFFFFF 400 401 static inline le_id_t be_id_to_le(be_id_t id) 402 { 403 le_id_t res; 404 405 res.domain = id.domain; 406 res.area = id.area; 407 res.al_pa = id.al_pa; 408 409 return res; 410 } 411 412 static inline be_id_t le_id_to_be(le_id_t id) 413 { 414 be_id_t res; 415 416 res.domain = id.domain; 417 res.area = id.area; 418 res.al_pa = id.al_pa; 419 420 return res; 421 } 422 423 static inline port_id_t be_to_port_id(be_id_t id) 424 { 425 port_id_t res; 426 427 res.b.domain = id.domain; 428 res.b.area = id.area; 429 res.b.al_pa = id.al_pa; 430 res.b.rsvd_1 = 0; 431 432 return res; 433 } 434 435 static inline be_id_t port_id_to_be_id(port_id_t port_id) 436 { 437 be_id_t res; 438 439 res.domain = port_id.b.domain; 440 res.area = port_id.b.area; 441 res.al_pa = port_id.b.al_pa; 442 443 return res; 444 } 445 446 struct els_logo_payload { 447 uint8_t opcode; 448 uint8_t rsvd[3]; 449 uint8_t s_id[3]; 450 uint8_t rsvd1[1]; 451 uint8_t wwpn[WWN_SIZE]; 452 }; 453 454 struct els_plogi_payload { 455 uint8_t opcode; 456 uint8_t rsvd[3]; 457 __be32 data[112 / 4]; 458 }; 459 460 struct ct_arg { 461 void *iocb; 462 u16 nport_handle; 463 dma_addr_t req_dma; 464 dma_addr_t rsp_dma; 465 u32 req_size; 466 u32 rsp_size; 467 u32 req_allocated_size; 468 u32 rsp_allocated_size; 469 void *req; 470 void *rsp; 471 port_id_t id; 472 }; 473 474 /* 475 * SRB extensions. 476 */ 477 struct srb_iocb { 478 union { 479 struct { 480 uint16_t flags; 481 #define SRB_LOGIN_RETRIED BIT_0 482 #define SRB_LOGIN_COND_PLOGI BIT_1 483 #define SRB_LOGIN_SKIP_PRLI BIT_2 484 #define SRB_LOGIN_NVME_PRLI BIT_3 485 #define SRB_LOGIN_PRLI_ONLY BIT_4 486 uint16_t data[2]; 487 u32 iop[2]; 488 } logio; 489 struct { 490 #define ELS_DCMD_TIMEOUT 20 491 #define ELS_DCMD_LOGO 0x5 492 uint32_t flags; 493 uint32_t els_cmd; 494 struct completion comp; 495 struct els_logo_payload *els_logo_pyld; 496 dma_addr_t els_logo_pyld_dma; 497 } els_logo; 498 struct els_plogi { 499 #define ELS_DCMD_PLOGI 0x3 500 uint32_t flags; 501 uint32_t els_cmd; 502 struct completion comp; 503 struct els_plogi_payload *els_plogi_pyld; 504 struct els_plogi_payload *els_resp_pyld; 505 u32 tx_size; 506 u32 rx_size; 507 dma_addr_t els_plogi_pyld_dma; 508 dma_addr_t els_resp_pyld_dma; 509 __le32 fw_status[3]; 510 __le16 comp_status; 511 __le16 len; 512 } els_plogi; 513 struct { 514 /* 515 * Values for flags field below are as 516 * defined in tsk_mgmt_entry struct 517 * for control_flags field in qla_fw.h. 518 */ 519 uint64_t lun; 520 uint32_t flags; 521 uint32_t data; 522 struct completion comp; 523 __le16 comp_status; 524 } tmf; 525 struct { 526 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 527 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 528 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 529 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 530 #define FXDISC_TIMEOUT 20 531 uint8_t flags; 532 uint32_t req_len; 533 uint32_t rsp_len; 534 void *req_addr; 535 void *rsp_addr; 536 dma_addr_t req_dma_handle; 537 dma_addr_t rsp_dma_handle; 538 __le32 adapter_id; 539 __le32 adapter_id_hi; 540 __le16 req_func_type; 541 __le32 req_data; 542 __le32 req_data_extra; 543 __le32 result; 544 __le32 seq_number; 545 __le16 fw_flags; 546 struct completion fxiocb_comp; 547 __le32 reserved_0; 548 uint8_t reserved_1; 549 } fxiocb; 550 struct { 551 uint32_t cmd_hndl; 552 __le16 comp_status; 553 __le16 req_que_no; 554 struct completion comp; 555 } abt; 556 struct ct_arg ctarg; 557 #define MAX_IOCB_MB_REG 28 558 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 559 struct { 560 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 561 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 562 void *out, *in; 563 dma_addr_t out_dma, in_dma; 564 struct completion comp; 565 int rc; 566 } mbx; 567 struct { 568 struct imm_ntfy_from_isp *ntfy; 569 } nack; 570 struct { 571 __le16 comp_status; 572 __le16 rsp_pyld_len; 573 uint8_t aen_op; 574 void *desc; 575 576 /* These are only used with ls4 requests */ 577 int cmd_len; 578 int rsp_len; 579 dma_addr_t cmd_dma; 580 dma_addr_t rsp_dma; 581 enum nvmefc_fcp_datadir dir; 582 uint32_t dl; 583 uint32_t timeout_sec; 584 struct list_head entry; 585 } nvme; 586 struct { 587 u16 cmd; 588 u16 vp_index; 589 } ctrlvp; 590 } u; 591 592 struct timer_list timer; 593 void (*timeout)(void *); 594 }; 595 596 /* Values for srb_ctx type */ 597 #define SRB_LOGIN_CMD 1 598 #define SRB_LOGOUT_CMD 2 599 #define SRB_ELS_CMD_RPT 3 600 #define SRB_ELS_CMD_HST 4 601 #define SRB_CT_CMD 5 602 #define SRB_ADISC_CMD 6 603 #define SRB_TM_CMD 7 604 #define SRB_SCSI_CMD 8 605 #define SRB_BIDI_CMD 9 606 #define SRB_FXIOCB_DCMD 10 607 #define SRB_FXIOCB_BCMD 11 608 #define SRB_ABT_CMD 12 609 #define SRB_ELS_DCMD 13 610 #define SRB_MB_IOCB 14 611 #define SRB_CT_PTHRU_CMD 15 612 #define SRB_NACK_PLOGI 16 613 #define SRB_NACK_PRLI 17 614 #define SRB_NACK_LOGO 18 615 #define SRB_NVME_CMD 19 616 #define SRB_NVME_LS 20 617 #define SRB_PRLI_CMD 21 618 #define SRB_CTRL_VP 22 619 #define SRB_PRLO_CMD 23 620 621 enum { 622 TYPE_SRB, 623 TYPE_TGT_CMD, 624 TYPE_TGT_TMCMD, /* task management */ 625 }; 626 627 typedef struct srb { 628 /* 629 * Do not move cmd_type field, it needs to 630 * line up with qla_tgt_cmd->cmd_type 631 */ 632 uint8_t cmd_type; 633 uint8_t pad[3]; 634 struct kref cmd_kref; /* need to migrate ref_count over to this */ 635 void *priv; 636 wait_queue_head_t nvme_ls_waitq; 637 struct fc_port *fcport; 638 struct scsi_qla_host *vha; 639 unsigned int start_timer:1; 640 641 uint32_t handle; 642 uint16_t flags; 643 uint16_t type; 644 const char *name; 645 int iocbs; 646 struct qla_qpair *qpair; 647 struct srb *cmd_sp; 648 struct list_head elem; 649 u32 gen1; /* scratch */ 650 u32 gen2; /* scratch */ 651 int rc; 652 int retry_count; 653 struct completion *comp; 654 union { 655 struct srb_iocb iocb_cmd; 656 struct bsg_job *bsg_job; 657 struct srb_cmd scmd; 658 } u; 659 /* 660 * Report completion status @res and call sp_put(@sp). @res is 661 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a 662 * QLA_* status value. 663 */ 664 void (*done)(struct srb *sp, int res); 665 /* Stop the timer and free @sp. Only used by the FCP code. */ 666 void (*free)(struct srb *sp); 667 /* 668 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe 669 * code. 670 */ 671 void (*put_fn)(struct kref *kref); 672 } srb_t; 673 674 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 675 676 #define GET_CMD_SENSE_LEN(sp) \ 677 (sp->u.scmd.request_sense_length) 678 #define SET_CMD_SENSE_LEN(sp, len) \ 679 (sp->u.scmd.request_sense_length = len) 680 #define GET_CMD_SENSE_PTR(sp) \ 681 (sp->u.scmd.request_sense_ptr) 682 #define SET_CMD_SENSE_PTR(sp, ptr) \ 683 (sp->u.scmd.request_sense_ptr = ptr) 684 #define GET_FW_SENSE_LEN(sp) \ 685 (sp->u.scmd.fw_sense_length) 686 #define SET_FW_SENSE_LEN(sp, len) \ 687 (sp->u.scmd.fw_sense_length = len) 688 689 struct msg_echo_lb { 690 dma_addr_t send_dma; 691 dma_addr_t rcv_dma; 692 uint16_t req_sg_cnt; 693 uint16_t rsp_sg_cnt; 694 uint16_t options; 695 uint32_t transfer_size; 696 uint32_t iteration_count; 697 }; 698 699 /* 700 * ISP I/O Register Set structure definitions. 701 */ 702 struct device_reg_2xxx { 703 __le16 flash_address; /* Flash BIOS address */ 704 __le16 flash_data; /* Flash BIOS data */ 705 __le16 unused_1[1]; /* Gap */ 706 __le16 ctrl_status; /* Control/Status */ 707 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 708 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 709 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 710 711 __le16 ictrl; /* Interrupt control */ 712 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 713 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 714 715 __le16 istatus; /* Interrupt status */ 716 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 717 718 __le16 semaphore; /* Semaphore */ 719 __le16 nvram; /* NVRAM register. */ 720 #define NVR_DESELECT 0 721 #define NVR_BUSY BIT_15 722 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 723 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 724 #define NVR_DATA_IN BIT_3 725 #define NVR_DATA_OUT BIT_2 726 #define NVR_SELECT BIT_1 727 #define NVR_CLOCK BIT_0 728 729 #define NVR_WAIT_CNT 20000 730 731 union { 732 struct { 733 __le16 mailbox0; 734 __le16 mailbox1; 735 __le16 mailbox2; 736 __le16 mailbox3; 737 __le16 mailbox4; 738 __le16 mailbox5; 739 __le16 mailbox6; 740 __le16 mailbox7; 741 __le16 unused_2[59]; /* Gap */ 742 } __attribute__((packed)) isp2100; 743 struct { 744 /* Request Queue */ 745 __le16 req_q_in; /* In-Pointer */ 746 __le16 req_q_out; /* Out-Pointer */ 747 /* Response Queue */ 748 __le16 rsp_q_in; /* In-Pointer */ 749 __le16 rsp_q_out; /* Out-Pointer */ 750 751 /* RISC to Host Status */ 752 __le32 host_status; 753 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 754 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 755 756 /* Host to Host Semaphore */ 757 __le16 host_semaphore; 758 __le16 unused_3[17]; /* Gap */ 759 __le16 mailbox0; 760 __le16 mailbox1; 761 __le16 mailbox2; 762 __le16 mailbox3; 763 __le16 mailbox4; 764 __le16 mailbox5; 765 __le16 mailbox6; 766 __le16 mailbox7; 767 __le16 mailbox8; 768 __le16 mailbox9; 769 __le16 mailbox10; 770 __le16 mailbox11; 771 __le16 mailbox12; 772 __le16 mailbox13; 773 __le16 mailbox14; 774 __le16 mailbox15; 775 __le16 mailbox16; 776 __le16 mailbox17; 777 __le16 mailbox18; 778 __le16 mailbox19; 779 __le16 mailbox20; 780 __le16 mailbox21; 781 __le16 mailbox22; 782 __le16 mailbox23; 783 __le16 mailbox24; 784 __le16 mailbox25; 785 __le16 mailbox26; 786 __le16 mailbox27; 787 __le16 mailbox28; 788 __le16 mailbox29; 789 __le16 mailbox30; 790 __le16 mailbox31; 791 __le16 fb_cmd; 792 __le16 unused_4[10]; /* Gap */ 793 } __attribute__((packed)) isp2300; 794 } u; 795 796 __le16 fpm_diag_config; 797 __le16 unused_5[0x4]; /* Gap */ 798 __le16 risc_hw; 799 __le16 unused_5_1; /* Gap */ 800 __le16 pcr; /* Processor Control Register. */ 801 __le16 unused_6[0x5]; /* Gap */ 802 __le16 mctr; /* Memory Configuration and Timing. */ 803 __le16 unused_7[0x3]; /* Gap */ 804 __le16 fb_cmd_2100; /* Unused on 23XX */ 805 __le16 unused_8[0x3]; /* Gap */ 806 __le16 hccr; /* Host command & control register. */ 807 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 808 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 809 /* HCCR commands */ 810 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 811 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 812 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 813 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 814 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 815 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 816 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 817 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 818 819 __le16 unused_9[5]; /* Gap */ 820 __le16 gpiod; /* GPIO Data register. */ 821 __le16 gpioe; /* GPIO Enable register. */ 822 #define GPIO_LED_MASK 0x00C0 823 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 824 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 825 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 826 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 827 #define GPIO_LED_ALL_OFF 0x0000 828 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 829 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 830 831 union { 832 struct { 833 __le16 unused_10[8]; /* Gap */ 834 __le16 mailbox8; 835 __le16 mailbox9; 836 __le16 mailbox10; 837 __le16 mailbox11; 838 __le16 mailbox12; 839 __le16 mailbox13; 840 __le16 mailbox14; 841 __le16 mailbox15; 842 __le16 mailbox16; 843 __le16 mailbox17; 844 __le16 mailbox18; 845 __le16 mailbox19; 846 __le16 mailbox20; 847 __le16 mailbox21; 848 __le16 mailbox22; 849 __le16 mailbox23; /* Also probe reg. */ 850 } __attribute__((packed)) isp2200; 851 } u_end; 852 }; 853 854 struct device_reg_25xxmq { 855 __le32 req_q_in; 856 __le32 req_q_out; 857 __le32 rsp_q_in; 858 __le32 rsp_q_out; 859 __le32 atio_q_in; 860 __le32 atio_q_out; 861 }; 862 863 864 struct device_reg_fx00 { 865 __le32 mailbox0; /* 00 */ 866 __le32 mailbox1; /* 04 */ 867 __le32 mailbox2; /* 08 */ 868 __le32 mailbox3; /* 0C */ 869 __le32 mailbox4; /* 10 */ 870 __le32 mailbox5; /* 14 */ 871 __le32 mailbox6; /* 18 */ 872 __le32 mailbox7; /* 1C */ 873 __le32 mailbox8; /* 20 */ 874 __le32 mailbox9; /* 24 */ 875 __le32 mailbox10; /* 28 */ 876 __le32 mailbox11; 877 __le32 mailbox12; 878 __le32 mailbox13; 879 __le32 mailbox14; 880 __le32 mailbox15; 881 __le32 mailbox16; 882 __le32 mailbox17; 883 __le32 mailbox18; 884 __le32 mailbox19; 885 __le32 mailbox20; 886 __le32 mailbox21; 887 __le32 mailbox22; 888 __le32 mailbox23; 889 __le32 mailbox24; 890 __le32 mailbox25; 891 __le32 mailbox26; 892 __le32 mailbox27; 893 __le32 mailbox28; 894 __le32 mailbox29; 895 __le32 mailbox30; 896 __le32 mailbox31; 897 __le32 aenmailbox0; 898 __le32 aenmailbox1; 899 __le32 aenmailbox2; 900 __le32 aenmailbox3; 901 __le32 aenmailbox4; 902 __le32 aenmailbox5; 903 __le32 aenmailbox6; 904 __le32 aenmailbox7; 905 /* Request Queue. */ 906 __le32 req_q_in; /* A0 - Request Queue In-Pointer */ 907 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */ 908 /* Response Queue. */ 909 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */ 910 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */ 911 /* Init values shadowed on FW Up Event */ 912 __le32 initval0; /* B0 */ 913 __le32 initval1; /* B4 */ 914 __le32 initval2; /* B8 */ 915 __le32 initval3; /* BC */ 916 __le32 initval4; /* C0 */ 917 __le32 initval5; /* C4 */ 918 __le32 initval6; /* C8 */ 919 __le32 initval7; /* CC */ 920 __le32 fwheartbeat; /* D0 */ 921 __le32 pseudoaen; /* D4 */ 922 }; 923 924 925 926 typedef union { 927 struct device_reg_2xxx isp; 928 struct device_reg_24xx isp24; 929 struct device_reg_25xxmq isp25mq; 930 struct device_reg_82xx isp82; 931 struct device_reg_fx00 ispfx00; 932 } __iomem device_reg_t; 933 934 #define ISP_REQ_Q_IN(ha, reg) \ 935 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 936 &(reg)->u.isp2100.mailbox4 : \ 937 &(reg)->u.isp2300.req_q_in) 938 #define ISP_REQ_Q_OUT(ha, reg) \ 939 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 940 &(reg)->u.isp2100.mailbox4 : \ 941 &(reg)->u.isp2300.req_q_out) 942 #define ISP_RSP_Q_IN(ha, reg) \ 943 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 944 &(reg)->u.isp2100.mailbox5 : \ 945 &(reg)->u.isp2300.rsp_q_in) 946 #define ISP_RSP_Q_OUT(ha, reg) \ 947 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 948 &(reg)->u.isp2100.mailbox5 : \ 949 &(reg)->u.isp2300.rsp_q_out) 950 951 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 952 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 953 954 #define MAILBOX_REG(ha, reg, num) \ 955 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 956 (num < 8 ? \ 957 &(reg)->u.isp2100.mailbox0 + (num) : \ 958 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 959 &(reg)->u.isp2300.mailbox0 + (num)) 960 #define RD_MAILBOX_REG(ha, reg, num) \ 961 rd_reg_word(MAILBOX_REG(ha, reg, num)) 962 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 963 wrt_reg_word(MAILBOX_REG(ha, reg, num), data) 964 965 #define FB_CMD_REG(ha, reg) \ 966 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 967 &(reg)->fb_cmd_2100 : \ 968 &(reg)->u.isp2300.fb_cmd) 969 #define RD_FB_CMD_REG(ha, reg) \ 970 rd_reg_word(FB_CMD_REG(ha, reg)) 971 #define WRT_FB_CMD_REG(ha, reg, data) \ 972 wrt_reg_word(FB_CMD_REG(ha, reg), data) 973 974 typedef struct { 975 uint32_t out_mb; /* outbound from driver */ 976 uint32_t in_mb; /* Incoming from RISC */ 977 uint16_t mb[MAILBOX_REGISTER_COUNT]; 978 long buf_size; 979 void *bufp; 980 uint32_t tov; 981 uint8_t flags; 982 #define MBX_DMA_IN BIT_0 983 #define MBX_DMA_OUT BIT_1 984 #define IOCTL_CMD BIT_2 985 } mbx_cmd_t; 986 987 struct mbx_cmd_32 { 988 uint32_t out_mb; /* outbound from driver */ 989 uint32_t in_mb; /* Incoming from RISC */ 990 uint32_t mb[MAILBOX_REGISTER_COUNT]; 991 long buf_size; 992 void *bufp; 993 uint32_t tov; 994 uint8_t flags; 995 #define MBX_DMA_IN BIT_0 996 #define MBX_DMA_OUT BIT_1 997 #define IOCTL_CMD BIT_2 998 }; 999 1000 1001 #define MBX_TOV_SECONDS 30 1002 1003 /* 1004 * ISP product identification definitions in mailboxes after reset. 1005 */ 1006 #define PROD_ID_1 0x4953 1007 #define PROD_ID_2 0x0000 1008 #define PROD_ID_2a 0x5020 1009 #define PROD_ID_3 0x2020 1010 1011 /* 1012 * ISP mailbox Self-Test status codes 1013 */ 1014 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 1015 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 1016 #define MBS_BUSY 4 /* Busy. */ 1017 1018 /* 1019 * ISP mailbox command complete status codes 1020 */ 1021 #define MBS_COMMAND_COMPLETE 0x4000 1022 #define MBS_INVALID_COMMAND 0x4001 1023 #define MBS_HOST_INTERFACE_ERROR 0x4002 1024 #define MBS_TEST_FAILED 0x4003 1025 #define MBS_COMMAND_ERROR 0x4005 1026 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 1027 #define MBS_PORT_ID_USED 0x4007 1028 #define MBS_LOOP_ID_USED 0x4008 1029 #define MBS_ALL_IDS_IN_USE 0x4009 1030 #define MBS_NOT_LOGGED_IN 0x400A 1031 #define MBS_LINK_DOWN_ERROR 0x400B 1032 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 1033 1034 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs) 1035 { 1036 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR; 1037 } 1038 1039 /* 1040 * ISP mailbox asynchronous event status codes 1041 */ 1042 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 1043 #define MBA_RESET 0x8001 /* Reset Detected. */ 1044 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 1045 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 1046 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 1047 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 1048 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 1049 /* occurred. */ 1050 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 1051 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 1052 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 1053 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 1054 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 1055 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 1056 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 1057 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 1058 #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */ 1059 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 1060 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 1061 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 1062 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 1063 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 1064 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 1065 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 1066 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 1067 /* used. */ 1068 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 1069 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 1070 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 1071 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 1072 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 1073 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 1074 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 1075 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 1076 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 1077 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 1078 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 1079 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 1080 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 1081 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 1082 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 1083 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 1084 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 1085 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 1086 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 1087 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 1088 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 1089 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 1090 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */ 1091 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 1092 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 1093 Notification */ 1094 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 1095 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 1096 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 1097 /* 83XX FCoE specific */ 1098 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 1099 1100 /* Interrupt type codes */ 1101 #define INTR_ROM_MB_SUCCESS 0x1 1102 #define INTR_ROM_MB_FAILED 0x2 1103 #define INTR_MB_SUCCESS 0x10 1104 #define INTR_MB_FAILED 0x11 1105 #define INTR_ASYNC_EVENT 0x12 1106 #define INTR_RSP_QUE_UPDATE 0x13 1107 #define INTR_RSP_QUE_UPDATE_83XX 0x14 1108 #define INTR_ATIO_QUE_UPDATE 0x1C 1109 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 1110 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 1111 1112 /* ISP mailbox loopback echo diagnostic error code */ 1113 #define MBS_LB_RESET 0x17 1114 /* 1115 * Firmware options 1, 2, 3. 1116 */ 1117 #define FO1_AE_ON_LIPF8 BIT_0 1118 #define FO1_AE_ALL_LIP_RESET BIT_1 1119 #define FO1_CTIO_RETRY BIT_3 1120 #define FO1_DISABLE_LIP_F7_SW BIT_4 1121 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 1122 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 1123 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 1124 #define FO1_SET_EMPHASIS_SWING BIT_8 1125 #define FO1_AE_AUTO_BYPASS BIT_9 1126 #define FO1_ENABLE_PURE_IOCB BIT_10 1127 #define FO1_AE_PLOGI_RJT BIT_11 1128 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 1129 #define FO1_AE_QUEUE_FULL BIT_13 1130 1131 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 1132 #define FO2_REV_LOOPBACK BIT_1 1133 1134 #define FO3_ENABLE_EMERG_IOCB BIT_0 1135 #define FO3_AE_RND_ERROR BIT_1 1136 1137 /* 24XX additional firmware options */ 1138 #define ADD_FO_COUNT 3 1139 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 1140 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 1141 1142 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 1143 1144 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 1145 1146 /* 1147 * ISP mailbox commands 1148 */ 1149 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1150 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1151 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 1152 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 1153 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1154 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 1155 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 1156 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 1157 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */ 1158 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 1159 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 1160 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 1161 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 1162 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 1163 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 1164 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 1165 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 1166 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1167 #define MBC_RESET 0x18 /* Reset. */ 1168 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1169 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1170 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1171 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1172 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1173 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1174 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1175 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1176 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */ 1177 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1178 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1179 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1180 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1181 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1182 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1183 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1184 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1185 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1186 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1187 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1188 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1189 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1190 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1191 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1192 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1193 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1194 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1195 /* Initialization Procedure */ 1196 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1197 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1198 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1199 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1200 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1201 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1202 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1203 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1204 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1205 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1206 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1207 /* commandd. */ 1208 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1209 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1210 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1211 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1212 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1213 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1214 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1215 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1216 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1217 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1218 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1219 1220 /* 1221 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1222 * should be defined with MBC_MR_* 1223 */ 1224 #define MBC_MR_DRV_SHUTDOWN 0x6A 1225 1226 /* 1227 * ISP24xx mailbox commands 1228 */ 1229 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1230 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1231 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1232 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1233 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1234 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1235 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1236 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1237 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1238 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1239 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1240 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1241 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1242 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1243 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1244 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1245 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1246 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1247 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1248 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1249 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1250 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1251 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1252 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1253 1254 /* 1255 * ISP81xx mailbox commands 1256 */ 1257 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1258 1259 /* 1260 * ISP8044 mailbox commands 1261 */ 1262 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1263 #define HCS_WRITE_SERDES 0x3 1264 #define HCS_READ_SERDES 0x4 1265 1266 /* Firmware return data sizes */ 1267 #define FCAL_MAP_SIZE 128 1268 1269 /* Mailbox bit definitions for out_mb and in_mb */ 1270 #define MBX_31 BIT_31 1271 #define MBX_30 BIT_30 1272 #define MBX_29 BIT_29 1273 #define MBX_28 BIT_28 1274 #define MBX_27 BIT_27 1275 #define MBX_26 BIT_26 1276 #define MBX_25 BIT_25 1277 #define MBX_24 BIT_24 1278 #define MBX_23 BIT_23 1279 #define MBX_22 BIT_22 1280 #define MBX_21 BIT_21 1281 #define MBX_20 BIT_20 1282 #define MBX_19 BIT_19 1283 #define MBX_18 BIT_18 1284 #define MBX_17 BIT_17 1285 #define MBX_16 BIT_16 1286 #define MBX_15 BIT_15 1287 #define MBX_14 BIT_14 1288 #define MBX_13 BIT_13 1289 #define MBX_12 BIT_12 1290 #define MBX_11 BIT_11 1291 #define MBX_10 BIT_10 1292 #define MBX_9 BIT_9 1293 #define MBX_8 BIT_8 1294 #define MBX_7 BIT_7 1295 #define MBX_6 BIT_6 1296 #define MBX_5 BIT_5 1297 #define MBX_4 BIT_4 1298 #define MBX_3 BIT_3 1299 #define MBX_2 BIT_2 1300 #define MBX_1 BIT_1 1301 #define MBX_0 BIT_0 1302 1303 #define RNID_TYPE_ELS_CMD 0x5 1304 #define RNID_TYPE_PORT_LOGIN 0x7 1305 #define RNID_BUFFER_CREDITS 0x8 1306 #define RNID_TYPE_SET_VERSION 0x9 1307 #define RNID_TYPE_ASIC_TEMP 0xC 1308 1309 #define ELS_CMD_MAP_SIZE 32 1310 1311 /* 1312 * Firmware state codes from get firmware state mailbox command 1313 */ 1314 #define FSTATE_CONFIG_WAIT 0 1315 #define FSTATE_WAIT_AL_PA 1 1316 #define FSTATE_WAIT_LOGIN 2 1317 #define FSTATE_READY 3 1318 #define FSTATE_LOSS_OF_SYNC 4 1319 #define FSTATE_ERROR 5 1320 #define FSTATE_REINIT 6 1321 #define FSTATE_NON_PART 7 1322 1323 #define FSTATE_CONFIG_CORRECT 0 1324 #define FSTATE_P2P_RCV_LIP 1 1325 #define FSTATE_P2P_CHOOSE_LOOP 2 1326 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1327 #define FSTATE_FATAL_ERROR 4 1328 #define FSTATE_LOOP_BACK_CONN 5 1329 1330 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1331 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1332 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1333 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1334 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1335 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED 1336 #define QLA27XX_DEFAULT_IMAGE 0 1337 #define QLA27XX_PRIMARY_IMAGE 1 1338 #define QLA27XX_SECONDARY_IMAGE 2 1339 1340 /* 1341 * Port Database structure definition 1342 * Little endian except where noted. 1343 */ 1344 #define PORT_DATABASE_SIZE 128 /* bytes */ 1345 typedef struct { 1346 uint8_t options; 1347 uint8_t control; 1348 uint8_t master_state; 1349 uint8_t slave_state; 1350 uint8_t reserved[2]; 1351 uint8_t hard_address; 1352 uint8_t reserved_1; 1353 uint8_t port_id[4]; 1354 uint8_t node_name[WWN_SIZE]; 1355 uint8_t port_name[WWN_SIZE]; 1356 __le16 execution_throttle; 1357 uint16_t execution_count; 1358 uint8_t reset_count; 1359 uint8_t reserved_2; 1360 uint16_t resource_allocation; 1361 uint16_t current_allocation; 1362 uint16_t queue_head; 1363 uint16_t queue_tail; 1364 uint16_t transmit_execution_list_next; 1365 uint16_t transmit_execution_list_previous; 1366 uint16_t common_features; 1367 uint16_t total_concurrent_sequences; 1368 uint16_t RO_by_information_category; 1369 uint8_t recipient; 1370 uint8_t initiator; 1371 uint16_t receive_data_size; 1372 uint16_t concurrent_sequences; 1373 uint16_t open_sequences_per_exchange; 1374 uint16_t lun_abort_flags; 1375 uint16_t lun_stop_flags; 1376 uint16_t stop_queue_head; 1377 uint16_t stop_queue_tail; 1378 uint16_t port_retry_timer; 1379 uint16_t next_sequence_id; 1380 uint16_t frame_count; 1381 uint16_t PRLI_payload_length; 1382 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1383 /* Bits 15-0 of word 0 */ 1384 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1385 /* Bits 15-0 of word 3 */ 1386 uint16_t loop_id; 1387 uint16_t extended_lun_info_list_pointer; 1388 uint16_t extended_lun_stop_list_pointer; 1389 } port_database_t; 1390 1391 /* 1392 * Port database slave/master states 1393 */ 1394 #define PD_STATE_DISCOVERY 0 1395 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1396 #define PD_STATE_PORT_LOGIN 2 1397 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1398 #define PD_STATE_PROCESS_LOGIN 4 1399 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1400 #define PD_STATE_PORT_LOGGED_IN 6 1401 #define PD_STATE_PORT_UNAVAILABLE 7 1402 #define PD_STATE_PROCESS_LOGOUT 8 1403 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1404 #define PD_STATE_PORT_LOGOUT 10 1405 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1406 1407 1408 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1409 #define QLA_ZIO_DISABLED 0 1410 #define QLA_ZIO_DEFAULT_TIMER 2 1411 1412 /* 1413 * ISP Initialization Control Block. 1414 * Little endian except where noted. 1415 */ 1416 #define ICB_VERSION 1 1417 typedef struct { 1418 uint8_t version; 1419 uint8_t reserved_1; 1420 1421 /* 1422 * LSB BIT 0 = Enable Hard Loop Id 1423 * LSB BIT 1 = Enable Fairness 1424 * LSB BIT 2 = Enable Full-Duplex 1425 * LSB BIT 3 = Enable Fast Posting 1426 * LSB BIT 4 = Enable Target Mode 1427 * LSB BIT 5 = Disable Initiator Mode 1428 * LSB BIT 6 = Enable ADISC 1429 * LSB BIT 7 = Enable Target Inquiry Data 1430 * 1431 * MSB BIT 0 = Enable PDBC Notify 1432 * MSB BIT 1 = Non Participating LIP 1433 * MSB BIT 2 = Descending Loop ID Search 1434 * MSB BIT 3 = Acquire Loop ID in LIPA 1435 * MSB BIT 4 = Stop PortQ on Full Status 1436 * MSB BIT 5 = Full Login after LIP 1437 * MSB BIT 6 = Node Name Option 1438 * MSB BIT 7 = Ext IFWCB enable bit 1439 */ 1440 uint8_t firmware_options[2]; 1441 1442 __le16 frame_payload_size; 1443 __le16 max_iocb_allocation; 1444 __le16 execution_throttle; 1445 uint8_t retry_count; 1446 uint8_t retry_delay; /* unused */ 1447 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1448 uint16_t hard_address; 1449 uint8_t inquiry_data; 1450 uint8_t login_timeout; 1451 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1452 1453 __le16 request_q_outpointer; 1454 __le16 response_q_inpointer; 1455 __le16 request_q_length; 1456 __le16 response_q_length; 1457 __le64 request_q_address __packed; 1458 __le64 response_q_address __packed; 1459 1460 __le16 lun_enables; 1461 uint8_t command_resource_count; 1462 uint8_t immediate_notify_resource_count; 1463 __le16 timeout; 1464 uint8_t reserved_2[2]; 1465 1466 /* 1467 * LSB BIT 0 = Timer Operation mode bit 0 1468 * LSB BIT 1 = Timer Operation mode bit 1 1469 * LSB BIT 2 = Timer Operation mode bit 2 1470 * LSB BIT 3 = Timer Operation mode bit 3 1471 * LSB BIT 4 = Init Config Mode bit 0 1472 * LSB BIT 5 = Init Config Mode bit 1 1473 * LSB BIT 6 = Init Config Mode bit 2 1474 * LSB BIT 7 = Enable Non part on LIHA failure 1475 * 1476 * MSB BIT 0 = Enable class 2 1477 * MSB BIT 1 = Enable ACK0 1478 * MSB BIT 2 = 1479 * MSB BIT 3 = 1480 * MSB BIT 4 = FC Tape Enable 1481 * MSB BIT 5 = Enable FC Confirm 1482 * MSB BIT 6 = Enable command queuing in target mode 1483 * MSB BIT 7 = No Logo On Link Down 1484 */ 1485 uint8_t add_firmware_options[2]; 1486 1487 uint8_t response_accumulation_timer; 1488 uint8_t interrupt_delay_timer; 1489 1490 /* 1491 * LSB BIT 0 = Enable Read xfr_rdy 1492 * LSB BIT 1 = Soft ID only 1493 * LSB BIT 2 = 1494 * LSB BIT 3 = 1495 * LSB BIT 4 = FCP RSP Payload [0] 1496 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1497 * LSB BIT 6 = Enable Out-of-Order frame handling 1498 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1499 * 1500 * MSB BIT 0 = Sbus enable - 2300 1501 * MSB BIT 1 = 1502 * MSB BIT 2 = 1503 * MSB BIT 3 = 1504 * MSB BIT 4 = LED mode 1505 * MSB BIT 5 = enable 50 ohm termination 1506 * MSB BIT 6 = Data Rate (2300 only) 1507 * MSB BIT 7 = Data Rate (2300 only) 1508 */ 1509 uint8_t special_options[2]; 1510 1511 uint8_t reserved_3[26]; 1512 } init_cb_t; 1513 1514 /* Special Features Control Block */ 1515 struct init_sf_cb { 1516 uint8_t format; 1517 uint8_t reserved0; 1518 /* 1519 * BIT 15-14 = Reserved 1520 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled) 1521 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled) 1522 * BIT 11-0 = Reserved 1523 */ 1524 uint16_t flags; 1525 uint8_t reserved1[32]; 1526 uint16_t discard_OHRB_timeout_value; 1527 uint16_t remote_write_opt_queue_num; 1528 uint8_t reserved2[40]; 1529 uint8_t scm_related_parameter[16]; 1530 uint8_t reserved3[32]; 1531 }; 1532 1533 /* 1534 * Get Link Status mailbox command return buffer. 1535 */ 1536 #define GLSO_SEND_RPS BIT_0 1537 #define GLSO_USE_DID BIT_3 1538 1539 struct link_statistics { 1540 __le32 link_fail_cnt; 1541 __le32 loss_sync_cnt; 1542 __le32 loss_sig_cnt; 1543 __le32 prim_seq_err_cnt; 1544 __le32 inval_xmit_word_cnt; 1545 __le32 inval_crc_cnt; 1546 __le32 lip_cnt; 1547 __le32 link_up_cnt; 1548 __le32 link_down_loop_init_tmo; 1549 __le32 link_down_los; 1550 __le32 link_down_loss_rcv_clk; 1551 uint32_t reserved0[5]; 1552 __le32 port_cfg_chg; 1553 uint32_t reserved1[11]; 1554 __le32 rsp_q_full; 1555 __le32 atio_q_full; 1556 __le32 drop_ae; 1557 __le32 els_proto_err; 1558 __le32 reserved2; 1559 __le32 tx_frames; 1560 __le32 rx_frames; 1561 __le32 discarded_frames; 1562 __le32 dropped_frames; 1563 uint32_t reserved3; 1564 __le32 nos_rcvd; 1565 uint32_t reserved4[4]; 1566 __le32 tx_prjt; 1567 __le32 rcv_exfail; 1568 __le32 rcv_abts; 1569 __le32 seq_frm_miss; 1570 __le32 corr_err; 1571 __le32 mb_rqst; 1572 __le32 nport_full; 1573 __le32 eofa; 1574 uint32_t reserved5; 1575 __le64 fpm_recv_word_cnt; 1576 __le64 fpm_disc_word_cnt; 1577 __le64 fpm_xmit_word_cnt; 1578 uint32_t reserved6[70]; 1579 }; 1580 1581 /* 1582 * NVRAM Command values. 1583 */ 1584 #define NV_START_BIT BIT_2 1585 #define NV_WRITE_OP (BIT_26+BIT_24) 1586 #define NV_READ_OP (BIT_26+BIT_25) 1587 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1588 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1589 #define NV_DELAY_COUNT 10 1590 1591 /* 1592 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1593 */ 1594 typedef struct { 1595 /* 1596 * NVRAM header 1597 */ 1598 uint8_t id[4]; 1599 uint8_t nvram_version; 1600 uint8_t reserved_0; 1601 1602 /* 1603 * NVRAM RISC parameter block 1604 */ 1605 uint8_t parameter_block_version; 1606 uint8_t reserved_1; 1607 1608 /* 1609 * LSB BIT 0 = Enable Hard Loop Id 1610 * LSB BIT 1 = Enable Fairness 1611 * LSB BIT 2 = Enable Full-Duplex 1612 * LSB BIT 3 = Enable Fast Posting 1613 * LSB BIT 4 = Enable Target Mode 1614 * LSB BIT 5 = Disable Initiator Mode 1615 * LSB BIT 6 = Enable ADISC 1616 * LSB BIT 7 = Enable Target Inquiry Data 1617 * 1618 * MSB BIT 0 = Enable PDBC Notify 1619 * MSB BIT 1 = Non Participating LIP 1620 * MSB BIT 2 = Descending Loop ID Search 1621 * MSB BIT 3 = Acquire Loop ID in LIPA 1622 * MSB BIT 4 = Stop PortQ on Full Status 1623 * MSB BIT 5 = Full Login after LIP 1624 * MSB BIT 6 = Node Name Option 1625 * MSB BIT 7 = Ext IFWCB enable bit 1626 */ 1627 uint8_t firmware_options[2]; 1628 1629 uint16_t frame_payload_size; 1630 __le16 max_iocb_allocation; 1631 __le16 execution_throttle; 1632 uint8_t retry_count; 1633 uint8_t retry_delay; /* unused */ 1634 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1635 uint16_t hard_address; 1636 uint8_t inquiry_data; 1637 uint8_t login_timeout; 1638 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1639 1640 /* 1641 * LSB BIT 0 = Timer Operation mode bit 0 1642 * LSB BIT 1 = Timer Operation mode bit 1 1643 * LSB BIT 2 = Timer Operation mode bit 2 1644 * LSB BIT 3 = Timer Operation mode bit 3 1645 * LSB BIT 4 = Init Config Mode bit 0 1646 * LSB BIT 5 = Init Config Mode bit 1 1647 * LSB BIT 6 = Init Config Mode bit 2 1648 * LSB BIT 7 = Enable Non part on LIHA failure 1649 * 1650 * MSB BIT 0 = Enable class 2 1651 * MSB BIT 1 = Enable ACK0 1652 * MSB BIT 2 = 1653 * MSB BIT 3 = 1654 * MSB BIT 4 = FC Tape Enable 1655 * MSB BIT 5 = Enable FC Confirm 1656 * MSB BIT 6 = Enable command queuing in target mode 1657 * MSB BIT 7 = No Logo On Link Down 1658 */ 1659 uint8_t add_firmware_options[2]; 1660 1661 uint8_t response_accumulation_timer; 1662 uint8_t interrupt_delay_timer; 1663 1664 /* 1665 * LSB BIT 0 = Enable Read xfr_rdy 1666 * LSB BIT 1 = Soft ID only 1667 * LSB BIT 2 = 1668 * LSB BIT 3 = 1669 * LSB BIT 4 = FCP RSP Payload [0] 1670 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1671 * LSB BIT 6 = Enable Out-of-Order frame handling 1672 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1673 * 1674 * MSB BIT 0 = Sbus enable - 2300 1675 * MSB BIT 1 = 1676 * MSB BIT 2 = 1677 * MSB BIT 3 = 1678 * MSB BIT 4 = LED mode 1679 * MSB BIT 5 = enable 50 ohm termination 1680 * MSB BIT 6 = Data Rate (2300 only) 1681 * MSB BIT 7 = Data Rate (2300 only) 1682 */ 1683 uint8_t special_options[2]; 1684 1685 /* Reserved for expanded RISC parameter block */ 1686 uint8_t reserved_2[22]; 1687 1688 /* 1689 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1690 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1691 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1692 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1693 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1694 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1695 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1696 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1697 * 1698 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1699 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1700 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1701 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1702 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1703 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1704 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1705 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1706 * 1707 * LSB BIT 0 = Output Swing 1G bit 0 1708 * LSB BIT 1 = Output Swing 1G bit 1 1709 * LSB BIT 2 = Output Swing 1G bit 2 1710 * LSB BIT 3 = Output Emphasis 1G bit 0 1711 * LSB BIT 4 = Output Emphasis 1G bit 1 1712 * LSB BIT 5 = Output Swing 2G bit 0 1713 * LSB BIT 6 = Output Swing 2G bit 1 1714 * LSB BIT 7 = Output Swing 2G bit 2 1715 * 1716 * MSB BIT 0 = Output Emphasis 2G bit 0 1717 * MSB BIT 1 = Output Emphasis 2G bit 1 1718 * MSB BIT 2 = Output Enable 1719 * MSB BIT 3 = 1720 * MSB BIT 4 = 1721 * MSB BIT 5 = 1722 * MSB BIT 6 = 1723 * MSB BIT 7 = 1724 */ 1725 uint8_t seriallink_options[4]; 1726 1727 /* 1728 * NVRAM host parameter block 1729 * 1730 * LSB BIT 0 = Enable spinup delay 1731 * LSB BIT 1 = Disable BIOS 1732 * LSB BIT 2 = Enable Memory Map BIOS 1733 * LSB BIT 3 = Enable Selectable Boot 1734 * LSB BIT 4 = Disable RISC code load 1735 * LSB BIT 5 = Set cache line size 1 1736 * LSB BIT 6 = PCI Parity Disable 1737 * LSB BIT 7 = Enable extended logging 1738 * 1739 * MSB BIT 0 = Enable 64bit addressing 1740 * MSB BIT 1 = Enable lip reset 1741 * MSB BIT 2 = Enable lip full login 1742 * MSB BIT 3 = Enable target reset 1743 * MSB BIT 4 = Enable database storage 1744 * MSB BIT 5 = Enable cache flush read 1745 * MSB BIT 6 = Enable database load 1746 * MSB BIT 7 = Enable alternate WWN 1747 */ 1748 uint8_t host_p[2]; 1749 1750 uint8_t boot_node_name[WWN_SIZE]; 1751 uint8_t boot_lun_number; 1752 uint8_t reset_delay; 1753 uint8_t port_down_retry_count; 1754 uint8_t boot_id_number; 1755 __le16 max_luns_per_target; 1756 uint8_t fcode_boot_port_name[WWN_SIZE]; 1757 uint8_t alternate_port_name[WWN_SIZE]; 1758 uint8_t alternate_node_name[WWN_SIZE]; 1759 1760 /* 1761 * BIT 0 = Selective Login 1762 * BIT 1 = Alt-Boot Enable 1763 * BIT 2 = 1764 * BIT 3 = Boot Order List 1765 * BIT 4 = 1766 * BIT 5 = Selective LUN 1767 * BIT 6 = 1768 * BIT 7 = unused 1769 */ 1770 uint8_t efi_parameters; 1771 1772 uint8_t link_down_timeout; 1773 1774 uint8_t adapter_id[16]; 1775 1776 uint8_t alt1_boot_node_name[WWN_SIZE]; 1777 uint16_t alt1_boot_lun_number; 1778 uint8_t alt2_boot_node_name[WWN_SIZE]; 1779 uint16_t alt2_boot_lun_number; 1780 uint8_t alt3_boot_node_name[WWN_SIZE]; 1781 uint16_t alt3_boot_lun_number; 1782 uint8_t alt4_boot_node_name[WWN_SIZE]; 1783 uint16_t alt4_boot_lun_number; 1784 uint8_t alt5_boot_node_name[WWN_SIZE]; 1785 uint16_t alt5_boot_lun_number; 1786 uint8_t alt6_boot_node_name[WWN_SIZE]; 1787 uint16_t alt6_boot_lun_number; 1788 uint8_t alt7_boot_node_name[WWN_SIZE]; 1789 uint16_t alt7_boot_lun_number; 1790 1791 uint8_t reserved_3[2]; 1792 1793 /* Offset 200-215 : Model Number */ 1794 uint8_t model_number[16]; 1795 1796 /* OEM related items */ 1797 uint8_t oem_specific[16]; 1798 1799 /* 1800 * NVRAM Adapter Features offset 232-239 1801 * 1802 * LSB BIT 0 = External GBIC 1803 * LSB BIT 1 = Risc RAM parity 1804 * LSB BIT 2 = Buffer Plus Module 1805 * LSB BIT 3 = Multi Chip Adapter 1806 * LSB BIT 4 = Internal connector 1807 * LSB BIT 5 = 1808 * LSB BIT 6 = 1809 * LSB BIT 7 = 1810 * 1811 * MSB BIT 0 = 1812 * MSB BIT 1 = 1813 * MSB BIT 2 = 1814 * MSB BIT 3 = 1815 * MSB BIT 4 = 1816 * MSB BIT 5 = 1817 * MSB BIT 6 = 1818 * MSB BIT 7 = 1819 */ 1820 uint8_t adapter_features[2]; 1821 1822 uint8_t reserved_4[16]; 1823 1824 /* Subsystem vendor ID for ISP2200 */ 1825 uint16_t subsystem_vendor_id_2200; 1826 1827 /* Subsystem device ID for ISP2200 */ 1828 uint16_t subsystem_device_id_2200; 1829 1830 uint8_t reserved_5; 1831 uint8_t checksum; 1832 } nvram_t; 1833 1834 /* 1835 * ISP queue - response queue entry definition. 1836 */ 1837 typedef struct { 1838 uint8_t entry_type; /* Entry type. */ 1839 uint8_t entry_count; /* Entry count. */ 1840 uint8_t sys_define; /* System defined. */ 1841 uint8_t entry_status; /* Entry Status. */ 1842 uint32_t handle; /* System defined handle */ 1843 uint8_t data[52]; 1844 uint32_t signature; 1845 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1846 } response_t; 1847 1848 /* 1849 * ISP queue - ATIO queue entry definition. 1850 */ 1851 struct atio { 1852 uint8_t entry_type; /* Entry type. */ 1853 uint8_t entry_count; /* Entry count. */ 1854 __le16 attr_n_length; 1855 uint8_t data[56]; 1856 uint32_t signature; 1857 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1858 }; 1859 1860 typedef union { 1861 __le16 extended; 1862 struct { 1863 uint8_t reserved; 1864 uint8_t standard; 1865 } id; 1866 } target_id_t; 1867 1868 #define SET_TARGET_ID(ha, to, from) \ 1869 do { \ 1870 if (HAS_EXTENDED_IDS(ha)) \ 1871 to.extended = cpu_to_le16(from); \ 1872 else \ 1873 to.id.standard = (uint8_t)from; \ 1874 } while (0) 1875 1876 /* 1877 * ISP queue - command entry structure definition. 1878 */ 1879 #define COMMAND_TYPE 0x11 /* Command entry */ 1880 typedef struct { 1881 uint8_t entry_type; /* Entry type. */ 1882 uint8_t entry_count; /* Entry count. */ 1883 uint8_t sys_define; /* System defined. */ 1884 uint8_t entry_status; /* Entry Status. */ 1885 uint32_t handle; /* System handle. */ 1886 target_id_t target; /* SCSI ID */ 1887 __le16 lun; /* SCSI LUN */ 1888 __le16 control_flags; /* Control flags. */ 1889 #define CF_WRITE BIT_6 1890 #define CF_READ BIT_5 1891 #define CF_SIMPLE_TAG BIT_3 1892 #define CF_ORDERED_TAG BIT_2 1893 #define CF_HEAD_TAG BIT_1 1894 uint16_t reserved_1; 1895 __le16 timeout; /* Command timeout. */ 1896 __le16 dseg_count; /* Data segment count. */ 1897 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1898 __le32 byte_count; /* Total byte count. */ 1899 union { 1900 struct dsd32 dsd32[3]; 1901 struct dsd64 dsd64[2]; 1902 }; 1903 } cmd_entry_t; 1904 1905 /* 1906 * ISP queue - 64-Bit addressing, command entry structure definition. 1907 */ 1908 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1909 typedef struct { 1910 uint8_t entry_type; /* Entry type. */ 1911 uint8_t entry_count; /* Entry count. */ 1912 uint8_t sys_define; /* System defined. */ 1913 uint8_t entry_status; /* Entry Status. */ 1914 uint32_t handle; /* System handle. */ 1915 target_id_t target; /* SCSI ID */ 1916 __le16 lun; /* SCSI LUN */ 1917 __le16 control_flags; /* Control flags. */ 1918 uint16_t reserved_1; 1919 __le16 timeout; /* Command timeout. */ 1920 __le16 dseg_count; /* Data segment count. */ 1921 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1922 uint32_t byte_count; /* Total byte count. */ 1923 struct dsd64 dsd[2]; 1924 } cmd_a64_entry_t, request_t; 1925 1926 /* 1927 * ISP queue - continuation entry structure definition. 1928 */ 1929 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1930 typedef struct { 1931 uint8_t entry_type; /* Entry type. */ 1932 uint8_t entry_count; /* Entry count. */ 1933 uint8_t sys_define; /* System defined. */ 1934 uint8_t entry_status; /* Entry Status. */ 1935 uint32_t reserved; 1936 struct dsd32 dsd[7]; 1937 } cont_entry_t; 1938 1939 /* 1940 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1941 */ 1942 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1943 typedef struct { 1944 uint8_t entry_type; /* Entry type. */ 1945 uint8_t entry_count; /* Entry count. */ 1946 uint8_t sys_define; /* System defined. */ 1947 uint8_t entry_status; /* Entry Status. */ 1948 struct dsd64 dsd[5]; 1949 } cont_a64_entry_t; 1950 1951 #define PO_MODE_DIF_INSERT 0 1952 #define PO_MODE_DIF_REMOVE 1 1953 #define PO_MODE_DIF_PASS 2 1954 #define PO_MODE_DIF_REPLACE 3 1955 #define PO_MODE_DIF_TCP_CKSUM 6 1956 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1957 #define PO_DISABLE_GUARD_CHECK BIT_4 1958 #define PO_DISABLE_INCR_REF_TAG BIT_5 1959 #define PO_DIS_HEADER_MODE BIT_7 1960 #define PO_ENABLE_DIF_BUNDLING BIT_8 1961 #define PO_DIS_FRAME_MODE BIT_9 1962 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1963 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1964 1965 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1966 #define PO_DIS_REF_TAG_REPL BIT_13 1967 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1968 #define PO_DIS_REF_TAG_VALD BIT_15 1969 1970 /* 1971 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1972 */ 1973 struct crc_context { 1974 uint32_t handle; /* System handle. */ 1975 __le32 ref_tag; 1976 __le16 app_tag; 1977 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1978 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1979 __le16 guard_seed; /* Initial Guard Seed */ 1980 __le16 prot_opts; /* Requested Data Protection Mode */ 1981 __le16 blk_size; /* Data size in bytes */ 1982 __le16 runt_blk_guard; /* Guard value for runt block (tape 1983 * only) */ 1984 __le32 byte_count; /* Total byte count/ total data 1985 * transfer count */ 1986 union { 1987 struct { 1988 uint32_t reserved_1; 1989 uint16_t reserved_2; 1990 uint16_t reserved_3; 1991 uint32_t reserved_4; 1992 struct dsd64 data_dsd[1]; 1993 uint32_t reserved_5[2]; 1994 uint32_t reserved_6; 1995 } nobundling; 1996 struct { 1997 __le32 dif_byte_count; /* Total DIF byte 1998 * count */ 1999 uint16_t reserved_1; 2000 __le16 dseg_count; /* Data segment count */ 2001 uint32_t reserved_2; 2002 struct dsd64 data_dsd[1]; 2003 struct dsd64 dif_dsd; 2004 } bundling; 2005 } u; 2006 2007 struct fcp_cmnd fcp_cmnd; 2008 dma_addr_t crc_ctx_dma; 2009 /* List of DMA context transfers */ 2010 struct list_head dsd_list; 2011 2012 /* List of DIF Bundling context DMA address */ 2013 struct list_head ldif_dsd_list; 2014 u8 no_ldif_dsd; 2015 2016 struct list_head ldif_dma_hndl_list; 2017 u32 dif_bundl_len; 2018 u8 no_dif_bundl; 2019 /* This structure should not exceed 512 bytes */ 2020 }; 2021 2022 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 2023 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 2024 2025 /* 2026 * ISP queue - status entry structure definition. 2027 */ 2028 #define STATUS_TYPE 0x03 /* Status entry. */ 2029 typedef struct { 2030 uint8_t entry_type; /* Entry type. */ 2031 uint8_t entry_count; /* Entry count. */ 2032 uint8_t sys_define; /* System defined. */ 2033 uint8_t entry_status; /* Entry Status. */ 2034 uint32_t handle; /* System handle. */ 2035 __le16 scsi_status; /* SCSI status. */ 2036 __le16 comp_status; /* Completion status. */ 2037 __le16 state_flags; /* State flags. */ 2038 __le16 status_flags; /* Status flags. */ 2039 __le16 rsp_info_len; /* Response Info Length. */ 2040 __le16 req_sense_length; /* Request sense data length. */ 2041 __le32 residual_length; /* Residual transfer length. */ 2042 uint8_t rsp_info[8]; /* FCP response information. */ 2043 uint8_t req_sense_data[32]; /* Request sense data. */ 2044 } sts_entry_t; 2045 2046 /* 2047 * Status entry entry status 2048 */ 2049 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 2050 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 2051 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 2052 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 2053 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 2054 #define RF_BUSY BIT_1 /* Busy */ 2055 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 2056 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 2057 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 2058 RF_INV_E_TYPE) 2059 2060 /* 2061 * Status entry SCSI status bit definitions. 2062 */ 2063 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 2064 #define SS_RESIDUAL_UNDER BIT_11 2065 #define SS_RESIDUAL_OVER BIT_10 2066 #define SS_SENSE_LEN_VALID BIT_9 2067 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 2068 #define SS_SCSI_STATUS_BYTE 0xff 2069 2070 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 2071 #define SS_BUSY_CONDITION BIT_3 2072 #define SS_CONDITION_MET BIT_2 2073 #define SS_CHECK_CONDITION BIT_1 2074 2075 /* 2076 * Status entry completion status 2077 */ 2078 #define CS_COMPLETE 0x0 /* No errors */ 2079 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 2080 #define CS_DMA 0x2 /* A DMA direction error. */ 2081 #define CS_TRANSPORT 0x3 /* Transport error. */ 2082 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 2083 #define CS_ABORTED 0x5 /* System aborted command. */ 2084 #define CS_TIMEOUT 0x6 /* Timeout error. */ 2085 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 2086 #define CS_DIF_ERROR 0xC /* DIF error detected */ 2087 2088 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 2089 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 2090 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 2091 /* (selection timeout) */ 2092 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 2093 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 2094 #define CS_PORT_BUSY 0x2B /* Port Busy */ 2095 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 2096 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 2097 failure */ 2098 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 2099 #define CS_UNKNOWN 0x81 /* Driver defined */ 2100 #define CS_RETRY 0x82 /* Driver defined */ 2101 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 2102 2103 #define CS_BIDIR_RD_OVERRUN 0x700 2104 #define CS_BIDIR_RD_WR_OVERRUN 0x707 2105 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 2106 #define CS_BIDIR_RD_UNDERRUN 0x1500 2107 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 2108 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 2109 #define CS_BIDIR_DMA 0x200 2110 /* 2111 * Status entry status flags 2112 */ 2113 #define SF_ABTS_TERMINATED BIT_10 2114 #define SF_LOGOUT_SENT BIT_13 2115 2116 /* 2117 * ISP queue - status continuation entry structure definition. 2118 */ 2119 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 2120 typedef struct { 2121 uint8_t entry_type; /* Entry type. */ 2122 uint8_t entry_count; /* Entry count. */ 2123 uint8_t sys_define; /* System defined. */ 2124 uint8_t entry_status; /* Entry Status. */ 2125 uint8_t data[60]; /* data */ 2126 } sts_cont_entry_t; 2127 2128 /* 2129 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 2130 * structure definition. 2131 */ 2132 #define STATUS_TYPE_21 0x21 /* Status entry. */ 2133 typedef struct { 2134 uint8_t entry_type; /* Entry type. */ 2135 uint8_t entry_count; /* Entry count. */ 2136 uint8_t handle_count; /* Handle count. */ 2137 uint8_t entry_status; /* Entry Status. */ 2138 uint32_t handle[15]; /* System handles. */ 2139 } sts21_entry_t; 2140 2141 /* 2142 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 2143 * structure definition. 2144 */ 2145 #define STATUS_TYPE_22 0x22 /* Status entry. */ 2146 typedef struct { 2147 uint8_t entry_type; /* Entry type. */ 2148 uint8_t entry_count; /* Entry count. */ 2149 uint8_t handle_count; /* Handle count. */ 2150 uint8_t entry_status; /* Entry Status. */ 2151 uint16_t handle[30]; /* System handles. */ 2152 } sts22_entry_t; 2153 2154 /* 2155 * ISP queue - marker entry structure definition. 2156 */ 2157 #define MARKER_TYPE 0x04 /* Marker entry. */ 2158 typedef struct { 2159 uint8_t entry_type; /* Entry type. */ 2160 uint8_t entry_count; /* Entry count. */ 2161 uint8_t handle_count; /* Handle count. */ 2162 uint8_t entry_status; /* Entry Status. */ 2163 uint32_t sys_define_2; /* System defined. */ 2164 target_id_t target; /* SCSI ID */ 2165 uint8_t modifier; /* Modifier (7-0). */ 2166 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 2167 #define MK_SYNC_ID 1 /* Synchronize ID */ 2168 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2169 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2170 /* clear port changed, */ 2171 /* use sequence number. */ 2172 uint8_t reserved_1; 2173 __le16 sequence_number; /* Sequence number of event */ 2174 __le16 lun; /* SCSI LUN */ 2175 uint8_t reserved_2[48]; 2176 } mrk_entry_t; 2177 2178 /* 2179 * ISP queue - Management Server entry structure definition. 2180 */ 2181 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2182 typedef struct { 2183 uint8_t entry_type; /* Entry type. */ 2184 uint8_t entry_count; /* Entry count. */ 2185 uint8_t handle_count; /* Handle count. */ 2186 uint8_t entry_status; /* Entry Status. */ 2187 uint32_t handle1; /* System handle. */ 2188 target_id_t loop_id; 2189 __le16 status; 2190 __le16 control_flags; /* Control flags. */ 2191 uint16_t reserved2; 2192 __le16 timeout; 2193 __le16 cmd_dsd_count; 2194 __le16 total_dsd_count; 2195 uint8_t type; 2196 uint8_t r_ctl; 2197 __le16 rx_id; 2198 uint16_t reserved3; 2199 uint32_t handle2; 2200 __le32 rsp_bytecount; 2201 __le32 req_bytecount; 2202 struct dsd64 req_dsd; 2203 struct dsd64 rsp_dsd; 2204 } ms_iocb_entry_t; 2205 2206 #define SCM_EDC_ACC_RECEIVED BIT_6 2207 #define SCM_RDF_ACC_RECEIVED BIT_7 2208 2209 /* 2210 * ISP queue - Mailbox Command entry structure definition. 2211 */ 2212 #define MBX_IOCB_TYPE 0x39 2213 struct mbx_entry { 2214 uint8_t entry_type; 2215 uint8_t entry_count; 2216 uint8_t sys_define1; 2217 /* Use sys_define1 for source type */ 2218 #define SOURCE_SCSI 0x00 2219 #define SOURCE_IP 0x01 2220 #define SOURCE_VI 0x02 2221 #define SOURCE_SCTP 0x03 2222 #define SOURCE_MP 0x04 2223 #define SOURCE_MPIOCTL 0x05 2224 #define SOURCE_ASYNC_IOCB 0x07 2225 2226 uint8_t entry_status; 2227 2228 uint32_t handle; 2229 target_id_t loop_id; 2230 2231 __le16 status; 2232 __le16 state_flags; 2233 __le16 status_flags; 2234 2235 uint32_t sys_define2[2]; 2236 2237 __le16 mb0; 2238 __le16 mb1; 2239 __le16 mb2; 2240 __le16 mb3; 2241 __le16 mb6; 2242 __le16 mb7; 2243 __le16 mb9; 2244 __le16 mb10; 2245 uint32_t reserved_2[2]; 2246 uint8_t node_name[WWN_SIZE]; 2247 uint8_t port_name[WWN_SIZE]; 2248 }; 2249 2250 #ifndef IMMED_NOTIFY_TYPE 2251 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2252 /* 2253 * ISP queue - immediate notify entry structure definition. 2254 * This is sent by the ISP to the Target driver. 2255 * This IOCB would have report of events sent by the 2256 * initiator, that needs to be handled by the target 2257 * driver immediately. 2258 */ 2259 struct imm_ntfy_from_isp { 2260 uint8_t entry_type; /* Entry type. */ 2261 uint8_t entry_count; /* Entry count. */ 2262 uint8_t sys_define; /* System defined. */ 2263 uint8_t entry_status; /* Entry Status. */ 2264 union { 2265 struct { 2266 __le32 sys_define_2; /* System defined. */ 2267 target_id_t target; 2268 __le16 lun; 2269 uint8_t target_id; 2270 uint8_t reserved_1; 2271 __le16 status_modifier; 2272 __le16 status; 2273 __le16 task_flags; 2274 __le16 seq_id; 2275 __le16 srr_rx_id; 2276 __le32 srr_rel_offs; 2277 __le16 srr_ui; 2278 #define SRR_IU_DATA_IN 0x1 2279 #define SRR_IU_DATA_OUT 0x5 2280 #define SRR_IU_STATUS 0x7 2281 __le16 srr_ox_id; 2282 uint8_t reserved_2[28]; 2283 } isp2x; 2284 struct { 2285 uint32_t reserved; 2286 __le16 nport_handle; 2287 uint16_t reserved_2; 2288 __le16 flags; 2289 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2290 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2291 __le16 srr_rx_id; 2292 __le16 status; 2293 uint8_t status_subcode; 2294 uint8_t fw_handle; 2295 __le32 exchange_address; 2296 __le32 srr_rel_offs; 2297 __le16 srr_ui; 2298 __le16 srr_ox_id; 2299 union { 2300 struct { 2301 uint8_t node_name[8]; 2302 } plogi; /* PLOGI/ADISC/PDISC */ 2303 struct { 2304 /* PRLI word 3 bit 0-15 */ 2305 __le16 wd3_lo; 2306 uint8_t resv0[6]; 2307 } prli; 2308 struct { 2309 uint8_t port_id[3]; 2310 uint8_t resv1; 2311 __le16 nport_handle; 2312 uint16_t resv2; 2313 } req_els; 2314 } u; 2315 uint8_t port_name[8]; 2316 uint8_t resv3[3]; 2317 uint8_t vp_index; 2318 uint32_t reserved_5; 2319 uint8_t port_id[3]; 2320 uint8_t reserved_6; 2321 } isp24; 2322 } u; 2323 uint16_t reserved_7; 2324 __le16 ox_id; 2325 } __packed; 2326 #endif 2327 2328 /* 2329 * ISP request and response queue entry sizes 2330 */ 2331 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2332 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2333 2334 2335 2336 /* 2337 * Switch info gathering structure. 2338 */ 2339 typedef struct { 2340 port_id_t d_id; 2341 uint8_t node_name[WWN_SIZE]; 2342 uint8_t port_name[WWN_SIZE]; 2343 uint8_t fabric_port_name[WWN_SIZE]; 2344 uint16_t fp_speed; 2345 uint8_t fc4_type; 2346 uint8_t fc4_features; 2347 } sw_info_t; 2348 2349 /* FCP-4 types */ 2350 #define FC4_TYPE_FCP_SCSI 0x08 2351 #define FC4_TYPE_NVME 0x28 2352 #define FC4_TYPE_OTHER 0x0 2353 #define FC4_TYPE_UNKNOWN 0xff 2354 2355 /* mailbox command 4G & above */ 2356 struct mbx_24xx_entry { 2357 uint8_t entry_type; 2358 uint8_t entry_count; 2359 uint8_t sys_define1; 2360 uint8_t entry_status; 2361 uint32_t handle; 2362 uint16_t mb[28]; 2363 }; 2364 2365 #define IOCB_SIZE 64 2366 2367 /* 2368 * Fibre channel port type. 2369 */ 2370 typedef enum { 2371 FCT_UNKNOWN, 2372 FCT_RSCN, 2373 FCT_SWITCH, 2374 FCT_BROADCAST, 2375 FCT_INITIATOR, 2376 FCT_TARGET, 2377 FCT_NVME_INITIATOR = 0x10, 2378 FCT_NVME_TARGET = 0x20, 2379 FCT_NVME_DISCOVERY = 0x40, 2380 FCT_NVME = 0xf0, 2381 } fc_port_type_t; 2382 2383 enum qla_sess_deletion { 2384 QLA_SESS_DELETION_NONE = 0, 2385 QLA_SESS_DELETION_IN_PROGRESS, 2386 QLA_SESS_DELETED, 2387 }; 2388 2389 enum qlt_plogi_link_t { 2390 QLT_PLOGI_LINK_SAME_WWN, 2391 QLT_PLOGI_LINK_CONFLICT, 2392 QLT_PLOGI_LINK_MAX 2393 }; 2394 2395 struct qlt_plogi_ack_t { 2396 struct list_head list; 2397 struct imm_ntfy_from_isp iocb; 2398 port_id_t id; 2399 int ref_count; 2400 void *fcport; 2401 }; 2402 2403 struct ct_sns_desc { 2404 struct ct_sns_pkt *ct_sns; 2405 dma_addr_t ct_sns_dma; 2406 }; 2407 2408 enum discovery_state { 2409 DSC_DELETED, 2410 DSC_GNN_ID, 2411 DSC_GNL, 2412 DSC_LOGIN_PEND, 2413 DSC_LOGIN_FAILED, 2414 DSC_GPDB, 2415 DSC_UPD_FCPORT, 2416 DSC_LOGIN_COMPLETE, 2417 DSC_ADISC, 2418 DSC_DELETE_PEND, 2419 }; 2420 2421 enum login_state { /* FW control Target side */ 2422 DSC_LS_LLIOCB_SENT = 2, 2423 DSC_LS_PLOGI_PEND, 2424 DSC_LS_PLOGI_COMP, 2425 DSC_LS_PRLI_PEND, 2426 DSC_LS_PRLI_COMP, 2427 DSC_LS_PORT_UNAVAIL, 2428 DSC_LS_PRLO_PEND = 9, 2429 DSC_LS_LOGO_PEND, 2430 }; 2431 2432 enum rscn_addr_format { 2433 RSCN_PORT_ADDR, 2434 RSCN_AREA_ADDR, 2435 RSCN_DOM_ADDR, 2436 RSCN_FAB_ADDR, 2437 }; 2438 2439 /* 2440 * Fibre channel port structure. 2441 */ 2442 typedef struct fc_port { 2443 struct list_head list; 2444 struct scsi_qla_host *vha; 2445 2446 uint8_t node_name[WWN_SIZE]; 2447 uint8_t port_name[WWN_SIZE]; 2448 port_id_t d_id; 2449 uint16_t loop_id; 2450 uint16_t old_loop_id; 2451 2452 unsigned int conf_compl_supported:1; 2453 unsigned int deleted:2; 2454 unsigned int free_pending:1; 2455 unsigned int local:1; 2456 unsigned int logout_on_delete:1; 2457 unsigned int logo_ack_needed:1; 2458 unsigned int keep_nport_handle:1; 2459 unsigned int send_els_logo:1; 2460 unsigned int login_pause:1; 2461 unsigned int login_succ:1; 2462 unsigned int query:1; 2463 unsigned int id_changed:1; 2464 unsigned int scan_needed:1; 2465 unsigned int n2n_flag:1; 2466 unsigned int explicit_logout:1; 2467 unsigned int prli_pend_timer:1; 2468 2469 struct completion nvme_del_done; 2470 uint32_t nvme_prli_service_param; 2471 #define NVME_PRLI_SP_CONF BIT_7 2472 #define NVME_PRLI_SP_INITIATOR BIT_5 2473 #define NVME_PRLI_SP_TARGET BIT_4 2474 #define NVME_PRLI_SP_DISCOVERY BIT_3 2475 #define NVME_PRLI_SP_FIRST_BURST BIT_0 2476 uint8_t nvme_flag; 2477 uint32_t nvme_first_burst_size; 2478 #define NVME_FLAG_REGISTERED 4 2479 #define NVME_FLAG_DELETING 2 2480 #define NVME_FLAG_RESETTING 1 2481 2482 struct fc_port *conflict; 2483 unsigned char logout_completed; 2484 int generation; 2485 2486 struct se_session *se_sess; 2487 struct kref sess_kref; 2488 struct qla_tgt *tgt; 2489 unsigned long expires; 2490 struct list_head del_list_entry; 2491 struct work_struct free_work; 2492 struct work_struct reg_work; 2493 uint64_t jiffies_at_registration; 2494 unsigned long prli_expired; 2495 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2496 2497 uint16_t tgt_id; 2498 uint16_t old_tgt_id; 2499 uint16_t sec_since_registration; 2500 2501 uint8_t fcp_prio; 2502 2503 uint8_t fabric_port_name[WWN_SIZE]; 2504 uint16_t fp_speed; 2505 2506 fc_port_type_t port_type; 2507 2508 atomic_t state; 2509 uint32_t flags; 2510 2511 int login_retry; 2512 2513 struct fc_rport *rport, *drport; 2514 u32 supported_classes; 2515 2516 uint8_t fc4_type; 2517 uint8_t fc4_features; 2518 uint8_t scan_state; 2519 2520 unsigned long last_queue_full; 2521 unsigned long last_ramp_up; 2522 2523 uint16_t port_id; 2524 2525 struct nvme_fc_remote_port *nvme_remote_port; 2526 2527 unsigned long retry_delay_timestamp; 2528 struct qla_tgt_sess *tgt_session; 2529 struct ct_sns_desc ct_desc; 2530 enum discovery_state disc_state; 2531 atomic_t shadow_disc_state; 2532 enum discovery_state next_disc_state; 2533 enum login_state fw_login_state; 2534 unsigned long dm_login_expire; 2535 unsigned long plogi_nack_done_deadline; 2536 2537 u32 login_gen, last_login_gen; 2538 u32 rscn_gen, last_rscn_gen; 2539 u32 chip_reset; 2540 struct list_head gnl_entry; 2541 struct work_struct del_work; 2542 u8 iocb[IOCB_SIZE]; 2543 u8 current_login_state; 2544 u8 last_login_state; 2545 u16 n2n_link_reset_cnt; 2546 u16 n2n_chip_reset; 2547 } fc_port_t; 2548 2549 enum { 2550 FC4_PRIORITY_NVME = 1, 2551 FC4_PRIORITY_FCP = 2, 2552 }; 2553 2554 #define QLA_FCPORT_SCAN 1 2555 #define QLA_FCPORT_FOUND 2 2556 2557 struct event_arg { 2558 fc_port_t *fcport; 2559 srb_t *sp; 2560 port_id_t id; 2561 u16 data[2], rc; 2562 u8 port_name[WWN_SIZE]; 2563 u32 iop[2]; 2564 }; 2565 2566 #include "qla_mr.h" 2567 2568 /* 2569 * Fibre channel port/lun states. 2570 */ 2571 #define FCS_UNCONFIGURED 1 2572 #define FCS_DEVICE_DEAD 2 2573 #define FCS_DEVICE_LOST 3 2574 #define FCS_ONLINE 4 2575 2576 extern const char *const port_state_str[5]; 2577 2578 static const char * const port_dstate_str[] = { 2579 "DELETED", 2580 "GNN_ID", 2581 "GNL", 2582 "LOGIN_PEND", 2583 "LOGIN_FAILED", 2584 "GPDB", 2585 "UPD_FCPORT", 2586 "LOGIN_COMPLETE", 2587 "ADISC", 2588 "DELETE_PEND" 2589 }; 2590 2591 /* 2592 * FC port flags. 2593 */ 2594 #define FCF_FABRIC_DEVICE BIT_0 2595 #define FCF_LOGIN_NEEDED BIT_1 2596 #define FCF_FCP2_DEVICE BIT_2 2597 #define FCF_ASYNC_SENT BIT_3 2598 #define FCF_CONF_COMP_SUPPORTED BIT_4 2599 #define FCF_ASYNC_ACTIVE BIT_5 2600 2601 /* No loop ID flag. */ 2602 #define FC_NO_LOOP_ID 0x1000 2603 2604 /* 2605 * FC-CT interface 2606 * 2607 * NOTE: All structures are big-endian in form. 2608 */ 2609 2610 #define CT_REJECT_RESPONSE 0x8001 2611 #define CT_ACCEPT_RESPONSE 0x8002 2612 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2613 #define CT_REASON_CANNOT_PERFORM 0x09 2614 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2615 #define CT_EXPL_ALREADY_REGISTERED 0x10 2616 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2617 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2618 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2619 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2620 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2621 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2622 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2623 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2624 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2625 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2626 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2627 2628 #define NS_N_PORT_TYPE 0x01 2629 #define NS_NL_PORT_TYPE 0x02 2630 #define NS_NX_PORT_TYPE 0x7F 2631 2632 #define GA_NXT_CMD 0x100 2633 #define GA_NXT_REQ_SIZE (16 + 4) 2634 #define GA_NXT_RSP_SIZE (16 + 620) 2635 2636 #define GPN_FT_CMD 0x172 2637 #define GPN_FT_REQ_SIZE (16 + 4) 2638 #define GNN_FT_CMD 0x173 2639 #define GNN_FT_REQ_SIZE (16 + 4) 2640 2641 #define GID_PT_CMD 0x1A1 2642 #define GID_PT_REQ_SIZE (16 + 4) 2643 2644 #define GPN_ID_CMD 0x112 2645 #define GPN_ID_REQ_SIZE (16 + 4) 2646 #define GPN_ID_RSP_SIZE (16 + 8) 2647 2648 #define GNN_ID_CMD 0x113 2649 #define GNN_ID_REQ_SIZE (16 + 4) 2650 #define GNN_ID_RSP_SIZE (16 + 8) 2651 2652 #define GFT_ID_CMD 0x117 2653 #define GFT_ID_REQ_SIZE (16 + 4) 2654 #define GFT_ID_RSP_SIZE (16 + 32) 2655 2656 #define GID_PN_CMD 0x121 2657 #define GID_PN_REQ_SIZE (16 + 8) 2658 #define GID_PN_RSP_SIZE (16 + 4) 2659 2660 #define RFT_ID_CMD 0x217 2661 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2662 #define RFT_ID_RSP_SIZE 16 2663 2664 #define RFF_ID_CMD 0x21F 2665 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2666 #define RFF_ID_RSP_SIZE 16 2667 2668 #define RNN_ID_CMD 0x213 2669 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2670 #define RNN_ID_RSP_SIZE 16 2671 2672 #define RSNN_NN_CMD 0x239 2673 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2674 #define RSNN_NN_RSP_SIZE 16 2675 2676 #define GFPN_ID_CMD 0x11C 2677 #define GFPN_ID_REQ_SIZE (16 + 4) 2678 #define GFPN_ID_RSP_SIZE (16 + 8) 2679 2680 #define GPSC_CMD 0x127 2681 #define GPSC_REQ_SIZE (16 + 8) 2682 #define GPSC_RSP_SIZE (16 + 2 + 2) 2683 2684 #define GFF_ID_CMD 0x011F 2685 #define GFF_ID_REQ_SIZE (16 + 4) 2686 #define GFF_ID_RSP_SIZE (16 + 128) 2687 2688 /* 2689 * FDMI HBA attribute types. 2690 */ 2691 #define FDMI1_HBA_ATTR_COUNT 9 2692 #define FDMI2_HBA_ATTR_COUNT 17 2693 2694 #define FDMI_HBA_NODE_NAME 0x1 2695 #define FDMI_HBA_MANUFACTURER 0x2 2696 #define FDMI_HBA_SERIAL_NUMBER 0x3 2697 #define FDMI_HBA_MODEL 0x4 2698 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2699 #define FDMI_HBA_HARDWARE_VERSION 0x6 2700 #define FDMI_HBA_DRIVER_VERSION 0x7 2701 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2702 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2703 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2704 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2705 2706 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2707 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd 2708 #define FDMI_HBA_NUM_PORTS 0xe 2709 #define FDMI_HBA_FABRIC_NAME 0xf 2710 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2711 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0 2712 2713 struct ct_fdmi_hba_attr { 2714 __be16 type; 2715 __be16 len; 2716 union { 2717 uint8_t node_name[WWN_SIZE]; 2718 uint8_t manufacturer[64]; 2719 uint8_t serial_num[32]; 2720 uint8_t model[16+1]; 2721 uint8_t model_desc[80]; 2722 uint8_t hw_version[32]; 2723 uint8_t driver_version[32]; 2724 uint8_t orom_version[16]; 2725 uint8_t fw_version[32]; 2726 uint8_t os_version[128]; 2727 __be32 max_ct_len; 2728 2729 uint8_t sym_name[256]; 2730 __be32 vendor_specific_info; 2731 __be32 num_ports; 2732 uint8_t fabric_name[WWN_SIZE]; 2733 uint8_t bios_name[32]; 2734 uint8_t vendor_identifier[8]; 2735 } a; 2736 }; 2737 2738 struct ct_fdmi1_hba_attributes { 2739 __be32 count; 2740 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT]; 2741 }; 2742 2743 struct ct_fdmi2_hba_attributes { 2744 __be32 count; 2745 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT]; 2746 }; 2747 2748 /* 2749 * FDMI Port attribute types. 2750 */ 2751 #define FDMI1_PORT_ATTR_COUNT 6 2752 #define FDMI2_PORT_ATTR_COUNT 16 2753 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23 2754 2755 #define FDMI_PORT_FC4_TYPES 0x1 2756 #define FDMI_PORT_SUPPORT_SPEED 0x2 2757 #define FDMI_PORT_CURRENT_SPEED 0x3 2758 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2759 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2760 #define FDMI_PORT_HOST_NAME 0x6 2761 2762 #define FDMI_PORT_NODE_NAME 0x7 2763 #define FDMI_PORT_NAME 0x8 2764 #define FDMI_PORT_SYM_NAME 0x9 2765 #define FDMI_PORT_TYPE 0xa 2766 #define FDMI_PORT_SUPP_COS 0xb 2767 #define FDMI_PORT_FABRIC_NAME 0xc 2768 #define FDMI_PORT_FC4_TYPE 0xd 2769 #define FDMI_PORT_STATE 0x101 2770 #define FDMI_PORT_COUNT 0x102 2771 #define FDMI_PORT_IDENTIFIER 0x103 2772 2773 #define FDMI_SMARTSAN_SERVICE 0xF100 2774 #define FDMI_SMARTSAN_GUID 0xF101 2775 #define FDMI_SMARTSAN_VERSION 0xF102 2776 #define FDMI_SMARTSAN_PROD_NAME 0xF103 2777 #define FDMI_SMARTSAN_PORT_INFO 0xF104 2778 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105 2779 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106 2780 2781 #define FDMI_PORT_SPEED_1GB 0x1 2782 #define FDMI_PORT_SPEED_2GB 0x2 2783 #define FDMI_PORT_SPEED_10GB 0x4 2784 #define FDMI_PORT_SPEED_4GB 0x8 2785 #define FDMI_PORT_SPEED_8GB 0x10 2786 #define FDMI_PORT_SPEED_16GB 0x20 2787 #define FDMI_PORT_SPEED_32GB 0x40 2788 #define FDMI_PORT_SPEED_64GB 0x80 2789 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2790 2791 #define FC_CLASS_2 0x04 2792 #define FC_CLASS_3 0x08 2793 #define FC_CLASS_2_3 0x0C 2794 2795 struct ct_fdmi_port_attr { 2796 __be16 type; 2797 __be16 len; 2798 union { 2799 uint8_t fc4_types[32]; 2800 __be32 sup_speed; 2801 __be32 cur_speed; 2802 __be32 max_frame_size; 2803 uint8_t os_dev_name[32]; 2804 uint8_t host_name[256]; 2805 2806 uint8_t node_name[WWN_SIZE]; 2807 uint8_t port_name[WWN_SIZE]; 2808 uint8_t port_sym_name[128]; 2809 __be32 port_type; 2810 __be32 port_supported_cos; 2811 uint8_t fabric_name[WWN_SIZE]; 2812 uint8_t port_fc4_type[32]; 2813 __be32 port_state; 2814 __be32 num_ports; 2815 __be32 port_id; 2816 2817 uint8_t smartsan_service[24]; 2818 uint8_t smartsan_guid[16]; 2819 uint8_t smartsan_version[24]; 2820 uint8_t smartsan_prod_name[16]; 2821 __be32 smartsan_port_info; 2822 __be32 smartsan_qos_support; 2823 __be32 smartsan_security_support; 2824 } a; 2825 }; 2826 2827 struct ct_fdmi1_port_attributes { 2828 __be32 count; 2829 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT]; 2830 }; 2831 2832 struct ct_fdmi2_port_attributes { 2833 __be32 count; 2834 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT]; 2835 }; 2836 2837 #define FDMI_ATTR_TYPELEN(obj) \ 2838 (sizeof((obj)->type) + sizeof((obj)->len)) 2839 2840 #define FDMI_ATTR_ALIGNMENT(len) \ 2841 (4 - ((len) & 3)) 2842 2843 /* FDMI register call options */ 2844 #define CALLOPT_FDMI1 0 2845 #define CALLOPT_FDMI2 1 2846 #define CALLOPT_FDMI2_SMARTSAN 2 2847 2848 /* FDMI definitions. */ 2849 #define GRHL_CMD 0x100 2850 #define GHAT_CMD 0x101 2851 #define GRPL_CMD 0x102 2852 #define GPAT_CMD 0x110 2853 2854 #define RHBA_CMD 0x200 2855 #define RHBA_RSP_SIZE 16 2856 2857 #define RHAT_CMD 0x201 2858 2859 #define RPRT_CMD 0x210 2860 #define RPRT_RSP_SIZE 24 2861 2862 #define RPA_CMD 0x211 2863 #define RPA_RSP_SIZE 16 2864 #define SMARTSAN_RPA_RSP_SIZE 24 2865 2866 #define DHBA_CMD 0x300 2867 #define DHBA_REQ_SIZE (16 + 8) 2868 #define DHBA_RSP_SIZE 16 2869 2870 #define DHAT_CMD 0x301 2871 #define DPRT_CMD 0x310 2872 #define DPA_CMD 0x311 2873 2874 /* CT command header -- request/response common fields */ 2875 struct ct_cmd_hdr { 2876 uint8_t revision; 2877 uint8_t in_id[3]; 2878 uint8_t gs_type; 2879 uint8_t gs_subtype; 2880 uint8_t options; 2881 uint8_t reserved; 2882 }; 2883 2884 /* CT command request */ 2885 struct ct_sns_req { 2886 struct ct_cmd_hdr header; 2887 __be16 command; 2888 __be16 max_rsp_size; 2889 uint8_t fragment_id; 2890 uint8_t reserved[3]; 2891 2892 union { 2893 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2894 struct { 2895 uint8_t reserved; 2896 be_id_t port_id; 2897 } port_id; 2898 2899 struct { 2900 uint8_t reserved; 2901 uint8_t domain; 2902 uint8_t area; 2903 uint8_t port_type; 2904 } gpn_ft; 2905 2906 struct { 2907 uint8_t port_type; 2908 uint8_t domain; 2909 uint8_t area; 2910 uint8_t reserved; 2911 } gid_pt; 2912 2913 struct { 2914 uint8_t reserved; 2915 be_id_t port_id; 2916 uint8_t fc4_types[32]; 2917 } rft_id; 2918 2919 struct { 2920 uint8_t reserved; 2921 be_id_t port_id; 2922 uint16_t reserved2; 2923 uint8_t fc4_feature; 2924 uint8_t fc4_type; 2925 } rff_id; 2926 2927 struct { 2928 uint8_t reserved; 2929 be_id_t port_id; 2930 uint8_t node_name[8]; 2931 } rnn_id; 2932 2933 struct { 2934 uint8_t node_name[8]; 2935 uint8_t name_len; 2936 uint8_t sym_node_name[255]; 2937 } rsnn_nn; 2938 2939 struct { 2940 uint8_t hba_identifier[8]; 2941 } ghat; 2942 2943 struct { 2944 uint8_t hba_identifier[8]; 2945 __be32 entry_count; 2946 uint8_t port_name[8]; 2947 struct ct_fdmi2_hba_attributes attrs; 2948 } rhba; 2949 2950 struct { 2951 uint8_t hba_identifier[8]; 2952 struct ct_fdmi1_hba_attributes attrs; 2953 } rhat; 2954 2955 struct { 2956 uint8_t port_name[8]; 2957 struct ct_fdmi2_port_attributes attrs; 2958 } rpa; 2959 2960 struct { 2961 uint8_t hba_identifier[8]; 2962 uint8_t port_name[8]; 2963 struct ct_fdmi2_port_attributes attrs; 2964 } rprt; 2965 2966 struct { 2967 uint8_t port_name[8]; 2968 } dhba; 2969 2970 struct { 2971 uint8_t port_name[8]; 2972 } dhat; 2973 2974 struct { 2975 uint8_t port_name[8]; 2976 } dprt; 2977 2978 struct { 2979 uint8_t port_name[8]; 2980 } dpa; 2981 2982 struct { 2983 uint8_t port_name[8]; 2984 } gpsc; 2985 2986 struct { 2987 uint8_t reserved; 2988 uint8_t port_id[3]; 2989 } gff_id; 2990 2991 struct { 2992 uint8_t port_name[8]; 2993 } gid_pn; 2994 } req; 2995 }; 2996 2997 /* CT command response header */ 2998 struct ct_rsp_hdr { 2999 struct ct_cmd_hdr header; 3000 __be16 response; 3001 uint16_t residual; 3002 uint8_t fragment_id; 3003 uint8_t reason_code; 3004 uint8_t explanation_code; 3005 uint8_t vendor_unique; 3006 }; 3007 3008 struct ct_sns_gid_pt_data { 3009 uint8_t control_byte; 3010 be_id_t port_id; 3011 }; 3012 3013 /* It's the same for both GPN_FT and GNN_FT */ 3014 struct ct_sns_gpnft_rsp { 3015 struct { 3016 struct ct_cmd_hdr header; 3017 uint16_t response; 3018 uint16_t residual; 3019 uint8_t fragment_id; 3020 uint8_t reason_code; 3021 uint8_t explanation_code; 3022 uint8_t vendor_unique; 3023 }; 3024 /* Assume the largest number of targets for the union */ 3025 struct ct_sns_gpn_ft_data { 3026 u8 control_byte; 3027 u8 port_id[3]; 3028 u32 reserved; 3029 u8 port_name[8]; 3030 } entries[1]; 3031 }; 3032 3033 /* CT command response */ 3034 struct ct_sns_rsp { 3035 struct ct_rsp_hdr header; 3036 3037 union { 3038 struct { 3039 uint8_t port_type; 3040 be_id_t port_id; 3041 uint8_t port_name[8]; 3042 uint8_t sym_port_name_len; 3043 uint8_t sym_port_name[255]; 3044 uint8_t node_name[8]; 3045 uint8_t sym_node_name_len; 3046 uint8_t sym_node_name[255]; 3047 uint8_t init_proc_assoc[8]; 3048 uint8_t node_ip_addr[16]; 3049 uint8_t class_of_service[4]; 3050 uint8_t fc4_types[32]; 3051 uint8_t ip_address[16]; 3052 uint8_t fabric_port_name[8]; 3053 uint8_t reserved; 3054 uint8_t hard_address[3]; 3055 } ga_nxt; 3056 3057 struct { 3058 /* Assume the largest number of targets for the union */ 3059 struct ct_sns_gid_pt_data 3060 entries[MAX_FIBRE_DEVICES_MAX]; 3061 } gid_pt; 3062 3063 struct { 3064 uint8_t port_name[8]; 3065 } gpn_id; 3066 3067 struct { 3068 uint8_t node_name[8]; 3069 } gnn_id; 3070 3071 struct { 3072 uint8_t fc4_types[32]; 3073 } gft_id; 3074 3075 struct { 3076 uint32_t entry_count; 3077 uint8_t port_name[8]; 3078 struct ct_fdmi1_hba_attributes attrs; 3079 } ghat; 3080 3081 struct { 3082 uint8_t port_name[8]; 3083 } gfpn_id; 3084 3085 struct { 3086 __be16 speeds; 3087 __be16 speed; 3088 } gpsc; 3089 3090 #define GFF_FCP_SCSI_OFFSET 7 3091 #define GFF_NVME_OFFSET 23 /* type = 28h */ 3092 struct { 3093 uint8_t fc4_features[128]; 3094 } gff_id; 3095 struct { 3096 uint8_t reserved; 3097 uint8_t port_id[3]; 3098 } gid_pn; 3099 } rsp; 3100 }; 3101 3102 struct ct_sns_pkt { 3103 union { 3104 struct ct_sns_req req; 3105 struct ct_sns_rsp rsp; 3106 } p; 3107 }; 3108 3109 struct ct_sns_gpnft_pkt { 3110 union { 3111 struct ct_sns_req req; 3112 struct ct_sns_gpnft_rsp rsp; 3113 } p; 3114 }; 3115 3116 enum scan_flags_t { 3117 SF_SCANNING = BIT_0, 3118 SF_QUEUED = BIT_1, 3119 }; 3120 3121 enum fc4type_t { 3122 FS_FC4TYPE_FCP = BIT_0, 3123 FS_FC4TYPE_NVME = BIT_1, 3124 FS_FCP_IS_N2N = BIT_7, 3125 }; 3126 3127 struct fab_scan_rp { 3128 port_id_t id; 3129 enum fc4type_t fc4type; 3130 u8 port_name[8]; 3131 u8 node_name[8]; 3132 }; 3133 3134 struct fab_scan { 3135 struct fab_scan_rp *l; 3136 u32 size; 3137 u16 scan_retry; 3138 #define MAX_SCAN_RETRIES 5 3139 enum scan_flags_t scan_flags; 3140 struct delayed_work scan_work; 3141 }; 3142 3143 /* 3144 * SNS command structures -- for 2200 compatibility. 3145 */ 3146 #define RFT_ID_SNS_SCMD_LEN 22 3147 #define RFT_ID_SNS_CMD_SIZE 60 3148 #define RFT_ID_SNS_DATA_SIZE 16 3149 3150 #define RNN_ID_SNS_SCMD_LEN 10 3151 #define RNN_ID_SNS_CMD_SIZE 36 3152 #define RNN_ID_SNS_DATA_SIZE 16 3153 3154 #define GA_NXT_SNS_SCMD_LEN 6 3155 #define GA_NXT_SNS_CMD_SIZE 28 3156 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 3157 3158 #define GID_PT_SNS_SCMD_LEN 6 3159 #define GID_PT_SNS_CMD_SIZE 28 3160 /* 3161 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 3162 * adapters. 3163 */ 3164 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 3165 3166 #define GPN_ID_SNS_SCMD_LEN 6 3167 #define GPN_ID_SNS_CMD_SIZE 28 3168 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 3169 3170 #define GNN_ID_SNS_SCMD_LEN 6 3171 #define GNN_ID_SNS_CMD_SIZE 28 3172 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 3173 3174 struct sns_cmd_pkt { 3175 union { 3176 struct { 3177 __le16 buffer_length; 3178 __le16 reserved_1; 3179 __le64 buffer_address __packed; 3180 __le16 subcommand_length; 3181 __le16 reserved_2; 3182 __le16 subcommand; 3183 __le16 size; 3184 uint32_t reserved_3; 3185 uint8_t param[36]; 3186 } cmd; 3187 3188 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 3189 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 3190 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 3191 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 3192 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 3193 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 3194 } p; 3195 }; 3196 3197 struct fw_blob { 3198 char *name; 3199 uint32_t segs[4]; 3200 const struct firmware *fw; 3201 }; 3202 3203 /* Return data from MBC_GET_ID_LIST call. */ 3204 struct gid_list_info { 3205 uint8_t al_pa; 3206 uint8_t area; 3207 uint8_t domain; 3208 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 3209 __le16 loop_id; /* ISP23XX -- 6 bytes. */ 3210 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 3211 }; 3212 3213 /* NPIV */ 3214 typedef struct vport_info { 3215 uint8_t port_name[WWN_SIZE]; 3216 uint8_t node_name[WWN_SIZE]; 3217 int vp_id; 3218 uint16_t loop_id; 3219 unsigned long host_no; 3220 uint8_t port_id[3]; 3221 int loop_state; 3222 } vport_info_t; 3223 3224 typedef struct vport_params { 3225 uint8_t port_name[WWN_SIZE]; 3226 uint8_t node_name[WWN_SIZE]; 3227 uint32_t options; 3228 #define VP_OPTS_RETRY_ENABLE BIT_0 3229 #define VP_OPTS_VP_DISABLE BIT_1 3230 } vport_params_t; 3231 3232 /* NPIV - return codes of VP create and modify */ 3233 #define VP_RET_CODE_OK 0 3234 #define VP_RET_CODE_FATAL 1 3235 #define VP_RET_CODE_WRONG_ID 2 3236 #define VP_RET_CODE_WWPN 3 3237 #define VP_RET_CODE_RESOURCES 4 3238 #define VP_RET_CODE_NO_MEM 5 3239 #define VP_RET_CODE_NOT_FOUND 6 3240 3241 struct qla_hw_data; 3242 struct rsp_que; 3243 /* 3244 * ISP operations 3245 */ 3246 struct isp_operations { 3247 3248 int (*pci_config) (struct scsi_qla_host *); 3249 int (*reset_chip)(struct scsi_qla_host *); 3250 int (*chip_diag) (struct scsi_qla_host *); 3251 void (*config_rings) (struct scsi_qla_host *); 3252 int (*reset_adapter)(struct scsi_qla_host *); 3253 int (*nvram_config) (struct scsi_qla_host *); 3254 void (*update_fw_options) (struct scsi_qla_host *); 3255 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3256 3257 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t); 3258 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3259 3260 irq_handler_t intr_handler; 3261 void (*enable_intrs) (struct qla_hw_data *); 3262 void (*disable_intrs) (struct qla_hw_data *); 3263 3264 int (*abort_command) (srb_t *); 3265 int (*target_reset) (struct fc_port *, uint64_t, int); 3266 int (*lun_reset) (struct fc_port *, uint64_t, int); 3267 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3268 uint8_t, uint8_t, uint16_t *, uint8_t); 3269 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3270 uint8_t, uint8_t); 3271 3272 uint16_t (*calc_req_entries) (uint16_t); 3273 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3274 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3275 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3276 uint32_t); 3277 3278 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *, 3279 uint32_t, uint32_t); 3280 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t, 3281 uint32_t); 3282 3283 void (*fw_dump)(struct scsi_qla_host *vha); 3284 void (*mpi_fw_dump)(struct scsi_qla_host *, int); 3285 3286 int (*beacon_on) (struct scsi_qla_host *); 3287 int (*beacon_off) (struct scsi_qla_host *); 3288 void (*beacon_blink) (struct scsi_qla_host *); 3289 3290 void *(*read_optrom)(struct scsi_qla_host *, void *, 3291 uint32_t, uint32_t); 3292 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t, 3293 uint32_t); 3294 3295 int (*get_flash_version) (struct scsi_qla_host *, void *); 3296 int (*start_scsi) (srb_t *); 3297 int (*start_scsi_mq) (srb_t *); 3298 int (*abort_isp) (struct scsi_qla_host *); 3299 int (*iospace_config)(struct qla_hw_data *); 3300 int (*initialize_adapter)(struct scsi_qla_host *); 3301 }; 3302 3303 /* MSI-X Support *************************************************************/ 3304 3305 #define QLA_MSIX_CHIP_REV_24XX 3 3306 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3307 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3308 3309 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3310 #define QLA_MSIX_RSP_Q 0x01 3311 #define QLA_ATIO_VECTOR 0x02 3312 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3313 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04 3314 3315 #define QLA_MIDX_DEFAULT 0 3316 #define QLA_MIDX_RSP_Q 1 3317 #define QLA_PCI_MSIX_CONTROL 0xa2 3318 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3319 3320 struct scsi_qla_host; 3321 3322 3323 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3324 3325 struct qla_msix_entry { 3326 int have_irq; 3327 int in_use; 3328 uint32_t vector; 3329 uint16_t entry; 3330 char name[30]; 3331 void *handle; 3332 int cpuid; 3333 }; 3334 3335 #define WATCH_INTERVAL 1 /* number of seconds */ 3336 3337 /* Work events. */ 3338 enum qla_work_type { 3339 QLA_EVT_AEN, 3340 QLA_EVT_IDC_ACK, 3341 QLA_EVT_ASYNC_LOGIN, 3342 QLA_EVT_ASYNC_LOGOUT, 3343 QLA_EVT_ASYNC_ADISC, 3344 QLA_EVT_UEVENT, 3345 QLA_EVT_AENFX, 3346 QLA_EVT_GPNID, 3347 QLA_EVT_UNMAP, 3348 QLA_EVT_NEW_SESS, 3349 QLA_EVT_GPDB, 3350 QLA_EVT_PRLI, 3351 QLA_EVT_GPSC, 3352 QLA_EVT_GNL, 3353 QLA_EVT_NACK, 3354 QLA_EVT_RELOGIN, 3355 QLA_EVT_ASYNC_PRLO, 3356 QLA_EVT_ASYNC_PRLO_DONE, 3357 QLA_EVT_GPNFT, 3358 QLA_EVT_GPNFT_DONE, 3359 QLA_EVT_GNNFT_DONE, 3360 QLA_EVT_GNNID, 3361 QLA_EVT_GFPNID, 3362 QLA_EVT_SP_RETRY, 3363 QLA_EVT_IIDMA, 3364 QLA_EVT_ELS_PLOGI, 3365 }; 3366 3367 3368 struct qla_work_evt { 3369 struct list_head list; 3370 enum qla_work_type type; 3371 u32 flags; 3372 #define QLA_EVT_FLAG_FREE 0x1 3373 3374 union { 3375 struct { 3376 enum fc_host_event_code code; 3377 u32 data; 3378 } aen; 3379 struct { 3380 #define QLA_IDC_ACK_REGS 7 3381 uint16_t mb[QLA_IDC_ACK_REGS]; 3382 } idc_ack; 3383 struct { 3384 struct fc_port *fcport; 3385 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3386 u16 data[2]; 3387 } logio; 3388 struct { 3389 u32 code; 3390 #define QLA_UEVENT_CODE_FW_DUMP 0 3391 } uevent; 3392 struct { 3393 uint32_t evtcode; 3394 uint32_t mbx[8]; 3395 uint32_t count; 3396 } aenfx; 3397 struct { 3398 srb_t *sp; 3399 } iosb; 3400 struct { 3401 port_id_t id; 3402 } gpnid; 3403 struct { 3404 port_id_t id; 3405 u8 port_name[8]; 3406 u8 node_name[8]; 3407 void *pla; 3408 u8 fc4_type; 3409 } new_sess; 3410 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */ 3411 fc_port_t *fcport; 3412 u8 opt; 3413 } fcport; 3414 struct { 3415 fc_port_t *fcport; 3416 u8 iocb[IOCB_SIZE]; 3417 int type; 3418 } nack; 3419 struct { 3420 u8 fc4_type; 3421 srb_t *sp; 3422 } gpnft; 3423 } u; 3424 }; 3425 3426 struct qla_chip_state_84xx { 3427 struct list_head list; 3428 struct kref kref; 3429 3430 void *bus; 3431 spinlock_t access_lock; 3432 struct mutex fw_update_mutex; 3433 uint32_t fw_update; 3434 uint32_t op_fw_version; 3435 uint32_t op_fw_size; 3436 uint32_t op_fw_seq_size; 3437 uint32_t diag_fw_version; 3438 uint32_t gold_fw_version; 3439 }; 3440 3441 struct qla_dif_statistics { 3442 uint64_t dif_input_bytes; 3443 uint64_t dif_output_bytes; 3444 uint64_t dif_input_requests; 3445 uint64_t dif_output_requests; 3446 uint32_t dif_guard_err; 3447 uint32_t dif_ref_tag_err; 3448 uint32_t dif_app_tag_err; 3449 }; 3450 3451 struct qla_statistics { 3452 uint32_t total_isp_aborts; 3453 uint64_t input_bytes; 3454 uint64_t output_bytes; 3455 uint64_t input_requests; 3456 uint64_t output_requests; 3457 uint32_t control_requests; 3458 3459 uint64_t jiffies_at_last_reset; 3460 uint32_t stat_max_pend_cmds; 3461 uint32_t stat_max_qfull_cmds_alloc; 3462 uint32_t stat_max_qfull_cmds_dropped; 3463 3464 struct qla_dif_statistics qla_dif_stats; 3465 }; 3466 3467 struct bidi_statistics { 3468 unsigned long long io_count; 3469 unsigned long long transfer_bytes; 3470 }; 3471 3472 struct qla_tc_param { 3473 struct scsi_qla_host *vha; 3474 uint32_t blk_sz; 3475 uint32_t bufflen; 3476 struct scatterlist *sg; 3477 struct scatterlist *prot_sg; 3478 struct crc_context *ctx; 3479 uint8_t *ctx_dsd_alloced; 3480 }; 3481 3482 /* Multi queue support */ 3483 #define MBC_INITIALIZE_MULTIQ 0x1f 3484 #define QLA_QUE_PAGE 0X1000 3485 #define QLA_MQ_SIZE 32 3486 #define QLA_MAX_QUEUES 256 3487 #define ISP_QUE_REG(ha, id) \ 3488 ((ha->mqenable || IS_QLA83XX(ha) || \ 3489 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \ 3490 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3491 ((void __iomem *)ha->iobase)) 3492 #define QLA_REQ_QUE_ID(tag) \ 3493 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3494 #define QLA_DEFAULT_QUE_QOS 5 3495 #define QLA_PRECONFIG_VPORTS 32 3496 #define QLA_MAX_VPORTS_QLA24XX 128 3497 #define QLA_MAX_VPORTS_QLA25XX 256 3498 3499 struct qla_tgt_counters { 3500 uint64_t qla_core_sbt_cmd; 3501 uint64_t core_qla_que_buf; 3502 uint64_t qla_core_ret_ctio; 3503 uint64_t core_qla_snd_status; 3504 uint64_t qla_core_ret_sta_ctio; 3505 uint64_t core_qla_free_cmd; 3506 uint64_t num_q_full_sent; 3507 uint64_t num_alloc_iocb_failed; 3508 uint64_t num_term_xchg_sent; 3509 }; 3510 3511 struct qla_qpair; 3512 3513 /* Response queue data structure */ 3514 struct rsp_que { 3515 dma_addr_t dma; 3516 response_t *ring; 3517 response_t *ring_ptr; 3518 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */ 3519 __le32 __iomem *rsp_q_out; 3520 uint16_t ring_index; 3521 uint16_t out_ptr; 3522 uint16_t *in_ptr; /* queue shadow in index */ 3523 uint16_t length; 3524 uint16_t options; 3525 uint16_t rid; 3526 uint16_t id; 3527 uint16_t vp_idx; 3528 struct qla_hw_data *hw; 3529 struct qla_msix_entry *msix; 3530 struct req_que *req; 3531 srb_t *status_srb; /* status continuation entry */ 3532 struct qla_qpair *qpair; 3533 3534 dma_addr_t dma_fx00; 3535 response_t *ring_fx00; 3536 uint16_t length_fx00; 3537 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3538 }; 3539 3540 /* Request queue data structure */ 3541 struct req_que { 3542 dma_addr_t dma; 3543 request_t *ring; 3544 request_t *ring_ptr; 3545 __le32 __iomem *req_q_in; /* FWI2-capable only. */ 3546 __le32 __iomem *req_q_out; 3547 uint16_t ring_index; 3548 uint16_t in_ptr; 3549 uint16_t *out_ptr; /* queue shadow out index */ 3550 uint16_t cnt; 3551 uint16_t length; 3552 uint16_t options; 3553 uint16_t rid; 3554 uint16_t id; 3555 uint16_t qos; 3556 uint16_t vp_idx; 3557 struct rsp_que *rsp; 3558 srb_t **outstanding_cmds; 3559 uint32_t current_outstanding_cmd; 3560 uint16_t num_outstanding_cmds; 3561 int max_q_depth; 3562 3563 dma_addr_t dma_fx00; 3564 request_t *ring_fx00; 3565 uint16_t length_fx00; 3566 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3567 }; 3568 3569 /*Queue pair data structure */ 3570 struct qla_qpair { 3571 spinlock_t qp_lock; 3572 atomic_t ref_count; 3573 uint32_t lun_cnt; 3574 /* 3575 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3576 * legacy code. For other Qpair(s), it will point at qp_lock. 3577 */ 3578 spinlock_t *qp_lock_ptr; 3579 struct scsi_qla_host *vha; 3580 u32 chip_reset; 3581 3582 /* distill these fields down to 'online=0/1' 3583 * ha->flags.eeh_busy 3584 * ha->flags.pci_channel_io_perm_failure 3585 * base_vha->loop_state 3586 */ 3587 uint32_t online:1; 3588 /* move vha->flags.difdix_supported here */ 3589 uint32_t difdix_supported:1; 3590 uint32_t delete_in_progress:1; 3591 uint32_t fw_started:1; 3592 uint32_t enable_class_2:1; 3593 uint32_t enable_explicit_conf:1; 3594 uint32_t use_shadow_reg:1; 3595 3596 uint16_t id; /* qp number used with FW */ 3597 uint16_t vp_idx; /* vport ID */ 3598 mempool_t *srb_mempool; 3599 3600 struct pci_dev *pdev; 3601 void (*reqq_start_iocbs)(struct qla_qpair *); 3602 3603 /* to do: New driver: move queues to here instead of pointers */ 3604 struct req_que *req; 3605 struct rsp_que *rsp; 3606 struct atio_que *atio; 3607 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3608 struct qla_hw_data *hw; 3609 struct work_struct q_work; 3610 struct list_head qp_list_elem; /* vha->qp_list */ 3611 struct list_head hints_list; 3612 uint16_t cpuid; 3613 uint16_t retry_term_cnt; 3614 __le32 retry_term_exchg_addr; 3615 uint64_t retry_term_jiff; 3616 struct qla_tgt_counters tgt_counters; 3617 }; 3618 3619 /* Place holder for FW buffer parameters */ 3620 struct qlfc_fw { 3621 void *fw_buf; 3622 dma_addr_t fw_dma; 3623 uint32_t len; 3624 }; 3625 3626 struct rdp_req_payload { 3627 uint32_t els_request; 3628 uint32_t desc_list_len; 3629 3630 /* NPIV descriptor */ 3631 struct { 3632 uint32_t desc_tag; 3633 uint32_t desc_len; 3634 uint8_t reserved; 3635 uint8_t nport_id[3]; 3636 } npiv_desc; 3637 }; 3638 3639 struct rdp_rsp_payload { 3640 struct { 3641 __be32 cmd; 3642 __be32 len; 3643 } hdr; 3644 3645 /* LS Request Info descriptor */ 3646 struct { 3647 __be32 desc_tag; 3648 __be32 desc_len; 3649 __be32 req_payload_word_0; 3650 } ls_req_info_desc; 3651 3652 /* LS Request Info descriptor */ 3653 struct { 3654 __be32 desc_tag; 3655 __be32 desc_len; 3656 __be32 req_payload_word_0; 3657 } ls_req_info_desc2; 3658 3659 /* SFP diagnostic param descriptor */ 3660 struct { 3661 __be32 desc_tag; 3662 __be32 desc_len; 3663 __be16 temperature; 3664 __be16 vcc; 3665 __be16 tx_bias; 3666 __be16 tx_power; 3667 __be16 rx_power; 3668 __be16 sfp_flags; 3669 } sfp_diag_desc; 3670 3671 /* Port Speed Descriptor */ 3672 struct { 3673 __be32 desc_tag; 3674 __be32 desc_len; 3675 __be16 speed_capab; 3676 __be16 operating_speed; 3677 } port_speed_desc; 3678 3679 /* Link Error Status Descriptor */ 3680 struct { 3681 __be32 desc_tag; 3682 __be32 desc_len; 3683 __be32 link_fail_cnt; 3684 __be32 loss_sync_cnt; 3685 __be32 loss_sig_cnt; 3686 __be32 prim_seq_err_cnt; 3687 __be32 inval_xmit_word_cnt; 3688 __be32 inval_crc_cnt; 3689 uint8_t pn_port_phy_type; 3690 uint8_t reserved[3]; 3691 } ls_err_desc; 3692 3693 /* Port name description with diag param */ 3694 struct { 3695 __be32 desc_tag; 3696 __be32 desc_len; 3697 uint8_t WWNN[WWN_SIZE]; 3698 uint8_t WWPN[WWN_SIZE]; 3699 } port_name_diag_desc; 3700 3701 /* Port Name desc for Direct attached Fx_Port or Nx_Port */ 3702 struct { 3703 __be32 desc_tag; 3704 __be32 desc_len; 3705 uint8_t WWNN[WWN_SIZE]; 3706 uint8_t WWPN[WWN_SIZE]; 3707 } port_name_direct_desc; 3708 3709 /* Buffer Credit descriptor */ 3710 struct { 3711 __be32 desc_tag; 3712 __be32 desc_len; 3713 __be32 fcport_b2b; 3714 __be32 attached_fcport_b2b; 3715 __be32 fcport_rtt; 3716 } buffer_credit_desc; 3717 3718 /* Optical Element Data Descriptor */ 3719 struct { 3720 __be32 desc_tag; 3721 __be32 desc_len; 3722 __be16 high_alarm; 3723 __be16 low_alarm; 3724 __be16 high_warn; 3725 __be16 low_warn; 3726 __be32 element_flags; 3727 } optical_elmt_desc[5]; 3728 3729 /* Optical Product Data Descriptor */ 3730 struct { 3731 __be32 desc_tag; 3732 __be32 desc_len; 3733 uint8_t vendor_name[16]; 3734 uint8_t part_number[16]; 3735 uint8_t serial_number[16]; 3736 uint8_t revision[4]; 3737 uint8_t date[8]; 3738 } optical_prod_desc; 3739 }; 3740 3741 #define RDP_DESC_LEN(obj) \ 3742 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len)) 3743 3744 #define RDP_PORT_SPEED_1GB BIT_15 3745 #define RDP_PORT_SPEED_2GB BIT_14 3746 #define RDP_PORT_SPEED_4GB BIT_13 3747 #define RDP_PORT_SPEED_10GB BIT_12 3748 #define RDP_PORT_SPEED_8GB BIT_11 3749 #define RDP_PORT_SPEED_16GB BIT_10 3750 #define RDP_PORT_SPEED_32GB BIT_9 3751 #define RDP_PORT_SPEED_64GB BIT_8 3752 #define RDP_PORT_SPEED_UNKNOWN BIT_0 3753 3754 struct scsi_qlt_host { 3755 void *target_lport_ptr; 3756 struct mutex tgt_mutex; 3757 struct mutex tgt_host_action_mutex; 3758 struct qla_tgt *qla_tgt; 3759 }; 3760 3761 struct qlt_hw_data { 3762 /* Protected by hw lock */ 3763 uint32_t node_name_set:1; 3764 3765 dma_addr_t atio_dma; /* Physical address. */ 3766 struct atio *atio_ring; /* Base virtual address */ 3767 struct atio *atio_ring_ptr; /* Current address. */ 3768 uint16_t atio_ring_index; /* Current index. */ 3769 uint16_t atio_q_length; 3770 __le32 __iomem *atio_q_in; 3771 __le32 __iomem *atio_q_out; 3772 3773 struct qla_tgt_func_tmpl *tgt_ops; 3774 struct qla_tgt_vp_map *tgt_vp_map; 3775 3776 int saved_set; 3777 __le16 saved_exchange_count; 3778 __le32 saved_firmware_options_1; 3779 __le32 saved_firmware_options_2; 3780 __le32 saved_firmware_options_3; 3781 uint8_t saved_firmware_options[2]; 3782 uint8_t saved_add_firmware_options[2]; 3783 3784 uint8_t tgt_node_name[WWN_SIZE]; 3785 3786 struct dentry *dfs_tgt_sess; 3787 struct dentry *dfs_tgt_port_database; 3788 struct dentry *dfs_naqp; 3789 3790 struct list_head q_full_list; 3791 uint32_t num_pend_cmds; 3792 uint32_t num_qfull_cmds_alloc; 3793 uint32_t num_qfull_cmds_dropped; 3794 spinlock_t q_full_lock; 3795 uint32_t leak_exchg_thresh_hold; 3796 spinlock_t sess_lock; 3797 int num_act_qpairs; 3798 #define DEFAULT_NAQP 2 3799 spinlock_t atio_lock ____cacheline_aligned; 3800 struct btree_head32 host_map; 3801 }; 3802 3803 #define MAX_QFULL_CMDS_ALLOC 8192 3804 #define Q_FULL_THRESH_HOLD_PERCENT 90 3805 #define Q_FULL_THRESH_HOLD(ha) \ 3806 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3807 3808 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3809 3810 struct qla_hw_data_stat { 3811 u32 num_fw_dump; 3812 u32 num_mpi_reset; 3813 }; 3814 3815 /* 3816 * Qlogic host adapter specific data structure. 3817 */ 3818 struct qla_hw_data { 3819 struct pci_dev *pdev; 3820 /* SRB cache. */ 3821 #define SRB_MIN_REQ 128 3822 mempool_t *srb_mempool; 3823 3824 volatile struct { 3825 uint32_t mbox_int :1; 3826 uint32_t mbox_busy :1; 3827 uint32_t disable_risc_code_load :1; 3828 uint32_t enable_64bit_addressing :1; 3829 uint32_t enable_lip_reset :1; 3830 uint32_t enable_target_reset :1; 3831 uint32_t enable_lip_full_login :1; 3832 uint32_t enable_led_scheme :1; 3833 3834 uint32_t msi_enabled :1; 3835 uint32_t msix_enabled :1; 3836 uint32_t disable_serdes :1; 3837 uint32_t gpsc_supported :1; 3838 uint32_t npiv_supported :1; 3839 uint32_t pci_channel_io_perm_failure :1; 3840 uint32_t fce_enabled :1; 3841 uint32_t fac_supported :1; 3842 3843 uint32_t chip_reset_done :1; 3844 uint32_t running_gold_fw :1; 3845 uint32_t eeh_busy :1; 3846 uint32_t disable_msix_handshake :1; 3847 uint32_t fcp_prio_enabled :1; 3848 uint32_t isp82xx_fw_hung:1; 3849 uint32_t nic_core_hung:1; 3850 3851 uint32_t quiesce_owner:1; 3852 uint32_t nic_core_reset_hdlr_active:1; 3853 uint32_t nic_core_reset_owner:1; 3854 uint32_t isp82xx_no_md_cap:1; 3855 uint32_t host_shutting_down:1; 3856 uint32_t idc_compl_status:1; 3857 uint32_t mr_reset_hdlr_active:1; 3858 uint32_t mr_intr_valid:1; 3859 3860 uint32_t dport_enabled:1; 3861 uint32_t fawwpn_enabled:1; 3862 uint32_t exlogins_enabled:1; 3863 uint32_t exchoffld_enabled:1; 3864 3865 uint32_t lip_ae:1; 3866 uint32_t n2n_ae:1; 3867 uint32_t fw_started:1; 3868 uint32_t fw_init_done:1; 3869 3870 uint32_t lr_detected:1; 3871 3872 uint32_t rida_fmt2:1; 3873 uint32_t purge_mbox:1; 3874 uint32_t n2n_bigger:1; 3875 uint32_t secure_adapter:1; 3876 uint32_t secure_fw:1; 3877 /* Supported by Adapter */ 3878 uint32_t scm_supported_a:1; 3879 /* Supported by Firmware */ 3880 uint32_t scm_supported_f:1; 3881 /* Enabled in Driver */ 3882 uint32_t scm_enabled:1; 3883 uint32_t max_req_queue_warned:1; 3884 } flags; 3885 3886 uint16_t max_exchg; 3887 uint16_t lr_distance; /* 32G & above */ 3888 #define LR_DISTANCE_5K 1 3889 #define LR_DISTANCE_10K 0 3890 3891 /* This spinlock is used to protect "io transactions", you must 3892 * acquire it before doing any IO to the card, eg with RD_REG*() and 3893 * WRT_REG*() for the duration of your entire commandtransaction. 3894 * 3895 * This spinlock is of lower priority than the io request lock. 3896 */ 3897 3898 spinlock_t hardware_lock ____cacheline_aligned; 3899 int bars; 3900 int mem_only; 3901 device_reg_t *iobase; /* Base I/O address */ 3902 resource_size_t pio_address; 3903 3904 #define MIN_IOBASE_LEN 0x100 3905 dma_addr_t bar0_hdl; 3906 3907 void __iomem *cregbase; 3908 dma_addr_t bar2_hdl; 3909 #define BAR0_LEN_FX00 (1024 * 1024) 3910 #define BAR2_LEN_FX00 (128 * 1024) 3911 3912 uint32_t rqstq_intr_code; 3913 uint32_t mbx_intr_code; 3914 uint32_t req_que_len; 3915 uint32_t rsp_que_len; 3916 uint32_t req_que_off; 3917 uint32_t rsp_que_off; 3918 3919 /* Multi queue data structs */ 3920 device_reg_t *mqiobase; 3921 device_reg_t *msixbase; 3922 uint16_t msix_count; 3923 uint8_t mqenable; 3924 struct req_que **req_q_map; 3925 struct rsp_que **rsp_q_map; 3926 struct qla_qpair **queue_pair_map; 3927 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3928 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3929 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 3930 / sizeof(unsigned long)]; 3931 uint8_t max_req_queues; 3932 uint8_t max_rsp_queues; 3933 uint8_t max_qpairs; 3934 uint8_t num_qpairs; 3935 struct qla_qpair *base_qpair; 3936 struct qla_npiv_entry *npiv_info; 3937 uint16_t nvram_npiv_size; 3938 3939 uint16_t switch_cap; 3940 #define FLOGI_SEQ_DEL BIT_8 3941 #define FLOGI_MID_SUPPORT BIT_10 3942 #define FLOGI_VSAN_SUPPORT BIT_12 3943 #define FLOGI_SP_SUPPORT BIT_13 3944 3945 uint8_t port_no; /* Physical port of adapter */ 3946 uint8_t exch_starvation; 3947 3948 /* Timeout timers. */ 3949 uint8_t loop_down_abort_time; /* port down timer */ 3950 atomic_t loop_down_timer; /* loop down timer */ 3951 uint8_t link_down_timeout; /* link down timeout */ 3952 uint16_t max_loop_id; 3953 uint16_t max_fibre_devices; /* Maximum number of targets */ 3954 3955 uint16_t fb_rev; 3956 uint16_t min_external_loopid; /* First external loop Id */ 3957 3958 #define PORT_SPEED_UNKNOWN 0xFFFF 3959 #define PORT_SPEED_1GB 0x00 3960 #define PORT_SPEED_2GB 0x01 3961 #define PORT_SPEED_AUTO 0x02 3962 #define PORT_SPEED_4GB 0x03 3963 #define PORT_SPEED_8GB 0x04 3964 #define PORT_SPEED_16GB 0x05 3965 #define PORT_SPEED_32GB 0x06 3966 #define PORT_SPEED_64GB 0x07 3967 #define PORT_SPEED_10GB 0x13 3968 uint16_t link_data_rate; /* F/W operating speed */ 3969 uint16_t set_data_rate; /* Set by user */ 3970 3971 uint8_t current_topology; 3972 uint8_t prev_topology; 3973 #define ISP_CFG_NL 1 3974 #define ISP_CFG_N 2 3975 #define ISP_CFG_FL 4 3976 #define ISP_CFG_F 8 3977 3978 uint8_t operating_mode; /* F/W operating mode */ 3979 #define LOOP 0 3980 #define P2P 1 3981 #define LOOP_P2P 2 3982 #define P2P_LOOP 3 3983 uint8_t interrupts_on; 3984 uint32_t isp_abort_cnt; 3985 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 3986 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 3987 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 3988 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 3989 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 3990 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 3991 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 3992 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 3993 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061 3994 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081 3995 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089 3996 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281 3997 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289 3998 3999 uint32_t isp_type; 4000 #define DT_ISP2100 BIT_0 4001 #define DT_ISP2200 BIT_1 4002 #define DT_ISP2300 BIT_2 4003 #define DT_ISP2312 BIT_3 4004 #define DT_ISP2322 BIT_4 4005 #define DT_ISP6312 BIT_5 4006 #define DT_ISP6322 BIT_6 4007 #define DT_ISP2422 BIT_7 4008 #define DT_ISP2432 BIT_8 4009 #define DT_ISP5422 BIT_9 4010 #define DT_ISP5432 BIT_10 4011 #define DT_ISP2532 BIT_11 4012 #define DT_ISP8432 BIT_12 4013 #define DT_ISP8001 BIT_13 4014 #define DT_ISP8021 BIT_14 4015 #define DT_ISP2031 BIT_15 4016 #define DT_ISP8031 BIT_16 4017 #define DT_ISPFX00 BIT_17 4018 #define DT_ISP8044 BIT_18 4019 #define DT_ISP2071 BIT_19 4020 #define DT_ISP2271 BIT_20 4021 #define DT_ISP2261 BIT_21 4022 #define DT_ISP2061 BIT_22 4023 #define DT_ISP2081 BIT_23 4024 #define DT_ISP2089 BIT_24 4025 #define DT_ISP2281 BIT_25 4026 #define DT_ISP2289 BIT_26 4027 #define DT_ISP_LAST (DT_ISP2289 << 1) 4028 4029 uint32_t device_type; 4030 #define DT_T10_PI BIT_25 4031 #define DT_IIDMA BIT_26 4032 #define DT_FWI2 BIT_27 4033 #define DT_ZIO_SUPPORTED BIT_28 4034 #define DT_OEM_001 BIT_29 4035 #define DT_ISP2200A BIT_30 4036 #define DT_EXTENDED_IDS BIT_31 4037 4038 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 4039 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 4040 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 4041 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 4042 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 4043 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 4044 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 4045 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 4046 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 4047 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 4048 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 4049 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 4050 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 4051 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 4052 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 4053 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 4054 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 4055 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 4056 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 4057 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 4058 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 4059 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 4060 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 4061 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 4062 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081) 4063 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281) 4064 4065 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 4066 IS_QLA6312(ha) || IS_QLA6322(ha)) 4067 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 4068 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 4069 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 4070 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 4071 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 4072 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 4073 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha)) 4074 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 4075 IS_QLA84XX(ha)) 4076 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 4077 IS_QLA8031(ha) || IS_QLA8044(ha)) 4078 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 4079 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 4080 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 4081 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 4082 IS_QLA8044(ha) || IS_QLA27XX(ha) || \ 4083 IS_QLA28XX(ha)) 4084 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4085 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4086 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 4087 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4088 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4089 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4090 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4091 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 4092 4093 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 4094 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 4095 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 4096 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 4097 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 4098 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 4099 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 4100 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 4101 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4102 #define IS_BIDI_CAPABLE(ha) \ 4103 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4104 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 4105 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 4106 ((ha)->fw_attributes_ext[0] & BIT_0)) 4107 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4108 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4109 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 4110 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4111 IS_QLA28XX(ha)) 4112 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 4113 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 4114 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4115 IS_QLA28XX(ha)) 4116 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 4117 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4118 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4119 IS_QLA28XX(ha)) 4120 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4121 IS_QLA28XX(ha)) 4122 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 4123 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4124 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 4125 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4126 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4127 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ 4128 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4129 4130 /* HBA serial number */ 4131 uint8_t serial0; 4132 uint8_t serial1; 4133 uint8_t serial2; 4134 4135 /* NVRAM configuration data */ 4136 #define MAX_NVRAM_SIZE 4096 4137 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2) 4138 uint16_t nvram_size; 4139 uint16_t nvram_base; 4140 void *nvram; 4141 uint16_t vpd_size; 4142 uint16_t vpd_base; 4143 void *vpd; 4144 4145 uint16_t loop_reset_delay; 4146 uint8_t retry_count; 4147 uint8_t login_timeout; 4148 uint16_t r_a_tov; 4149 int port_down_retry_count; 4150 uint8_t mbx_count; 4151 uint8_t aen_mbx_count; 4152 atomic_t num_pend_mbx_stage1; 4153 atomic_t num_pend_mbx_stage2; 4154 atomic_t num_pend_mbx_stage3; 4155 uint16_t frame_payload_size; 4156 4157 uint32_t login_retry_count; 4158 /* SNS command interfaces. */ 4159 ms_iocb_entry_t *ms_iocb; 4160 dma_addr_t ms_iocb_dma; 4161 struct ct_sns_pkt *ct_sns; 4162 dma_addr_t ct_sns_dma; 4163 /* SNS command interfaces for 2200. */ 4164 struct sns_cmd_pkt *sns_cmd; 4165 dma_addr_t sns_cmd_dma; 4166 4167 #define SFP_DEV_SIZE 512 4168 #define SFP_BLOCK_SIZE 64 4169 #define SFP_RTDI_LEN SFP_BLOCK_SIZE 4170 4171 void *sfp_data; 4172 dma_addr_t sfp_data_dma; 4173 4174 struct qla_flt_header *flt; 4175 dma_addr_t flt_dma; 4176 4177 #define XGMAC_DATA_SIZE 4096 4178 void *xgmac_data; 4179 dma_addr_t xgmac_data_dma; 4180 4181 #define DCBX_TLV_DATA_SIZE 4096 4182 void *dcbx_tlv; 4183 dma_addr_t dcbx_tlv_dma; 4184 4185 struct task_struct *dpc_thread; 4186 uint8_t dpc_active; /* DPC routine is active */ 4187 4188 dma_addr_t gid_list_dma; 4189 struct gid_list_info *gid_list; 4190 int gid_list_info_size; 4191 4192 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 4193 #define DMA_POOL_SIZE 256 4194 struct dma_pool *s_dma_pool; 4195 4196 dma_addr_t init_cb_dma; 4197 init_cb_t *init_cb; 4198 int init_cb_size; 4199 dma_addr_t ex_init_cb_dma; 4200 struct ex_init_cb_81xx *ex_init_cb; 4201 dma_addr_t sf_init_cb_dma; 4202 struct init_sf_cb *sf_init_cb; 4203 4204 void *scm_fpin_els_buff; 4205 uint64_t scm_fpin_els_buff_size; 4206 bool scm_fpin_valid; 4207 bool scm_fpin_payload_size; 4208 4209 void *async_pd; 4210 dma_addr_t async_pd_dma; 4211 4212 #define ENABLE_EXTENDED_LOGIN BIT_7 4213 4214 /* Extended Logins */ 4215 void *exlogin_buf; 4216 dma_addr_t exlogin_buf_dma; 4217 int exlogin_size; 4218 4219 #define ENABLE_EXCHANGE_OFFLD BIT_2 4220 4221 /* Exchange Offload */ 4222 void *exchoffld_buf; 4223 dma_addr_t exchoffld_buf_dma; 4224 int exchoffld_size; 4225 int exchoffld_count; 4226 4227 /* n2n */ 4228 struct els_plogi_payload plogi_els_payld; 4229 4230 void *swl; 4231 4232 /* These are used by mailbox operations. */ 4233 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 4234 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 4235 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 4236 4237 mbx_cmd_t *mcp; 4238 struct mbx_cmd_32 *mcp32; 4239 4240 unsigned long mbx_cmd_flags; 4241 #define MBX_INTERRUPT 1 4242 #define MBX_INTR_WAIT 2 4243 #define MBX_UPDATE_FLASH_ACTIVE 3 4244 4245 struct mutex vport_lock; /* Virtual port synchronization */ 4246 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 4247 struct mutex mq_lock; /* multi-queue synchronization */ 4248 struct completion mbx_cmd_comp; /* Serialize mbx access */ 4249 struct completion mbx_intr_comp; /* Used for completion notification */ 4250 struct completion dcbx_comp; /* For set port config notification */ 4251 struct completion lb_portup_comp; /* Used to wait for link up during 4252 * loopback */ 4253 #define DCBX_COMP_TIMEOUT 20 4254 #define LB_PORTUP_COMP_TIMEOUT 10 4255 4256 int notify_dcbx_comp; 4257 int notify_lb_portup_comp; 4258 struct mutex selflogin_lock; 4259 4260 /* Basic firmware related information. */ 4261 uint16_t fw_major_version; 4262 uint16_t fw_minor_version; 4263 uint16_t fw_subminor_version; 4264 uint16_t fw_attributes; 4265 uint16_t fw_attributes_h; 4266 #define FW_ATTR_H_NVME_FBURST BIT_1 4267 #define FW_ATTR_H_NVME BIT_10 4268 #define FW_ATTR_H_NVME_UPDATED BIT_14 4269 4270 /* About firmware SCM support */ 4271 #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12 4272 /* Brocade fabric attached */ 4273 #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000 4274 /* Cisco fabric attached */ 4275 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000 4276 uint16_t fw_attributes_ext[2]; 4277 uint32_t fw_memory_size; 4278 uint32_t fw_transfer_size; 4279 uint32_t fw_srisc_address; 4280 #define RISC_START_ADDRESS_2100 0x1000 4281 #define RISC_START_ADDRESS_2300 0x800 4282 #define RISC_START_ADDRESS_2400 0x100000 4283 4284 uint16_t orig_fw_tgt_xcb_count; 4285 uint16_t cur_fw_tgt_xcb_count; 4286 uint16_t orig_fw_xcb_count; 4287 uint16_t cur_fw_xcb_count; 4288 uint16_t orig_fw_iocb_count; 4289 uint16_t cur_fw_iocb_count; 4290 uint16_t fw_max_fcf_count; 4291 4292 uint32_t fw_shared_ram_start; 4293 uint32_t fw_shared_ram_end; 4294 uint32_t fw_ddr_ram_start; 4295 uint32_t fw_ddr_ram_end; 4296 4297 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 4298 uint8_t fw_seriallink_options[4]; 4299 __le16 fw_seriallink_options24[4]; 4300 4301 uint8_t serdes_version[3]; 4302 uint8_t mpi_version[3]; 4303 uint32_t mpi_capabilities; 4304 uint8_t phy_version[3]; 4305 uint8_t pep_version[3]; 4306 4307 /* Firmware dump template */ 4308 struct fwdt { 4309 void *template; 4310 ulong length; 4311 ulong dump_size; 4312 } fwdt[2]; 4313 struct qla2xxx_fw_dump *fw_dump; 4314 uint32_t fw_dump_len; 4315 u32 fw_dump_alloc_len; 4316 bool fw_dumped; 4317 unsigned long fw_dump_cap_flags; 4318 #define RISC_PAUSE_CMPL 0 4319 #define DMA_SHUTDOWN_CMPL 1 4320 #define ISP_RESET_CMPL 2 4321 #define RISC_RDY_AFT_RESET 3 4322 #define RISC_SRAM_DUMP_CMPL 4 4323 #define RISC_EXT_MEM_DUMP_CMPL 5 4324 #define ISP_MBX_RDY 6 4325 #define ISP_SOFT_RESET_CMPL 7 4326 int fw_dump_reading; 4327 void *mpi_fw_dump; 4328 u32 mpi_fw_dump_len; 4329 unsigned int mpi_fw_dump_reading:1; 4330 unsigned int mpi_fw_dumped:1; 4331 int prev_minidump_failed; 4332 dma_addr_t eft_dma; 4333 void *eft; 4334 /* Current size of mctp dump is 0x086064 bytes */ 4335 #define MCTP_DUMP_SIZE 0x086064 4336 dma_addr_t mctp_dump_dma; 4337 void *mctp_dump; 4338 int mctp_dumped; 4339 int mctp_dump_reading; 4340 uint32_t chain_offset; 4341 struct dentry *dfs_dir; 4342 struct dentry *dfs_fce; 4343 struct dentry *dfs_tgt_counters; 4344 struct dentry *dfs_fw_resource_cnt; 4345 4346 dma_addr_t fce_dma; 4347 void *fce; 4348 uint32_t fce_bufs; 4349 uint16_t fce_mb[8]; 4350 uint64_t fce_wr, fce_rd; 4351 struct mutex fce_mutex; 4352 4353 uint32_t pci_attr; 4354 uint16_t chip_revision; 4355 4356 uint16_t product_id[4]; 4357 4358 uint8_t model_number[16+1]; 4359 char model_desc[80]; 4360 uint8_t adapter_id[16+1]; 4361 4362 /* Option ROM information. */ 4363 char *optrom_buffer; 4364 uint32_t optrom_size; 4365 int optrom_state; 4366 #define QLA_SWAITING 0 4367 #define QLA_SREADING 1 4368 #define QLA_SWRITING 2 4369 uint32_t optrom_region_start; 4370 uint32_t optrom_region_size; 4371 struct mutex optrom_mutex; 4372 4373 /* PCI expansion ROM image information. */ 4374 #define ROM_CODE_TYPE_BIOS 0 4375 #define ROM_CODE_TYPE_FCODE 1 4376 #define ROM_CODE_TYPE_EFI 3 4377 uint8_t bios_revision[2]; 4378 uint8_t efi_revision[2]; 4379 uint8_t fcode_revision[16]; 4380 uint32_t fw_revision[4]; 4381 4382 uint32_t gold_fw_version[4]; 4383 4384 /* Offsets for flash/nvram access (set to ~0 if not used). */ 4385 uint32_t flash_conf_off; 4386 uint32_t flash_data_off; 4387 uint32_t nvram_conf_off; 4388 uint32_t nvram_data_off; 4389 4390 uint32_t fdt_wrt_disable; 4391 uint32_t fdt_wrt_enable; 4392 uint32_t fdt_erase_cmd; 4393 uint32_t fdt_block_size; 4394 uint32_t fdt_unprotect_sec_cmd; 4395 uint32_t fdt_protect_sec_cmd; 4396 uint32_t fdt_wrt_sts_reg_cmd; 4397 4398 struct { 4399 uint32_t flt_region_flt; 4400 uint32_t flt_region_fdt; 4401 uint32_t flt_region_boot; 4402 uint32_t flt_region_boot_sec; 4403 uint32_t flt_region_fw; 4404 uint32_t flt_region_fw_sec; 4405 uint32_t flt_region_vpd_nvram; 4406 uint32_t flt_region_vpd_nvram_sec; 4407 uint32_t flt_region_vpd; 4408 uint32_t flt_region_vpd_sec; 4409 uint32_t flt_region_nvram; 4410 uint32_t flt_region_nvram_sec; 4411 uint32_t flt_region_npiv_conf; 4412 uint32_t flt_region_gold_fw; 4413 uint32_t flt_region_fcp_prio; 4414 uint32_t flt_region_bootload; 4415 uint32_t flt_region_img_status_pri; 4416 uint32_t flt_region_img_status_sec; 4417 uint32_t flt_region_aux_img_status_pri; 4418 uint32_t flt_region_aux_img_status_sec; 4419 }; 4420 uint8_t active_image; 4421 4422 /* Needed for BEACON */ 4423 uint16_t beacon_blink_led; 4424 uint8_t beacon_color_state; 4425 #define QLA_LED_GRN_ON 0x01 4426 #define QLA_LED_YLW_ON 0x02 4427 #define QLA_LED_ABR_ON 0x04 4428 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 4429 /* ISP2322: red, green, amber. */ 4430 uint16_t zio_mode; 4431 uint16_t zio_timer; 4432 4433 struct qla_msix_entry *msix_entries; 4434 4435 struct list_head vp_list; /* list of VP */ 4436 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 4437 sizeof(unsigned long)]; 4438 uint16_t num_vhosts; /* number of vports created */ 4439 uint16_t num_vsans; /* number of vsan created */ 4440 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 4441 int cur_vport_count; 4442 4443 struct qla_chip_state_84xx *cs84xx; 4444 struct isp_operations *isp_ops; 4445 struct workqueue_struct *wq; 4446 struct qlfc_fw fw_buf; 4447 4448 /* FCP_CMND priority support */ 4449 struct qla_fcp_prio_cfg *fcp_prio_cfg; 4450 4451 struct dma_pool *dl_dma_pool; 4452 #define DSD_LIST_DMA_POOL_SIZE 512 4453 4454 struct dma_pool *fcp_cmnd_dma_pool; 4455 mempool_t *ctx_mempool; 4456 #define FCP_CMND_DMA_POOL_SIZE 512 4457 4458 void __iomem *nx_pcibase; /* Base I/O address */ 4459 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4460 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4461 4462 uint32_t crb_win; 4463 uint32_t curr_window; 4464 uint32_t ddr_mn_window; 4465 unsigned long mn_win_crb; 4466 unsigned long ms_win_crb; 4467 int qdr_sn_window; 4468 uint32_t fcoe_dev_init_timeout; 4469 uint32_t fcoe_reset_timeout; 4470 rwlock_t hw_lock; 4471 uint16_t portnum; /* port number */ 4472 int link_width; 4473 struct fw_blob *hablob; 4474 struct qla82xx_legacy_intr_set nx_legacy_intr; 4475 4476 uint16_t gbl_dsd_inuse; 4477 uint16_t gbl_dsd_avail; 4478 struct list_head gbl_dsd_list; 4479 #define NUM_DSD_CHAIN 4096 4480 4481 uint8_t fw_type; 4482 uint32_t file_prd_off; /* File firmware product offset */ 4483 4484 uint32_t md_template_size; 4485 void *md_tmplt_hdr; 4486 dma_addr_t md_tmplt_hdr_dma; 4487 void *md_dump; 4488 uint32_t md_dump_size; 4489 4490 void *loop_id_map; 4491 4492 /* QLA83XX IDC specific fields */ 4493 uint32_t idc_audit_ts; 4494 uint32_t idc_extend_tmo; 4495 4496 /* DPC low-priority workqueue */ 4497 struct workqueue_struct *dpc_lp_wq; 4498 struct work_struct idc_aen; 4499 /* DPC high-priority workqueue */ 4500 struct workqueue_struct *dpc_hp_wq; 4501 struct work_struct nic_core_reset; 4502 struct work_struct idc_state_handler; 4503 struct work_struct nic_core_unrecoverable; 4504 struct work_struct board_disable; 4505 4506 struct mr_data_fx00 mr; 4507 uint32_t chip_reset; 4508 4509 struct qlt_hw_data tgt; 4510 int allow_cna_fw_dump; 4511 uint32_t fw_ability_mask; 4512 uint16_t min_supported_speed; 4513 uint16_t max_supported_speed; 4514 4515 /* DMA pool for the DIF bundling buffers */ 4516 struct dma_pool *dif_bundl_pool; 4517 #define DIF_BUNDLING_DMA_POOL_SIZE 1024 4518 struct { 4519 struct { 4520 struct list_head head; 4521 uint count; 4522 } good; 4523 struct { 4524 struct list_head head; 4525 uint count; 4526 } unusable; 4527 } pool; 4528 4529 unsigned long long dif_bundle_crossed_pages; 4530 unsigned long long dif_bundle_reads; 4531 unsigned long long dif_bundle_writes; 4532 unsigned long long dif_bundle_kallocs; 4533 unsigned long long dif_bundle_dma_allocs; 4534 4535 atomic_t nvme_active_aen_cnt; 4536 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4537 4538 uint8_t fc4_type_priority; 4539 4540 atomic_t zio_threshold; 4541 uint16_t last_zio_threshold; 4542 4543 #define DEFAULT_ZIO_THRESHOLD 5 4544 4545 struct qla_hw_data_stat stat; 4546 }; 4547 4548 struct active_regions { 4549 uint8_t global; 4550 struct { 4551 uint8_t board_config; 4552 uint8_t vpd_nvram; 4553 uint8_t npiv_config_0_1; 4554 uint8_t npiv_config_2_3; 4555 } aux; 4556 }; 4557 4558 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4559 #define FW_ABILITY_MAX_SPEED_16G 0x0 4560 #define FW_ABILITY_MAX_SPEED_32G 0x1 4561 #define FW_ABILITY_MAX_SPEED(ha) \ 4562 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4563 4564 #define QLA_GET_DATA_RATE 0 4565 #define QLA_SET_DATA_RATE_NOLR 1 4566 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */ 4567 4568 #define QLA_DEFAULT_PAYLOAD_SIZE 64 4569 /* 4570 * This item might be allocated with a size > sizeof(struct purex_item). 4571 * The "size" variable gives the size of the payload (which 4572 * is variable) starting at "iocb". 4573 */ 4574 struct purex_item { 4575 struct list_head list; 4576 struct scsi_qla_host *vha; 4577 void (*process_item)(struct scsi_qla_host *vha, 4578 struct purex_item *pkt); 4579 atomic_t in_use; 4580 uint16_t size; 4581 struct { 4582 uint8_t iocb[64]; 4583 } iocb; 4584 }; 4585 4586 #define SCM_FLAG_RDF_REJECT 0x00 4587 #define SCM_FLAG_RDF_COMPLETED 0x01 4588 4589 #define QLA_CON_PRIMITIVE_RECEIVED 0x1 4590 #define QLA_CONGESTION_ARB_WARNING 0x1 4591 #define QLA_CONGESTION_ARB_ALARM 0X2 4592 4593 /* 4594 * Qlogic scsi host structure 4595 */ 4596 typedef struct scsi_qla_host { 4597 struct list_head list; 4598 struct list_head vp_fcports; /* list of fcports */ 4599 struct list_head work_list; 4600 spinlock_t work_lock; 4601 struct work_struct iocb_work; 4602 4603 /* Commonly used flags and state information. */ 4604 struct Scsi_Host *host; 4605 unsigned long host_no; 4606 uint8_t host_str[16]; 4607 4608 volatile struct { 4609 uint32_t init_done :1; 4610 uint32_t online :1; 4611 uint32_t reset_active :1; 4612 4613 uint32_t management_server_logged_in :1; 4614 uint32_t process_response_queue :1; 4615 uint32_t difdix_supported:1; 4616 uint32_t delete_progress:1; 4617 4618 uint32_t fw_tgt_reported:1; 4619 uint32_t bbcr_enable:1; 4620 uint32_t qpairs_available:1; 4621 uint32_t qpairs_req_created:1; 4622 uint32_t qpairs_rsp_created:1; 4623 uint32_t nvme_enabled:1; 4624 uint32_t nvme_first_burst:1; 4625 } flags; 4626 4627 atomic_t loop_state; 4628 #define LOOP_TIMEOUT 1 4629 #define LOOP_DOWN 2 4630 #define LOOP_UP 3 4631 #define LOOP_UPDATE 4 4632 #define LOOP_READY 5 4633 #define LOOP_DEAD 6 4634 4635 unsigned long relogin_jif; 4636 unsigned long dpc_flags; 4637 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4638 #define RESET_ACTIVE 1 4639 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4640 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4641 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4642 #define LOOP_RESYNC_ACTIVE 5 4643 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4644 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4645 #define RELOGIN_NEEDED 8 4646 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4647 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4648 #define BEACON_BLINK_NEEDED 11 4649 #define REGISTER_FDMI_NEEDED 12 4650 #define FCPORT_UPDATE_NEEDED 13 4651 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4652 #define UNLOADING 15 4653 #define NPIV_CONFIG_NEEDED 16 4654 #define ISP_UNRECOVERABLE 17 4655 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4656 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4657 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4658 #define N2N_LINK_RESET 21 4659 #define PORT_UPDATE_NEEDED 22 4660 #define FX00_RESET_RECOVERY 23 4661 #define FX00_TARGET_SCAN 24 4662 #define FX00_CRITEMP_RECOVERY 25 4663 #define FX00_HOST_INFO_RESEND 26 4664 #define QPAIR_ONLINE_CHECK_NEEDED 27 4665 #define SET_NVME_ZIO_THRESHOLD_NEEDED 28 4666 #define DETECT_SFP_CHANGE 29 4667 #define N2N_LOGIN_NEEDED 30 4668 #define IOCB_WORK_ACTIVE 31 4669 #define SET_ZIO_THRESHOLD_NEEDED 32 4670 #define ISP_ABORT_TO_ROM 33 4671 #define VPORT_DELETE 34 4672 4673 #define PROCESS_PUREX_IOCB 63 4674 4675 unsigned long pci_flags; 4676 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4677 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4678 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4679 4680 uint32_t device_flags; 4681 #define SWITCH_FOUND BIT_0 4682 #define DFLG_NO_CABLE BIT_1 4683 #define DFLG_DEV_FAILED BIT_5 4684 4685 /* ISP configuration data. */ 4686 uint16_t loop_id; /* Host adapter loop id */ 4687 uint16_t self_login_loop_id; /* host adapter loop id 4688 * get it on self login 4689 */ 4690 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4691 * no need of allocating it for 4692 * each command 4693 */ 4694 4695 port_id_t d_id; /* Host adapter port id */ 4696 uint8_t marker_needed; 4697 uint16_t mgmt_svr_loop_id; 4698 4699 4700 4701 /* Timeout timers. */ 4702 uint8_t loop_down_abort_time; /* port down timer */ 4703 atomic_t loop_down_timer; /* loop down timer */ 4704 uint8_t link_down_timeout; /* link down timeout */ 4705 4706 uint32_t timer_active; 4707 struct timer_list timer; 4708 4709 uint8_t node_name[WWN_SIZE]; 4710 uint8_t port_name[WWN_SIZE]; 4711 uint8_t fabric_node_name[WWN_SIZE]; 4712 uint8_t fabric_port_name[WWN_SIZE]; 4713 4714 struct nvme_fc_local_port *nvme_local_port; 4715 struct completion nvme_del_done; 4716 4717 uint16_t fcoe_vlan_id; 4718 uint16_t fcoe_fcf_idx; 4719 uint8_t fcoe_vn_port_mac[6]; 4720 4721 /* list of commands waiting on workqueue */ 4722 struct list_head qla_cmd_list; 4723 struct list_head qla_sess_op_cmd_list; 4724 struct list_head unknown_atio_list; 4725 spinlock_t cmd_list_lock; 4726 struct delayed_work unknown_atio_work; 4727 4728 /* Counter to detect races between ELS and RSCN events */ 4729 atomic_t generation_tick; 4730 /* Time when global fcport update has been scheduled */ 4731 int total_fcport_update_gen; 4732 /* List of pending LOGOs, protected by tgt_mutex */ 4733 struct list_head logo_list; 4734 /* List of pending PLOGI acks, protected by hw lock */ 4735 struct list_head plogi_ack_list; 4736 4737 struct list_head qp_list; 4738 4739 uint32_t vp_abort_cnt; 4740 4741 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4742 uint16_t vp_idx; /* vport ID */ 4743 struct qla_qpair *qpair; /* base qpair */ 4744 4745 unsigned long vp_flags; 4746 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4747 #define VP_CREATE_NEEDED 1 4748 #define VP_BIND_NEEDED 2 4749 #define VP_DELETE_NEEDED 3 4750 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4751 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4752 atomic_t vp_state; 4753 #define VP_OFFLINE 0 4754 #define VP_ACTIVE 1 4755 #define VP_FAILED 2 4756 // #define VP_DISABLE 3 4757 uint16_t vp_err_state; 4758 uint16_t vp_prev_err_state; 4759 #define VP_ERR_UNKWN 0 4760 #define VP_ERR_PORTDWN 1 4761 #define VP_ERR_FAB_UNSUPPORTED 2 4762 #define VP_ERR_FAB_NORESOURCES 3 4763 #define VP_ERR_FAB_LOGOUT 4 4764 #define VP_ERR_ADAP_NORESOURCES 5 4765 struct qla_hw_data *hw; 4766 struct scsi_qlt_host vha_tgt; 4767 struct req_que *req; 4768 int fw_heartbeat_counter; 4769 int seconds_since_last_heartbeat; 4770 struct fc_host_statistics fc_host_stat; 4771 struct qla_statistics qla_stats; 4772 struct bidi_statistics bidi_stats; 4773 atomic_t vref_count; 4774 struct qla8044_reset_template reset_tmplt; 4775 uint16_t bbcr; 4776 4777 uint16_t u_ql2xexchoffld; 4778 uint16_t u_ql2xiniexchg; 4779 uint16_t qlini_mode; 4780 uint16_t ql2xexchoffld; 4781 uint16_t ql2xiniexchg; 4782 4783 struct purex_list { 4784 struct list_head head; 4785 spinlock_t lock; 4786 } purex_list; 4787 struct purex_item default_item; 4788 4789 struct name_list_extended gnl; 4790 /* Count of active session/fcport */ 4791 int fcport_count; 4792 wait_queue_head_t fcport_waitQ; 4793 wait_queue_head_t vref_waitq; 4794 uint8_t min_supported_speed; 4795 uint8_t n2n_node_name[WWN_SIZE]; 4796 uint8_t n2n_port_name[WWN_SIZE]; 4797 uint16_t n2n_id; 4798 __le16 dport_data[4]; 4799 struct list_head gpnid_list; 4800 struct fab_scan scan; 4801 uint8_t scm_fabric_connection_flags; 4802 4803 unsigned int irq_offset; 4804 } scsi_qla_host_t; 4805 4806 struct qla27xx_image_status { 4807 uint8_t image_status_mask; 4808 __le16 generation; 4809 uint8_t ver_major; 4810 uint8_t ver_minor; 4811 uint8_t bitmap; /* 28xx only */ 4812 uint8_t reserved[2]; 4813 __le32 checksum; 4814 __le32 signature; 4815 } __packed; 4816 4817 /* 28xx aux image status bimap values */ 4818 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0 4819 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1 4820 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2 4821 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3 4822 4823 #define SET_VP_IDX 1 4824 #define SET_AL_PA 2 4825 #define RESET_VP_IDX 3 4826 #define RESET_AL_PA 4 4827 struct qla_tgt_vp_map { 4828 uint8_t idx; 4829 scsi_qla_host_t *vha; 4830 }; 4831 4832 struct qla2_sgx { 4833 dma_addr_t dma_addr; /* OUT */ 4834 uint32_t dma_len; /* OUT */ 4835 4836 uint32_t tot_bytes; /* IN */ 4837 struct scatterlist *cur_sg; /* IN */ 4838 4839 /* for book keeping, bzero on initial invocation */ 4840 uint32_t bytes_consumed; 4841 uint32_t num_bytes; 4842 uint32_t tot_partial; 4843 4844 /* for debugging */ 4845 uint32_t num_sg; 4846 srb_t *sp; 4847 }; 4848 4849 #define QLA_FW_STARTED(_ha) { \ 4850 int i; \ 4851 _ha->flags.fw_started = 1; \ 4852 _ha->base_qpair->fw_started = 1; \ 4853 for (i = 0; i < _ha->max_qpairs; i++) { \ 4854 if (_ha->queue_pair_map[i]) \ 4855 _ha->queue_pair_map[i]->fw_started = 1; \ 4856 } \ 4857 } 4858 4859 #define QLA_FW_STOPPED(_ha) { \ 4860 int i; \ 4861 _ha->flags.fw_started = 0; \ 4862 _ha->base_qpair->fw_started = 0; \ 4863 for (i = 0; i < _ha->max_qpairs; i++) { \ 4864 if (_ha->queue_pair_map[i]) \ 4865 _ha->queue_pair_map[i]->fw_started = 0; \ 4866 } \ 4867 } 4868 4869 4870 #define SFUB_CHECKSUM_SIZE 4 4871 4872 struct secure_flash_update_block { 4873 uint32_t block_info; 4874 uint32_t signature_lo; 4875 uint32_t signature_hi; 4876 uint32_t signature_upper[0x3e]; 4877 }; 4878 4879 struct secure_flash_update_block_pk { 4880 uint32_t block_info; 4881 uint32_t signature_lo; 4882 uint32_t signature_hi; 4883 uint32_t signature_upper[0x3e]; 4884 uint32_t public_key[0x41]; 4885 }; 4886 4887 /* 4888 * Macros to help code, maintain, etc. 4889 */ 4890 #define LOOP_TRANSITION(ha) \ 4891 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4892 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 4893 atomic_read(&ha->loop_state) == LOOP_DOWN) 4894 4895 #define STATE_TRANSITION(ha) \ 4896 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4897 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 4898 4899 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 4900 atomic_inc(&__vha->vref_count); \ 4901 mb(); \ 4902 if (__vha->flags.delete_progress) { \ 4903 atomic_dec(&__vha->vref_count); \ 4904 wake_up(&__vha->vref_waitq); \ 4905 __bail = 1; \ 4906 } else { \ 4907 __bail = 0; \ 4908 } \ 4909 } while (0) 4910 4911 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 4912 atomic_dec(&__vha->vref_count); \ 4913 wake_up(&__vha->vref_waitq); \ 4914 } while (0) \ 4915 4916 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 4917 atomic_inc(&__qpair->ref_count); \ 4918 mb(); \ 4919 if (__qpair->delete_in_progress) { \ 4920 atomic_dec(&__qpair->ref_count); \ 4921 __bail = 1; \ 4922 } else { \ 4923 __bail = 0; \ 4924 } \ 4925 } while (0) 4926 4927 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 4928 atomic_dec(&__qpair->ref_count); \ 4929 4930 4931 #define QLA_ENA_CONF(_ha) {\ 4932 int i;\ 4933 _ha->base_qpair->enable_explicit_conf = 1; \ 4934 for (i = 0; i < _ha->max_qpairs; i++) { \ 4935 if (_ha->queue_pair_map[i]) \ 4936 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 4937 } \ 4938 } 4939 4940 #define QLA_DIS_CONF(_ha) {\ 4941 int i;\ 4942 _ha->base_qpair->enable_explicit_conf = 0; \ 4943 for (i = 0; i < _ha->max_qpairs; i++) { \ 4944 if (_ha->queue_pair_map[i]) \ 4945 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 4946 } \ 4947 } 4948 4949 /* 4950 * qla2x00 local function return status codes 4951 */ 4952 #define MBS_MASK 0x3fff 4953 4954 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 4955 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 4956 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 4957 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 4958 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 4959 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 4960 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 4961 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 4962 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 4963 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 4964 4965 #define QLA_FUNCTION_TIMEOUT 0x100 4966 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 4967 #define QLA_FUNCTION_FAILED 0x102 4968 #define QLA_MEMORY_ALLOC_FAILED 0x103 4969 #define QLA_LOCK_TIMEOUT 0x104 4970 #define QLA_ABORTED 0x105 4971 #define QLA_SUSPENDED 0x106 4972 #define QLA_BUSY 0x107 4973 #define QLA_ALREADY_REGISTERED 0x109 4974 #define QLA_OS_TIMER_EXPIRED 0x10a 4975 4976 #define NVRAM_DELAY() udelay(10) 4977 4978 /* 4979 * Flash support definitions 4980 */ 4981 #define OPTROM_SIZE_2300 0x20000 4982 #define OPTROM_SIZE_2322 0x100000 4983 #define OPTROM_SIZE_24XX 0x100000 4984 #define OPTROM_SIZE_25XX 0x200000 4985 #define OPTROM_SIZE_81XX 0x400000 4986 #define OPTROM_SIZE_82XX 0x800000 4987 #define OPTROM_SIZE_83XX 0x1000000 4988 #define OPTROM_SIZE_28XX 0x2000000 4989 4990 #define OPTROM_BURST_SIZE 0x1000 4991 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 4992 4993 #define QLA_DSDS_PER_IOCB 37 4994 4995 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 4996 4997 #define QLA_SG_ALL 1024 4998 4999 enum nexus_wait_type { 5000 WAIT_HOST = 0, 5001 WAIT_TARGET, 5002 WAIT_LUN, 5003 }; 5004 5005 /* Refer to SNIA SFF 8247 */ 5006 struct sff_8247_a0 { 5007 u8 txid; /* transceiver id */ 5008 u8 ext_txid; 5009 u8 connector; 5010 /* compliance code */ 5011 u8 eth_infi_cc3; /* ethernet, inifiband */ 5012 u8 sonet_cc4[2]; 5013 u8 eth_cc6; 5014 /* link length */ 5015 #define FC_LL_VL BIT_7 /* very long */ 5016 #define FC_LL_S BIT_6 /* Short */ 5017 #define FC_LL_I BIT_5 /* Intermidiate*/ 5018 #define FC_LL_L BIT_4 /* Long */ 5019 #define FC_LL_M BIT_3 /* Medium */ 5020 #define FC_LL_SA BIT_2 /* ShortWave laser */ 5021 #define FC_LL_LC BIT_1 /* LongWave laser */ 5022 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 5023 u8 fc_ll_cc7; 5024 /* FC technology */ 5025 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 5026 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 5027 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 5028 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 5029 #define FC_TEC_ACT BIT_3 /* Active cable */ 5030 #define FC_TEC_PAS BIT_2 /* Passive cable */ 5031 u8 fc_tec_cc8; 5032 /* Transmission Media */ 5033 #define FC_MED_TW BIT_7 /* Twin Ax */ 5034 #define FC_MED_TP BIT_6 /* Twited Pair */ 5035 #define FC_MED_MI BIT_5 /* Min Coax */ 5036 #define FC_MED_TV BIT_4 /* Video Coax */ 5037 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 5038 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 5039 #define FC_MED_SM BIT_0 /* Single Mode */ 5040 u8 fc_med_cc9; 5041 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 5042 #define FC_SP_12 BIT_7 5043 #define FC_SP_8 BIT_6 5044 #define FC_SP_16 BIT_5 5045 #define FC_SP_4 BIT_4 5046 #define FC_SP_32 BIT_3 5047 #define FC_SP_2 BIT_2 5048 #define FC_SP_1 BIT_0 5049 u8 fc_sp_cc10; 5050 u8 encode; 5051 u8 bitrate; 5052 u8 rate_id; 5053 u8 length_km; /* offset 14/eh */ 5054 u8 length_100m; 5055 u8 length_50um_10m; 5056 u8 length_62um_10m; 5057 u8 length_om4_10m; 5058 u8 length_om3_10m; 5059 #define SFF_VEN_NAME_LEN 16 5060 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 5061 u8 tx_compat; 5062 u8 vendor_oui[3]; 5063 #define SFF_PART_NAME_LEN 16 5064 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 5065 u8 vendor_rev[4]; 5066 u8 wavelength[2]; 5067 u8 resv; 5068 u8 cc_base; 5069 u8 options[2]; /* offset 64 */ 5070 u8 br_max; 5071 u8 br_min; 5072 u8 vendor_sn[16]; 5073 u8 date_code[8]; 5074 u8 diag; 5075 u8 enh_options; 5076 u8 sff_revision; 5077 u8 cc_ext; 5078 u8 vendor_specific[32]; 5079 u8 resv2[128]; 5080 }; 5081 5082 /* BPM -- Buffer Plus Management support. */ 5083 #define IS_BPM_CAPABLE(ha) \ 5084 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 5085 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5086 #define IS_BPM_RANGE_CAPABLE(ha) \ 5087 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5088 #define IS_BPM_ENABLED(vha) \ 5089 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw)) 5090 5091 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016 5092 5093 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 5094 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha))) 5095 5096 #define SAVE_TOPO(_ha) { \ 5097 if (_ha->current_topology) \ 5098 _ha->prev_topology = _ha->current_topology; \ 5099 } 5100 5101 #define N2N_TOPO(ha) \ 5102 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ 5103 ha->current_topology == ISP_CFG_N || \ 5104 !ha->current_topology) 5105 5106 #define NVME_TYPE(fcport) \ 5107 (fcport->fc4_type & FS_FC4TYPE_NVME) \ 5108 5109 #define FCP_TYPE(fcport) \ 5110 (fcport->fc4_type & FS_FC4TYPE_FCP) \ 5111 5112 #define NVME_ONLY_TARGET(fcport) \ 5113 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \ 5114 5115 #define NVME_FCP_TARGET(fcport) \ 5116 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \ 5117 5118 #define NVME_TARGET(ha, fcport) \ 5119 ((NVME_FCP_TARGET(fcport) && \ 5120 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) || \ 5121 NVME_ONLY_TARGET(fcport)) \ 5122 5123 #define PRLI_PHASE(_cls) \ 5124 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP)) 5125 5126 #include "qla_target.h" 5127 #include "qla_gbl.h" 5128 #include "qla_dbg.h" 5129 #include "qla_inline.h" 5130 #endif 5131