1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #ifndef __QLA_DEF_H 7 #define __QLA_DEF_H 8 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/types.h> 12 #include <linux/module.h> 13 #include <linux/list.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/sched.h> 17 #include <linux/slab.h> 18 #include <linux/dmapool.h> 19 #include <linux/mempool.h> 20 #include <linux/spinlock.h> 21 #include <linux/completion.h> 22 #include <linux/interrupt.h> 23 #include <linux/workqueue.h> 24 #include <linux/firmware.h> 25 #include <linux/mutex.h> 26 #include <linux/btree.h> 27 28 #include <scsi/scsi.h> 29 #include <scsi/scsi_host.h> 30 #include <scsi/scsi_device.h> 31 #include <scsi/scsi_cmnd.h> 32 #include <scsi/scsi_transport_fc.h> 33 #include <scsi/scsi_bsg_fc.h> 34 35 #include <uapi/scsi/fc/fc_els.h> 36 37 #define QLA_DFS_DEFINE_DENTRY(_debugfs_file_name) \ 38 struct dentry *dfs_##_debugfs_file_name 39 #define QLA_DFS_ROOT_DEFINE_DENTRY(_debugfs_file_name) \ 40 struct dentry *qla_dfs_##_debugfs_file_name 41 42 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 43 typedef struct { 44 uint8_t domain; 45 uint8_t area; 46 uint8_t al_pa; 47 } be_id_t; 48 49 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 50 typedef struct { 51 uint8_t al_pa; 52 uint8_t area; 53 uint8_t domain; 54 } le_id_t; 55 56 /* 57 * 24 bit port ID type definition. 58 */ 59 typedef union { 60 uint32_t b24 : 24; 61 struct { 62 #ifdef __BIG_ENDIAN 63 uint8_t domain; 64 uint8_t area; 65 uint8_t al_pa; 66 #elif defined(__LITTLE_ENDIAN) 67 uint8_t al_pa; 68 uint8_t area; 69 uint8_t domain; 70 #else 71 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 72 #endif 73 uint8_t rsvd_1; 74 } b; 75 } port_id_t; 76 #define INVALID_PORT_ID 0xFFFFFF 77 78 #include "qla_bsg.h" 79 #include "qla_dsd.h" 80 #include "qla_nx.h" 81 #include "qla_nx2.h" 82 #include "qla_nvme.h" 83 #define QLA2XXX_DRIVER_NAME "qla2xxx" 84 #define QLA2XXX_APIDEV "ql2xapidev" 85 #define QLA2XXX_MANUFACTURER "Marvell Semiconductor, Inc." 86 87 /* 88 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 89 * but that's fine as we don't look at the last 24 ones for 90 * ISP2100 HBAs. 91 */ 92 #define MAILBOX_REGISTER_COUNT_2100 8 93 #define MAILBOX_REGISTER_COUNT_2200 24 94 #define MAILBOX_REGISTER_COUNT 32 95 96 #define QLA2200A_RISC_ROM_VER 4 97 #define FPM_2300 6 98 #define FPM_2310 7 99 100 #include "qla_settings.h" 101 102 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 103 104 /* 105 * Data bit definitions 106 */ 107 #define BIT_0 0x1 108 #define BIT_1 0x2 109 #define BIT_2 0x4 110 #define BIT_3 0x8 111 #define BIT_4 0x10 112 #define BIT_5 0x20 113 #define BIT_6 0x40 114 #define BIT_7 0x80 115 #define BIT_8 0x100 116 #define BIT_9 0x200 117 #define BIT_10 0x400 118 #define BIT_11 0x800 119 #define BIT_12 0x1000 120 #define BIT_13 0x2000 121 #define BIT_14 0x4000 122 #define BIT_15 0x8000 123 #define BIT_16 0x10000 124 #define BIT_17 0x20000 125 #define BIT_18 0x40000 126 #define BIT_19 0x80000 127 #define BIT_20 0x100000 128 #define BIT_21 0x200000 129 #define BIT_22 0x400000 130 #define BIT_23 0x800000 131 #define BIT_24 0x1000000 132 #define BIT_25 0x2000000 133 #define BIT_26 0x4000000 134 #define BIT_27 0x8000000 135 #define BIT_28 0x10000000 136 #define BIT_29 0x20000000 137 #define BIT_30 0x40000000 138 #define BIT_31 0x80000000 139 140 #define LSB(x) ((uint8_t)(x)) 141 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 142 143 #define LSW(x) ((uint16_t)(x)) 144 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 145 146 #define LSD(x) ((uint32_t)((uint64_t)(x))) 147 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 148 149 static inline uint32_t make_handle(uint16_t x, uint16_t y) 150 { 151 return ((uint32_t)x << 16) | y; 152 } 153 154 /* 155 * I/O register 156 */ 157 158 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr) 159 { 160 return readb(addr); 161 } 162 163 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr) 164 { 165 return readw(addr); 166 } 167 168 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr) 169 { 170 return readl(addr); 171 } 172 173 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr) 174 { 175 return readb_relaxed(addr); 176 } 177 178 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr) 179 { 180 return readw_relaxed(addr); 181 } 182 183 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr) 184 { 185 return readl_relaxed(addr); 186 } 187 188 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data) 189 { 190 return writeb(data, addr); 191 } 192 193 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data) 194 { 195 return writew(data, addr); 196 } 197 198 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data) 199 { 200 return writel(data, addr); 201 } 202 203 /* 204 * ISP83XX specific remote register addresses 205 */ 206 #define QLA83XX_LED_PORT0 0x00201320 207 #define QLA83XX_LED_PORT1 0x00201328 208 #define QLA83XX_IDC_DEV_STATE 0x22102384 209 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 210 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 211 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 212 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 213 #define QLA83XX_IDC_CONTROL 0x22102390 214 #define QLA83XX_IDC_AUDIT 0x22102394 215 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 216 #define QLA83XX_DRIVER_LOCKID 0x22102104 217 #define QLA83XX_DRIVER_LOCK 0x8111c028 218 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 219 #define QLA83XX_FLASH_LOCKID 0x22102100 220 #define QLA83XX_FLASH_LOCK 0x8111c010 221 #define QLA83XX_FLASH_UNLOCK 0x8111c014 222 #define QLA83XX_DEV_PARTINFO1 0x221023e0 223 #define QLA83XX_DEV_PARTINFO2 0x221023e4 224 #define QLA83XX_FW_HEARTBEAT 0x221020b0 225 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 226 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 227 228 /* 83XX: Macros defining 8200 AEN Reason codes */ 229 #define IDC_DEVICE_STATE_CHANGE BIT_0 230 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 231 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 232 #define IDC_HEARTBEAT_FAILURE BIT_3 233 234 /* 83XX: Macros defining 8200 AEN Error-levels */ 235 #define ERR_LEVEL_NON_FATAL 0x1 236 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 237 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 238 239 /* 83XX: Macros for IDC Version */ 240 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 241 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 242 243 /* 83XX: Macros for scheduling dpc tasks */ 244 #define QLA83XX_NIC_CORE_RESET 0x1 245 #define QLA83XX_IDC_STATE_HANDLER 0x2 246 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 247 248 /* 83XX: Macros for defining IDC-Control bits */ 249 #define QLA83XX_IDC_RESET_DISABLED BIT_0 250 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 251 252 /* 83XX: Macros for different timeouts */ 253 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 254 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 255 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 256 257 /* 83XX: Macros for defining class in DEV-Partition Info register */ 258 #define QLA83XX_CLASS_TYPE_NONE 0x0 259 #define QLA83XX_CLASS_TYPE_NIC 0x1 260 #define QLA83XX_CLASS_TYPE_FCOE 0x2 261 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 262 263 /* 83XX: Macros for IDC Lock-Recovery stages */ 264 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 265 * lock-recovery 266 */ 267 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 268 269 /* 83XX: Macros for IDC Audit type */ 270 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 271 * dev-state change to NEED-RESET 272 * or NEED-QUIESCENT 273 */ 274 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 275 * reset-recovery completion is 276 * second 277 */ 278 /* ISP2031: Values for laser on/off */ 279 #define PORT_0_2031 0x00201340 280 #define PORT_1_2031 0x00201350 281 #define LASER_ON_2031 0x01800100 282 #define LASER_OFF_2031 0x01800180 283 284 /* 285 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 286 * 133Mhz slot. 287 */ 288 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 289 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr)) 290 291 /* 292 * Fibre Channel device definitions. 293 */ 294 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 295 #define MAX_FIBRE_DEVICES_2100 512 296 #define MAX_FIBRE_DEVICES_2400 2048 297 #define MAX_FIBRE_DEVICES_LOOP 128 298 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 299 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 300 #define MAX_FIBRE_LUNS 0xFFFF 301 #define MAX_HOST_COUNT 16 302 303 /* 304 * Host adapter default definitions. 305 */ 306 #define MAX_BUSES 1 /* We only have one bus today */ 307 #define MIN_LUNS 8 308 #define MAX_LUNS MAX_FIBRE_LUNS 309 #define MAX_CMDS_PER_LUN 255 310 311 /* 312 * Fibre Channel device definitions. 313 */ 314 #define SNS_LAST_LOOP_ID_2100 0xfe 315 #define SNS_LAST_LOOP_ID_2300 0x7ff 316 317 #define LAST_LOCAL_LOOP_ID 0x7d 318 #define SNS_FL_PORT 0x7e 319 #define FABRIC_CONTROLLER 0x7f 320 #define SIMPLE_NAME_SERVER 0x80 321 #define SNS_FIRST_LOOP_ID 0x81 322 #define MANAGEMENT_SERVER 0xfe 323 #define BROADCAST 0xff 324 325 /* 326 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 327 * valid range of an N-PORT id is 0 through 0x7ef. 328 */ 329 #define NPH_LAST_HANDLE 0x7ee 330 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ 331 #define NPH_SNS 0x7fc /* FFFFFC */ 332 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 333 #define NPH_F_PORT 0x7fe /* FFFFFE */ 334 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 335 336 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 337 338 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 339 #include "qla_fw.h" 340 341 struct name_list_extended { 342 struct get_name_list_extended *l; 343 dma_addr_t ldma; 344 struct list_head fcports; 345 u32 size; 346 u8 sent; 347 }; 348 349 struct els_reject { 350 struct fc_els_ls_rjt *c; 351 dma_addr_t cdma; 352 u16 size; 353 }; 354 355 /* 356 * Timeout timer counts in seconds 357 */ 358 #define PORT_RETRY_TIME 1 359 #define LOOP_DOWN_TIMEOUT 60 360 #define LOOP_DOWN_TIME 255 /* 240 */ 361 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 362 363 #define DEFAULT_OUTSTANDING_COMMANDS 4096 364 #define MIN_OUTSTANDING_COMMANDS 128 365 366 /* ISP request and response entry counts (37-65535) */ 367 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 368 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 369 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 370 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 371 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 372 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 373 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 374 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 375 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 376 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 377 #define FW_DEF_EXCHANGES_CNT 2048 378 #define FW_MAX_EXCHANGES_CNT (32 * 1024) 379 #define REDUCE_EXCHANGES_CNT (8 * 1024) 380 381 #define SET_DID_STATUS(stat_var, status) (stat_var = status << 16) 382 383 struct req_que; 384 struct qla_tgt_sess; 385 386 struct qla_buf_dsc { 387 u16 tag; 388 #define TAG_FREED 0xffff 389 void *buf; 390 dma_addr_t buf_dma; 391 }; 392 393 /* 394 * SCSI Request Block 395 */ 396 struct srb_cmd { 397 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 398 uint32_t request_sense_length; 399 uint32_t fw_sense_length; 400 uint8_t *request_sense_ptr; 401 struct crc_context *crc_ctx; 402 struct ct6_dsd ct6_ctx; 403 struct qla_buf_dsc buf_dsc; 404 }; 405 406 /* 407 * SRB flag definitions 408 */ 409 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 410 #define SRB_GOT_BUF BIT_1 411 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 412 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 413 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 414 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 415 #define SRB_WAKEUP_ON_COMP BIT_6 416 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */ 417 #define SRB_EDIF_CLEANUP_DELETE BIT_9 418 419 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 420 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 421 #define ISP_REG16_DISCONNECT 0xFFFF 422 423 static inline le_id_t be_id_to_le(be_id_t id) 424 { 425 le_id_t res; 426 427 res.domain = id.domain; 428 res.area = id.area; 429 res.al_pa = id.al_pa; 430 431 return res; 432 } 433 434 static inline be_id_t le_id_to_be(le_id_t id) 435 { 436 be_id_t res; 437 438 res.domain = id.domain; 439 res.area = id.area; 440 res.al_pa = id.al_pa; 441 442 return res; 443 } 444 445 static inline port_id_t be_to_port_id(be_id_t id) 446 { 447 port_id_t res; 448 449 res.b.domain = id.domain; 450 res.b.area = id.area; 451 res.b.al_pa = id.al_pa; 452 res.b.rsvd_1 = 0; 453 454 return res; 455 } 456 457 static inline be_id_t port_id_to_be_id(port_id_t port_id) 458 { 459 be_id_t res; 460 461 res.domain = port_id.b.domain; 462 res.area = port_id.b.area; 463 res.al_pa = port_id.b.al_pa; 464 465 return res; 466 } 467 468 struct els_logo_payload { 469 uint8_t opcode; 470 uint8_t rsvd[3]; 471 uint8_t s_id[3]; 472 uint8_t rsvd1[1]; 473 uint8_t wwpn[WWN_SIZE]; 474 }; 475 476 struct els_plogi_payload { 477 uint8_t opcode; 478 uint8_t rsvd[3]; 479 __be32 data[112 / 4]; 480 }; 481 482 struct ct_arg { 483 void *iocb; 484 u16 nport_handle; 485 dma_addr_t req_dma; 486 dma_addr_t rsp_dma; 487 u32 req_size; 488 u32 rsp_size; 489 u32 req_allocated_size; 490 u32 rsp_allocated_size; 491 void *req; 492 void *rsp; 493 port_id_t id; 494 }; 495 496 /* 497 * SRB extensions. 498 */ 499 struct srb_iocb { 500 union { 501 struct { 502 uint16_t flags; 503 #define SRB_LOGIN_RETRIED BIT_0 504 #define SRB_LOGIN_COND_PLOGI BIT_1 505 #define SRB_LOGIN_SKIP_PRLI BIT_2 506 #define SRB_LOGIN_NVME_PRLI BIT_3 507 #define SRB_LOGIN_PRLI_ONLY BIT_4 508 #define SRB_LOGIN_FCSP BIT_5 509 uint16_t data[2]; 510 u32 iop[2]; 511 } logio; 512 struct { 513 #define ELS_DCMD_TIMEOUT 20 514 #define ELS_DCMD_LOGO 0x5 515 uint32_t flags; 516 uint32_t els_cmd; 517 struct completion comp; 518 struct els_logo_payload *els_logo_pyld; 519 dma_addr_t els_logo_pyld_dma; 520 } els_logo; 521 struct els_plogi { 522 #define ELS_DCMD_PLOGI 0x3 523 uint32_t flags; 524 uint32_t els_cmd; 525 struct completion comp; 526 struct els_plogi_payload *els_plogi_pyld; 527 struct els_plogi_payload *els_resp_pyld; 528 u32 tx_size; 529 u32 rx_size; 530 dma_addr_t els_plogi_pyld_dma; 531 dma_addr_t els_resp_pyld_dma; 532 __le32 fw_status[3]; 533 __le16 comp_status; 534 __le16 len; 535 } els_plogi; 536 struct { 537 /* 538 * Values for flags field below are as 539 * defined in tsk_mgmt_entry struct 540 * for control_flags field in qla_fw.h. 541 */ 542 uint64_t lun; 543 uint32_t flags; 544 uint32_t data; 545 struct completion comp; 546 __le16 comp_status; 547 } tmf; 548 struct { 549 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 550 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 551 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 552 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 553 #define FXDISC_TIMEOUT 20 554 uint8_t flags; 555 uint32_t req_len; 556 uint32_t rsp_len; 557 void *req_addr; 558 void *rsp_addr; 559 dma_addr_t req_dma_handle; 560 dma_addr_t rsp_dma_handle; 561 __le32 adapter_id; 562 __le32 adapter_id_hi; 563 __le16 req_func_type; 564 __le32 req_data; 565 __le32 req_data_extra; 566 __le32 result; 567 __le32 seq_number; 568 __le16 fw_flags; 569 struct completion fxiocb_comp; 570 __le32 reserved_0; 571 uint8_t reserved_1; 572 } fxiocb; 573 struct { 574 uint32_t cmd_hndl; 575 __le16 comp_status; 576 __le16 req_que_no; 577 struct completion comp; 578 } abt; 579 struct ct_arg ctarg; 580 #define MAX_IOCB_MB_REG 28 581 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 582 struct { 583 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 584 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 585 void *out, *in; 586 dma_addr_t out_dma, in_dma; 587 struct completion comp; 588 int rc; 589 } mbx; 590 struct { 591 struct imm_ntfy_from_isp *ntfy; 592 } nack; 593 struct { 594 __le16 comp_status; 595 __le16 rsp_pyld_len; 596 uint8_t aen_op; 597 void *desc; 598 599 /* These are only used with ls4 requests */ 600 int cmd_len; 601 int rsp_len; 602 dma_addr_t cmd_dma; 603 dma_addr_t rsp_dma; 604 enum nvmefc_fcp_datadir dir; 605 uint32_t dl; 606 uint32_t timeout_sec; 607 struct list_head entry; 608 } nvme; 609 struct { 610 u16 cmd; 611 u16 vp_index; 612 } ctrlvp; 613 struct { 614 struct edif_sa_ctl *sa_ctl; 615 struct qla_sa_update_frame sa_frame; 616 } sa_update; 617 } u; 618 619 struct timer_list timer; 620 void (*timeout)(void *); 621 }; 622 623 /* Values for srb_ctx type */ 624 #define SRB_LOGIN_CMD 1 625 #define SRB_LOGOUT_CMD 2 626 #define SRB_ELS_CMD_RPT 3 627 #define SRB_ELS_CMD_HST 4 628 #define SRB_CT_CMD 5 629 #define SRB_ADISC_CMD 6 630 #define SRB_TM_CMD 7 631 #define SRB_SCSI_CMD 8 632 #define SRB_BIDI_CMD 9 633 #define SRB_FXIOCB_DCMD 10 634 #define SRB_FXIOCB_BCMD 11 635 #define SRB_ABT_CMD 12 636 #define SRB_ELS_DCMD 13 637 #define SRB_MB_IOCB 14 638 #define SRB_CT_PTHRU_CMD 15 639 #define SRB_NACK_PLOGI 16 640 #define SRB_NACK_PRLI 17 641 #define SRB_NACK_LOGO 18 642 #define SRB_NVME_CMD 19 643 #define SRB_NVME_LS 20 644 #define SRB_PRLI_CMD 21 645 #define SRB_CTRL_VP 22 646 #define SRB_PRLO_CMD 23 647 #define SRB_SA_UPDATE 25 648 #define SRB_ELS_CMD_HST_NOLOGIN 26 649 #define SRB_SA_REPLACE 27 650 651 struct qla_els_pt_arg { 652 u8 els_opcode; 653 u8 vp_idx; 654 __le16 nport_handle; 655 u16 control_flags, ox_id; 656 __le32 rx_xchg_address; 657 port_id_t did, sid; 658 u32 tx_len, tx_byte_count, rx_len, rx_byte_count; 659 dma_addr_t tx_addr, rx_addr; 660 661 }; 662 663 enum { 664 TYPE_SRB, 665 TYPE_TGT_CMD, 666 TYPE_TGT_TMCMD, /* task management */ 667 }; 668 669 struct iocb_resource { 670 u8 res_type; 671 u8 exch_cnt; 672 u16 iocb_cnt; 673 }; 674 675 struct bsg_cmd { 676 struct bsg_job *bsg_job; 677 union { 678 struct qla_els_pt_arg els_arg; 679 } u; 680 }; 681 682 typedef struct srb { 683 /* 684 * Do not move cmd_type field, it needs to 685 * line up with qla_tgt_cmd->cmd_type 686 */ 687 uint8_t cmd_type; 688 uint8_t pad[3]; 689 struct iocb_resource iores; 690 struct kref cmd_kref; /* need to migrate ref_count over to this */ 691 void *priv; 692 wait_queue_head_t nvme_ls_waitq; 693 struct fc_port *fcport; 694 struct scsi_qla_host *vha; 695 unsigned int start_timer:1; 696 697 uint32_t handle; 698 uint16_t flags; 699 uint16_t type; 700 const char *name; 701 int iocbs; 702 struct qla_qpair *qpair; 703 struct srb *cmd_sp; 704 struct list_head elem; 705 u32 gen1; /* scratch */ 706 u32 gen2; /* scratch */ 707 int rc; 708 int retry_count; 709 struct completion *comp; 710 union { 711 struct srb_iocb iocb_cmd; 712 struct bsg_job *bsg_job; 713 struct srb_cmd scmd; 714 struct bsg_cmd bsg_cmd; 715 } u; 716 struct { 717 bool remapped; 718 struct { 719 dma_addr_t dma; 720 void *buf; 721 uint len; 722 } req; 723 struct { 724 dma_addr_t dma; 725 void *buf; 726 uint len; 727 } rsp; 728 } remap; 729 /* 730 * Report completion status @res and call sp_put(@sp). @res is 731 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a 732 * QLA_* status value. 733 */ 734 void (*done)(struct srb *sp, int res); 735 /* Stop the timer and free @sp. Only used by the FCP code. */ 736 void (*free)(struct srb *sp); 737 /* 738 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe 739 * code. 740 */ 741 void (*put_fn)(struct kref *kref); 742 743 /* 744 * Report completion for asynchronous commands. 745 */ 746 void (*async_done)(struct srb *sp, int res); 747 } srb_t; 748 749 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 750 751 #define GET_CMD_SENSE_LEN(sp) \ 752 (sp->u.scmd.request_sense_length) 753 #define SET_CMD_SENSE_LEN(sp, len) \ 754 (sp->u.scmd.request_sense_length = len) 755 #define GET_CMD_SENSE_PTR(sp) \ 756 (sp->u.scmd.request_sense_ptr) 757 #define SET_CMD_SENSE_PTR(sp, ptr) \ 758 (sp->u.scmd.request_sense_ptr = ptr) 759 #define GET_FW_SENSE_LEN(sp) \ 760 (sp->u.scmd.fw_sense_length) 761 #define SET_FW_SENSE_LEN(sp, len) \ 762 (sp->u.scmd.fw_sense_length = len) 763 764 struct msg_echo_lb { 765 dma_addr_t send_dma; 766 dma_addr_t rcv_dma; 767 uint16_t req_sg_cnt; 768 uint16_t rsp_sg_cnt; 769 uint16_t options; 770 uint32_t transfer_size; 771 uint32_t iteration_count; 772 }; 773 774 /* 775 * ISP I/O Register Set structure definitions. 776 */ 777 struct device_reg_2xxx { 778 __le16 flash_address; /* Flash BIOS address */ 779 __le16 flash_data; /* Flash BIOS data */ 780 __le16 unused_1[1]; /* Gap */ 781 __le16 ctrl_status; /* Control/Status */ 782 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 783 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 784 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 785 786 __le16 ictrl; /* Interrupt control */ 787 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 788 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 789 790 __le16 istatus; /* Interrupt status */ 791 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 792 793 __le16 semaphore; /* Semaphore */ 794 __le16 nvram; /* NVRAM register. */ 795 #define NVR_DESELECT 0 796 #define NVR_BUSY BIT_15 797 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 798 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 799 #define NVR_DATA_IN BIT_3 800 #define NVR_DATA_OUT BIT_2 801 #define NVR_SELECT BIT_1 802 #define NVR_CLOCK BIT_0 803 804 #define NVR_WAIT_CNT 20000 805 806 union { 807 struct { 808 __le16 mailbox0; 809 __le16 mailbox1; 810 __le16 mailbox2; 811 __le16 mailbox3; 812 __le16 mailbox4; 813 __le16 mailbox5; 814 __le16 mailbox6; 815 __le16 mailbox7; 816 __le16 unused_2[59]; /* Gap */ 817 } __attribute__((packed)) isp2100; 818 struct { 819 /* Request Queue */ 820 __le16 req_q_in; /* In-Pointer */ 821 __le16 req_q_out; /* Out-Pointer */ 822 /* Response Queue */ 823 __le16 rsp_q_in; /* In-Pointer */ 824 __le16 rsp_q_out; /* Out-Pointer */ 825 826 /* RISC to Host Status */ 827 __le32 host_status; 828 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 829 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 830 831 /* Host to Host Semaphore */ 832 __le16 host_semaphore; 833 __le16 unused_3[17]; /* Gap */ 834 __le16 mailbox0; 835 __le16 mailbox1; 836 __le16 mailbox2; 837 __le16 mailbox3; 838 __le16 mailbox4; 839 __le16 mailbox5; 840 __le16 mailbox6; 841 __le16 mailbox7; 842 __le16 mailbox8; 843 __le16 mailbox9; 844 __le16 mailbox10; 845 __le16 mailbox11; 846 __le16 mailbox12; 847 __le16 mailbox13; 848 __le16 mailbox14; 849 __le16 mailbox15; 850 __le16 mailbox16; 851 __le16 mailbox17; 852 __le16 mailbox18; 853 __le16 mailbox19; 854 __le16 mailbox20; 855 __le16 mailbox21; 856 __le16 mailbox22; 857 __le16 mailbox23; 858 __le16 mailbox24; 859 __le16 mailbox25; 860 __le16 mailbox26; 861 __le16 mailbox27; 862 __le16 mailbox28; 863 __le16 mailbox29; 864 __le16 mailbox30; 865 __le16 mailbox31; 866 __le16 fb_cmd; 867 __le16 unused_4[10]; /* Gap */ 868 } __attribute__((packed)) isp2300; 869 } u; 870 871 __le16 fpm_diag_config; 872 __le16 unused_5[0x4]; /* Gap */ 873 __le16 risc_hw; 874 __le16 unused_5_1; /* Gap */ 875 __le16 pcr; /* Processor Control Register. */ 876 __le16 unused_6[0x5]; /* Gap */ 877 __le16 mctr; /* Memory Configuration and Timing. */ 878 __le16 unused_7[0x3]; /* Gap */ 879 __le16 fb_cmd_2100; /* Unused on 23XX */ 880 __le16 unused_8[0x3]; /* Gap */ 881 __le16 hccr; /* Host command & control register. */ 882 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 883 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 884 /* HCCR commands */ 885 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 886 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 887 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 888 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 889 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 890 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 891 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 892 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 893 894 __le16 unused_9[5]; /* Gap */ 895 __le16 gpiod; /* GPIO Data register. */ 896 __le16 gpioe; /* GPIO Enable register. */ 897 #define GPIO_LED_MASK 0x00C0 898 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 899 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 900 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 901 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 902 #define GPIO_LED_ALL_OFF 0x0000 903 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 904 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 905 906 union { 907 struct { 908 __le16 unused_10[8]; /* Gap */ 909 __le16 mailbox8; 910 __le16 mailbox9; 911 __le16 mailbox10; 912 __le16 mailbox11; 913 __le16 mailbox12; 914 __le16 mailbox13; 915 __le16 mailbox14; 916 __le16 mailbox15; 917 __le16 mailbox16; 918 __le16 mailbox17; 919 __le16 mailbox18; 920 __le16 mailbox19; 921 __le16 mailbox20; 922 __le16 mailbox21; 923 __le16 mailbox22; 924 __le16 mailbox23; /* Also probe reg. */ 925 } __attribute__((packed)) isp2200; 926 } u_end; 927 }; 928 929 struct device_reg_25xxmq { 930 __le32 req_q_in; 931 __le32 req_q_out; 932 __le32 rsp_q_in; 933 __le32 rsp_q_out; 934 __le32 atio_q_in; 935 __le32 atio_q_out; 936 }; 937 938 939 struct device_reg_fx00 { 940 __le32 mailbox0; /* 00 */ 941 __le32 mailbox1; /* 04 */ 942 __le32 mailbox2; /* 08 */ 943 __le32 mailbox3; /* 0C */ 944 __le32 mailbox4; /* 10 */ 945 __le32 mailbox5; /* 14 */ 946 __le32 mailbox6; /* 18 */ 947 __le32 mailbox7; /* 1C */ 948 __le32 mailbox8; /* 20 */ 949 __le32 mailbox9; /* 24 */ 950 __le32 mailbox10; /* 28 */ 951 __le32 mailbox11; 952 __le32 mailbox12; 953 __le32 mailbox13; 954 __le32 mailbox14; 955 __le32 mailbox15; 956 __le32 mailbox16; 957 __le32 mailbox17; 958 __le32 mailbox18; 959 __le32 mailbox19; 960 __le32 mailbox20; 961 __le32 mailbox21; 962 __le32 mailbox22; 963 __le32 mailbox23; 964 __le32 mailbox24; 965 __le32 mailbox25; 966 __le32 mailbox26; 967 __le32 mailbox27; 968 __le32 mailbox28; 969 __le32 mailbox29; 970 __le32 mailbox30; 971 __le32 mailbox31; 972 __le32 aenmailbox0; 973 __le32 aenmailbox1; 974 __le32 aenmailbox2; 975 __le32 aenmailbox3; 976 __le32 aenmailbox4; 977 __le32 aenmailbox5; 978 __le32 aenmailbox6; 979 __le32 aenmailbox7; 980 /* Request Queue. */ 981 __le32 req_q_in; /* A0 - Request Queue In-Pointer */ 982 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */ 983 /* Response Queue. */ 984 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */ 985 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */ 986 /* Init values shadowed on FW Up Event */ 987 __le32 initval0; /* B0 */ 988 __le32 initval1; /* B4 */ 989 __le32 initval2; /* B8 */ 990 __le32 initval3; /* BC */ 991 __le32 initval4; /* C0 */ 992 __le32 initval5; /* C4 */ 993 __le32 initval6; /* C8 */ 994 __le32 initval7; /* CC */ 995 __le32 fwheartbeat; /* D0 */ 996 __le32 pseudoaen; /* D4 */ 997 }; 998 999 1000 1001 typedef union { 1002 struct device_reg_2xxx isp; 1003 struct device_reg_24xx isp24; 1004 struct device_reg_25xxmq isp25mq; 1005 struct device_reg_82xx isp82; 1006 struct device_reg_fx00 ispfx00; 1007 } __iomem device_reg_t; 1008 1009 #define ISP_REQ_Q_IN(ha, reg) \ 1010 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1011 &(reg)->u.isp2100.mailbox4 : \ 1012 &(reg)->u.isp2300.req_q_in) 1013 #define ISP_REQ_Q_OUT(ha, reg) \ 1014 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1015 &(reg)->u.isp2100.mailbox4 : \ 1016 &(reg)->u.isp2300.req_q_out) 1017 #define ISP_RSP_Q_IN(ha, reg) \ 1018 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1019 &(reg)->u.isp2100.mailbox5 : \ 1020 &(reg)->u.isp2300.rsp_q_in) 1021 #define ISP_RSP_Q_OUT(ha, reg) \ 1022 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1023 &(reg)->u.isp2100.mailbox5 : \ 1024 &(reg)->u.isp2300.rsp_q_out) 1025 1026 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 1027 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 1028 1029 #define MAILBOX_REG(ha, reg, num) \ 1030 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1031 (num < 8 ? \ 1032 &(reg)->u.isp2100.mailbox0 + (num) : \ 1033 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 1034 &(reg)->u.isp2300.mailbox0 + (num)) 1035 #define RD_MAILBOX_REG(ha, reg, num) \ 1036 rd_reg_word(MAILBOX_REG(ha, reg, num)) 1037 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 1038 wrt_reg_word(MAILBOX_REG(ha, reg, num), data) 1039 1040 #define FB_CMD_REG(ha, reg) \ 1041 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1042 &(reg)->fb_cmd_2100 : \ 1043 &(reg)->u.isp2300.fb_cmd) 1044 #define RD_FB_CMD_REG(ha, reg) \ 1045 rd_reg_word(FB_CMD_REG(ha, reg)) 1046 #define WRT_FB_CMD_REG(ha, reg, data) \ 1047 wrt_reg_word(FB_CMD_REG(ha, reg), data) 1048 1049 typedef struct { 1050 uint32_t out_mb; /* outbound from driver */ 1051 uint32_t in_mb; /* Incoming from RISC */ 1052 uint16_t mb[MAILBOX_REGISTER_COUNT]; 1053 long buf_size; 1054 void *bufp; 1055 uint32_t tov; 1056 uint8_t flags; 1057 #define MBX_DMA_IN BIT_0 1058 #define MBX_DMA_OUT BIT_1 1059 #define IOCTL_CMD BIT_2 1060 } mbx_cmd_t; 1061 1062 struct mbx_cmd_32 { 1063 uint32_t out_mb; /* outbound from driver */ 1064 uint32_t in_mb; /* Incoming from RISC */ 1065 uint32_t mb[MAILBOX_REGISTER_COUNT]; 1066 long buf_size; 1067 void *bufp; 1068 uint32_t tov; 1069 uint8_t flags; 1070 #define MBX_DMA_IN BIT_0 1071 #define MBX_DMA_OUT BIT_1 1072 #define IOCTL_CMD BIT_2 1073 }; 1074 1075 1076 #define MBX_TOV_SECONDS 30 1077 1078 /* 1079 * ISP product identification definitions in mailboxes after reset. 1080 */ 1081 #define PROD_ID_1 0x4953 1082 #define PROD_ID_2 0x0000 1083 #define PROD_ID_2a 0x5020 1084 #define PROD_ID_3 0x2020 1085 1086 /* 1087 * ISP mailbox Self-Test status codes 1088 */ 1089 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 1090 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 1091 #define MBS_BUSY 4 /* Busy. */ 1092 1093 /* 1094 * ISP mailbox command complete status codes 1095 */ 1096 #define MBS_COMMAND_COMPLETE 0x4000 1097 #define MBS_INVALID_COMMAND 0x4001 1098 #define MBS_HOST_INTERFACE_ERROR 0x4002 1099 #define MBS_TEST_FAILED 0x4003 1100 #define MBS_COMMAND_ERROR 0x4005 1101 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 1102 #define MBS_PORT_ID_USED 0x4007 1103 #define MBS_LOOP_ID_USED 0x4008 1104 #define MBS_ALL_IDS_IN_USE 0x4009 1105 #define MBS_NOT_LOGGED_IN 0x400A 1106 #define MBS_LINK_DOWN_ERROR 0x400B 1107 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 1108 1109 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs) 1110 { 1111 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR; 1112 } 1113 1114 /* 1115 * ISP mailbox asynchronous event status codes 1116 */ 1117 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 1118 #define MBA_RESET 0x8001 /* Reset Detected. */ 1119 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 1120 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 1121 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 1122 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 1123 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 1124 /* occurred. */ 1125 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 1126 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 1127 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 1128 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 1129 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 1130 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 1131 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 1132 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 1133 #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */ 1134 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 1135 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 1136 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 1137 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 1138 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 1139 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 1140 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 1141 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 1142 /* used. */ 1143 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 1144 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 1145 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 1146 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 1147 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 1148 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 1149 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 1150 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 1151 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 1152 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 1153 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 1154 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 1155 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 1156 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 1157 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 1158 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 1159 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 1160 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 1161 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 1162 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 1163 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 1164 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 1165 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */ 1166 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 1167 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 1168 Notification */ 1169 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 1170 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 1171 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 1172 /* 83XX FCoE specific */ 1173 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 1174 1175 /* Interrupt type codes */ 1176 #define INTR_ROM_MB_SUCCESS 0x1 1177 #define INTR_ROM_MB_FAILED 0x2 1178 #define INTR_MB_SUCCESS 0x10 1179 #define INTR_MB_FAILED 0x11 1180 #define INTR_ASYNC_EVENT 0x12 1181 #define INTR_RSP_QUE_UPDATE 0x13 1182 #define INTR_RSP_QUE_UPDATE_83XX 0x14 1183 #define INTR_ATIO_QUE_UPDATE 0x1C 1184 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 1185 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 1186 1187 /* ISP mailbox loopback echo diagnostic error code */ 1188 #define MBS_LB_RESET 0x17 1189 1190 /* AEN mailbox Port Diagnostics test */ 1191 #define AEN_START_DIAG_TEST 0x0 /* start the diagnostics */ 1192 #define AEN_DONE_DIAG_TEST_WITH_NOERR 0x1 /* Done with no errors */ 1193 #define AEN_DONE_DIAG_TEST_WITH_ERR 0x2 /* Done with error.*/ 1194 1195 /* 1196 * Firmware options 1, 2, 3. 1197 */ 1198 #define FO1_AE_ON_LIPF8 BIT_0 1199 #define FO1_AE_ALL_LIP_RESET BIT_1 1200 #define FO1_CTIO_RETRY BIT_3 1201 #define FO1_DISABLE_LIP_F7_SW BIT_4 1202 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 1203 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 1204 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 1205 #define FO1_SET_EMPHASIS_SWING BIT_8 1206 #define FO1_AE_AUTO_BYPASS BIT_9 1207 #define FO1_ENABLE_PURE_IOCB BIT_10 1208 #define FO1_AE_PLOGI_RJT BIT_11 1209 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 1210 #define FO1_AE_QUEUE_FULL BIT_13 1211 1212 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 1213 #define FO2_REV_LOOPBACK BIT_1 1214 1215 #define FO3_ENABLE_EMERG_IOCB BIT_0 1216 #define FO3_AE_RND_ERROR BIT_1 1217 1218 /* 24XX additional firmware options */ 1219 #define ADD_FO_COUNT 3 1220 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 1221 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 1222 1223 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 1224 1225 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 1226 1227 /* 1228 * ISP mailbox commands 1229 */ 1230 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1231 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1232 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 1233 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 1234 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1235 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 1236 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 1237 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 1238 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */ 1239 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 1240 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 1241 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 1242 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 1243 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 1244 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 1245 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 1246 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 1247 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1248 #define MBC_RESET 0x18 /* Reset. */ 1249 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1250 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1251 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1252 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1253 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1254 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1255 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1256 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1257 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */ 1258 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1259 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1260 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1261 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1262 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1263 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1264 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1265 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1266 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1267 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1268 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1269 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1270 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1271 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1272 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1273 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1274 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1275 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1276 /* Initialization Procedure */ 1277 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1278 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1279 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1280 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1281 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1282 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1283 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1284 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1285 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1286 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1287 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1288 /* commandd. */ 1289 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1290 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1291 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1292 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1293 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1294 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1295 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1296 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1297 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1298 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1299 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1300 1301 /* 1302 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1303 * should be defined with MBC_MR_* 1304 */ 1305 #define MBC_MR_DRV_SHUTDOWN 0x6A 1306 1307 /* 1308 * ISP24xx mailbox commands 1309 */ 1310 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1311 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1312 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1313 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1314 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1315 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1316 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1317 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1318 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1319 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1320 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1321 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1322 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1323 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1324 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1325 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1326 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1327 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1328 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1329 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1330 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1331 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1332 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1333 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1334 1335 /* 1336 * ISP81xx mailbox commands 1337 */ 1338 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1339 1340 /* 1341 * ISP8044 mailbox commands 1342 */ 1343 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1344 #define HCS_WRITE_SERDES 0x3 1345 #define HCS_READ_SERDES 0x4 1346 1347 /* Firmware return data sizes */ 1348 #define FCAL_MAP_SIZE 128 1349 1350 /* Mailbox bit definitions for out_mb and in_mb */ 1351 #define MBX_31 BIT_31 1352 #define MBX_30 BIT_30 1353 #define MBX_29 BIT_29 1354 #define MBX_28 BIT_28 1355 #define MBX_27 BIT_27 1356 #define MBX_26 BIT_26 1357 #define MBX_25 BIT_25 1358 #define MBX_24 BIT_24 1359 #define MBX_23 BIT_23 1360 #define MBX_22 BIT_22 1361 #define MBX_21 BIT_21 1362 #define MBX_20 BIT_20 1363 #define MBX_19 BIT_19 1364 #define MBX_18 BIT_18 1365 #define MBX_17 BIT_17 1366 #define MBX_16 BIT_16 1367 #define MBX_15 BIT_15 1368 #define MBX_14 BIT_14 1369 #define MBX_13 BIT_13 1370 #define MBX_12 BIT_12 1371 #define MBX_11 BIT_11 1372 #define MBX_10 BIT_10 1373 #define MBX_9 BIT_9 1374 #define MBX_8 BIT_8 1375 #define MBX_7 BIT_7 1376 #define MBX_6 BIT_6 1377 #define MBX_5 BIT_5 1378 #define MBX_4 BIT_4 1379 #define MBX_3 BIT_3 1380 #define MBX_2 BIT_2 1381 #define MBX_1 BIT_1 1382 #define MBX_0 BIT_0 1383 1384 #define RNID_TYPE_ELS_CMD 0x5 1385 #define RNID_TYPE_PORT_LOGIN 0x7 1386 #define RNID_BUFFER_CREDITS 0x8 1387 #define RNID_TYPE_SET_VERSION 0x9 1388 #define RNID_TYPE_ASIC_TEMP 0xC 1389 1390 #define ELS_CMD_MAP_SIZE 32 1391 1392 /* 1393 * Firmware state codes from get firmware state mailbox command 1394 */ 1395 #define FSTATE_CONFIG_WAIT 0 1396 #define FSTATE_WAIT_AL_PA 1 1397 #define FSTATE_WAIT_LOGIN 2 1398 #define FSTATE_READY 3 1399 #define FSTATE_LOSS_OF_SYNC 4 1400 #define FSTATE_ERROR 5 1401 #define FSTATE_REINIT 6 1402 #define FSTATE_NON_PART 7 1403 1404 #define FSTATE_CONFIG_CORRECT 0 1405 #define FSTATE_P2P_RCV_LIP 1 1406 #define FSTATE_P2P_CHOOSE_LOOP 2 1407 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1408 #define FSTATE_FATAL_ERROR 4 1409 #define FSTATE_LOOP_BACK_CONN 5 1410 1411 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1412 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1413 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1414 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1415 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1416 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED 1417 #define QLA27XX_DEFAULT_IMAGE 0 1418 #define QLA27XX_PRIMARY_IMAGE 1 1419 #define QLA27XX_SECONDARY_IMAGE 2 1420 1421 /* 1422 * Port Database structure definition 1423 * Little endian except where noted. 1424 */ 1425 #define PORT_DATABASE_SIZE 128 /* bytes */ 1426 typedef struct { 1427 uint8_t options; 1428 uint8_t control; 1429 uint8_t master_state; 1430 uint8_t slave_state; 1431 uint8_t reserved[2]; 1432 uint8_t hard_address; 1433 uint8_t reserved_1; 1434 uint8_t port_id[4]; 1435 uint8_t node_name[WWN_SIZE]; 1436 uint8_t port_name[WWN_SIZE]; 1437 __le16 execution_throttle; 1438 uint16_t execution_count; 1439 uint8_t reset_count; 1440 uint8_t reserved_2; 1441 uint16_t resource_allocation; 1442 uint16_t current_allocation; 1443 uint16_t queue_head; 1444 uint16_t queue_tail; 1445 uint16_t transmit_execution_list_next; 1446 uint16_t transmit_execution_list_previous; 1447 uint16_t common_features; 1448 uint16_t total_concurrent_sequences; 1449 uint16_t RO_by_information_category; 1450 uint8_t recipient; 1451 uint8_t initiator; 1452 uint16_t receive_data_size; 1453 uint16_t concurrent_sequences; 1454 uint16_t open_sequences_per_exchange; 1455 uint16_t lun_abort_flags; 1456 uint16_t lun_stop_flags; 1457 uint16_t stop_queue_head; 1458 uint16_t stop_queue_tail; 1459 uint16_t port_retry_timer; 1460 uint16_t next_sequence_id; 1461 uint16_t frame_count; 1462 uint16_t PRLI_payload_length; 1463 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1464 /* Bits 15-0 of word 0 */ 1465 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1466 /* Bits 15-0 of word 3 */ 1467 uint16_t loop_id; 1468 uint16_t extended_lun_info_list_pointer; 1469 uint16_t extended_lun_stop_list_pointer; 1470 } port_database_t; 1471 1472 /* 1473 * Port database slave/master states 1474 */ 1475 #define PD_STATE_DISCOVERY 0 1476 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1477 #define PD_STATE_PORT_LOGIN 2 1478 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1479 #define PD_STATE_PROCESS_LOGIN 4 1480 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1481 #define PD_STATE_PORT_LOGGED_IN 6 1482 #define PD_STATE_PORT_UNAVAILABLE 7 1483 #define PD_STATE_PROCESS_LOGOUT 8 1484 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1485 #define PD_STATE_PORT_LOGOUT 10 1486 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1487 1488 1489 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1490 #define QLA_ZIO_DISABLED 0 1491 #define QLA_ZIO_DEFAULT_TIMER 2 1492 1493 /* 1494 * ISP Initialization Control Block. 1495 * Little endian except where noted. 1496 */ 1497 #define ICB_VERSION 1 1498 typedef struct { 1499 uint8_t version; 1500 uint8_t reserved_1; 1501 1502 /* 1503 * LSB BIT 0 = Enable Hard Loop Id 1504 * LSB BIT 1 = Enable Fairness 1505 * LSB BIT 2 = Enable Full-Duplex 1506 * LSB BIT 3 = Enable Fast Posting 1507 * LSB BIT 4 = Enable Target Mode 1508 * LSB BIT 5 = Disable Initiator Mode 1509 * LSB BIT 6 = Enable ADISC 1510 * LSB BIT 7 = Enable Target Inquiry Data 1511 * 1512 * MSB BIT 0 = Enable PDBC Notify 1513 * MSB BIT 1 = Non Participating LIP 1514 * MSB BIT 2 = Descending Loop ID Search 1515 * MSB BIT 3 = Acquire Loop ID in LIPA 1516 * MSB BIT 4 = Stop PortQ on Full Status 1517 * MSB BIT 5 = Full Login after LIP 1518 * MSB BIT 6 = Node Name Option 1519 * MSB BIT 7 = Ext IFWCB enable bit 1520 */ 1521 uint8_t firmware_options[2]; 1522 1523 __le16 frame_payload_size; 1524 __le16 max_iocb_allocation; 1525 __le16 execution_throttle; 1526 uint8_t retry_count; 1527 uint8_t retry_delay; /* unused */ 1528 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1529 uint16_t hard_address; 1530 uint8_t inquiry_data; 1531 uint8_t login_timeout; 1532 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1533 1534 __le16 request_q_outpointer; 1535 __le16 response_q_inpointer; 1536 __le16 request_q_length; 1537 __le16 response_q_length; 1538 __le64 request_q_address __packed; 1539 __le64 response_q_address __packed; 1540 1541 __le16 lun_enables; 1542 uint8_t command_resource_count; 1543 uint8_t immediate_notify_resource_count; 1544 __le16 timeout; 1545 uint8_t reserved_2[2]; 1546 1547 /* 1548 * LSB BIT 0 = Timer Operation mode bit 0 1549 * LSB BIT 1 = Timer Operation mode bit 1 1550 * LSB BIT 2 = Timer Operation mode bit 2 1551 * LSB BIT 3 = Timer Operation mode bit 3 1552 * LSB BIT 4 = Init Config Mode bit 0 1553 * LSB BIT 5 = Init Config Mode bit 1 1554 * LSB BIT 6 = Init Config Mode bit 2 1555 * LSB BIT 7 = Enable Non part on LIHA failure 1556 * 1557 * MSB BIT 0 = Enable class 2 1558 * MSB BIT 1 = Enable ACK0 1559 * MSB BIT 2 = 1560 * MSB BIT 3 = 1561 * MSB BIT 4 = FC Tape Enable 1562 * MSB BIT 5 = Enable FC Confirm 1563 * MSB BIT 6 = Enable command queuing in target mode 1564 * MSB BIT 7 = No Logo On Link Down 1565 */ 1566 uint8_t add_firmware_options[2]; 1567 1568 uint8_t response_accumulation_timer; 1569 uint8_t interrupt_delay_timer; 1570 1571 /* 1572 * LSB BIT 0 = Enable Read xfr_rdy 1573 * LSB BIT 1 = Soft ID only 1574 * LSB BIT 2 = 1575 * LSB BIT 3 = 1576 * LSB BIT 4 = FCP RSP Payload [0] 1577 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1578 * LSB BIT 6 = Enable Out-of-Order frame handling 1579 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1580 * 1581 * MSB BIT 0 = Sbus enable - 2300 1582 * MSB BIT 1 = 1583 * MSB BIT 2 = 1584 * MSB BIT 3 = 1585 * MSB BIT 4 = LED mode 1586 * MSB BIT 5 = enable 50 ohm termination 1587 * MSB BIT 6 = Data Rate (2300 only) 1588 * MSB BIT 7 = Data Rate (2300 only) 1589 */ 1590 uint8_t special_options[2]; 1591 1592 uint8_t reserved_3[26]; 1593 } init_cb_t; 1594 1595 /* Special Features Control Block */ 1596 struct init_sf_cb { 1597 uint8_t format; 1598 uint8_t reserved0; 1599 /* 1600 * BIT 15-14 = Reserved 1601 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled) 1602 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled) 1603 * BIT 11-0 = Reserved 1604 */ 1605 __le16 flags; 1606 uint8_t reserved1[32]; 1607 uint16_t discard_OHRB_timeout_value; 1608 uint16_t remote_write_opt_queue_num; 1609 uint8_t reserved2[40]; 1610 uint8_t scm_related_parameter[16]; 1611 uint8_t reserved3[32]; 1612 }; 1613 1614 /* 1615 * Get Link Status mailbox command return buffer. 1616 */ 1617 #define GLSO_SEND_RPS BIT_0 1618 #define GLSO_USE_DID BIT_3 1619 1620 struct link_statistics { 1621 __le32 link_fail_cnt; 1622 __le32 loss_sync_cnt; 1623 __le32 loss_sig_cnt; 1624 __le32 prim_seq_err_cnt; 1625 __le32 inval_xmit_word_cnt; 1626 __le32 inval_crc_cnt; 1627 __le32 lip_cnt; 1628 __le32 link_up_cnt; 1629 __le32 link_down_loop_init_tmo; 1630 __le32 link_down_los; 1631 __le32 link_down_loss_rcv_clk; 1632 uint32_t reserved0[5]; 1633 __le32 port_cfg_chg; 1634 uint32_t reserved1[11]; 1635 __le32 rsp_q_full; 1636 __le32 atio_q_full; 1637 __le32 drop_ae; 1638 __le32 els_proto_err; 1639 __le32 reserved2; 1640 __le32 tx_frames; 1641 __le32 rx_frames; 1642 __le32 discarded_frames; 1643 __le32 dropped_frames; 1644 uint32_t reserved3; 1645 __le32 nos_rcvd; 1646 uint32_t reserved4[4]; 1647 __le32 tx_prjt; 1648 __le32 rcv_exfail; 1649 __le32 rcv_abts; 1650 __le32 seq_frm_miss; 1651 __le32 corr_err; 1652 __le32 mb_rqst; 1653 __le32 nport_full; 1654 __le32 eofa; 1655 uint32_t reserved5; 1656 __le64 fpm_recv_word_cnt; 1657 __le64 fpm_disc_word_cnt; 1658 __le64 fpm_xmit_word_cnt; 1659 uint32_t reserved6[70]; 1660 }; 1661 1662 /* 1663 * NVRAM Command values. 1664 */ 1665 #define NV_START_BIT BIT_2 1666 #define NV_WRITE_OP (BIT_26+BIT_24) 1667 #define NV_READ_OP (BIT_26+BIT_25) 1668 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1669 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1670 #define NV_DELAY_COUNT 10 1671 1672 /* 1673 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1674 */ 1675 typedef struct { 1676 /* 1677 * NVRAM header 1678 */ 1679 uint8_t id[4]; 1680 uint8_t nvram_version; 1681 uint8_t reserved_0; 1682 1683 /* 1684 * NVRAM RISC parameter block 1685 */ 1686 uint8_t parameter_block_version; 1687 uint8_t reserved_1; 1688 1689 /* 1690 * LSB BIT 0 = Enable Hard Loop Id 1691 * LSB BIT 1 = Enable Fairness 1692 * LSB BIT 2 = Enable Full-Duplex 1693 * LSB BIT 3 = Enable Fast Posting 1694 * LSB BIT 4 = Enable Target Mode 1695 * LSB BIT 5 = Disable Initiator Mode 1696 * LSB BIT 6 = Enable ADISC 1697 * LSB BIT 7 = Enable Target Inquiry Data 1698 * 1699 * MSB BIT 0 = Enable PDBC Notify 1700 * MSB BIT 1 = Non Participating LIP 1701 * MSB BIT 2 = Descending Loop ID Search 1702 * MSB BIT 3 = Acquire Loop ID in LIPA 1703 * MSB BIT 4 = Stop PortQ on Full Status 1704 * MSB BIT 5 = Full Login after LIP 1705 * MSB BIT 6 = Node Name Option 1706 * MSB BIT 7 = Ext IFWCB enable bit 1707 */ 1708 uint8_t firmware_options[2]; 1709 1710 __le16 frame_payload_size; 1711 __le16 max_iocb_allocation; 1712 __le16 execution_throttle; 1713 uint8_t retry_count; 1714 uint8_t retry_delay; /* unused */ 1715 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1716 uint16_t hard_address; 1717 uint8_t inquiry_data; 1718 uint8_t login_timeout; 1719 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1720 1721 /* 1722 * LSB BIT 0 = Timer Operation mode bit 0 1723 * LSB BIT 1 = Timer Operation mode bit 1 1724 * LSB BIT 2 = Timer Operation mode bit 2 1725 * LSB BIT 3 = Timer Operation mode bit 3 1726 * LSB BIT 4 = Init Config Mode bit 0 1727 * LSB BIT 5 = Init Config Mode bit 1 1728 * LSB BIT 6 = Init Config Mode bit 2 1729 * LSB BIT 7 = Enable Non part on LIHA failure 1730 * 1731 * MSB BIT 0 = Enable class 2 1732 * MSB BIT 1 = Enable ACK0 1733 * MSB BIT 2 = 1734 * MSB BIT 3 = 1735 * MSB BIT 4 = FC Tape Enable 1736 * MSB BIT 5 = Enable FC Confirm 1737 * MSB BIT 6 = Enable command queuing in target mode 1738 * MSB BIT 7 = No Logo On Link Down 1739 */ 1740 uint8_t add_firmware_options[2]; 1741 1742 uint8_t response_accumulation_timer; 1743 uint8_t interrupt_delay_timer; 1744 1745 /* 1746 * LSB BIT 0 = Enable Read xfr_rdy 1747 * LSB BIT 1 = Soft ID only 1748 * LSB BIT 2 = 1749 * LSB BIT 3 = 1750 * LSB BIT 4 = FCP RSP Payload [0] 1751 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1752 * LSB BIT 6 = Enable Out-of-Order frame handling 1753 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1754 * 1755 * MSB BIT 0 = Sbus enable - 2300 1756 * MSB BIT 1 = 1757 * MSB BIT 2 = 1758 * MSB BIT 3 = 1759 * MSB BIT 4 = LED mode 1760 * MSB BIT 5 = enable 50 ohm termination 1761 * MSB BIT 6 = Data Rate (2300 only) 1762 * MSB BIT 7 = Data Rate (2300 only) 1763 */ 1764 uint8_t special_options[2]; 1765 1766 /* Reserved for expanded RISC parameter block */ 1767 uint8_t reserved_2[22]; 1768 1769 /* 1770 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1771 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1772 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1773 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1774 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1775 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1776 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1777 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1778 * 1779 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1780 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1781 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1782 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1783 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1784 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1785 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1786 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1787 * 1788 * LSB BIT 0 = Output Swing 1G bit 0 1789 * LSB BIT 1 = Output Swing 1G bit 1 1790 * LSB BIT 2 = Output Swing 1G bit 2 1791 * LSB BIT 3 = Output Emphasis 1G bit 0 1792 * LSB BIT 4 = Output Emphasis 1G bit 1 1793 * LSB BIT 5 = Output Swing 2G bit 0 1794 * LSB BIT 6 = Output Swing 2G bit 1 1795 * LSB BIT 7 = Output Swing 2G bit 2 1796 * 1797 * MSB BIT 0 = Output Emphasis 2G bit 0 1798 * MSB BIT 1 = Output Emphasis 2G bit 1 1799 * MSB BIT 2 = Output Enable 1800 * MSB BIT 3 = 1801 * MSB BIT 4 = 1802 * MSB BIT 5 = 1803 * MSB BIT 6 = 1804 * MSB BIT 7 = 1805 */ 1806 uint8_t seriallink_options[4]; 1807 1808 /* 1809 * NVRAM host parameter block 1810 * 1811 * LSB BIT 0 = Enable spinup delay 1812 * LSB BIT 1 = Disable BIOS 1813 * LSB BIT 2 = Enable Memory Map BIOS 1814 * LSB BIT 3 = Enable Selectable Boot 1815 * LSB BIT 4 = Disable RISC code load 1816 * LSB BIT 5 = Set cache line size 1 1817 * LSB BIT 6 = PCI Parity Disable 1818 * LSB BIT 7 = Enable extended logging 1819 * 1820 * MSB BIT 0 = Enable 64bit addressing 1821 * MSB BIT 1 = Enable lip reset 1822 * MSB BIT 2 = Enable lip full login 1823 * MSB BIT 3 = Enable target reset 1824 * MSB BIT 4 = Enable database storage 1825 * MSB BIT 5 = Enable cache flush read 1826 * MSB BIT 6 = Enable database load 1827 * MSB BIT 7 = Enable alternate WWN 1828 */ 1829 uint8_t host_p[2]; 1830 1831 uint8_t boot_node_name[WWN_SIZE]; 1832 uint8_t boot_lun_number; 1833 uint8_t reset_delay; 1834 uint8_t port_down_retry_count; 1835 uint8_t boot_id_number; 1836 __le16 max_luns_per_target; 1837 uint8_t fcode_boot_port_name[WWN_SIZE]; 1838 uint8_t alternate_port_name[WWN_SIZE]; 1839 uint8_t alternate_node_name[WWN_SIZE]; 1840 1841 /* 1842 * BIT 0 = Selective Login 1843 * BIT 1 = Alt-Boot Enable 1844 * BIT 2 = 1845 * BIT 3 = Boot Order List 1846 * BIT 4 = 1847 * BIT 5 = Selective LUN 1848 * BIT 6 = 1849 * BIT 7 = unused 1850 */ 1851 uint8_t efi_parameters; 1852 1853 uint8_t link_down_timeout; 1854 1855 uint8_t adapter_id[16]; 1856 1857 uint8_t alt1_boot_node_name[WWN_SIZE]; 1858 uint16_t alt1_boot_lun_number; 1859 uint8_t alt2_boot_node_name[WWN_SIZE]; 1860 uint16_t alt2_boot_lun_number; 1861 uint8_t alt3_boot_node_name[WWN_SIZE]; 1862 uint16_t alt3_boot_lun_number; 1863 uint8_t alt4_boot_node_name[WWN_SIZE]; 1864 uint16_t alt4_boot_lun_number; 1865 uint8_t alt5_boot_node_name[WWN_SIZE]; 1866 uint16_t alt5_boot_lun_number; 1867 uint8_t alt6_boot_node_name[WWN_SIZE]; 1868 uint16_t alt6_boot_lun_number; 1869 uint8_t alt7_boot_node_name[WWN_SIZE]; 1870 uint16_t alt7_boot_lun_number; 1871 1872 uint8_t reserved_3[2]; 1873 1874 /* Offset 200-215 : Model Number */ 1875 uint8_t model_number[16]; 1876 1877 /* OEM related items */ 1878 uint8_t oem_specific[16]; 1879 1880 /* 1881 * NVRAM Adapter Features offset 232-239 1882 * 1883 * LSB BIT 0 = External GBIC 1884 * LSB BIT 1 = Risc RAM parity 1885 * LSB BIT 2 = Buffer Plus Module 1886 * LSB BIT 3 = Multi Chip Adapter 1887 * LSB BIT 4 = Internal connector 1888 * LSB BIT 5 = 1889 * LSB BIT 6 = 1890 * LSB BIT 7 = 1891 * 1892 * MSB BIT 0 = 1893 * MSB BIT 1 = 1894 * MSB BIT 2 = 1895 * MSB BIT 3 = 1896 * MSB BIT 4 = 1897 * MSB BIT 5 = 1898 * MSB BIT 6 = 1899 * MSB BIT 7 = 1900 */ 1901 uint8_t adapter_features[2]; 1902 1903 uint8_t reserved_4[16]; 1904 1905 /* Subsystem vendor ID for ISP2200 */ 1906 uint16_t subsystem_vendor_id_2200; 1907 1908 /* Subsystem device ID for ISP2200 */ 1909 uint16_t subsystem_device_id_2200; 1910 1911 uint8_t reserved_5; 1912 uint8_t checksum; 1913 } nvram_t; 1914 1915 /* 1916 * ISP queue - response queue entry definition. 1917 */ 1918 typedef struct { 1919 uint8_t entry_type; /* Entry type. */ 1920 uint8_t entry_count; /* Entry count. */ 1921 uint8_t sys_define; /* System defined. */ 1922 uint8_t entry_status; /* Entry Status. */ 1923 uint32_t handle; /* System defined handle */ 1924 uint8_t data[52]; 1925 uint32_t signature; 1926 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1927 } response_t; 1928 1929 /* 1930 * ISP queue - ATIO queue entry definition. 1931 */ 1932 struct atio { 1933 uint8_t entry_type; /* Entry type. */ 1934 uint8_t entry_count; /* Entry count. */ 1935 __le16 attr_n_length; 1936 uint8_t data[56]; 1937 uint32_t signature; 1938 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1939 }; 1940 1941 typedef union { 1942 __le16 extended; 1943 struct { 1944 uint8_t reserved; 1945 uint8_t standard; 1946 } id; 1947 } target_id_t; 1948 1949 #define SET_TARGET_ID(ha, to, from) \ 1950 do { \ 1951 if (HAS_EXTENDED_IDS(ha)) \ 1952 to.extended = cpu_to_le16(from); \ 1953 else \ 1954 to.id.standard = (uint8_t)from; \ 1955 } while (0) 1956 1957 /* 1958 * ISP queue - command entry structure definition. 1959 */ 1960 #define COMMAND_TYPE 0x11 /* Command entry */ 1961 typedef struct { 1962 uint8_t entry_type; /* Entry type. */ 1963 uint8_t entry_count; /* Entry count. */ 1964 uint8_t sys_define; /* System defined. */ 1965 uint8_t entry_status; /* Entry Status. */ 1966 uint32_t handle; /* System handle. */ 1967 target_id_t target; /* SCSI ID */ 1968 __le16 lun; /* SCSI LUN */ 1969 __le16 control_flags; /* Control flags. */ 1970 #define CF_WRITE BIT_6 1971 #define CF_READ BIT_5 1972 #define CF_SIMPLE_TAG BIT_3 1973 #define CF_ORDERED_TAG BIT_2 1974 #define CF_HEAD_TAG BIT_1 1975 uint16_t reserved_1; 1976 __le16 timeout; /* Command timeout. */ 1977 __le16 dseg_count; /* Data segment count. */ 1978 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1979 __le32 byte_count; /* Total byte count. */ 1980 union { 1981 struct dsd32 dsd32[3]; 1982 struct dsd64 dsd64[2]; 1983 }; 1984 } cmd_entry_t; 1985 1986 /* 1987 * ISP queue - 64-Bit addressing, command entry structure definition. 1988 */ 1989 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1990 typedef struct { 1991 uint8_t entry_type; /* Entry type. */ 1992 uint8_t entry_count; /* Entry count. */ 1993 uint8_t sys_define; /* System defined. */ 1994 uint8_t entry_status; /* Entry Status. */ 1995 uint32_t handle; /* System handle. */ 1996 target_id_t target; /* SCSI ID */ 1997 __le16 lun; /* SCSI LUN */ 1998 __le16 control_flags; /* Control flags. */ 1999 uint16_t reserved_1; 2000 __le16 timeout; /* Command timeout. */ 2001 __le16 dseg_count; /* Data segment count. */ 2002 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 2003 uint32_t byte_count; /* Total byte count. */ 2004 struct dsd64 dsd[2]; 2005 } cmd_a64_entry_t, request_t; 2006 2007 /* 2008 * ISP queue - continuation entry structure definition. 2009 */ 2010 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 2011 typedef struct { 2012 uint8_t entry_type; /* Entry type. */ 2013 uint8_t entry_count; /* Entry count. */ 2014 uint8_t sys_define; /* System defined. */ 2015 uint8_t entry_status; /* Entry Status. */ 2016 uint32_t reserved; 2017 struct dsd32 dsd[7]; 2018 } cont_entry_t; 2019 2020 /* 2021 * ISP queue - 64-Bit addressing, continuation entry structure definition. 2022 */ 2023 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 2024 typedef struct { 2025 uint8_t entry_type; /* Entry type. */ 2026 uint8_t entry_count; /* Entry count. */ 2027 uint8_t sys_define; /* System defined. */ 2028 uint8_t entry_status; /* Entry Status. */ 2029 struct dsd64 dsd[5]; 2030 } cont_a64_entry_t; 2031 2032 #define PO_MODE_DIF_INSERT 0 2033 #define PO_MODE_DIF_REMOVE 1 2034 #define PO_MODE_DIF_PASS 2 2035 #define PO_MODE_DIF_REPLACE 3 2036 #define PO_MODE_DIF_TCP_CKSUM 6 2037 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 2038 #define PO_DISABLE_GUARD_CHECK BIT_4 2039 #define PO_DISABLE_INCR_REF_TAG BIT_5 2040 #define PO_DIS_HEADER_MODE BIT_7 2041 #define PO_ENABLE_DIF_BUNDLING BIT_8 2042 #define PO_DIS_FRAME_MODE BIT_9 2043 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 2044 #define PO_DIS_VALD_APP_REF_ESC BIT_11 2045 2046 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 2047 #define PO_DIS_REF_TAG_REPL BIT_13 2048 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 2049 #define PO_DIS_REF_TAG_VALD BIT_15 2050 2051 /* 2052 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 2053 */ 2054 struct crc_context { 2055 uint32_t handle; /* System handle. */ 2056 __le32 ref_tag; 2057 __le16 app_tag; 2058 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 2059 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 2060 __le16 guard_seed; /* Initial Guard Seed */ 2061 __le16 prot_opts; /* Requested Data Protection Mode */ 2062 __le16 blk_size; /* Data size in bytes */ 2063 __le16 runt_blk_guard; /* Guard value for runt block (tape 2064 * only) */ 2065 __le32 byte_count; /* Total byte count/ total data 2066 * transfer count */ 2067 union { 2068 struct { 2069 uint32_t reserved_1; 2070 uint16_t reserved_2; 2071 uint16_t reserved_3; 2072 uint32_t reserved_4; 2073 struct dsd64 data_dsd[1]; 2074 uint32_t reserved_5[2]; 2075 uint32_t reserved_6; 2076 } nobundling; 2077 struct { 2078 __le32 dif_byte_count; /* Total DIF byte 2079 * count */ 2080 uint16_t reserved_1; 2081 __le16 dseg_count; /* Data segment count */ 2082 uint32_t reserved_2; 2083 struct dsd64 data_dsd[1]; 2084 struct dsd64 dif_dsd; 2085 } bundling; 2086 } u; 2087 2088 struct fcp_cmnd fcp_cmnd; 2089 dma_addr_t crc_ctx_dma; 2090 /* List of DMA context transfers */ 2091 struct list_head dsd_list; 2092 2093 /* List of DIF Bundling context DMA address */ 2094 struct list_head ldif_dsd_list; 2095 u8 no_ldif_dsd; 2096 2097 struct list_head ldif_dma_hndl_list; 2098 u32 dif_bundl_len; 2099 u8 no_dif_bundl; 2100 /* This structure should not exceed 512 bytes */ 2101 }; 2102 2103 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 2104 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 2105 2106 /* 2107 * ISP queue - status entry structure definition. 2108 */ 2109 #define STATUS_TYPE 0x03 /* Status entry. */ 2110 typedef struct { 2111 uint8_t entry_type; /* Entry type. */ 2112 uint8_t entry_count; /* Entry count. */ 2113 uint8_t sys_define; /* System defined. */ 2114 uint8_t entry_status; /* Entry Status. */ 2115 uint32_t handle; /* System handle. */ 2116 __le16 scsi_status; /* SCSI status. */ 2117 __le16 comp_status; /* Completion status. */ 2118 __le16 state_flags; /* State flags. */ 2119 __le16 status_flags; /* Status flags. */ 2120 __le16 rsp_info_len; /* Response Info Length. */ 2121 __le16 req_sense_length; /* Request sense data length. */ 2122 __le32 residual_length; /* Residual transfer length. */ 2123 uint8_t rsp_info[8]; /* FCP response information. */ 2124 uint8_t req_sense_data[32]; /* Request sense data. */ 2125 } sts_entry_t; 2126 2127 /* 2128 * Status entry entry status 2129 */ 2130 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 2131 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 2132 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 2133 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 2134 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 2135 #define RF_BUSY BIT_1 /* Busy */ 2136 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 2137 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 2138 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 2139 RF_INV_E_TYPE) 2140 2141 /* 2142 * Status entry SCSI status bit definitions. 2143 */ 2144 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 2145 #define SS_RESIDUAL_UNDER BIT_11 2146 #define SS_RESIDUAL_OVER BIT_10 2147 #define SS_SENSE_LEN_VALID BIT_9 2148 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 2149 #define SS_SCSI_STATUS_BYTE 0xff 2150 2151 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 2152 #define SS_BUSY_CONDITION BIT_3 2153 #define SS_CONDITION_MET BIT_2 2154 #define SS_CHECK_CONDITION BIT_1 2155 2156 /* 2157 * Status entry completion status 2158 */ 2159 #define CS_COMPLETE 0x0 /* No errors */ 2160 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 2161 #define CS_DMA 0x2 /* A DMA direction error. */ 2162 #define CS_TRANSPORT 0x3 /* Transport error. */ 2163 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 2164 #define CS_ABORTED 0x5 /* System aborted command. */ 2165 #define CS_TIMEOUT 0x6 /* Timeout error. */ 2166 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 2167 #define CS_DIF_ERROR 0xC /* DIF error detected */ 2168 2169 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 2170 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 2171 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 2172 /* (selection timeout) */ 2173 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 2174 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 2175 #define CS_PORT_BUSY 0x2B /* Port Busy */ 2176 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 2177 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 2178 failure */ 2179 #define CS_REJECT_RECEIVED 0x4E /* Reject received */ 2180 #define CS_EDIF_AUTH_ERROR 0x63 /* decrypt error */ 2181 #define CS_EDIF_PAD_LEN_ERROR 0x65 /* pad > frame size, not 4byte align */ 2182 #define CS_EDIF_INV_REQ 0x66 /* invalid request */ 2183 #define CS_EDIF_SPI_ERROR 0x67 /* rx frame unable to locate sa */ 2184 #define CS_EDIF_HDR_ERROR 0x69 /* data frame != expected len */ 2185 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 2186 #define CS_UNKNOWN 0x81 /* Driver defined */ 2187 #define CS_RETRY 0x82 /* Driver defined */ 2188 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 2189 2190 #define CS_BIDIR_RD_OVERRUN 0x700 2191 #define CS_BIDIR_RD_WR_OVERRUN 0x707 2192 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 2193 #define CS_BIDIR_RD_UNDERRUN 0x1500 2194 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 2195 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 2196 #define CS_BIDIR_DMA 0x200 2197 /* 2198 * Status entry status flags 2199 */ 2200 #define SF_ABTS_TERMINATED BIT_10 2201 #define SF_LOGOUT_SENT BIT_13 2202 2203 /* 2204 * ISP queue - status continuation entry structure definition. 2205 */ 2206 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 2207 typedef struct { 2208 uint8_t entry_type; /* Entry type. */ 2209 uint8_t entry_count; /* Entry count. */ 2210 uint8_t sys_define; /* System defined. */ 2211 uint8_t entry_status; /* Entry Status. */ 2212 uint8_t data[60]; /* data */ 2213 } sts_cont_entry_t; 2214 2215 /* 2216 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 2217 * structure definition. 2218 */ 2219 #define STATUS_TYPE_21 0x21 /* Status entry. */ 2220 typedef struct { 2221 uint8_t entry_type; /* Entry type. */ 2222 uint8_t entry_count; /* Entry count. */ 2223 uint8_t handle_count; /* Handle count. */ 2224 uint8_t entry_status; /* Entry Status. */ 2225 uint32_t handle[15]; /* System handles. */ 2226 } sts21_entry_t; 2227 2228 /* 2229 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 2230 * structure definition. 2231 */ 2232 #define STATUS_TYPE_22 0x22 /* Status entry. */ 2233 typedef struct { 2234 uint8_t entry_type; /* Entry type. */ 2235 uint8_t entry_count; /* Entry count. */ 2236 uint8_t handle_count; /* Handle count. */ 2237 uint8_t entry_status; /* Entry Status. */ 2238 uint16_t handle[30]; /* System handles. */ 2239 } sts22_entry_t; 2240 2241 /* 2242 * ISP queue - marker entry structure definition. 2243 */ 2244 #define MARKER_TYPE 0x04 /* Marker entry. */ 2245 typedef struct { 2246 uint8_t entry_type; /* Entry type. */ 2247 uint8_t entry_count; /* Entry count. */ 2248 uint8_t handle_count; /* Handle count. */ 2249 uint8_t entry_status; /* Entry Status. */ 2250 uint32_t sys_define_2; /* System defined. */ 2251 target_id_t target; /* SCSI ID */ 2252 uint8_t modifier; /* Modifier (7-0). */ 2253 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 2254 #define MK_SYNC_ID 1 /* Synchronize ID */ 2255 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2256 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2257 /* clear port changed, */ 2258 /* use sequence number. */ 2259 uint8_t reserved_1; 2260 __le16 sequence_number; /* Sequence number of event */ 2261 __le16 lun; /* SCSI LUN */ 2262 uint8_t reserved_2[48]; 2263 } mrk_entry_t; 2264 2265 /* 2266 * ISP queue - Management Server entry structure definition. 2267 */ 2268 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2269 typedef struct { 2270 uint8_t entry_type; /* Entry type. */ 2271 uint8_t entry_count; /* Entry count. */ 2272 uint8_t handle_count; /* Handle count. */ 2273 uint8_t entry_status; /* Entry Status. */ 2274 uint32_t handle1; /* System handle. */ 2275 target_id_t loop_id; 2276 __le16 status; 2277 __le16 control_flags; /* Control flags. */ 2278 uint16_t reserved2; 2279 __le16 timeout; 2280 __le16 cmd_dsd_count; 2281 __le16 total_dsd_count; 2282 uint8_t type; 2283 uint8_t r_ctl; 2284 __le16 rx_id; 2285 uint16_t reserved3; 2286 uint32_t handle2; 2287 __le32 rsp_bytecount; 2288 __le32 req_bytecount; 2289 struct dsd64 req_dsd; 2290 struct dsd64 rsp_dsd; 2291 } ms_iocb_entry_t; 2292 2293 #define SCM_EDC_ACC_RECEIVED BIT_6 2294 #define SCM_RDF_ACC_RECEIVED BIT_7 2295 2296 /* 2297 * ISP queue - Mailbox Command entry structure definition. 2298 */ 2299 #define MBX_IOCB_TYPE 0x39 2300 struct mbx_entry { 2301 uint8_t entry_type; 2302 uint8_t entry_count; 2303 uint8_t sys_define1; 2304 /* Use sys_define1 for source type */ 2305 #define SOURCE_SCSI 0x00 2306 #define SOURCE_IP 0x01 2307 #define SOURCE_VI 0x02 2308 #define SOURCE_SCTP 0x03 2309 #define SOURCE_MP 0x04 2310 #define SOURCE_MPIOCTL 0x05 2311 #define SOURCE_ASYNC_IOCB 0x07 2312 2313 uint8_t entry_status; 2314 2315 uint32_t handle; 2316 target_id_t loop_id; 2317 2318 __le16 status; 2319 __le16 state_flags; 2320 __le16 status_flags; 2321 2322 uint32_t sys_define2[2]; 2323 2324 __le16 mb0; 2325 __le16 mb1; 2326 __le16 mb2; 2327 __le16 mb3; 2328 __le16 mb6; 2329 __le16 mb7; 2330 __le16 mb9; 2331 __le16 mb10; 2332 uint32_t reserved_2[2]; 2333 uint8_t node_name[WWN_SIZE]; 2334 uint8_t port_name[WWN_SIZE]; 2335 }; 2336 2337 #ifndef IMMED_NOTIFY_TYPE 2338 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2339 /* 2340 * ISP queue - immediate notify entry structure definition. 2341 * This is sent by the ISP to the Target driver. 2342 * This IOCB would have report of events sent by the 2343 * initiator, that needs to be handled by the target 2344 * driver immediately. 2345 */ 2346 struct imm_ntfy_from_isp { 2347 uint8_t entry_type; /* Entry type. */ 2348 uint8_t entry_count; /* Entry count. */ 2349 uint8_t sys_define; /* System defined. */ 2350 uint8_t entry_status; /* Entry Status. */ 2351 union { 2352 struct { 2353 __le32 sys_define_2; /* System defined. */ 2354 target_id_t target; 2355 __le16 lun; 2356 uint8_t target_id; 2357 uint8_t reserved_1; 2358 __le16 status_modifier; 2359 __le16 status; 2360 __le16 task_flags; 2361 __le16 seq_id; 2362 __le16 srr_rx_id; 2363 __le32 srr_rel_offs; 2364 __le16 srr_ui; 2365 #define SRR_IU_DATA_IN 0x1 2366 #define SRR_IU_DATA_OUT 0x5 2367 #define SRR_IU_STATUS 0x7 2368 __le16 srr_ox_id; 2369 uint8_t reserved_2[28]; 2370 } isp2x; 2371 struct { 2372 uint32_t reserved; 2373 __le16 nport_handle; 2374 uint16_t reserved_2; 2375 __le16 flags; 2376 #define NOTIFY24XX_FLAGS_FCSP BIT_5 2377 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2378 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2379 __le16 srr_rx_id; 2380 __le16 status; 2381 uint8_t status_subcode; 2382 uint8_t fw_handle; 2383 __le32 exchange_address; 2384 __le32 srr_rel_offs; 2385 __le16 srr_ui; 2386 __le16 srr_ox_id; 2387 union { 2388 struct { 2389 uint8_t node_name[8]; 2390 } plogi; /* PLOGI/ADISC/PDISC */ 2391 struct { 2392 /* PRLI word 3 bit 0-15 */ 2393 __le16 wd3_lo; 2394 uint8_t resv0[6]; 2395 } prli; 2396 struct { 2397 uint8_t port_id[3]; 2398 uint8_t resv1; 2399 __le16 nport_handle; 2400 uint16_t resv2; 2401 } req_els; 2402 } u; 2403 uint8_t port_name[8]; 2404 uint8_t resv3[3]; 2405 uint8_t vp_index; 2406 uint32_t reserved_5; 2407 uint8_t port_id[3]; 2408 uint8_t reserved_6; 2409 } isp24; 2410 } u; 2411 uint16_t reserved_7; 2412 __le16 ox_id; 2413 } __packed; 2414 #endif 2415 2416 /* 2417 * ISP request and response queue entry sizes 2418 */ 2419 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2420 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2421 2422 2423 2424 /* 2425 * Switch info gathering structure. 2426 */ 2427 typedef struct { 2428 port_id_t d_id; 2429 uint8_t node_name[WWN_SIZE]; 2430 uint8_t port_name[WWN_SIZE]; 2431 uint8_t fabric_port_name[WWN_SIZE]; 2432 uint16_t fp_speed; 2433 uint8_t fc4_type; 2434 uint8_t fc4_features; 2435 } sw_info_t; 2436 2437 /* FCP-4 types */ 2438 #define FC4_TYPE_FCP_SCSI 0x08 2439 #define FC4_TYPE_NVME 0x28 2440 #define FC4_TYPE_OTHER 0x0 2441 #define FC4_TYPE_UNKNOWN 0xff 2442 2443 /* mailbox command 4G & above */ 2444 struct mbx_24xx_entry { 2445 uint8_t entry_type; 2446 uint8_t entry_count; 2447 uint8_t sys_define1; 2448 uint8_t entry_status; 2449 uint32_t handle; 2450 uint16_t mb[28]; 2451 }; 2452 2453 #define IOCB_SIZE 64 2454 2455 /* 2456 * Fibre channel port type. 2457 */ 2458 typedef enum { 2459 FCT_UNKNOWN, 2460 FCT_BROADCAST = 0x01, 2461 FCT_INITIATOR = 0x02, 2462 FCT_TARGET = 0x04, 2463 FCT_NVME_INITIATOR = 0x10, 2464 FCT_NVME_TARGET = 0x20, 2465 FCT_NVME_DISCOVERY = 0x40, 2466 FCT_NVME = 0xf0, 2467 } fc_port_type_t; 2468 2469 enum qla_sess_deletion { 2470 QLA_SESS_DELETION_NONE = 0, 2471 QLA_SESS_DELETION_IN_PROGRESS, 2472 QLA_SESS_DELETED, 2473 }; 2474 2475 enum qlt_plogi_link_t { 2476 QLT_PLOGI_LINK_SAME_WWN, 2477 QLT_PLOGI_LINK_CONFLICT, 2478 QLT_PLOGI_LINK_MAX 2479 }; 2480 2481 struct qlt_plogi_ack_t { 2482 struct list_head list; 2483 struct imm_ntfy_from_isp iocb; 2484 port_id_t id; 2485 int ref_count; 2486 void *fcport; 2487 }; 2488 2489 struct ct_sns_desc { 2490 struct ct_sns_pkt *ct_sns; 2491 dma_addr_t ct_sns_dma; 2492 }; 2493 2494 enum discovery_state { 2495 DSC_DELETED, 2496 DSC_GNL, 2497 DSC_LOGIN_PEND, 2498 DSC_LOGIN_FAILED, 2499 DSC_GPDB, 2500 DSC_UPD_FCPORT, 2501 DSC_LOGIN_COMPLETE, 2502 DSC_ADISC, 2503 DSC_DELETE_PEND, 2504 DSC_LOGIN_AUTH_PEND, 2505 }; 2506 2507 enum login_state { /* FW control Target side */ 2508 DSC_LS_LLIOCB_SENT = 2, 2509 DSC_LS_PLOGI_PEND, 2510 DSC_LS_PLOGI_COMP, 2511 DSC_LS_PRLI_PEND, 2512 DSC_LS_PRLI_COMP, 2513 DSC_LS_PORT_UNAVAIL, 2514 DSC_LS_PRLO_PEND = 9, 2515 DSC_LS_LOGO_PEND, 2516 }; 2517 2518 enum rscn_addr_format { 2519 RSCN_PORT_ADDR, 2520 RSCN_AREA_ADDR, 2521 RSCN_DOM_ADDR, 2522 RSCN_FAB_ADDR, 2523 }; 2524 2525 /* 2526 * Fibre channel port structure. 2527 */ 2528 typedef struct fc_port { 2529 struct list_head list; 2530 struct scsi_qla_host *vha; 2531 2532 unsigned int conf_compl_supported:1; 2533 unsigned int deleted:2; 2534 unsigned int free_pending:1; 2535 unsigned int local:1; 2536 unsigned int logout_on_delete:1; 2537 unsigned int logo_ack_needed:1; 2538 unsigned int keep_nport_handle:1; 2539 unsigned int send_els_logo:1; 2540 unsigned int login_pause:1; 2541 unsigned int login_succ:1; 2542 unsigned int query:1; 2543 unsigned int id_changed:1; 2544 unsigned int scan_needed:1; 2545 unsigned int n2n_flag:1; 2546 unsigned int explicit_logout:1; 2547 unsigned int prli_pend_timer:1; 2548 unsigned int do_prli_nvme:1; 2549 2550 uint8_t nvme_flag; 2551 2552 uint8_t node_name[WWN_SIZE]; 2553 uint8_t port_name[WWN_SIZE]; 2554 port_id_t d_id; 2555 uint16_t loop_id; 2556 uint16_t old_loop_id; 2557 2558 struct completion nvme_del_done; 2559 uint32_t nvme_prli_service_param; 2560 #define NVME_PRLI_SP_PI_CTRL BIT_9 2561 #define NVME_PRLI_SP_SLER BIT_8 2562 #define NVME_PRLI_SP_CONF BIT_7 2563 #define NVME_PRLI_SP_INITIATOR BIT_5 2564 #define NVME_PRLI_SP_TARGET BIT_4 2565 #define NVME_PRLI_SP_DISCOVERY BIT_3 2566 #define NVME_PRLI_SP_FIRST_BURST BIT_0 2567 2568 uint32_t nvme_first_burst_size; 2569 #define NVME_FLAG_REGISTERED 4 2570 #define NVME_FLAG_DELETING 2 2571 #define NVME_FLAG_RESETTING 1 2572 2573 struct fc_port *conflict; 2574 unsigned char logout_completed; 2575 int generation; 2576 2577 struct se_session *se_sess; 2578 struct list_head sess_cmd_list; 2579 spinlock_t sess_cmd_lock; 2580 struct kref sess_kref; 2581 struct qla_tgt *tgt; 2582 unsigned long expires; 2583 struct list_head del_list_entry; 2584 struct work_struct free_work; 2585 struct work_struct reg_work; 2586 uint64_t jiffies_at_registration; 2587 unsigned long prli_expired; 2588 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2589 2590 uint16_t tgt_id; 2591 uint16_t old_tgt_id; 2592 uint16_t sec_since_registration; 2593 2594 uint8_t fcp_prio; 2595 2596 uint8_t fabric_port_name[WWN_SIZE]; 2597 uint16_t fp_speed; 2598 2599 fc_port_type_t port_type; 2600 2601 atomic_t state; 2602 uint32_t flags; 2603 2604 int login_retry; 2605 2606 struct fc_rport *rport; 2607 u32 supported_classes; 2608 2609 uint8_t fc4_type; 2610 uint8_t fc4_features; 2611 uint8_t scan_state; 2612 2613 unsigned long last_queue_full; 2614 unsigned long last_ramp_up; 2615 2616 uint16_t port_id; 2617 2618 struct nvme_fc_remote_port *nvme_remote_port; 2619 2620 unsigned long retry_delay_timestamp; 2621 struct qla_tgt_sess *tgt_session; 2622 struct ct_sns_desc ct_desc; 2623 enum discovery_state disc_state; 2624 atomic_t shadow_disc_state; 2625 enum discovery_state next_disc_state; 2626 enum login_state fw_login_state; 2627 unsigned long dm_login_expire; 2628 unsigned long plogi_nack_done_deadline; 2629 2630 u32 login_gen, last_login_gen; 2631 u32 rscn_gen, last_rscn_gen; 2632 u32 chip_reset; 2633 struct list_head gnl_entry; 2634 struct work_struct del_work; 2635 u8 iocb[IOCB_SIZE]; 2636 u8 current_login_state; 2637 u8 last_login_state; 2638 u16 n2n_link_reset_cnt; 2639 u16 n2n_chip_reset; 2640 2641 struct dentry *dfs_rport_dir; 2642 2643 u64 tgt_short_link_down_cnt; 2644 u64 tgt_link_down_time; 2645 u64 dev_loss_tmo; 2646 /* 2647 * EDIF parameters for encryption. 2648 */ 2649 struct { 2650 uint32_t enable:1; /* device is edif enabled/req'd */ 2651 uint32_t app_stop:2; 2652 uint32_t aes_gmac:1; 2653 uint32_t app_sess_online:1; 2654 uint32_t tx_sa_set:1; 2655 uint32_t rx_sa_set:1; 2656 uint32_t tx_sa_pending:1; 2657 uint32_t rx_sa_pending:1; 2658 uint32_t tx_rekey_cnt; 2659 uint32_t rx_rekey_cnt; 2660 uint64_t tx_bytes; 2661 uint64_t rx_bytes; 2662 uint8_t sess_down_acked; 2663 uint8_t auth_state; 2664 uint16_t authok:1; 2665 uint16_t rekey_cnt; 2666 struct list_head edif_indx_list; 2667 spinlock_t indx_list_lock; 2668 2669 struct list_head tx_sa_list; 2670 struct list_head rx_sa_list; 2671 spinlock_t sa_list_lock; 2672 } edif; 2673 } fc_port_t; 2674 2675 enum { 2676 FC4_PRIORITY_NVME = 1, 2677 FC4_PRIORITY_FCP = 2, 2678 }; 2679 2680 #define QLA_FCPORT_SCAN 1 2681 #define QLA_FCPORT_FOUND 2 2682 2683 struct event_arg { 2684 fc_port_t *fcport; 2685 srb_t *sp; 2686 port_id_t id; 2687 u16 data[2], rc; 2688 u8 port_name[WWN_SIZE]; 2689 u32 iop[2]; 2690 }; 2691 2692 #include "qla_mr.h" 2693 2694 /* 2695 * Fibre channel port/lun states. 2696 */ 2697 enum { 2698 FCS_UNKNOWN, 2699 FCS_UNCONFIGURED, 2700 FCS_DEVICE_DEAD, 2701 FCS_DEVICE_LOST, 2702 FCS_ONLINE, 2703 }; 2704 2705 extern const char *const port_state_str[5]; 2706 2707 static const char *const port_dstate_str[] = { 2708 [DSC_DELETED] = "DELETED", 2709 [DSC_GNL] = "GNL", 2710 [DSC_LOGIN_PEND] = "LOGIN_PEND", 2711 [DSC_LOGIN_FAILED] = "LOGIN_FAILED", 2712 [DSC_GPDB] = "GPDB", 2713 [DSC_UPD_FCPORT] = "UPD_FCPORT", 2714 [DSC_LOGIN_COMPLETE] = "LOGIN_COMPLETE", 2715 [DSC_ADISC] = "ADISC", 2716 [DSC_DELETE_PEND] = "DELETE_PEND", 2717 [DSC_LOGIN_AUTH_PEND] = "LOGIN_AUTH_PEND", 2718 }; 2719 2720 /* 2721 * FC port flags. 2722 */ 2723 #define FCF_FABRIC_DEVICE BIT_0 2724 #define FCF_LOGIN_NEEDED BIT_1 2725 #define FCF_FCP2_DEVICE BIT_2 2726 #define FCF_ASYNC_SENT BIT_3 2727 #define FCF_CONF_COMP_SUPPORTED BIT_4 2728 #define FCF_ASYNC_ACTIVE BIT_5 2729 #define FCF_FCSP_DEVICE BIT_6 2730 #define FCF_EDIF_DELETE BIT_7 2731 2732 /* No loop ID flag. */ 2733 #define FC_NO_LOOP_ID 0x1000 2734 2735 /* 2736 * FC-CT interface 2737 * 2738 * NOTE: All structures are big-endian in form. 2739 */ 2740 2741 #define CT_REJECT_RESPONSE 0x8001 2742 #define CT_ACCEPT_RESPONSE 0x8002 2743 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2744 #define CT_REASON_CANNOT_PERFORM 0x09 2745 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2746 #define CT_EXPL_ALREADY_REGISTERED 0x10 2747 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2748 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2749 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2750 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2751 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2752 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2753 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2754 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2755 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2756 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2757 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2758 2759 #define NS_N_PORT_TYPE 0x01 2760 #define NS_NL_PORT_TYPE 0x02 2761 #define NS_NX_PORT_TYPE 0x7F 2762 2763 #define GA_NXT_CMD 0x100 2764 #define GA_NXT_REQ_SIZE (16 + 4) 2765 #define GA_NXT_RSP_SIZE (16 + 620) 2766 2767 #define GPN_FT_CMD 0x172 2768 #define GPN_FT_REQ_SIZE (16 + 4) 2769 #define GNN_FT_CMD 0x173 2770 #define GNN_FT_REQ_SIZE (16 + 4) 2771 2772 #define GID_PT_CMD 0x1A1 2773 #define GID_PT_REQ_SIZE (16 + 4) 2774 2775 #define GPN_ID_CMD 0x112 2776 #define GPN_ID_REQ_SIZE (16 + 4) 2777 #define GPN_ID_RSP_SIZE (16 + 8) 2778 2779 #define GNN_ID_CMD 0x113 2780 #define GNN_ID_REQ_SIZE (16 + 4) 2781 #define GNN_ID_RSP_SIZE (16 + 8) 2782 2783 #define GFT_ID_CMD 0x117 2784 #define GFT_ID_REQ_SIZE (16 + 4) 2785 #define GFT_ID_RSP_SIZE (16 + 32) 2786 2787 #define GID_PN_CMD 0x121 2788 #define GID_PN_REQ_SIZE (16 + 8) 2789 #define GID_PN_RSP_SIZE (16 + 4) 2790 2791 #define RFT_ID_CMD 0x217 2792 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2793 #define RFT_ID_RSP_SIZE 16 2794 2795 #define RFF_ID_CMD 0x21F 2796 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2797 #define RFF_ID_RSP_SIZE 16 2798 2799 #define RNN_ID_CMD 0x213 2800 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2801 #define RNN_ID_RSP_SIZE 16 2802 2803 #define RSNN_NN_CMD 0x239 2804 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2805 #define RSNN_NN_RSP_SIZE 16 2806 2807 #define GFPN_ID_CMD 0x11C 2808 #define GFPN_ID_REQ_SIZE (16 + 4) 2809 #define GFPN_ID_RSP_SIZE (16 + 8) 2810 2811 #define GPSC_CMD 0x127 2812 #define GPSC_REQ_SIZE (16 + 8) 2813 #define GPSC_RSP_SIZE (16 + 2 + 2) 2814 2815 #define GFF_ID_CMD 0x011F 2816 #define GFF_ID_REQ_SIZE (16 + 4) 2817 #define GFF_ID_RSP_SIZE (16 + 128) 2818 2819 /* 2820 * FDMI HBA attribute types. 2821 */ 2822 #define FDMI1_HBA_ATTR_COUNT 10 2823 #define FDMI2_HBA_ATTR_COUNT 17 2824 2825 #define FDMI_HBA_NODE_NAME 0x1 2826 #define FDMI_HBA_MANUFACTURER 0x2 2827 #define FDMI_HBA_SERIAL_NUMBER 0x3 2828 #define FDMI_HBA_MODEL 0x4 2829 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2830 #define FDMI_HBA_HARDWARE_VERSION 0x6 2831 #define FDMI_HBA_DRIVER_VERSION 0x7 2832 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2833 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2834 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2835 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2836 2837 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2838 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd 2839 #define FDMI_HBA_NUM_PORTS 0xe 2840 #define FDMI_HBA_FABRIC_NAME 0xf 2841 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2842 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0 2843 2844 struct ct_fdmi_hba_attr { 2845 __be16 type; 2846 __be16 len; 2847 union { 2848 uint8_t node_name[WWN_SIZE]; 2849 uint8_t manufacturer[64]; 2850 uint8_t serial_num[32]; 2851 uint8_t model[16+1]; 2852 uint8_t model_desc[80]; 2853 uint8_t hw_version[32]; 2854 uint8_t driver_version[32]; 2855 uint8_t orom_version[16]; 2856 uint8_t fw_version[32]; 2857 uint8_t os_version[128]; 2858 __be32 max_ct_len; 2859 2860 uint8_t sym_name[256]; 2861 __be32 vendor_specific_info; 2862 __be32 num_ports; 2863 uint8_t fabric_name[WWN_SIZE]; 2864 uint8_t bios_name[32]; 2865 uint8_t vendor_identifier[8]; 2866 } a; 2867 }; 2868 2869 struct ct_fdmi1_hba_attributes { 2870 __be32 count; 2871 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT]; 2872 }; 2873 2874 struct ct_fdmi2_hba_attributes { 2875 __be32 count; 2876 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT]; 2877 }; 2878 2879 /* 2880 * FDMI Port attribute types. 2881 */ 2882 #define FDMI1_PORT_ATTR_COUNT 6 2883 #define FDMI2_PORT_ATTR_COUNT 16 2884 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23 2885 2886 #define FDMI_PORT_FC4_TYPES 0x1 2887 #define FDMI_PORT_SUPPORT_SPEED 0x2 2888 #define FDMI_PORT_CURRENT_SPEED 0x3 2889 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2890 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2891 #define FDMI_PORT_HOST_NAME 0x6 2892 2893 #define FDMI_PORT_NODE_NAME 0x7 2894 #define FDMI_PORT_NAME 0x8 2895 #define FDMI_PORT_SYM_NAME 0x9 2896 #define FDMI_PORT_TYPE 0xa 2897 #define FDMI_PORT_SUPP_COS 0xb 2898 #define FDMI_PORT_FABRIC_NAME 0xc 2899 #define FDMI_PORT_FC4_TYPE 0xd 2900 #define FDMI_PORT_STATE 0x101 2901 #define FDMI_PORT_COUNT 0x102 2902 #define FDMI_PORT_IDENTIFIER 0x103 2903 2904 #define FDMI_SMARTSAN_SERVICE 0xF100 2905 #define FDMI_SMARTSAN_GUID 0xF101 2906 #define FDMI_SMARTSAN_VERSION 0xF102 2907 #define FDMI_SMARTSAN_PROD_NAME 0xF103 2908 #define FDMI_SMARTSAN_PORT_INFO 0xF104 2909 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105 2910 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106 2911 2912 #define FDMI_PORT_SPEED_1GB 0x1 2913 #define FDMI_PORT_SPEED_2GB 0x2 2914 #define FDMI_PORT_SPEED_10GB 0x4 2915 #define FDMI_PORT_SPEED_4GB 0x8 2916 #define FDMI_PORT_SPEED_8GB 0x10 2917 #define FDMI_PORT_SPEED_16GB 0x20 2918 #define FDMI_PORT_SPEED_32GB 0x40 2919 #define FDMI_PORT_SPEED_20GB 0x80 2920 #define FDMI_PORT_SPEED_40GB 0x100 2921 #define FDMI_PORT_SPEED_128GB 0x200 2922 #define FDMI_PORT_SPEED_64GB 0x400 2923 #define FDMI_PORT_SPEED_256GB 0x800 2924 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2925 2926 #define FC_CLASS_2 0x04 2927 #define FC_CLASS_3 0x08 2928 #define FC_CLASS_2_3 0x0C 2929 2930 struct ct_fdmi_port_attr { 2931 __be16 type; 2932 __be16 len; 2933 union { 2934 uint8_t fc4_types[32]; 2935 __be32 sup_speed; 2936 __be32 cur_speed; 2937 __be32 max_frame_size; 2938 uint8_t os_dev_name[32]; 2939 uint8_t host_name[256]; 2940 2941 uint8_t node_name[WWN_SIZE]; 2942 uint8_t port_name[WWN_SIZE]; 2943 uint8_t port_sym_name[128]; 2944 __be32 port_type; 2945 __be32 port_supported_cos; 2946 uint8_t fabric_name[WWN_SIZE]; 2947 uint8_t port_fc4_type[32]; 2948 __be32 port_state; 2949 __be32 num_ports; 2950 __be32 port_id; 2951 2952 uint8_t smartsan_service[24]; 2953 uint8_t smartsan_guid[16]; 2954 uint8_t smartsan_version[24]; 2955 uint8_t smartsan_prod_name[16]; 2956 __be32 smartsan_port_info; 2957 __be32 smartsan_qos_support; 2958 __be32 smartsan_security_support; 2959 } a; 2960 }; 2961 2962 struct ct_fdmi1_port_attributes { 2963 __be32 count; 2964 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT]; 2965 }; 2966 2967 struct ct_fdmi2_port_attributes { 2968 __be32 count; 2969 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT]; 2970 }; 2971 2972 #define FDMI_ATTR_TYPELEN(obj) \ 2973 (sizeof((obj)->type) + sizeof((obj)->len)) 2974 2975 #define FDMI_ATTR_ALIGNMENT(len) \ 2976 (4 - ((len) & 3)) 2977 2978 /* FDMI register call options */ 2979 #define CALLOPT_FDMI1 0 2980 #define CALLOPT_FDMI2 1 2981 #define CALLOPT_FDMI2_SMARTSAN 2 2982 2983 /* FDMI definitions. */ 2984 #define GRHL_CMD 0x100 2985 #define GHAT_CMD 0x101 2986 #define GRPL_CMD 0x102 2987 #define GPAT_CMD 0x110 2988 2989 #define RHBA_CMD 0x200 2990 #define RHBA_RSP_SIZE 16 2991 2992 #define RHAT_CMD 0x201 2993 2994 #define RPRT_CMD 0x210 2995 #define RPRT_RSP_SIZE 24 2996 2997 #define RPA_CMD 0x211 2998 #define RPA_RSP_SIZE 16 2999 #define SMARTSAN_RPA_RSP_SIZE 24 3000 3001 #define DHBA_CMD 0x300 3002 #define DHBA_REQ_SIZE (16 + 8) 3003 #define DHBA_RSP_SIZE 16 3004 3005 #define DHAT_CMD 0x301 3006 #define DPRT_CMD 0x310 3007 #define DPA_CMD 0x311 3008 3009 /* CT command header -- request/response common fields */ 3010 struct ct_cmd_hdr { 3011 uint8_t revision; 3012 uint8_t in_id[3]; 3013 uint8_t gs_type; 3014 uint8_t gs_subtype; 3015 uint8_t options; 3016 uint8_t reserved; 3017 }; 3018 3019 /* CT command request */ 3020 struct ct_sns_req { 3021 struct ct_cmd_hdr header; 3022 __be16 command; 3023 __be16 max_rsp_size; 3024 uint8_t fragment_id; 3025 uint8_t reserved[3]; 3026 3027 union { 3028 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 3029 struct { 3030 uint8_t reserved; 3031 be_id_t port_id; 3032 } port_id; 3033 3034 struct { 3035 uint8_t reserved; 3036 uint8_t domain; 3037 uint8_t area; 3038 uint8_t port_type; 3039 } gpn_ft; 3040 3041 struct { 3042 uint8_t port_type; 3043 uint8_t domain; 3044 uint8_t area; 3045 uint8_t reserved; 3046 } gid_pt; 3047 3048 struct { 3049 uint8_t reserved; 3050 be_id_t port_id; 3051 uint8_t fc4_types[32]; 3052 } rft_id; 3053 3054 struct { 3055 uint8_t reserved; 3056 be_id_t port_id; 3057 uint16_t reserved2; 3058 uint8_t fc4_feature; 3059 uint8_t fc4_type; 3060 } rff_id; 3061 3062 struct { 3063 uint8_t reserved; 3064 be_id_t port_id; 3065 uint8_t node_name[8]; 3066 } rnn_id; 3067 3068 struct { 3069 uint8_t node_name[8]; 3070 uint8_t name_len; 3071 uint8_t sym_node_name[255]; 3072 } rsnn_nn; 3073 3074 struct { 3075 uint8_t hba_identifier[8]; 3076 } ghat; 3077 3078 struct { 3079 uint8_t hba_identifier[8]; 3080 __be32 entry_count; 3081 uint8_t port_name[8]; 3082 struct ct_fdmi2_hba_attributes attrs; 3083 } rhba; 3084 3085 struct { 3086 uint8_t hba_identifier[8]; 3087 struct ct_fdmi1_hba_attributes attrs; 3088 } rhat; 3089 3090 struct { 3091 uint8_t port_name[8]; 3092 struct ct_fdmi2_port_attributes attrs; 3093 } rpa; 3094 3095 struct { 3096 uint8_t hba_identifier[8]; 3097 uint8_t port_name[8]; 3098 struct ct_fdmi2_port_attributes attrs; 3099 } rprt; 3100 3101 struct { 3102 uint8_t port_name[8]; 3103 } dhba; 3104 3105 struct { 3106 uint8_t port_name[8]; 3107 } dhat; 3108 3109 struct { 3110 uint8_t port_name[8]; 3111 } dprt; 3112 3113 struct { 3114 uint8_t port_name[8]; 3115 } dpa; 3116 3117 struct { 3118 uint8_t port_name[8]; 3119 } gpsc; 3120 3121 struct { 3122 uint8_t reserved; 3123 uint8_t port_id[3]; 3124 } gff_id; 3125 3126 struct { 3127 uint8_t port_name[8]; 3128 } gid_pn; 3129 } req; 3130 }; 3131 3132 /* CT command response header */ 3133 struct ct_rsp_hdr { 3134 struct ct_cmd_hdr header; 3135 __be16 response; 3136 uint16_t residual; 3137 uint8_t fragment_id; 3138 uint8_t reason_code; 3139 uint8_t explanation_code; 3140 uint8_t vendor_unique; 3141 }; 3142 3143 struct ct_sns_gid_pt_data { 3144 uint8_t control_byte; 3145 be_id_t port_id; 3146 }; 3147 3148 /* It's the same for both GPN_FT and GNN_FT */ 3149 struct ct_sns_gpnft_rsp { 3150 struct { 3151 struct ct_cmd_hdr header; 3152 uint16_t response; 3153 uint16_t residual; 3154 uint8_t fragment_id; 3155 uint8_t reason_code; 3156 uint8_t explanation_code; 3157 uint8_t vendor_unique; 3158 }; 3159 /* Assume the largest number of targets for the union */ 3160 struct ct_sns_gpn_ft_data { 3161 u8 control_byte; 3162 u8 port_id[3]; 3163 u32 reserved; 3164 u8 port_name[8]; 3165 } entries[1]; 3166 }; 3167 3168 /* CT command response */ 3169 struct ct_sns_rsp { 3170 struct ct_rsp_hdr header; 3171 3172 union { 3173 struct { 3174 uint8_t port_type; 3175 be_id_t port_id; 3176 uint8_t port_name[8]; 3177 uint8_t sym_port_name_len; 3178 uint8_t sym_port_name[255]; 3179 uint8_t node_name[8]; 3180 uint8_t sym_node_name_len; 3181 uint8_t sym_node_name[255]; 3182 uint8_t init_proc_assoc[8]; 3183 uint8_t node_ip_addr[16]; 3184 uint8_t class_of_service[4]; 3185 uint8_t fc4_types[32]; 3186 uint8_t ip_address[16]; 3187 uint8_t fabric_port_name[8]; 3188 uint8_t reserved; 3189 uint8_t hard_address[3]; 3190 } ga_nxt; 3191 3192 struct { 3193 /* Assume the largest number of targets for the union */ 3194 struct ct_sns_gid_pt_data 3195 entries[MAX_FIBRE_DEVICES_MAX]; 3196 } gid_pt; 3197 3198 struct { 3199 uint8_t port_name[8]; 3200 } gpn_id; 3201 3202 struct { 3203 uint8_t node_name[8]; 3204 } gnn_id; 3205 3206 struct { 3207 uint8_t fc4_types[32]; 3208 } gft_id; 3209 3210 struct { 3211 uint32_t entry_count; 3212 uint8_t port_name[8]; 3213 struct ct_fdmi1_hba_attributes attrs; 3214 } ghat; 3215 3216 struct { 3217 uint8_t port_name[8]; 3218 } gfpn_id; 3219 3220 struct { 3221 __be16 speeds; 3222 __be16 speed; 3223 } gpsc; 3224 3225 #define GFF_FCP_SCSI_OFFSET 7 3226 #define GFF_NVME_OFFSET 23 /* type = 28h */ 3227 struct { 3228 uint8_t fc4_features[128]; 3229 #define FC4_FF_TARGET BIT_0 3230 #define FC4_FF_INITIATOR BIT_1 3231 } gff_id; 3232 struct { 3233 uint8_t reserved; 3234 uint8_t port_id[3]; 3235 } gid_pn; 3236 } rsp; 3237 }; 3238 3239 struct ct_sns_pkt { 3240 union { 3241 struct ct_sns_req req; 3242 struct ct_sns_rsp rsp; 3243 } p; 3244 }; 3245 3246 struct ct_sns_gpnft_pkt { 3247 union { 3248 struct ct_sns_req req; 3249 struct ct_sns_gpnft_rsp rsp; 3250 } p; 3251 }; 3252 3253 enum scan_flags_t { 3254 SF_SCANNING = BIT_0, 3255 SF_QUEUED = BIT_1, 3256 }; 3257 3258 enum fc4type_t { 3259 FS_FC4TYPE_FCP = BIT_0, 3260 FS_FC4TYPE_NVME = BIT_1, 3261 FS_FCP_IS_N2N = BIT_7, 3262 }; 3263 3264 struct fab_scan_rp { 3265 port_id_t id; 3266 enum fc4type_t fc4type; 3267 u8 port_name[8]; 3268 u8 node_name[8]; 3269 }; 3270 3271 struct fab_scan { 3272 struct fab_scan_rp *l; 3273 u32 size; 3274 u16 scan_retry; 3275 #define MAX_SCAN_RETRIES 5 3276 enum scan_flags_t scan_flags; 3277 struct delayed_work scan_work; 3278 }; 3279 3280 /* 3281 * SNS command structures -- for 2200 compatibility. 3282 */ 3283 #define RFT_ID_SNS_SCMD_LEN 22 3284 #define RFT_ID_SNS_CMD_SIZE 60 3285 #define RFT_ID_SNS_DATA_SIZE 16 3286 3287 #define RNN_ID_SNS_SCMD_LEN 10 3288 #define RNN_ID_SNS_CMD_SIZE 36 3289 #define RNN_ID_SNS_DATA_SIZE 16 3290 3291 #define GA_NXT_SNS_SCMD_LEN 6 3292 #define GA_NXT_SNS_CMD_SIZE 28 3293 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 3294 3295 #define GID_PT_SNS_SCMD_LEN 6 3296 #define GID_PT_SNS_CMD_SIZE 28 3297 /* 3298 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 3299 * adapters. 3300 */ 3301 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 3302 3303 #define GPN_ID_SNS_SCMD_LEN 6 3304 #define GPN_ID_SNS_CMD_SIZE 28 3305 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 3306 3307 #define GNN_ID_SNS_SCMD_LEN 6 3308 #define GNN_ID_SNS_CMD_SIZE 28 3309 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 3310 3311 struct sns_cmd_pkt { 3312 union { 3313 struct { 3314 __le16 buffer_length; 3315 __le16 reserved_1; 3316 __le64 buffer_address __packed; 3317 __le16 subcommand_length; 3318 __le16 reserved_2; 3319 __le16 subcommand; 3320 __le16 size; 3321 uint32_t reserved_3; 3322 uint8_t param[36]; 3323 } cmd; 3324 3325 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 3326 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 3327 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 3328 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 3329 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 3330 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 3331 } p; 3332 }; 3333 3334 struct fw_blob { 3335 char *name; 3336 uint32_t segs[4]; 3337 const struct firmware *fw; 3338 }; 3339 3340 /* Return data from MBC_GET_ID_LIST call. */ 3341 struct gid_list_info { 3342 uint8_t al_pa; 3343 uint8_t area; 3344 uint8_t domain; 3345 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 3346 __le16 loop_id; /* ISP23XX -- 6 bytes. */ 3347 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 3348 }; 3349 3350 /* NPIV */ 3351 typedef struct vport_info { 3352 uint8_t port_name[WWN_SIZE]; 3353 uint8_t node_name[WWN_SIZE]; 3354 int vp_id; 3355 uint16_t loop_id; 3356 unsigned long host_no; 3357 uint8_t port_id[3]; 3358 int loop_state; 3359 } vport_info_t; 3360 3361 typedef struct vport_params { 3362 uint8_t port_name[WWN_SIZE]; 3363 uint8_t node_name[WWN_SIZE]; 3364 uint32_t options; 3365 #define VP_OPTS_RETRY_ENABLE BIT_0 3366 #define VP_OPTS_VP_DISABLE BIT_1 3367 } vport_params_t; 3368 3369 /* NPIV - return codes of VP create and modify */ 3370 #define VP_RET_CODE_OK 0 3371 #define VP_RET_CODE_FATAL 1 3372 #define VP_RET_CODE_WRONG_ID 2 3373 #define VP_RET_CODE_WWPN 3 3374 #define VP_RET_CODE_RESOURCES 4 3375 #define VP_RET_CODE_NO_MEM 5 3376 #define VP_RET_CODE_NOT_FOUND 6 3377 3378 struct qla_hw_data; 3379 struct rsp_que; 3380 /* 3381 * ISP operations 3382 */ 3383 struct isp_operations { 3384 3385 int (*pci_config) (struct scsi_qla_host *); 3386 int (*reset_chip)(struct scsi_qla_host *); 3387 int (*chip_diag) (struct scsi_qla_host *); 3388 void (*config_rings) (struct scsi_qla_host *); 3389 int (*reset_adapter)(struct scsi_qla_host *); 3390 int (*nvram_config) (struct scsi_qla_host *); 3391 void (*update_fw_options) (struct scsi_qla_host *); 3392 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3393 3394 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t); 3395 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3396 3397 irq_handler_t intr_handler; 3398 void (*enable_intrs) (struct qla_hw_data *); 3399 void (*disable_intrs) (struct qla_hw_data *); 3400 3401 int (*abort_command) (srb_t *); 3402 int (*target_reset) (struct fc_port *, uint64_t, int); 3403 int (*lun_reset) (struct fc_port *, uint64_t, int); 3404 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3405 uint8_t, uint8_t, uint16_t *, uint8_t); 3406 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3407 uint8_t, uint8_t); 3408 3409 uint16_t (*calc_req_entries) (uint16_t); 3410 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3411 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3412 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3413 uint32_t); 3414 3415 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *, 3416 uint32_t, uint32_t); 3417 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t, 3418 uint32_t); 3419 3420 void (*fw_dump)(struct scsi_qla_host *vha); 3421 void (*mpi_fw_dump)(struct scsi_qla_host *, int); 3422 3423 /* Context: task, might sleep */ 3424 int (*beacon_on) (struct scsi_qla_host *); 3425 int (*beacon_off) (struct scsi_qla_host *); 3426 3427 void (*beacon_blink) (struct scsi_qla_host *); 3428 3429 void *(*read_optrom)(struct scsi_qla_host *, void *, 3430 uint32_t, uint32_t); 3431 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t, 3432 uint32_t); 3433 3434 int (*get_flash_version) (struct scsi_qla_host *, void *); 3435 int (*start_scsi) (srb_t *); 3436 int (*start_scsi_mq) (srb_t *); 3437 3438 /* Context: task, might sleep */ 3439 int (*abort_isp) (struct scsi_qla_host *); 3440 3441 int (*iospace_config)(struct qla_hw_data *); 3442 int (*initialize_adapter)(struct scsi_qla_host *); 3443 }; 3444 3445 /* MSI-X Support *************************************************************/ 3446 3447 #define QLA_MSIX_CHIP_REV_24XX 3 3448 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3449 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3450 3451 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3452 #define QLA_MSIX_RSP_Q 0x01 3453 #define QLA_ATIO_VECTOR 0x02 3454 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3455 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04 3456 3457 #define QLA_MIDX_DEFAULT 0 3458 #define QLA_MIDX_RSP_Q 1 3459 #define QLA_PCI_MSIX_CONTROL 0xa2 3460 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3461 3462 struct scsi_qla_host; 3463 3464 3465 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3466 3467 struct qla_msix_entry { 3468 int have_irq; 3469 int in_use; 3470 uint32_t vector; 3471 uint32_t vector_base0; 3472 uint16_t entry; 3473 char name[30]; 3474 void *handle; 3475 int cpuid; 3476 }; 3477 3478 #define WATCH_INTERVAL 1 /* number of seconds */ 3479 3480 /* Work events. */ 3481 enum qla_work_type { 3482 QLA_EVT_AEN, 3483 QLA_EVT_IDC_ACK, 3484 QLA_EVT_ASYNC_LOGIN, 3485 QLA_EVT_ASYNC_LOGOUT, 3486 QLA_EVT_ASYNC_ADISC, 3487 QLA_EVT_UEVENT, 3488 QLA_EVT_AENFX, 3489 QLA_EVT_UNMAP, 3490 QLA_EVT_NEW_SESS, 3491 QLA_EVT_GPDB, 3492 QLA_EVT_PRLI, 3493 QLA_EVT_GPSC, 3494 QLA_EVT_GNL, 3495 QLA_EVT_NACK, 3496 QLA_EVT_RELOGIN, 3497 QLA_EVT_ASYNC_PRLO, 3498 QLA_EVT_ASYNC_PRLO_DONE, 3499 QLA_EVT_GPNFT, 3500 QLA_EVT_GPNFT_DONE, 3501 QLA_EVT_GNNFT_DONE, 3502 QLA_EVT_GFPNID, 3503 QLA_EVT_SP_RETRY, 3504 QLA_EVT_IIDMA, 3505 QLA_EVT_ELS_PLOGI, 3506 QLA_EVT_SA_REPLACE, 3507 }; 3508 3509 3510 struct qla_work_evt { 3511 struct list_head list; 3512 enum qla_work_type type; 3513 u32 flags; 3514 #define QLA_EVT_FLAG_FREE 0x1 3515 3516 union { 3517 struct { 3518 enum fc_host_event_code code; 3519 u32 data; 3520 } aen; 3521 struct { 3522 #define QLA_IDC_ACK_REGS 7 3523 uint16_t mb[QLA_IDC_ACK_REGS]; 3524 } idc_ack; 3525 struct { 3526 struct fc_port *fcport; 3527 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3528 u16 data[2]; 3529 } logio; 3530 struct { 3531 u32 code; 3532 #define QLA_UEVENT_CODE_FW_DUMP 0 3533 } uevent; 3534 struct { 3535 uint32_t evtcode; 3536 uint32_t mbx[8]; 3537 uint32_t count; 3538 } aenfx; 3539 struct { 3540 srb_t *sp; 3541 } iosb; 3542 struct { 3543 port_id_t id; 3544 u8 port_name[8]; 3545 u8 node_name[8]; 3546 void *pla; 3547 u8 fc4_type; 3548 } new_sess; 3549 struct { /*Get PDB, Get Speed, update fcport, gnl */ 3550 fc_port_t *fcport; 3551 u8 opt; 3552 } fcport; 3553 struct { 3554 fc_port_t *fcport; 3555 u8 iocb[IOCB_SIZE]; 3556 int type; 3557 } nack; 3558 struct { 3559 u8 fc4_type; 3560 srb_t *sp; 3561 } gpnft; 3562 struct { 3563 struct edif_sa_ctl *sa_ctl; 3564 fc_port_t *fcport; 3565 uint16_t nport_handle; 3566 } sa_update; 3567 } u; 3568 }; 3569 3570 struct qla_chip_state_84xx { 3571 struct list_head list; 3572 struct kref kref; 3573 3574 void *bus; 3575 spinlock_t access_lock; 3576 struct mutex fw_update_mutex; 3577 uint32_t fw_update; 3578 uint32_t op_fw_version; 3579 uint32_t op_fw_size; 3580 uint32_t op_fw_seq_size; 3581 uint32_t diag_fw_version; 3582 uint32_t gold_fw_version; 3583 }; 3584 3585 struct qla_dif_statistics { 3586 uint64_t dif_input_bytes; 3587 uint64_t dif_output_bytes; 3588 uint64_t dif_input_requests; 3589 uint64_t dif_output_requests; 3590 uint32_t dif_guard_err; 3591 uint32_t dif_ref_tag_err; 3592 uint32_t dif_app_tag_err; 3593 }; 3594 3595 struct qla_statistics { 3596 uint32_t total_isp_aborts; 3597 uint64_t input_bytes; 3598 uint64_t output_bytes; 3599 uint64_t input_requests; 3600 uint64_t output_requests; 3601 uint32_t control_requests; 3602 3603 uint64_t jiffies_at_last_reset; 3604 uint32_t stat_max_pend_cmds; 3605 uint32_t stat_max_qfull_cmds_alloc; 3606 uint32_t stat_max_qfull_cmds_dropped; 3607 3608 struct qla_dif_statistics qla_dif_stats; 3609 }; 3610 3611 struct bidi_statistics { 3612 unsigned long long io_count; 3613 unsigned long long transfer_bytes; 3614 }; 3615 3616 struct qla_tc_param { 3617 struct scsi_qla_host *vha; 3618 uint32_t blk_sz; 3619 uint32_t bufflen; 3620 struct scatterlist *sg; 3621 struct scatterlist *prot_sg; 3622 struct crc_context *ctx; 3623 uint8_t *ctx_dsd_alloced; 3624 }; 3625 3626 /* Multi queue support */ 3627 #define MBC_INITIALIZE_MULTIQ 0x1f 3628 #define QLA_QUE_PAGE 0X1000 3629 #define QLA_MQ_SIZE 32 3630 #define QLA_MAX_QUEUES 256 3631 #define ISP_QUE_REG(ha, id) \ 3632 ((ha->mqenable || IS_QLA83XX(ha) || \ 3633 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \ 3634 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3635 ((void __iomem *)ha->iobase)) 3636 #define QLA_REQ_QUE_ID(tag) \ 3637 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3638 #define QLA_DEFAULT_QUE_QOS 5 3639 #define QLA_PRECONFIG_VPORTS 32 3640 #define QLA_MAX_VPORTS_QLA24XX 128 3641 #define QLA_MAX_VPORTS_QLA25XX 256 3642 3643 struct qla_tgt_counters { 3644 uint64_t qla_core_sbt_cmd; 3645 uint64_t core_qla_que_buf; 3646 uint64_t qla_core_ret_ctio; 3647 uint64_t core_qla_snd_status; 3648 uint64_t qla_core_ret_sta_ctio; 3649 uint64_t core_qla_free_cmd; 3650 uint64_t num_q_full_sent; 3651 uint64_t num_alloc_iocb_failed; 3652 uint64_t num_term_xchg_sent; 3653 }; 3654 3655 struct qla_counters { 3656 uint64_t input_bytes; 3657 uint64_t input_requests; 3658 uint64_t output_bytes; 3659 uint64_t output_requests; 3660 3661 }; 3662 3663 struct qla_qpair; 3664 3665 /* Response queue data structure */ 3666 struct rsp_que { 3667 dma_addr_t dma; 3668 response_t *ring; 3669 response_t *ring_ptr; 3670 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */ 3671 __le32 __iomem *rsp_q_out; 3672 uint16_t ring_index; 3673 uint16_t out_ptr; 3674 uint16_t *in_ptr; /* queue shadow in index */ 3675 uint16_t length; 3676 uint16_t options; 3677 uint16_t rid; 3678 uint16_t id; 3679 uint16_t vp_idx; 3680 struct qla_hw_data *hw; 3681 struct qla_msix_entry *msix; 3682 struct req_que *req; 3683 srb_t *status_srb; /* status continuation entry */ 3684 struct qla_qpair *qpair; 3685 3686 dma_addr_t dma_fx00; 3687 response_t *ring_fx00; 3688 uint16_t length_fx00; 3689 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3690 }; 3691 3692 /* Request queue data structure */ 3693 struct req_que { 3694 dma_addr_t dma; 3695 request_t *ring; 3696 request_t *ring_ptr; 3697 __le32 __iomem *req_q_in; /* FWI2-capable only. */ 3698 __le32 __iomem *req_q_out; 3699 uint16_t ring_index; 3700 uint16_t in_ptr; 3701 uint16_t *out_ptr; /* queue shadow out index */ 3702 uint16_t cnt; 3703 uint16_t length; 3704 uint16_t options; 3705 uint16_t rid; 3706 uint16_t id; 3707 uint16_t qos; 3708 uint16_t vp_idx; 3709 struct rsp_que *rsp; 3710 srb_t **outstanding_cmds; 3711 uint32_t current_outstanding_cmd; 3712 uint16_t num_outstanding_cmds; 3713 int max_q_depth; 3714 3715 dma_addr_t dma_fx00; 3716 request_t *ring_fx00; 3717 uint16_t length_fx00; 3718 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3719 }; 3720 3721 struct qla_fw_resources { 3722 u16 iocbs_total; 3723 u16 iocbs_limit; 3724 u16 iocbs_qp_limit; 3725 u16 iocbs_used; 3726 u16 exch_total; 3727 u16 exch_limit; 3728 u16 exch_used; 3729 u16 pad; 3730 }; 3731 3732 #define QLA_IOCB_PCT_LIMIT 95 3733 3734 struct qla_buf_pool { 3735 u16 num_bufs; 3736 u16 num_active; 3737 u16 max_used; 3738 u16 num_alloc; 3739 u16 prev_max; 3740 u16 pad; 3741 uint32_t take_snapshot:1; 3742 unsigned long *buf_map; 3743 void **buf_array; 3744 dma_addr_t *dma_array; 3745 }; 3746 3747 /*Queue pair data structure */ 3748 struct qla_qpair { 3749 spinlock_t qp_lock; 3750 atomic_t ref_count; 3751 uint32_t lun_cnt; 3752 /* 3753 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3754 * legacy code. For other Qpair(s), it will point at qp_lock. 3755 */ 3756 spinlock_t *qp_lock_ptr; 3757 struct scsi_qla_host *vha; 3758 u32 chip_reset; 3759 3760 /* distill these fields down to 'online=0/1' 3761 * ha->flags.eeh_busy 3762 * ha->flags.pci_channel_io_perm_failure 3763 * base_vha->loop_state 3764 */ 3765 uint32_t online:1; 3766 /* move vha->flags.difdix_supported here */ 3767 uint32_t difdix_supported:1; 3768 uint32_t delete_in_progress:1; 3769 uint32_t fw_started:1; 3770 uint32_t enable_class_2:1; 3771 uint32_t enable_explicit_conf:1; 3772 uint32_t use_shadow_reg:1; 3773 uint32_t rcv_intr:1; 3774 3775 uint16_t id; /* qp number used with FW */ 3776 uint16_t vp_idx; /* vport ID */ 3777 mempool_t *srb_mempool; 3778 3779 struct pci_dev *pdev; 3780 void (*reqq_start_iocbs)(struct qla_qpair *); 3781 3782 /* to do: New driver: move queues to here instead of pointers */ 3783 struct req_que *req; 3784 struct rsp_que *rsp; 3785 struct atio_que *atio; 3786 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3787 struct qla_hw_data *hw; 3788 struct work_struct q_work; 3789 struct qla_counters counters; 3790 3791 struct list_head qp_list_elem; /* vha->qp_list */ 3792 struct list_head hints_list; 3793 3794 uint16_t retry_term_cnt; 3795 __le32 retry_term_exchg_addr; 3796 uint64_t retry_term_jiff; 3797 struct qla_tgt_counters tgt_counters; 3798 uint16_t cpuid; 3799 bool cpu_mapped; 3800 struct qla_fw_resources fwres ____cacheline_aligned; 3801 struct qla_buf_pool buf_pool; 3802 u32 cmd_cnt; 3803 u32 cmd_completion_cnt; 3804 u32 prev_completion_cnt; 3805 }; 3806 3807 /* Place holder for FW buffer parameters */ 3808 struct qlfc_fw { 3809 void *fw_buf; 3810 dma_addr_t fw_dma; 3811 uint32_t len; 3812 }; 3813 3814 struct rdp_req_payload { 3815 uint32_t els_request; 3816 uint32_t desc_list_len; 3817 3818 /* NPIV descriptor */ 3819 struct { 3820 uint32_t desc_tag; 3821 uint32_t desc_len; 3822 uint8_t reserved; 3823 uint8_t nport_id[3]; 3824 } npiv_desc; 3825 }; 3826 3827 struct rdp_rsp_payload { 3828 struct { 3829 __be32 cmd; 3830 __be32 len; 3831 } hdr; 3832 3833 /* LS Request Info descriptor */ 3834 struct { 3835 __be32 desc_tag; 3836 __be32 desc_len; 3837 __be32 req_payload_word_0; 3838 } ls_req_info_desc; 3839 3840 /* LS Request Info descriptor */ 3841 struct { 3842 __be32 desc_tag; 3843 __be32 desc_len; 3844 __be32 req_payload_word_0; 3845 } ls_req_info_desc2; 3846 3847 /* SFP diagnostic param descriptor */ 3848 struct { 3849 __be32 desc_tag; 3850 __be32 desc_len; 3851 __be16 temperature; 3852 __be16 vcc; 3853 __be16 tx_bias; 3854 __be16 tx_power; 3855 __be16 rx_power; 3856 __be16 sfp_flags; 3857 } sfp_diag_desc; 3858 3859 /* Port Speed Descriptor */ 3860 struct { 3861 __be32 desc_tag; 3862 __be32 desc_len; 3863 __be16 speed_capab; 3864 __be16 operating_speed; 3865 } port_speed_desc; 3866 3867 /* Link Error Status Descriptor */ 3868 struct { 3869 __be32 desc_tag; 3870 __be32 desc_len; 3871 __be32 link_fail_cnt; 3872 __be32 loss_sync_cnt; 3873 __be32 loss_sig_cnt; 3874 __be32 prim_seq_err_cnt; 3875 __be32 inval_xmit_word_cnt; 3876 __be32 inval_crc_cnt; 3877 uint8_t pn_port_phy_type; 3878 uint8_t reserved[3]; 3879 } ls_err_desc; 3880 3881 /* Port name description with diag param */ 3882 struct { 3883 __be32 desc_tag; 3884 __be32 desc_len; 3885 uint8_t WWNN[WWN_SIZE]; 3886 uint8_t WWPN[WWN_SIZE]; 3887 } port_name_diag_desc; 3888 3889 /* Port Name desc for Direct attached Fx_Port or Nx_Port */ 3890 struct { 3891 __be32 desc_tag; 3892 __be32 desc_len; 3893 uint8_t WWNN[WWN_SIZE]; 3894 uint8_t WWPN[WWN_SIZE]; 3895 } port_name_direct_desc; 3896 3897 /* Buffer Credit descriptor */ 3898 struct { 3899 __be32 desc_tag; 3900 __be32 desc_len; 3901 __be32 fcport_b2b; 3902 __be32 attached_fcport_b2b; 3903 __be32 fcport_rtt; 3904 } buffer_credit_desc; 3905 3906 /* Optical Element Data Descriptor */ 3907 struct { 3908 __be32 desc_tag; 3909 __be32 desc_len; 3910 __be16 high_alarm; 3911 __be16 low_alarm; 3912 __be16 high_warn; 3913 __be16 low_warn; 3914 __be32 element_flags; 3915 } optical_elmt_desc[5]; 3916 3917 /* Optical Product Data Descriptor */ 3918 struct { 3919 __be32 desc_tag; 3920 __be32 desc_len; 3921 uint8_t vendor_name[16]; 3922 uint8_t part_number[16]; 3923 uint8_t serial_number[16]; 3924 uint8_t revision[4]; 3925 uint8_t date[8]; 3926 } optical_prod_desc; 3927 }; 3928 3929 #define RDP_DESC_LEN(obj) \ 3930 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len)) 3931 3932 #define RDP_PORT_SPEED_1GB BIT_15 3933 #define RDP_PORT_SPEED_2GB BIT_14 3934 #define RDP_PORT_SPEED_4GB BIT_13 3935 #define RDP_PORT_SPEED_10GB BIT_12 3936 #define RDP_PORT_SPEED_8GB BIT_11 3937 #define RDP_PORT_SPEED_16GB BIT_10 3938 #define RDP_PORT_SPEED_32GB BIT_9 3939 #define RDP_PORT_SPEED_64GB BIT_8 3940 #define RDP_PORT_SPEED_UNKNOWN BIT_0 3941 3942 struct scsi_qlt_host { 3943 void *target_lport_ptr; 3944 struct mutex tgt_mutex; 3945 struct mutex tgt_host_action_mutex; 3946 struct qla_tgt *qla_tgt; 3947 }; 3948 3949 struct qlt_hw_data { 3950 /* Protected by hw lock */ 3951 uint32_t node_name_set:1; 3952 3953 dma_addr_t atio_dma; /* Physical address. */ 3954 struct atio *atio_ring; /* Base virtual address */ 3955 struct atio *atio_ring_ptr; /* Current address. */ 3956 uint16_t atio_ring_index; /* Current index. */ 3957 uint16_t atio_q_length; 3958 __le32 __iomem *atio_q_in; 3959 __le32 __iomem *atio_q_out; 3960 3961 const struct qla_tgt_func_tmpl *tgt_ops; 3962 3963 int saved_set; 3964 __le16 saved_exchange_count; 3965 __le32 saved_firmware_options_1; 3966 __le32 saved_firmware_options_2; 3967 __le32 saved_firmware_options_3; 3968 uint8_t saved_firmware_options[2]; 3969 uint8_t saved_add_firmware_options[2]; 3970 3971 uint8_t tgt_node_name[WWN_SIZE]; 3972 3973 struct dentry *dfs_tgt_sess; 3974 struct dentry *dfs_tgt_port_database; 3975 struct dentry *dfs_naqp; 3976 3977 struct list_head q_full_list; 3978 uint32_t num_pend_cmds; 3979 uint32_t num_qfull_cmds_alloc; 3980 uint32_t num_qfull_cmds_dropped; 3981 spinlock_t q_full_lock; 3982 uint32_t leak_exchg_thresh_hold; 3983 spinlock_t sess_lock; 3984 int num_act_qpairs; 3985 #define DEFAULT_NAQP 2 3986 spinlock_t atio_lock ____cacheline_aligned; 3987 }; 3988 3989 #define MAX_QFULL_CMDS_ALLOC 8192 3990 #define Q_FULL_THRESH_HOLD_PERCENT 90 3991 #define Q_FULL_THRESH_HOLD(ha) \ 3992 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3993 3994 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3995 3996 struct qla_hw_data_stat { 3997 u32 num_fw_dump; 3998 u32 num_mpi_reset; 3999 }; 4000 4001 /* refer to pcie_do_recovery reference */ 4002 typedef enum { 4003 QLA_PCI_RESUME, 4004 QLA_PCI_ERR_DETECTED, 4005 QLA_PCI_MMIO_ENABLED, 4006 QLA_PCI_SLOT_RESET, 4007 } pci_error_state_t; 4008 /* 4009 * Qlogic host adapter specific data structure. 4010 */ 4011 struct qla_hw_data { 4012 struct pci_dev *pdev; 4013 /* SRB cache. */ 4014 #define SRB_MIN_REQ 128 4015 mempool_t *srb_mempool; 4016 u8 port_name[WWN_SIZE]; 4017 4018 volatile struct { 4019 uint32_t mbox_int :1; 4020 uint32_t mbox_busy :1; 4021 uint32_t disable_risc_code_load :1; 4022 uint32_t enable_64bit_addressing :1; 4023 uint32_t enable_lip_reset :1; 4024 uint32_t enable_target_reset :1; 4025 uint32_t enable_lip_full_login :1; 4026 uint32_t enable_led_scheme :1; 4027 4028 uint32_t msi_enabled :1; 4029 uint32_t msix_enabled :1; 4030 uint32_t disable_serdes :1; 4031 uint32_t gpsc_supported :1; 4032 uint32_t npiv_supported :1; 4033 uint32_t pci_channel_io_perm_failure :1; 4034 uint32_t fce_enabled :1; 4035 uint32_t fac_supported :1; 4036 4037 uint32_t chip_reset_done :1; 4038 uint32_t running_gold_fw :1; 4039 uint32_t eeh_busy :1; 4040 uint32_t disable_msix_handshake :1; 4041 uint32_t fcp_prio_enabled :1; 4042 uint32_t isp82xx_fw_hung:1; 4043 uint32_t nic_core_hung:1; 4044 4045 uint32_t quiesce_owner:1; 4046 uint32_t nic_core_reset_hdlr_active:1; 4047 uint32_t nic_core_reset_owner:1; 4048 uint32_t isp82xx_no_md_cap:1; 4049 uint32_t host_shutting_down:1; 4050 uint32_t idc_compl_status:1; 4051 uint32_t mr_reset_hdlr_active:1; 4052 uint32_t mr_intr_valid:1; 4053 4054 uint32_t dport_enabled:1; 4055 uint32_t fawwpn_enabled:1; 4056 uint32_t exlogins_enabled:1; 4057 uint32_t exchoffld_enabled:1; 4058 4059 uint32_t lip_ae:1; 4060 uint32_t n2n_ae:1; 4061 uint32_t fw_started:1; 4062 uint32_t fw_init_done:1; 4063 4064 uint32_t lr_detected:1; 4065 4066 uint32_t rida_fmt2:1; 4067 uint32_t purge_mbox:1; 4068 uint32_t n2n_bigger:1; 4069 uint32_t secure_adapter:1; 4070 uint32_t secure_fw:1; 4071 /* Supported by Adapter */ 4072 uint32_t scm_supported_a:1; 4073 /* Supported by Firmware */ 4074 uint32_t scm_supported_f:1; 4075 /* Enabled in Driver */ 4076 uint32_t scm_enabled:1; 4077 uint32_t edif_hw:1; 4078 uint32_t edif_enabled:1; 4079 uint32_t n2n_fw_acc_sec:1; 4080 uint32_t plogi_template_valid:1; 4081 uint32_t port_isolated:1; 4082 uint32_t eeh_flush:2; 4083 #define EEH_FLUSH_RDY 1 4084 #define EEH_FLUSH_DONE 2 4085 } flags; 4086 4087 uint16_t max_exchg; 4088 uint16_t lr_distance; /* 32G & above */ 4089 #define LR_DISTANCE_5K 1 4090 #define LR_DISTANCE_10K 0 4091 4092 /* This spinlock is used to protect "io transactions", you must 4093 * acquire it before doing any IO to the card, eg with RD_REG*() and 4094 * WRT_REG*() for the duration of your entire commandtransaction. 4095 * 4096 * This spinlock is of lower priority than the io request lock. 4097 */ 4098 4099 spinlock_t hardware_lock ____cacheline_aligned; 4100 int bars; 4101 int mem_only; 4102 device_reg_t *iobase; /* Base I/O address */ 4103 resource_size_t pio_address; 4104 4105 #define MIN_IOBASE_LEN 0x100 4106 dma_addr_t bar0_hdl; 4107 4108 void __iomem *cregbase; 4109 dma_addr_t bar2_hdl; 4110 #define BAR0_LEN_FX00 (1024 * 1024) 4111 #define BAR2_LEN_FX00 (128 * 1024) 4112 4113 uint32_t rqstq_intr_code; 4114 uint32_t mbx_intr_code; 4115 uint32_t req_que_len; 4116 uint32_t rsp_que_len; 4117 uint32_t req_que_off; 4118 uint32_t rsp_que_off; 4119 unsigned long eeh_jif; 4120 4121 /* Multi queue data structs */ 4122 device_reg_t *mqiobase; 4123 device_reg_t *msixbase; 4124 uint16_t msix_count; 4125 uint8_t mqenable; 4126 struct req_que **req_q_map; 4127 struct rsp_que **rsp_q_map; 4128 struct qla_qpair **queue_pair_map; 4129 struct qla_qpair **qp_cpu_map; 4130 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4131 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4132 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 4133 / sizeof(unsigned long)]; 4134 uint8_t max_req_queues; 4135 uint8_t max_rsp_queues; 4136 uint8_t max_qpairs; 4137 uint8_t num_qpairs; 4138 struct qla_qpair *base_qpair; 4139 struct qla_npiv_entry *npiv_info; 4140 uint16_t nvram_npiv_size; 4141 4142 uint16_t switch_cap; 4143 #define FLOGI_SEQ_DEL BIT_8 4144 #define FLOGI_MID_SUPPORT BIT_10 4145 #define FLOGI_VSAN_SUPPORT BIT_12 4146 #define FLOGI_SP_SUPPORT BIT_13 4147 4148 uint8_t port_no; /* Physical port of adapter */ 4149 uint8_t exch_starvation; 4150 4151 /* Timeout timers. */ 4152 uint8_t loop_down_abort_time; /* port down timer */ 4153 atomic_t loop_down_timer; /* loop down timer */ 4154 uint8_t link_down_timeout; /* link down timeout */ 4155 uint16_t max_loop_id; 4156 uint16_t max_fibre_devices; /* Maximum number of targets */ 4157 4158 uint16_t fb_rev; 4159 uint16_t min_external_loopid; /* First external loop Id */ 4160 4161 #define PORT_SPEED_UNKNOWN 0xFFFF 4162 #define PORT_SPEED_1GB 0x00 4163 #define PORT_SPEED_2GB 0x01 4164 #define PORT_SPEED_AUTO 0x02 4165 #define PORT_SPEED_4GB 0x03 4166 #define PORT_SPEED_8GB 0x04 4167 #define PORT_SPEED_16GB 0x05 4168 #define PORT_SPEED_32GB 0x06 4169 #define PORT_SPEED_64GB 0x07 4170 #define PORT_SPEED_10GB 0x13 4171 uint16_t link_data_rate; /* F/W operating speed */ 4172 uint16_t set_data_rate; /* Set by user */ 4173 4174 uint8_t current_topology; 4175 uint8_t prev_topology; 4176 #define ISP_CFG_NL 1 4177 #define ISP_CFG_N 2 4178 #define ISP_CFG_FL 4 4179 #define ISP_CFG_F 8 4180 4181 uint8_t operating_mode; /* F/W operating mode */ 4182 #define LOOP 0 4183 #define P2P 1 4184 #define LOOP_P2P 2 4185 #define P2P_LOOP 3 4186 uint8_t interrupts_on; 4187 uint32_t isp_abort_cnt; 4188 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 4189 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 4190 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 4191 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 4192 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 4193 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 4194 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 4195 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 4196 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061 4197 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081 4198 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089 4199 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281 4200 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289 4201 4202 uint32_t isp_type; 4203 #define DT_ISP2100 BIT_0 4204 #define DT_ISP2200 BIT_1 4205 #define DT_ISP2300 BIT_2 4206 #define DT_ISP2312 BIT_3 4207 #define DT_ISP2322 BIT_4 4208 #define DT_ISP6312 BIT_5 4209 #define DT_ISP6322 BIT_6 4210 #define DT_ISP2422 BIT_7 4211 #define DT_ISP2432 BIT_8 4212 #define DT_ISP5422 BIT_9 4213 #define DT_ISP5432 BIT_10 4214 #define DT_ISP2532 BIT_11 4215 #define DT_ISP8432 BIT_12 4216 #define DT_ISP8001 BIT_13 4217 #define DT_ISP8021 BIT_14 4218 #define DT_ISP2031 BIT_15 4219 #define DT_ISP8031 BIT_16 4220 #define DT_ISPFX00 BIT_17 4221 #define DT_ISP8044 BIT_18 4222 #define DT_ISP2071 BIT_19 4223 #define DT_ISP2271 BIT_20 4224 #define DT_ISP2261 BIT_21 4225 #define DT_ISP2061 BIT_22 4226 #define DT_ISP2081 BIT_23 4227 #define DT_ISP2089 BIT_24 4228 #define DT_ISP2281 BIT_25 4229 #define DT_ISP2289 BIT_26 4230 #define DT_ISP_LAST (DT_ISP2289 << 1) 4231 4232 uint32_t device_type; 4233 #define DT_T10_PI BIT_25 4234 #define DT_IIDMA BIT_26 4235 #define DT_FWI2 BIT_27 4236 #define DT_ZIO_SUPPORTED BIT_28 4237 #define DT_OEM_001 BIT_29 4238 #define DT_ISP2200A BIT_30 4239 #define DT_EXTENDED_IDS BIT_31 4240 4241 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 4242 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 4243 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 4244 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 4245 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 4246 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 4247 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 4248 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 4249 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 4250 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 4251 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 4252 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 4253 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 4254 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 4255 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 4256 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 4257 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 4258 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 4259 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 4260 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 4261 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 4262 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 4263 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 4264 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 4265 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081) 4266 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281) 4267 4268 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 4269 IS_QLA6312(ha) || IS_QLA6322(ha)) 4270 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 4271 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 4272 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 4273 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 4274 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 4275 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 4276 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha)) 4277 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 4278 IS_QLA84XX(ha)) 4279 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 4280 IS_QLA8031(ha) || IS_QLA8044(ha)) 4281 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 4282 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 4283 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 4284 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 4285 IS_QLA8044(ha) || IS_QLA27XX(ha) || \ 4286 IS_QLA28XX(ha)) 4287 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4288 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4289 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 4290 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4291 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4292 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4293 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4294 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 4295 4296 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 4297 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 4298 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 4299 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 4300 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 4301 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 4302 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 4303 #define IS_MQUE_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4304 IS_QLA28XX(ha)) 4305 #define IS_BIDI_CAPABLE(ha) \ 4306 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4307 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 4308 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 4309 ((ha)->fw_attributes_ext[0] & BIT_0)) 4310 #define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14) 4311 #define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS) 4312 #define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD) 4313 #define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp)) 4314 #define QLA_LS_ABTS_WAIT_ENABLED(_sp) \ 4315 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4316 #define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \ 4317 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4318 #define QLA_ABTS_WAIT_ENABLED(_sp) \ 4319 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4320 4321 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4322 IS_QLA28XX(ha)) 4323 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4324 IS_QLA28XX(ha)) 4325 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 4326 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4327 IS_QLA28XX(ha)) 4328 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 4329 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 4330 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4331 IS_QLA28XX(ha)) 4332 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 4333 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4334 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4335 IS_QLA28XX(ha)) 4336 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4337 IS_QLA28XX(ha)) 4338 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 4339 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4340 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 4341 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4342 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4343 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ 4344 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4345 4346 #define IS_ZIO_THRESHOLD_CAPABLE(ha) \ 4347 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\ 4348 (ha->zio_mode == QLA_ZIO_MODE_6)) 4349 4350 /* HBA serial number */ 4351 uint8_t serial0; 4352 uint8_t serial1; 4353 uint8_t serial2; 4354 4355 /* NVRAM configuration data */ 4356 #define MAX_NVRAM_SIZE 4096 4357 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2) 4358 uint16_t nvram_size; 4359 uint16_t nvram_base; 4360 void *nvram; 4361 uint16_t vpd_size; 4362 uint16_t vpd_base; 4363 void *vpd; 4364 4365 uint16_t loop_reset_delay; 4366 uint8_t retry_count; 4367 uint8_t login_timeout; 4368 uint16_t r_a_tov; 4369 int port_down_retry_count; 4370 uint8_t mbx_count; 4371 uint8_t aen_mbx_count; 4372 atomic_t num_pend_mbx_stage1; 4373 atomic_t num_pend_mbx_stage2; 4374 atomic_t num_pend_mbx_stage3; 4375 uint16_t frame_payload_size; 4376 4377 uint32_t login_retry_count; 4378 /* SNS command interfaces. */ 4379 ms_iocb_entry_t *ms_iocb; 4380 dma_addr_t ms_iocb_dma; 4381 struct ct_sns_pkt *ct_sns; 4382 dma_addr_t ct_sns_dma; 4383 /* SNS command interfaces for 2200. */ 4384 struct sns_cmd_pkt *sns_cmd; 4385 dma_addr_t sns_cmd_dma; 4386 4387 #define SFP_DEV_SIZE 512 4388 #define SFP_BLOCK_SIZE 64 4389 #define SFP_RTDI_LEN SFP_BLOCK_SIZE 4390 4391 void *sfp_data; 4392 dma_addr_t sfp_data_dma; 4393 4394 struct qla_flt_header *flt; 4395 dma_addr_t flt_dma; 4396 4397 #define XGMAC_DATA_SIZE 4096 4398 void *xgmac_data; 4399 dma_addr_t xgmac_data_dma; 4400 4401 #define DCBX_TLV_DATA_SIZE 4096 4402 void *dcbx_tlv; 4403 dma_addr_t dcbx_tlv_dma; 4404 4405 struct task_struct *dpc_thread; 4406 uint8_t dpc_active; /* DPC routine is active */ 4407 4408 dma_addr_t gid_list_dma; 4409 struct gid_list_info *gid_list; 4410 int gid_list_info_size; 4411 4412 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 4413 #define DMA_POOL_SIZE 256 4414 struct dma_pool *s_dma_pool; 4415 4416 dma_addr_t init_cb_dma; 4417 init_cb_t *init_cb; 4418 int init_cb_size; 4419 dma_addr_t ex_init_cb_dma; 4420 struct ex_init_cb_81xx *ex_init_cb; 4421 dma_addr_t sf_init_cb_dma; 4422 struct init_sf_cb *sf_init_cb; 4423 4424 void *scm_fpin_els_buff; 4425 uint64_t scm_fpin_els_buff_size; 4426 bool scm_fpin_valid; 4427 bool scm_fpin_payload_size; 4428 4429 void *async_pd; 4430 dma_addr_t async_pd_dma; 4431 4432 #define ENABLE_EXTENDED_LOGIN BIT_7 4433 4434 /* Extended Logins */ 4435 void *exlogin_buf; 4436 dma_addr_t exlogin_buf_dma; 4437 uint32_t exlogin_size; 4438 4439 #define ENABLE_EXCHANGE_OFFLD BIT_2 4440 4441 /* Exchange Offload */ 4442 void *exchoffld_buf; 4443 dma_addr_t exchoffld_buf_dma; 4444 int exchoffld_size; 4445 int exchoffld_count; 4446 4447 /* n2n */ 4448 struct fc_els_flogi plogi_els_payld; 4449 #define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4) 4450 4451 void *swl; 4452 4453 /* These are used by mailbox operations. */ 4454 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 4455 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 4456 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 4457 4458 mbx_cmd_t *mcp; 4459 struct mbx_cmd_32 *mcp32; 4460 4461 unsigned long mbx_cmd_flags; 4462 #define MBX_INTERRUPT 1 4463 #define MBX_INTR_WAIT 2 4464 #define MBX_UPDATE_FLASH_ACTIVE 3 4465 4466 struct mutex vport_lock; /* Virtual port synchronization */ 4467 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 4468 struct mutex mq_lock; /* multi-queue synchronization */ 4469 struct completion mbx_cmd_comp; /* Serialize mbx access */ 4470 struct completion mbx_intr_comp; /* Used for completion notification */ 4471 struct completion dcbx_comp; /* For set port config notification */ 4472 struct completion lb_portup_comp; /* Used to wait for link up during 4473 * loopback */ 4474 #define DCBX_COMP_TIMEOUT 20 4475 #define LB_PORTUP_COMP_TIMEOUT 10 4476 4477 int notify_dcbx_comp; 4478 int notify_lb_portup_comp; 4479 struct mutex selflogin_lock; 4480 4481 /* Basic firmware related information. */ 4482 uint16_t fw_major_version; 4483 uint16_t fw_minor_version; 4484 uint16_t fw_subminor_version; 4485 uint16_t fw_attributes; 4486 uint16_t fw_attributes_h; 4487 #define FW_ATTR_H_NVME_FBURST BIT_1 4488 #define FW_ATTR_H_NVME BIT_10 4489 #define FW_ATTR_H_NVME_UPDATED BIT_14 4490 4491 /* About firmware SCM support */ 4492 #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12 4493 /* Brocade fabric attached */ 4494 #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000 4495 /* Cisco fabric attached */ 4496 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000 4497 #define FW_ATTR_EXT0_NVME2 BIT_13 4498 #define FW_ATTR_EXT0_EDIF BIT_5 4499 uint16_t fw_attributes_ext[2]; 4500 uint32_t fw_memory_size; 4501 uint32_t fw_transfer_size; 4502 uint32_t fw_srisc_address; 4503 #define RISC_START_ADDRESS_2100 0x1000 4504 #define RISC_START_ADDRESS_2300 0x800 4505 #define RISC_START_ADDRESS_2400 0x100000 4506 4507 uint16_t orig_fw_tgt_xcb_count; 4508 uint16_t cur_fw_tgt_xcb_count; 4509 uint16_t orig_fw_xcb_count; 4510 uint16_t cur_fw_xcb_count; 4511 uint16_t orig_fw_iocb_count; 4512 uint16_t cur_fw_iocb_count; 4513 uint16_t fw_max_fcf_count; 4514 4515 uint32_t fw_shared_ram_start; 4516 uint32_t fw_shared_ram_end; 4517 uint32_t fw_ddr_ram_start; 4518 uint32_t fw_ddr_ram_end; 4519 4520 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 4521 uint8_t fw_seriallink_options[4]; 4522 __le16 fw_seriallink_options24[4]; 4523 4524 uint8_t serdes_version[3]; 4525 uint8_t mpi_version[3]; 4526 uint32_t mpi_capabilities; 4527 uint8_t phy_version[3]; 4528 uint8_t pep_version[3]; 4529 4530 /* Firmware dump template */ 4531 struct fwdt { 4532 void *template; 4533 ulong length; 4534 ulong dump_size; 4535 } fwdt[2]; 4536 struct qla2xxx_fw_dump *fw_dump; 4537 uint32_t fw_dump_len; 4538 u32 fw_dump_alloc_len; 4539 bool fw_dumped; 4540 unsigned long fw_dump_cap_flags; 4541 #define RISC_PAUSE_CMPL 0 4542 #define DMA_SHUTDOWN_CMPL 1 4543 #define ISP_RESET_CMPL 2 4544 #define RISC_RDY_AFT_RESET 3 4545 #define RISC_SRAM_DUMP_CMPL 4 4546 #define RISC_EXT_MEM_DUMP_CMPL 5 4547 #define ISP_MBX_RDY 6 4548 #define ISP_SOFT_RESET_CMPL 7 4549 int fw_dump_reading; 4550 void *mpi_fw_dump; 4551 u32 mpi_fw_dump_len; 4552 unsigned int mpi_fw_dump_reading:1; 4553 unsigned int mpi_fw_dumped:1; 4554 int prev_minidump_failed; 4555 dma_addr_t eft_dma; 4556 void *eft; 4557 /* Current size of mctp dump is 0x086064 bytes */ 4558 #define MCTP_DUMP_SIZE 0x086064 4559 dma_addr_t mctp_dump_dma; 4560 void *mctp_dump; 4561 int mctp_dumped; 4562 int mctp_dump_reading; 4563 uint32_t chain_offset; 4564 struct dentry *dfs_dir; 4565 struct dentry *dfs_fce; 4566 struct dentry *dfs_tgt_counters; 4567 struct dentry *dfs_fw_resource_cnt; 4568 4569 dma_addr_t fce_dma; 4570 void *fce; 4571 uint32_t fce_bufs; 4572 uint16_t fce_mb[8]; 4573 uint64_t fce_wr, fce_rd; 4574 struct mutex fce_mutex; 4575 4576 uint32_t pci_attr; 4577 uint16_t chip_revision; 4578 4579 uint16_t product_id[4]; 4580 4581 uint8_t model_number[16+1]; 4582 char model_desc[80]; 4583 uint8_t adapter_id[16+1]; 4584 4585 /* Option ROM information. */ 4586 char *optrom_buffer; 4587 uint32_t optrom_size; 4588 int optrom_state; 4589 #define QLA_SWAITING 0 4590 #define QLA_SREADING 1 4591 #define QLA_SWRITING 2 4592 uint32_t optrom_region_start; 4593 uint32_t optrom_region_size; 4594 struct mutex optrom_mutex; 4595 4596 /* PCI expansion ROM image information. */ 4597 #define ROM_CODE_TYPE_BIOS 0 4598 #define ROM_CODE_TYPE_FCODE 1 4599 #define ROM_CODE_TYPE_EFI 3 4600 uint8_t bios_revision[2]; 4601 uint8_t efi_revision[2]; 4602 uint8_t fcode_revision[16]; 4603 uint32_t fw_revision[4]; 4604 4605 uint32_t gold_fw_version[4]; 4606 4607 /* Offsets for flash/nvram access (set to ~0 if not used). */ 4608 uint32_t flash_conf_off; 4609 uint32_t flash_data_off; 4610 uint32_t nvram_conf_off; 4611 uint32_t nvram_data_off; 4612 4613 uint32_t fdt_wrt_disable; 4614 uint32_t fdt_wrt_enable; 4615 uint32_t fdt_erase_cmd; 4616 uint32_t fdt_block_size; 4617 uint32_t fdt_unprotect_sec_cmd; 4618 uint32_t fdt_protect_sec_cmd; 4619 uint32_t fdt_wrt_sts_reg_cmd; 4620 4621 struct { 4622 uint32_t flt_region_flt; 4623 uint32_t flt_region_fdt; 4624 uint32_t flt_region_boot; 4625 uint32_t flt_region_boot_sec; 4626 uint32_t flt_region_fw; 4627 uint32_t flt_region_fw_sec; 4628 uint32_t flt_region_vpd_nvram; 4629 uint32_t flt_region_vpd_nvram_sec; 4630 uint32_t flt_region_vpd; 4631 uint32_t flt_region_vpd_sec; 4632 uint32_t flt_region_nvram; 4633 uint32_t flt_region_nvram_sec; 4634 uint32_t flt_region_npiv_conf; 4635 uint32_t flt_region_gold_fw; 4636 uint32_t flt_region_fcp_prio; 4637 uint32_t flt_region_bootload; 4638 uint32_t flt_region_img_status_pri; 4639 uint32_t flt_region_img_status_sec; 4640 uint32_t flt_region_aux_img_status_pri; 4641 uint32_t flt_region_aux_img_status_sec; 4642 }; 4643 uint8_t active_image; 4644 4645 /* Needed for BEACON */ 4646 uint16_t beacon_blink_led; 4647 uint8_t beacon_color_state; 4648 #define QLA_LED_GRN_ON 0x01 4649 #define QLA_LED_YLW_ON 0x02 4650 #define QLA_LED_ABR_ON 0x04 4651 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 4652 /* ISP2322: red, green, amber. */ 4653 uint16_t zio_mode; 4654 uint16_t zio_timer; 4655 4656 struct qla_msix_entry *msix_entries; 4657 4658 struct list_head vp_list; /* list of VP */ 4659 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 4660 sizeof(unsigned long)]; 4661 uint16_t num_vhosts; /* number of vports created */ 4662 uint16_t num_vsans; /* number of vsan created */ 4663 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 4664 int cur_vport_count; 4665 4666 struct qla_chip_state_84xx *cs84xx; 4667 struct isp_operations *isp_ops; 4668 struct workqueue_struct *wq; 4669 struct work_struct heartbeat_work; 4670 struct qlfc_fw fw_buf; 4671 unsigned long last_heartbeat_run_jiffies; 4672 4673 /* FCP_CMND priority support */ 4674 struct qla_fcp_prio_cfg *fcp_prio_cfg; 4675 4676 struct dma_pool *dl_dma_pool; 4677 #define DSD_LIST_DMA_POOL_SIZE 512 4678 4679 struct dma_pool *fcp_cmnd_dma_pool; 4680 mempool_t *ctx_mempool; 4681 #define FCP_CMND_DMA_POOL_SIZE 512 4682 4683 void __iomem *nx_pcibase; /* Base I/O address */ 4684 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4685 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4686 4687 uint32_t crb_win; 4688 uint32_t curr_window; 4689 uint32_t ddr_mn_window; 4690 unsigned long mn_win_crb; 4691 unsigned long ms_win_crb; 4692 int qdr_sn_window; 4693 uint32_t fcoe_dev_init_timeout; 4694 uint32_t fcoe_reset_timeout; 4695 rwlock_t hw_lock; 4696 uint16_t portnum; /* port number */ 4697 int link_width; 4698 struct fw_blob *hablob; 4699 struct qla82xx_legacy_intr_set nx_legacy_intr; 4700 4701 uint16_t gbl_dsd_inuse; 4702 uint16_t gbl_dsd_avail; 4703 struct list_head gbl_dsd_list; 4704 #define NUM_DSD_CHAIN 4096 4705 4706 uint8_t fw_type; 4707 uint32_t file_prd_off; /* File firmware product offset */ 4708 4709 uint32_t md_template_size; 4710 void *md_tmplt_hdr; 4711 dma_addr_t md_tmplt_hdr_dma; 4712 void *md_dump; 4713 uint32_t md_dump_size; 4714 4715 void *loop_id_map; 4716 4717 /* QLA83XX IDC specific fields */ 4718 uint32_t idc_audit_ts; 4719 uint32_t idc_extend_tmo; 4720 4721 /* DPC low-priority workqueue */ 4722 struct workqueue_struct *dpc_lp_wq; 4723 struct work_struct idc_aen; 4724 /* DPC high-priority workqueue */ 4725 struct workqueue_struct *dpc_hp_wq; 4726 struct work_struct nic_core_reset; 4727 struct work_struct idc_state_handler; 4728 struct work_struct nic_core_unrecoverable; 4729 struct work_struct board_disable; 4730 4731 struct mr_data_fx00 mr; 4732 uint32_t chip_reset; 4733 4734 struct qlt_hw_data tgt; 4735 int allow_cna_fw_dump; 4736 uint32_t fw_ability_mask; 4737 uint16_t min_supported_speed; 4738 uint16_t max_supported_speed; 4739 4740 /* DMA pool for the DIF bundling buffers */ 4741 struct dma_pool *dif_bundl_pool; 4742 #define DIF_BUNDLING_DMA_POOL_SIZE 1024 4743 struct { 4744 struct { 4745 struct list_head head; 4746 uint count; 4747 } good; 4748 struct { 4749 struct list_head head; 4750 uint count; 4751 } unusable; 4752 } pool; 4753 4754 unsigned long long dif_bundle_crossed_pages; 4755 unsigned long long dif_bundle_reads; 4756 unsigned long long dif_bundle_writes; 4757 unsigned long long dif_bundle_kallocs; 4758 unsigned long long dif_bundle_dma_allocs; 4759 4760 atomic_t nvme_active_aen_cnt; 4761 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4762 4763 uint8_t fc4_type_priority; 4764 4765 atomic_t zio_threshold; 4766 uint16_t last_zio_threshold; 4767 4768 #define DEFAULT_ZIO_THRESHOLD 5 4769 4770 struct qla_hw_data_stat stat; 4771 pci_error_state_t pci_error_state; 4772 struct dma_pool *purex_dma_pool; 4773 struct btree_head32 host_map; 4774 4775 #define EDIF_NUM_SA_INDEX 512 4776 #define EDIF_TX_SA_INDEX_BASE EDIF_NUM_SA_INDEX 4777 void *edif_rx_sa_id_map; 4778 void *edif_tx_sa_id_map; 4779 spinlock_t sadb_fp_lock; 4780 4781 struct list_head sadb_tx_index_list; 4782 struct list_head sadb_rx_index_list; 4783 spinlock_t sadb_lock; /* protects list */ 4784 struct els_reject elsrej; 4785 u8 edif_post_stop_cnt_down; 4786 struct qla_vp_map *vp_map; 4787 }; 4788 4789 #define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES)) 4790 4791 struct active_regions { 4792 uint8_t global; 4793 struct { 4794 uint8_t board_config; 4795 uint8_t vpd_nvram; 4796 uint8_t npiv_config_0_1; 4797 uint8_t npiv_config_2_3; 4798 uint8_t nvme_params; 4799 } aux; 4800 }; 4801 4802 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4803 #define FW_ABILITY_MAX_SPEED_16G 0x0 4804 #define FW_ABILITY_MAX_SPEED_32G 0x1 4805 #define FW_ABILITY_MAX_SPEED(ha) \ 4806 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4807 4808 #define QLA_GET_DATA_RATE 0 4809 #define QLA_SET_DATA_RATE_NOLR 1 4810 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */ 4811 4812 #define QLA_DEFAULT_PAYLOAD_SIZE 64 4813 /* 4814 * This item might be allocated with a size > sizeof(struct purex_item). 4815 * The "size" variable gives the size of the payload (which 4816 * is variable) starting at "iocb". 4817 */ 4818 struct purex_item { 4819 struct list_head list; 4820 struct scsi_qla_host *vha; 4821 void (*process_item)(struct scsi_qla_host *vha, 4822 struct purex_item *pkt); 4823 atomic_t in_use; 4824 uint16_t size; 4825 struct { 4826 uint8_t iocb[64]; 4827 } iocb; 4828 }; 4829 4830 #include "qla_edif.h" 4831 4832 #define SCM_FLAG_RDF_REJECT 0x00 4833 #define SCM_FLAG_RDF_COMPLETED 0x01 4834 4835 #define QLA_CON_PRIMITIVE_RECEIVED 0x1 4836 #define QLA_CONGESTION_ARB_WARNING 0x1 4837 #define QLA_CONGESTION_ARB_ALARM 0X2 4838 4839 /* 4840 * Qlogic scsi host structure 4841 */ 4842 typedef struct scsi_qla_host { 4843 struct list_head list; 4844 struct list_head vp_fcports; /* list of fcports */ 4845 struct list_head work_list; 4846 spinlock_t work_lock; 4847 struct work_struct iocb_work; 4848 4849 /* Commonly used flags and state information. */ 4850 struct Scsi_Host *host; 4851 unsigned long host_no; 4852 uint8_t host_str[16]; 4853 4854 volatile struct { 4855 uint32_t init_done :1; 4856 uint32_t online :1; 4857 uint32_t reset_active :1; 4858 4859 uint32_t management_server_logged_in :1; 4860 uint32_t process_response_queue :1; 4861 uint32_t difdix_supported:1; 4862 uint32_t delete_progress:1; 4863 4864 uint32_t fw_tgt_reported:1; 4865 uint32_t bbcr_enable:1; 4866 uint32_t qpairs_available:1; 4867 uint32_t qpairs_req_created:1; 4868 uint32_t qpairs_rsp_created:1; 4869 uint32_t nvme_enabled:1; 4870 uint32_t nvme_first_burst:1; 4871 uint32_t nvme2_enabled:1; 4872 } flags; 4873 4874 atomic_t loop_state; 4875 #define LOOP_TIMEOUT 1 4876 #define LOOP_DOWN 2 4877 #define LOOP_UP 3 4878 #define LOOP_UPDATE 4 4879 #define LOOP_READY 5 4880 #define LOOP_DEAD 6 4881 4882 unsigned long buf_expired; 4883 unsigned long relogin_jif; 4884 unsigned long dpc_flags; 4885 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4886 #define RESET_ACTIVE 1 4887 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4888 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4889 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4890 #define LOOP_RESYNC_ACTIVE 5 4891 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4892 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4893 #define RELOGIN_NEEDED 8 4894 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4895 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4896 #define BEACON_BLINK_NEEDED 11 4897 #define REGISTER_FDMI_NEEDED 12 4898 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4899 #define UNLOADING 15 4900 #define NPIV_CONFIG_NEEDED 16 4901 #define ISP_UNRECOVERABLE 17 4902 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4903 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4904 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4905 #define N2N_LINK_RESET 21 4906 #define PORT_UPDATE_NEEDED 22 4907 #define FX00_RESET_RECOVERY 23 4908 #define FX00_TARGET_SCAN 24 4909 #define FX00_CRITEMP_RECOVERY 25 4910 #define FX00_HOST_INFO_RESEND 26 4911 #define QPAIR_ONLINE_CHECK_NEEDED 27 4912 #define DO_EEH_RECOVERY 28 4913 #define DETECT_SFP_CHANGE 29 4914 #define N2N_LOGIN_NEEDED 30 4915 #define IOCB_WORK_ACTIVE 31 4916 #define SET_ZIO_THRESHOLD_NEEDED 32 4917 #define ISP_ABORT_TO_ROM 33 4918 #define VPORT_DELETE 34 4919 4920 #define PROCESS_PUREX_IOCB 63 4921 4922 unsigned long pci_flags; 4923 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4924 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4925 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4926 4927 uint32_t device_flags; 4928 #define SWITCH_FOUND BIT_0 4929 #define DFLG_NO_CABLE BIT_1 4930 #define DFLG_DEV_FAILED BIT_5 4931 4932 /* ISP configuration data. */ 4933 uint16_t loop_id; /* Host adapter loop id */ 4934 uint16_t self_login_loop_id; /* host adapter loop id 4935 * get it on self login 4936 */ 4937 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4938 * no need of allocating it for 4939 * each command 4940 */ 4941 4942 port_id_t d_id; /* Host adapter port id */ 4943 uint8_t marker_needed; 4944 uint16_t mgmt_svr_loop_id; 4945 4946 4947 4948 /* Timeout timers. */ 4949 uint8_t loop_down_abort_time; /* port down timer */ 4950 atomic_t loop_down_timer; /* loop down timer */ 4951 uint8_t link_down_timeout; /* link down timeout */ 4952 4953 uint32_t timer_active; 4954 struct timer_list timer; 4955 4956 uint8_t node_name[WWN_SIZE]; 4957 uint8_t port_name[WWN_SIZE]; 4958 uint8_t fabric_node_name[WWN_SIZE]; 4959 uint8_t fabric_port_name[WWN_SIZE]; 4960 4961 struct nvme_fc_local_port *nvme_local_port; 4962 struct completion nvme_del_done; 4963 4964 uint16_t fcoe_vlan_id; 4965 uint16_t fcoe_fcf_idx; 4966 uint8_t fcoe_vn_port_mac[6]; 4967 4968 /* list of commands waiting on workqueue */ 4969 struct list_head qla_cmd_list; 4970 struct list_head unknown_atio_list; 4971 spinlock_t cmd_list_lock; 4972 struct delayed_work unknown_atio_work; 4973 4974 /* Counter to detect races between ELS and RSCN events */ 4975 atomic_t generation_tick; 4976 /* Time when global fcport update has been scheduled */ 4977 int total_fcport_update_gen; 4978 /* List of pending LOGOs, protected by tgt_mutex */ 4979 struct list_head logo_list; 4980 /* List of pending PLOGI acks, protected by hw lock */ 4981 struct list_head plogi_ack_list; 4982 4983 struct list_head qp_list; 4984 4985 uint32_t vp_abort_cnt; 4986 4987 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4988 uint16_t vp_idx; /* vport ID */ 4989 struct qla_qpair *qpair; /* base qpair */ 4990 4991 unsigned long vp_flags; 4992 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4993 #define VP_CREATE_NEEDED 1 4994 #define VP_BIND_NEEDED 2 4995 #define VP_DELETE_NEEDED 3 4996 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4997 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4998 atomic_t vp_state; 4999 #define VP_OFFLINE 0 5000 #define VP_ACTIVE 1 5001 #define VP_FAILED 2 5002 // #define VP_DISABLE 3 5003 uint16_t vp_err_state; 5004 uint16_t vp_prev_err_state; 5005 #define VP_ERR_UNKWN 0 5006 #define VP_ERR_PORTDWN 1 5007 #define VP_ERR_FAB_UNSUPPORTED 2 5008 #define VP_ERR_FAB_NORESOURCES 3 5009 #define VP_ERR_FAB_LOGOUT 4 5010 #define VP_ERR_ADAP_NORESOURCES 5 5011 struct qla_hw_data *hw; 5012 struct scsi_qlt_host vha_tgt; 5013 struct req_que *req; 5014 int fw_heartbeat_counter; 5015 int seconds_since_last_heartbeat; 5016 struct fc_host_statistics fc_host_stat; 5017 struct qla_statistics qla_stats; 5018 struct bidi_statistics bidi_stats; 5019 atomic_t vref_count; 5020 struct qla8044_reset_template reset_tmplt; 5021 uint16_t bbcr; 5022 5023 uint16_t u_ql2xexchoffld; 5024 uint16_t u_ql2xiniexchg; 5025 uint16_t qlini_mode; 5026 uint16_t ql2xexchoffld; 5027 uint16_t ql2xiniexchg; 5028 5029 struct dentry *dfs_rport_root; 5030 5031 struct purex_list { 5032 struct list_head head; 5033 spinlock_t lock; 5034 } purex_list; 5035 struct purex_item default_item; 5036 5037 struct name_list_extended gnl; 5038 /* Count of active session/fcport */ 5039 int fcport_count; 5040 wait_queue_head_t fcport_waitQ; 5041 wait_queue_head_t vref_waitq; 5042 uint8_t min_supported_speed; 5043 uint8_t n2n_node_name[WWN_SIZE]; 5044 uint8_t n2n_port_name[WWN_SIZE]; 5045 uint16_t n2n_id; 5046 __le16 dport_data[4]; 5047 struct fab_scan scan; 5048 uint8_t scm_fabric_connection_flags; 5049 5050 unsigned int irq_offset; 5051 5052 u64 hw_err_cnt; 5053 u64 interface_err_cnt; 5054 u64 cmd_timeout_cnt; 5055 u64 reset_cmd_err_cnt; 5056 u64 link_down_time; 5057 u64 short_link_down_cnt; 5058 struct edif_dbell e_dbell; 5059 struct pur_core pur_cinfo; 5060 5061 #define DPORT_DIAG_IN_PROGRESS BIT_0 5062 #define DPORT_DIAG_CHIP_RESET_IN_PROGRESS BIT_1 5063 uint16_t dport_status; 5064 } scsi_qla_host_t; 5065 5066 struct qla27xx_image_status { 5067 uint8_t image_status_mask; 5068 __le16 generation; 5069 uint8_t ver_major; 5070 uint8_t ver_minor; 5071 uint8_t bitmap; /* 28xx only */ 5072 uint8_t reserved[2]; 5073 __le32 checksum; 5074 __le32 signature; 5075 } __packed; 5076 5077 /* 28xx aux image status bimap values */ 5078 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0 5079 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1 5080 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2 5081 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3 5082 #define QLA28XX_AUX_IMG_NVME_PARAMS BIT_4 5083 5084 #define SET_VP_IDX 1 5085 #define SET_AL_PA 2 5086 #define RESET_VP_IDX 3 5087 #define RESET_AL_PA 4 5088 struct qla_vp_map { 5089 uint8_t idx; 5090 scsi_qla_host_t *vha; 5091 }; 5092 5093 struct qla2_sgx { 5094 dma_addr_t dma_addr; /* OUT */ 5095 uint32_t dma_len; /* OUT */ 5096 5097 uint32_t tot_bytes; /* IN */ 5098 struct scatterlist *cur_sg; /* IN */ 5099 5100 /* for book keeping, bzero on initial invocation */ 5101 uint32_t bytes_consumed; 5102 uint32_t num_bytes; 5103 uint32_t tot_partial; 5104 5105 /* for debugging */ 5106 uint32_t num_sg; 5107 srb_t *sp; 5108 }; 5109 5110 #define QLA_FW_STARTED(_ha) { \ 5111 int i; \ 5112 _ha->flags.fw_started = 1; \ 5113 _ha->base_qpair->fw_started = 1; \ 5114 for (i = 0; i < _ha->max_qpairs; i++) { \ 5115 if (_ha->queue_pair_map[i]) \ 5116 _ha->queue_pair_map[i]->fw_started = 1; \ 5117 } \ 5118 } 5119 5120 #define QLA_FW_STOPPED(_ha) { \ 5121 int i; \ 5122 _ha->flags.fw_started = 0; \ 5123 _ha->base_qpair->fw_started = 0; \ 5124 for (i = 0; i < _ha->max_qpairs; i++) { \ 5125 if (_ha->queue_pair_map[i]) \ 5126 _ha->queue_pair_map[i]->fw_started = 0; \ 5127 } \ 5128 } 5129 5130 5131 #define SFUB_CHECKSUM_SIZE 4 5132 5133 struct secure_flash_update_block { 5134 uint32_t block_info; 5135 uint32_t signature_lo; 5136 uint32_t signature_hi; 5137 uint32_t signature_upper[0x3e]; 5138 }; 5139 5140 struct secure_flash_update_block_pk { 5141 uint32_t block_info; 5142 uint32_t signature_lo; 5143 uint32_t signature_hi; 5144 uint32_t signature_upper[0x3e]; 5145 uint32_t public_key[0x41]; 5146 }; 5147 5148 /* 5149 * Macros to help code, maintain, etc. 5150 */ 5151 #define LOOP_TRANSITION(ha) \ 5152 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5153 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 5154 atomic_read(&ha->loop_state) == LOOP_DOWN) 5155 5156 #define STATE_TRANSITION(ha) \ 5157 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5158 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 5159 5160 static inline bool qla_vha_mark_busy(scsi_qla_host_t *vha) 5161 { 5162 atomic_inc(&vha->vref_count); 5163 mb(); 5164 if (vha->flags.delete_progress) { 5165 atomic_dec(&vha->vref_count); 5166 wake_up(&vha->vref_waitq); 5167 return true; 5168 } 5169 return false; 5170 } 5171 5172 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 5173 atomic_dec(&__vha->vref_count); \ 5174 wake_up(&__vha->vref_waitq); \ 5175 } while (0) \ 5176 5177 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 5178 atomic_inc(&__qpair->ref_count); \ 5179 mb(); \ 5180 if (__qpair->delete_in_progress) { \ 5181 atomic_dec(&__qpair->ref_count); \ 5182 __bail = 1; \ 5183 } else { \ 5184 __bail = 0; \ 5185 } \ 5186 } while (0) 5187 5188 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 5189 atomic_dec(&__qpair->ref_count) 5190 5191 #define QLA_ENA_CONF(_ha) {\ 5192 int i;\ 5193 _ha->base_qpair->enable_explicit_conf = 1; \ 5194 for (i = 0; i < _ha->max_qpairs; i++) { \ 5195 if (_ha->queue_pair_map[i]) \ 5196 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 5197 } \ 5198 } 5199 5200 #define QLA_DIS_CONF(_ha) {\ 5201 int i;\ 5202 _ha->base_qpair->enable_explicit_conf = 0; \ 5203 for (i = 0; i < _ha->max_qpairs; i++) { \ 5204 if (_ha->queue_pair_map[i]) \ 5205 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 5206 } \ 5207 } 5208 5209 /* 5210 * qla2x00 local function return status codes 5211 */ 5212 #define MBS_MASK 0x3fff 5213 5214 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 5215 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 5216 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 5217 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 5218 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 5219 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 5220 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 5221 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 5222 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 5223 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 5224 5225 #define QLA_FUNCTION_TIMEOUT 0x100 5226 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 5227 #define QLA_FUNCTION_FAILED 0x102 5228 #define QLA_MEMORY_ALLOC_FAILED 0x103 5229 #define QLA_LOCK_TIMEOUT 0x104 5230 #define QLA_ABORTED 0x105 5231 #define QLA_SUSPENDED 0x106 5232 #define QLA_BUSY 0x107 5233 #define QLA_ALREADY_REGISTERED 0x109 5234 #define QLA_OS_TIMER_EXPIRED 0x10a 5235 #define QLA_ERR_NO_QPAIR 0x10b 5236 #define QLA_ERR_NOT_FOUND 0x10c 5237 #define QLA_ERR_FROM_FW 0x10d 5238 5239 #define NVRAM_DELAY() udelay(10) 5240 5241 /* 5242 * Flash support definitions 5243 */ 5244 #define OPTROM_SIZE_2300 0x20000 5245 #define OPTROM_SIZE_2322 0x100000 5246 #define OPTROM_SIZE_24XX 0x100000 5247 #define OPTROM_SIZE_25XX 0x200000 5248 #define OPTROM_SIZE_81XX 0x400000 5249 #define OPTROM_SIZE_82XX 0x800000 5250 #define OPTROM_SIZE_83XX 0x1000000 5251 #define OPTROM_SIZE_28XX 0x2000000 5252 5253 #define OPTROM_BURST_SIZE 0x1000 5254 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 5255 5256 #define QLA_DSDS_PER_IOCB 37 5257 5258 #define QLA_SG_ALL 1024 5259 5260 enum nexus_wait_type { 5261 WAIT_HOST = 0, 5262 WAIT_TARGET, 5263 WAIT_LUN, 5264 }; 5265 5266 #define INVALID_EDIF_SA_INDEX 0xffff 5267 #define RX_DELETE_NO_EDIF_SA_INDEX 0xfffe 5268 5269 #define QLA_SKIP_HANDLE QLA_TGT_SKIP_HANDLE 5270 5271 /* edif hash element */ 5272 struct edif_list_entry { 5273 uint16_t handle; /* nport_handle */ 5274 uint32_t update_sa_index; 5275 uint32_t delete_sa_index; 5276 uint32_t count; /* counter for filtering sa_index */ 5277 #define EDIF_ENTRY_FLAGS_CLEANUP 0x01 /* this index is being cleaned up */ 5278 uint32_t flags; /* used by sadb cleanup code */ 5279 fc_port_t *fcport; /* needed by rx delay timer function */ 5280 struct timer_list timer; /* rx delay timer */ 5281 struct list_head next; 5282 }; 5283 5284 #define EDIF_TX_INDX_BASE 512 5285 #define EDIF_RX_INDX_BASE 0 5286 #define EDIF_RX_DELETE_FILTER_COUNT 3 /* delay queuing rx delete until this many */ 5287 5288 /* entry in the sa_index free pool */ 5289 5290 struct sa_index_pair { 5291 uint16_t sa_index; 5292 uint32_t spi; 5293 }; 5294 5295 /* edif sa_index data structure */ 5296 struct edif_sa_index_entry { 5297 struct sa_index_pair sa_pair[2]; 5298 fc_port_t *fcport; 5299 uint16_t handle; 5300 struct list_head next; 5301 }; 5302 5303 /* Refer to SNIA SFF 8247 */ 5304 struct sff_8247_a0 { 5305 u8 txid; /* transceiver id */ 5306 u8 ext_txid; 5307 u8 connector; 5308 /* compliance code */ 5309 u8 eth_infi_cc3; /* ethernet, inifiband */ 5310 u8 sonet_cc4[2]; 5311 u8 eth_cc6; 5312 /* link length */ 5313 #define FC_LL_VL BIT_7 /* very long */ 5314 #define FC_LL_S BIT_6 /* Short */ 5315 #define FC_LL_I BIT_5 /* Intermidiate*/ 5316 #define FC_LL_L BIT_4 /* Long */ 5317 #define FC_LL_M BIT_3 /* Medium */ 5318 #define FC_LL_SA BIT_2 /* ShortWave laser */ 5319 #define FC_LL_LC BIT_1 /* LongWave laser */ 5320 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 5321 u8 fc_ll_cc7; 5322 /* FC technology */ 5323 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 5324 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 5325 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 5326 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 5327 #define FC_TEC_ACT BIT_3 /* Active cable */ 5328 #define FC_TEC_PAS BIT_2 /* Passive cable */ 5329 u8 fc_tec_cc8; 5330 /* Transmission Media */ 5331 #define FC_MED_TW BIT_7 /* Twin Ax */ 5332 #define FC_MED_TP BIT_6 /* Twited Pair */ 5333 #define FC_MED_MI BIT_5 /* Min Coax */ 5334 #define FC_MED_TV BIT_4 /* Video Coax */ 5335 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 5336 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 5337 #define FC_MED_SM BIT_0 /* Single Mode */ 5338 u8 fc_med_cc9; 5339 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 5340 #define FC_SP_12 BIT_7 5341 #define FC_SP_8 BIT_6 5342 #define FC_SP_16 BIT_5 5343 #define FC_SP_4 BIT_4 5344 #define FC_SP_32 BIT_3 5345 #define FC_SP_2 BIT_2 5346 #define FC_SP_1 BIT_0 5347 u8 fc_sp_cc10; 5348 u8 encode; 5349 u8 bitrate; 5350 u8 rate_id; 5351 u8 length_km; /* offset 14/eh */ 5352 u8 length_100m; 5353 u8 length_50um_10m; 5354 u8 length_62um_10m; 5355 u8 length_om4_10m; 5356 u8 length_om3_10m; 5357 #define SFF_VEN_NAME_LEN 16 5358 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 5359 u8 tx_compat; 5360 u8 vendor_oui[3]; 5361 #define SFF_PART_NAME_LEN 16 5362 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 5363 u8 vendor_rev[4]; 5364 u8 wavelength[2]; 5365 u8 resv; 5366 u8 cc_base; 5367 u8 options[2]; /* offset 64 */ 5368 u8 br_max; 5369 u8 br_min; 5370 u8 vendor_sn[16]; 5371 u8 date_code[8]; 5372 u8 diag; 5373 u8 enh_options; 5374 u8 sff_revision; 5375 u8 cc_ext; 5376 u8 vendor_specific[32]; 5377 u8 resv2[128]; 5378 }; 5379 5380 /* BPM -- Buffer Plus Management support. */ 5381 #define IS_BPM_CAPABLE(ha) \ 5382 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 5383 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5384 #define IS_BPM_RANGE_CAPABLE(ha) \ 5385 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5386 #define IS_BPM_ENABLED(vha) \ 5387 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw)) 5388 5389 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016 5390 5391 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 5392 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha))) 5393 5394 #define SAVE_TOPO(_ha) { \ 5395 if (_ha->current_topology) \ 5396 _ha->prev_topology = _ha->current_topology; \ 5397 } 5398 5399 #define N2N_TOPO(ha) \ 5400 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ 5401 ha->current_topology == ISP_CFG_N || \ 5402 !ha->current_topology) 5403 5404 #define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */ 5405 5406 #define NVME_TYPE(fcport) \ 5407 (fcport->fc4_type & FS_FC4TYPE_NVME) \ 5408 5409 #define FCP_TYPE(fcport) \ 5410 (fcport->fc4_type & FS_FC4TYPE_FCP) \ 5411 5412 #define NVME_ONLY_TARGET(fcport) \ 5413 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \ 5414 5415 #define NVME_FCP_TARGET(fcport) \ 5416 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \ 5417 5418 #define NVME_PRIORITY(ha, fcport) \ 5419 (NVME_FCP_TARGET(fcport) && \ 5420 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) 5421 5422 #define NVME_TARGET(ha, fcport) \ 5423 (fcport->do_prli_nvme || \ 5424 NVME_ONLY_TARGET(fcport)) \ 5425 5426 #define PRLI_PHASE(_cls) \ 5427 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP)) 5428 5429 enum ql_vnd_host_stat_action { 5430 QLA_STOP = 0, 5431 QLA_START, 5432 QLA_CLEAR, 5433 }; 5434 5435 struct ql_vnd_mng_host_stats_param { 5436 u32 stat_type; 5437 enum ql_vnd_host_stat_action action; 5438 } __packed; 5439 5440 struct ql_vnd_mng_host_stats_resp { 5441 u32 status; 5442 } __packed; 5443 5444 struct ql_vnd_stats_param { 5445 u32 stat_type; 5446 } __packed; 5447 5448 struct ql_vnd_tgt_stats_param { 5449 s32 tgt_id; 5450 u32 stat_type; 5451 } __packed; 5452 5453 enum ql_vnd_host_port_action { 5454 QLA_ENABLE = 0, 5455 QLA_DISABLE, 5456 }; 5457 5458 struct ql_vnd_mng_host_port_param { 5459 enum ql_vnd_host_port_action action; 5460 } __packed; 5461 5462 struct ql_vnd_mng_host_port_resp { 5463 u32 status; 5464 } __packed; 5465 5466 struct ql_vnd_stat_entry { 5467 u32 stat_type; /* Failure type */ 5468 u32 tgt_num; /* Target Num */ 5469 u64 cnt; /* Counter value */ 5470 } __packed; 5471 5472 struct ql_vnd_stats { 5473 u64 entry_count; /* Num of entries */ 5474 u64 rservd; 5475 struct ql_vnd_stat_entry entry[]; /* Place holder of entries */ 5476 } __packed; 5477 5478 struct ql_vnd_host_stats_resp { 5479 u32 status; 5480 struct ql_vnd_stats stats; 5481 } __packed; 5482 5483 struct ql_vnd_tgt_stats_resp { 5484 u32 status; 5485 struct ql_vnd_stats stats; 5486 } __packed; 5487 5488 #include "qla_target.h" 5489 #include "qla_gbl.h" 5490 #include "qla_dbg.h" 5491 #include "qla_inline.h" 5492 5493 #define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND || \ 5494 _fcport->disc_state == DSC_DELETED) 5495 5496 #define DBG_FCPORT_PRFMT(_fp, _fmt, _args...) \ 5497 "%s: %8phC: " _fmt " (state=%d disc_state=%d scan_state=%d loopid=0x%x deleted=%d flags=0x%x)\n", \ 5498 __func__, _fp->port_name, ##_args, atomic_read(&_fp->state), \ 5499 _fp->disc_state, _fp->scan_state, _fp->loop_id, _fp->deleted, \ 5500 _fp->flags 5501 5502 #endif 5503