1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 #include <linux/btree.h> 29 30 #include <scsi/scsi.h> 31 #include <scsi/scsi_host.h> 32 #include <scsi/scsi_device.h> 33 #include <scsi/scsi_cmnd.h> 34 #include <scsi/scsi_transport_fc.h> 35 #include <scsi/scsi_bsg_fc.h> 36 37 #include "qla_bsg.h" 38 #include "qla_nx.h" 39 #include "qla_nx2.h" 40 #include "qla_nvme.h" 41 #define QLA2XXX_DRIVER_NAME "qla2xxx" 42 #define QLA2XXX_APIDEV "ql2xapidev" 43 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 44 45 /* 46 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 47 * but that's fine as we don't look at the last 24 ones for 48 * ISP2100 HBAs. 49 */ 50 #define MAILBOX_REGISTER_COUNT_2100 8 51 #define MAILBOX_REGISTER_COUNT_2200 24 52 #define MAILBOX_REGISTER_COUNT 32 53 54 #define QLA2200A_RISC_ROM_VER 4 55 #define FPM_2300 6 56 #define FPM_2310 7 57 58 #include "qla_settings.h" 59 60 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 61 62 /* 63 * Data bit definitions 64 */ 65 #define BIT_0 0x1 66 #define BIT_1 0x2 67 #define BIT_2 0x4 68 #define BIT_3 0x8 69 #define BIT_4 0x10 70 #define BIT_5 0x20 71 #define BIT_6 0x40 72 #define BIT_7 0x80 73 #define BIT_8 0x100 74 #define BIT_9 0x200 75 #define BIT_10 0x400 76 #define BIT_11 0x800 77 #define BIT_12 0x1000 78 #define BIT_13 0x2000 79 #define BIT_14 0x4000 80 #define BIT_15 0x8000 81 #define BIT_16 0x10000 82 #define BIT_17 0x20000 83 #define BIT_18 0x40000 84 #define BIT_19 0x80000 85 #define BIT_20 0x100000 86 #define BIT_21 0x200000 87 #define BIT_22 0x400000 88 #define BIT_23 0x800000 89 #define BIT_24 0x1000000 90 #define BIT_25 0x2000000 91 #define BIT_26 0x4000000 92 #define BIT_27 0x8000000 93 #define BIT_28 0x10000000 94 #define BIT_29 0x20000000 95 #define BIT_30 0x40000000 96 #define BIT_31 0x80000000 97 98 #define LSB(x) ((uint8_t)(x)) 99 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 100 101 #define LSW(x) ((uint16_t)(x)) 102 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 103 104 #define LSD(x) ((uint32_t)((uint64_t)(x))) 105 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 106 107 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 108 109 /* 110 * I/O register 111 */ 112 113 #define RD_REG_BYTE(addr) readb(addr) 114 #define RD_REG_WORD(addr) readw(addr) 115 #define RD_REG_DWORD(addr) readl(addr) 116 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 117 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 118 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 119 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 120 #define WRT_REG_WORD(addr, data) writew(data,addr) 121 #define WRT_REG_DWORD(addr, data) writel(data,addr) 122 123 /* 124 * ISP83XX specific remote register addresses 125 */ 126 #define QLA83XX_LED_PORT0 0x00201320 127 #define QLA83XX_LED_PORT1 0x00201328 128 #define QLA83XX_IDC_DEV_STATE 0x22102384 129 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 130 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 131 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 132 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 133 #define QLA83XX_IDC_CONTROL 0x22102390 134 #define QLA83XX_IDC_AUDIT 0x22102394 135 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 136 #define QLA83XX_DRIVER_LOCKID 0x22102104 137 #define QLA83XX_DRIVER_LOCK 0x8111c028 138 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 139 #define QLA83XX_FLASH_LOCKID 0x22102100 140 #define QLA83XX_FLASH_LOCK 0x8111c010 141 #define QLA83XX_FLASH_UNLOCK 0x8111c014 142 #define QLA83XX_DEV_PARTINFO1 0x221023e0 143 #define QLA83XX_DEV_PARTINFO2 0x221023e4 144 #define QLA83XX_FW_HEARTBEAT 0x221020b0 145 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 146 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 147 148 /* 83XX: Macros defining 8200 AEN Reason codes */ 149 #define IDC_DEVICE_STATE_CHANGE BIT_0 150 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 151 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 152 #define IDC_HEARTBEAT_FAILURE BIT_3 153 154 /* 83XX: Macros defining 8200 AEN Error-levels */ 155 #define ERR_LEVEL_NON_FATAL 0x1 156 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 157 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 158 159 /* 83XX: Macros for IDC Version */ 160 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 161 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 162 163 /* 83XX: Macros for scheduling dpc tasks */ 164 #define QLA83XX_NIC_CORE_RESET 0x1 165 #define QLA83XX_IDC_STATE_HANDLER 0x2 166 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 167 168 /* 83XX: Macros for defining IDC-Control bits */ 169 #define QLA83XX_IDC_RESET_DISABLED BIT_0 170 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 171 172 /* 83XX: Macros for different timeouts */ 173 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 174 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 175 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 176 177 /* 83XX: Macros for defining class in DEV-Partition Info register */ 178 #define QLA83XX_CLASS_TYPE_NONE 0x0 179 #define QLA83XX_CLASS_TYPE_NIC 0x1 180 #define QLA83XX_CLASS_TYPE_FCOE 0x2 181 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 182 183 /* 83XX: Macros for IDC Lock-Recovery stages */ 184 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 185 * lock-recovery 186 */ 187 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 188 189 /* 83XX: Macros for IDC Audit type */ 190 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 191 * dev-state change to NEED-RESET 192 * or NEED-QUIESCENT 193 */ 194 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 195 * reset-recovery completion is 196 * second 197 */ 198 /* ISP2031: Values for laser on/off */ 199 #define PORT_0_2031 0x00201340 200 #define PORT_1_2031 0x00201350 201 #define LASER_ON_2031 0x01800100 202 #define LASER_OFF_2031 0x01800180 203 204 /* 205 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 206 * 133Mhz slot. 207 */ 208 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 209 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 210 211 /* 212 * Fibre Channel device definitions. 213 */ 214 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 215 #define MAX_FIBRE_DEVICES_2100 512 216 #define MAX_FIBRE_DEVICES_2400 2048 217 #define MAX_FIBRE_DEVICES_LOOP 128 218 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 219 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 220 #define MAX_FIBRE_LUNS 0xFFFF 221 #define MAX_HOST_COUNT 16 222 223 /* 224 * Host adapter default definitions. 225 */ 226 #define MAX_BUSES 1 /* We only have one bus today */ 227 #define MIN_LUNS 8 228 #define MAX_LUNS MAX_FIBRE_LUNS 229 #define MAX_CMDS_PER_LUN 255 230 231 /* 232 * Fibre Channel device definitions. 233 */ 234 #define SNS_LAST_LOOP_ID_2100 0xfe 235 #define SNS_LAST_LOOP_ID_2300 0x7ff 236 237 #define LAST_LOCAL_LOOP_ID 0x7d 238 #define SNS_FL_PORT 0x7e 239 #define FABRIC_CONTROLLER 0x7f 240 #define SIMPLE_NAME_SERVER 0x80 241 #define SNS_FIRST_LOOP_ID 0x81 242 #define MANAGEMENT_SERVER 0xfe 243 #define BROADCAST 0xff 244 245 /* 246 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 247 * valid range of an N-PORT id is 0 through 0x7ef. 248 */ 249 #define NPH_LAST_HANDLE 0x7ee 250 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ 251 #define NPH_SNS 0x7fc /* FFFFFC */ 252 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 253 #define NPH_F_PORT 0x7fe /* FFFFFE */ 254 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 255 256 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 257 258 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 259 #include "qla_fw.h" 260 261 struct name_list_extended { 262 struct get_name_list_extended *l; 263 dma_addr_t ldma; 264 struct list_head fcports; 265 spinlock_t fcports_lock; 266 u32 size; 267 }; 268 /* 269 * Timeout timer counts in seconds 270 */ 271 #define PORT_RETRY_TIME 1 272 #define LOOP_DOWN_TIMEOUT 60 273 #define LOOP_DOWN_TIME 255 /* 240 */ 274 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 275 276 #define DEFAULT_OUTSTANDING_COMMANDS 4096 277 #define MIN_OUTSTANDING_COMMANDS 128 278 279 /* ISP request and response entry counts (37-65535) */ 280 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 281 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 282 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 283 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 284 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 285 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 286 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 287 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 288 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 289 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 290 #define FW_DEF_EXCHANGES_CNT 2048 291 #define FW_MAX_EXCHANGES_CNT (32 * 1024) 292 #define REDUCE_EXCHANGES_CNT (8 * 1024) 293 294 struct req_que; 295 struct qla_tgt_sess; 296 297 /* 298 * SCSI Request Block 299 */ 300 struct srb_cmd { 301 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 302 uint32_t request_sense_length; 303 uint32_t fw_sense_length; 304 uint8_t *request_sense_ptr; 305 void *ctx; 306 }; 307 308 /* 309 * SRB flag definitions 310 */ 311 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 312 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 313 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 314 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 315 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 316 #define SRB_WAKEUP_ON_COMP BIT_6 317 318 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 319 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 320 321 /* 322 * 24 bit port ID type definition. 323 */ 324 typedef union { 325 uint32_t b24 : 24; 326 327 struct { 328 #ifdef __BIG_ENDIAN 329 uint8_t domain; 330 uint8_t area; 331 uint8_t al_pa; 332 #elif defined(__LITTLE_ENDIAN) 333 uint8_t al_pa; 334 uint8_t area; 335 uint8_t domain; 336 #else 337 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 338 #endif 339 uint8_t rsvd_1; 340 } b; 341 } port_id_t; 342 #define INVALID_PORT_ID 0xFFFFFF 343 344 struct els_logo_payload { 345 uint8_t opcode; 346 uint8_t rsvd[3]; 347 uint8_t s_id[3]; 348 uint8_t rsvd1[1]; 349 uint8_t wwpn[WWN_SIZE]; 350 }; 351 352 struct els_plogi_payload { 353 uint8_t opcode; 354 uint8_t rsvd[3]; 355 uint8_t data[112]; 356 }; 357 358 struct ct_arg { 359 void *iocb; 360 u16 nport_handle; 361 dma_addr_t req_dma; 362 dma_addr_t rsp_dma; 363 u32 req_size; 364 u32 rsp_size; 365 u32 req_allocated_size; 366 u32 rsp_allocated_size; 367 void *req; 368 void *rsp; 369 port_id_t id; 370 }; 371 372 /* 373 * SRB extensions. 374 */ 375 struct srb_iocb { 376 union { 377 struct { 378 uint16_t flags; 379 #define SRB_LOGIN_RETRIED BIT_0 380 #define SRB_LOGIN_COND_PLOGI BIT_1 381 #define SRB_LOGIN_SKIP_PRLI BIT_2 382 #define SRB_LOGIN_NVME_PRLI BIT_3 383 #define SRB_LOGIN_PRLI_ONLY BIT_4 384 uint16_t data[2]; 385 u32 iop[2]; 386 } logio; 387 struct { 388 #define ELS_DCMD_TIMEOUT 20 389 #define ELS_DCMD_LOGO 0x5 390 uint32_t flags; 391 uint32_t els_cmd; 392 struct completion comp; 393 struct els_logo_payload *els_logo_pyld; 394 dma_addr_t els_logo_pyld_dma; 395 } els_logo; 396 struct { 397 #define ELS_DCMD_PLOGI 0x3 398 uint32_t flags; 399 uint32_t els_cmd; 400 struct completion comp; 401 struct els_plogi_payload *els_plogi_pyld; 402 struct els_plogi_payload *els_resp_pyld; 403 u32 tx_size; 404 u32 rx_size; 405 dma_addr_t els_plogi_pyld_dma; 406 dma_addr_t els_resp_pyld_dma; 407 uint32_t fw_status[3]; 408 __le16 comp_status; 409 __le16 len; 410 } els_plogi; 411 struct { 412 /* 413 * Values for flags field below are as 414 * defined in tsk_mgmt_entry struct 415 * for control_flags field in qla_fw.h. 416 */ 417 uint64_t lun; 418 uint32_t flags; 419 uint32_t data; 420 struct completion comp; 421 __le16 comp_status; 422 } tmf; 423 struct { 424 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 425 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 426 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 427 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 428 #define FXDISC_TIMEOUT 20 429 uint8_t flags; 430 uint32_t req_len; 431 uint32_t rsp_len; 432 void *req_addr; 433 void *rsp_addr; 434 dma_addr_t req_dma_handle; 435 dma_addr_t rsp_dma_handle; 436 __le32 adapter_id; 437 __le32 adapter_id_hi; 438 __le16 req_func_type; 439 __le32 req_data; 440 __le32 req_data_extra; 441 __le32 result; 442 __le32 seq_number; 443 __le16 fw_flags; 444 struct completion fxiocb_comp; 445 __le32 reserved_0; 446 uint8_t reserved_1; 447 } fxiocb; 448 struct { 449 uint32_t cmd_hndl; 450 __le16 comp_status; 451 __le16 req_que_no; 452 struct completion comp; 453 } abt; 454 struct ct_arg ctarg; 455 #define MAX_IOCB_MB_REG 28 456 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 457 struct { 458 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 459 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 460 void *out, *in; 461 dma_addr_t out_dma, in_dma; 462 struct completion comp; 463 int rc; 464 } mbx; 465 struct { 466 struct imm_ntfy_from_isp *ntfy; 467 } nack; 468 struct { 469 __le16 comp_status; 470 uint16_t rsp_pyld_len; 471 uint8_t aen_op; 472 void *desc; 473 474 /* These are only used with ls4 requests */ 475 int cmd_len; 476 int rsp_len; 477 dma_addr_t cmd_dma; 478 dma_addr_t rsp_dma; 479 enum nvmefc_fcp_datadir dir; 480 uint32_t dl; 481 uint32_t timeout_sec; 482 struct list_head entry; 483 } nvme; 484 struct { 485 u16 cmd; 486 u16 vp_index; 487 } ctrlvp; 488 } u; 489 490 struct timer_list timer; 491 void (*timeout)(void *); 492 }; 493 494 /* Values for srb_ctx type */ 495 #define SRB_LOGIN_CMD 1 496 #define SRB_LOGOUT_CMD 2 497 #define SRB_ELS_CMD_RPT 3 498 #define SRB_ELS_CMD_HST 4 499 #define SRB_CT_CMD 5 500 #define SRB_ADISC_CMD 6 501 #define SRB_TM_CMD 7 502 #define SRB_SCSI_CMD 8 503 #define SRB_BIDI_CMD 9 504 #define SRB_FXIOCB_DCMD 10 505 #define SRB_FXIOCB_BCMD 11 506 #define SRB_ABT_CMD 12 507 #define SRB_ELS_DCMD 13 508 #define SRB_MB_IOCB 14 509 #define SRB_CT_PTHRU_CMD 15 510 #define SRB_NACK_PLOGI 16 511 #define SRB_NACK_PRLI 17 512 #define SRB_NACK_LOGO 18 513 #define SRB_NVME_CMD 19 514 #define SRB_NVME_LS 20 515 #define SRB_PRLI_CMD 21 516 #define SRB_CTRL_VP 22 517 #define SRB_PRLO_CMD 23 518 519 enum { 520 TYPE_SRB, 521 TYPE_TGT_CMD, 522 }; 523 524 typedef struct srb { 525 /* 526 * Do not move cmd_type field, it needs to 527 * line up with qla_tgt_cmd->cmd_type 528 */ 529 uint8_t cmd_type; 530 uint8_t pad[3]; 531 atomic_t ref_count; 532 wait_queue_head_t nvme_ls_waitq; 533 struct fc_port *fcport; 534 struct scsi_qla_host *vha; 535 uint32_t handle; 536 uint16_t flags; 537 uint16_t type; 538 const char *name; 539 int iocbs; 540 struct qla_qpair *qpair; 541 struct list_head elem; 542 u32 gen1; /* scratch */ 543 u32 gen2; /* scratch */ 544 int rc; 545 int retry_count; 546 struct completion comp; 547 union { 548 struct srb_iocb iocb_cmd; 549 struct bsg_job *bsg_job; 550 struct srb_cmd scmd; 551 } u; 552 void (*done)(void *, int); 553 void (*free)(void *); 554 } srb_t; 555 556 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 557 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 558 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 559 560 #define GET_CMD_SENSE_LEN(sp) \ 561 (sp->u.scmd.request_sense_length) 562 #define SET_CMD_SENSE_LEN(sp, len) \ 563 (sp->u.scmd.request_sense_length = len) 564 #define GET_CMD_SENSE_PTR(sp) \ 565 (sp->u.scmd.request_sense_ptr) 566 #define SET_CMD_SENSE_PTR(sp, ptr) \ 567 (sp->u.scmd.request_sense_ptr = ptr) 568 #define GET_FW_SENSE_LEN(sp) \ 569 (sp->u.scmd.fw_sense_length) 570 #define SET_FW_SENSE_LEN(sp, len) \ 571 (sp->u.scmd.fw_sense_length = len) 572 573 struct msg_echo_lb { 574 dma_addr_t send_dma; 575 dma_addr_t rcv_dma; 576 uint16_t req_sg_cnt; 577 uint16_t rsp_sg_cnt; 578 uint16_t options; 579 uint32_t transfer_size; 580 uint32_t iteration_count; 581 }; 582 583 /* 584 * ISP I/O Register Set structure definitions. 585 */ 586 struct device_reg_2xxx { 587 uint16_t flash_address; /* Flash BIOS address */ 588 uint16_t flash_data; /* Flash BIOS data */ 589 uint16_t unused_1[1]; /* Gap */ 590 uint16_t ctrl_status; /* Control/Status */ 591 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 592 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 593 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 594 595 uint16_t ictrl; /* Interrupt control */ 596 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 597 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 598 599 uint16_t istatus; /* Interrupt status */ 600 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 601 602 uint16_t semaphore; /* Semaphore */ 603 uint16_t nvram; /* NVRAM register. */ 604 #define NVR_DESELECT 0 605 #define NVR_BUSY BIT_15 606 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 607 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 608 #define NVR_DATA_IN BIT_3 609 #define NVR_DATA_OUT BIT_2 610 #define NVR_SELECT BIT_1 611 #define NVR_CLOCK BIT_0 612 613 #define NVR_WAIT_CNT 20000 614 615 union { 616 struct { 617 uint16_t mailbox0; 618 uint16_t mailbox1; 619 uint16_t mailbox2; 620 uint16_t mailbox3; 621 uint16_t mailbox4; 622 uint16_t mailbox5; 623 uint16_t mailbox6; 624 uint16_t mailbox7; 625 uint16_t unused_2[59]; /* Gap */ 626 } __attribute__((packed)) isp2100; 627 struct { 628 /* Request Queue */ 629 uint16_t req_q_in; /* In-Pointer */ 630 uint16_t req_q_out; /* Out-Pointer */ 631 /* Response Queue */ 632 uint16_t rsp_q_in; /* In-Pointer */ 633 uint16_t rsp_q_out; /* Out-Pointer */ 634 635 /* RISC to Host Status */ 636 uint32_t host_status; 637 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 638 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 639 640 /* Host to Host Semaphore */ 641 uint16_t host_semaphore; 642 uint16_t unused_3[17]; /* Gap */ 643 uint16_t mailbox0; 644 uint16_t mailbox1; 645 uint16_t mailbox2; 646 uint16_t mailbox3; 647 uint16_t mailbox4; 648 uint16_t mailbox5; 649 uint16_t mailbox6; 650 uint16_t mailbox7; 651 uint16_t mailbox8; 652 uint16_t mailbox9; 653 uint16_t mailbox10; 654 uint16_t mailbox11; 655 uint16_t mailbox12; 656 uint16_t mailbox13; 657 uint16_t mailbox14; 658 uint16_t mailbox15; 659 uint16_t mailbox16; 660 uint16_t mailbox17; 661 uint16_t mailbox18; 662 uint16_t mailbox19; 663 uint16_t mailbox20; 664 uint16_t mailbox21; 665 uint16_t mailbox22; 666 uint16_t mailbox23; 667 uint16_t mailbox24; 668 uint16_t mailbox25; 669 uint16_t mailbox26; 670 uint16_t mailbox27; 671 uint16_t mailbox28; 672 uint16_t mailbox29; 673 uint16_t mailbox30; 674 uint16_t mailbox31; 675 uint16_t fb_cmd; 676 uint16_t unused_4[10]; /* Gap */ 677 } __attribute__((packed)) isp2300; 678 } u; 679 680 uint16_t fpm_diag_config; 681 uint16_t unused_5[0x4]; /* Gap */ 682 uint16_t risc_hw; 683 uint16_t unused_5_1; /* Gap */ 684 uint16_t pcr; /* Processor Control Register. */ 685 uint16_t unused_6[0x5]; /* Gap */ 686 uint16_t mctr; /* Memory Configuration and Timing. */ 687 uint16_t unused_7[0x3]; /* Gap */ 688 uint16_t fb_cmd_2100; /* Unused on 23XX */ 689 uint16_t unused_8[0x3]; /* Gap */ 690 uint16_t hccr; /* Host command & control register. */ 691 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 692 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 693 /* HCCR commands */ 694 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 695 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 696 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 697 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 698 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 699 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 700 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 701 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 702 703 uint16_t unused_9[5]; /* Gap */ 704 uint16_t gpiod; /* GPIO Data register. */ 705 uint16_t gpioe; /* GPIO Enable register. */ 706 #define GPIO_LED_MASK 0x00C0 707 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 708 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 709 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 710 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 711 #define GPIO_LED_ALL_OFF 0x0000 712 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 713 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 714 715 union { 716 struct { 717 uint16_t unused_10[8]; /* Gap */ 718 uint16_t mailbox8; 719 uint16_t mailbox9; 720 uint16_t mailbox10; 721 uint16_t mailbox11; 722 uint16_t mailbox12; 723 uint16_t mailbox13; 724 uint16_t mailbox14; 725 uint16_t mailbox15; 726 uint16_t mailbox16; 727 uint16_t mailbox17; 728 uint16_t mailbox18; 729 uint16_t mailbox19; 730 uint16_t mailbox20; 731 uint16_t mailbox21; 732 uint16_t mailbox22; 733 uint16_t mailbox23; /* Also probe reg. */ 734 } __attribute__((packed)) isp2200; 735 } u_end; 736 }; 737 738 struct device_reg_25xxmq { 739 uint32_t req_q_in; 740 uint32_t req_q_out; 741 uint32_t rsp_q_in; 742 uint32_t rsp_q_out; 743 uint32_t atio_q_in; 744 uint32_t atio_q_out; 745 }; 746 747 748 struct device_reg_fx00 { 749 uint32_t mailbox0; /* 00 */ 750 uint32_t mailbox1; /* 04 */ 751 uint32_t mailbox2; /* 08 */ 752 uint32_t mailbox3; /* 0C */ 753 uint32_t mailbox4; /* 10 */ 754 uint32_t mailbox5; /* 14 */ 755 uint32_t mailbox6; /* 18 */ 756 uint32_t mailbox7; /* 1C */ 757 uint32_t mailbox8; /* 20 */ 758 uint32_t mailbox9; /* 24 */ 759 uint32_t mailbox10; /* 28 */ 760 uint32_t mailbox11; 761 uint32_t mailbox12; 762 uint32_t mailbox13; 763 uint32_t mailbox14; 764 uint32_t mailbox15; 765 uint32_t mailbox16; 766 uint32_t mailbox17; 767 uint32_t mailbox18; 768 uint32_t mailbox19; 769 uint32_t mailbox20; 770 uint32_t mailbox21; 771 uint32_t mailbox22; 772 uint32_t mailbox23; 773 uint32_t mailbox24; 774 uint32_t mailbox25; 775 uint32_t mailbox26; 776 uint32_t mailbox27; 777 uint32_t mailbox28; 778 uint32_t mailbox29; 779 uint32_t mailbox30; 780 uint32_t mailbox31; 781 uint32_t aenmailbox0; 782 uint32_t aenmailbox1; 783 uint32_t aenmailbox2; 784 uint32_t aenmailbox3; 785 uint32_t aenmailbox4; 786 uint32_t aenmailbox5; 787 uint32_t aenmailbox6; 788 uint32_t aenmailbox7; 789 /* Request Queue. */ 790 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 791 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 792 /* Response Queue. */ 793 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 794 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 795 /* Init values shadowed on FW Up Event */ 796 uint32_t initval0; /* B0 */ 797 uint32_t initval1; /* B4 */ 798 uint32_t initval2; /* B8 */ 799 uint32_t initval3; /* BC */ 800 uint32_t initval4; /* C0 */ 801 uint32_t initval5; /* C4 */ 802 uint32_t initval6; /* C8 */ 803 uint32_t initval7; /* CC */ 804 uint32_t fwheartbeat; /* D0 */ 805 uint32_t pseudoaen; /* D4 */ 806 }; 807 808 809 810 typedef union { 811 struct device_reg_2xxx isp; 812 struct device_reg_24xx isp24; 813 struct device_reg_25xxmq isp25mq; 814 struct device_reg_82xx isp82; 815 struct device_reg_fx00 ispfx00; 816 } __iomem device_reg_t; 817 818 #define ISP_REQ_Q_IN(ha, reg) \ 819 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 820 &(reg)->u.isp2100.mailbox4 : \ 821 &(reg)->u.isp2300.req_q_in) 822 #define ISP_REQ_Q_OUT(ha, reg) \ 823 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 824 &(reg)->u.isp2100.mailbox4 : \ 825 &(reg)->u.isp2300.req_q_out) 826 #define ISP_RSP_Q_IN(ha, reg) \ 827 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 828 &(reg)->u.isp2100.mailbox5 : \ 829 &(reg)->u.isp2300.rsp_q_in) 830 #define ISP_RSP_Q_OUT(ha, reg) \ 831 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 832 &(reg)->u.isp2100.mailbox5 : \ 833 &(reg)->u.isp2300.rsp_q_out) 834 835 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 836 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 837 838 #define MAILBOX_REG(ha, reg, num) \ 839 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 840 (num < 8 ? \ 841 &(reg)->u.isp2100.mailbox0 + (num) : \ 842 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 843 &(reg)->u.isp2300.mailbox0 + (num)) 844 #define RD_MAILBOX_REG(ha, reg, num) \ 845 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 846 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 847 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 848 849 #define FB_CMD_REG(ha, reg) \ 850 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 851 &(reg)->fb_cmd_2100 : \ 852 &(reg)->u.isp2300.fb_cmd) 853 #define RD_FB_CMD_REG(ha, reg) \ 854 RD_REG_WORD(FB_CMD_REG(ha, reg)) 855 #define WRT_FB_CMD_REG(ha, reg, data) \ 856 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 857 858 typedef struct { 859 uint32_t out_mb; /* outbound from driver */ 860 uint32_t in_mb; /* Incoming from RISC */ 861 uint16_t mb[MAILBOX_REGISTER_COUNT]; 862 long buf_size; 863 void *bufp; 864 uint32_t tov; 865 uint8_t flags; 866 #define MBX_DMA_IN BIT_0 867 #define MBX_DMA_OUT BIT_1 868 #define IOCTL_CMD BIT_2 869 } mbx_cmd_t; 870 871 struct mbx_cmd_32 { 872 uint32_t out_mb; /* outbound from driver */ 873 uint32_t in_mb; /* Incoming from RISC */ 874 uint32_t mb[MAILBOX_REGISTER_COUNT]; 875 long buf_size; 876 void *bufp; 877 uint32_t tov; 878 uint8_t flags; 879 #define MBX_DMA_IN BIT_0 880 #define MBX_DMA_OUT BIT_1 881 #define IOCTL_CMD BIT_2 882 }; 883 884 885 #define MBX_TOV_SECONDS 30 886 887 /* 888 * ISP product identification definitions in mailboxes after reset. 889 */ 890 #define PROD_ID_1 0x4953 891 #define PROD_ID_2 0x0000 892 #define PROD_ID_2a 0x5020 893 #define PROD_ID_3 0x2020 894 895 /* 896 * ISP mailbox Self-Test status codes 897 */ 898 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 899 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 900 #define MBS_BUSY 4 /* Busy. */ 901 902 /* 903 * ISP mailbox command complete status codes 904 */ 905 #define MBS_COMMAND_COMPLETE 0x4000 906 #define MBS_INVALID_COMMAND 0x4001 907 #define MBS_HOST_INTERFACE_ERROR 0x4002 908 #define MBS_TEST_FAILED 0x4003 909 #define MBS_COMMAND_ERROR 0x4005 910 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 911 #define MBS_PORT_ID_USED 0x4007 912 #define MBS_LOOP_ID_USED 0x4008 913 #define MBS_ALL_IDS_IN_USE 0x4009 914 #define MBS_NOT_LOGGED_IN 0x400A 915 #define MBS_LINK_DOWN_ERROR 0x400B 916 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 917 918 /* 919 * ISP mailbox asynchronous event status codes 920 */ 921 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 922 #define MBA_RESET 0x8001 /* Reset Detected. */ 923 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 924 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 925 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 926 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 927 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 928 /* occurred. */ 929 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 930 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 931 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 932 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 933 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 934 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 935 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 936 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 937 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 938 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 939 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 940 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 941 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 942 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 943 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 944 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 945 /* used. */ 946 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 947 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 948 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 949 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 950 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 951 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 952 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 953 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 954 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 955 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 956 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 957 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 958 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 959 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 960 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 961 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 962 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 963 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 964 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 965 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 966 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 967 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 968 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 969 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 970 Notification */ 971 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 972 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 973 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 974 /* 83XX FCoE specific */ 975 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 976 977 /* Interrupt type codes */ 978 #define INTR_ROM_MB_SUCCESS 0x1 979 #define INTR_ROM_MB_FAILED 0x2 980 #define INTR_MB_SUCCESS 0x10 981 #define INTR_MB_FAILED 0x11 982 #define INTR_ASYNC_EVENT 0x12 983 #define INTR_RSP_QUE_UPDATE 0x13 984 #define INTR_RSP_QUE_UPDATE_83XX 0x14 985 #define INTR_ATIO_QUE_UPDATE 0x1C 986 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 987 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 988 989 /* ISP mailbox loopback echo diagnostic error code */ 990 #define MBS_LB_RESET 0x17 991 /* 992 * Firmware options 1, 2, 3. 993 */ 994 #define FO1_AE_ON_LIPF8 BIT_0 995 #define FO1_AE_ALL_LIP_RESET BIT_1 996 #define FO1_CTIO_RETRY BIT_3 997 #define FO1_DISABLE_LIP_F7_SW BIT_4 998 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 999 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 1000 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 1001 #define FO1_SET_EMPHASIS_SWING BIT_8 1002 #define FO1_AE_AUTO_BYPASS BIT_9 1003 #define FO1_ENABLE_PURE_IOCB BIT_10 1004 #define FO1_AE_PLOGI_RJT BIT_11 1005 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 1006 #define FO1_AE_QUEUE_FULL BIT_13 1007 1008 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 1009 #define FO2_REV_LOOPBACK BIT_1 1010 1011 #define FO3_ENABLE_EMERG_IOCB BIT_0 1012 #define FO3_AE_RND_ERROR BIT_1 1013 1014 /* 24XX additional firmware options */ 1015 #define ADD_FO_COUNT 3 1016 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 1017 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 1018 1019 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 1020 1021 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 1022 1023 /* 1024 * ISP mailbox commands 1025 */ 1026 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1027 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1028 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 1029 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 1030 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1031 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 1032 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 1033 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 1034 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 1035 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 1036 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 1037 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 1038 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 1039 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 1040 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 1041 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 1042 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1043 #define MBC_RESET 0x18 /* Reset. */ 1044 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1045 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1046 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1047 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1048 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1049 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1050 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1051 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1052 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1053 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1054 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1055 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1056 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1057 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1058 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1059 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1060 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1061 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1062 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1063 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1064 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1065 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1066 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1067 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1068 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1069 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1070 /* Initialization Procedure */ 1071 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1072 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1073 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1074 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1075 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1076 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1077 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1078 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1079 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1080 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1081 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1082 /* commandd. */ 1083 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1084 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1085 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1086 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1087 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1088 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1089 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1090 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1091 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1092 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1093 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1094 1095 /* 1096 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1097 * should be defined with MBC_MR_* 1098 */ 1099 #define MBC_MR_DRV_SHUTDOWN 0x6A 1100 1101 /* 1102 * ISP24xx mailbox commands 1103 */ 1104 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1105 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1106 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1107 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1108 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1109 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1110 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1111 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1112 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1113 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1114 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1115 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1116 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1117 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1118 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1119 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1120 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1121 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1122 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1123 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1124 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1125 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1126 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1127 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1128 1129 /* 1130 * ISP81xx mailbox commands 1131 */ 1132 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1133 1134 /* 1135 * ISP8044 mailbox commands 1136 */ 1137 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1138 #define HCS_WRITE_SERDES 0x3 1139 #define HCS_READ_SERDES 0x4 1140 1141 /* Firmware return data sizes */ 1142 #define FCAL_MAP_SIZE 128 1143 1144 /* Mailbox bit definitions for out_mb and in_mb */ 1145 #define MBX_31 BIT_31 1146 #define MBX_30 BIT_30 1147 #define MBX_29 BIT_29 1148 #define MBX_28 BIT_28 1149 #define MBX_27 BIT_27 1150 #define MBX_26 BIT_26 1151 #define MBX_25 BIT_25 1152 #define MBX_24 BIT_24 1153 #define MBX_23 BIT_23 1154 #define MBX_22 BIT_22 1155 #define MBX_21 BIT_21 1156 #define MBX_20 BIT_20 1157 #define MBX_19 BIT_19 1158 #define MBX_18 BIT_18 1159 #define MBX_17 BIT_17 1160 #define MBX_16 BIT_16 1161 #define MBX_15 BIT_15 1162 #define MBX_14 BIT_14 1163 #define MBX_13 BIT_13 1164 #define MBX_12 BIT_12 1165 #define MBX_11 BIT_11 1166 #define MBX_10 BIT_10 1167 #define MBX_9 BIT_9 1168 #define MBX_8 BIT_8 1169 #define MBX_7 BIT_7 1170 #define MBX_6 BIT_6 1171 #define MBX_5 BIT_5 1172 #define MBX_4 BIT_4 1173 #define MBX_3 BIT_3 1174 #define MBX_2 BIT_2 1175 #define MBX_1 BIT_1 1176 #define MBX_0 BIT_0 1177 1178 #define RNID_TYPE_PORT_LOGIN 0x7 1179 #define RNID_TYPE_SET_VERSION 0x9 1180 #define RNID_TYPE_ASIC_TEMP 0xC 1181 1182 /* 1183 * Firmware state codes from get firmware state mailbox command 1184 */ 1185 #define FSTATE_CONFIG_WAIT 0 1186 #define FSTATE_WAIT_AL_PA 1 1187 #define FSTATE_WAIT_LOGIN 2 1188 #define FSTATE_READY 3 1189 #define FSTATE_LOSS_OF_SYNC 4 1190 #define FSTATE_ERROR 5 1191 #define FSTATE_REINIT 6 1192 #define FSTATE_NON_PART 7 1193 1194 #define FSTATE_CONFIG_CORRECT 0 1195 #define FSTATE_P2P_RCV_LIP 1 1196 #define FSTATE_P2P_CHOOSE_LOOP 2 1197 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1198 #define FSTATE_FATAL_ERROR 4 1199 #define FSTATE_LOOP_BACK_CONN 5 1200 1201 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1202 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1203 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1204 #define QLA27XX_PRIMARY_IMAGE 1 1205 #define QLA27XX_SECONDARY_IMAGE 2 1206 1207 /* 1208 * Port Database structure definition 1209 * Little endian except where noted. 1210 */ 1211 #define PORT_DATABASE_SIZE 128 /* bytes */ 1212 typedef struct { 1213 uint8_t options; 1214 uint8_t control; 1215 uint8_t master_state; 1216 uint8_t slave_state; 1217 uint8_t reserved[2]; 1218 uint8_t hard_address; 1219 uint8_t reserved_1; 1220 uint8_t port_id[4]; 1221 uint8_t node_name[WWN_SIZE]; 1222 uint8_t port_name[WWN_SIZE]; 1223 uint16_t execution_throttle; 1224 uint16_t execution_count; 1225 uint8_t reset_count; 1226 uint8_t reserved_2; 1227 uint16_t resource_allocation; 1228 uint16_t current_allocation; 1229 uint16_t queue_head; 1230 uint16_t queue_tail; 1231 uint16_t transmit_execution_list_next; 1232 uint16_t transmit_execution_list_previous; 1233 uint16_t common_features; 1234 uint16_t total_concurrent_sequences; 1235 uint16_t RO_by_information_category; 1236 uint8_t recipient; 1237 uint8_t initiator; 1238 uint16_t receive_data_size; 1239 uint16_t concurrent_sequences; 1240 uint16_t open_sequences_per_exchange; 1241 uint16_t lun_abort_flags; 1242 uint16_t lun_stop_flags; 1243 uint16_t stop_queue_head; 1244 uint16_t stop_queue_tail; 1245 uint16_t port_retry_timer; 1246 uint16_t next_sequence_id; 1247 uint16_t frame_count; 1248 uint16_t PRLI_payload_length; 1249 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1250 /* Bits 15-0 of word 0 */ 1251 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1252 /* Bits 15-0 of word 3 */ 1253 uint16_t loop_id; 1254 uint16_t extended_lun_info_list_pointer; 1255 uint16_t extended_lun_stop_list_pointer; 1256 } port_database_t; 1257 1258 /* 1259 * Port database slave/master states 1260 */ 1261 #define PD_STATE_DISCOVERY 0 1262 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1263 #define PD_STATE_PORT_LOGIN 2 1264 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1265 #define PD_STATE_PROCESS_LOGIN 4 1266 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1267 #define PD_STATE_PORT_LOGGED_IN 6 1268 #define PD_STATE_PORT_UNAVAILABLE 7 1269 #define PD_STATE_PROCESS_LOGOUT 8 1270 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1271 #define PD_STATE_PORT_LOGOUT 10 1272 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1273 1274 1275 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1276 #define QLA_ZIO_DISABLED 0 1277 #define QLA_ZIO_DEFAULT_TIMER 2 1278 1279 /* 1280 * ISP Initialization Control Block. 1281 * Little endian except where noted. 1282 */ 1283 #define ICB_VERSION 1 1284 typedef struct { 1285 uint8_t version; 1286 uint8_t reserved_1; 1287 1288 /* 1289 * LSB BIT 0 = Enable Hard Loop Id 1290 * LSB BIT 1 = Enable Fairness 1291 * LSB BIT 2 = Enable Full-Duplex 1292 * LSB BIT 3 = Enable Fast Posting 1293 * LSB BIT 4 = Enable Target Mode 1294 * LSB BIT 5 = Disable Initiator Mode 1295 * LSB BIT 6 = Enable ADISC 1296 * LSB BIT 7 = Enable Target Inquiry Data 1297 * 1298 * MSB BIT 0 = Enable PDBC Notify 1299 * MSB BIT 1 = Non Participating LIP 1300 * MSB BIT 2 = Descending Loop ID Search 1301 * MSB BIT 3 = Acquire Loop ID in LIPA 1302 * MSB BIT 4 = Stop PortQ on Full Status 1303 * MSB BIT 5 = Full Login after LIP 1304 * MSB BIT 6 = Node Name Option 1305 * MSB BIT 7 = Ext IFWCB enable bit 1306 */ 1307 uint8_t firmware_options[2]; 1308 1309 uint16_t frame_payload_size; 1310 uint16_t max_iocb_allocation; 1311 uint16_t execution_throttle; 1312 uint8_t retry_count; 1313 uint8_t retry_delay; /* unused */ 1314 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1315 uint16_t hard_address; 1316 uint8_t inquiry_data; 1317 uint8_t login_timeout; 1318 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1319 1320 uint16_t request_q_outpointer; 1321 uint16_t response_q_inpointer; 1322 uint16_t request_q_length; 1323 uint16_t response_q_length; 1324 uint32_t request_q_address[2]; 1325 uint32_t response_q_address[2]; 1326 1327 uint16_t lun_enables; 1328 uint8_t command_resource_count; 1329 uint8_t immediate_notify_resource_count; 1330 uint16_t timeout; 1331 uint8_t reserved_2[2]; 1332 1333 /* 1334 * LSB BIT 0 = Timer Operation mode bit 0 1335 * LSB BIT 1 = Timer Operation mode bit 1 1336 * LSB BIT 2 = Timer Operation mode bit 2 1337 * LSB BIT 3 = Timer Operation mode bit 3 1338 * LSB BIT 4 = Init Config Mode bit 0 1339 * LSB BIT 5 = Init Config Mode bit 1 1340 * LSB BIT 6 = Init Config Mode bit 2 1341 * LSB BIT 7 = Enable Non part on LIHA failure 1342 * 1343 * MSB BIT 0 = Enable class 2 1344 * MSB BIT 1 = Enable ACK0 1345 * MSB BIT 2 = 1346 * MSB BIT 3 = 1347 * MSB BIT 4 = FC Tape Enable 1348 * MSB BIT 5 = Enable FC Confirm 1349 * MSB BIT 6 = Enable command queuing in target mode 1350 * MSB BIT 7 = No Logo On Link Down 1351 */ 1352 uint8_t add_firmware_options[2]; 1353 1354 uint8_t response_accumulation_timer; 1355 uint8_t interrupt_delay_timer; 1356 1357 /* 1358 * LSB BIT 0 = Enable Read xfr_rdy 1359 * LSB BIT 1 = Soft ID only 1360 * LSB BIT 2 = 1361 * LSB BIT 3 = 1362 * LSB BIT 4 = FCP RSP Payload [0] 1363 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1364 * LSB BIT 6 = Enable Out-of-Order frame handling 1365 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1366 * 1367 * MSB BIT 0 = Sbus enable - 2300 1368 * MSB BIT 1 = 1369 * MSB BIT 2 = 1370 * MSB BIT 3 = 1371 * MSB BIT 4 = LED mode 1372 * MSB BIT 5 = enable 50 ohm termination 1373 * MSB BIT 6 = Data Rate (2300 only) 1374 * MSB BIT 7 = Data Rate (2300 only) 1375 */ 1376 uint8_t special_options[2]; 1377 1378 uint8_t reserved_3[26]; 1379 } init_cb_t; 1380 1381 /* 1382 * Get Link Status mailbox command return buffer. 1383 */ 1384 #define GLSO_SEND_RPS BIT_0 1385 #define GLSO_USE_DID BIT_3 1386 1387 struct link_statistics { 1388 uint32_t link_fail_cnt; 1389 uint32_t loss_sync_cnt; 1390 uint32_t loss_sig_cnt; 1391 uint32_t prim_seq_err_cnt; 1392 uint32_t inval_xmit_word_cnt; 1393 uint32_t inval_crc_cnt; 1394 uint32_t lip_cnt; 1395 uint32_t link_up_cnt; 1396 uint32_t link_down_loop_init_tmo; 1397 uint32_t link_down_los; 1398 uint32_t link_down_loss_rcv_clk; 1399 uint32_t reserved0[5]; 1400 uint32_t port_cfg_chg; 1401 uint32_t reserved1[11]; 1402 uint32_t rsp_q_full; 1403 uint32_t atio_q_full; 1404 uint32_t drop_ae; 1405 uint32_t els_proto_err; 1406 uint32_t reserved2; 1407 uint32_t tx_frames; 1408 uint32_t rx_frames; 1409 uint32_t discarded_frames; 1410 uint32_t dropped_frames; 1411 uint32_t reserved3; 1412 uint32_t nos_rcvd; 1413 uint32_t reserved4[4]; 1414 uint32_t tx_prjt; 1415 uint32_t rcv_exfail; 1416 uint32_t rcv_abts; 1417 uint32_t seq_frm_miss; 1418 uint32_t corr_err; 1419 uint32_t mb_rqst; 1420 uint32_t nport_full; 1421 uint32_t eofa; 1422 uint32_t reserved5; 1423 uint32_t fpm_recv_word_cnt_lo; 1424 uint32_t fpm_recv_word_cnt_hi; 1425 uint32_t fpm_disc_word_cnt_lo; 1426 uint32_t fpm_disc_word_cnt_hi; 1427 uint32_t fpm_xmit_word_cnt_lo; 1428 uint32_t fpm_xmit_word_cnt_hi; 1429 uint32_t reserved6[70]; 1430 }; 1431 1432 /* 1433 * NVRAM Command values. 1434 */ 1435 #define NV_START_BIT BIT_2 1436 #define NV_WRITE_OP (BIT_26+BIT_24) 1437 #define NV_READ_OP (BIT_26+BIT_25) 1438 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1439 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1440 #define NV_DELAY_COUNT 10 1441 1442 /* 1443 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1444 */ 1445 typedef struct { 1446 /* 1447 * NVRAM header 1448 */ 1449 uint8_t id[4]; 1450 uint8_t nvram_version; 1451 uint8_t reserved_0; 1452 1453 /* 1454 * NVRAM RISC parameter block 1455 */ 1456 uint8_t parameter_block_version; 1457 uint8_t reserved_1; 1458 1459 /* 1460 * LSB BIT 0 = Enable Hard Loop Id 1461 * LSB BIT 1 = Enable Fairness 1462 * LSB BIT 2 = Enable Full-Duplex 1463 * LSB BIT 3 = Enable Fast Posting 1464 * LSB BIT 4 = Enable Target Mode 1465 * LSB BIT 5 = Disable Initiator Mode 1466 * LSB BIT 6 = Enable ADISC 1467 * LSB BIT 7 = Enable Target Inquiry Data 1468 * 1469 * MSB BIT 0 = Enable PDBC Notify 1470 * MSB BIT 1 = Non Participating LIP 1471 * MSB BIT 2 = Descending Loop ID Search 1472 * MSB BIT 3 = Acquire Loop ID in LIPA 1473 * MSB BIT 4 = Stop PortQ on Full Status 1474 * MSB BIT 5 = Full Login after LIP 1475 * MSB BIT 6 = Node Name Option 1476 * MSB BIT 7 = Ext IFWCB enable bit 1477 */ 1478 uint8_t firmware_options[2]; 1479 1480 uint16_t frame_payload_size; 1481 uint16_t max_iocb_allocation; 1482 uint16_t execution_throttle; 1483 uint8_t retry_count; 1484 uint8_t retry_delay; /* unused */ 1485 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1486 uint16_t hard_address; 1487 uint8_t inquiry_data; 1488 uint8_t login_timeout; 1489 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1490 1491 /* 1492 * LSB BIT 0 = Timer Operation mode bit 0 1493 * LSB BIT 1 = Timer Operation mode bit 1 1494 * LSB BIT 2 = Timer Operation mode bit 2 1495 * LSB BIT 3 = Timer Operation mode bit 3 1496 * LSB BIT 4 = Init Config Mode bit 0 1497 * LSB BIT 5 = Init Config Mode bit 1 1498 * LSB BIT 6 = Init Config Mode bit 2 1499 * LSB BIT 7 = Enable Non part on LIHA failure 1500 * 1501 * MSB BIT 0 = Enable class 2 1502 * MSB BIT 1 = Enable ACK0 1503 * MSB BIT 2 = 1504 * MSB BIT 3 = 1505 * MSB BIT 4 = FC Tape Enable 1506 * MSB BIT 5 = Enable FC Confirm 1507 * MSB BIT 6 = Enable command queuing in target mode 1508 * MSB BIT 7 = No Logo On Link Down 1509 */ 1510 uint8_t add_firmware_options[2]; 1511 1512 uint8_t response_accumulation_timer; 1513 uint8_t interrupt_delay_timer; 1514 1515 /* 1516 * LSB BIT 0 = Enable Read xfr_rdy 1517 * LSB BIT 1 = Soft ID only 1518 * LSB BIT 2 = 1519 * LSB BIT 3 = 1520 * LSB BIT 4 = FCP RSP Payload [0] 1521 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1522 * LSB BIT 6 = Enable Out-of-Order frame handling 1523 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1524 * 1525 * MSB BIT 0 = Sbus enable - 2300 1526 * MSB BIT 1 = 1527 * MSB BIT 2 = 1528 * MSB BIT 3 = 1529 * MSB BIT 4 = LED mode 1530 * MSB BIT 5 = enable 50 ohm termination 1531 * MSB BIT 6 = Data Rate (2300 only) 1532 * MSB BIT 7 = Data Rate (2300 only) 1533 */ 1534 uint8_t special_options[2]; 1535 1536 /* Reserved for expanded RISC parameter block */ 1537 uint8_t reserved_2[22]; 1538 1539 /* 1540 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1541 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1542 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1543 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1544 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1545 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1546 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1547 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1548 * 1549 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1550 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1551 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1552 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1553 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1554 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1555 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1556 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1557 * 1558 * LSB BIT 0 = Output Swing 1G bit 0 1559 * LSB BIT 1 = Output Swing 1G bit 1 1560 * LSB BIT 2 = Output Swing 1G bit 2 1561 * LSB BIT 3 = Output Emphasis 1G bit 0 1562 * LSB BIT 4 = Output Emphasis 1G bit 1 1563 * LSB BIT 5 = Output Swing 2G bit 0 1564 * LSB BIT 6 = Output Swing 2G bit 1 1565 * LSB BIT 7 = Output Swing 2G bit 2 1566 * 1567 * MSB BIT 0 = Output Emphasis 2G bit 0 1568 * MSB BIT 1 = Output Emphasis 2G bit 1 1569 * MSB BIT 2 = Output Enable 1570 * MSB BIT 3 = 1571 * MSB BIT 4 = 1572 * MSB BIT 5 = 1573 * MSB BIT 6 = 1574 * MSB BIT 7 = 1575 */ 1576 uint8_t seriallink_options[4]; 1577 1578 /* 1579 * NVRAM host parameter block 1580 * 1581 * LSB BIT 0 = Enable spinup delay 1582 * LSB BIT 1 = Disable BIOS 1583 * LSB BIT 2 = Enable Memory Map BIOS 1584 * LSB BIT 3 = Enable Selectable Boot 1585 * LSB BIT 4 = Disable RISC code load 1586 * LSB BIT 5 = Set cache line size 1 1587 * LSB BIT 6 = PCI Parity Disable 1588 * LSB BIT 7 = Enable extended logging 1589 * 1590 * MSB BIT 0 = Enable 64bit addressing 1591 * MSB BIT 1 = Enable lip reset 1592 * MSB BIT 2 = Enable lip full login 1593 * MSB BIT 3 = Enable target reset 1594 * MSB BIT 4 = Enable database storage 1595 * MSB BIT 5 = Enable cache flush read 1596 * MSB BIT 6 = Enable database load 1597 * MSB BIT 7 = Enable alternate WWN 1598 */ 1599 uint8_t host_p[2]; 1600 1601 uint8_t boot_node_name[WWN_SIZE]; 1602 uint8_t boot_lun_number; 1603 uint8_t reset_delay; 1604 uint8_t port_down_retry_count; 1605 uint8_t boot_id_number; 1606 uint16_t max_luns_per_target; 1607 uint8_t fcode_boot_port_name[WWN_SIZE]; 1608 uint8_t alternate_port_name[WWN_SIZE]; 1609 uint8_t alternate_node_name[WWN_SIZE]; 1610 1611 /* 1612 * BIT 0 = Selective Login 1613 * BIT 1 = Alt-Boot Enable 1614 * BIT 2 = 1615 * BIT 3 = Boot Order List 1616 * BIT 4 = 1617 * BIT 5 = Selective LUN 1618 * BIT 6 = 1619 * BIT 7 = unused 1620 */ 1621 uint8_t efi_parameters; 1622 1623 uint8_t link_down_timeout; 1624 1625 uint8_t adapter_id[16]; 1626 1627 uint8_t alt1_boot_node_name[WWN_SIZE]; 1628 uint16_t alt1_boot_lun_number; 1629 uint8_t alt2_boot_node_name[WWN_SIZE]; 1630 uint16_t alt2_boot_lun_number; 1631 uint8_t alt3_boot_node_name[WWN_SIZE]; 1632 uint16_t alt3_boot_lun_number; 1633 uint8_t alt4_boot_node_name[WWN_SIZE]; 1634 uint16_t alt4_boot_lun_number; 1635 uint8_t alt5_boot_node_name[WWN_SIZE]; 1636 uint16_t alt5_boot_lun_number; 1637 uint8_t alt6_boot_node_name[WWN_SIZE]; 1638 uint16_t alt6_boot_lun_number; 1639 uint8_t alt7_boot_node_name[WWN_SIZE]; 1640 uint16_t alt7_boot_lun_number; 1641 1642 uint8_t reserved_3[2]; 1643 1644 /* Offset 200-215 : Model Number */ 1645 uint8_t model_number[16]; 1646 1647 /* OEM related items */ 1648 uint8_t oem_specific[16]; 1649 1650 /* 1651 * NVRAM Adapter Features offset 232-239 1652 * 1653 * LSB BIT 0 = External GBIC 1654 * LSB BIT 1 = Risc RAM parity 1655 * LSB BIT 2 = Buffer Plus Module 1656 * LSB BIT 3 = Multi Chip Adapter 1657 * LSB BIT 4 = Internal connector 1658 * LSB BIT 5 = 1659 * LSB BIT 6 = 1660 * LSB BIT 7 = 1661 * 1662 * MSB BIT 0 = 1663 * MSB BIT 1 = 1664 * MSB BIT 2 = 1665 * MSB BIT 3 = 1666 * MSB BIT 4 = 1667 * MSB BIT 5 = 1668 * MSB BIT 6 = 1669 * MSB BIT 7 = 1670 */ 1671 uint8_t adapter_features[2]; 1672 1673 uint8_t reserved_4[16]; 1674 1675 /* Subsystem vendor ID for ISP2200 */ 1676 uint16_t subsystem_vendor_id_2200; 1677 1678 /* Subsystem device ID for ISP2200 */ 1679 uint16_t subsystem_device_id_2200; 1680 1681 uint8_t reserved_5; 1682 uint8_t checksum; 1683 } nvram_t; 1684 1685 /* 1686 * ISP queue - response queue entry definition. 1687 */ 1688 typedef struct { 1689 uint8_t entry_type; /* Entry type. */ 1690 uint8_t entry_count; /* Entry count. */ 1691 uint8_t sys_define; /* System defined. */ 1692 uint8_t entry_status; /* Entry Status. */ 1693 uint32_t handle; /* System defined handle */ 1694 uint8_t data[52]; 1695 uint32_t signature; 1696 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1697 } response_t; 1698 1699 /* 1700 * ISP queue - ATIO queue entry definition. 1701 */ 1702 struct atio { 1703 uint8_t entry_type; /* Entry type. */ 1704 uint8_t entry_count; /* Entry count. */ 1705 __le16 attr_n_length; 1706 uint8_t data[56]; 1707 uint32_t signature; 1708 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1709 }; 1710 1711 typedef union { 1712 uint16_t extended; 1713 struct { 1714 uint8_t reserved; 1715 uint8_t standard; 1716 } id; 1717 } target_id_t; 1718 1719 #define SET_TARGET_ID(ha, to, from) \ 1720 do { \ 1721 if (HAS_EXTENDED_IDS(ha)) \ 1722 to.extended = cpu_to_le16(from); \ 1723 else \ 1724 to.id.standard = (uint8_t)from; \ 1725 } while (0) 1726 1727 /* 1728 * ISP queue - command entry structure definition. 1729 */ 1730 #define COMMAND_TYPE 0x11 /* Command entry */ 1731 typedef struct { 1732 uint8_t entry_type; /* Entry type. */ 1733 uint8_t entry_count; /* Entry count. */ 1734 uint8_t sys_define; /* System defined. */ 1735 uint8_t entry_status; /* Entry Status. */ 1736 uint32_t handle; /* System handle. */ 1737 target_id_t target; /* SCSI ID */ 1738 uint16_t lun; /* SCSI LUN */ 1739 uint16_t control_flags; /* Control flags. */ 1740 #define CF_WRITE BIT_6 1741 #define CF_READ BIT_5 1742 #define CF_SIMPLE_TAG BIT_3 1743 #define CF_ORDERED_TAG BIT_2 1744 #define CF_HEAD_TAG BIT_1 1745 uint16_t reserved_1; 1746 uint16_t timeout; /* Command timeout. */ 1747 uint16_t dseg_count; /* Data segment count. */ 1748 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1749 uint32_t byte_count; /* Total byte count. */ 1750 uint32_t dseg_0_address; /* Data segment 0 address. */ 1751 uint32_t dseg_0_length; /* Data segment 0 length. */ 1752 uint32_t dseg_1_address; /* Data segment 1 address. */ 1753 uint32_t dseg_1_length; /* Data segment 1 length. */ 1754 uint32_t dseg_2_address; /* Data segment 2 address. */ 1755 uint32_t dseg_2_length; /* Data segment 2 length. */ 1756 } cmd_entry_t; 1757 1758 /* 1759 * ISP queue - 64-Bit addressing, command entry structure definition. 1760 */ 1761 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1762 typedef struct { 1763 uint8_t entry_type; /* Entry type. */ 1764 uint8_t entry_count; /* Entry count. */ 1765 uint8_t sys_define; /* System defined. */ 1766 uint8_t entry_status; /* Entry Status. */ 1767 uint32_t handle; /* System handle. */ 1768 target_id_t target; /* SCSI ID */ 1769 uint16_t lun; /* SCSI LUN */ 1770 uint16_t control_flags; /* Control flags. */ 1771 uint16_t reserved_1; 1772 uint16_t timeout; /* Command timeout. */ 1773 uint16_t dseg_count; /* Data segment count. */ 1774 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1775 uint32_t byte_count; /* Total byte count. */ 1776 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1777 uint32_t dseg_0_length; /* Data segment 0 length. */ 1778 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1779 uint32_t dseg_1_length; /* Data segment 1 length. */ 1780 } cmd_a64_entry_t, request_t; 1781 1782 /* 1783 * ISP queue - continuation entry structure definition. 1784 */ 1785 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1786 typedef struct { 1787 uint8_t entry_type; /* Entry type. */ 1788 uint8_t entry_count; /* Entry count. */ 1789 uint8_t sys_define; /* System defined. */ 1790 uint8_t entry_status; /* Entry Status. */ 1791 uint32_t reserved; 1792 uint32_t dseg_0_address; /* Data segment 0 address. */ 1793 uint32_t dseg_0_length; /* Data segment 0 length. */ 1794 uint32_t dseg_1_address; /* Data segment 1 address. */ 1795 uint32_t dseg_1_length; /* Data segment 1 length. */ 1796 uint32_t dseg_2_address; /* Data segment 2 address. */ 1797 uint32_t dseg_2_length; /* Data segment 2 length. */ 1798 uint32_t dseg_3_address; /* Data segment 3 address. */ 1799 uint32_t dseg_3_length; /* Data segment 3 length. */ 1800 uint32_t dseg_4_address; /* Data segment 4 address. */ 1801 uint32_t dseg_4_length; /* Data segment 4 length. */ 1802 uint32_t dseg_5_address; /* Data segment 5 address. */ 1803 uint32_t dseg_5_length; /* Data segment 5 length. */ 1804 uint32_t dseg_6_address; /* Data segment 6 address. */ 1805 uint32_t dseg_6_length; /* Data segment 6 length. */ 1806 } cont_entry_t; 1807 1808 /* 1809 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1810 */ 1811 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1812 typedef struct { 1813 uint8_t entry_type; /* Entry type. */ 1814 uint8_t entry_count; /* Entry count. */ 1815 uint8_t sys_define; /* System defined. */ 1816 uint8_t entry_status; /* Entry Status. */ 1817 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1818 uint32_t dseg_0_length; /* Data segment 0 length. */ 1819 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1820 uint32_t dseg_1_length; /* Data segment 1 length. */ 1821 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1822 uint32_t dseg_2_length; /* Data segment 2 length. */ 1823 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1824 uint32_t dseg_3_length; /* Data segment 3 length. */ 1825 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1826 uint32_t dseg_4_length; /* Data segment 4 length. */ 1827 } cont_a64_entry_t; 1828 1829 #define PO_MODE_DIF_INSERT 0 1830 #define PO_MODE_DIF_REMOVE 1 1831 #define PO_MODE_DIF_PASS 2 1832 #define PO_MODE_DIF_REPLACE 3 1833 #define PO_MODE_DIF_TCP_CKSUM 6 1834 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1835 #define PO_DISABLE_GUARD_CHECK BIT_4 1836 #define PO_DISABLE_INCR_REF_TAG BIT_5 1837 #define PO_DIS_HEADER_MODE BIT_7 1838 #define PO_ENABLE_DIF_BUNDLING BIT_8 1839 #define PO_DIS_FRAME_MODE BIT_9 1840 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1841 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1842 1843 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1844 #define PO_DIS_REF_TAG_REPL BIT_13 1845 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1846 #define PO_DIS_REF_TAG_VALD BIT_15 1847 1848 /* 1849 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1850 */ 1851 struct crc_context { 1852 uint32_t handle; /* System handle. */ 1853 __le32 ref_tag; 1854 __le16 app_tag; 1855 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1856 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1857 __le16 guard_seed; /* Initial Guard Seed */ 1858 __le16 prot_opts; /* Requested Data Protection Mode */ 1859 __le16 blk_size; /* Data size in bytes */ 1860 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1861 * only) */ 1862 __le32 byte_count; /* Total byte count/ total data 1863 * transfer count */ 1864 union { 1865 struct { 1866 uint32_t reserved_1; 1867 uint16_t reserved_2; 1868 uint16_t reserved_3; 1869 uint32_t reserved_4; 1870 uint32_t data_address[2]; 1871 uint32_t data_length; 1872 uint32_t reserved_5[2]; 1873 uint32_t reserved_6; 1874 } nobundling; 1875 struct { 1876 __le32 dif_byte_count; /* Total DIF byte 1877 * count */ 1878 uint16_t reserved_1; 1879 __le16 dseg_count; /* Data segment count */ 1880 uint32_t reserved_2; 1881 uint32_t data_address[2]; 1882 uint32_t data_length; 1883 uint32_t dif_address[2]; 1884 uint32_t dif_length; /* Data segment 0 1885 * length */ 1886 } bundling; 1887 } u; 1888 1889 struct fcp_cmnd fcp_cmnd; 1890 dma_addr_t crc_ctx_dma; 1891 /* List of DMA context transfers */ 1892 struct list_head dsd_list; 1893 1894 /* This structure should not exceed 512 bytes */ 1895 }; 1896 1897 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1898 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1899 1900 /* 1901 * ISP queue - status entry structure definition. 1902 */ 1903 #define STATUS_TYPE 0x03 /* Status entry. */ 1904 typedef struct { 1905 uint8_t entry_type; /* Entry type. */ 1906 uint8_t entry_count; /* Entry count. */ 1907 uint8_t sys_define; /* System defined. */ 1908 uint8_t entry_status; /* Entry Status. */ 1909 uint32_t handle; /* System handle. */ 1910 uint16_t scsi_status; /* SCSI status. */ 1911 uint16_t comp_status; /* Completion status. */ 1912 uint16_t state_flags; /* State flags. */ 1913 uint16_t status_flags; /* Status flags. */ 1914 uint16_t rsp_info_len; /* Response Info Length. */ 1915 uint16_t req_sense_length; /* Request sense data length. */ 1916 uint32_t residual_length; /* Residual transfer length. */ 1917 uint8_t rsp_info[8]; /* FCP response information. */ 1918 uint8_t req_sense_data[32]; /* Request sense data. */ 1919 } sts_entry_t; 1920 1921 /* 1922 * Status entry entry status 1923 */ 1924 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1925 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1926 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1927 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1928 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1929 #define RF_BUSY BIT_1 /* Busy */ 1930 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1931 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1932 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1933 RF_INV_E_TYPE) 1934 1935 /* 1936 * Status entry SCSI status bit definitions. 1937 */ 1938 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1939 #define SS_RESIDUAL_UNDER BIT_11 1940 #define SS_RESIDUAL_OVER BIT_10 1941 #define SS_SENSE_LEN_VALID BIT_9 1942 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1943 #define SS_SCSI_STATUS_BYTE 0xff 1944 1945 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1946 #define SS_BUSY_CONDITION BIT_3 1947 #define SS_CONDITION_MET BIT_2 1948 #define SS_CHECK_CONDITION BIT_1 1949 1950 /* 1951 * Status entry completion status 1952 */ 1953 #define CS_COMPLETE 0x0 /* No errors */ 1954 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1955 #define CS_DMA 0x2 /* A DMA direction error. */ 1956 #define CS_TRANSPORT 0x3 /* Transport error. */ 1957 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1958 #define CS_ABORTED 0x5 /* System aborted command. */ 1959 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1960 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1961 #define CS_DIF_ERROR 0xC /* DIF error detected */ 1962 1963 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1964 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1965 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1966 /* (selection timeout) */ 1967 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1968 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1969 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1970 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1971 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 1972 failure */ 1973 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1974 #define CS_UNKNOWN 0x81 /* Driver defined */ 1975 #define CS_RETRY 0x82 /* Driver defined */ 1976 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1977 1978 #define CS_BIDIR_RD_OVERRUN 0x700 1979 #define CS_BIDIR_RD_WR_OVERRUN 0x707 1980 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 1981 #define CS_BIDIR_RD_UNDERRUN 0x1500 1982 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 1983 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 1984 #define CS_BIDIR_DMA 0x200 1985 /* 1986 * Status entry status flags 1987 */ 1988 #define SF_ABTS_TERMINATED BIT_10 1989 #define SF_LOGOUT_SENT BIT_13 1990 1991 /* 1992 * ISP queue - status continuation entry structure definition. 1993 */ 1994 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1995 typedef struct { 1996 uint8_t entry_type; /* Entry type. */ 1997 uint8_t entry_count; /* Entry count. */ 1998 uint8_t sys_define; /* System defined. */ 1999 uint8_t entry_status; /* Entry Status. */ 2000 uint8_t data[60]; /* data */ 2001 } sts_cont_entry_t; 2002 2003 /* 2004 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 2005 * structure definition. 2006 */ 2007 #define STATUS_TYPE_21 0x21 /* Status entry. */ 2008 typedef struct { 2009 uint8_t entry_type; /* Entry type. */ 2010 uint8_t entry_count; /* Entry count. */ 2011 uint8_t handle_count; /* Handle count. */ 2012 uint8_t entry_status; /* Entry Status. */ 2013 uint32_t handle[15]; /* System handles. */ 2014 } sts21_entry_t; 2015 2016 /* 2017 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 2018 * structure definition. 2019 */ 2020 #define STATUS_TYPE_22 0x22 /* Status entry. */ 2021 typedef struct { 2022 uint8_t entry_type; /* Entry type. */ 2023 uint8_t entry_count; /* Entry count. */ 2024 uint8_t handle_count; /* Handle count. */ 2025 uint8_t entry_status; /* Entry Status. */ 2026 uint16_t handle[30]; /* System handles. */ 2027 } sts22_entry_t; 2028 2029 /* 2030 * ISP queue - marker entry structure definition. 2031 */ 2032 #define MARKER_TYPE 0x04 /* Marker entry. */ 2033 typedef struct { 2034 uint8_t entry_type; /* Entry type. */ 2035 uint8_t entry_count; /* Entry count. */ 2036 uint8_t handle_count; /* Handle count. */ 2037 uint8_t entry_status; /* Entry Status. */ 2038 uint32_t sys_define_2; /* System defined. */ 2039 target_id_t target; /* SCSI ID */ 2040 uint8_t modifier; /* Modifier (7-0). */ 2041 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 2042 #define MK_SYNC_ID 1 /* Synchronize ID */ 2043 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2044 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2045 /* clear port changed, */ 2046 /* use sequence number. */ 2047 uint8_t reserved_1; 2048 uint16_t sequence_number; /* Sequence number of event */ 2049 uint16_t lun; /* SCSI LUN */ 2050 uint8_t reserved_2[48]; 2051 } mrk_entry_t; 2052 2053 /* 2054 * ISP queue - Management Server entry structure definition. 2055 */ 2056 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2057 typedef struct { 2058 uint8_t entry_type; /* Entry type. */ 2059 uint8_t entry_count; /* Entry count. */ 2060 uint8_t handle_count; /* Handle count. */ 2061 uint8_t entry_status; /* Entry Status. */ 2062 uint32_t handle1; /* System handle. */ 2063 target_id_t loop_id; 2064 uint16_t status; 2065 uint16_t control_flags; /* Control flags. */ 2066 uint16_t reserved2; 2067 uint16_t timeout; 2068 uint16_t cmd_dsd_count; 2069 uint16_t total_dsd_count; 2070 uint8_t type; 2071 uint8_t r_ctl; 2072 uint16_t rx_id; 2073 uint16_t reserved3; 2074 uint32_t handle2; 2075 uint32_t rsp_bytecount; 2076 uint32_t req_bytecount; 2077 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 2078 uint32_t dseg_req_length; /* Data segment 0 length. */ 2079 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 2080 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 2081 } ms_iocb_entry_t; 2082 2083 2084 /* 2085 * ISP queue - Mailbox Command entry structure definition. 2086 */ 2087 #define MBX_IOCB_TYPE 0x39 2088 struct mbx_entry { 2089 uint8_t entry_type; 2090 uint8_t entry_count; 2091 uint8_t sys_define1; 2092 /* Use sys_define1 for source type */ 2093 #define SOURCE_SCSI 0x00 2094 #define SOURCE_IP 0x01 2095 #define SOURCE_VI 0x02 2096 #define SOURCE_SCTP 0x03 2097 #define SOURCE_MP 0x04 2098 #define SOURCE_MPIOCTL 0x05 2099 #define SOURCE_ASYNC_IOCB 0x07 2100 2101 uint8_t entry_status; 2102 2103 uint32_t handle; 2104 target_id_t loop_id; 2105 2106 uint16_t status; 2107 uint16_t state_flags; 2108 uint16_t status_flags; 2109 2110 uint32_t sys_define2[2]; 2111 2112 uint16_t mb0; 2113 uint16_t mb1; 2114 uint16_t mb2; 2115 uint16_t mb3; 2116 uint16_t mb6; 2117 uint16_t mb7; 2118 uint16_t mb9; 2119 uint16_t mb10; 2120 uint32_t reserved_2[2]; 2121 uint8_t node_name[WWN_SIZE]; 2122 uint8_t port_name[WWN_SIZE]; 2123 }; 2124 2125 #ifndef IMMED_NOTIFY_TYPE 2126 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2127 /* 2128 * ISP queue - immediate notify entry structure definition. 2129 * This is sent by the ISP to the Target driver. 2130 * This IOCB would have report of events sent by the 2131 * initiator, that needs to be handled by the target 2132 * driver immediately. 2133 */ 2134 struct imm_ntfy_from_isp { 2135 uint8_t entry_type; /* Entry type. */ 2136 uint8_t entry_count; /* Entry count. */ 2137 uint8_t sys_define; /* System defined. */ 2138 uint8_t entry_status; /* Entry Status. */ 2139 union { 2140 struct { 2141 uint32_t sys_define_2; /* System defined. */ 2142 target_id_t target; 2143 uint16_t lun; 2144 uint8_t target_id; 2145 uint8_t reserved_1; 2146 uint16_t status_modifier; 2147 uint16_t status; 2148 uint16_t task_flags; 2149 uint16_t seq_id; 2150 uint16_t srr_rx_id; 2151 uint32_t srr_rel_offs; 2152 uint16_t srr_ui; 2153 #define SRR_IU_DATA_IN 0x1 2154 #define SRR_IU_DATA_OUT 0x5 2155 #define SRR_IU_STATUS 0x7 2156 uint16_t srr_ox_id; 2157 uint8_t reserved_2[28]; 2158 } isp2x; 2159 struct { 2160 uint32_t reserved; 2161 uint16_t nport_handle; 2162 uint16_t reserved_2; 2163 uint16_t flags; 2164 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2165 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2166 uint16_t srr_rx_id; 2167 uint16_t status; 2168 uint8_t status_subcode; 2169 uint8_t fw_handle; 2170 uint32_t exchange_address; 2171 uint32_t srr_rel_offs; 2172 uint16_t srr_ui; 2173 uint16_t srr_ox_id; 2174 union { 2175 struct { 2176 uint8_t node_name[8]; 2177 } plogi; /* PLOGI/ADISC/PDISC */ 2178 struct { 2179 /* PRLI word 3 bit 0-15 */ 2180 uint16_t wd3_lo; 2181 uint8_t resv0[6]; 2182 } prli; 2183 struct { 2184 uint8_t port_id[3]; 2185 uint8_t resv1; 2186 uint16_t nport_handle; 2187 uint16_t resv2; 2188 } req_els; 2189 } u; 2190 uint8_t port_name[8]; 2191 uint8_t resv3[3]; 2192 uint8_t vp_index; 2193 uint32_t reserved_5; 2194 uint8_t port_id[3]; 2195 uint8_t reserved_6; 2196 } isp24; 2197 } u; 2198 uint16_t reserved_7; 2199 uint16_t ox_id; 2200 } __packed; 2201 #endif 2202 2203 /* 2204 * ISP request and response queue entry sizes 2205 */ 2206 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2207 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2208 2209 2210 2211 /* 2212 * Switch info gathering structure. 2213 */ 2214 typedef struct { 2215 port_id_t d_id; 2216 uint8_t node_name[WWN_SIZE]; 2217 uint8_t port_name[WWN_SIZE]; 2218 uint8_t fabric_port_name[WWN_SIZE]; 2219 uint16_t fp_speed; 2220 uint8_t fc4_type; 2221 uint8_t fc4f_nvme; /* nvme fc4 feature bits */ 2222 } sw_info_t; 2223 2224 /* FCP-4 types */ 2225 #define FC4_TYPE_FCP_SCSI 0x08 2226 #define FC4_TYPE_NVME 0x28 2227 #define FC4_TYPE_OTHER 0x0 2228 #define FC4_TYPE_UNKNOWN 0xff 2229 2230 /* mailbox command 4G & above */ 2231 struct mbx_24xx_entry { 2232 uint8_t entry_type; 2233 uint8_t entry_count; 2234 uint8_t sys_define1; 2235 uint8_t entry_status; 2236 uint32_t handle; 2237 uint16_t mb[28]; 2238 }; 2239 2240 #define IOCB_SIZE 64 2241 2242 /* 2243 * Fibre channel port type. 2244 */ 2245 typedef enum { 2246 FCT_UNKNOWN, 2247 FCT_RSCN, 2248 FCT_SWITCH, 2249 FCT_BROADCAST, 2250 FCT_INITIATOR, 2251 FCT_TARGET, 2252 FCT_NVME 2253 } fc_port_type_t; 2254 2255 enum qla_sess_deletion { 2256 QLA_SESS_DELETION_NONE = 0, 2257 QLA_SESS_DELETION_IN_PROGRESS, 2258 QLA_SESS_DELETED, 2259 }; 2260 2261 enum qlt_plogi_link_t { 2262 QLT_PLOGI_LINK_SAME_WWN, 2263 QLT_PLOGI_LINK_CONFLICT, 2264 QLT_PLOGI_LINK_MAX 2265 }; 2266 2267 struct qlt_plogi_ack_t { 2268 struct list_head list; 2269 struct imm_ntfy_from_isp iocb; 2270 port_id_t id; 2271 int ref_count; 2272 void *fcport; 2273 }; 2274 2275 struct ct_sns_desc { 2276 struct ct_sns_pkt *ct_sns; 2277 dma_addr_t ct_sns_dma; 2278 }; 2279 2280 enum discovery_state { 2281 DSC_DELETED, 2282 DSC_GNN_ID, 2283 DSC_GID_PN, 2284 DSC_GNL, 2285 DSC_LOGIN_PEND, 2286 DSC_LOGIN_FAILED, 2287 DSC_GPDB, 2288 DSC_UPD_FCPORT, 2289 DSC_LOGIN_COMPLETE, 2290 DSC_ADISC, 2291 DSC_DELETE_PEND, 2292 }; 2293 2294 enum login_state { /* FW control Target side */ 2295 DSC_LS_LLIOCB_SENT = 2, 2296 DSC_LS_PLOGI_PEND, 2297 DSC_LS_PLOGI_COMP, 2298 DSC_LS_PRLI_PEND, 2299 DSC_LS_PRLI_COMP, 2300 DSC_LS_PORT_UNAVAIL, 2301 DSC_LS_PRLO_PEND = 9, 2302 DSC_LS_LOGO_PEND, 2303 }; 2304 2305 enum fcport_mgt_event { 2306 FCME_RELOGIN = 1, 2307 FCME_RSCN, 2308 FCME_GIDPN_DONE, 2309 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */ 2310 FCME_PRLI_DONE, 2311 FCME_GNL_DONE, 2312 FCME_GPSC_DONE, 2313 FCME_GPDB_DONE, 2314 FCME_GPNID_DONE, 2315 FCME_GFFID_DONE, 2316 FCME_ADISC_DONE, 2317 FCME_GNNID_DONE, 2318 FCME_GFPNID_DONE, 2319 FCME_ELS_PLOGI_DONE, 2320 }; 2321 2322 enum rscn_addr_format { 2323 RSCN_PORT_ADDR, 2324 RSCN_AREA_ADDR, 2325 RSCN_DOM_ADDR, 2326 RSCN_FAB_ADDR, 2327 }; 2328 2329 /* 2330 * Fibre channel port structure. 2331 */ 2332 typedef struct fc_port { 2333 struct list_head list; 2334 struct scsi_qla_host *vha; 2335 2336 uint8_t node_name[WWN_SIZE]; 2337 uint8_t port_name[WWN_SIZE]; 2338 port_id_t d_id; 2339 uint16_t loop_id; 2340 uint16_t old_loop_id; 2341 2342 unsigned int conf_compl_supported:1; 2343 unsigned int deleted:2; 2344 unsigned int free_pending:1; 2345 unsigned int local:1; 2346 unsigned int logout_on_delete:1; 2347 unsigned int logo_ack_needed:1; 2348 unsigned int keep_nport_handle:1; 2349 unsigned int send_els_logo:1; 2350 unsigned int login_pause:1; 2351 unsigned int login_succ:1; 2352 unsigned int query:1; 2353 unsigned int id_changed:1; 2354 unsigned int rscn_rcvd:1; 2355 2356 struct work_struct nvme_del_work; 2357 struct completion nvme_del_done; 2358 uint32_t nvme_prli_service_param; 2359 #define NVME_PRLI_SP_CONF BIT_7 2360 #define NVME_PRLI_SP_INITIATOR BIT_5 2361 #define NVME_PRLI_SP_TARGET BIT_4 2362 #define NVME_PRLI_SP_DISCOVERY BIT_3 2363 uint8_t nvme_flag; 2364 #define NVME_FLAG_REGISTERED 4 2365 #define NVME_FLAG_DELETING 2 2366 #define NVME_FLAG_RESETTING 1 2367 2368 struct fc_port *conflict; 2369 unsigned char logout_completed; 2370 int generation; 2371 2372 struct se_session *se_sess; 2373 struct kref sess_kref; 2374 struct qla_tgt *tgt; 2375 unsigned long expires; 2376 struct list_head del_list_entry; 2377 struct work_struct free_work; 2378 2379 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2380 2381 uint16_t tgt_id; 2382 uint16_t old_tgt_id; 2383 2384 uint8_t fcp_prio; 2385 2386 uint8_t fabric_port_name[WWN_SIZE]; 2387 uint16_t fp_speed; 2388 2389 fc_port_type_t port_type; 2390 2391 atomic_t state; 2392 uint32_t flags; 2393 2394 int login_retry; 2395 2396 struct fc_rport *rport, *drport; 2397 u32 supported_classes; 2398 2399 uint8_t fc4_type; 2400 uint8_t fc4f_nvme; 2401 uint8_t scan_state; 2402 uint8_t n2n_flag; 2403 2404 unsigned long last_queue_full; 2405 unsigned long last_ramp_up; 2406 2407 uint16_t port_id; 2408 2409 struct nvme_fc_remote_port *nvme_remote_port; 2410 2411 unsigned long retry_delay_timestamp; 2412 struct qla_tgt_sess *tgt_session; 2413 struct ct_sns_desc ct_desc; 2414 enum discovery_state disc_state; 2415 enum login_state fw_login_state; 2416 unsigned long dm_login_expire; 2417 unsigned long plogi_nack_done_deadline; 2418 2419 u32 login_gen, last_login_gen; 2420 u32 rscn_gen, last_rscn_gen; 2421 u32 chip_reset; 2422 struct list_head gnl_entry; 2423 struct work_struct del_work; 2424 u8 iocb[IOCB_SIZE]; 2425 u8 current_login_state; 2426 u8 last_login_state; 2427 u16 n2n_link_reset_cnt; 2428 u16 n2n_chip_reset; 2429 } fc_port_t; 2430 2431 #define QLA_FCPORT_SCAN 1 2432 #define QLA_FCPORT_FOUND 2 2433 2434 struct event_arg { 2435 enum fcport_mgt_event event; 2436 fc_port_t *fcport; 2437 srb_t *sp; 2438 port_id_t id; 2439 u16 data[2], rc; 2440 u8 port_name[WWN_SIZE]; 2441 u32 iop[2]; 2442 }; 2443 2444 #include "qla_mr.h" 2445 2446 /* 2447 * Fibre channel port/lun states. 2448 */ 2449 #define FCS_UNCONFIGURED 1 2450 #define FCS_DEVICE_DEAD 2 2451 #define FCS_DEVICE_LOST 3 2452 #define FCS_ONLINE 4 2453 2454 static const char * const port_state_str[] = { 2455 "Unknown", 2456 "UNCONFIGURED", 2457 "DEAD", 2458 "LOST", 2459 "ONLINE" 2460 }; 2461 2462 /* 2463 * FC port flags. 2464 */ 2465 #define FCF_FABRIC_DEVICE BIT_0 2466 #define FCF_LOGIN_NEEDED BIT_1 2467 #define FCF_FCP2_DEVICE BIT_2 2468 #define FCF_ASYNC_SENT BIT_3 2469 #define FCF_CONF_COMP_SUPPORTED BIT_4 2470 #define FCF_ASYNC_ACTIVE BIT_5 2471 2472 /* No loop ID flag. */ 2473 #define FC_NO_LOOP_ID 0x1000 2474 2475 /* 2476 * FC-CT interface 2477 * 2478 * NOTE: All structures are big-endian in form. 2479 */ 2480 2481 #define CT_REJECT_RESPONSE 0x8001 2482 #define CT_ACCEPT_RESPONSE 0x8002 2483 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2484 #define CT_REASON_CANNOT_PERFORM 0x09 2485 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2486 #define CT_EXPL_ALREADY_REGISTERED 0x10 2487 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2488 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2489 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2490 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2491 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2492 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2493 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2494 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2495 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2496 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2497 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2498 2499 #define NS_N_PORT_TYPE 0x01 2500 #define NS_NL_PORT_TYPE 0x02 2501 #define NS_NX_PORT_TYPE 0x7F 2502 2503 #define GA_NXT_CMD 0x100 2504 #define GA_NXT_REQ_SIZE (16 + 4) 2505 #define GA_NXT_RSP_SIZE (16 + 620) 2506 2507 #define GPN_FT_CMD 0x172 2508 #define GPN_FT_REQ_SIZE (16 + 4) 2509 #define GNN_FT_CMD 0x173 2510 #define GNN_FT_REQ_SIZE (16 + 4) 2511 2512 #define GID_PT_CMD 0x1A1 2513 #define GID_PT_REQ_SIZE (16 + 4) 2514 2515 #define GPN_ID_CMD 0x112 2516 #define GPN_ID_REQ_SIZE (16 + 4) 2517 #define GPN_ID_RSP_SIZE (16 + 8) 2518 2519 #define GNN_ID_CMD 0x113 2520 #define GNN_ID_REQ_SIZE (16 + 4) 2521 #define GNN_ID_RSP_SIZE (16 + 8) 2522 2523 #define GFT_ID_CMD 0x117 2524 #define GFT_ID_REQ_SIZE (16 + 4) 2525 #define GFT_ID_RSP_SIZE (16 + 32) 2526 2527 #define GID_PN_CMD 0x121 2528 #define GID_PN_REQ_SIZE (16 + 8) 2529 #define GID_PN_RSP_SIZE (16 + 4) 2530 2531 #define RFT_ID_CMD 0x217 2532 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2533 #define RFT_ID_RSP_SIZE 16 2534 2535 #define RFF_ID_CMD 0x21F 2536 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2537 #define RFF_ID_RSP_SIZE 16 2538 2539 #define RNN_ID_CMD 0x213 2540 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2541 #define RNN_ID_RSP_SIZE 16 2542 2543 #define RSNN_NN_CMD 0x239 2544 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2545 #define RSNN_NN_RSP_SIZE 16 2546 2547 #define GFPN_ID_CMD 0x11C 2548 #define GFPN_ID_REQ_SIZE (16 + 4) 2549 #define GFPN_ID_RSP_SIZE (16 + 8) 2550 2551 #define GPSC_CMD 0x127 2552 #define GPSC_REQ_SIZE (16 + 8) 2553 #define GPSC_RSP_SIZE (16 + 2 + 2) 2554 2555 #define GFF_ID_CMD 0x011F 2556 #define GFF_ID_REQ_SIZE (16 + 4) 2557 #define GFF_ID_RSP_SIZE (16 + 128) 2558 2559 /* 2560 * HBA attribute types. 2561 */ 2562 #define FDMI_HBA_ATTR_COUNT 9 2563 #define FDMIV2_HBA_ATTR_COUNT 17 2564 #define FDMI_HBA_NODE_NAME 0x1 2565 #define FDMI_HBA_MANUFACTURER 0x2 2566 #define FDMI_HBA_SERIAL_NUMBER 0x3 2567 #define FDMI_HBA_MODEL 0x4 2568 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2569 #define FDMI_HBA_HARDWARE_VERSION 0x6 2570 #define FDMI_HBA_DRIVER_VERSION 0x7 2571 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2572 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2573 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2574 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2575 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2576 #define FDMI_HBA_VENDOR_ID 0xd 2577 #define FDMI_HBA_NUM_PORTS 0xe 2578 #define FDMI_HBA_FABRIC_NAME 0xf 2579 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2580 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0 2581 2582 struct ct_fdmi_hba_attr { 2583 uint16_t type; 2584 uint16_t len; 2585 union { 2586 uint8_t node_name[WWN_SIZE]; 2587 uint8_t manufacturer[64]; 2588 uint8_t serial_num[32]; 2589 uint8_t model[16+1]; 2590 uint8_t model_desc[80]; 2591 uint8_t hw_version[32]; 2592 uint8_t driver_version[32]; 2593 uint8_t orom_version[16]; 2594 uint8_t fw_version[32]; 2595 uint8_t os_version[128]; 2596 uint32_t max_ct_len; 2597 } a; 2598 }; 2599 2600 struct ct_fdmi_hba_attributes { 2601 uint32_t count; 2602 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2603 }; 2604 2605 struct ct_fdmiv2_hba_attr { 2606 uint16_t type; 2607 uint16_t len; 2608 union { 2609 uint8_t node_name[WWN_SIZE]; 2610 uint8_t manufacturer[64]; 2611 uint8_t serial_num[32]; 2612 uint8_t model[16+1]; 2613 uint8_t model_desc[80]; 2614 uint8_t hw_version[16]; 2615 uint8_t driver_version[32]; 2616 uint8_t orom_version[16]; 2617 uint8_t fw_version[32]; 2618 uint8_t os_version[128]; 2619 uint32_t max_ct_len; 2620 uint8_t sym_name[256]; 2621 uint32_t vendor_id; 2622 uint32_t num_ports; 2623 uint8_t fabric_name[WWN_SIZE]; 2624 uint8_t bios_name[32]; 2625 uint8_t vendor_identifier[8]; 2626 } a; 2627 }; 2628 2629 struct ct_fdmiv2_hba_attributes { 2630 uint32_t count; 2631 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT]; 2632 }; 2633 2634 /* 2635 * Port attribute types. 2636 */ 2637 #define FDMI_PORT_ATTR_COUNT 6 2638 #define FDMIV2_PORT_ATTR_COUNT 16 2639 #define FDMI_PORT_FC4_TYPES 0x1 2640 #define FDMI_PORT_SUPPORT_SPEED 0x2 2641 #define FDMI_PORT_CURRENT_SPEED 0x3 2642 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2643 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2644 #define FDMI_PORT_HOST_NAME 0x6 2645 #define FDMI_PORT_NODE_NAME 0x7 2646 #define FDMI_PORT_NAME 0x8 2647 #define FDMI_PORT_SYM_NAME 0x9 2648 #define FDMI_PORT_TYPE 0xa 2649 #define FDMI_PORT_SUPP_COS 0xb 2650 #define FDMI_PORT_FABRIC_NAME 0xc 2651 #define FDMI_PORT_FC4_TYPE 0xd 2652 #define FDMI_PORT_STATE 0x101 2653 #define FDMI_PORT_COUNT 0x102 2654 #define FDMI_PORT_ID 0x103 2655 2656 #define FDMI_PORT_SPEED_1GB 0x1 2657 #define FDMI_PORT_SPEED_2GB 0x2 2658 #define FDMI_PORT_SPEED_10GB 0x4 2659 #define FDMI_PORT_SPEED_4GB 0x8 2660 #define FDMI_PORT_SPEED_8GB 0x10 2661 #define FDMI_PORT_SPEED_16GB 0x20 2662 #define FDMI_PORT_SPEED_32GB 0x40 2663 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2664 2665 #define FC_CLASS_2 0x04 2666 #define FC_CLASS_3 0x08 2667 #define FC_CLASS_2_3 0x0C 2668 2669 struct ct_fdmiv2_port_attr { 2670 uint16_t type; 2671 uint16_t len; 2672 union { 2673 uint8_t fc4_types[32]; 2674 uint32_t sup_speed; 2675 uint32_t cur_speed; 2676 uint32_t max_frame_size; 2677 uint8_t os_dev_name[32]; 2678 uint8_t host_name[256]; 2679 uint8_t node_name[WWN_SIZE]; 2680 uint8_t port_name[WWN_SIZE]; 2681 uint8_t port_sym_name[128]; 2682 uint32_t port_type; 2683 uint32_t port_supported_cos; 2684 uint8_t fabric_name[WWN_SIZE]; 2685 uint8_t port_fc4_type[32]; 2686 uint32_t port_state; 2687 uint32_t num_ports; 2688 uint32_t port_id; 2689 } a; 2690 }; 2691 2692 /* 2693 * Port Attribute Block. 2694 */ 2695 struct ct_fdmiv2_port_attributes { 2696 uint32_t count; 2697 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT]; 2698 }; 2699 2700 struct ct_fdmi_port_attr { 2701 uint16_t type; 2702 uint16_t len; 2703 union { 2704 uint8_t fc4_types[32]; 2705 uint32_t sup_speed; 2706 uint32_t cur_speed; 2707 uint32_t max_frame_size; 2708 uint8_t os_dev_name[32]; 2709 uint8_t host_name[256]; 2710 } a; 2711 }; 2712 2713 struct ct_fdmi_port_attributes { 2714 uint32_t count; 2715 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2716 }; 2717 2718 /* FDMI definitions. */ 2719 #define GRHL_CMD 0x100 2720 #define GHAT_CMD 0x101 2721 #define GRPL_CMD 0x102 2722 #define GPAT_CMD 0x110 2723 2724 #define RHBA_CMD 0x200 2725 #define RHBA_RSP_SIZE 16 2726 2727 #define RHAT_CMD 0x201 2728 #define RPRT_CMD 0x210 2729 2730 #define RPA_CMD 0x211 2731 #define RPA_RSP_SIZE 16 2732 2733 #define DHBA_CMD 0x300 2734 #define DHBA_REQ_SIZE (16 + 8) 2735 #define DHBA_RSP_SIZE 16 2736 2737 #define DHAT_CMD 0x301 2738 #define DPRT_CMD 0x310 2739 #define DPA_CMD 0x311 2740 2741 /* CT command header -- request/response common fields */ 2742 struct ct_cmd_hdr { 2743 uint8_t revision; 2744 uint8_t in_id[3]; 2745 uint8_t gs_type; 2746 uint8_t gs_subtype; 2747 uint8_t options; 2748 uint8_t reserved; 2749 }; 2750 2751 /* CT command request */ 2752 struct ct_sns_req { 2753 struct ct_cmd_hdr header; 2754 uint16_t command; 2755 uint16_t max_rsp_size; 2756 uint8_t fragment_id; 2757 uint8_t reserved[3]; 2758 2759 union { 2760 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2761 struct { 2762 uint8_t reserved; 2763 uint8_t port_id[3]; 2764 } port_id; 2765 2766 struct { 2767 uint8_t reserved; 2768 uint8_t domain; 2769 uint8_t area; 2770 uint8_t port_type; 2771 } gpn_ft; 2772 2773 struct { 2774 uint8_t port_type; 2775 uint8_t domain; 2776 uint8_t area; 2777 uint8_t reserved; 2778 } gid_pt; 2779 2780 struct { 2781 uint8_t reserved; 2782 uint8_t port_id[3]; 2783 uint8_t fc4_types[32]; 2784 } rft_id; 2785 2786 struct { 2787 uint8_t reserved; 2788 uint8_t port_id[3]; 2789 uint16_t reserved2; 2790 uint8_t fc4_feature; 2791 uint8_t fc4_type; 2792 } rff_id; 2793 2794 struct { 2795 uint8_t reserved; 2796 uint8_t port_id[3]; 2797 uint8_t node_name[8]; 2798 } rnn_id; 2799 2800 struct { 2801 uint8_t node_name[8]; 2802 uint8_t name_len; 2803 uint8_t sym_node_name[255]; 2804 } rsnn_nn; 2805 2806 struct { 2807 uint8_t hba_identifier[8]; 2808 } ghat; 2809 2810 struct { 2811 uint8_t hba_identifier[8]; 2812 uint32_t entry_count; 2813 uint8_t port_name[8]; 2814 struct ct_fdmi_hba_attributes attrs; 2815 } rhba; 2816 2817 struct { 2818 uint8_t hba_identifier[8]; 2819 uint32_t entry_count; 2820 uint8_t port_name[8]; 2821 struct ct_fdmiv2_hba_attributes attrs; 2822 } rhba2; 2823 2824 struct { 2825 uint8_t hba_identifier[8]; 2826 struct ct_fdmi_hba_attributes attrs; 2827 } rhat; 2828 2829 struct { 2830 uint8_t port_name[8]; 2831 struct ct_fdmi_port_attributes attrs; 2832 } rpa; 2833 2834 struct { 2835 uint8_t port_name[8]; 2836 struct ct_fdmiv2_port_attributes attrs; 2837 } rpa2; 2838 2839 struct { 2840 uint8_t port_name[8]; 2841 } dhba; 2842 2843 struct { 2844 uint8_t port_name[8]; 2845 } dhat; 2846 2847 struct { 2848 uint8_t port_name[8]; 2849 } dprt; 2850 2851 struct { 2852 uint8_t port_name[8]; 2853 } dpa; 2854 2855 struct { 2856 uint8_t port_name[8]; 2857 } gpsc; 2858 2859 struct { 2860 uint8_t reserved; 2861 uint8_t port_id[3]; 2862 } gff_id; 2863 2864 struct { 2865 uint8_t port_name[8]; 2866 } gid_pn; 2867 } req; 2868 }; 2869 2870 /* CT command response header */ 2871 struct ct_rsp_hdr { 2872 struct ct_cmd_hdr header; 2873 uint16_t response; 2874 uint16_t residual; 2875 uint8_t fragment_id; 2876 uint8_t reason_code; 2877 uint8_t explanation_code; 2878 uint8_t vendor_unique; 2879 }; 2880 2881 struct ct_sns_gid_pt_data { 2882 uint8_t control_byte; 2883 uint8_t port_id[3]; 2884 }; 2885 2886 /* It's the same for both GPN_FT and GNN_FT */ 2887 struct ct_sns_gpnft_rsp { 2888 struct { 2889 struct ct_cmd_hdr header; 2890 uint16_t response; 2891 uint16_t residual; 2892 uint8_t fragment_id; 2893 uint8_t reason_code; 2894 uint8_t explanation_code; 2895 uint8_t vendor_unique; 2896 }; 2897 /* Assume the largest number of targets for the union */ 2898 struct ct_sns_gpn_ft_data { 2899 u8 control_byte; 2900 u8 port_id[3]; 2901 u32 reserved; 2902 u8 port_name[8]; 2903 } entries[1]; 2904 }; 2905 2906 /* CT command response */ 2907 struct ct_sns_rsp { 2908 struct ct_rsp_hdr header; 2909 2910 union { 2911 struct { 2912 uint8_t port_type; 2913 uint8_t port_id[3]; 2914 uint8_t port_name[8]; 2915 uint8_t sym_port_name_len; 2916 uint8_t sym_port_name[255]; 2917 uint8_t node_name[8]; 2918 uint8_t sym_node_name_len; 2919 uint8_t sym_node_name[255]; 2920 uint8_t init_proc_assoc[8]; 2921 uint8_t node_ip_addr[16]; 2922 uint8_t class_of_service[4]; 2923 uint8_t fc4_types[32]; 2924 uint8_t ip_address[16]; 2925 uint8_t fabric_port_name[8]; 2926 uint8_t reserved; 2927 uint8_t hard_address[3]; 2928 } ga_nxt; 2929 2930 struct { 2931 /* Assume the largest number of targets for the union */ 2932 struct ct_sns_gid_pt_data 2933 entries[MAX_FIBRE_DEVICES_MAX]; 2934 } gid_pt; 2935 2936 struct { 2937 uint8_t port_name[8]; 2938 } gpn_id; 2939 2940 struct { 2941 uint8_t node_name[8]; 2942 } gnn_id; 2943 2944 struct { 2945 uint8_t fc4_types[32]; 2946 } gft_id; 2947 2948 struct { 2949 uint32_t entry_count; 2950 uint8_t port_name[8]; 2951 struct ct_fdmi_hba_attributes attrs; 2952 } ghat; 2953 2954 struct { 2955 uint8_t port_name[8]; 2956 } gfpn_id; 2957 2958 struct { 2959 uint16_t speeds; 2960 uint16_t speed; 2961 } gpsc; 2962 2963 #define GFF_FCP_SCSI_OFFSET 7 2964 #define GFF_NVME_OFFSET 23 /* type = 28h */ 2965 struct { 2966 uint8_t fc4_features[128]; 2967 } gff_id; 2968 struct { 2969 uint8_t reserved; 2970 uint8_t port_id[3]; 2971 } gid_pn; 2972 } rsp; 2973 }; 2974 2975 struct ct_sns_pkt { 2976 union { 2977 struct ct_sns_req req; 2978 struct ct_sns_rsp rsp; 2979 } p; 2980 }; 2981 2982 struct ct_sns_gpnft_pkt { 2983 union { 2984 struct ct_sns_req req; 2985 struct ct_sns_gpnft_rsp rsp; 2986 } p; 2987 }; 2988 2989 enum scan_flags_t { 2990 SF_SCANNING = BIT_0, 2991 SF_QUEUED = BIT_1, 2992 }; 2993 2994 enum fc4type_t { 2995 FS_FC4TYPE_FCP = BIT_0, 2996 FS_FC4TYPE_NVME = BIT_1, 2997 }; 2998 2999 struct fab_scan_rp { 3000 port_id_t id; 3001 enum fc4type_t fc4type; 3002 u8 port_name[8]; 3003 u8 node_name[8]; 3004 }; 3005 3006 struct fab_scan { 3007 struct fab_scan_rp *l; 3008 u32 size; 3009 u16 scan_retry; 3010 #define MAX_SCAN_RETRIES 5 3011 enum scan_flags_t scan_flags; 3012 struct delayed_work scan_work; 3013 }; 3014 3015 /* 3016 * SNS command structures -- for 2200 compatibility. 3017 */ 3018 #define RFT_ID_SNS_SCMD_LEN 22 3019 #define RFT_ID_SNS_CMD_SIZE 60 3020 #define RFT_ID_SNS_DATA_SIZE 16 3021 3022 #define RNN_ID_SNS_SCMD_LEN 10 3023 #define RNN_ID_SNS_CMD_SIZE 36 3024 #define RNN_ID_SNS_DATA_SIZE 16 3025 3026 #define GA_NXT_SNS_SCMD_LEN 6 3027 #define GA_NXT_SNS_CMD_SIZE 28 3028 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 3029 3030 #define GID_PT_SNS_SCMD_LEN 6 3031 #define GID_PT_SNS_CMD_SIZE 28 3032 /* 3033 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 3034 * adapters. 3035 */ 3036 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 3037 3038 #define GPN_ID_SNS_SCMD_LEN 6 3039 #define GPN_ID_SNS_CMD_SIZE 28 3040 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 3041 3042 #define GNN_ID_SNS_SCMD_LEN 6 3043 #define GNN_ID_SNS_CMD_SIZE 28 3044 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 3045 3046 struct sns_cmd_pkt { 3047 union { 3048 struct { 3049 uint16_t buffer_length; 3050 uint16_t reserved_1; 3051 uint32_t buffer_address[2]; 3052 uint16_t subcommand_length; 3053 uint16_t reserved_2; 3054 uint16_t subcommand; 3055 uint16_t size; 3056 uint32_t reserved_3; 3057 uint8_t param[36]; 3058 } cmd; 3059 3060 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 3061 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 3062 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 3063 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 3064 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 3065 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 3066 } p; 3067 }; 3068 3069 struct fw_blob { 3070 char *name; 3071 uint32_t segs[4]; 3072 const struct firmware *fw; 3073 }; 3074 3075 /* Return data from MBC_GET_ID_LIST call. */ 3076 struct gid_list_info { 3077 uint8_t al_pa; 3078 uint8_t area; 3079 uint8_t domain; 3080 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 3081 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 3082 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 3083 }; 3084 3085 /* NPIV */ 3086 typedef struct vport_info { 3087 uint8_t port_name[WWN_SIZE]; 3088 uint8_t node_name[WWN_SIZE]; 3089 int vp_id; 3090 uint16_t loop_id; 3091 unsigned long host_no; 3092 uint8_t port_id[3]; 3093 int loop_state; 3094 } vport_info_t; 3095 3096 typedef struct vport_params { 3097 uint8_t port_name[WWN_SIZE]; 3098 uint8_t node_name[WWN_SIZE]; 3099 uint32_t options; 3100 #define VP_OPTS_RETRY_ENABLE BIT_0 3101 #define VP_OPTS_VP_DISABLE BIT_1 3102 } vport_params_t; 3103 3104 /* NPIV - return codes of VP create and modify */ 3105 #define VP_RET_CODE_OK 0 3106 #define VP_RET_CODE_FATAL 1 3107 #define VP_RET_CODE_WRONG_ID 2 3108 #define VP_RET_CODE_WWPN 3 3109 #define VP_RET_CODE_RESOURCES 4 3110 #define VP_RET_CODE_NO_MEM 5 3111 #define VP_RET_CODE_NOT_FOUND 6 3112 3113 struct qla_hw_data; 3114 struct rsp_que; 3115 /* 3116 * ISP operations 3117 */ 3118 struct isp_operations { 3119 3120 int (*pci_config) (struct scsi_qla_host *); 3121 void (*reset_chip) (struct scsi_qla_host *); 3122 int (*chip_diag) (struct scsi_qla_host *); 3123 void (*config_rings) (struct scsi_qla_host *); 3124 void (*reset_adapter) (struct scsi_qla_host *); 3125 int (*nvram_config) (struct scsi_qla_host *); 3126 void (*update_fw_options) (struct scsi_qla_host *); 3127 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3128 3129 char * (*pci_info_str) (struct scsi_qla_host *, char *); 3130 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3131 3132 irq_handler_t intr_handler; 3133 void (*enable_intrs) (struct qla_hw_data *); 3134 void (*disable_intrs) (struct qla_hw_data *); 3135 3136 int (*abort_command) (srb_t *); 3137 int (*target_reset) (struct fc_port *, uint64_t, int); 3138 int (*lun_reset) (struct fc_port *, uint64_t, int); 3139 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3140 uint8_t, uint8_t, uint16_t *, uint8_t); 3141 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3142 uint8_t, uint8_t); 3143 3144 uint16_t (*calc_req_entries) (uint16_t); 3145 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3146 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3147 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3148 uint32_t); 3149 3150 uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *, 3151 uint32_t, uint32_t); 3152 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 3153 uint32_t); 3154 3155 void (*fw_dump) (struct scsi_qla_host *, int); 3156 3157 int (*beacon_on) (struct scsi_qla_host *); 3158 int (*beacon_off) (struct scsi_qla_host *); 3159 void (*beacon_blink) (struct scsi_qla_host *); 3160 3161 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 3162 uint32_t, uint32_t); 3163 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 3164 uint32_t); 3165 3166 int (*get_flash_version) (struct scsi_qla_host *, void *); 3167 int (*start_scsi) (srb_t *); 3168 int (*start_scsi_mq) (srb_t *); 3169 int (*abort_isp) (struct scsi_qla_host *); 3170 int (*iospace_config)(struct qla_hw_data*); 3171 int (*initialize_adapter)(struct scsi_qla_host *); 3172 }; 3173 3174 /* MSI-X Support *************************************************************/ 3175 3176 #define QLA_MSIX_CHIP_REV_24XX 3 3177 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3178 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3179 3180 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3181 #define QLA_MSIX_RSP_Q 0x01 3182 #define QLA_ATIO_VECTOR 0x02 3183 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3184 3185 #define QLA_MIDX_DEFAULT 0 3186 #define QLA_MIDX_RSP_Q 1 3187 #define QLA_PCI_MSIX_CONTROL 0xa2 3188 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3189 3190 struct scsi_qla_host; 3191 3192 3193 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3194 3195 struct qla_msix_entry { 3196 int have_irq; 3197 int in_use; 3198 uint32_t vector; 3199 uint16_t entry; 3200 char name[30]; 3201 void *handle; 3202 int cpuid; 3203 }; 3204 3205 #define WATCH_INTERVAL 1 /* number of seconds */ 3206 3207 /* Work events. */ 3208 enum qla_work_type { 3209 QLA_EVT_AEN, 3210 QLA_EVT_IDC_ACK, 3211 QLA_EVT_ASYNC_LOGIN, 3212 QLA_EVT_ASYNC_LOGOUT, 3213 QLA_EVT_ASYNC_LOGOUT_DONE, 3214 QLA_EVT_ASYNC_ADISC, 3215 QLA_EVT_ASYNC_ADISC_DONE, 3216 QLA_EVT_UEVENT, 3217 QLA_EVT_AENFX, 3218 QLA_EVT_GIDPN, 3219 QLA_EVT_GPNID, 3220 QLA_EVT_UNMAP, 3221 QLA_EVT_NEW_SESS, 3222 QLA_EVT_GPDB, 3223 QLA_EVT_PRLI, 3224 QLA_EVT_GPSC, 3225 QLA_EVT_UPD_FCPORT, 3226 QLA_EVT_GNL, 3227 QLA_EVT_NACK, 3228 QLA_EVT_RELOGIN, 3229 QLA_EVT_ASYNC_PRLO, 3230 QLA_EVT_ASYNC_PRLO_DONE, 3231 QLA_EVT_GPNFT, 3232 QLA_EVT_GPNFT_DONE, 3233 QLA_EVT_GNNFT_DONE, 3234 QLA_EVT_GNNID, 3235 QLA_EVT_GFPNID, 3236 QLA_EVT_SP_RETRY, 3237 QLA_EVT_IIDMA, 3238 QLA_EVT_ELS_PLOGI, 3239 }; 3240 3241 3242 struct qla_work_evt { 3243 struct list_head list; 3244 enum qla_work_type type; 3245 u32 flags; 3246 #define QLA_EVT_FLAG_FREE 0x1 3247 3248 union { 3249 struct { 3250 enum fc_host_event_code code; 3251 u32 data; 3252 } aen; 3253 struct { 3254 #define QLA_IDC_ACK_REGS 7 3255 uint16_t mb[QLA_IDC_ACK_REGS]; 3256 } idc_ack; 3257 struct { 3258 struct fc_port *fcport; 3259 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3260 u16 data[2]; 3261 } logio; 3262 struct { 3263 u32 code; 3264 #define QLA_UEVENT_CODE_FW_DUMP 0 3265 } uevent; 3266 struct { 3267 uint32_t evtcode; 3268 uint32_t mbx[8]; 3269 uint32_t count; 3270 } aenfx; 3271 struct { 3272 srb_t *sp; 3273 } iosb; 3274 struct { 3275 port_id_t id; 3276 } gpnid; 3277 struct { 3278 port_id_t id; 3279 u8 port_name[8]; 3280 u8 node_name[8]; 3281 void *pla; 3282 u8 fc4_type; 3283 } new_sess; 3284 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */ 3285 fc_port_t *fcport; 3286 u8 opt; 3287 } fcport; 3288 struct { 3289 fc_port_t *fcport; 3290 u8 iocb[IOCB_SIZE]; 3291 int type; 3292 } nack; 3293 struct { 3294 u8 fc4_type; 3295 srb_t *sp; 3296 } gpnft; 3297 } u; 3298 }; 3299 3300 struct qla_chip_state_84xx { 3301 struct list_head list; 3302 struct kref kref; 3303 3304 void *bus; 3305 spinlock_t access_lock; 3306 struct mutex fw_update_mutex; 3307 uint32_t fw_update; 3308 uint32_t op_fw_version; 3309 uint32_t op_fw_size; 3310 uint32_t op_fw_seq_size; 3311 uint32_t diag_fw_version; 3312 uint32_t gold_fw_version; 3313 }; 3314 3315 struct qla_dif_statistics { 3316 uint64_t dif_input_bytes; 3317 uint64_t dif_output_bytes; 3318 uint64_t dif_input_requests; 3319 uint64_t dif_output_requests; 3320 uint32_t dif_guard_err; 3321 uint32_t dif_ref_tag_err; 3322 uint32_t dif_app_tag_err; 3323 }; 3324 3325 struct qla_statistics { 3326 uint32_t total_isp_aborts; 3327 uint64_t input_bytes; 3328 uint64_t output_bytes; 3329 uint64_t input_requests; 3330 uint64_t output_requests; 3331 uint32_t control_requests; 3332 3333 uint64_t jiffies_at_last_reset; 3334 uint32_t stat_max_pend_cmds; 3335 uint32_t stat_max_qfull_cmds_alloc; 3336 uint32_t stat_max_qfull_cmds_dropped; 3337 3338 struct qla_dif_statistics qla_dif_stats; 3339 }; 3340 3341 struct bidi_statistics { 3342 unsigned long long io_count; 3343 unsigned long long transfer_bytes; 3344 }; 3345 3346 struct qla_tc_param { 3347 struct scsi_qla_host *vha; 3348 uint32_t blk_sz; 3349 uint32_t bufflen; 3350 struct scatterlist *sg; 3351 struct scatterlist *prot_sg; 3352 struct crc_context *ctx; 3353 uint8_t *ctx_dsd_alloced; 3354 }; 3355 3356 /* Multi queue support */ 3357 #define MBC_INITIALIZE_MULTIQ 0x1f 3358 #define QLA_QUE_PAGE 0X1000 3359 #define QLA_MQ_SIZE 32 3360 #define QLA_MAX_QUEUES 256 3361 #define ISP_QUE_REG(ha, id) \ 3362 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \ 3363 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3364 ((void __iomem *)ha->iobase)) 3365 #define QLA_REQ_QUE_ID(tag) \ 3366 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3367 #define QLA_DEFAULT_QUE_QOS 5 3368 #define QLA_PRECONFIG_VPORTS 32 3369 #define QLA_MAX_VPORTS_QLA24XX 128 3370 #define QLA_MAX_VPORTS_QLA25XX 256 3371 3372 struct qla_tgt_counters { 3373 uint64_t qla_core_sbt_cmd; 3374 uint64_t core_qla_que_buf; 3375 uint64_t qla_core_ret_ctio; 3376 uint64_t core_qla_snd_status; 3377 uint64_t qla_core_ret_sta_ctio; 3378 uint64_t core_qla_free_cmd; 3379 uint64_t num_q_full_sent; 3380 uint64_t num_alloc_iocb_failed; 3381 uint64_t num_term_xchg_sent; 3382 }; 3383 3384 struct qla_qpair; 3385 3386 /* Response queue data structure */ 3387 struct rsp_que { 3388 dma_addr_t dma; 3389 response_t *ring; 3390 response_t *ring_ptr; 3391 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 3392 uint32_t __iomem *rsp_q_out; 3393 uint16_t ring_index; 3394 uint16_t out_ptr; 3395 uint16_t *in_ptr; /* queue shadow in index */ 3396 uint16_t length; 3397 uint16_t options; 3398 uint16_t rid; 3399 uint16_t id; 3400 uint16_t vp_idx; 3401 struct qla_hw_data *hw; 3402 struct qla_msix_entry *msix; 3403 struct req_que *req; 3404 srb_t *status_srb; /* status continuation entry */ 3405 struct qla_qpair *qpair; 3406 3407 dma_addr_t dma_fx00; 3408 response_t *ring_fx00; 3409 uint16_t length_fx00; 3410 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3411 }; 3412 3413 /* Request queue data structure */ 3414 struct req_que { 3415 dma_addr_t dma; 3416 request_t *ring; 3417 request_t *ring_ptr; 3418 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 3419 uint32_t __iomem *req_q_out; 3420 uint16_t ring_index; 3421 uint16_t in_ptr; 3422 uint16_t *out_ptr; /* queue shadow out index */ 3423 uint16_t cnt; 3424 uint16_t length; 3425 uint16_t options; 3426 uint16_t rid; 3427 uint16_t id; 3428 uint16_t qos; 3429 uint16_t vp_idx; 3430 struct rsp_que *rsp; 3431 srb_t **outstanding_cmds; 3432 uint32_t current_outstanding_cmd; 3433 uint16_t num_outstanding_cmds; 3434 int max_q_depth; 3435 3436 dma_addr_t dma_fx00; 3437 request_t *ring_fx00; 3438 uint16_t length_fx00; 3439 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3440 }; 3441 3442 /*Queue pair data structure */ 3443 struct qla_qpair { 3444 spinlock_t qp_lock; 3445 atomic_t ref_count; 3446 uint32_t lun_cnt; 3447 /* 3448 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3449 * legacy code. For other Qpair(s), it will point at qp_lock. 3450 */ 3451 spinlock_t *qp_lock_ptr; 3452 struct scsi_qla_host *vha; 3453 u32 chip_reset; 3454 3455 /* distill these fields down to 'online=0/1' 3456 * ha->flags.eeh_busy 3457 * ha->flags.pci_channel_io_perm_failure 3458 * base_vha->loop_state 3459 */ 3460 uint32_t online:1; 3461 /* move vha->flags.difdix_supported here */ 3462 uint32_t difdix_supported:1; 3463 uint32_t delete_in_progress:1; 3464 uint32_t fw_started:1; 3465 uint32_t enable_class_2:1; 3466 uint32_t enable_explicit_conf:1; 3467 uint32_t use_shadow_reg:1; 3468 3469 uint16_t id; /* qp number used with FW */ 3470 uint16_t vp_idx; /* vport ID */ 3471 mempool_t *srb_mempool; 3472 3473 struct pci_dev *pdev; 3474 void (*reqq_start_iocbs)(struct qla_qpair *); 3475 3476 /* to do: New driver: move queues to here instead of pointers */ 3477 struct req_que *req; 3478 struct rsp_que *rsp; 3479 struct atio_que *atio; 3480 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3481 struct qla_hw_data *hw; 3482 struct work_struct q_work; 3483 struct list_head qp_list_elem; /* vha->qp_list */ 3484 struct list_head hints_list; 3485 uint16_t cpuid; 3486 struct qla_tgt_counters tgt_counters; 3487 }; 3488 3489 /* Place holder for FW buffer parameters */ 3490 struct qlfc_fw { 3491 void *fw_buf; 3492 dma_addr_t fw_dma; 3493 uint32_t len; 3494 }; 3495 3496 struct scsi_qlt_host { 3497 void *target_lport_ptr; 3498 struct mutex tgt_mutex; 3499 struct mutex tgt_host_action_mutex; 3500 struct qla_tgt *qla_tgt; 3501 }; 3502 3503 struct qlt_hw_data { 3504 /* Protected by hw lock */ 3505 uint32_t node_name_set:1; 3506 3507 dma_addr_t atio_dma; /* Physical address. */ 3508 struct atio *atio_ring; /* Base virtual address */ 3509 struct atio *atio_ring_ptr; /* Current address. */ 3510 uint16_t atio_ring_index; /* Current index. */ 3511 uint16_t atio_q_length; 3512 uint32_t __iomem *atio_q_in; 3513 uint32_t __iomem *atio_q_out; 3514 3515 struct qla_tgt_func_tmpl *tgt_ops; 3516 struct qla_tgt_vp_map *tgt_vp_map; 3517 3518 int saved_set; 3519 uint16_t saved_exchange_count; 3520 uint32_t saved_firmware_options_1; 3521 uint32_t saved_firmware_options_2; 3522 uint32_t saved_firmware_options_3; 3523 uint8_t saved_firmware_options[2]; 3524 uint8_t saved_add_firmware_options[2]; 3525 3526 uint8_t tgt_node_name[WWN_SIZE]; 3527 3528 struct dentry *dfs_tgt_sess; 3529 struct dentry *dfs_tgt_port_database; 3530 struct dentry *dfs_naqp; 3531 3532 struct list_head q_full_list; 3533 uint32_t num_pend_cmds; 3534 uint32_t num_qfull_cmds_alloc; 3535 uint32_t num_qfull_cmds_dropped; 3536 spinlock_t q_full_lock; 3537 uint32_t leak_exchg_thresh_hold; 3538 spinlock_t sess_lock; 3539 int num_act_qpairs; 3540 #define DEFAULT_NAQP 2 3541 spinlock_t atio_lock ____cacheline_aligned; 3542 struct btree_head32 host_map; 3543 }; 3544 3545 #define MAX_QFULL_CMDS_ALLOC 8192 3546 #define Q_FULL_THRESH_HOLD_PERCENT 90 3547 #define Q_FULL_THRESH_HOLD(ha) \ 3548 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3549 3550 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3551 3552 /* 3553 * Qlogic host adapter specific data structure. 3554 */ 3555 struct qla_hw_data { 3556 struct pci_dev *pdev; 3557 /* SRB cache. */ 3558 #define SRB_MIN_REQ 128 3559 mempool_t *srb_mempool; 3560 3561 volatile struct { 3562 uint32_t mbox_int :1; 3563 uint32_t mbox_busy :1; 3564 uint32_t disable_risc_code_load :1; 3565 uint32_t enable_64bit_addressing :1; 3566 uint32_t enable_lip_reset :1; 3567 uint32_t enable_target_reset :1; 3568 uint32_t enable_lip_full_login :1; 3569 uint32_t enable_led_scheme :1; 3570 3571 uint32_t msi_enabled :1; 3572 uint32_t msix_enabled :1; 3573 uint32_t disable_serdes :1; 3574 uint32_t gpsc_supported :1; 3575 uint32_t npiv_supported :1; 3576 uint32_t pci_channel_io_perm_failure :1; 3577 uint32_t fce_enabled :1; 3578 uint32_t fac_supported :1; 3579 3580 uint32_t chip_reset_done :1; 3581 uint32_t running_gold_fw :1; 3582 uint32_t eeh_busy :1; 3583 uint32_t disable_msix_handshake :1; 3584 uint32_t fcp_prio_enabled :1; 3585 uint32_t isp82xx_fw_hung:1; 3586 uint32_t nic_core_hung:1; 3587 3588 uint32_t quiesce_owner:1; 3589 uint32_t nic_core_reset_hdlr_active:1; 3590 uint32_t nic_core_reset_owner:1; 3591 uint32_t isp82xx_no_md_cap:1; 3592 uint32_t host_shutting_down:1; 3593 uint32_t idc_compl_status:1; 3594 uint32_t mr_reset_hdlr_active:1; 3595 uint32_t mr_intr_valid:1; 3596 3597 uint32_t dport_enabled:1; 3598 uint32_t fawwpn_enabled:1; 3599 uint32_t exlogins_enabled:1; 3600 uint32_t exchoffld_enabled:1; 3601 3602 uint32_t lip_ae:1; 3603 uint32_t n2n_ae:1; 3604 uint32_t fw_started:1; 3605 uint32_t fw_init_done:1; 3606 3607 uint32_t detected_lr_sfp:1; 3608 uint32_t using_lr_setting:1; 3609 uint32_t rida_fmt2:1; 3610 uint32_t purge_mbox:1; 3611 uint32_t n2n_bigger:1; 3612 } flags; 3613 3614 uint16_t max_exchg; 3615 uint16_t long_range_distance; /* 32G & above */ 3616 #define LR_DISTANCE_5K 1 3617 #define LR_DISTANCE_10K 0 3618 3619 /* This spinlock is used to protect "io transactions", you must 3620 * acquire it before doing any IO to the card, eg with RD_REG*() and 3621 * WRT_REG*() for the duration of your entire commandtransaction. 3622 * 3623 * This spinlock is of lower priority than the io request lock. 3624 */ 3625 3626 spinlock_t hardware_lock ____cacheline_aligned; 3627 int bars; 3628 int mem_only; 3629 device_reg_t *iobase; /* Base I/O address */ 3630 resource_size_t pio_address; 3631 3632 #define MIN_IOBASE_LEN 0x100 3633 dma_addr_t bar0_hdl; 3634 3635 void __iomem *cregbase; 3636 dma_addr_t bar2_hdl; 3637 #define BAR0_LEN_FX00 (1024 * 1024) 3638 #define BAR2_LEN_FX00 (128 * 1024) 3639 3640 uint32_t rqstq_intr_code; 3641 uint32_t mbx_intr_code; 3642 uint32_t req_que_len; 3643 uint32_t rsp_que_len; 3644 uint32_t req_que_off; 3645 uint32_t rsp_que_off; 3646 3647 /* Multi queue data structs */ 3648 device_reg_t *mqiobase; 3649 device_reg_t *msixbase; 3650 uint16_t msix_count; 3651 uint8_t mqenable; 3652 struct req_que **req_q_map; 3653 struct rsp_que **rsp_q_map; 3654 struct qla_qpair **queue_pair_map; 3655 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3656 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3657 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 3658 / sizeof(unsigned long)]; 3659 uint8_t max_req_queues; 3660 uint8_t max_rsp_queues; 3661 uint8_t max_qpairs; 3662 uint8_t num_qpairs; 3663 struct qla_qpair *base_qpair; 3664 struct qla_npiv_entry *npiv_info; 3665 uint16_t nvram_npiv_size; 3666 3667 uint16_t switch_cap; 3668 #define FLOGI_SEQ_DEL BIT_8 3669 #define FLOGI_MID_SUPPORT BIT_10 3670 #define FLOGI_VSAN_SUPPORT BIT_12 3671 #define FLOGI_SP_SUPPORT BIT_13 3672 3673 uint8_t port_no; /* Physical port of adapter */ 3674 uint8_t exch_starvation; 3675 3676 /* Timeout timers. */ 3677 uint8_t loop_down_abort_time; /* port down timer */ 3678 atomic_t loop_down_timer; /* loop down timer */ 3679 uint8_t link_down_timeout; /* link down timeout */ 3680 uint16_t max_loop_id; 3681 uint16_t max_fibre_devices; /* Maximum number of targets */ 3682 3683 uint16_t fb_rev; 3684 uint16_t min_external_loopid; /* First external loop Id */ 3685 3686 #define PORT_SPEED_UNKNOWN 0xFFFF 3687 #define PORT_SPEED_1GB 0x00 3688 #define PORT_SPEED_2GB 0x01 3689 #define PORT_SPEED_4GB 0x03 3690 #define PORT_SPEED_8GB 0x04 3691 #define PORT_SPEED_16GB 0x05 3692 #define PORT_SPEED_32GB 0x06 3693 #define PORT_SPEED_10GB 0x13 3694 uint16_t link_data_rate; /* F/W operating speed */ 3695 3696 uint8_t current_topology; 3697 uint8_t prev_topology; 3698 #define ISP_CFG_NL 1 3699 #define ISP_CFG_N 2 3700 #define ISP_CFG_FL 4 3701 #define ISP_CFG_F 8 3702 3703 uint8_t operating_mode; /* F/W operating mode */ 3704 #define LOOP 0 3705 #define P2P 1 3706 #define LOOP_P2P 2 3707 #define P2P_LOOP 3 3708 uint8_t interrupts_on; 3709 uint32_t isp_abort_cnt; 3710 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 3711 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 3712 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 3713 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 3714 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 3715 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 3716 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 3717 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 3718 3719 uint32_t isp_type; 3720 #define DT_ISP2100 BIT_0 3721 #define DT_ISP2200 BIT_1 3722 #define DT_ISP2300 BIT_2 3723 #define DT_ISP2312 BIT_3 3724 #define DT_ISP2322 BIT_4 3725 #define DT_ISP6312 BIT_5 3726 #define DT_ISP6322 BIT_6 3727 #define DT_ISP2422 BIT_7 3728 #define DT_ISP2432 BIT_8 3729 #define DT_ISP5422 BIT_9 3730 #define DT_ISP5432 BIT_10 3731 #define DT_ISP2532 BIT_11 3732 #define DT_ISP8432 BIT_12 3733 #define DT_ISP8001 BIT_13 3734 #define DT_ISP8021 BIT_14 3735 #define DT_ISP2031 BIT_15 3736 #define DT_ISP8031 BIT_16 3737 #define DT_ISPFX00 BIT_17 3738 #define DT_ISP8044 BIT_18 3739 #define DT_ISP2071 BIT_19 3740 #define DT_ISP2271 BIT_20 3741 #define DT_ISP2261 BIT_21 3742 #define DT_ISP_LAST (DT_ISP2261 << 1) 3743 3744 uint32_t device_type; 3745 #define DT_T10_PI BIT_25 3746 #define DT_IIDMA BIT_26 3747 #define DT_FWI2 BIT_27 3748 #define DT_ZIO_SUPPORTED BIT_28 3749 #define DT_OEM_001 BIT_29 3750 #define DT_ISP2200A BIT_30 3751 #define DT_EXTENDED_IDS BIT_31 3752 3753 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 3754 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 3755 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 3756 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 3757 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 3758 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 3759 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 3760 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 3761 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 3762 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 3763 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 3764 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 3765 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 3766 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 3767 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 3768 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 3769 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 3770 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 3771 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 3772 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 3773 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 3774 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 3775 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 3776 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 3777 3778 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 3779 IS_QLA6312(ha) || IS_QLA6322(ha)) 3780 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 3781 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 3782 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 3783 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 3784 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 3785 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 3786 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 3787 IS_QLA84XX(ha)) 3788 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 3789 IS_QLA8031(ha) || IS_QLA8044(ha)) 3790 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 3791 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 3792 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 3793 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 3794 IS_QLA8044(ha) || IS_QLA27XX(ha)) 3795 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3796 IS_QLA27XX(ha)) 3797 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 3798 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3799 IS_QLA27XX(ha)) 3800 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3801 IS_QLA27XX(ha)) 3802 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 3803 3804 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 3805 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 3806 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 3807 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 3808 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 3809 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 3810 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 3811 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 3812 IS_QLA27XX(ha)) 3813 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) 3814 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 3815 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3816 ((ha)->fw_attributes_ext[0] & BIT_0)) 3817 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3818 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3819 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3820 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3821 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3822 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3823 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3824 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3825 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha)) 3826 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3827 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3828 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 3829 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3830 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 3831 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3832 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ 3833 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3834 3835 /* HBA serial number */ 3836 uint8_t serial0; 3837 uint8_t serial1; 3838 uint8_t serial2; 3839 3840 /* NVRAM configuration data */ 3841 #define MAX_NVRAM_SIZE 4096 3842 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 3843 uint16_t nvram_size; 3844 uint16_t nvram_base; 3845 void *nvram; 3846 uint16_t vpd_size; 3847 uint16_t vpd_base; 3848 void *vpd; 3849 3850 uint16_t loop_reset_delay; 3851 uint8_t retry_count; 3852 uint8_t login_timeout; 3853 uint16_t r_a_tov; 3854 int port_down_retry_count; 3855 uint8_t mbx_count; 3856 uint8_t aen_mbx_count; 3857 atomic_t num_pend_mbx_stage1; 3858 atomic_t num_pend_mbx_stage2; 3859 atomic_t num_pend_mbx_stage3; 3860 uint16_t frame_payload_size; 3861 3862 uint32_t login_retry_count; 3863 /* SNS command interfaces. */ 3864 ms_iocb_entry_t *ms_iocb; 3865 dma_addr_t ms_iocb_dma; 3866 struct ct_sns_pkt *ct_sns; 3867 dma_addr_t ct_sns_dma; 3868 /* SNS command interfaces for 2200. */ 3869 struct sns_cmd_pkt *sns_cmd; 3870 dma_addr_t sns_cmd_dma; 3871 3872 #define SFP_DEV_SIZE 512 3873 #define SFP_BLOCK_SIZE 64 3874 void *sfp_data; 3875 dma_addr_t sfp_data_dma; 3876 3877 #define XGMAC_DATA_SIZE 4096 3878 void *xgmac_data; 3879 dma_addr_t xgmac_data_dma; 3880 3881 #define DCBX_TLV_DATA_SIZE 4096 3882 void *dcbx_tlv; 3883 dma_addr_t dcbx_tlv_dma; 3884 3885 struct task_struct *dpc_thread; 3886 uint8_t dpc_active; /* DPC routine is active */ 3887 3888 dma_addr_t gid_list_dma; 3889 struct gid_list_info *gid_list; 3890 int gid_list_info_size; 3891 3892 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3893 #define DMA_POOL_SIZE 256 3894 struct dma_pool *s_dma_pool; 3895 3896 dma_addr_t init_cb_dma; 3897 init_cb_t *init_cb; 3898 int init_cb_size; 3899 dma_addr_t ex_init_cb_dma; 3900 struct ex_init_cb_81xx *ex_init_cb; 3901 3902 void *async_pd; 3903 dma_addr_t async_pd_dma; 3904 3905 #define ENABLE_EXTENDED_LOGIN BIT_7 3906 3907 /* Extended Logins */ 3908 void *exlogin_buf; 3909 dma_addr_t exlogin_buf_dma; 3910 int exlogin_size; 3911 3912 #define ENABLE_EXCHANGE_OFFLD BIT_2 3913 3914 /* Exchange Offload */ 3915 void *exchoffld_buf; 3916 dma_addr_t exchoffld_buf_dma; 3917 int exchoffld_size; 3918 int exchoffld_count; 3919 3920 /* n2n */ 3921 struct els_plogi_payload plogi_els_payld; 3922 3923 void *swl; 3924 3925 /* These are used by mailbox operations. */ 3926 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3927 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 3928 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 3929 3930 mbx_cmd_t *mcp; 3931 struct mbx_cmd_32 *mcp32; 3932 3933 unsigned long mbx_cmd_flags; 3934 #define MBX_INTERRUPT 1 3935 #define MBX_INTR_WAIT 2 3936 #define MBX_UPDATE_FLASH_ACTIVE 3 3937 3938 struct mutex vport_lock; /* Virtual port synchronization */ 3939 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 3940 struct mutex mq_lock; /* multi-queue synchronization */ 3941 struct completion mbx_cmd_comp; /* Serialize mbx access */ 3942 struct completion mbx_intr_comp; /* Used for completion notification */ 3943 struct completion dcbx_comp; /* For set port config notification */ 3944 struct completion lb_portup_comp; /* Used to wait for link up during 3945 * loopback */ 3946 #define DCBX_COMP_TIMEOUT 20 3947 #define LB_PORTUP_COMP_TIMEOUT 10 3948 3949 int notify_dcbx_comp; 3950 int notify_lb_portup_comp; 3951 struct mutex selflogin_lock; 3952 3953 /* Basic firmware related information. */ 3954 uint16_t fw_major_version; 3955 uint16_t fw_minor_version; 3956 uint16_t fw_subminor_version; 3957 uint16_t fw_attributes; 3958 uint16_t fw_attributes_h; 3959 uint16_t fw_attributes_ext[2]; 3960 uint32_t fw_memory_size; 3961 uint32_t fw_transfer_size; 3962 uint32_t fw_srisc_address; 3963 #define RISC_START_ADDRESS_2100 0x1000 3964 #define RISC_START_ADDRESS_2300 0x800 3965 #define RISC_START_ADDRESS_2400 0x100000 3966 3967 uint16_t orig_fw_tgt_xcb_count; 3968 uint16_t cur_fw_tgt_xcb_count; 3969 uint16_t orig_fw_xcb_count; 3970 uint16_t cur_fw_xcb_count; 3971 uint16_t orig_fw_iocb_count; 3972 uint16_t cur_fw_iocb_count; 3973 uint16_t fw_max_fcf_count; 3974 3975 uint32_t fw_shared_ram_start; 3976 uint32_t fw_shared_ram_end; 3977 uint32_t fw_ddr_ram_start; 3978 uint32_t fw_ddr_ram_end; 3979 3980 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 3981 uint8_t fw_seriallink_options[4]; 3982 uint16_t fw_seriallink_options24[4]; 3983 3984 uint8_t mpi_version[3]; 3985 uint32_t mpi_capabilities; 3986 uint8_t phy_version[3]; 3987 uint8_t pep_version[3]; 3988 3989 /* Firmware dump template */ 3990 void *fw_dump_template; 3991 uint32_t fw_dump_template_len; 3992 /* Firmware dump information. */ 3993 struct qla2xxx_fw_dump *fw_dump; 3994 uint32_t fw_dump_len; 3995 int fw_dumped; 3996 unsigned long fw_dump_cap_flags; 3997 #define RISC_PAUSE_CMPL 0 3998 #define DMA_SHUTDOWN_CMPL 1 3999 #define ISP_RESET_CMPL 2 4000 #define RISC_RDY_AFT_RESET 3 4001 #define RISC_SRAM_DUMP_CMPL 4 4002 #define RISC_EXT_MEM_DUMP_CMPL 5 4003 #define ISP_MBX_RDY 6 4004 #define ISP_SOFT_RESET_CMPL 7 4005 int fw_dump_reading; 4006 int prev_minidump_failed; 4007 dma_addr_t eft_dma; 4008 void *eft; 4009 /* Current size of mctp dump is 0x086064 bytes */ 4010 #define MCTP_DUMP_SIZE 0x086064 4011 dma_addr_t mctp_dump_dma; 4012 void *mctp_dump; 4013 int mctp_dumped; 4014 int mctp_dump_reading; 4015 uint32_t chain_offset; 4016 struct dentry *dfs_dir; 4017 struct dentry *dfs_fce; 4018 struct dentry *dfs_tgt_counters; 4019 struct dentry *dfs_fw_resource_cnt; 4020 4021 dma_addr_t fce_dma; 4022 void *fce; 4023 uint32_t fce_bufs; 4024 uint16_t fce_mb[8]; 4025 uint64_t fce_wr, fce_rd; 4026 struct mutex fce_mutex; 4027 4028 uint32_t pci_attr; 4029 uint16_t chip_revision; 4030 4031 uint16_t product_id[4]; 4032 4033 uint8_t model_number[16+1]; 4034 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 4035 char model_desc[80]; 4036 uint8_t adapter_id[16+1]; 4037 4038 /* Option ROM information. */ 4039 char *optrom_buffer; 4040 uint32_t optrom_size; 4041 int optrom_state; 4042 #define QLA_SWAITING 0 4043 #define QLA_SREADING 1 4044 #define QLA_SWRITING 2 4045 uint32_t optrom_region_start; 4046 uint32_t optrom_region_size; 4047 struct mutex optrom_mutex; 4048 4049 /* PCI expansion ROM image information. */ 4050 #define ROM_CODE_TYPE_BIOS 0 4051 #define ROM_CODE_TYPE_FCODE 1 4052 #define ROM_CODE_TYPE_EFI 3 4053 uint8_t bios_revision[2]; 4054 uint8_t efi_revision[2]; 4055 uint8_t fcode_revision[16]; 4056 uint32_t fw_revision[4]; 4057 4058 uint32_t gold_fw_version[4]; 4059 4060 /* Offsets for flash/nvram access (set to ~0 if not used). */ 4061 uint32_t flash_conf_off; 4062 uint32_t flash_data_off; 4063 uint32_t nvram_conf_off; 4064 uint32_t nvram_data_off; 4065 4066 uint32_t fdt_wrt_disable; 4067 uint32_t fdt_wrt_enable; 4068 uint32_t fdt_erase_cmd; 4069 uint32_t fdt_block_size; 4070 uint32_t fdt_unprotect_sec_cmd; 4071 uint32_t fdt_protect_sec_cmd; 4072 uint32_t fdt_wrt_sts_reg_cmd; 4073 4074 uint32_t flt_region_flt; 4075 uint32_t flt_region_fdt; 4076 uint32_t flt_region_boot; 4077 uint32_t flt_region_boot_sec; 4078 uint32_t flt_region_fw; 4079 uint32_t flt_region_fw_sec; 4080 uint32_t flt_region_vpd_nvram; 4081 uint32_t flt_region_vpd; 4082 uint32_t flt_region_vpd_sec; 4083 uint32_t flt_region_nvram; 4084 uint32_t flt_region_npiv_conf; 4085 uint32_t flt_region_gold_fw; 4086 uint32_t flt_region_fcp_prio; 4087 uint32_t flt_region_bootload; 4088 uint32_t flt_region_img_status_pri; 4089 uint32_t flt_region_img_status_sec; 4090 uint8_t active_image; 4091 4092 /* Needed for BEACON */ 4093 uint16_t beacon_blink_led; 4094 uint8_t beacon_color_state; 4095 #define QLA_LED_GRN_ON 0x01 4096 #define QLA_LED_YLW_ON 0x02 4097 #define QLA_LED_ABR_ON 0x04 4098 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 4099 /* ISP2322: red, green, amber. */ 4100 uint16_t zio_mode; 4101 uint16_t zio_timer; 4102 4103 struct qla_msix_entry *msix_entries; 4104 4105 struct list_head vp_list; /* list of VP */ 4106 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 4107 sizeof(unsigned long)]; 4108 uint16_t num_vhosts; /* number of vports created */ 4109 uint16_t num_vsans; /* number of vsan created */ 4110 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 4111 int cur_vport_count; 4112 4113 struct qla_chip_state_84xx *cs84xx; 4114 struct isp_operations *isp_ops; 4115 struct workqueue_struct *wq; 4116 struct qlfc_fw fw_buf; 4117 4118 /* FCP_CMND priority support */ 4119 struct qla_fcp_prio_cfg *fcp_prio_cfg; 4120 4121 struct dma_pool *dl_dma_pool; 4122 #define DSD_LIST_DMA_POOL_SIZE 512 4123 4124 struct dma_pool *fcp_cmnd_dma_pool; 4125 mempool_t *ctx_mempool; 4126 #define FCP_CMND_DMA_POOL_SIZE 512 4127 4128 void __iomem *nx_pcibase; /* Base I/O address */ 4129 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4130 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4131 4132 uint32_t crb_win; 4133 uint32_t curr_window; 4134 uint32_t ddr_mn_window; 4135 unsigned long mn_win_crb; 4136 unsigned long ms_win_crb; 4137 int qdr_sn_window; 4138 uint32_t fcoe_dev_init_timeout; 4139 uint32_t fcoe_reset_timeout; 4140 rwlock_t hw_lock; 4141 uint16_t portnum; /* port number */ 4142 int link_width; 4143 struct fw_blob *hablob; 4144 struct qla82xx_legacy_intr_set nx_legacy_intr; 4145 4146 uint16_t gbl_dsd_inuse; 4147 uint16_t gbl_dsd_avail; 4148 struct list_head gbl_dsd_list; 4149 #define NUM_DSD_CHAIN 4096 4150 4151 uint8_t fw_type; 4152 __le32 file_prd_off; /* File firmware product offset */ 4153 4154 uint32_t md_template_size; 4155 void *md_tmplt_hdr; 4156 dma_addr_t md_tmplt_hdr_dma; 4157 void *md_dump; 4158 uint32_t md_dump_size; 4159 4160 void *loop_id_map; 4161 4162 /* QLA83XX IDC specific fields */ 4163 uint32_t idc_audit_ts; 4164 uint32_t idc_extend_tmo; 4165 4166 /* DPC low-priority workqueue */ 4167 struct workqueue_struct *dpc_lp_wq; 4168 struct work_struct idc_aen; 4169 /* DPC high-priority workqueue */ 4170 struct workqueue_struct *dpc_hp_wq; 4171 struct work_struct nic_core_reset; 4172 struct work_struct idc_state_handler; 4173 struct work_struct nic_core_unrecoverable; 4174 struct work_struct board_disable; 4175 4176 struct mr_data_fx00 mr; 4177 uint32_t chip_reset; 4178 4179 struct qlt_hw_data tgt; 4180 int allow_cna_fw_dump; 4181 uint32_t fw_ability_mask; 4182 uint16_t min_link_speed; 4183 uint16_t max_speed_sup; 4184 4185 atomic_t nvme_active_aen_cnt; 4186 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4187 }; 4188 4189 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4190 #define FW_ABILITY_MAX_SPEED_16G 0x0 4191 #define FW_ABILITY_MAX_SPEED_32G 0x1 4192 #define FW_ABILITY_MAX_SPEED(ha) \ 4193 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4194 4195 /* 4196 * Qlogic scsi host structure 4197 */ 4198 typedef struct scsi_qla_host { 4199 struct list_head list; 4200 struct list_head vp_fcports; /* list of fcports */ 4201 struct list_head work_list; 4202 spinlock_t work_lock; 4203 struct work_struct iocb_work; 4204 4205 /* Commonly used flags and state information. */ 4206 struct Scsi_Host *host; 4207 unsigned long host_no; 4208 uint8_t host_str[16]; 4209 4210 volatile struct { 4211 uint32_t init_done :1; 4212 uint32_t online :1; 4213 uint32_t reset_active :1; 4214 4215 uint32_t management_server_logged_in :1; 4216 uint32_t process_response_queue :1; 4217 uint32_t difdix_supported:1; 4218 uint32_t delete_progress:1; 4219 4220 uint32_t fw_tgt_reported:1; 4221 uint32_t bbcr_enable:1; 4222 uint32_t qpairs_available:1; 4223 uint32_t qpairs_req_created:1; 4224 uint32_t qpairs_rsp_created:1; 4225 uint32_t nvme_enabled:1; 4226 } flags; 4227 4228 atomic_t loop_state; 4229 #define LOOP_TIMEOUT 1 4230 #define LOOP_DOWN 2 4231 #define LOOP_UP 3 4232 #define LOOP_UPDATE 4 4233 #define LOOP_READY 5 4234 #define LOOP_DEAD 6 4235 4236 unsigned long relogin_jif; 4237 unsigned long dpc_flags; 4238 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4239 #define RESET_ACTIVE 1 4240 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4241 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4242 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4243 #define LOOP_RESYNC_ACTIVE 5 4244 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4245 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4246 #define RELOGIN_NEEDED 8 4247 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4248 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4249 #define BEACON_BLINK_NEEDED 11 4250 #define REGISTER_FDMI_NEEDED 12 4251 #define FCPORT_UPDATE_NEEDED 13 4252 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4253 #define UNLOADING 15 4254 #define NPIV_CONFIG_NEEDED 16 4255 #define ISP_UNRECOVERABLE 17 4256 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4257 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4258 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4259 #define N2N_LINK_RESET 21 4260 #define PORT_UPDATE_NEEDED 22 4261 #define FX00_RESET_RECOVERY 23 4262 #define FX00_TARGET_SCAN 24 4263 #define FX00_CRITEMP_RECOVERY 25 4264 #define FX00_HOST_INFO_RESEND 26 4265 #define QPAIR_ONLINE_CHECK_NEEDED 27 4266 #define SET_ZIO_THRESHOLD_NEEDED 28 4267 #define DETECT_SFP_CHANGE 29 4268 #define N2N_LOGIN_NEEDED 30 4269 #define IOCB_WORK_ACTIVE 31 4270 4271 unsigned long pci_flags; 4272 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4273 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4274 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4275 4276 uint32_t device_flags; 4277 #define SWITCH_FOUND BIT_0 4278 #define DFLG_NO_CABLE BIT_1 4279 #define DFLG_DEV_FAILED BIT_5 4280 4281 /* ISP configuration data. */ 4282 uint16_t loop_id; /* Host adapter loop id */ 4283 uint16_t self_login_loop_id; /* host adapter loop id 4284 * get it on self login 4285 */ 4286 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4287 * no need of allocating it for 4288 * each command 4289 */ 4290 4291 port_id_t d_id; /* Host adapter port id */ 4292 uint8_t marker_needed; 4293 uint16_t mgmt_svr_loop_id; 4294 4295 4296 4297 /* Timeout timers. */ 4298 uint8_t loop_down_abort_time; /* port down timer */ 4299 atomic_t loop_down_timer; /* loop down timer */ 4300 uint8_t link_down_timeout; /* link down timeout */ 4301 4302 uint32_t timer_active; 4303 struct timer_list timer; 4304 4305 uint8_t node_name[WWN_SIZE]; 4306 uint8_t port_name[WWN_SIZE]; 4307 uint8_t fabric_node_name[WWN_SIZE]; 4308 4309 struct nvme_fc_local_port *nvme_local_port; 4310 struct completion nvme_del_done; 4311 struct list_head nvme_rport_list; 4312 4313 uint16_t fcoe_vlan_id; 4314 uint16_t fcoe_fcf_idx; 4315 uint8_t fcoe_vn_port_mac[6]; 4316 4317 /* list of commands waiting on workqueue */ 4318 struct list_head qla_cmd_list; 4319 struct list_head qla_sess_op_cmd_list; 4320 struct list_head unknown_atio_list; 4321 spinlock_t cmd_list_lock; 4322 struct delayed_work unknown_atio_work; 4323 4324 /* Counter to detect races between ELS and RSCN events */ 4325 atomic_t generation_tick; 4326 /* Time when global fcport update has been scheduled */ 4327 int total_fcport_update_gen; 4328 /* List of pending LOGOs, protected by tgt_mutex */ 4329 struct list_head logo_list; 4330 /* List of pending PLOGI acks, protected by hw lock */ 4331 struct list_head plogi_ack_list; 4332 4333 struct list_head qp_list; 4334 4335 uint32_t vp_abort_cnt; 4336 4337 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4338 uint16_t vp_idx; /* vport ID */ 4339 struct qla_qpair *qpair; /* base qpair */ 4340 4341 unsigned long vp_flags; 4342 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4343 #define VP_CREATE_NEEDED 1 4344 #define VP_BIND_NEEDED 2 4345 #define VP_DELETE_NEEDED 3 4346 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4347 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4348 atomic_t vp_state; 4349 #define VP_OFFLINE 0 4350 #define VP_ACTIVE 1 4351 #define VP_FAILED 2 4352 // #define VP_DISABLE 3 4353 uint16_t vp_err_state; 4354 uint16_t vp_prev_err_state; 4355 #define VP_ERR_UNKWN 0 4356 #define VP_ERR_PORTDWN 1 4357 #define VP_ERR_FAB_UNSUPPORTED 2 4358 #define VP_ERR_FAB_NORESOURCES 3 4359 #define VP_ERR_FAB_LOGOUT 4 4360 #define VP_ERR_ADAP_NORESOURCES 5 4361 struct qla_hw_data *hw; 4362 struct scsi_qlt_host vha_tgt; 4363 struct req_que *req; 4364 int fw_heartbeat_counter; 4365 int seconds_since_last_heartbeat; 4366 struct fc_host_statistics fc_host_stat; 4367 struct qla_statistics qla_stats; 4368 struct bidi_statistics bidi_stats; 4369 atomic_t vref_count; 4370 struct qla8044_reset_template reset_tmplt; 4371 uint16_t bbcr; 4372 struct name_list_extended gnl; 4373 /* Count of active session/fcport */ 4374 int fcport_count; 4375 wait_queue_head_t fcport_waitQ; 4376 wait_queue_head_t vref_waitq; 4377 uint8_t min_link_speed_feat; 4378 uint8_t n2n_node_name[WWN_SIZE]; 4379 uint8_t n2n_port_name[WWN_SIZE]; 4380 uint16_t n2n_id; 4381 struct list_head gpnid_list; 4382 struct fab_scan scan; 4383 } scsi_qla_host_t; 4384 4385 struct qla27xx_image_status { 4386 uint8_t image_status_mask; 4387 uint16_t generation_number; 4388 uint8_t reserved[3]; 4389 uint8_t ver_minor; 4390 uint8_t ver_major; 4391 uint32_t checksum; 4392 uint32_t signature; 4393 } __packed; 4394 4395 #define SET_VP_IDX 1 4396 #define SET_AL_PA 2 4397 #define RESET_VP_IDX 3 4398 #define RESET_AL_PA 4 4399 struct qla_tgt_vp_map { 4400 uint8_t idx; 4401 scsi_qla_host_t *vha; 4402 }; 4403 4404 struct qla2_sgx { 4405 dma_addr_t dma_addr; /* OUT */ 4406 uint32_t dma_len; /* OUT */ 4407 4408 uint32_t tot_bytes; /* IN */ 4409 struct scatterlist *cur_sg; /* IN */ 4410 4411 /* for book keeping, bzero on initial invocation */ 4412 uint32_t bytes_consumed; 4413 uint32_t num_bytes; 4414 uint32_t tot_partial; 4415 4416 /* for debugging */ 4417 uint32_t num_sg; 4418 srb_t *sp; 4419 }; 4420 4421 #define QLA_FW_STARTED(_ha) { \ 4422 int i; \ 4423 _ha->flags.fw_started = 1; \ 4424 _ha->base_qpair->fw_started = 1; \ 4425 for (i = 0; i < _ha->max_qpairs; i++) { \ 4426 if (_ha->queue_pair_map[i]) \ 4427 _ha->queue_pair_map[i]->fw_started = 1; \ 4428 } \ 4429 } 4430 4431 #define QLA_FW_STOPPED(_ha) { \ 4432 int i; \ 4433 _ha->flags.fw_started = 0; \ 4434 _ha->base_qpair->fw_started = 0; \ 4435 for (i = 0; i < _ha->max_qpairs; i++) { \ 4436 if (_ha->queue_pair_map[i]) \ 4437 _ha->queue_pair_map[i]->fw_started = 0; \ 4438 } \ 4439 } 4440 4441 /* 4442 * Macros to help code, maintain, etc. 4443 */ 4444 #define LOOP_TRANSITION(ha) \ 4445 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4446 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 4447 atomic_read(&ha->loop_state) == LOOP_DOWN) 4448 4449 #define STATE_TRANSITION(ha) \ 4450 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4451 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 4452 4453 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 4454 atomic_inc(&__vha->vref_count); \ 4455 mb(); \ 4456 if (__vha->flags.delete_progress) { \ 4457 atomic_dec(&__vha->vref_count); \ 4458 wake_up(&__vha->vref_waitq); \ 4459 __bail = 1; \ 4460 } else { \ 4461 __bail = 0; \ 4462 } \ 4463 } while (0) 4464 4465 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 4466 atomic_dec(&__vha->vref_count); \ 4467 wake_up(&__vha->vref_waitq); \ 4468 } while (0) \ 4469 4470 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 4471 atomic_inc(&__qpair->ref_count); \ 4472 mb(); \ 4473 if (__qpair->delete_in_progress) { \ 4474 atomic_dec(&__qpair->ref_count); \ 4475 __bail = 1; \ 4476 } else { \ 4477 __bail = 0; \ 4478 } \ 4479 } while (0) 4480 4481 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 4482 atomic_dec(&__qpair->ref_count); \ 4483 4484 4485 #define QLA_ENA_CONF(_ha) {\ 4486 int i;\ 4487 _ha->base_qpair->enable_explicit_conf = 1; \ 4488 for (i = 0; i < _ha->max_qpairs; i++) { \ 4489 if (_ha->queue_pair_map[i]) \ 4490 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 4491 } \ 4492 } 4493 4494 #define QLA_DIS_CONF(_ha) {\ 4495 int i;\ 4496 _ha->base_qpair->enable_explicit_conf = 0; \ 4497 for (i = 0; i < _ha->max_qpairs; i++) { \ 4498 if (_ha->queue_pair_map[i]) \ 4499 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 4500 } \ 4501 } 4502 4503 /* 4504 * qla2x00 local function return status codes 4505 */ 4506 #define MBS_MASK 0x3fff 4507 4508 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 4509 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 4510 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 4511 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 4512 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 4513 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 4514 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 4515 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 4516 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 4517 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 4518 4519 #define QLA_FUNCTION_TIMEOUT 0x100 4520 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 4521 #define QLA_FUNCTION_FAILED 0x102 4522 #define QLA_MEMORY_ALLOC_FAILED 0x103 4523 #define QLA_LOCK_TIMEOUT 0x104 4524 #define QLA_ABORTED 0x105 4525 #define QLA_SUSPENDED 0x106 4526 #define QLA_BUSY 0x107 4527 #define QLA_ALREADY_REGISTERED 0x109 4528 4529 #define NVRAM_DELAY() udelay(10) 4530 4531 /* 4532 * Flash support definitions 4533 */ 4534 #define OPTROM_SIZE_2300 0x20000 4535 #define OPTROM_SIZE_2322 0x100000 4536 #define OPTROM_SIZE_24XX 0x100000 4537 #define OPTROM_SIZE_25XX 0x200000 4538 #define OPTROM_SIZE_81XX 0x400000 4539 #define OPTROM_SIZE_82XX 0x800000 4540 #define OPTROM_SIZE_83XX 0x1000000 4541 4542 #define OPTROM_BURST_SIZE 0x1000 4543 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 4544 4545 #define QLA_DSDS_PER_IOCB 37 4546 4547 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 4548 4549 #define QLA_SG_ALL 1024 4550 4551 enum nexus_wait_type { 4552 WAIT_HOST = 0, 4553 WAIT_TARGET, 4554 WAIT_LUN, 4555 }; 4556 4557 /* Refer to SNIA SFF 8247 */ 4558 struct sff_8247_a0 { 4559 u8 txid; /* transceiver id */ 4560 u8 ext_txid; 4561 u8 connector; 4562 /* compliance code */ 4563 u8 eth_infi_cc3; /* ethernet, inifiband */ 4564 u8 sonet_cc4[2]; 4565 u8 eth_cc6; 4566 /* link length */ 4567 #define FC_LL_VL BIT_7 /* very long */ 4568 #define FC_LL_S BIT_6 /* Short */ 4569 #define FC_LL_I BIT_5 /* Intermidiate*/ 4570 #define FC_LL_L BIT_4 /* Long */ 4571 #define FC_LL_M BIT_3 /* Medium */ 4572 #define FC_LL_SA BIT_2 /* ShortWave laser */ 4573 #define FC_LL_LC BIT_1 /* LongWave laser */ 4574 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 4575 u8 fc_ll_cc7; 4576 /* FC technology */ 4577 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 4578 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 4579 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 4580 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 4581 #define FC_TEC_ACT BIT_3 /* Active cable */ 4582 #define FC_TEC_PAS BIT_2 /* Passive cable */ 4583 u8 fc_tec_cc8; 4584 /* Transmission Media */ 4585 #define FC_MED_TW BIT_7 /* Twin Ax */ 4586 #define FC_MED_TP BIT_6 /* Twited Pair */ 4587 #define FC_MED_MI BIT_5 /* Min Coax */ 4588 #define FC_MED_TV BIT_4 /* Video Coax */ 4589 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 4590 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 4591 #define FC_MED_SM BIT_0 /* Single Mode */ 4592 u8 fc_med_cc9; 4593 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 4594 #define FC_SP_12 BIT_7 4595 #define FC_SP_8 BIT_6 4596 #define FC_SP_16 BIT_5 4597 #define FC_SP_4 BIT_4 4598 #define FC_SP_32 BIT_3 4599 #define FC_SP_2 BIT_2 4600 #define FC_SP_1 BIT_0 4601 u8 fc_sp_cc10; 4602 u8 encode; 4603 u8 bitrate; 4604 u8 rate_id; 4605 u8 length_km; /* offset 14/eh */ 4606 u8 length_100m; 4607 u8 length_50um_10m; 4608 u8 length_62um_10m; 4609 u8 length_om4_10m; 4610 u8 length_om3_10m; 4611 #define SFF_VEN_NAME_LEN 16 4612 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 4613 u8 tx_compat; 4614 u8 vendor_oui[3]; 4615 #define SFF_PART_NAME_LEN 16 4616 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 4617 u8 vendor_rev[4]; 4618 u8 wavelength[2]; 4619 u8 resv; 4620 u8 cc_base; 4621 u8 options[2]; /* offset 64 */ 4622 u8 br_max; 4623 u8 br_min; 4624 u8 vendor_sn[16]; 4625 u8 date_code[8]; 4626 u8 diag; 4627 u8 enh_options; 4628 u8 sff_revision; 4629 u8 cc_ext; 4630 u8 vendor_specific[32]; 4631 u8 resv2[128]; 4632 }; 4633 4634 #define AUTO_DETECT_SFP_SUPPORT(_vha)\ 4635 (ql2xautodetectsfp && !_vha->vp_idx && \ 4636 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\ 4637 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw))) 4638 4639 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 4640 (IS_QLA27XX(_ha) || IS_QLA83XX(_ha))) 4641 4642 #define SAVE_TOPO(_ha) { \ 4643 if (_ha->current_topology) \ 4644 _ha->prev_topology = _ha->current_topology; \ 4645 } 4646 4647 #define N2N_TOPO(ha) \ 4648 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ 4649 ha->current_topology == ISP_CFG_N || \ 4650 !ha->current_topology) 4651 4652 #include "qla_target.h" 4653 #include "qla_gbl.h" 4654 #include "qla_dbg.h" 4655 #include "qla_inline.h" 4656 #endif 4657