1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 #include <linux/btree.h> 29 30 #include <scsi/scsi.h> 31 #include <scsi/scsi_host.h> 32 #include <scsi/scsi_device.h> 33 #include <scsi/scsi_cmnd.h> 34 #include <scsi/scsi_transport_fc.h> 35 #include <scsi/scsi_bsg_fc.h> 36 37 #include "qla_bsg.h" 38 #include "qla_nx.h" 39 #include "qla_nx2.h" 40 #include "qla_nvme.h" 41 #define QLA2XXX_DRIVER_NAME "qla2xxx" 42 #define QLA2XXX_APIDEV "ql2xapidev" 43 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 44 45 /* 46 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 47 * but that's fine as we don't look at the last 24 ones for 48 * ISP2100 HBAs. 49 */ 50 #define MAILBOX_REGISTER_COUNT_2100 8 51 #define MAILBOX_REGISTER_COUNT_2200 24 52 #define MAILBOX_REGISTER_COUNT 32 53 54 #define QLA2200A_RISC_ROM_VER 4 55 #define FPM_2300 6 56 #define FPM_2310 7 57 58 #include "qla_settings.h" 59 60 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 61 62 /* 63 * Data bit definitions 64 */ 65 #define BIT_0 0x1 66 #define BIT_1 0x2 67 #define BIT_2 0x4 68 #define BIT_3 0x8 69 #define BIT_4 0x10 70 #define BIT_5 0x20 71 #define BIT_6 0x40 72 #define BIT_7 0x80 73 #define BIT_8 0x100 74 #define BIT_9 0x200 75 #define BIT_10 0x400 76 #define BIT_11 0x800 77 #define BIT_12 0x1000 78 #define BIT_13 0x2000 79 #define BIT_14 0x4000 80 #define BIT_15 0x8000 81 #define BIT_16 0x10000 82 #define BIT_17 0x20000 83 #define BIT_18 0x40000 84 #define BIT_19 0x80000 85 #define BIT_20 0x100000 86 #define BIT_21 0x200000 87 #define BIT_22 0x400000 88 #define BIT_23 0x800000 89 #define BIT_24 0x1000000 90 #define BIT_25 0x2000000 91 #define BIT_26 0x4000000 92 #define BIT_27 0x8000000 93 #define BIT_28 0x10000000 94 #define BIT_29 0x20000000 95 #define BIT_30 0x40000000 96 #define BIT_31 0x80000000 97 98 #define LSB(x) ((uint8_t)(x)) 99 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 100 101 #define LSW(x) ((uint16_t)(x)) 102 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 103 104 #define LSD(x) ((uint32_t)((uint64_t)(x))) 105 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 106 107 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 108 109 /* 110 * I/O register 111 */ 112 113 #define RD_REG_BYTE(addr) readb(addr) 114 #define RD_REG_WORD(addr) readw(addr) 115 #define RD_REG_DWORD(addr) readl(addr) 116 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 117 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 118 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 119 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 120 #define WRT_REG_WORD(addr, data) writew(data,addr) 121 #define WRT_REG_DWORD(addr, data) writel(data,addr) 122 123 /* 124 * ISP83XX specific remote register addresses 125 */ 126 #define QLA83XX_LED_PORT0 0x00201320 127 #define QLA83XX_LED_PORT1 0x00201328 128 #define QLA83XX_IDC_DEV_STATE 0x22102384 129 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 130 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 131 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 132 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 133 #define QLA83XX_IDC_CONTROL 0x22102390 134 #define QLA83XX_IDC_AUDIT 0x22102394 135 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 136 #define QLA83XX_DRIVER_LOCKID 0x22102104 137 #define QLA83XX_DRIVER_LOCK 0x8111c028 138 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 139 #define QLA83XX_FLASH_LOCKID 0x22102100 140 #define QLA83XX_FLASH_LOCK 0x8111c010 141 #define QLA83XX_FLASH_UNLOCK 0x8111c014 142 #define QLA83XX_DEV_PARTINFO1 0x221023e0 143 #define QLA83XX_DEV_PARTINFO2 0x221023e4 144 #define QLA83XX_FW_HEARTBEAT 0x221020b0 145 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 146 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 147 148 /* 83XX: Macros defining 8200 AEN Reason codes */ 149 #define IDC_DEVICE_STATE_CHANGE BIT_0 150 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 151 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 152 #define IDC_HEARTBEAT_FAILURE BIT_3 153 154 /* 83XX: Macros defining 8200 AEN Error-levels */ 155 #define ERR_LEVEL_NON_FATAL 0x1 156 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 157 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 158 159 /* 83XX: Macros for IDC Version */ 160 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 161 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 162 163 /* 83XX: Macros for scheduling dpc tasks */ 164 #define QLA83XX_NIC_CORE_RESET 0x1 165 #define QLA83XX_IDC_STATE_HANDLER 0x2 166 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 167 168 /* 83XX: Macros for defining IDC-Control bits */ 169 #define QLA83XX_IDC_RESET_DISABLED BIT_0 170 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 171 172 /* 83XX: Macros for different timeouts */ 173 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 174 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 175 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 176 177 /* 83XX: Macros for defining class in DEV-Partition Info register */ 178 #define QLA83XX_CLASS_TYPE_NONE 0x0 179 #define QLA83XX_CLASS_TYPE_NIC 0x1 180 #define QLA83XX_CLASS_TYPE_FCOE 0x2 181 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 182 183 /* 83XX: Macros for IDC Lock-Recovery stages */ 184 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 185 * lock-recovery 186 */ 187 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 188 189 /* 83XX: Macros for IDC Audit type */ 190 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 191 * dev-state change to NEED-RESET 192 * or NEED-QUIESCENT 193 */ 194 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 195 * reset-recovery completion is 196 * second 197 */ 198 /* ISP2031: Values for laser on/off */ 199 #define PORT_0_2031 0x00201340 200 #define PORT_1_2031 0x00201350 201 #define LASER_ON_2031 0x01800100 202 #define LASER_OFF_2031 0x01800180 203 204 /* 205 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 206 * 133Mhz slot. 207 */ 208 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 209 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 210 211 /* 212 * Fibre Channel device definitions. 213 */ 214 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 215 #define MAX_FIBRE_DEVICES_2100 512 216 #define MAX_FIBRE_DEVICES_2400 2048 217 #define MAX_FIBRE_DEVICES_LOOP 128 218 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 219 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 220 #define MAX_FIBRE_LUNS 0xFFFF 221 #define MAX_HOST_COUNT 16 222 223 /* 224 * Host adapter default definitions. 225 */ 226 #define MAX_BUSES 1 /* We only have one bus today */ 227 #define MIN_LUNS 8 228 #define MAX_LUNS MAX_FIBRE_LUNS 229 #define MAX_CMDS_PER_LUN 255 230 231 /* 232 * Fibre Channel device definitions. 233 */ 234 #define SNS_LAST_LOOP_ID_2100 0xfe 235 #define SNS_LAST_LOOP_ID_2300 0x7ff 236 237 #define LAST_LOCAL_LOOP_ID 0x7d 238 #define SNS_FL_PORT 0x7e 239 #define FABRIC_CONTROLLER 0x7f 240 #define SIMPLE_NAME_SERVER 0x80 241 #define SNS_FIRST_LOOP_ID 0x81 242 #define MANAGEMENT_SERVER 0xfe 243 #define BROADCAST 0xff 244 245 /* 246 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 247 * valid range of an N-PORT id is 0 through 0x7ef. 248 */ 249 #define NPH_LAST_HANDLE 0x7ee 250 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ 251 #define NPH_SNS 0x7fc /* FFFFFC */ 252 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 253 #define NPH_F_PORT 0x7fe /* FFFFFE */ 254 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 255 256 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 257 258 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 259 #include "qla_fw.h" 260 261 struct name_list_extended { 262 struct get_name_list_extended *l; 263 dma_addr_t ldma; 264 struct list_head fcports; 265 spinlock_t fcports_lock; 266 u32 size; 267 }; 268 /* 269 * Timeout timer counts in seconds 270 */ 271 #define PORT_RETRY_TIME 1 272 #define LOOP_DOWN_TIMEOUT 60 273 #define LOOP_DOWN_TIME 255 /* 240 */ 274 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 275 276 #define DEFAULT_OUTSTANDING_COMMANDS 4096 277 #define MIN_OUTSTANDING_COMMANDS 128 278 279 /* ISP request and response entry counts (37-65535) */ 280 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 281 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 282 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 283 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 284 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 285 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 286 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 287 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 288 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 289 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 290 #define FW_DEF_EXCHANGES_CNT 2048 291 #define FW_MAX_EXCHANGES_CNT (32 * 1024) 292 #define REDUCE_EXCHANGES_CNT (8 * 1024) 293 294 struct req_que; 295 struct qla_tgt_sess; 296 297 /* 298 * SCSI Request Block 299 */ 300 struct srb_cmd { 301 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 302 uint32_t request_sense_length; 303 uint32_t fw_sense_length; 304 uint8_t *request_sense_ptr; 305 void *ctx; 306 }; 307 308 /* 309 * SRB flag definitions 310 */ 311 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 312 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 313 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 314 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 315 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 316 317 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 318 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 319 320 /* 321 * 24 bit port ID type definition. 322 */ 323 typedef union { 324 uint32_t b24 : 24; 325 326 struct { 327 #ifdef __BIG_ENDIAN 328 uint8_t domain; 329 uint8_t area; 330 uint8_t al_pa; 331 #elif defined(__LITTLE_ENDIAN) 332 uint8_t al_pa; 333 uint8_t area; 334 uint8_t domain; 335 #else 336 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 337 #endif 338 uint8_t rsvd_1; 339 } b; 340 } port_id_t; 341 #define INVALID_PORT_ID 0xFFFFFF 342 343 struct els_logo_payload { 344 uint8_t opcode; 345 uint8_t rsvd[3]; 346 uint8_t s_id[3]; 347 uint8_t rsvd1[1]; 348 uint8_t wwpn[WWN_SIZE]; 349 }; 350 351 struct els_plogi_payload { 352 uint8_t opcode; 353 uint8_t rsvd[3]; 354 uint8_t data[112]; 355 }; 356 357 struct ct_arg { 358 void *iocb; 359 u16 nport_handle; 360 dma_addr_t req_dma; 361 dma_addr_t rsp_dma; 362 u32 req_size; 363 u32 rsp_size; 364 void *req; 365 void *rsp; 366 port_id_t id; 367 }; 368 369 /* 370 * SRB extensions. 371 */ 372 struct srb_iocb { 373 union { 374 struct { 375 uint16_t flags; 376 #define SRB_LOGIN_RETRIED BIT_0 377 #define SRB_LOGIN_COND_PLOGI BIT_1 378 #define SRB_LOGIN_SKIP_PRLI BIT_2 379 #define SRB_LOGIN_NVME_PRLI BIT_3 380 uint16_t data[2]; 381 u32 iop[2]; 382 } logio; 383 struct { 384 #define ELS_DCMD_TIMEOUT 20 385 #define ELS_DCMD_LOGO 0x5 386 uint32_t flags; 387 uint32_t els_cmd; 388 struct completion comp; 389 struct els_logo_payload *els_logo_pyld; 390 dma_addr_t els_logo_pyld_dma; 391 } els_logo; 392 struct { 393 #define ELS_DCMD_PLOGI 0x3 394 uint32_t flags; 395 uint32_t els_cmd; 396 struct completion comp; 397 struct els_plogi_payload *els_plogi_pyld; 398 struct els_plogi_payload *els_resp_pyld; 399 dma_addr_t els_plogi_pyld_dma; 400 dma_addr_t els_resp_pyld_dma; 401 uint32_t fw_status[3]; 402 __le16 comp_status; 403 __le16 len; 404 } els_plogi; 405 struct { 406 /* 407 * Values for flags field below are as 408 * defined in tsk_mgmt_entry struct 409 * for control_flags field in qla_fw.h. 410 */ 411 uint64_t lun; 412 uint32_t flags; 413 uint32_t data; 414 struct completion comp; 415 __le16 comp_status; 416 } tmf; 417 struct { 418 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 419 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 420 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 421 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 422 #define FXDISC_TIMEOUT 20 423 uint8_t flags; 424 uint32_t req_len; 425 uint32_t rsp_len; 426 void *req_addr; 427 void *rsp_addr; 428 dma_addr_t req_dma_handle; 429 dma_addr_t rsp_dma_handle; 430 __le32 adapter_id; 431 __le32 adapter_id_hi; 432 __le16 req_func_type; 433 __le32 req_data; 434 __le32 req_data_extra; 435 __le32 result; 436 __le32 seq_number; 437 __le16 fw_flags; 438 struct completion fxiocb_comp; 439 __le32 reserved_0; 440 uint8_t reserved_1; 441 } fxiocb; 442 struct { 443 uint32_t cmd_hndl; 444 __le16 comp_status; 445 __le16 req_que_no; 446 struct completion comp; 447 } abt; 448 struct ct_arg ctarg; 449 #define MAX_IOCB_MB_REG 28 450 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 451 struct { 452 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 453 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 454 void *out, *in; 455 dma_addr_t out_dma, in_dma; 456 struct completion comp; 457 int rc; 458 } mbx; 459 struct { 460 struct imm_ntfy_from_isp *ntfy; 461 } nack; 462 struct { 463 __le16 comp_status; 464 uint16_t rsp_pyld_len; 465 uint8_t aen_op; 466 void *desc; 467 468 /* These are only used with ls4 requests */ 469 int cmd_len; 470 int rsp_len; 471 dma_addr_t cmd_dma; 472 dma_addr_t rsp_dma; 473 enum nvmefc_fcp_datadir dir; 474 uint32_t dl; 475 uint32_t timeout_sec; 476 struct list_head entry; 477 } nvme; 478 struct { 479 u16 cmd; 480 u16 vp_index; 481 } ctrlvp; 482 } u; 483 484 struct timer_list timer; 485 void (*timeout)(void *); 486 }; 487 488 /* Values for srb_ctx type */ 489 #define SRB_LOGIN_CMD 1 490 #define SRB_LOGOUT_CMD 2 491 #define SRB_ELS_CMD_RPT 3 492 #define SRB_ELS_CMD_HST 4 493 #define SRB_CT_CMD 5 494 #define SRB_ADISC_CMD 6 495 #define SRB_TM_CMD 7 496 #define SRB_SCSI_CMD 8 497 #define SRB_BIDI_CMD 9 498 #define SRB_FXIOCB_DCMD 10 499 #define SRB_FXIOCB_BCMD 11 500 #define SRB_ABT_CMD 12 501 #define SRB_ELS_DCMD 13 502 #define SRB_MB_IOCB 14 503 #define SRB_CT_PTHRU_CMD 15 504 #define SRB_NACK_PLOGI 16 505 #define SRB_NACK_PRLI 17 506 #define SRB_NACK_LOGO 18 507 #define SRB_NVME_CMD 19 508 #define SRB_NVME_LS 20 509 #define SRB_PRLI_CMD 21 510 #define SRB_CTRL_VP 22 511 #define SRB_PRLO_CMD 23 512 513 enum { 514 TYPE_SRB, 515 TYPE_TGT_CMD, 516 }; 517 518 typedef struct srb { 519 /* 520 * Do not move cmd_type field, it needs to 521 * line up with qla_tgt_cmd->cmd_type 522 */ 523 uint8_t cmd_type; 524 uint8_t pad[3]; 525 atomic_t ref_count; 526 wait_queue_head_t nvme_ls_waitq; 527 struct fc_port *fcport; 528 struct scsi_qla_host *vha; 529 uint32_t handle; 530 uint16_t flags; 531 uint16_t type; 532 const char *name; 533 int iocbs; 534 struct qla_qpair *qpair; 535 struct list_head elem; 536 u32 gen1; /* scratch */ 537 u32 gen2; /* scratch */ 538 int rc; 539 int retry_count; 540 struct completion comp; 541 union { 542 struct srb_iocb iocb_cmd; 543 struct bsg_job *bsg_job; 544 struct srb_cmd scmd; 545 } u; 546 void (*done)(void *, int); 547 void (*free)(void *); 548 } srb_t; 549 550 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 551 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 552 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 553 554 #define GET_CMD_SENSE_LEN(sp) \ 555 (sp->u.scmd.request_sense_length) 556 #define SET_CMD_SENSE_LEN(sp, len) \ 557 (sp->u.scmd.request_sense_length = len) 558 #define GET_CMD_SENSE_PTR(sp) \ 559 (sp->u.scmd.request_sense_ptr) 560 #define SET_CMD_SENSE_PTR(sp, ptr) \ 561 (sp->u.scmd.request_sense_ptr = ptr) 562 #define GET_FW_SENSE_LEN(sp) \ 563 (sp->u.scmd.fw_sense_length) 564 #define SET_FW_SENSE_LEN(sp, len) \ 565 (sp->u.scmd.fw_sense_length = len) 566 567 struct msg_echo_lb { 568 dma_addr_t send_dma; 569 dma_addr_t rcv_dma; 570 uint16_t req_sg_cnt; 571 uint16_t rsp_sg_cnt; 572 uint16_t options; 573 uint32_t transfer_size; 574 uint32_t iteration_count; 575 }; 576 577 /* 578 * ISP I/O Register Set structure definitions. 579 */ 580 struct device_reg_2xxx { 581 uint16_t flash_address; /* Flash BIOS address */ 582 uint16_t flash_data; /* Flash BIOS data */ 583 uint16_t unused_1[1]; /* Gap */ 584 uint16_t ctrl_status; /* Control/Status */ 585 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 586 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 587 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 588 589 uint16_t ictrl; /* Interrupt control */ 590 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 591 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 592 593 uint16_t istatus; /* Interrupt status */ 594 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 595 596 uint16_t semaphore; /* Semaphore */ 597 uint16_t nvram; /* NVRAM register. */ 598 #define NVR_DESELECT 0 599 #define NVR_BUSY BIT_15 600 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 601 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 602 #define NVR_DATA_IN BIT_3 603 #define NVR_DATA_OUT BIT_2 604 #define NVR_SELECT BIT_1 605 #define NVR_CLOCK BIT_0 606 607 #define NVR_WAIT_CNT 20000 608 609 union { 610 struct { 611 uint16_t mailbox0; 612 uint16_t mailbox1; 613 uint16_t mailbox2; 614 uint16_t mailbox3; 615 uint16_t mailbox4; 616 uint16_t mailbox5; 617 uint16_t mailbox6; 618 uint16_t mailbox7; 619 uint16_t unused_2[59]; /* Gap */ 620 } __attribute__((packed)) isp2100; 621 struct { 622 /* Request Queue */ 623 uint16_t req_q_in; /* In-Pointer */ 624 uint16_t req_q_out; /* Out-Pointer */ 625 /* Response Queue */ 626 uint16_t rsp_q_in; /* In-Pointer */ 627 uint16_t rsp_q_out; /* Out-Pointer */ 628 629 /* RISC to Host Status */ 630 uint32_t host_status; 631 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 632 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 633 634 /* Host to Host Semaphore */ 635 uint16_t host_semaphore; 636 uint16_t unused_3[17]; /* Gap */ 637 uint16_t mailbox0; 638 uint16_t mailbox1; 639 uint16_t mailbox2; 640 uint16_t mailbox3; 641 uint16_t mailbox4; 642 uint16_t mailbox5; 643 uint16_t mailbox6; 644 uint16_t mailbox7; 645 uint16_t mailbox8; 646 uint16_t mailbox9; 647 uint16_t mailbox10; 648 uint16_t mailbox11; 649 uint16_t mailbox12; 650 uint16_t mailbox13; 651 uint16_t mailbox14; 652 uint16_t mailbox15; 653 uint16_t mailbox16; 654 uint16_t mailbox17; 655 uint16_t mailbox18; 656 uint16_t mailbox19; 657 uint16_t mailbox20; 658 uint16_t mailbox21; 659 uint16_t mailbox22; 660 uint16_t mailbox23; 661 uint16_t mailbox24; 662 uint16_t mailbox25; 663 uint16_t mailbox26; 664 uint16_t mailbox27; 665 uint16_t mailbox28; 666 uint16_t mailbox29; 667 uint16_t mailbox30; 668 uint16_t mailbox31; 669 uint16_t fb_cmd; 670 uint16_t unused_4[10]; /* Gap */ 671 } __attribute__((packed)) isp2300; 672 } u; 673 674 uint16_t fpm_diag_config; 675 uint16_t unused_5[0x4]; /* Gap */ 676 uint16_t risc_hw; 677 uint16_t unused_5_1; /* Gap */ 678 uint16_t pcr; /* Processor Control Register. */ 679 uint16_t unused_6[0x5]; /* Gap */ 680 uint16_t mctr; /* Memory Configuration and Timing. */ 681 uint16_t unused_7[0x3]; /* Gap */ 682 uint16_t fb_cmd_2100; /* Unused on 23XX */ 683 uint16_t unused_8[0x3]; /* Gap */ 684 uint16_t hccr; /* Host command & control register. */ 685 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 686 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 687 /* HCCR commands */ 688 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 689 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 690 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 691 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 692 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 693 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 694 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 695 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 696 697 uint16_t unused_9[5]; /* Gap */ 698 uint16_t gpiod; /* GPIO Data register. */ 699 uint16_t gpioe; /* GPIO Enable register. */ 700 #define GPIO_LED_MASK 0x00C0 701 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 702 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 703 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 704 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 705 #define GPIO_LED_ALL_OFF 0x0000 706 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 707 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 708 709 union { 710 struct { 711 uint16_t unused_10[8]; /* Gap */ 712 uint16_t mailbox8; 713 uint16_t mailbox9; 714 uint16_t mailbox10; 715 uint16_t mailbox11; 716 uint16_t mailbox12; 717 uint16_t mailbox13; 718 uint16_t mailbox14; 719 uint16_t mailbox15; 720 uint16_t mailbox16; 721 uint16_t mailbox17; 722 uint16_t mailbox18; 723 uint16_t mailbox19; 724 uint16_t mailbox20; 725 uint16_t mailbox21; 726 uint16_t mailbox22; 727 uint16_t mailbox23; /* Also probe reg. */ 728 } __attribute__((packed)) isp2200; 729 } u_end; 730 }; 731 732 struct device_reg_25xxmq { 733 uint32_t req_q_in; 734 uint32_t req_q_out; 735 uint32_t rsp_q_in; 736 uint32_t rsp_q_out; 737 uint32_t atio_q_in; 738 uint32_t atio_q_out; 739 }; 740 741 742 struct device_reg_fx00 { 743 uint32_t mailbox0; /* 00 */ 744 uint32_t mailbox1; /* 04 */ 745 uint32_t mailbox2; /* 08 */ 746 uint32_t mailbox3; /* 0C */ 747 uint32_t mailbox4; /* 10 */ 748 uint32_t mailbox5; /* 14 */ 749 uint32_t mailbox6; /* 18 */ 750 uint32_t mailbox7; /* 1C */ 751 uint32_t mailbox8; /* 20 */ 752 uint32_t mailbox9; /* 24 */ 753 uint32_t mailbox10; /* 28 */ 754 uint32_t mailbox11; 755 uint32_t mailbox12; 756 uint32_t mailbox13; 757 uint32_t mailbox14; 758 uint32_t mailbox15; 759 uint32_t mailbox16; 760 uint32_t mailbox17; 761 uint32_t mailbox18; 762 uint32_t mailbox19; 763 uint32_t mailbox20; 764 uint32_t mailbox21; 765 uint32_t mailbox22; 766 uint32_t mailbox23; 767 uint32_t mailbox24; 768 uint32_t mailbox25; 769 uint32_t mailbox26; 770 uint32_t mailbox27; 771 uint32_t mailbox28; 772 uint32_t mailbox29; 773 uint32_t mailbox30; 774 uint32_t mailbox31; 775 uint32_t aenmailbox0; 776 uint32_t aenmailbox1; 777 uint32_t aenmailbox2; 778 uint32_t aenmailbox3; 779 uint32_t aenmailbox4; 780 uint32_t aenmailbox5; 781 uint32_t aenmailbox6; 782 uint32_t aenmailbox7; 783 /* Request Queue. */ 784 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 785 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 786 /* Response Queue. */ 787 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 788 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 789 /* Init values shadowed on FW Up Event */ 790 uint32_t initval0; /* B0 */ 791 uint32_t initval1; /* B4 */ 792 uint32_t initval2; /* B8 */ 793 uint32_t initval3; /* BC */ 794 uint32_t initval4; /* C0 */ 795 uint32_t initval5; /* C4 */ 796 uint32_t initval6; /* C8 */ 797 uint32_t initval7; /* CC */ 798 uint32_t fwheartbeat; /* D0 */ 799 uint32_t pseudoaen; /* D4 */ 800 }; 801 802 803 804 typedef union { 805 struct device_reg_2xxx isp; 806 struct device_reg_24xx isp24; 807 struct device_reg_25xxmq isp25mq; 808 struct device_reg_82xx isp82; 809 struct device_reg_fx00 ispfx00; 810 } __iomem device_reg_t; 811 812 #define ISP_REQ_Q_IN(ha, reg) \ 813 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 814 &(reg)->u.isp2100.mailbox4 : \ 815 &(reg)->u.isp2300.req_q_in) 816 #define ISP_REQ_Q_OUT(ha, reg) \ 817 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 818 &(reg)->u.isp2100.mailbox4 : \ 819 &(reg)->u.isp2300.req_q_out) 820 #define ISP_RSP_Q_IN(ha, reg) \ 821 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 822 &(reg)->u.isp2100.mailbox5 : \ 823 &(reg)->u.isp2300.rsp_q_in) 824 #define ISP_RSP_Q_OUT(ha, reg) \ 825 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 826 &(reg)->u.isp2100.mailbox5 : \ 827 &(reg)->u.isp2300.rsp_q_out) 828 829 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 830 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 831 832 #define MAILBOX_REG(ha, reg, num) \ 833 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 834 (num < 8 ? \ 835 &(reg)->u.isp2100.mailbox0 + (num) : \ 836 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 837 &(reg)->u.isp2300.mailbox0 + (num)) 838 #define RD_MAILBOX_REG(ha, reg, num) \ 839 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 840 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 841 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 842 843 #define FB_CMD_REG(ha, reg) \ 844 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 845 &(reg)->fb_cmd_2100 : \ 846 &(reg)->u.isp2300.fb_cmd) 847 #define RD_FB_CMD_REG(ha, reg) \ 848 RD_REG_WORD(FB_CMD_REG(ha, reg)) 849 #define WRT_FB_CMD_REG(ha, reg, data) \ 850 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 851 852 typedef struct { 853 uint32_t out_mb; /* outbound from driver */ 854 uint32_t in_mb; /* Incoming from RISC */ 855 uint16_t mb[MAILBOX_REGISTER_COUNT]; 856 long buf_size; 857 void *bufp; 858 uint32_t tov; 859 uint8_t flags; 860 #define MBX_DMA_IN BIT_0 861 #define MBX_DMA_OUT BIT_1 862 #define IOCTL_CMD BIT_2 863 } mbx_cmd_t; 864 865 struct mbx_cmd_32 { 866 uint32_t out_mb; /* outbound from driver */ 867 uint32_t in_mb; /* Incoming from RISC */ 868 uint32_t mb[MAILBOX_REGISTER_COUNT]; 869 long buf_size; 870 void *bufp; 871 uint32_t tov; 872 uint8_t flags; 873 #define MBX_DMA_IN BIT_0 874 #define MBX_DMA_OUT BIT_1 875 #define IOCTL_CMD BIT_2 876 }; 877 878 879 #define MBX_TOV_SECONDS 30 880 881 /* 882 * ISP product identification definitions in mailboxes after reset. 883 */ 884 #define PROD_ID_1 0x4953 885 #define PROD_ID_2 0x0000 886 #define PROD_ID_2a 0x5020 887 #define PROD_ID_3 0x2020 888 889 /* 890 * ISP mailbox Self-Test status codes 891 */ 892 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 893 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 894 #define MBS_BUSY 4 /* Busy. */ 895 896 /* 897 * ISP mailbox command complete status codes 898 */ 899 #define MBS_COMMAND_COMPLETE 0x4000 900 #define MBS_INVALID_COMMAND 0x4001 901 #define MBS_HOST_INTERFACE_ERROR 0x4002 902 #define MBS_TEST_FAILED 0x4003 903 #define MBS_COMMAND_ERROR 0x4005 904 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 905 #define MBS_PORT_ID_USED 0x4007 906 #define MBS_LOOP_ID_USED 0x4008 907 #define MBS_ALL_IDS_IN_USE 0x4009 908 #define MBS_NOT_LOGGED_IN 0x400A 909 #define MBS_LINK_DOWN_ERROR 0x400B 910 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 911 912 /* 913 * ISP mailbox asynchronous event status codes 914 */ 915 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 916 #define MBA_RESET 0x8001 /* Reset Detected. */ 917 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 918 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 919 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 920 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 921 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 922 /* occurred. */ 923 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 924 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 925 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 926 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 927 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 928 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 929 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 930 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 931 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 932 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 933 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 934 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 935 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 936 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 937 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 938 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 939 /* used. */ 940 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 941 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 942 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 943 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 944 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 945 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 946 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 947 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 948 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 949 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 950 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 951 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 952 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 953 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 954 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 955 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 956 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 957 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 958 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 959 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 960 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 961 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 962 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 963 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 964 Notification */ 965 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 966 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 967 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 968 /* 83XX FCoE specific */ 969 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 970 971 /* Interrupt type codes */ 972 #define INTR_ROM_MB_SUCCESS 0x1 973 #define INTR_ROM_MB_FAILED 0x2 974 #define INTR_MB_SUCCESS 0x10 975 #define INTR_MB_FAILED 0x11 976 #define INTR_ASYNC_EVENT 0x12 977 #define INTR_RSP_QUE_UPDATE 0x13 978 #define INTR_RSP_QUE_UPDATE_83XX 0x14 979 #define INTR_ATIO_QUE_UPDATE 0x1C 980 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 981 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 982 983 /* ISP mailbox loopback echo diagnostic error code */ 984 #define MBS_LB_RESET 0x17 985 /* 986 * Firmware options 1, 2, 3. 987 */ 988 #define FO1_AE_ON_LIPF8 BIT_0 989 #define FO1_AE_ALL_LIP_RESET BIT_1 990 #define FO1_CTIO_RETRY BIT_3 991 #define FO1_DISABLE_LIP_F7_SW BIT_4 992 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 993 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 994 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 995 #define FO1_SET_EMPHASIS_SWING BIT_8 996 #define FO1_AE_AUTO_BYPASS BIT_9 997 #define FO1_ENABLE_PURE_IOCB BIT_10 998 #define FO1_AE_PLOGI_RJT BIT_11 999 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 1000 #define FO1_AE_QUEUE_FULL BIT_13 1001 1002 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 1003 #define FO2_REV_LOOPBACK BIT_1 1004 1005 #define FO3_ENABLE_EMERG_IOCB BIT_0 1006 #define FO3_AE_RND_ERROR BIT_1 1007 1008 /* 24XX additional firmware options */ 1009 #define ADD_FO_COUNT 3 1010 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 1011 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 1012 1013 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 1014 1015 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 1016 1017 /* 1018 * ISP mailbox commands 1019 */ 1020 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1021 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1022 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 1023 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 1024 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1025 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 1026 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 1027 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 1028 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 1029 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 1030 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 1031 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 1032 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 1033 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 1034 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 1035 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 1036 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1037 #define MBC_RESET 0x18 /* Reset. */ 1038 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1039 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1040 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1041 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1042 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1043 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1044 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1045 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1046 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1047 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1048 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1049 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1050 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1051 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1052 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1053 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1054 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1055 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1056 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1057 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1058 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1059 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1060 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1061 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1062 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1063 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1064 /* Initialization Procedure */ 1065 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1066 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1067 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1068 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1069 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1070 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1071 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1072 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1073 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1074 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1075 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1076 /* commandd. */ 1077 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1078 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1079 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1080 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1081 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1082 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1083 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1084 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1085 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1086 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1087 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1088 1089 /* 1090 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1091 * should be defined with MBC_MR_* 1092 */ 1093 #define MBC_MR_DRV_SHUTDOWN 0x6A 1094 1095 /* 1096 * ISP24xx mailbox commands 1097 */ 1098 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1099 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1100 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1101 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1102 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1103 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1104 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1105 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1106 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1107 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1108 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1109 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1110 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1111 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1112 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1113 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1114 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1115 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1116 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1117 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1118 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1119 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1120 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1121 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1122 1123 /* 1124 * ISP81xx mailbox commands 1125 */ 1126 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1127 1128 /* 1129 * ISP8044 mailbox commands 1130 */ 1131 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1132 #define HCS_WRITE_SERDES 0x3 1133 #define HCS_READ_SERDES 0x4 1134 1135 /* Firmware return data sizes */ 1136 #define FCAL_MAP_SIZE 128 1137 1138 /* Mailbox bit definitions for out_mb and in_mb */ 1139 #define MBX_31 BIT_31 1140 #define MBX_30 BIT_30 1141 #define MBX_29 BIT_29 1142 #define MBX_28 BIT_28 1143 #define MBX_27 BIT_27 1144 #define MBX_26 BIT_26 1145 #define MBX_25 BIT_25 1146 #define MBX_24 BIT_24 1147 #define MBX_23 BIT_23 1148 #define MBX_22 BIT_22 1149 #define MBX_21 BIT_21 1150 #define MBX_20 BIT_20 1151 #define MBX_19 BIT_19 1152 #define MBX_18 BIT_18 1153 #define MBX_17 BIT_17 1154 #define MBX_16 BIT_16 1155 #define MBX_15 BIT_15 1156 #define MBX_14 BIT_14 1157 #define MBX_13 BIT_13 1158 #define MBX_12 BIT_12 1159 #define MBX_11 BIT_11 1160 #define MBX_10 BIT_10 1161 #define MBX_9 BIT_9 1162 #define MBX_8 BIT_8 1163 #define MBX_7 BIT_7 1164 #define MBX_6 BIT_6 1165 #define MBX_5 BIT_5 1166 #define MBX_4 BIT_4 1167 #define MBX_3 BIT_3 1168 #define MBX_2 BIT_2 1169 #define MBX_1 BIT_1 1170 #define MBX_0 BIT_0 1171 1172 #define RNID_TYPE_PORT_LOGIN 0x7 1173 #define RNID_TYPE_SET_VERSION 0x9 1174 #define RNID_TYPE_ASIC_TEMP 0xC 1175 1176 /* 1177 * Firmware state codes from get firmware state mailbox command 1178 */ 1179 #define FSTATE_CONFIG_WAIT 0 1180 #define FSTATE_WAIT_AL_PA 1 1181 #define FSTATE_WAIT_LOGIN 2 1182 #define FSTATE_READY 3 1183 #define FSTATE_LOSS_OF_SYNC 4 1184 #define FSTATE_ERROR 5 1185 #define FSTATE_REINIT 6 1186 #define FSTATE_NON_PART 7 1187 1188 #define FSTATE_CONFIG_CORRECT 0 1189 #define FSTATE_P2P_RCV_LIP 1 1190 #define FSTATE_P2P_CHOOSE_LOOP 2 1191 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1192 #define FSTATE_FATAL_ERROR 4 1193 #define FSTATE_LOOP_BACK_CONN 5 1194 1195 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1196 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1197 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1198 #define QLA27XX_PRIMARY_IMAGE 1 1199 #define QLA27XX_SECONDARY_IMAGE 2 1200 1201 /* 1202 * Port Database structure definition 1203 * Little endian except where noted. 1204 */ 1205 #define PORT_DATABASE_SIZE 128 /* bytes */ 1206 typedef struct { 1207 uint8_t options; 1208 uint8_t control; 1209 uint8_t master_state; 1210 uint8_t slave_state; 1211 uint8_t reserved[2]; 1212 uint8_t hard_address; 1213 uint8_t reserved_1; 1214 uint8_t port_id[4]; 1215 uint8_t node_name[WWN_SIZE]; 1216 uint8_t port_name[WWN_SIZE]; 1217 uint16_t execution_throttle; 1218 uint16_t execution_count; 1219 uint8_t reset_count; 1220 uint8_t reserved_2; 1221 uint16_t resource_allocation; 1222 uint16_t current_allocation; 1223 uint16_t queue_head; 1224 uint16_t queue_tail; 1225 uint16_t transmit_execution_list_next; 1226 uint16_t transmit_execution_list_previous; 1227 uint16_t common_features; 1228 uint16_t total_concurrent_sequences; 1229 uint16_t RO_by_information_category; 1230 uint8_t recipient; 1231 uint8_t initiator; 1232 uint16_t receive_data_size; 1233 uint16_t concurrent_sequences; 1234 uint16_t open_sequences_per_exchange; 1235 uint16_t lun_abort_flags; 1236 uint16_t lun_stop_flags; 1237 uint16_t stop_queue_head; 1238 uint16_t stop_queue_tail; 1239 uint16_t port_retry_timer; 1240 uint16_t next_sequence_id; 1241 uint16_t frame_count; 1242 uint16_t PRLI_payload_length; 1243 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1244 /* Bits 15-0 of word 0 */ 1245 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1246 /* Bits 15-0 of word 3 */ 1247 uint16_t loop_id; 1248 uint16_t extended_lun_info_list_pointer; 1249 uint16_t extended_lun_stop_list_pointer; 1250 } port_database_t; 1251 1252 /* 1253 * Port database slave/master states 1254 */ 1255 #define PD_STATE_DISCOVERY 0 1256 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1257 #define PD_STATE_PORT_LOGIN 2 1258 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1259 #define PD_STATE_PROCESS_LOGIN 4 1260 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1261 #define PD_STATE_PORT_LOGGED_IN 6 1262 #define PD_STATE_PORT_UNAVAILABLE 7 1263 #define PD_STATE_PROCESS_LOGOUT 8 1264 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1265 #define PD_STATE_PORT_LOGOUT 10 1266 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1267 1268 1269 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1270 #define QLA_ZIO_DISABLED 0 1271 #define QLA_ZIO_DEFAULT_TIMER 2 1272 1273 /* 1274 * ISP Initialization Control Block. 1275 * Little endian except where noted. 1276 */ 1277 #define ICB_VERSION 1 1278 typedef struct { 1279 uint8_t version; 1280 uint8_t reserved_1; 1281 1282 /* 1283 * LSB BIT 0 = Enable Hard Loop Id 1284 * LSB BIT 1 = Enable Fairness 1285 * LSB BIT 2 = Enable Full-Duplex 1286 * LSB BIT 3 = Enable Fast Posting 1287 * LSB BIT 4 = Enable Target Mode 1288 * LSB BIT 5 = Disable Initiator Mode 1289 * LSB BIT 6 = Enable ADISC 1290 * LSB BIT 7 = Enable Target Inquiry Data 1291 * 1292 * MSB BIT 0 = Enable PDBC Notify 1293 * MSB BIT 1 = Non Participating LIP 1294 * MSB BIT 2 = Descending Loop ID Search 1295 * MSB BIT 3 = Acquire Loop ID in LIPA 1296 * MSB BIT 4 = Stop PortQ on Full Status 1297 * MSB BIT 5 = Full Login after LIP 1298 * MSB BIT 6 = Node Name Option 1299 * MSB BIT 7 = Ext IFWCB enable bit 1300 */ 1301 uint8_t firmware_options[2]; 1302 1303 uint16_t frame_payload_size; 1304 uint16_t max_iocb_allocation; 1305 uint16_t execution_throttle; 1306 uint8_t retry_count; 1307 uint8_t retry_delay; /* unused */ 1308 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1309 uint16_t hard_address; 1310 uint8_t inquiry_data; 1311 uint8_t login_timeout; 1312 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1313 1314 uint16_t request_q_outpointer; 1315 uint16_t response_q_inpointer; 1316 uint16_t request_q_length; 1317 uint16_t response_q_length; 1318 uint32_t request_q_address[2]; 1319 uint32_t response_q_address[2]; 1320 1321 uint16_t lun_enables; 1322 uint8_t command_resource_count; 1323 uint8_t immediate_notify_resource_count; 1324 uint16_t timeout; 1325 uint8_t reserved_2[2]; 1326 1327 /* 1328 * LSB BIT 0 = Timer Operation mode bit 0 1329 * LSB BIT 1 = Timer Operation mode bit 1 1330 * LSB BIT 2 = Timer Operation mode bit 2 1331 * LSB BIT 3 = Timer Operation mode bit 3 1332 * LSB BIT 4 = Init Config Mode bit 0 1333 * LSB BIT 5 = Init Config Mode bit 1 1334 * LSB BIT 6 = Init Config Mode bit 2 1335 * LSB BIT 7 = Enable Non part on LIHA failure 1336 * 1337 * MSB BIT 0 = Enable class 2 1338 * MSB BIT 1 = Enable ACK0 1339 * MSB BIT 2 = 1340 * MSB BIT 3 = 1341 * MSB BIT 4 = FC Tape Enable 1342 * MSB BIT 5 = Enable FC Confirm 1343 * MSB BIT 6 = Enable command queuing in target mode 1344 * MSB BIT 7 = No Logo On Link Down 1345 */ 1346 uint8_t add_firmware_options[2]; 1347 1348 uint8_t response_accumulation_timer; 1349 uint8_t interrupt_delay_timer; 1350 1351 /* 1352 * LSB BIT 0 = Enable Read xfr_rdy 1353 * LSB BIT 1 = Soft ID only 1354 * LSB BIT 2 = 1355 * LSB BIT 3 = 1356 * LSB BIT 4 = FCP RSP Payload [0] 1357 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1358 * LSB BIT 6 = Enable Out-of-Order frame handling 1359 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1360 * 1361 * MSB BIT 0 = Sbus enable - 2300 1362 * MSB BIT 1 = 1363 * MSB BIT 2 = 1364 * MSB BIT 3 = 1365 * MSB BIT 4 = LED mode 1366 * MSB BIT 5 = enable 50 ohm termination 1367 * MSB BIT 6 = Data Rate (2300 only) 1368 * MSB BIT 7 = Data Rate (2300 only) 1369 */ 1370 uint8_t special_options[2]; 1371 1372 uint8_t reserved_3[26]; 1373 } init_cb_t; 1374 1375 /* 1376 * Get Link Status mailbox command return buffer. 1377 */ 1378 #define GLSO_SEND_RPS BIT_0 1379 #define GLSO_USE_DID BIT_3 1380 1381 struct link_statistics { 1382 uint32_t link_fail_cnt; 1383 uint32_t loss_sync_cnt; 1384 uint32_t loss_sig_cnt; 1385 uint32_t prim_seq_err_cnt; 1386 uint32_t inval_xmit_word_cnt; 1387 uint32_t inval_crc_cnt; 1388 uint32_t lip_cnt; 1389 uint32_t link_up_cnt; 1390 uint32_t link_down_loop_init_tmo; 1391 uint32_t link_down_los; 1392 uint32_t link_down_loss_rcv_clk; 1393 uint32_t reserved0[5]; 1394 uint32_t port_cfg_chg; 1395 uint32_t reserved1[11]; 1396 uint32_t rsp_q_full; 1397 uint32_t atio_q_full; 1398 uint32_t drop_ae; 1399 uint32_t els_proto_err; 1400 uint32_t reserved2; 1401 uint32_t tx_frames; 1402 uint32_t rx_frames; 1403 uint32_t discarded_frames; 1404 uint32_t dropped_frames; 1405 uint32_t reserved3; 1406 uint32_t nos_rcvd; 1407 uint32_t reserved4[4]; 1408 uint32_t tx_prjt; 1409 uint32_t rcv_exfail; 1410 uint32_t rcv_abts; 1411 uint32_t seq_frm_miss; 1412 uint32_t corr_err; 1413 uint32_t mb_rqst; 1414 uint32_t nport_full; 1415 uint32_t eofa; 1416 uint32_t reserved5; 1417 uint32_t fpm_recv_word_cnt_lo; 1418 uint32_t fpm_recv_word_cnt_hi; 1419 uint32_t fpm_disc_word_cnt_lo; 1420 uint32_t fpm_disc_word_cnt_hi; 1421 uint32_t fpm_xmit_word_cnt_lo; 1422 uint32_t fpm_xmit_word_cnt_hi; 1423 uint32_t reserved6[70]; 1424 }; 1425 1426 /* 1427 * NVRAM Command values. 1428 */ 1429 #define NV_START_BIT BIT_2 1430 #define NV_WRITE_OP (BIT_26+BIT_24) 1431 #define NV_READ_OP (BIT_26+BIT_25) 1432 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1433 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1434 #define NV_DELAY_COUNT 10 1435 1436 /* 1437 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1438 */ 1439 typedef struct { 1440 /* 1441 * NVRAM header 1442 */ 1443 uint8_t id[4]; 1444 uint8_t nvram_version; 1445 uint8_t reserved_0; 1446 1447 /* 1448 * NVRAM RISC parameter block 1449 */ 1450 uint8_t parameter_block_version; 1451 uint8_t reserved_1; 1452 1453 /* 1454 * LSB BIT 0 = Enable Hard Loop Id 1455 * LSB BIT 1 = Enable Fairness 1456 * LSB BIT 2 = Enable Full-Duplex 1457 * LSB BIT 3 = Enable Fast Posting 1458 * LSB BIT 4 = Enable Target Mode 1459 * LSB BIT 5 = Disable Initiator Mode 1460 * LSB BIT 6 = Enable ADISC 1461 * LSB BIT 7 = Enable Target Inquiry Data 1462 * 1463 * MSB BIT 0 = Enable PDBC Notify 1464 * MSB BIT 1 = Non Participating LIP 1465 * MSB BIT 2 = Descending Loop ID Search 1466 * MSB BIT 3 = Acquire Loop ID in LIPA 1467 * MSB BIT 4 = Stop PortQ on Full Status 1468 * MSB BIT 5 = Full Login after LIP 1469 * MSB BIT 6 = Node Name Option 1470 * MSB BIT 7 = Ext IFWCB enable bit 1471 */ 1472 uint8_t firmware_options[2]; 1473 1474 uint16_t frame_payload_size; 1475 uint16_t max_iocb_allocation; 1476 uint16_t execution_throttle; 1477 uint8_t retry_count; 1478 uint8_t retry_delay; /* unused */ 1479 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1480 uint16_t hard_address; 1481 uint8_t inquiry_data; 1482 uint8_t login_timeout; 1483 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1484 1485 /* 1486 * LSB BIT 0 = Timer Operation mode bit 0 1487 * LSB BIT 1 = Timer Operation mode bit 1 1488 * LSB BIT 2 = Timer Operation mode bit 2 1489 * LSB BIT 3 = Timer Operation mode bit 3 1490 * LSB BIT 4 = Init Config Mode bit 0 1491 * LSB BIT 5 = Init Config Mode bit 1 1492 * LSB BIT 6 = Init Config Mode bit 2 1493 * LSB BIT 7 = Enable Non part on LIHA failure 1494 * 1495 * MSB BIT 0 = Enable class 2 1496 * MSB BIT 1 = Enable ACK0 1497 * MSB BIT 2 = 1498 * MSB BIT 3 = 1499 * MSB BIT 4 = FC Tape Enable 1500 * MSB BIT 5 = Enable FC Confirm 1501 * MSB BIT 6 = Enable command queuing in target mode 1502 * MSB BIT 7 = No Logo On Link Down 1503 */ 1504 uint8_t add_firmware_options[2]; 1505 1506 uint8_t response_accumulation_timer; 1507 uint8_t interrupt_delay_timer; 1508 1509 /* 1510 * LSB BIT 0 = Enable Read xfr_rdy 1511 * LSB BIT 1 = Soft ID only 1512 * LSB BIT 2 = 1513 * LSB BIT 3 = 1514 * LSB BIT 4 = FCP RSP Payload [0] 1515 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1516 * LSB BIT 6 = Enable Out-of-Order frame handling 1517 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1518 * 1519 * MSB BIT 0 = Sbus enable - 2300 1520 * MSB BIT 1 = 1521 * MSB BIT 2 = 1522 * MSB BIT 3 = 1523 * MSB BIT 4 = LED mode 1524 * MSB BIT 5 = enable 50 ohm termination 1525 * MSB BIT 6 = Data Rate (2300 only) 1526 * MSB BIT 7 = Data Rate (2300 only) 1527 */ 1528 uint8_t special_options[2]; 1529 1530 /* Reserved for expanded RISC parameter block */ 1531 uint8_t reserved_2[22]; 1532 1533 /* 1534 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1535 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1536 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1537 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1538 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1539 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1540 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1541 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1542 * 1543 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1544 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1545 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1546 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1547 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1548 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1549 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1550 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1551 * 1552 * LSB BIT 0 = Output Swing 1G bit 0 1553 * LSB BIT 1 = Output Swing 1G bit 1 1554 * LSB BIT 2 = Output Swing 1G bit 2 1555 * LSB BIT 3 = Output Emphasis 1G bit 0 1556 * LSB BIT 4 = Output Emphasis 1G bit 1 1557 * LSB BIT 5 = Output Swing 2G bit 0 1558 * LSB BIT 6 = Output Swing 2G bit 1 1559 * LSB BIT 7 = Output Swing 2G bit 2 1560 * 1561 * MSB BIT 0 = Output Emphasis 2G bit 0 1562 * MSB BIT 1 = Output Emphasis 2G bit 1 1563 * MSB BIT 2 = Output Enable 1564 * MSB BIT 3 = 1565 * MSB BIT 4 = 1566 * MSB BIT 5 = 1567 * MSB BIT 6 = 1568 * MSB BIT 7 = 1569 */ 1570 uint8_t seriallink_options[4]; 1571 1572 /* 1573 * NVRAM host parameter block 1574 * 1575 * LSB BIT 0 = Enable spinup delay 1576 * LSB BIT 1 = Disable BIOS 1577 * LSB BIT 2 = Enable Memory Map BIOS 1578 * LSB BIT 3 = Enable Selectable Boot 1579 * LSB BIT 4 = Disable RISC code load 1580 * LSB BIT 5 = Set cache line size 1 1581 * LSB BIT 6 = PCI Parity Disable 1582 * LSB BIT 7 = Enable extended logging 1583 * 1584 * MSB BIT 0 = Enable 64bit addressing 1585 * MSB BIT 1 = Enable lip reset 1586 * MSB BIT 2 = Enable lip full login 1587 * MSB BIT 3 = Enable target reset 1588 * MSB BIT 4 = Enable database storage 1589 * MSB BIT 5 = Enable cache flush read 1590 * MSB BIT 6 = Enable database load 1591 * MSB BIT 7 = Enable alternate WWN 1592 */ 1593 uint8_t host_p[2]; 1594 1595 uint8_t boot_node_name[WWN_SIZE]; 1596 uint8_t boot_lun_number; 1597 uint8_t reset_delay; 1598 uint8_t port_down_retry_count; 1599 uint8_t boot_id_number; 1600 uint16_t max_luns_per_target; 1601 uint8_t fcode_boot_port_name[WWN_SIZE]; 1602 uint8_t alternate_port_name[WWN_SIZE]; 1603 uint8_t alternate_node_name[WWN_SIZE]; 1604 1605 /* 1606 * BIT 0 = Selective Login 1607 * BIT 1 = Alt-Boot Enable 1608 * BIT 2 = 1609 * BIT 3 = Boot Order List 1610 * BIT 4 = 1611 * BIT 5 = Selective LUN 1612 * BIT 6 = 1613 * BIT 7 = unused 1614 */ 1615 uint8_t efi_parameters; 1616 1617 uint8_t link_down_timeout; 1618 1619 uint8_t adapter_id[16]; 1620 1621 uint8_t alt1_boot_node_name[WWN_SIZE]; 1622 uint16_t alt1_boot_lun_number; 1623 uint8_t alt2_boot_node_name[WWN_SIZE]; 1624 uint16_t alt2_boot_lun_number; 1625 uint8_t alt3_boot_node_name[WWN_SIZE]; 1626 uint16_t alt3_boot_lun_number; 1627 uint8_t alt4_boot_node_name[WWN_SIZE]; 1628 uint16_t alt4_boot_lun_number; 1629 uint8_t alt5_boot_node_name[WWN_SIZE]; 1630 uint16_t alt5_boot_lun_number; 1631 uint8_t alt6_boot_node_name[WWN_SIZE]; 1632 uint16_t alt6_boot_lun_number; 1633 uint8_t alt7_boot_node_name[WWN_SIZE]; 1634 uint16_t alt7_boot_lun_number; 1635 1636 uint8_t reserved_3[2]; 1637 1638 /* Offset 200-215 : Model Number */ 1639 uint8_t model_number[16]; 1640 1641 /* OEM related items */ 1642 uint8_t oem_specific[16]; 1643 1644 /* 1645 * NVRAM Adapter Features offset 232-239 1646 * 1647 * LSB BIT 0 = External GBIC 1648 * LSB BIT 1 = Risc RAM parity 1649 * LSB BIT 2 = Buffer Plus Module 1650 * LSB BIT 3 = Multi Chip Adapter 1651 * LSB BIT 4 = Internal connector 1652 * LSB BIT 5 = 1653 * LSB BIT 6 = 1654 * LSB BIT 7 = 1655 * 1656 * MSB BIT 0 = 1657 * MSB BIT 1 = 1658 * MSB BIT 2 = 1659 * MSB BIT 3 = 1660 * MSB BIT 4 = 1661 * MSB BIT 5 = 1662 * MSB BIT 6 = 1663 * MSB BIT 7 = 1664 */ 1665 uint8_t adapter_features[2]; 1666 1667 uint8_t reserved_4[16]; 1668 1669 /* Subsystem vendor ID for ISP2200 */ 1670 uint16_t subsystem_vendor_id_2200; 1671 1672 /* Subsystem device ID for ISP2200 */ 1673 uint16_t subsystem_device_id_2200; 1674 1675 uint8_t reserved_5; 1676 uint8_t checksum; 1677 } nvram_t; 1678 1679 /* 1680 * ISP queue - response queue entry definition. 1681 */ 1682 typedef struct { 1683 uint8_t entry_type; /* Entry type. */ 1684 uint8_t entry_count; /* Entry count. */ 1685 uint8_t sys_define; /* System defined. */ 1686 uint8_t entry_status; /* Entry Status. */ 1687 uint32_t handle; /* System defined handle */ 1688 uint8_t data[52]; 1689 uint32_t signature; 1690 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1691 } response_t; 1692 1693 /* 1694 * ISP queue - ATIO queue entry definition. 1695 */ 1696 struct atio { 1697 uint8_t entry_type; /* Entry type. */ 1698 uint8_t entry_count; /* Entry count. */ 1699 __le16 attr_n_length; 1700 uint8_t data[56]; 1701 uint32_t signature; 1702 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1703 }; 1704 1705 typedef union { 1706 uint16_t extended; 1707 struct { 1708 uint8_t reserved; 1709 uint8_t standard; 1710 } id; 1711 } target_id_t; 1712 1713 #define SET_TARGET_ID(ha, to, from) \ 1714 do { \ 1715 if (HAS_EXTENDED_IDS(ha)) \ 1716 to.extended = cpu_to_le16(from); \ 1717 else \ 1718 to.id.standard = (uint8_t)from; \ 1719 } while (0) 1720 1721 /* 1722 * ISP queue - command entry structure definition. 1723 */ 1724 #define COMMAND_TYPE 0x11 /* Command entry */ 1725 typedef struct { 1726 uint8_t entry_type; /* Entry type. */ 1727 uint8_t entry_count; /* Entry count. */ 1728 uint8_t sys_define; /* System defined. */ 1729 uint8_t entry_status; /* Entry Status. */ 1730 uint32_t handle; /* System handle. */ 1731 target_id_t target; /* SCSI ID */ 1732 uint16_t lun; /* SCSI LUN */ 1733 uint16_t control_flags; /* Control flags. */ 1734 #define CF_WRITE BIT_6 1735 #define CF_READ BIT_5 1736 #define CF_SIMPLE_TAG BIT_3 1737 #define CF_ORDERED_TAG BIT_2 1738 #define CF_HEAD_TAG BIT_1 1739 uint16_t reserved_1; 1740 uint16_t timeout; /* Command timeout. */ 1741 uint16_t dseg_count; /* Data segment count. */ 1742 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1743 uint32_t byte_count; /* Total byte count. */ 1744 uint32_t dseg_0_address; /* Data segment 0 address. */ 1745 uint32_t dseg_0_length; /* Data segment 0 length. */ 1746 uint32_t dseg_1_address; /* Data segment 1 address. */ 1747 uint32_t dseg_1_length; /* Data segment 1 length. */ 1748 uint32_t dseg_2_address; /* Data segment 2 address. */ 1749 uint32_t dseg_2_length; /* Data segment 2 length. */ 1750 } cmd_entry_t; 1751 1752 /* 1753 * ISP queue - 64-Bit addressing, command entry structure definition. 1754 */ 1755 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1756 typedef struct { 1757 uint8_t entry_type; /* Entry type. */ 1758 uint8_t entry_count; /* Entry count. */ 1759 uint8_t sys_define; /* System defined. */ 1760 uint8_t entry_status; /* Entry Status. */ 1761 uint32_t handle; /* System handle. */ 1762 target_id_t target; /* SCSI ID */ 1763 uint16_t lun; /* SCSI LUN */ 1764 uint16_t control_flags; /* Control flags. */ 1765 uint16_t reserved_1; 1766 uint16_t timeout; /* Command timeout. */ 1767 uint16_t dseg_count; /* Data segment count. */ 1768 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1769 uint32_t byte_count; /* Total byte count. */ 1770 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1771 uint32_t dseg_0_length; /* Data segment 0 length. */ 1772 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1773 uint32_t dseg_1_length; /* Data segment 1 length. */ 1774 } cmd_a64_entry_t, request_t; 1775 1776 /* 1777 * ISP queue - continuation entry structure definition. 1778 */ 1779 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1780 typedef struct { 1781 uint8_t entry_type; /* Entry type. */ 1782 uint8_t entry_count; /* Entry count. */ 1783 uint8_t sys_define; /* System defined. */ 1784 uint8_t entry_status; /* Entry Status. */ 1785 uint32_t reserved; 1786 uint32_t dseg_0_address; /* Data segment 0 address. */ 1787 uint32_t dseg_0_length; /* Data segment 0 length. */ 1788 uint32_t dseg_1_address; /* Data segment 1 address. */ 1789 uint32_t dseg_1_length; /* Data segment 1 length. */ 1790 uint32_t dseg_2_address; /* Data segment 2 address. */ 1791 uint32_t dseg_2_length; /* Data segment 2 length. */ 1792 uint32_t dseg_3_address; /* Data segment 3 address. */ 1793 uint32_t dseg_3_length; /* Data segment 3 length. */ 1794 uint32_t dseg_4_address; /* Data segment 4 address. */ 1795 uint32_t dseg_4_length; /* Data segment 4 length. */ 1796 uint32_t dseg_5_address; /* Data segment 5 address. */ 1797 uint32_t dseg_5_length; /* Data segment 5 length. */ 1798 uint32_t dseg_6_address; /* Data segment 6 address. */ 1799 uint32_t dseg_6_length; /* Data segment 6 length. */ 1800 } cont_entry_t; 1801 1802 /* 1803 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1804 */ 1805 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1806 typedef struct { 1807 uint8_t entry_type; /* Entry type. */ 1808 uint8_t entry_count; /* Entry count. */ 1809 uint8_t sys_define; /* System defined. */ 1810 uint8_t entry_status; /* Entry Status. */ 1811 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1812 uint32_t dseg_0_length; /* Data segment 0 length. */ 1813 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1814 uint32_t dseg_1_length; /* Data segment 1 length. */ 1815 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1816 uint32_t dseg_2_length; /* Data segment 2 length. */ 1817 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1818 uint32_t dseg_3_length; /* Data segment 3 length. */ 1819 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1820 uint32_t dseg_4_length; /* Data segment 4 length. */ 1821 } cont_a64_entry_t; 1822 1823 #define PO_MODE_DIF_INSERT 0 1824 #define PO_MODE_DIF_REMOVE 1 1825 #define PO_MODE_DIF_PASS 2 1826 #define PO_MODE_DIF_REPLACE 3 1827 #define PO_MODE_DIF_TCP_CKSUM 6 1828 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1829 #define PO_DISABLE_GUARD_CHECK BIT_4 1830 #define PO_DISABLE_INCR_REF_TAG BIT_5 1831 #define PO_DIS_HEADER_MODE BIT_7 1832 #define PO_ENABLE_DIF_BUNDLING BIT_8 1833 #define PO_DIS_FRAME_MODE BIT_9 1834 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1835 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1836 1837 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1838 #define PO_DIS_REF_TAG_REPL BIT_13 1839 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1840 #define PO_DIS_REF_TAG_VALD BIT_15 1841 1842 /* 1843 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1844 */ 1845 struct crc_context { 1846 uint32_t handle; /* System handle. */ 1847 __le32 ref_tag; 1848 __le16 app_tag; 1849 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1850 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1851 __le16 guard_seed; /* Initial Guard Seed */ 1852 __le16 prot_opts; /* Requested Data Protection Mode */ 1853 __le16 blk_size; /* Data size in bytes */ 1854 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1855 * only) */ 1856 __le32 byte_count; /* Total byte count/ total data 1857 * transfer count */ 1858 union { 1859 struct { 1860 uint32_t reserved_1; 1861 uint16_t reserved_2; 1862 uint16_t reserved_3; 1863 uint32_t reserved_4; 1864 uint32_t data_address[2]; 1865 uint32_t data_length; 1866 uint32_t reserved_5[2]; 1867 uint32_t reserved_6; 1868 } nobundling; 1869 struct { 1870 __le32 dif_byte_count; /* Total DIF byte 1871 * count */ 1872 uint16_t reserved_1; 1873 __le16 dseg_count; /* Data segment count */ 1874 uint32_t reserved_2; 1875 uint32_t data_address[2]; 1876 uint32_t data_length; 1877 uint32_t dif_address[2]; 1878 uint32_t dif_length; /* Data segment 0 1879 * length */ 1880 } bundling; 1881 } u; 1882 1883 struct fcp_cmnd fcp_cmnd; 1884 dma_addr_t crc_ctx_dma; 1885 /* List of DMA context transfers */ 1886 struct list_head dsd_list; 1887 1888 /* This structure should not exceed 512 bytes */ 1889 }; 1890 1891 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1892 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1893 1894 /* 1895 * ISP queue - status entry structure definition. 1896 */ 1897 #define STATUS_TYPE 0x03 /* Status entry. */ 1898 typedef struct { 1899 uint8_t entry_type; /* Entry type. */ 1900 uint8_t entry_count; /* Entry count. */ 1901 uint8_t sys_define; /* System defined. */ 1902 uint8_t entry_status; /* Entry Status. */ 1903 uint32_t handle; /* System handle. */ 1904 uint16_t scsi_status; /* SCSI status. */ 1905 uint16_t comp_status; /* Completion status. */ 1906 uint16_t state_flags; /* State flags. */ 1907 uint16_t status_flags; /* Status flags. */ 1908 uint16_t rsp_info_len; /* Response Info Length. */ 1909 uint16_t req_sense_length; /* Request sense data length. */ 1910 uint32_t residual_length; /* Residual transfer length. */ 1911 uint8_t rsp_info[8]; /* FCP response information. */ 1912 uint8_t req_sense_data[32]; /* Request sense data. */ 1913 } sts_entry_t; 1914 1915 /* 1916 * Status entry entry status 1917 */ 1918 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1919 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1920 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1921 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1922 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1923 #define RF_BUSY BIT_1 /* Busy */ 1924 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1925 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1926 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1927 RF_INV_E_TYPE) 1928 1929 /* 1930 * Status entry SCSI status bit definitions. 1931 */ 1932 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1933 #define SS_RESIDUAL_UNDER BIT_11 1934 #define SS_RESIDUAL_OVER BIT_10 1935 #define SS_SENSE_LEN_VALID BIT_9 1936 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1937 #define SS_SCSI_STATUS_BYTE 0xff 1938 1939 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1940 #define SS_BUSY_CONDITION BIT_3 1941 #define SS_CONDITION_MET BIT_2 1942 #define SS_CHECK_CONDITION BIT_1 1943 1944 /* 1945 * Status entry completion status 1946 */ 1947 #define CS_COMPLETE 0x0 /* No errors */ 1948 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1949 #define CS_DMA 0x2 /* A DMA direction error. */ 1950 #define CS_TRANSPORT 0x3 /* Transport error. */ 1951 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1952 #define CS_ABORTED 0x5 /* System aborted command. */ 1953 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1954 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1955 #define CS_DIF_ERROR 0xC /* DIF error detected */ 1956 1957 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1958 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1959 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1960 /* (selection timeout) */ 1961 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1962 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1963 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1964 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1965 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 1966 failure */ 1967 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1968 #define CS_UNKNOWN 0x81 /* Driver defined */ 1969 #define CS_RETRY 0x82 /* Driver defined */ 1970 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1971 1972 #define CS_BIDIR_RD_OVERRUN 0x700 1973 #define CS_BIDIR_RD_WR_OVERRUN 0x707 1974 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 1975 #define CS_BIDIR_RD_UNDERRUN 0x1500 1976 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 1977 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 1978 #define CS_BIDIR_DMA 0x200 1979 /* 1980 * Status entry status flags 1981 */ 1982 #define SF_ABTS_TERMINATED BIT_10 1983 #define SF_LOGOUT_SENT BIT_13 1984 1985 /* 1986 * ISP queue - status continuation entry structure definition. 1987 */ 1988 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1989 typedef struct { 1990 uint8_t entry_type; /* Entry type. */ 1991 uint8_t entry_count; /* Entry count. */ 1992 uint8_t sys_define; /* System defined. */ 1993 uint8_t entry_status; /* Entry Status. */ 1994 uint8_t data[60]; /* data */ 1995 } sts_cont_entry_t; 1996 1997 /* 1998 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1999 * structure definition. 2000 */ 2001 #define STATUS_TYPE_21 0x21 /* Status entry. */ 2002 typedef struct { 2003 uint8_t entry_type; /* Entry type. */ 2004 uint8_t entry_count; /* Entry count. */ 2005 uint8_t handle_count; /* Handle count. */ 2006 uint8_t entry_status; /* Entry Status. */ 2007 uint32_t handle[15]; /* System handles. */ 2008 } sts21_entry_t; 2009 2010 /* 2011 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 2012 * structure definition. 2013 */ 2014 #define STATUS_TYPE_22 0x22 /* Status entry. */ 2015 typedef struct { 2016 uint8_t entry_type; /* Entry type. */ 2017 uint8_t entry_count; /* Entry count. */ 2018 uint8_t handle_count; /* Handle count. */ 2019 uint8_t entry_status; /* Entry Status. */ 2020 uint16_t handle[30]; /* System handles. */ 2021 } sts22_entry_t; 2022 2023 /* 2024 * ISP queue - marker entry structure definition. 2025 */ 2026 #define MARKER_TYPE 0x04 /* Marker entry. */ 2027 typedef struct { 2028 uint8_t entry_type; /* Entry type. */ 2029 uint8_t entry_count; /* Entry count. */ 2030 uint8_t handle_count; /* Handle count. */ 2031 uint8_t entry_status; /* Entry Status. */ 2032 uint32_t sys_define_2; /* System defined. */ 2033 target_id_t target; /* SCSI ID */ 2034 uint8_t modifier; /* Modifier (7-0). */ 2035 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 2036 #define MK_SYNC_ID 1 /* Synchronize ID */ 2037 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2038 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2039 /* clear port changed, */ 2040 /* use sequence number. */ 2041 uint8_t reserved_1; 2042 uint16_t sequence_number; /* Sequence number of event */ 2043 uint16_t lun; /* SCSI LUN */ 2044 uint8_t reserved_2[48]; 2045 } mrk_entry_t; 2046 2047 /* 2048 * ISP queue - Management Server entry structure definition. 2049 */ 2050 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2051 typedef struct { 2052 uint8_t entry_type; /* Entry type. */ 2053 uint8_t entry_count; /* Entry count. */ 2054 uint8_t handle_count; /* Handle count. */ 2055 uint8_t entry_status; /* Entry Status. */ 2056 uint32_t handle1; /* System handle. */ 2057 target_id_t loop_id; 2058 uint16_t status; 2059 uint16_t control_flags; /* Control flags. */ 2060 uint16_t reserved2; 2061 uint16_t timeout; 2062 uint16_t cmd_dsd_count; 2063 uint16_t total_dsd_count; 2064 uint8_t type; 2065 uint8_t r_ctl; 2066 uint16_t rx_id; 2067 uint16_t reserved3; 2068 uint32_t handle2; 2069 uint32_t rsp_bytecount; 2070 uint32_t req_bytecount; 2071 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 2072 uint32_t dseg_req_length; /* Data segment 0 length. */ 2073 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 2074 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 2075 } ms_iocb_entry_t; 2076 2077 2078 /* 2079 * ISP queue - Mailbox Command entry structure definition. 2080 */ 2081 #define MBX_IOCB_TYPE 0x39 2082 struct mbx_entry { 2083 uint8_t entry_type; 2084 uint8_t entry_count; 2085 uint8_t sys_define1; 2086 /* Use sys_define1 for source type */ 2087 #define SOURCE_SCSI 0x00 2088 #define SOURCE_IP 0x01 2089 #define SOURCE_VI 0x02 2090 #define SOURCE_SCTP 0x03 2091 #define SOURCE_MP 0x04 2092 #define SOURCE_MPIOCTL 0x05 2093 #define SOURCE_ASYNC_IOCB 0x07 2094 2095 uint8_t entry_status; 2096 2097 uint32_t handle; 2098 target_id_t loop_id; 2099 2100 uint16_t status; 2101 uint16_t state_flags; 2102 uint16_t status_flags; 2103 2104 uint32_t sys_define2[2]; 2105 2106 uint16_t mb0; 2107 uint16_t mb1; 2108 uint16_t mb2; 2109 uint16_t mb3; 2110 uint16_t mb6; 2111 uint16_t mb7; 2112 uint16_t mb9; 2113 uint16_t mb10; 2114 uint32_t reserved_2[2]; 2115 uint8_t node_name[WWN_SIZE]; 2116 uint8_t port_name[WWN_SIZE]; 2117 }; 2118 2119 #ifndef IMMED_NOTIFY_TYPE 2120 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2121 /* 2122 * ISP queue - immediate notify entry structure definition. 2123 * This is sent by the ISP to the Target driver. 2124 * This IOCB would have report of events sent by the 2125 * initiator, that needs to be handled by the target 2126 * driver immediately. 2127 */ 2128 struct imm_ntfy_from_isp { 2129 uint8_t entry_type; /* Entry type. */ 2130 uint8_t entry_count; /* Entry count. */ 2131 uint8_t sys_define; /* System defined. */ 2132 uint8_t entry_status; /* Entry Status. */ 2133 union { 2134 struct { 2135 uint32_t sys_define_2; /* System defined. */ 2136 target_id_t target; 2137 uint16_t lun; 2138 uint8_t target_id; 2139 uint8_t reserved_1; 2140 uint16_t status_modifier; 2141 uint16_t status; 2142 uint16_t task_flags; 2143 uint16_t seq_id; 2144 uint16_t srr_rx_id; 2145 uint32_t srr_rel_offs; 2146 uint16_t srr_ui; 2147 #define SRR_IU_DATA_IN 0x1 2148 #define SRR_IU_DATA_OUT 0x5 2149 #define SRR_IU_STATUS 0x7 2150 uint16_t srr_ox_id; 2151 uint8_t reserved_2[28]; 2152 } isp2x; 2153 struct { 2154 uint32_t reserved; 2155 uint16_t nport_handle; 2156 uint16_t reserved_2; 2157 uint16_t flags; 2158 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2159 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2160 uint16_t srr_rx_id; 2161 uint16_t status; 2162 uint8_t status_subcode; 2163 uint8_t fw_handle; 2164 uint32_t exchange_address; 2165 uint32_t srr_rel_offs; 2166 uint16_t srr_ui; 2167 uint16_t srr_ox_id; 2168 union { 2169 struct { 2170 uint8_t node_name[8]; 2171 } plogi; /* PLOGI/ADISC/PDISC */ 2172 struct { 2173 /* PRLI word 3 bit 0-15 */ 2174 uint16_t wd3_lo; 2175 uint8_t resv0[6]; 2176 } prli; 2177 struct { 2178 uint8_t port_id[3]; 2179 uint8_t resv1; 2180 uint16_t nport_handle; 2181 uint16_t resv2; 2182 } req_els; 2183 } u; 2184 uint8_t port_name[8]; 2185 uint8_t resv3[3]; 2186 uint8_t vp_index; 2187 uint32_t reserved_5; 2188 uint8_t port_id[3]; 2189 uint8_t reserved_6; 2190 } isp24; 2191 } u; 2192 uint16_t reserved_7; 2193 uint16_t ox_id; 2194 } __packed; 2195 #endif 2196 2197 /* 2198 * ISP request and response queue entry sizes 2199 */ 2200 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2201 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2202 2203 2204 2205 /* 2206 * Switch info gathering structure. 2207 */ 2208 typedef struct { 2209 port_id_t d_id; 2210 uint8_t node_name[WWN_SIZE]; 2211 uint8_t port_name[WWN_SIZE]; 2212 uint8_t fabric_port_name[WWN_SIZE]; 2213 uint16_t fp_speed; 2214 uint8_t fc4_type; 2215 uint8_t fc4f_nvme; /* nvme fc4 feature bits */ 2216 } sw_info_t; 2217 2218 /* FCP-4 types */ 2219 #define FC4_TYPE_FCP_SCSI 0x08 2220 #define FC4_TYPE_NVME 0x28 2221 #define FC4_TYPE_OTHER 0x0 2222 #define FC4_TYPE_UNKNOWN 0xff 2223 2224 /* mailbox command 4G & above */ 2225 struct mbx_24xx_entry { 2226 uint8_t entry_type; 2227 uint8_t entry_count; 2228 uint8_t sys_define1; 2229 uint8_t entry_status; 2230 uint32_t handle; 2231 uint16_t mb[28]; 2232 }; 2233 2234 #define IOCB_SIZE 64 2235 2236 /* 2237 * Fibre channel port type. 2238 */ 2239 typedef enum { 2240 FCT_UNKNOWN, 2241 FCT_RSCN, 2242 FCT_SWITCH, 2243 FCT_BROADCAST, 2244 FCT_INITIATOR, 2245 FCT_TARGET, 2246 FCT_NVME 2247 } fc_port_type_t; 2248 2249 enum qla_sess_deletion { 2250 QLA_SESS_DELETION_NONE = 0, 2251 QLA_SESS_DELETION_IN_PROGRESS, 2252 QLA_SESS_DELETED, 2253 }; 2254 2255 enum qlt_plogi_link_t { 2256 QLT_PLOGI_LINK_SAME_WWN, 2257 QLT_PLOGI_LINK_CONFLICT, 2258 QLT_PLOGI_LINK_MAX 2259 }; 2260 2261 struct qlt_plogi_ack_t { 2262 struct list_head list; 2263 struct imm_ntfy_from_isp iocb; 2264 port_id_t id; 2265 int ref_count; 2266 void *fcport; 2267 }; 2268 2269 struct ct_sns_desc { 2270 struct ct_sns_pkt *ct_sns; 2271 dma_addr_t ct_sns_dma; 2272 }; 2273 2274 enum discovery_state { 2275 DSC_DELETED, 2276 DSC_GNN_ID, 2277 DSC_GID_PN, 2278 DSC_GNL, 2279 DSC_LOGIN_PEND, 2280 DSC_LOGIN_FAILED, 2281 DSC_GPDB, 2282 DSC_UPD_FCPORT, 2283 DSC_LOGIN_COMPLETE, 2284 DSC_ADISC, 2285 DSC_DELETE_PEND, 2286 }; 2287 2288 enum login_state { /* FW control Target side */ 2289 DSC_LS_LLIOCB_SENT = 2, 2290 DSC_LS_PLOGI_PEND, 2291 DSC_LS_PLOGI_COMP, 2292 DSC_LS_PRLI_PEND, 2293 DSC_LS_PRLI_COMP, 2294 DSC_LS_PORT_UNAVAIL, 2295 DSC_LS_PRLO_PEND = 9, 2296 DSC_LS_LOGO_PEND, 2297 }; 2298 2299 enum fcport_mgt_event { 2300 FCME_RELOGIN = 1, 2301 FCME_RSCN, 2302 FCME_GIDPN_DONE, 2303 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */ 2304 FCME_PRLI_DONE, 2305 FCME_GNL_DONE, 2306 FCME_GPSC_DONE, 2307 FCME_GPDB_DONE, 2308 FCME_GPNID_DONE, 2309 FCME_GFFID_DONE, 2310 FCME_ADISC_DONE, 2311 FCME_GNNID_DONE, 2312 FCME_GFPNID_DONE, 2313 }; 2314 2315 enum rscn_addr_format { 2316 RSCN_PORT_ADDR, 2317 RSCN_AREA_ADDR, 2318 RSCN_DOM_ADDR, 2319 RSCN_FAB_ADDR, 2320 }; 2321 2322 /* 2323 * Fibre channel port structure. 2324 */ 2325 typedef struct fc_port { 2326 struct list_head list; 2327 struct scsi_qla_host *vha; 2328 2329 uint8_t node_name[WWN_SIZE]; 2330 uint8_t port_name[WWN_SIZE]; 2331 port_id_t d_id; 2332 uint16_t loop_id; 2333 uint16_t old_loop_id; 2334 2335 unsigned int conf_compl_supported:1; 2336 unsigned int deleted:2; 2337 unsigned int free_pending:1; 2338 unsigned int local:1; 2339 unsigned int logout_on_delete:1; 2340 unsigned int logo_ack_needed:1; 2341 unsigned int keep_nport_handle:1; 2342 unsigned int send_els_logo:1; 2343 unsigned int login_pause:1; 2344 unsigned int login_succ:1; 2345 unsigned int query:1; 2346 unsigned int id_changed:1; 2347 unsigned int rscn_rcvd:1; 2348 2349 struct work_struct nvme_del_work; 2350 struct completion nvme_del_done; 2351 uint32_t nvme_prli_service_param; 2352 #define NVME_PRLI_SP_CONF BIT_7 2353 #define NVME_PRLI_SP_INITIATOR BIT_5 2354 #define NVME_PRLI_SP_TARGET BIT_4 2355 #define NVME_PRLI_SP_DISCOVERY BIT_3 2356 uint8_t nvme_flag; 2357 #define NVME_FLAG_REGISTERED 4 2358 #define NVME_FLAG_DELETING 2 2359 #define NVME_FLAG_RESETTING 1 2360 2361 struct fc_port *conflict; 2362 unsigned char logout_completed; 2363 int generation; 2364 2365 struct se_session *se_sess; 2366 struct kref sess_kref; 2367 struct qla_tgt *tgt; 2368 unsigned long expires; 2369 struct list_head del_list_entry; 2370 struct work_struct free_work; 2371 2372 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2373 2374 uint16_t tgt_id; 2375 uint16_t old_tgt_id; 2376 2377 uint8_t fcp_prio; 2378 2379 uint8_t fabric_port_name[WWN_SIZE]; 2380 uint16_t fp_speed; 2381 2382 fc_port_type_t port_type; 2383 2384 atomic_t state; 2385 uint32_t flags; 2386 2387 int login_retry; 2388 2389 struct fc_rport *rport, *drport; 2390 u32 supported_classes; 2391 2392 uint8_t fc4_type; 2393 uint8_t fc4f_nvme; 2394 uint8_t scan_state; 2395 uint8_t n2n_flag; 2396 2397 unsigned long last_queue_full; 2398 unsigned long last_ramp_up; 2399 2400 uint16_t port_id; 2401 2402 struct nvme_fc_remote_port *nvme_remote_port; 2403 2404 unsigned long retry_delay_timestamp; 2405 struct qla_tgt_sess *tgt_session; 2406 struct ct_sns_desc ct_desc; 2407 enum discovery_state disc_state; 2408 enum login_state fw_login_state; 2409 unsigned long plogi_nack_done_deadline; 2410 2411 u32 login_gen, last_login_gen; 2412 u32 rscn_gen, last_rscn_gen; 2413 u32 chip_reset; 2414 struct list_head gnl_entry; 2415 struct work_struct del_work; 2416 u8 iocb[IOCB_SIZE]; 2417 u8 current_login_state; 2418 u8 last_login_state; 2419 struct completion n2n_done; 2420 } fc_port_t; 2421 2422 #define QLA_FCPORT_SCAN 1 2423 #define QLA_FCPORT_FOUND 2 2424 2425 struct event_arg { 2426 enum fcport_mgt_event event; 2427 fc_port_t *fcport; 2428 srb_t *sp; 2429 port_id_t id; 2430 u16 data[2], rc; 2431 u8 port_name[WWN_SIZE]; 2432 u32 iop[2]; 2433 }; 2434 2435 #include "qla_mr.h" 2436 2437 /* 2438 * Fibre channel port/lun states. 2439 */ 2440 #define FCS_UNCONFIGURED 1 2441 #define FCS_DEVICE_DEAD 2 2442 #define FCS_DEVICE_LOST 3 2443 #define FCS_ONLINE 4 2444 2445 static const char * const port_state_str[] = { 2446 "Unknown", 2447 "UNCONFIGURED", 2448 "DEAD", 2449 "LOST", 2450 "ONLINE" 2451 }; 2452 2453 /* 2454 * FC port flags. 2455 */ 2456 #define FCF_FABRIC_DEVICE BIT_0 2457 #define FCF_LOGIN_NEEDED BIT_1 2458 #define FCF_FCP2_DEVICE BIT_2 2459 #define FCF_ASYNC_SENT BIT_3 2460 #define FCF_CONF_COMP_SUPPORTED BIT_4 2461 #define FCF_ASYNC_ACTIVE BIT_5 2462 2463 /* No loop ID flag. */ 2464 #define FC_NO_LOOP_ID 0x1000 2465 2466 /* 2467 * FC-CT interface 2468 * 2469 * NOTE: All structures are big-endian in form. 2470 */ 2471 2472 #define CT_REJECT_RESPONSE 0x8001 2473 #define CT_ACCEPT_RESPONSE 0x8002 2474 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2475 #define CT_REASON_CANNOT_PERFORM 0x09 2476 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2477 #define CT_EXPL_ALREADY_REGISTERED 0x10 2478 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2479 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2480 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2481 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2482 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2483 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2484 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2485 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2486 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2487 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2488 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2489 2490 #define NS_N_PORT_TYPE 0x01 2491 #define NS_NL_PORT_TYPE 0x02 2492 #define NS_NX_PORT_TYPE 0x7F 2493 2494 #define GA_NXT_CMD 0x100 2495 #define GA_NXT_REQ_SIZE (16 + 4) 2496 #define GA_NXT_RSP_SIZE (16 + 620) 2497 2498 #define GPN_FT_CMD 0x172 2499 #define GPN_FT_REQ_SIZE (16 + 4) 2500 #define GNN_FT_CMD 0x173 2501 #define GNN_FT_REQ_SIZE (16 + 4) 2502 2503 #define GID_PT_CMD 0x1A1 2504 #define GID_PT_REQ_SIZE (16 + 4) 2505 2506 #define GPN_ID_CMD 0x112 2507 #define GPN_ID_REQ_SIZE (16 + 4) 2508 #define GPN_ID_RSP_SIZE (16 + 8) 2509 2510 #define GNN_ID_CMD 0x113 2511 #define GNN_ID_REQ_SIZE (16 + 4) 2512 #define GNN_ID_RSP_SIZE (16 + 8) 2513 2514 #define GFT_ID_CMD 0x117 2515 #define GFT_ID_REQ_SIZE (16 + 4) 2516 #define GFT_ID_RSP_SIZE (16 + 32) 2517 2518 #define GID_PN_CMD 0x121 2519 #define GID_PN_REQ_SIZE (16 + 8) 2520 #define GID_PN_RSP_SIZE (16 + 4) 2521 2522 #define RFT_ID_CMD 0x217 2523 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2524 #define RFT_ID_RSP_SIZE 16 2525 2526 #define RFF_ID_CMD 0x21F 2527 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2528 #define RFF_ID_RSP_SIZE 16 2529 2530 #define RNN_ID_CMD 0x213 2531 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2532 #define RNN_ID_RSP_SIZE 16 2533 2534 #define RSNN_NN_CMD 0x239 2535 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2536 #define RSNN_NN_RSP_SIZE 16 2537 2538 #define GFPN_ID_CMD 0x11C 2539 #define GFPN_ID_REQ_SIZE (16 + 4) 2540 #define GFPN_ID_RSP_SIZE (16 + 8) 2541 2542 #define GPSC_CMD 0x127 2543 #define GPSC_REQ_SIZE (16 + 8) 2544 #define GPSC_RSP_SIZE (16 + 2 + 2) 2545 2546 #define GFF_ID_CMD 0x011F 2547 #define GFF_ID_REQ_SIZE (16 + 4) 2548 #define GFF_ID_RSP_SIZE (16 + 128) 2549 2550 /* 2551 * HBA attribute types. 2552 */ 2553 #define FDMI_HBA_ATTR_COUNT 9 2554 #define FDMIV2_HBA_ATTR_COUNT 17 2555 #define FDMI_HBA_NODE_NAME 0x1 2556 #define FDMI_HBA_MANUFACTURER 0x2 2557 #define FDMI_HBA_SERIAL_NUMBER 0x3 2558 #define FDMI_HBA_MODEL 0x4 2559 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2560 #define FDMI_HBA_HARDWARE_VERSION 0x6 2561 #define FDMI_HBA_DRIVER_VERSION 0x7 2562 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2563 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2564 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2565 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2566 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2567 #define FDMI_HBA_VENDOR_ID 0xd 2568 #define FDMI_HBA_NUM_PORTS 0xe 2569 #define FDMI_HBA_FABRIC_NAME 0xf 2570 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2571 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0 2572 2573 struct ct_fdmi_hba_attr { 2574 uint16_t type; 2575 uint16_t len; 2576 union { 2577 uint8_t node_name[WWN_SIZE]; 2578 uint8_t manufacturer[64]; 2579 uint8_t serial_num[32]; 2580 uint8_t model[16+1]; 2581 uint8_t model_desc[80]; 2582 uint8_t hw_version[32]; 2583 uint8_t driver_version[32]; 2584 uint8_t orom_version[16]; 2585 uint8_t fw_version[32]; 2586 uint8_t os_version[128]; 2587 uint32_t max_ct_len; 2588 } a; 2589 }; 2590 2591 struct ct_fdmi_hba_attributes { 2592 uint32_t count; 2593 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2594 }; 2595 2596 struct ct_fdmiv2_hba_attr { 2597 uint16_t type; 2598 uint16_t len; 2599 union { 2600 uint8_t node_name[WWN_SIZE]; 2601 uint8_t manufacturer[64]; 2602 uint8_t serial_num[32]; 2603 uint8_t model[16+1]; 2604 uint8_t model_desc[80]; 2605 uint8_t hw_version[16]; 2606 uint8_t driver_version[32]; 2607 uint8_t orom_version[16]; 2608 uint8_t fw_version[32]; 2609 uint8_t os_version[128]; 2610 uint32_t max_ct_len; 2611 uint8_t sym_name[256]; 2612 uint32_t vendor_id; 2613 uint32_t num_ports; 2614 uint8_t fabric_name[WWN_SIZE]; 2615 uint8_t bios_name[32]; 2616 uint8_t vendor_identifier[8]; 2617 } a; 2618 }; 2619 2620 struct ct_fdmiv2_hba_attributes { 2621 uint32_t count; 2622 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT]; 2623 }; 2624 2625 /* 2626 * Port attribute types. 2627 */ 2628 #define FDMI_PORT_ATTR_COUNT 6 2629 #define FDMIV2_PORT_ATTR_COUNT 16 2630 #define FDMI_PORT_FC4_TYPES 0x1 2631 #define FDMI_PORT_SUPPORT_SPEED 0x2 2632 #define FDMI_PORT_CURRENT_SPEED 0x3 2633 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2634 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2635 #define FDMI_PORT_HOST_NAME 0x6 2636 #define FDMI_PORT_NODE_NAME 0x7 2637 #define FDMI_PORT_NAME 0x8 2638 #define FDMI_PORT_SYM_NAME 0x9 2639 #define FDMI_PORT_TYPE 0xa 2640 #define FDMI_PORT_SUPP_COS 0xb 2641 #define FDMI_PORT_FABRIC_NAME 0xc 2642 #define FDMI_PORT_FC4_TYPE 0xd 2643 #define FDMI_PORT_STATE 0x101 2644 #define FDMI_PORT_COUNT 0x102 2645 #define FDMI_PORT_ID 0x103 2646 2647 #define FDMI_PORT_SPEED_1GB 0x1 2648 #define FDMI_PORT_SPEED_2GB 0x2 2649 #define FDMI_PORT_SPEED_10GB 0x4 2650 #define FDMI_PORT_SPEED_4GB 0x8 2651 #define FDMI_PORT_SPEED_8GB 0x10 2652 #define FDMI_PORT_SPEED_16GB 0x20 2653 #define FDMI_PORT_SPEED_32GB 0x40 2654 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2655 2656 #define FC_CLASS_2 0x04 2657 #define FC_CLASS_3 0x08 2658 #define FC_CLASS_2_3 0x0C 2659 2660 struct ct_fdmiv2_port_attr { 2661 uint16_t type; 2662 uint16_t len; 2663 union { 2664 uint8_t fc4_types[32]; 2665 uint32_t sup_speed; 2666 uint32_t cur_speed; 2667 uint32_t max_frame_size; 2668 uint8_t os_dev_name[32]; 2669 uint8_t host_name[256]; 2670 uint8_t node_name[WWN_SIZE]; 2671 uint8_t port_name[WWN_SIZE]; 2672 uint8_t port_sym_name[128]; 2673 uint32_t port_type; 2674 uint32_t port_supported_cos; 2675 uint8_t fabric_name[WWN_SIZE]; 2676 uint8_t port_fc4_type[32]; 2677 uint32_t port_state; 2678 uint32_t num_ports; 2679 uint32_t port_id; 2680 } a; 2681 }; 2682 2683 /* 2684 * Port Attribute Block. 2685 */ 2686 struct ct_fdmiv2_port_attributes { 2687 uint32_t count; 2688 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT]; 2689 }; 2690 2691 struct ct_fdmi_port_attr { 2692 uint16_t type; 2693 uint16_t len; 2694 union { 2695 uint8_t fc4_types[32]; 2696 uint32_t sup_speed; 2697 uint32_t cur_speed; 2698 uint32_t max_frame_size; 2699 uint8_t os_dev_name[32]; 2700 uint8_t host_name[256]; 2701 } a; 2702 }; 2703 2704 struct ct_fdmi_port_attributes { 2705 uint32_t count; 2706 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2707 }; 2708 2709 /* FDMI definitions. */ 2710 #define GRHL_CMD 0x100 2711 #define GHAT_CMD 0x101 2712 #define GRPL_CMD 0x102 2713 #define GPAT_CMD 0x110 2714 2715 #define RHBA_CMD 0x200 2716 #define RHBA_RSP_SIZE 16 2717 2718 #define RHAT_CMD 0x201 2719 #define RPRT_CMD 0x210 2720 2721 #define RPA_CMD 0x211 2722 #define RPA_RSP_SIZE 16 2723 2724 #define DHBA_CMD 0x300 2725 #define DHBA_REQ_SIZE (16 + 8) 2726 #define DHBA_RSP_SIZE 16 2727 2728 #define DHAT_CMD 0x301 2729 #define DPRT_CMD 0x310 2730 #define DPA_CMD 0x311 2731 2732 /* CT command header -- request/response common fields */ 2733 struct ct_cmd_hdr { 2734 uint8_t revision; 2735 uint8_t in_id[3]; 2736 uint8_t gs_type; 2737 uint8_t gs_subtype; 2738 uint8_t options; 2739 uint8_t reserved; 2740 }; 2741 2742 /* CT command request */ 2743 struct ct_sns_req { 2744 struct ct_cmd_hdr header; 2745 uint16_t command; 2746 uint16_t max_rsp_size; 2747 uint8_t fragment_id; 2748 uint8_t reserved[3]; 2749 2750 union { 2751 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2752 struct { 2753 uint8_t reserved; 2754 uint8_t port_id[3]; 2755 } port_id; 2756 2757 struct { 2758 uint8_t reserved; 2759 uint8_t domain; 2760 uint8_t area; 2761 uint8_t port_type; 2762 } gpn_ft; 2763 2764 struct { 2765 uint8_t port_type; 2766 uint8_t domain; 2767 uint8_t area; 2768 uint8_t reserved; 2769 } gid_pt; 2770 2771 struct { 2772 uint8_t reserved; 2773 uint8_t port_id[3]; 2774 uint8_t fc4_types[32]; 2775 } rft_id; 2776 2777 struct { 2778 uint8_t reserved; 2779 uint8_t port_id[3]; 2780 uint16_t reserved2; 2781 uint8_t fc4_feature; 2782 uint8_t fc4_type; 2783 } rff_id; 2784 2785 struct { 2786 uint8_t reserved; 2787 uint8_t port_id[3]; 2788 uint8_t node_name[8]; 2789 } rnn_id; 2790 2791 struct { 2792 uint8_t node_name[8]; 2793 uint8_t name_len; 2794 uint8_t sym_node_name[255]; 2795 } rsnn_nn; 2796 2797 struct { 2798 uint8_t hba_identifier[8]; 2799 } ghat; 2800 2801 struct { 2802 uint8_t hba_identifier[8]; 2803 uint32_t entry_count; 2804 uint8_t port_name[8]; 2805 struct ct_fdmi_hba_attributes attrs; 2806 } rhba; 2807 2808 struct { 2809 uint8_t hba_identifier[8]; 2810 uint32_t entry_count; 2811 uint8_t port_name[8]; 2812 struct ct_fdmiv2_hba_attributes attrs; 2813 } rhba2; 2814 2815 struct { 2816 uint8_t hba_identifier[8]; 2817 struct ct_fdmi_hba_attributes attrs; 2818 } rhat; 2819 2820 struct { 2821 uint8_t port_name[8]; 2822 struct ct_fdmi_port_attributes attrs; 2823 } rpa; 2824 2825 struct { 2826 uint8_t port_name[8]; 2827 struct ct_fdmiv2_port_attributes attrs; 2828 } rpa2; 2829 2830 struct { 2831 uint8_t port_name[8]; 2832 } dhba; 2833 2834 struct { 2835 uint8_t port_name[8]; 2836 } dhat; 2837 2838 struct { 2839 uint8_t port_name[8]; 2840 } dprt; 2841 2842 struct { 2843 uint8_t port_name[8]; 2844 } dpa; 2845 2846 struct { 2847 uint8_t port_name[8]; 2848 } gpsc; 2849 2850 struct { 2851 uint8_t reserved; 2852 uint8_t port_id[3]; 2853 } gff_id; 2854 2855 struct { 2856 uint8_t port_name[8]; 2857 } gid_pn; 2858 } req; 2859 }; 2860 2861 /* CT command response header */ 2862 struct ct_rsp_hdr { 2863 struct ct_cmd_hdr header; 2864 uint16_t response; 2865 uint16_t residual; 2866 uint8_t fragment_id; 2867 uint8_t reason_code; 2868 uint8_t explanation_code; 2869 uint8_t vendor_unique; 2870 }; 2871 2872 struct ct_sns_gid_pt_data { 2873 uint8_t control_byte; 2874 uint8_t port_id[3]; 2875 }; 2876 2877 /* It's the same for both GPN_FT and GNN_FT */ 2878 struct ct_sns_gpnft_rsp { 2879 struct { 2880 struct ct_cmd_hdr header; 2881 uint16_t response; 2882 uint16_t residual; 2883 uint8_t fragment_id; 2884 uint8_t reason_code; 2885 uint8_t explanation_code; 2886 uint8_t vendor_unique; 2887 }; 2888 /* Assume the largest number of targets for the union */ 2889 struct ct_sns_gpn_ft_data { 2890 u8 control_byte; 2891 u8 port_id[3]; 2892 u32 reserved; 2893 u8 port_name[8]; 2894 } entries[1]; 2895 }; 2896 2897 /* CT command response */ 2898 struct ct_sns_rsp { 2899 struct ct_rsp_hdr header; 2900 2901 union { 2902 struct { 2903 uint8_t port_type; 2904 uint8_t port_id[3]; 2905 uint8_t port_name[8]; 2906 uint8_t sym_port_name_len; 2907 uint8_t sym_port_name[255]; 2908 uint8_t node_name[8]; 2909 uint8_t sym_node_name_len; 2910 uint8_t sym_node_name[255]; 2911 uint8_t init_proc_assoc[8]; 2912 uint8_t node_ip_addr[16]; 2913 uint8_t class_of_service[4]; 2914 uint8_t fc4_types[32]; 2915 uint8_t ip_address[16]; 2916 uint8_t fabric_port_name[8]; 2917 uint8_t reserved; 2918 uint8_t hard_address[3]; 2919 } ga_nxt; 2920 2921 struct { 2922 /* Assume the largest number of targets for the union */ 2923 struct ct_sns_gid_pt_data 2924 entries[MAX_FIBRE_DEVICES_MAX]; 2925 } gid_pt; 2926 2927 struct { 2928 uint8_t port_name[8]; 2929 } gpn_id; 2930 2931 struct { 2932 uint8_t node_name[8]; 2933 } gnn_id; 2934 2935 struct { 2936 uint8_t fc4_types[32]; 2937 } gft_id; 2938 2939 struct { 2940 uint32_t entry_count; 2941 uint8_t port_name[8]; 2942 struct ct_fdmi_hba_attributes attrs; 2943 } ghat; 2944 2945 struct { 2946 uint8_t port_name[8]; 2947 } gfpn_id; 2948 2949 struct { 2950 uint16_t speeds; 2951 uint16_t speed; 2952 } gpsc; 2953 2954 #define GFF_FCP_SCSI_OFFSET 7 2955 #define GFF_NVME_OFFSET 23 /* type = 28h */ 2956 struct { 2957 uint8_t fc4_features[128]; 2958 } gff_id; 2959 struct { 2960 uint8_t reserved; 2961 uint8_t port_id[3]; 2962 } gid_pn; 2963 } rsp; 2964 }; 2965 2966 struct ct_sns_pkt { 2967 union { 2968 struct ct_sns_req req; 2969 struct ct_sns_rsp rsp; 2970 } p; 2971 }; 2972 2973 struct ct_sns_gpnft_pkt { 2974 union { 2975 struct ct_sns_req req; 2976 struct ct_sns_gpnft_rsp rsp; 2977 } p; 2978 }; 2979 2980 enum scan_flags_t { 2981 SF_SCANNING = BIT_0, 2982 SF_QUEUED = BIT_1, 2983 }; 2984 2985 enum fc4type_t { 2986 FS_FC4TYPE_FCP = BIT_0, 2987 FS_FC4TYPE_NVME = BIT_1, 2988 }; 2989 2990 struct fab_scan_rp { 2991 port_id_t id; 2992 enum fc4type_t fc4type; 2993 u8 port_name[8]; 2994 u8 node_name[8]; 2995 }; 2996 2997 struct fab_scan { 2998 struct fab_scan_rp *l; 2999 u32 size; 3000 u16 scan_retry; 3001 #define MAX_SCAN_RETRIES 5 3002 enum scan_flags_t scan_flags; 3003 struct delayed_work scan_work; 3004 }; 3005 3006 /* 3007 * SNS command structures -- for 2200 compatibility. 3008 */ 3009 #define RFT_ID_SNS_SCMD_LEN 22 3010 #define RFT_ID_SNS_CMD_SIZE 60 3011 #define RFT_ID_SNS_DATA_SIZE 16 3012 3013 #define RNN_ID_SNS_SCMD_LEN 10 3014 #define RNN_ID_SNS_CMD_SIZE 36 3015 #define RNN_ID_SNS_DATA_SIZE 16 3016 3017 #define GA_NXT_SNS_SCMD_LEN 6 3018 #define GA_NXT_SNS_CMD_SIZE 28 3019 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 3020 3021 #define GID_PT_SNS_SCMD_LEN 6 3022 #define GID_PT_SNS_CMD_SIZE 28 3023 /* 3024 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 3025 * adapters. 3026 */ 3027 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 3028 3029 #define GPN_ID_SNS_SCMD_LEN 6 3030 #define GPN_ID_SNS_CMD_SIZE 28 3031 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 3032 3033 #define GNN_ID_SNS_SCMD_LEN 6 3034 #define GNN_ID_SNS_CMD_SIZE 28 3035 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 3036 3037 struct sns_cmd_pkt { 3038 union { 3039 struct { 3040 uint16_t buffer_length; 3041 uint16_t reserved_1; 3042 uint32_t buffer_address[2]; 3043 uint16_t subcommand_length; 3044 uint16_t reserved_2; 3045 uint16_t subcommand; 3046 uint16_t size; 3047 uint32_t reserved_3; 3048 uint8_t param[36]; 3049 } cmd; 3050 3051 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 3052 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 3053 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 3054 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 3055 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 3056 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 3057 } p; 3058 }; 3059 3060 struct fw_blob { 3061 char *name; 3062 uint32_t segs[4]; 3063 const struct firmware *fw; 3064 }; 3065 3066 /* Return data from MBC_GET_ID_LIST call. */ 3067 struct gid_list_info { 3068 uint8_t al_pa; 3069 uint8_t area; 3070 uint8_t domain; 3071 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 3072 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 3073 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 3074 }; 3075 3076 /* NPIV */ 3077 typedef struct vport_info { 3078 uint8_t port_name[WWN_SIZE]; 3079 uint8_t node_name[WWN_SIZE]; 3080 int vp_id; 3081 uint16_t loop_id; 3082 unsigned long host_no; 3083 uint8_t port_id[3]; 3084 int loop_state; 3085 } vport_info_t; 3086 3087 typedef struct vport_params { 3088 uint8_t port_name[WWN_SIZE]; 3089 uint8_t node_name[WWN_SIZE]; 3090 uint32_t options; 3091 #define VP_OPTS_RETRY_ENABLE BIT_0 3092 #define VP_OPTS_VP_DISABLE BIT_1 3093 } vport_params_t; 3094 3095 /* NPIV - return codes of VP create and modify */ 3096 #define VP_RET_CODE_OK 0 3097 #define VP_RET_CODE_FATAL 1 3098 #define VP_RET_CODE_WRONG_ID 2 3099 #define VP_RET_CODE_WWPN 3 3100 #define VP_RET_CODE_RESOURCES 4 3101 #define VP_RET_CODE_NO_MEM 5 3102 #define VP_RET_CODE_NOT_FOUND 6 3103 3104 struct qla_hw_data; 3105 struct rsp_que; 3106 /* 3107 * ISP operations 3108 */ 3109 struct isp_operations { 3110 3111 int (*pci_config) (struct scsi_qla_host *); 3112 void (*reset_chip) (struct scsi_qla_host *); 3113 int (*chip_diag) (struct scsi_qla_host *); 3114 void (*config_rings) (struct scsi_qla_host *); 3115 void (*reset_adapter) (struct scsi_qla_host *); 3116 int (*nvram_config) (struct scsi_qla_host *); 3117 void (*update_fw_options) (struct scsi_qla_host *); 3118 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3119 3120 char * (*pci_info_str) (struct scsi_qla_host *, char *); 3121 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3122 3123 irq_handler_t intr_handler; 3124 void (*enable_intrs) (struct qla_hw_data *); 3125 void (*disable_intrs) (struct qla_hw_data *); 3126 3127 int (*abort_command) (srb_t *); 3128 int (*target_reset) (struct fc_port *, uint64_t, int); 3129 int (*lun_reset) (struct fc_port *, uint64_t, int); 3130 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3131 uint8_t, uint8_t, uint16_t *, uint8_t); 3132 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3133 uint8_t, uint8_t); 3134 3135 uint16_t (*calc_req_entries) (uint16_t); 3136 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3137 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3138 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3139 uint32_t); 3140 3141 uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *, 3142 uint32_t, uint32_t); 3143 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 3144 uint32_t); 3145 3146 void (*fw_dump) (struct scsi_qla_host *, int); 3147 3148 int (*beacon_on) (struct scsi_qla_host *); 3149 int (*beacon_off) (struct scsi_qla_host *); 3150 void (*beacon_blink) (struct scsi_qla_host *); 3151 3152 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 3153 uint32_t, uint32_t); 3154 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 3155 uint32_t); 3156 3157 int (*get_flash_version) (struct scsi_qla_host *, void *); 3158 int (*start_scsi) (srb_t *); 3159 int (*start_scsi_mq) (srb_t *); 3160 int (*abort_isp) (struct scsi_qla_host *); 3161 int (*iospace_config)(struct qla_hw_data*); 3162 int (*initialize_adapter)(struct scsi_qla_host *); 3163 }; 3164 3165 /* MSI-X Support *************************************************************/ 3166 3167 #define QLA_MSIX_CHIP_REV_24XX 3 3168 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3169 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3170 3171 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3172 #define QLA_MSIX_RSP_Q 0x01 3173 #define QLA_ATIO_VECTOR 0x02 3174 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3175 3176 #define QLA_MIDX_DEFAULT 0 3177 #define QLA_MIDX_RSP_Q 1 3178 #define QLA_PCI_MSIX_CONTROL 0xa2 3179 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3180 3181 struct scsi_qla_host; 3182 3183 3184 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3185 3186 struct qla_msix_entry { 3187 int have_irq; 3188 int in_use; 3189 uint32_t vector; 3190 uint16_t entry; 3191 char name[30]; 3192 void *handle; 3193 int cpuid; 3194 }; 3195 3196 #define WATCH_INTERVAL 1 /* number of seconds */ 3197 3198 /* Work events. */ 3199 enum qla_work_type { 3200 QLA_EVT_AEN, 3201 QLA_EVT_IDC_ACK, 3202 QLA_EVT_ASYNC_LOGIN, 3203 QLA_EVT_ASYNC_LOGOUT, 3204 QLA_EVT_ASYNC_LOGOUT_DONE, 3205 QLA_EVT_ASYNC_ADISC, 3206 QLA_EVT_ASYNC_ADISC_DONE, 3207 QLA_EVT_UEVENT, 3208 QLA_EVT_AENFX, 3209 QLA_EVT_GIDPN, 3210 QLA_EVT_GPNID, 3211 QLA_EVT_UNMAP, 3212 QLA_EVT_NEW_SESS, 3213 QLA_EVT_GPDB, 3214 QLA_EVT_PRLI, 3215 QLA_EVT_GPSC, 3216 QLA_EVT_UPD_FCPORT, 3217 QLA_EVT_GNL, 3218 QLA_EVT_NACK, 3219 QLA_EVT_RELOGIN, 3220 QLA_EVT_ASYNC_PRLO, 3221 QLA_EVT_ASYNC_PRLO_DONE, 3222 QLA_EVT_GPNFT, 3223 QLA_EVT_GPNFT_DONE, 3224 QLA_EVT_GNNFT_DONE, 3225 QLA_EVT_GNNID, 3226 QLA_EVT_GFPNID, 3227 QLA_EVT_SP_RETRY, 3228 QLA_EVT_IIDMA, 3229 }; 3230 3231 3232 struct qla_work_evt { 3233 struct list_head list; 3234 enum qla_work_type type; 3235 u32 flags; 3236 #define QLA_EVT_FLAG_FREE 0x1 3237 3238 union { 3239 struct { 3240 enum fc_host_event_code code; 3241 u32 data; 3242 } aen; 3243 struct { 3244 #define QLA_IDC_ACK_REGS 7 3245 uint16_t mb[QLA_IDC_ACK_REGS]; 3246 } idc_ack; 3247 struct { 3248 struct fc_port *fcport; 3249 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3250 u16 data[2]; 3251 } logio; 3252 struct { 3253 u32 code; 3254 #define QLA_UEVENT_CODE_FW_DUMP 0 3255 } uevent; 3256 struct { 3257 uint32_t evtcode; 3258 uint32_t mbx[8]; 3259 uint32_t count; 3260 } aenfx; 3261 struct { 3262 srb_t *sp; 3263 } iosb; 3264 struct { 3265 port_id_t id; 3266 } gpnid; 3267 struct { 3268 port_id_t id; 3269 u8 port_name[8]; 3270 u8 node_name[8]; 3271 void *pla; 3272 u8 fc4_type; 3273 } new_sess; 3274 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */ 3275 fc_port_t *fcport; 3276 u8 opt; 3277 } fcport; 3278 struct { 3279 fc_port_t *fcport; 3280 u8 iocb[IOCB_SIZE]; 3281 int type; 3282 } nack; 3283 struct { 3284 u8 fc4_type; 3285 srb_t *sp; 3286 } gpnft; 3287 } u; 3288 }; 3289 3290 struct qla_chip_state_84xx { 3291 struct list_head list; 3292 struct kref kref; 3293 3294 void *bus; 3295 spinlock_t access_lock; 3296 struct mutex fw_update_mutex; 3297 uint32_t fw_update; 3298 uint32_t op_fw_version; 3299 uint32_t op_fw_size; 3300 uint32_t op_fw_seq_size; 3301 uint32_t diag_fw_version; 3302 uint32_t gold_fw_version; 3303 }; 3304 3305 struct qla_dif_statistics { 3306 uint64_t dif_input_bytes; 3307 uint64_t dif_output_bytes; 3308 uint64_t dif_input_requests; 3309 uint64_t dif_output_requests; 3310 uint32_t dif_guard_err; 3311 uint32_t dif_ref_tag_err; 3312 uint32_t dif_app_tag_err; 3313 }; 3314 3315 struct qla_statistics { 3316 uint32_t total_isp_aborts; 3317 uint64_t input_bytes; 3318 uint64_t output_bytes; 3319 uint64_t input_requests; 3320 uint64_t output_requests; 3321 uint32_t control_requests; 3322 3323 uint64_t jiffies_at_last_reset; 3324 uint32_t stat_max_pend_cmds; 3325 uint32_t stat_max_qfull_cmds_alloc; 3326 uint32_t stat_max_qfull_cmds_dropped; 3327 3328 struct qla_dif_statistics qla_dif_stats; 3329 }; 3330 3331 struct bidi_statistics { 3332 unsigned long long io_count; 3333 unsigned long long transfer_bytes; 3334 }; 3335 3336 struct qla_tc_param { 3337 struct scsi_qla_host *vha; 3338 uint32_t blk_sz; 3339 uint32_t bufflen; 3340 struct scatterlist *sg; 3341 struct scatterlist *prot_sg; 3342 struct crc_context *ctx; 3343 uint8_t *ctx_dsd_alloced; 3344 }; 3345 3346 /* Multi queue support */ 3347 #define MBC_INITIALIZE_MULTIQ 0x1f 3348 #define QLA_QUE_PAGE 0X1000 3349 #define QLA_MQ_SIZE 32 3350 #define QLA_MAX_QUEUES 256 3351 #define ISP_QUE_REG(ha, id) \ 3352 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \ 3353 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3354 ((void __iomem *)ha->iobase)) 3355 #define QLA_REQ_QUE_ID(tag) \ 3356 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3357 #define QLA_DEFAULT_QUE_QOS 5 3358 #define QLA_PRECONFIG_VPORTS 32 3359 #define QLA_MAX_VPORTS_QLA24XX 128 3360 #define QLA_MAX_VPORTS_QLA25XX 256 3361 3362 struct qla_tgt_counters { 3363 uint64_t qla_core_sbt_cmd; 3364 uint64_t core_qla_que_buf; 3365 uint64_t qla_core_ret_ctio; 3366 uint64_t core_qla_snd_status; 3367 uint64_t qla_core_ret_sta_ctio; 3368 uint64_t core_qla_free_cmd; 3369 uint64_t num_q_full_sent; 3370 uint64_t num_alloc_iocb_failed; 3371 uint64_t num_term_xchg_sent; 3372 }; 3373 3374 struct qla_qpair; 3375 3376 /* Response queue data structure */ 3377 struct rsp_que { 3378 dma_addr_t dma; 3379 response_t *ring; 3380 response_t *ring_ptr; 3381 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 3382 uint32_t __iomem *rsp_q_out; 3383 uint16_t ring_index; 3384 uint16_t out_ptr; 3385 uint16_t *in_ptr; /* queue shadow in index */ 3386 uint16_t length; 3387 uint16_t options; 3388 uint16_t rid; 3389 uint16_t id; 3390 uint16_t vp_idx; 3391 struct qla_hw_data *hw; 3392 struct qla_msix_entry *msix; 3393 struct req_que *req; 3394 srb_t *status_srb; /* status continuation entry */ 3395 struct qla_qpair *qpair; 3396 3397 dma_addr_t dma_fx00; 3398 response_t *ring_fx00; 3399 uint16_t length_fx00; 3400 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3401 }; 3402 3403 /* Request queue data structure */ 3404 struct req_que { 3405 dma_addr_t dma; 3406 request_t *ring; 3407 request_t *ring_ptr; 3408 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 3409 uint32_t __iomem *req_q_out; 3410 uint16_t ring_index; 3411 uint16_t in_ptr; 3412 uint16_t *out_ptr; /* queue shadow out index */ 3413 uint16_t cnt; 3414 uint16_t length; 3415 uint16_t options; 3416 uint16_t rid; 3417 uint16_t id; 3418 uint16_t qos; 3419 uint16_t vp_idx; 3420 struct rsp_que *rsp; 3421 srb_t **outstanding_cmds; 3422 uint32_t current_outstanding_cmd; 3423 uint16_t num_outstanding_cmds; 3424 int max_q_depth; 3425 3426 dma_addr_t dma_fx00; 3427 request_t *ring_fx00; 3428 uint16_t length_fx00; 3429 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3430 }; 3431 3432 /*Queue pair data structure */ 3433 struct qla_qpair { 3434 spinlock_t qp_lock; 3435 atomic_t ref_count; 3436 uint32_t lun_cnt; 3437 /* 3438 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3439 * legacy code. For other Qpair(s), it will point at qp_lock. 3440 */ 3441 spinlock_t *qp_lock_ptr; 3442 struct scsi_qla_host *vha; 3443 u32 chip_reset; 3444 3445 /* distill these fields down to 'online=0/1' 3446 * ha->flags.eeh_busy 3447 * ha->flags.pci_channel_io_perm_failure 3448 * base_vha->loop_state 3449 */ 3450 uint32_t online:1; 3451 /* move vha->flags.difdix_supported here */ 3452 uint32_t difdix_supported:1; 3453 uint32_t delete_in_progress:1; 3454 uint32_t fw_started:1; 3455 uint32_t enable_class_2:1; 3456 uint32_t enable_explicit_conf:1; 3457 uint32_t use_shadow_reg:1; 3458 3459 uint16_t id; /* qp number used with FW */ 3460 uint16_t vp_idx; /* vport ID */ 3461 mempool_t *srb_mempool; 3462 3463 struct pci_dev *pdev; 3464 void (*reqq_start_iocbs)(struct qla_qpair *); 3465 3466 /* to do: New driver: move queues to here instead of pointers */ 3467 struct req_que *req; 3468 struct rsp_que *rsp; 3469 struct atio_que *atio; 3470 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3471 struct qla_hw_data *hw; 3472 struct work_struct q_work; 3473 struct list_head qp_list_elem; /* vha->qp_list */ 3474 struct list_head hints_list; 3475 uint16_t cpuid; 3476 struct qla_tgt_counters tgt_counters; 3477 }; 3478 3479 /* Place holder for FW buffer parameters */ 3480 struct qlfc_fw { 3481 void *fw_buf; 3482 dma_addr_t fw_dma; 3483 uint32_t len; 3484 }; 3485 3486 struct scsi_qlt_host { 3487 void *target_lport_ptr; 3488 struct mutex tgt_mutex; 3489 struct mutex tgt_host_action_mutex; 3490 struct qla_tgt *qla_tgt; 3491 }; 3492 3493 struct qlt_hw_data { 3494 /* Protected by hw lock */ 3495 uint32_t node_name_set:1; 3496 3497 dma_addr_t atio_dma; /* Physical address. */ 3498 struct atio *atio_ring; /* Base virtual address */ 3499 struct atio *atio_ring_ptr; /* Current address. */ 3500 uint16_t atio_ring_index; /* Current index. */ 3501 uint16_t atio_q_length; 3502 uint32_t __iomem *atio_q_in; 3503 uint32_t __iomem *atio_q_out; 3504 3505 struct qla_tgt_func_tmpl *tgt_ops; 3506 struct qla_tgt_vp_map *tgt_vp_map; 3507 3508 int saved_set; 3509 uint16_t saved_exchange_count; 3510 uint32_t saved_firmware_options_1; 3511 uint32_t saved_firmware_options_2; 3512 uint32_t saved_firmware_options_3; 3513 uint8_t saved_firmware_options[2]; 3514 uint8_t saved_add_firmware_options[2]; 3515 3516 uint8_t tgt_node_name[WWN_SIZE]; 3517 3518 struct dentry *dfs_tgt_sess; 3519 struct dentry *dfs_tgt_port_database; 3520 struct dentry *dfs_naqp; 3521 3522 struct list_head q_full_list; 3523 uint32_t num_pend_cmds; 3524 uint32_t num_qfull_cmds_alloc; 3525 uint32_t num_qfull_cmds_dropped; 3526 spinlock_t q_full_lock; 3527 uint32_t leak_exchg_thresh_hold; 3528 spinlock_t sess_lock; 3529 int num_act_qpairs; 3530 #define DEFAULT_NAQP 2 3531 spinlock_t atio_lock ____cacheline_aligned; 3532 struct btree_head32 host_map; 3533 }; 3534 3535 #define MAX_QFULL_CMDS_ALLOC 8192 3536 #define Q_FULL_THRESH_HOLD_PERCENT 90 3537 #define Q_FULL_THRESH_HOLD(ha) \ 3538 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3539 3540 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3541 3542 /* 3543 * Qlogic host adapter specific data structure. 3544 */ 3545 struct qla_hw_data { 3546 struct pci_dev *pdev; 3547 /* SRB cache. */ 3548 #define SRB_MIN_REQ 128 3549 mempool_t *srb_mempool; 3550 3551 volatile struct { 3552 uint32_t mbox_int :1; 3553 uint32_t mbox_busy :1; 3554 uint32_t disable_risc_code_load :1; 3555 uint32_t enable_64bit_addressing :1; 3556 uint32_t enable_lip_reset :1; 3557 uint32_t enable_target_reset :1; 3558 uint32_t enable_lip_full_login :1; 3559 uint32_t enable_led_scheme :1; 3560 3561 uint32_t msi_enabled :1; 3562 uint32_t msix_enabled :1; 3563 uint32_t disable_serdes :1; 3564 uint32_t gpsc_supported :1; 3565 uint32_t npiv_supported :1; 3566 uint32_t pci_channel_io_perm_failure :1; 3567 uint32_t fce_enabled :1; 3568 uint32_t fac_supported :1; 3569 3570 uint32_t chip_reset_done :1; 3571 uint32_t running_gold_fw :1; 3572 uint32_t eeh_busy :1; 3573 uint32_t disable_msix_handshake :1; 3574 uint32_t fcp_prio_enabled :1; 3575 uint32_t isp82xx_fw_hung:1; 3576 uint32_t nic_core_hung:1; 3577 3578 uint32_t quiesce_owner:1; 3579 uint32_t nic_core_reset_hdlr_active:1; 3580 uint32_t nic_core_reset_owner:1; 3581 uint32_t isp82xx_no_md_cap:1; 3582 uint32_t host_shutting_down:1; 3583 uint32_t idc_compl_status:1; 3584 uint32_t mr_reset_hdlr_active:1; 3585 uint32_t mr_intr_valid:1; 3586 3587 uint32_t dport_enabled:1; 3588 uint32_t fawwpn_enabled:1; 3589 uint32_t exlogins_enabled:1; 3590 uint32_t exchoffld_enabled:1; 3591 3592 uint32_t lip_ae:1; 3593 uint32_t n2n_ae:1; 3594 uint32_t fw_started:1; 3595 uint32_t fw_init_done:1; 3596 3597 uint32_t detected_lr_sfp:1; 3598 uint32_t using_lr_setting:1; 3599 uint32_t rida_fmt2:1; 3600 } flags; 3601 3602 uint16_t max_exchg; 3603 uint16_t long_range_distance; /* 32G & above */ 3604 #define LR_DISTANCE_5K 1 3605 #define LR_DISTANCE_10K 0 3606 3607 /* This spinlock is used to protect "io transactions", you must 3608 * acquire it before doing any IO to the card, eg with RD_REG*() and 3609 * WRT_REG*() for the duration of your entire commandtransaction. 3610 * 3611 * This spinlock is of lower priority than the io request lock. 3612 */ 3613 3614 spinlock_t hardware_lock ____cacheline_aligned; 3615 int bars; 3616 int mem_only; 3617 device_reg_t *iobase; /* Base I/O address */ 3618 resource_size_t pio_address; 3619 3620 #define MIN_IOBASE_LEN 0x100 3621 dma_addr_t bar0_hdl; 3622 3623 void __iomem *cregbase; 3624 dma_addr_t bar2_hdl; 3625 #define BAR0_LEN_FX00 (1024 * 1024) 3626 #define BAR2_LEN_FX00 (128 * 1024) 3627 3628 uint32_t rqstq_intr_code; 3629 uint32_t mbx_intr_code; 3630 uint32_t req_que_len; 3631 uint32_t rsp_que_len; 3632 uint32_t req_que_off; 3633 uint32_t rsp_que_off; 3634 3635 /* Multi queue data structs */ 3636 device_reg_t *mqiobase; 3637 device_reg_t *msixbase; 3638 uint16_t msix_count; 3639 uint8_t mqenable; 3640 struct req_que **req_q_map; 3641 struct rsp_que **rsp_q_map; 3642 struct qla_qpair **queue_pair_map; 3643 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3644 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3645 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 3646 / sizeof(unsigned long)]; 3647 uint8_t max_req_queues; 3648 uint8_t max_rsp_queues; 3649 uint8_t max_qpairs; 3650 uint8_t num_qpairs; 3651 struct qla_qpair *base_qpair; 3652 struct qla_npiv_entry *npiv_info; 3653 uint16_t nvram_npiv_size; 3654 3655 uint16_t switch_cap; 3656 #define FLOGI_SEQ_DEL BIT_8 3657 #define FLOGI_MID_SUPPORT BIT_10 3658 #define FLOGI_VSAN_SUPPORT BIT_12 3659 #define FLOGI_SP_SUPPORT BIT_13 3660 3661 uint8_t port_no; /* Physical port of adapter */ 3662 uint8_t exch_starvation; 3663 3664 /* Timeout timers. */ 3665 uint8_t loop_down_abort_time; /* port down timer */ 3666 atomic_t loop_down_timer; /* loop down timer */ 3667 uint8_t link_down_timeout; /* link down timeout */ 3668 uint16_t max_loop_id; 3669 uint16_t max_fibre_devices; /* Maximum number of targets */ 3670 3671 uint16_t fb_rev; 3672 uint16_t min_external_loopid; /* First external loop Id */ 3673 3674 #define PORT_SPEED_UNKNOWN 0xFFFF 3675 #define PORT_SPEED_1GB 0x00 3676 #define PORT_SPEED_2GB 0x01 3677 #define PORT_SPEED_4GB 0x03 3678 #define PORT_SPEED_8GB 0x04 3679 #define PORT_SPEED_16GB 0x05 3680 #define PORT_SPEED_32GB 0x06 3681 #define PORT_SPEED_10GB 0x13 3682 uint16_t link_data_rate; /* F/W operating speed */ 3683 3684 uint8_t current_topology; 3685 uint8_t prev_topology; 3686 #define ISP_CFG_NL 1 3687 #define ISP_CFG_N 2 3688 #define ISP_CFG_FL 4 3689 #define ISP_CFG_F 8 3690 3691 uint8_t operating_mode; /* F/W operating mode */ 3692 #define LOOP 0 3693 #define P2P 1 3694 #define LOOP_P2P 2 3695 #define P2P_LOOP 3 3696 uint8_t interrupts_on; 3697 uint32_t isp_abort_cnt; 3698 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 3699 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 3700 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 3701 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 3702 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 3703 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 3704 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 3705 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 3706 3707 uint32_t isp_type; 3708 #define DT_ISP2100 BIT_0 3709 #define DT_ISP2200 BIT_1 3710 #define DT_ISP2300 BIT_2 3711 #define DT_ISP2312 BIT_3 3712 #define DT_ISP2322 BIT_4 3713 #define DT_ISP6312 BIT_5 3714 #define DT_ISP6322 BIT_6 3715 #define DT_ISP2422 BIT_7 3716 #define DT_ISP2432 BIT_8 3717 #define DT_ISP5422 BIT_9 3718 #define DT_ISP5432 BIT_10 3719 #define DT_ISP2532 BIT_11 3720 #define DT_ISP8432 BIT_12 3721 #define DT_ISP8001 BIT_13 3722 #define DT_ISP8021 BIT_14 3723 #define DT_ISP2031 BIT_15 3724 #define DT_ISP8031 BIT_16 3725 #define DT_ISPFX00 BIT_17 3726 #define DT_ISP8044 BIT_18 3727 #define DT_ISP2071 BIT_19 3728 #define DT_ISP2271 BIT_20 3729 #define DT_ISP2261 BIT_21 3730 #define DT_ISP_LAST (DT_ISP2261 << 1) 3731 3732 uint32_t device_type; 3733 #define DT_T10_PI BIT_25 3734 #define DT_IIDMA BIT_26 3735 #define DT_FWI2 BIT_27 3736 #define DT_ZIO_SUPPORTED BIT_28 3737 #define DT_OEM_001 BIT_29 3738 #define DT_ISP2200A BIT_30 3739 #define DT_EXTENDED_IDS BIT_31 3740 3741 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 3742 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 3743 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 3744 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 3745 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 3746 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 3747 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 3748 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 3749 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 3750 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 3751 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 3752 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 3753 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 3754 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 3755 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 3756 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 3757 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 3758 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 3759 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 3760 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 3761 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 3762 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 3763 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 3764 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 3765 3766 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 3767 IS_QLA6312(ha) || IS_QLA6322(ha)) 3768 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 3769 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 3770 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 3771 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 3772 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 3773 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 3774 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 3775 IS_QLA84XX(ha)) 3776 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 3777 IS_QLA8031(ha) || IS_QLA8044(ha)) 3778 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 3779 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 3780 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 3781 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 3782 IS_QLA8044(ha) || IS_QLA27XX(ha)) 3783 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3784 IS_QLA27XX(ha)) 3785 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 3786 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3787 IS_QLA27XX(ha)) 3788 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3789 IS_QLA27XX(ha)) 3790 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 3791 3792 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 3793 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 3794 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 3795 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 3796 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 3797 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 3798 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 3799 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 3800 IS_QLA27XX(ha)) 3801 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) 3802 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 3803 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3804 ((ha)->fw_attributes_ext[0] & BIT_0)) 3805 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3806 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3807 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3808 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3809 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3810 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3811 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3812 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3813 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha)) 3814 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3815 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3816 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 3817 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3818 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 3819 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3820 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ 3821 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3822 3823 /* HBA serial number */ 3824 uint8_t serial0; 3825 uint8_t serial1; 3826 uint8_t serial2; 3827 3828 /* NVRAM configuration data */ 3829 #define MAX_NVRAM_SIZE 4096 3830 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 3831 uint16_t nvram_size; 3832 uint16_t nvram_base; 3833 void *nvram; 3834 uint16_t vpd_size; 3835 uint16_t vpd_base; 3836 void *vpd; 3837 3838 uint16_t loop_reset_delay; 3839 uint8_t retry_count; 3840 uint8_t login_timeout; 3841 uint16_t r_a_tov; 3842 int port_down_retry_count; 3843 uint8_t mbx_count; 3844 uint8_t aen_mbx_count; 3845 3846 uint32_t login_retry_count; 3847 /* SNS command interfaces. */ 3848 ms_iocb_entry_t *ms_iocb; 3849 dma_addr_t ms_iocb_dma; 3850 struct ct_sns_pkt *ct_sns; 3851 dma_addr_t ct_sns_dma; 3852 /* SNS command interfaces for 2200. */ 3853 struct sns_cmd_pkt *sns_cmd; 3854 dma_addr_t sns_cmd_dma; 3855 3856 #define SFP_DEV_SIZE 512 3857 #define SFP_BLOCK_SIZE 64 3858 void *sfp_data; 3859 dma_addr_t sfp_data_dma; 3860 3861 #define XGMAC_DATA_SIZE 4096 3862 void *xgmac_data; 3863 dma_addr_t xgmac_data_dma; 3864 3865 #define DCBX_TLV_DATA_SIZE 4096 3866 void *dcbx_tlv; 3867 dma_addr_t dcbx_tlv_dma; 3868 3869 struct task_struct *dpc_thread; 3870 uint8_t dpc_active; /* DPC routine is active */ 3871 3872 dma_addr_t gid_list_dma; 3873 struct gid_list_info *gid_list; 3874 int gid_list_info_size; 3875 3876 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3877 #define DMA_POOL_SIZE 256 3878 struct dma_pool *s_dma_pool; 3879 3880 dma_addr_t init_cb_dma; 3881 init_cb_t *init_cb; 3882 int init_cb_size; 3883 dma_addr_t ex_init_cb_dma; 3884 struct ex_init_cb_81xx *ex_init_cb; 3885 3886 void *async_pd; 3887 dma_addr_t async_pd_dma; 3888 3889 #define ENABLE_EXTENDED_LOGIN BIT_7 3890 3891 /* Extended Logins */ 3892 void *exlogin_buf; 3893 dma_addr_t exlogin_buf_dma; 3894 int exlogin_size; 3895 3896 #define ENABLE_EXCHANGE_OFFLD BIT_2 3897 3898 /* Exchange Offload */ 3899 void *exchoffld_buf; 3900 dma_addr_t exchoffld_buf_dma; 3901 int exchoffld_size; 3902 int exchoffld_count; 3903 3904 void *swl; 3905 3906 /* These are used by mailbox operations. */ 3907 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3908 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 3909 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 3910 3911 mbx_cmd_t *mcp; 3912 struct mbx_cmd_32 *mcp32; 3913 3914 unsigned long mbx_cmd_flags; 3915 #define MBX_INTERRUPT 1 3916 #define MBX_INTR_WAIT 2 3917 #define MBX_UPDATE_FLASH_ACTIVE 3 3918 3919 struct mutex vport_lock; /* Virtual port synchronization */ 3920 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 3921 struct mutex mq_lock; /* multi-queue synchronization */ 3922 struct completion mbx_cmd_comp; /* Serialize mbx access */ 3923 struct completion mbx_intr_comp; /* Used for completion notification */ 3924 struct completion dcbx_comp; /* For set port config notification */ 3925 struct completion lb_portup_comp; /* Used to wait for link up during 3926 * loopback */ 3927 #define DCBX_COMP_TIMEOUT 20 3928 #define LB_PORTUP_COMP_TIMEOUT 10 3929 3930 int notify_dcbx_comp; 3931 int notify_lb_portup_comp; 3932 struct mutex selflogin_lock; 3933 3934 /* Basic firmware related information. */ 3935 uint16_t fw_major_version; 3936 uint16_t fw_minor_version; 3937 uint16_t fw_subminor_version; 3938 uint16_t fw_attributes; 3939 uint16_t fw_attributes_h; 3940 uint16_t fw_attributes_ext[2]; 3941 uint32_t fw_memory_size; 3942 uint32_t fw_transfer_size; 3943 uint32_t fw_srisc_address; 3944 #define RISC_START_ADDRESS_2100 0x1000 3945 #define RISC_START_ADDRESS_2300 0x800 3946 #define RISC_START_ADDRESS_2400 0x100000 3947 3948 uint16_t orig_fw_tgt_xcb_count; 3949 uint16_t cur_fw_tgt_xcb_count; 3950 uint16_t orig_fw_xcb_count; 3951 uint16_t cur_fw_xcb_count; 3952 uint16_t orig_fw_iocb_count; 3953 uint16_t cur_fw_iocb_count; 3954 uint16_t fw_max_fcf_count; 3955 3956 uint32_t fw_shared_ram_start; 3957 uint32_t fw_shared_ram_end; 3958 uint32_t fw_ddr_ram_start; 3959 uint32_t fw_ddr_ram_end; 3960 3961 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 3962 uint8_t fw_seriallink_options[4]; 3963 uint16_t fw_seriallink_options24[4]; 3964 3965 uint8_t mpi_version[3]; 3966 uint32_t mpi_capabilities; 3967 uint8_t phy_version[3]; 3968 uint8_t pep_version[3]; 3969 3970 /* Firmware dump template */ 3971 void *fw_dump_template; 3972 uint32_t fw_dump_template_len; 3973 /* Firmware dump information. */ 3974 struct qla2xxx_fw_dump *fw_dump; 3975 uint32_t fw_dump_len; 3976 int fw_dumped; 3977 unsigned long fw_dump_cap_flags; 3978 #define RISC_PAUSE_CMPL 0 3979 #define DMA_SHUTDOWN_CMPL 1 3980 #define ISP_RESET_CMPL 2 3981 #define RISC_RDY_AFT_RESET 3 3982 #define RISC_SRAM_DUMP_CMPL 4 3983 #define RISC_EXT_MEM_DUMP_CMPL 5 3984 #define ISP_MBX_RDY 6 3985 #define ISP_SOFT_RESET_CMPL 7 3986 int fw_dump_reading; 3987 int prev_minidump_failed; 3988 dma_addr_t eft_dma; 3989 void *eft; 3990 /* Current size of mctp dump is 0x086064 bytes */ 3991 #define MCTP_DUMP_SIZE 0x086064 3992 dma_addr_t mctp_dump_dma; 3993 void *mctp_dump; 3994 int mctp_dumped; 3995 int mctp_dump_reading; 3996 uint32_t chain_offset; 3997 struct dentry *dfs_dir; 3998 struct dentry *dfs_fce; 3999 struct dentry *dfs_tgt_counters; 4000 struct dentry *dfs_fw_resource_cnt; 4001 4002 dma_addr_t fce_dma; 4003 void *fce; 4004 uint32_t fce_bufs; 4005 uint16_t fce_mb[8]; 4006 uint64_t fce_wr, fce_rd; 4007 struct mutex fce_mutex; 4008 4009 uint32_t pci_attr; 4010 uint16_t chip_revision; 4011 4012 uint16_t product_id[4]; 4013 4014 uint8_t model_number[16+1]; 4015 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 4016 char model_desc[80]; 4017 uint8_t adapter_id[16+1]; 4018 4019 /* Option ROM information. */ 4020 char *optrom_buffer; 4021 uint32_t optrom_size; 4022 int optrom_state; 4023 #define QLA_SWAITING 0 4024 #define QLA_SREADING 1 4025 #define QLA_SWRITING 2 4026 uint32_t optrom_region_start; 4027 uint32_t optrom_region_size; 4028 struct mutex optrom_mutex; 4029 4030 /* PCI expansion ROM image information. */ 4031 #define ROM_CODE_TYPE_BIOS 0 4032 #define ROM_CODE_TYPE_FCODE 1 4033 #define ROM_CODE_TYPE_EFI 3 4034 uint8_t bios_revision[2]; 4035 uint8_t efi_revision[2]; 4036 uint8_t fcode_revision[16]; 4037 uint32_t fw_revision[4]; 4038 4039 uint32_t gold_fw_version[4]; 4040 4041 /* Offsets for flash/nvram access (set to ~0 if not used). */ 4042 uint32_t flash_conf_off; 4043 uint32_t flash_data_off; 4044 uint32_t nvram_conf_off; 4045 uint32_t nvram_data_off; 4046 4047 uint32_t fdt_wrt_disable; 4048 uint32_t fdt_wrt_enable; 4049 uint32_t fdt_erase_cmd; 4050 uint32_t fdt_block_size; 4051 uint32_t fdt_unprotect_sec_cmd; 4052 uint32_t fdt_protect_sec_cmd; 4053 uint32_t fdt_wrt_sts_reg_cmd; 4054 4055 uint32_t flt_region_flt; 4056 uint32_t flt_region_fdt; 4057 uint32_t flt_region_boot; 4058 uint32_t flt_region_boot_sec; 4059 uint32_t flt_region_fw; 4060 uint32_t flt_region_fw_sec; 4061 uint32_t flt_region_vpd_nvram; 4062 uint32_t flt_region_vpd; 4063 uint32_t flt_region_vpd_sec; 4064 uint32_t flt_region_nvram; 4065 uint32_t flt_region_npiv_conf; 4066 uint32_t flt_region_gold_fw; 4067 uint32_t flt_region_fcp_prio; 4068 uint32_t flt_region_bootload; 4069 uint32_t flt_region_img_status_pri; 4070 uint32_t flt_region_img_status_sec; 4071 uint8_t active_image; 4072 4073 /* Needed for BEACON */ 4074 uint16_t beacon_blink_led; 4075 uint8_t beacon_color_state; 4076 #define QLA_LED_GRN_ON 0x01 4077 #define QLA_LED_YLW_ON 0x02 4078 #define QLA_LED_ABR_ON 0x04 4079 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 4080 /* ISP2322: red, green, amber. */ 4081 uint16_t zio_mode; 4082 uint16_t zio_timer; 4083 4084 struct qla_msix_entry *msix_entries; 4085 4086 struct list_head vp_list; /* list of VP */ 4087 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 4088 sizeof(unsigned long)]; 4089 uint16_t num_vhosts; /* number of vports created */ 4090 uint16_t num_vsans; /* number of vsan created */ 4091 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 4092 int cur_vport_count; 4093 4094 struct qla_chip_state_84xx *cs84xx; 4095 struct isp_operations *isp_ops; 4096 struct workqueue_struct *wq; 4097 struct qlfc_fw fw_buf; 4098 4099 /* FCP_CMND priority support */ 4100 struct qla_fcp_prio_cfg *fcp_prio_cfg; 4101 4102 struct dma_pool *dl_dma_pool; 4103 #define DSD_LIST_DMA_POOL_SIZE 512 4104 4105 struct dma_pool *fcp_cmnd_dma_pool; 4106 mempool_t *ctx_mempool; 4107 #define FCP_CMND_DMA_POOL_SIZE 512 4108 4109 void __iomem *nx_pcibase; /* Base I/O address */ 4110 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4111 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4112 4113 uint32_t crb_win; 4114 uint32_t curr_window; 4115 uint32_t ddr_mn_window; 4116 unsigned long mn_win_crb; 4117 unsigned long ms_win_crb; 4118 int qdr_sn_window; 4119 uint32_t fcoe_dev_init_timeout; 4120 uint32_t fcoe_reset_timeout; 4121 rwlock_t hw_lock; 4122 uint16_t portnum; /* port number */ 4123 int link_width; 4124 struct fw_blob *hablob; 4125 struct qla82xx_legacy_intr_set nx_legacy_intr; 4126 4127 uint16_t gbl_dsd_inuse; 4128 uint16_t gbl_dsd_avail; 4129 struct list_head gbl_dsd_list; 4130 #define NUM_DSD_CHAIN 4096 4131 4132 uint8_t fw_type; 4133 __le32 file_prd_off; /* File firmware product offset */ 4134 4135 uint32_t md_template_size; 4136 void *md_tmplt_hdr; 4137 dma_addr_t md_tmplt_hdr_dma; 4138 void *md_dump; 4139 uint32_t md_dump_size; 4140 4141 void *loop_id_map; 4142 4143 /* QLA83XX IDC specific fields */ 4144 uint32_t idc_audit_ts; 4145 uint32_t idc_extend_tmo; 4146 4147 /* DPC low-priority workqueue */ 4148 struct workqueue_struct *dpc_lp_wq; 4149 struct work_struct idc_aen; 4150 /* DPC high-priority workqueue */ 4151 struct workqueue_struct *dpc_hp_wq; 4152 struct work_struct nic_core_reset; 4153 struct work_struct idc_state_handler; 4154 struct work_struct nic_core_unrecoverable; 4155 struct work_struct board_disable; 4156 4157 struct mr_data_fx00 mr; 4158 4159 struct qlt_hw_data tgt; 4160 int allow_cna_fw_dump; 4161 uint32_t fw_ability_mask; 4162 uint16_t min_link_speed; 4163 uint16_t max_speed_sup; 4164 4165 atomic_t nvme_active_aen_cnt; 4166 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4167 }; 4168 4169 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4170 #define FW_ABILITY_MAX_SPEED_16G 0x0 4171 #define FW_ABILITY_MAX_SPEED_32G 0x1 4172 #define FW_ABILITY_MAX_SPEED(ha) \ 4173 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4174 4175 /* 4176 * Qlogic scsi host structure 4177 */ 4178 typedef struct scsi_qla_host { 4179 struct list_head list; 4180 struct list_head vp_fcports; /* list of fcports */ 4181 struct list_head work_list; 4182 spinlock_t work_lock; 4183 struct work_struct iocb_work; 4184 4185 /* Commonly used flags and state information. */ 4186 struct Scsi_Host *host; 4187 unsigned long host_no; 4188 uint8_t host_str[16]; 4189 4190 volatile struct { 4191 uint32_t init_done :1; 4192 uint32_t online :1; 4193 uint32_t reset_active :1; 4194 4195 uint32_t management_server_logged_in :1; 4196 uint32_t process_response_queue :1; 4197 uint32_t difdix_supported:1; 4198 uint32_t delete_progress:1; 4199 4200 uint32_t fw_tgt_reported:1; 4201 uint32_t bbcr_enable:1; 4202 uint32_t qpairs_available:1; 4203 uint32_t qpairs_req_created:1; 4204 uint32_t qpairs_rsp_created:1; 4205 uint32_t nvme_enabled:1; 4206 } flags; 4207 4208 atomic_t loop_state; 4209 #define LOOP_TIMEOUT 1 4210 #define LOOP_DOWN 2 4211 #define LOOP_UP 3 4212 #define LOOP_UPDATE 4 4213 #define LOOP_READY 5 4214 #define LOOP_DEAD 6 4215 4216 unsigned long relogin_jif; 4217 unsigned long dpc_flags; 4218 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4219 #define RESET_ACTIVE 1 4220 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4221 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4222 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4223 #define LOOP_RESYNC_ACTIVE 5 4224 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4225 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4226 #define RELOGIN_NEEDED 8 4227 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4228 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4229 #define BEACON_BLINK_NEEDED 11 4230 #define REGISTER_FDMI_NEEDED 12 4231 #define FCPORT_UPDATE_NEEDED 13 4232 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4233 #define UNLOADING 15 4234 #define NPIV_CONFIG_NEEDED 16 4235 #define ISP_UNRECOVERABLE 17 4236 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4237 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4238 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4239 #define FREE_BIT 21 4240 #define PORT_UPDATE_NEEDED 22 4241 #define FX00_RESET_RECOVERY 23 4242 #define FX00_TARGET_SCAN 24 4243 #define FX00_CRITEMP_RECOVERY 25 4244 #define FX00_HOST_INFO_RESEND 26 4245 #define QPAIR_ONLINE_CHECK_NEEDED 27 4246 #define SET_ZIO_THRESHOLD_NEEDED 28 4247 #define DETECT_SFP_CHANGE 29 4248 #define N2N_LOGIN_NEEDED 30 4249 #define IOCB_WORK_ACTIVE 31 4250 4251 unsigned long pci_flags; 4252 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4253 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4254 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4255 4256 uint32_t device_flags; 4257 #define SWITCH_FOUND BIT_0 4258 #define DFLG_NO_CABLE BIT_1 4259 #define DFLG_DEV_FAILED BIT_5 4260 4261 /* ISP configuration data. */ 4262 uint16_t loop_id; /* Host adapter loop id */ 4263 uint16_t self_login_loop_id; /* host adapter loop id 4264 * get it on self login 4265 */ 4266 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4267 * no need of allocating it for 4268 * each command 4269 */ 4270 4271 port_id_t d_id; /* Host adapter port id */ 4272 uint8_t marker_needed; 4273 uint16_t mgmt_svr_loop_id; 4274 4275 4276 4277 /* Timeout timers. */ 4278 uint8_t loop_down_abort_time; /* port down timer */ 4279 atomic_t loop_down_timer; /* loop down timer */ 4280 uint8_t link_down_timeout; /* link down timeout */ 4281 4282 uint32_t timer_active; 4283 struct timer_list timer; 4284 4285 uint8_t node_name[WWN_SIZE]; 4286 uint8_t port_name[WWN_SIZE]; 4287 uint8_t fabric_node_name[WWN_SIZE]; 4288 4289 struct nvme_fc_local_port *nvme_local_port; 4290 struct completion nvme_del_done; 4291 struct list_head nvme_rport_list; 4292 4293 uint16_t fcoe_vlan_id; 4294 uint16_t fcoe_fcf_idx; 4295 uint8_t fcoe_vn_port_mac[6]; 4296 4297 /* list of commands waiting on workqueue */ 4298 struct list_head qla_cmd_list; 4299 struct list_head qla_sess_op_cmd_list; 4300 struct list_head unknown_atio_list; 4301 spinlock_t cmd_list_lock; 4302 struct delayed_work unknown_atio_work; 4303 4304 /* Counter to detect races between ELS and RSCN events */ 4305 atomic_t generation_tick; 4306 /* Time when global fcport update has been scheduled */ 4307 int total_fcport_update_gen; 4308 /* List of pending LOGOs, protected by tgt_mutex */ 4309 struct list_head logo_list; 4310 /* List of pending PLOGI acks, protected by hw lock */ 4311 struct list_head plogi_ack_list; 4312 4313 struct list_head qp_list; 4314 4315 uint32_t vp_abort_cnt; 4316 4317 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4318 uint16_t vp_idx; /* vport ID */ 4319 struct qla_qpair *qpair; /* base qpair */ 4320 4321 unsigned long vp_flags; 4322 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4323 #define VP_CREATE_NEEDED 1 4324 #define VP_BIND_NEEDED 2 4325 #define VP_DELETE_NEEDED 3 4326 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4327 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4328 atomic_t vp_state; 4329 #define VP_OFFLINE 0 4330 #define VP_ACTIVE 1 4331 #define VP_FAILED 2 4332 // #define VP_DISABLE 3 4333 uint16_t vp_err_state; 4334 uint16_t vp_prev_err_state; 4335 #define VP_ERR_UNKWN 0 4336 #define VP_ERR_PORTDWN 1 4337 #define VP_ERR_FAB_UNSUPPORTED 2 4338 #define VP_ERR_FAB_NORESOURCES 3 4339 #define VP_ERR_FAB_LOGOUT 4 4340 #define VP_ERR_ADAP_NORESOURCES 5 4341 struct qla_hw_data *hw; 4342 struct scsi_qlt_host vha_tgt; 4343 struct req_que *req; 4344 int fw_heartbeat_counter; 4345 int seconds_since_last_heartbeat; 4346 struct fc_host_statistics fc_host_stat; 4347 struct qla_statistics qla_stats; 4348 struct bidi_statistics bidi_stats; 4349 atomic_t vref_count; 4350 struct qla8044_reset_template reset_tmplt; 4351 uint16_t bbcr; 4352 struct name_list_extended gnl; 4353 /* Count of active session/fcport */ 4354 int fcport_count; 4355 wait_queue_head_t fcport_waitQ; 4356 wait_queue_head_t vref_waitq; 4357 uint8_t min_link_speed_feat; 4358 uint8_t n2n_node_name[WWN_SIZE]; 4359 uint8_t n2n_port_name[WWN_SIZE]; 4360 uint16_t n2n_id; 4361 struct list_head gpnid_list; 4362 struct fab_scan scan; 4363 } scsi_qla_host_t; 4364 4365 struct qla27xx_image_status { 4366 uint8_t image_status_mask; 4367 uint16_t generation_number; 4368 uint8_t reserved[3]; 4369 uint8_t ver_minor; 4370 uint8_t ver_major; 4371 uint32_t checksum; 4372 uint32_t signature; 4373 } __packed; 4374 4375 #define SET_VP_IDX 1 4376 #define SET_AL_PA 2 4377 #define RESET_VP_IDX 3 4378 #define RESET_AL_PA 4 4379 struct qla_tgt_vp_map { 4380 uint8_t idx; 4381 scsi_qla_host_t *vha; 4382 }; 4383 4384 struct qla2_sgx { 4385 dma_addr_t dma_addr; /* OUT */ 4386 uint32_t dma_len; /* OUT */ 4387 4388 uint32_t tot_bytes; /* IN */ 4389 struct scatterlist *cur_sg; /* IN */ 4390 4391 /* for book keeping, bzero on initial invocation */ 4392 uint32_t bytes_consumed; 4393 uint32_t num_bytes; 4394 uint32_t tot_partial; 4395 4396 /* for debugging */ 4397 uint32_t num_sg; 4398 srb_t *sp; 4399 }; 4400 4401 #define QLA_FW_STARTED(_ha) { \ 4402 int i; \ 4403 _ha->flags.fw_started = 1; \ 4404 _ha->base_qpair->fw_started = 1; \ 4405 for (i = 0; i < _ha->max_qpairs; i++) { \ 4406 if (_ha->queue_pair_map[i]) \ 4407 _ha->queue_pair_map[i]->fw_started = 1; \ 4408 } \ 4409 } 4410 4411 #define QLA_FW_STOPPED(_ha) { \ 4412 int i; \ 4413 _ha->flags.fw_started = 0; \ 4414 _ha->base_qpair->fw_started = 0; \ 4415 for (i = 0; i < _ha->max_qpairs; i++) { \ 4416 if (_ha->queue_pair_map[i]) \ 4417 _ha->queue_pair_map[i]->fw_started = 0; \ 4418 } \ 4419 } 4420 4421 /* 4422 * Macros to help code, maintain, etc. 4423 */ 4424 #define LOOP_TRANSITION(ha) \ 4425 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4426 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 4427 atomic_read(&ha->loop_state) == LOOP_DOWN) 4428 4429 #define STATE_TRANSITION(ha) \ 4430 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4431 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 4432 4433 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 4434 atomic_inc(&__vha->vref_count); \ 4435 mb(); \ 4436 if (__vha->flags.delete_progress) { \ 4437 atomic_dec(&__vha->vref_count); \ 4438 wake_up(&__vha->vref_waitq); \ 4439 __bail = 1; \ 4440 } else { \ 4441 __bail = 0; \ 4442 } \ 4443 } while (0) 4444 4445 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 4446 atomic_dec(&__vha->vref_count); \ 4447 wake_up(&__vha->vref_waitq); \ 4448 } while (0) \ 4449 4450 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 4451 atomic_inc(&__qpair->ref_count); \ 4452 mb(); \ 4453 if (__qpair->delete_in_progress) { \ 4454 atomic_dec(&__qpair->ref_count); \ 4455 __bail = 1; \ 4456 } else { \ 4457 __bail = 0; \ 4458 } \ 4459 } while (0) 4460 4461 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 4462 atomic_dec(&__qpair->ref_count); \ 4463 4464 4465 #define QLA_ENA_CONF(_ha) {\ 4466 int i;\ 4467 _ha->base_qpair->enable_explicit_conf = 1; \ 4468 for (i = 0; i < _ha->max_qpairs; i++) { \ 4469 if (_ha->queue_pair_map[i]) \ 4470 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 4471 } \ 4472 } 4473 4474 #define QLA_DIS_CONF(_ha) {\ 4475 int i;\ 4476 _ha->base_qpair->enable_explicit_conf = 0; \ 4477 for (i = 0; i < _ha->max_qpairs; i++) { \ 4478 if (_ha->queue_pair_map[i]) \ 4479 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 4480 } \ 4481 } 4482 4483 /* 4484 * qla2x00 local function return status codes 4485 */ 4486 #define MBS_MASK 0x3fff 4487 4488 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 4489 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 4490 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 4491 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 4492 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 4493 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 4494 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 4495 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 4496 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 4497 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 4498 4499 #define QLA_FUNCTION_TIMEOUT 0x100 4500 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 4501 #define QLA_FUNCTION_FAILED 0x102 4502 #define QLA_MEMORY_ALLOC_FAILED 0x103 4503 #define QLA_LOCK_TIMEOUT 0x104 4504 #define QLA_ABORTED 0x105 4505 #define QLA_SUSPENDED 0x106 4506 #define QLA_BUSY 0x107 4507 #define QLA_ALREADY_REGISTERED 0x109 4508 4509 #define NVRAM_DELAY() udelay(10) 4510 4511 /* 4512 * Flash support definitions 4513 */ 4514 #define OPTROM_SIZE_2300 0x20000 4515 #define OPTROM_SIZE_2322 0x100000 4516 #define OPTROM_SIZE_24XX 0x100000 4517 #define OPTROM_SIZE_25XX 0x200000 4518 #define OPTROM_SIZE_81XX 0x400000 4519 #define OPTROM_SIZE_82XX 0x800000 4520 #define OPTROM_SIZE_83XX 0x1000000 4521 4522 #define OPTROM_BURST_SIZE 0x1000 4523 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 4524 4525 #define QLA_DSDS_PER_IOCB 37 4526 4527 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 4528 4529 #define QLA_SG_ALL 1024 4530 4531 enum nexus_wait_type { 4532 WAIT_HOST = 0, 4533 WAIT_TARGET, 4534 WAIT_LUN, 4535 }; 4536 4537 /* Refer to SNIA SFF 8247 */ 4538 struct sff_8247_a0 { 4539 u8 txid; /* transceiver id */ 4540 u8 ext_txid; 4541 u8 connector; 4542 /* compliance code */ 4543 u8 eth_infi_cc3; /* ethernet, inifiband */ 4544 u8 sonet_cc4[2]; 4545 u8 eth_cc6; 4546 /* link length */ 4547 #define FC_LL_VL BIT_7 /* very long */ 4548 #define FC_LL_S BIT_6 /* Short */ 4549 #define FC_LL_I BIT_5 /* Intermidiate*/ 4550 #define FC_LL_L BIT_4 /* Long */ 4551 #define FC_LL_M BIT_3 /* Medium */ 4552 #define FC_LL_SA BIT_2 /* ShortWave laser */ 4553 #define FC_LL_LC BIT_1 /* LongWave laser */ 4554 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 4555 u8 fc_ll_cc7; 4556 /* FC technology */ 4557 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 4558 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 4559 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 4560 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 4561 #define FC_TEC_ACT BIT_3 /* Active cable */ 4562 #define FC_TEC_PAS BIT_2 /* Passive cable */ 4563 u8 fc_tec_cc8; 4564 /* Transmission Media */ 4565 #define FC_MED_TW BIT_7 /* Twin Ax */ 4566 #define FC_MED_TP BIT_6 /* Twited Pair */ 4567 #define FC_MED_MI BIT_5 /* Min Coax */ 4568 #define FC_MED_TV BIT_4 /* Video Coax */ 4569 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 4570 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 4571 #define FC_MED_SM BIT_0 /* Single Mode */ 4572 u8 fc_med_cc9; 4573 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 4574 #define FC_SP_12 BIT_7 4575 #define FC_SP_8 BIT_6 4576 #define FC_SP_16 BIT_5 4577 #define FC_SP_4 BIT_4 4578 #define FC_SP_32 BIT_3 4579 #define FC_SP_2 BIT_2 4580 #define FC_SP_1 BIT_0 4581 u8 fc_sp_cc10; 4582 u8 encode; 4583 u8 bitrate; 4584 u8 rate_id; 4585 u8 length_km; /* offset 14/eh */ 4586 u8 length_100m; 4587 u8 length_50um_10m; 4588 u8 length_62um_10m; 4589 u8 length_om4_10m; 4590 u8 length_om3_10m; 4591 #define SFF_VEN_NAME_LEN 16 4592 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 4593 u8 tx_compat; 4594 u8 vendor_oui[3]; 4595 #define SFF_PART_NAME_LEN 16 4596 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 4597 u8 vendor_rev[4]; 4598 u8 wavelength[2]; 4599 u8 resv; 4600 u8 cc_base; 4601 u8 options[2]; /* offset 64 */ 4602 u8 br_max; 4603 u8 br_min; 4604 u8 vendor_sn[16]; 4605 u8 date_code[8]; 4606 u8 diag; 4607 u8 enh_options; 4608 u8 sff_revision; 4609 u8 cc_ext; 4610 u8 vendor_specific[32]; 4611 u8 resv2[128]; 4612 }; 4613 4614 #define AUTO_DETECT_SFP_SUPPORT(_vha)\ 4615 (ql2xautodetectsfp && !_vha->vp_idx && \ 4616 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\ 4617 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw))) 4618 4619 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 4620 (IS_QLA27XX(_ha) || IS_QLA83XX(_ha))) 4621 4622 #define SAVE_TOPO(_ha) { \ 4623 if (_ha->current_topology) \ 4624 _ha->prev_topology = _ha->current_topology; \ 4625 } 4626 4627 #define N2N_TOPO(ha) \ 4628 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ 4629 ha->current_topology == ISP_CFG_N || \ 4630 !ha->current_topology) 4631 4632 #include "qla_target.h" 4633 #include "qla_gbl.h" 4634 #include "qla_dbg.h" 4635 #include "qla_inline.h" 4636 #endif 4637