1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 #include <linux/btree.h> 29 30 #include <scsi/scsi.h> 31 #include <scsi/scsi_host.h> 32 #include <scsi/scsi_device.h> 33 #include <scsi/scsi_cmnd.h> 34 #include <scsi/scsi_transport_fc.h> 35 #include <scsi/scsi_bsg_fc.h> 36 37 #include "qla_bsg.h" 38 #include "qla_nx.h" 39 #include "qla_nx2.h" 40 #include "qla_nvme.h" 41 #define QLA2XXX_DRIVER_NAME "qla2xxx" 42 #define QLA2XXX_APIDEV "ql2xapidev" 43 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 44 45 /* 46 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 47 * but that's fine as we don't look at the last 24 ones for 48 * ISP2100 HBAs. 49 */ 50 #define MAILBOX_REGISTER_COUNT_2100 8 51 #define MAILBOX_REGISTER_COUNT_2200 24 52 #define MAILBOX_REGISTER_COUNT 32 53 54 #define QLA2200A_RISC_ROM_VER 4 55 #define FPM_2300 6 56 #define FPM_2310 7 57 58 #include "qla_settings.h" 59 60 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 61 62 /* 63 * Data bit definitions 64 */ 65 #define BIT_0 0x1 66 #define BIT_1 0x2 67 #define BIT_2 0x4 68 #define BIT_3 0x8 69 #define BIT_4 0x10 70 #define BIT_5 0x20 71 #define BIT_6 0x40 72 #define BIT_7 0x80 73 #define BIT_8 0x100 74 #define BIT_9 0x200 75 #define BIT_10 0x400 76 #define BIT_11 0x800 77 #define BIT_12 0x1000 78 #define BIT_13 0x2000 79 #define BIT_14 0x4000 80 #define BIT_15 0x8000 81 #define BIT_16 0x10000 82 #define BIT_17 0x20000 83 #define BIT_18 0x40000 84 #define BIT_19 0x80000 85 #define BIT_20 0x100000 86 #define BIT_21 0x200000 87 #define BIT_22 0x400000 88 #define BIT_23 0x800000 89 #define BIT_24 0x1000000 90 #define BIT_25 0x2000000 91 #define BIT_26 0x4000000 92 #define BIT_27 0x8000000 93 #define BIT_28 0x10000000 94 #define BIT_29 0x20000000 95 #define BIT_30 0x40000000 96 #define BIT_31 0x80000000 97 98 #define LSB(x) ((uint8_t)(x)) 99 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 100 101 #define LSW(x) ((uint16_t)(x)) 102 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 103 104 #define LSD(x) ((uint32_t)((uint64_t)(x))) 105 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 106 107 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 108 109 /* 110 * I/O register 111 */ 112 113 #define RD_REG_BYTE(addr) readb(addr) 114 #define RD_REG_WORD(addr) readw(addr) 115 #define RD_REG_DWORD(addr) readl(addr) 116 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 117 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 118 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 119 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 120 #define WRT_REG_WORD(addr, data) writew(data,addr) 121 #define WRT_REG_DWORD(addr, data) writel(data,addr) 122 123 /* 124 * ISP83XX specific remote register addresses 125 */ 126 #define QLA83XX_LED_PORT0 0x00201320 127 #define QLA83XX_LED_PORT1 0x00201328 128 #define QLA83XX_IDC_DEV_STATE 0x22102384 129 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 130 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 131 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 132 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 133 #define QLA83XX_IDC_CONTROL 0x22102390 134 #define QLA83XX_IDC_AUDIT 0x22102394 135 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 136 #define QLA83XX_DRIVER_LOCKID 0x22102104 137 #define QLA83XX_DRIVER_LOCK 0x8111c028 138 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 139 #define QLA83XX_FLASH_LOCKID 0x22102100 140 #define QLA83XX_FLASH_LOCK 0x8111c010 141 #define QLA83XX_FLASH_UNLOCK 0x8111c014 142 #define QLA83XX_DEV_PARTINFO1 0x221023e0 143 #define QLA83XX_DEV_PARTINFO2 0x221023e4 144 #define QLA83XX_FW_HEARTBEAT 0x221020b0 145 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 146 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 147 148 /* 83XX: Macros defining 8200 AEN Reason codes */ 149 #define IDC_DEVICE_STATE_CHANGE BIT_0 150 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 151 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 152 #define IDC_HEARTBEAT_FAILURE BIT_3 153 154 /* 83XX: Macros defining 8200 AEN Error-levels */ 155 #define ERR_LEVEL_NON_FATAL 0x1 156 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 157 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 158 159 /* 83XX: Macros for IDC Version */ 160 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 161 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 162 163 /* 83XX: Macros for scheduling dpc tasks */ 164 #define QLA83XX_NIC_CORE_RESET 0x1 165 #define QLA83XX_IDC_STATE_HANDLER 0x2 166 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 167 168 /* 83XX: Macros for defining IDC-Control bits */ 169 #define QLA83XX_IDC_RESET_DISABLED BIT_0 170 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 171 172 /* 83XX: Macros for different timeouts */ 173 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 174 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 175 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 176 177 /* 83XX: Macros for defining class in DEV-Partition Info register */ 178 #define QLA83XX_CLASS_TYPE_NONE 0x0 179 #define QLA83XX_CLASS_TYPE_NIC 0x1 180 #define QLA83XX_CLASS_TYPE_FCOE 0x2 181 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 182 183 /* 83XX: Macros for IDC Lock-Recovery stages */ 184 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 185 * lock-recovery 186 */ 187 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 188 189 /* 83XX: Macros for IDC Audit type */ 190 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 191 * dev-state change to NEED-RESET 192 * or NEED-QUIESCENT 193 */ 194 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 195 * reset-recovery completion is 196 * second 197 */ 198 /* ISP2031: Values for laser on/off */ 199 #define PORT_0_2031 0x00201340 200 #define PORT_1_2031 0x00201350 201 #define LASER_ON_2031 0x01800100 202 #define LASER_OFF_2031 0x01800180 203 204 /* 205 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 206 * 133Mhz slot. 207 */ 208 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 209 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 210 211 /* 212 * Fibre Channel device definitions. 213 */ 214 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 215 #define MAX_FIBRE_DEVICES_2100 512 216 #define MAX_FIBRE_DEVICES_2400 2048 217 #define MAX_FIBRE_DEVICES_LOOP 128 218 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 219 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 220 #define MAX_FIBRE_LUNS 0xFFFF 221 #define MAX_HOST_COUNT 16 222 223 /* 224 * Host adapter default definitions. 225 */ 226 #define MAX_BUSES 1 /* We only have one bus today */ 227 #define MIN_LUNS 8 228 #define MAX_LUNS MAX_FIBRE_LUNS 229 #define MAX_CMDS_PER_LUN 255 230 231 /* 232 * Fibre Channel device definitions. 233 */ 234 #define SNS_LAST_LOOP_ID_2100 0xfe 235 #define SNS_LAST_LOOP_ID_2300 0x7ff 236 237 #define LAST_LOCAL_LOOP_ID 0x7d 238 #define SNS_FL_PORT 0x7e 239 #define FABRIC_CONTROLLER 0x7f 240 #define SIMPLE_NAME_SERVER 0x80 241 #define SNS_FIRST_LOOP_ID 0x81 242 #define MANAGEMENT_SERVER 0xfe 243 #define BROADCAST 0xff 244 245 /* 246 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 247 * valid range of an N-PORT id is 0 through 0x7ef. 248 */ 249 #define NPH_LAST_HANDLE 0x7ef 250 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ 251 #define NPH_SNS 0x7fc /* FFFFFC */ 252 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 253 #define NPH_F_PORT 0x7fe /* FFFFFE */ 254 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 255 256 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 257 258 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 259 #include "qla_fw.h" 260 261 struct name_list_extended { 262 struct get_name_list_extended *l; 263 dma_addr_t ldma; 264 struct list_head fcports; /* protect by sess_list */ 265 u32 size; 266 u8 sent; 267 }; 268 /* 269 * Timeout timer counts in seconds 270 */ 271 #define PORT_RETRY_TIME 1 272 #define LOOP_DOWN_TIMEOUT 60 273 #define LOOP_DOWN_TIME 255 /* 240 */ 274 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 275 276 #define DEFAULT_OUTSTANDING_COMMANDS 4096 277 #define MIN_OUTSTANDING_COMMANDS 128 278 279 /* ISP request and response entry counts (37-65535) */ 280 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 281 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 282 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 283 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 284 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 285 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 286 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 287 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 288 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 289 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 290 #define FW_DEF_EXCHANGES_CNT 2048 291 292 struct req_que; 293 struct qla_tgt_sess; 294 295 /* 296 * SCSI Request Block 297 */ 298 struct srb_cmd { 299 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 300 uint32_t request_sense_length; 301 uint32_t fw_sense_length; 302 uint8_t *request_sense_ptr; 303 void *ctx; 304 }; 305 306 /* 307 * SRB flag definitions 308 */ 309 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 310 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 311 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 312 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 313 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 314 315 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 316 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 317 318 struct els_logo_payload { 319 uint8_t opcode; 320 uint8_t rsvd[3]; 321 uint8_t s_id[3]; 322 uint8_t rsvd1[1]; 323 uint8_t wwpn[WWN_SIZE]; 324 }; 325 326 struct ct_arg { 327 void *iocb; 328 u16 nport_handle; 329 dma_addr_t req_dma; 330 dma_addr_t rsp_dma; 331 u32 req_size; 332 u32 rsp_size; 333 void *req; 334 void *rsp; 335 }; 336 337 /* 338 * SRB extensions. 339 */ 340 struct srb_iocb { 341 union { 342 struct { 343 uint16_t flags; 344 #define SRB_LOGIN_RETRIED BIT_0 345 #define SRB_LOGIN_COND_PLOGI BIT_1 346 #define SRB_LOGIN_SKIP_PRLI BIT_2 347 #define SRB_LOGIN_NVME_PRLI BIT_3 348 uint16_t data[2]; 349 u32 iop[2]; 350 } logio; 351 struct { 352 #define ELS_DCMD_TIMEOUT 20 353 #define ELS_DCMD_LOGO 0x5 354 uint32_t flags; 355 uint32_t els_cmd; 356 struct completion comp; 357 struct els_logo_payload *els_logo_pyld; 358 dma_addr_t els_logo_pyld_dma; 359 } els_logo; 360 struct { 361 /* 362 * Values for flags field below are as 363 * defined in tsk_mgmt_entry struct 364 * for control_flags field in qla_fw.h. 365 */ 366 uint64_t lun; 367 uint32_t flags; 368 uint32_t data; 369 struct completion comp; 370 __le16 comp_status; 371 } tmf; 372 struct { 373 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 374 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 375 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 376 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 377 #define FXDISC_TIMEOUT 20 378 uint8_t flags; 379 uint32_t req_len; 380 uint32_t rsp_len; 381 void *req_addr; 382 void *rsp_addr; 383 dma_addr_t req_dma_handle; 384 dma_addr_t rsp_dma_handle; 385 __le32 adapter_id; 386 __le32 adapter_id_hi; 387 __le16 req_func_type; 388 __le32 req_data; 389 __le32 req_data_extra; 390 __le32 result; 391 __le32 seq_number; 392 __le16 fw_flags; 393 struct completion fxiocb_comp; 394 __le32 reserved_0; 395 uint8_t reserved_1; 396 } fxiocb; 397 struct { 398 uint32_t cmd_hndl; 399 __le16 comp_status; 400 struct completion comp; 401 } abt; 402 struct ct_arg ctarg; 403 #define MAX_IOCB_MB_REG 28 404 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 405 struct { 406 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 407 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 408 void *out, *in; 409 dma_addr_t out_dma, in_dma; 410 struct completion comp; 411 int rc; 412 } mbx; 413 struct { 414 struct imm_ntfy_from_isp *ntfy; 415 } nack; 416 struct { 417 __le16 comp_status; 418 uint16_t rsp_pyld_len; 419 uint8_t aen_op; 420 void *desc; 421 422 /* These are only used with ls4 requests */ 423 int cmd_len; 424 int rsp_len; 425 dma_addr_t cmd_dma; 426 dma_addr_t rsp_dma; 427 enum nvmefc_fcp_datadir dir; 428 uint32_t dl; 429 uint32_t timeout_sec; 430 } nvme; 431 } u; 432 433 struct timer_list timer; 434 void (*timeout)(void *); 435 }; 436 437 /* Values for srb_ctx type */ 438 #define SRB_LOGIN_CMD 1 439 #define SRB_LOGOUT_CMD 2 440 #define SRB_ELS_CMD_RPT 3 441 #define SRB_ELS_CMD_HST 4 442 #define SRB_CT_CMD 5 443 #define SRB_ADISC_CMD 6 444 #define SRB_TM_CMD 7 445 #define SRB_SCSI_CMD 8 446 #define SRB_BIDI_CMD 9 447 #define SRB_FXIOCB_DCMD 10 448 #define SRB_FXIOCB_BCMD 11 449 #define SRB_ABT_CMD 12 450 #define SRB_ELS_DCMD 13 451 #define SRB_MB_IOCB 14 452 #define SRB_CT_PTHRU_CMD 15 453 #define SRB_NACK_PLOGI 16 454 #define SRB_NACK_PRLI 17 455 #define SRB_NACK_LOGO 18 456 #define SRB_NVME_CMD 19 457 #define SRB_NVME_LS 20 458 #define SRB_PRLI_CMD 21 459 460 enum { 461 TYPE_SRB, 462 TYPE_TGT_CMD, 463 }; 464 465 typedef struct srb { 466 /* 467 * Do not move cmd_type field, it needs to 468 * line up with qla_tgt_cmd->cmd_type 469 */ 470 uint8_t cmd_type; 471 uint8_t pad[3]; 472 atomic_t ref_count; 473 wait_queue_head_t nvme_ls_waitQ; 474 struct fc_port *fcport; 475 struct scsi_qla_host *vha; 476 uint32_t handle; 477 uint16_t flags; 478 uint16_t type; 479 const char *name; 480 int iocbs; 481 struct qla_qpair *qpair; 482 u32 gen1; /* scratch */ 483 u32 gen2; /* scratch */ 484 union { 485 struct srb_iocb iocb_cmd; 486 struct bsg_job *bsg_job; 487 struct srb_cmd scmd; 488 } u; 489 void (*done)(void *, int); 490 void (*free)(void *); 491 } srb_t; 492 493 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 494 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 495 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 496 497 #define GET_CMD_SENSE_LEN(sp) \ 498 (sp->u.scmd.request_sense_length) 499 #define SET_CMD_SENSE_LEN(sp, len) \ 500 (sp->u.scmd.request_sense_length = len) 501 #define GET_CMD_SENSE_PTR(sp) \ 502 (sp->u.scmd.request_sense_ptr) 503 #define SET_CMD_SENSE_PTR(sp, ptr) \ 504 (sp->u.scmd.request_sense_ptr = ptr) 505 #define GET_FW_SENSE_LEN(sp) \ 506 (sp->u.scmd.fw_sense_length) 507 #define SET_FW_SENSE_LEN(sp, len) \ 508 (sp->u.scmd.fw_sense_length = len) 509 510 struct msg_echo_lb { 511 dma_addr_t send_dma; 512 dma_addr_t rcv_dma; 513 uint16_t req_sg_cnt; 514 uint16_t rsp_sg_cnt; 515 uint16_t options; 516 uint32_t transfer_size; 517 uint32_t iteration_count; 518 }; 519 520 /* 521 * ISP I/O Register Set structure definitions. 522 */ 523 struct device_reg_2xxx { 524 uint16_t flash_address; /* Flash BIOS address */ 525 uint16_t flash_data; /* Flash BIOS data */ 526 uint16_t unused_1[1]; /* Gap */ 527 uint16_t ctrl_status; /* Control/Status */ 528 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 529 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 530 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 531 532 uint16_t ictrl; /* Interrupt control */ 533 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 534 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 535 536 uint16_t istatus; /* Interrupt status */ 537 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 538 539 uint16_t semaphore; /* Semaphore */ 540 uint16_t nvram; /* NVRAM register. */ 541 #define NVR_DESELECT 0 542 #define NVR_BUSY BIT_15 543 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 544 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 545 #define NVR_DATA_IN BIT_3 546 #define NVR_DATA_OUT BIT_2 547 #define NVR_SELECT BIT_1 548 #define NVR_CLOCK BIT_0 549 550 #define NVR_WAIT_CNT 20000 551 552 union { 553 struct { 554 uint16_t mailbox0; 555 uint16_t mailbox1; 556 uint16_t mailbox2; 557 uint16_t mailbox3; 558 uint16_t mailbox4; 559 uint16_t mailbox5; 560 uint16_t mailbox6; 561 uint16_t mailbox7; 562 uint16_t unused_2[59]; /* Gap */ 563 } __attribute__((packed)) isp2100; 564 struct { 565 /* Request Queue */ 566 uint16_t req_q_in; /* In-Pointer */ 567 uint16_t req_q_out; /* Out-Pointer */ 568 /* Response Queue */ 569 uint16_t rsp_q_in; /* In-Pointer */ 570 uint16_t rsp_q_out; /* Out-Pointer */ 571 572 /* RISC to Host Status */ 573 uint32_t host_status; 574 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 575 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 576 577 /* Host to Host Semaphore */ 578 uint16_t host_semaphore; 579 uint16_t unused_3[17]; /* Gap */ 580 uint16_t mailbox0; 581 uint16_t mailbox1; 582 uint16_t mailbox2; 583 uint16_t mailbox3; 584 uint16_t mailbox4; 585 uint16_t mailbox5; 586 uint16_t mailbox6; 587 uint16_t mailbox7; 588 uint16_t mailbox8; 589 uint16_t mailbox9; 590 uint16_t mailbox10; 591 uint16_t mailbox11; 592 uint16_t mailbox12; 593 uint16_t mailbox13; 594 uint16_t mailbox14; 595 uint16_t mailbox15; 596 uint16_t mailbox16; 597 uint16_t mailbox17; 598 uint16_t mailbox18; 599 uint16_t mailbox19; 600 uint16_t mailbox20; 601 uint16_t mailbox21; 602 uint16_t mailbox22; 603 uint16_t mailbox23; 604 uint16_t mailbox24; 605 uint16_t mailbox25; 606 uint16_t mailbox26; 607 uint16_t mailbox27; 608 uint16_t mailbox28; 609 uint16_t mailbox29; 610 uint16_t mailbox30; 611 uint16_t mailbox31; 612 uint16_t fb_cmd; 613 uint16_t unused_4[10]; /* Gap */ 614 } __attribute__((packed)) isp2300; 615 } u; 616 617 uint16_t fpm_diag_config; 618 uint16_t unused_5[0x4]; /* Gap */ 619 uint16_t risc_hw; 620 uint16_t unused_5_1; /* Gap */ 621 uint16_t pcr; /* Processor Control Register. */ 622 uint16_t unused_6[0x5]; /* Gap */ 623 uint16_t mctr; /* Memory Configuration and Timing. */ 624 uint16_t unused_7[0x3]; /* Gap */ 625 uint16_t fb_cmd_2100; /* Unused on 23XX */ 626 uint16_t unused_8[0x3]; /* Gap */ 627 uint16_t hccr; /* Host command & control register. */ 628 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 629 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 630 /* HCCR commands */ 631 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 632 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 633 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 634 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 635 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 636 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 637 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 638 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 639 640 uint16_t unused_9[5]; /* Gap */ 641 uint16_t gpiod; /* GPIO Data register. */ 642 uint16_t gpioe; /* GPIO Enable register. */ 643 #define GPIO_LED_MASK 0x00C0 644 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 645 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 646 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 647 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 648 #define GPIO_LED_ALL_OFF 0x0000 649 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 650 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 651 652 union { 653 struct { 654 uint16_t unused_10[8]; /* Gap */ 655 uint16_t mailbox8; 656 uint16_t mailbox9; 657 uint16_t mailbox10; 658 uint16_t mailbox11; 659 uint16_t mailbox12; 660 uint16_t mailbox13; 661 uint16_t mailbox14; 662 uint16_t mailbox15; 663 uint16_t mailbox16; 664 uint16_t mailbox17; 665 uint16_t mailbox18; 666 uint16_t mailbox19; 667 uint16_t mailbox20; 668 uint16_t mailbox21; 669 uint16_t mailbox22; 670 uint16_t mailbox23; /* Also probe reg. */ 671 } __attribute__((packed)) isp2200; 672 } u_end; 673 }; 674 675 struct device_reg_25xxmq { 676 uint32_t req_q_in; 677 uint32_t req_q_out; 678 uint32_t rsp_q_in; 679 uint32_t rsp_q_out; 680 uint32_t atio_q_in; 681 uint32_t atio_q_out; 682 }; 683 684 685 struct device_reg_fx00 { 686 uint32_t mailbox0; /* 00 */ 687 uint32_t mailbox1; /* 04 */ 688 uint32_t mailbox2; /* 08 */ 689 uint32_t mailbox3; /* 0C */ 690 uint32_t mailbox4; /* 10 */ 691 uint32_t mailbox5; /* 14 */ 692 uint32_t mailbox6; /* 18 */ 693 uint32_t mailbox7; /* 1C */ 694 uint32_t mailbox8; /* 20 */ 695 uint32_t mailbox9; /* 24 */ 696 uint32_t mailbox10; /* 28 */ 697 uint32_t mailbox11; 698 uint32_t mailbox12; 699 uint32_t mailbox13; 700 uint32_t mailbox14; 701 uint32_t mailbox15; 702 uint32_t mailbox16; 703 uint32_t mailbox17; 704 uint32_t mailbox18; 705 uint32_t mailbox19; 706 uint32_t mailbox20; 707 uint32_t mailbox21; 708 uint32_t mailbox22; 709 uint32_t mailbox23; 710 uint32_t mailbox24; 711 uint32_t mailbox25; 712 uint32_t mailbox26; 713 uint32_t mailbox27; 714 uint32_t mailbox28; 715 uint32_t mailbox29; 716 uint32_t mailbox30; 717 uint32_t mailbox31; 718 uint32_t aenmailbox0; 719 uint32_t aenmailbox1; 720 uint32_t aenmailbox2; 721 uint32_t aenmailbox3; 722 uint32_t aenmailbox4; 723 uint32_t aenmailbox5; 724 uint32_t aenmailbox6; 725 uint32_t aenmailbox7; 726 /* Request Queue. */ 727 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 728 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 729 /* Response Queue. */ 730 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 731 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 732 /* Init values shadowed on FW Up Event */ 733 uint32_t initval0; /* B0 */ 734 uint32_t initval1; /* B4 */ 735 uint32_t initval2; /* B8 */ 736 uint32_t initval3; /* BC */ 737 uint32_t initval4; /* C0 */ 738 uint32_t initval5; /* C4 */ 739 uint32_t initval6; /* C8 */ 740 uint32_t initval7; /* CC */ 741 uint32_t fwheartbeat; /* D0 */ 742 uint32_t pseudoaen; /* D4 */ 743 }; 744 745 746 747 typedef union { 748 struct device_reg_2xxx isp; 749 struct device_reg_24xx isp24; 750 struct device_reg_25xxmq isp25mq; 751 struct device_reg_82xx isp82; 752 struct device_reg_fx00 ispfx00; 753 } __iomem device_reg_t; 754 755 #define ISP_REQ_Q_IN(ha, reg) \ 756 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 757 &(reg)->u.isp2100.mailbox4 : \ 758 &(reg)->u.isp2300.req_q_in) 759 #define ISP_REQ_Q_OUT(ha, reg) \ 760 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 761 &(reg)->u.isp2100.mailbox4 : \ 762 &(reg)->u.isp2300.req_q_out) 763 #define ISP_RSP_Q_IN(ha, reg) \ 764 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 765 &(reg)->u.isp2100.mailbox5 : \ 766 &(reg)->u.isp2300.rsp_q_in) 767 #define ISP_RSP_Q_OUT(ha, reg) \ 768 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 769 &(reg)->u.isp2100.mailbox5 : \ 770 &(reg)->u.isp2300.rsp_q_out) 771 772 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 773 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 774 775 #define MAILBOX_REG(ha, reg, num) \ 776 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 777 (num < 8 ? \ 778 &(reg)->u.isp2100.mailbox0 + (num) : \ 779 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 780 &(reg)->u.isp2300.mailbox0 + (num)) 781 #define RD_MAILBOX_REG(ha, reg, num) \ 782 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 783 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 784 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 785 786 #define FB_CMD_REG(ha, reg) \ 787 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 788 &(reg)->fb_cmd_2100 : \ 789 &(reg)->u.isp2300.fb_cmd) 790 #define RD_FB_CMD_REG(ha, reg) \ 791 RD_REG_WORD(FB_CMD_REG(ha, reg)) 792 #define WRT_FB_CMD_REG(ha, reg, data) \ 793 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 794 795 typedef struct { 796 uint32_t out_mb; /* outbound from driver */ 797 uint32_t in_mb; /* Incoming from RISC */ 798 uint16_t mb[MAILBOX_REGISTER_COUNT]; 799 long buf_size; 800 void *bufp; 801 uint32_t tov; 802 uint8_t flags; 803 #define MBX_DMA_IN BIT_0 804 #define MBX_DMA_OUT BIT_1 805 #define IOCTL_CMD BIT_2 806 } mbx_cmd_t; 807 808 struct mbx_cmd_32 { 809 uint32_t out_mb; /* outbound from driver */ 810 uint32_t in_mb; /* Incoming from RISC */ 811 uint32_t mb[MAILBOX_REGISTER_COUNT]; 812 long buf_size; 813 void *bufp; 814 uint32_t tov; 815 uint8_t flags; 816 #define MBX_DMA_IN BIT_0 817 #define MBX_DMA_OUT BIT_1 818 #define IOCTL_CMD BIT_2 819 }; 820 821 822 #define MBX_TOV_SECONDS 30 823 824 /* 825 * ISP product identification definitions in mailboxes after reset. 826 */ 827 #define PROD_ID_1 0x4953 828 #define PROD_ID_2 0x0000 829 #define PROD_ID_2a 0x5020 830 #define PROD_ID_3 0x2020 831 832 /* 833 * ISP mailbox Self-Test status codes 834 */ 835 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 836 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 837 #define MBS_BUSY 4 /* Busy. */ 838 839 /* 840 * ISP mailbox command complete status codes 841 */ 842 #define MBS_COMMAND_COMPLETE 0x4000 843 #define MBS_INVALID_COMMAND 0x4001 844 #define MBS_HOST_INTERFACE_ERROR 0x4002 845 #define MBS_TEST_FAILED 0x4003 846 #define MBS_COMMAND_ERROR 0x4005 847 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 848 #define MBS_PORT_ID_USED 0x4007 849 #define MBS_LOOP_ID_USED 0x4008 850 #define MBS_ALL_IDS_IN_USE 0x4009 851 #define MBS_NOT_LOGGED_IN 0x400A 852 #define MBS_LINK_DOWN_ERROR 0x400B 853 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 854 855 /* 856 * ISP mailbox asynchronous event status codes 857 */ 858 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 859 #define MBA_RESET 0x8001 /* Reset Detected. */ 860 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 861 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 862 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 863 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 864 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 865 /* occurred. */ 866 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 867 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 868 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 869 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 870 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 871 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 872 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 873 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 874 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 875 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 876 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 877 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 878 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 879 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 880 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 881 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 882 /* used. */ 883 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 884 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 885 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 886 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 887 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 888 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 889 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 890 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 891 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 892 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 893 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 894 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 895 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 896 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 897 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 898 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 899 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 900 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 901 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 902 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 903 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 904 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 905 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 906 Notification */ 907 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 908 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 909 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 910 /* 83XX FCoE specific */ 911 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 912 913 /* Interrupt type codes */ 914 #define INTR_ROM_MB_SUCCESS 0x1 915 #define INTR_ROM_MB_FAILED 0x2 916 #define INTR_MB_SUCCESS 0x10 917 #define INTR_MB_FAILED 0x11 918 #define INTR_ASYNC_EVENT 0x12 919 #define INTR_RSP_QUE_UPDATE 0x13 920 #define INTR_RSP_QUE_UPDATE_83XX 0x14 921 #define INTR_ATIO_QUE_UPDATE 0x1C 922 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 923 924 /* ISP mailbox loopback echo diagnostic error code */ 925 #define MBS_LB_RESET 0x17 926 /* 927 * Firmware options 1, 2, 3. 928 */ 929 #define FO1_AE_ON_LIPF8 BIT_0 930 #define FO1_AE_ALL_LIP_RESET BIT_1 931 #define FO1_CTIO_RETRY BIT_3 932 #define FO1_DISABLE_LIP_F7_SW BIT_4 933 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 934 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 935 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 936 #define FO1_SET_EMPHASIS_SWING BIT_8 937 #define FO1_AE_AUTO_BYPASS BIT_9 938 #define FO1_ENABLE_PURE_IOCB BIT_10 939 #define FO1_AE_PLOGI_RJT BIT_11 940 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 941 #define FO1_AE_QUEUE_FULL BIT_13 942 943 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 944 #define FO2_REV_LOOPBACK BIT_1 945 946 #define FO3_ENABLE_EMERG_IOCB BIT_0 947 #define FO3_AE_RND_ERROR BIT_1 948 949 /* 24XX additional firmware options */ 950 #define ADD_FO_COUNT 3 951 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 952 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 953 954 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 955 956 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 957 958 /* 959 * ISP mailbox commands 960 */ 961 #define MBC_LOAD_RAM 1 /* Load RAM. */ 962 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 963 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 964 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 965 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 966 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 967 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 968 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 969 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 970 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 971 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 972 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 973 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 974 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 975 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 976 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 977 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 978 #define MBC_RESET 0x18 /* Reset. */ 979 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 980 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 981 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 982 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 983 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 984 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 985 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 986 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 987 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 988 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 989 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 990 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 991 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 992 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 993 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 994 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 995 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 996 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 997 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 998 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 999 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1000 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1001 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1002 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1003 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1004 /* Initialization Procedure */ 1005 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1006 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1007 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1008 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1009 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1010 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1011 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1012 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1013 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1014 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1015 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1016 /* commandd. */ 1017 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1018 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1019 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1020 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1021 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1022 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1023 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1024 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1025 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1026 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1027 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1028 1029 /* 1030 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1031 * should be defined with MBC_MR_* 1032 */ 1033 #define MBC_MR_DRV_SHUTDOWN 0x6A 1034 1035 /* 1036 * ISP24xx mailbox commands 1037 */ 1038 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1039 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1040 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1041 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1042 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1043 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1044 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1045 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1046 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1047 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1048 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1049 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1050 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1051 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1052 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1053 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1054 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1055 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1056 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1057 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1058 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1059 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1060 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1061 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1062 1063 /* 1064 * ISP81xx mailbox commands 1065 */ 1066 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1067 1068 /* 1069 * ISP8044 mailbox commands 1070 */ 1071 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1072 #define HCS_WRITE_SERDES 0x3 1073 #define HCS_READ_SERDES 0x4 1074 1075 /* Firmware return data sizes */ 1076 #define FCAL_MAP_SIZE 128 1077 1078 /* Mailbox bit definitions for out_mb and in_mb */ 1079 #define MBX_31 BIT_31 1080 #define MBX_30 BIT_30 1081 #define MBX_29 BIT_29 1082 #define MBX_28 BIT_28 1083 #define MBX_27 BIT_27 1084 #define MBX_26 BIT_26 1085 #define MBX_25 BIT_25 1086 #define MBX_24 BIT_24 1087 #define MBX_23 BIT_23 1088 #define MBX_22 BIT_22 1089 #define MBX_21 BIT_21 1090 #define MBX_20 BIT_20 1091 #define MBX_19 BIT_19 1092 #define MBX_18 BIT_18 1093 #define MBX_17 BIT_17 1094 #define MBX_16 BIT_16 1095 #define MBX_15 BIT_15 1096 #define MBX_14 BIT_14 1097 #define MBX_13 BIT_13 1098 #define MBX_12 BIT_12 1099 #define MBX_11 BIT_11 1100 #define MBX_10 BIT_10 1101 #define MBX_9 BIT_9 1102 #define MBX_8 BIT_8 1103 #define MBX_7 BIT_7 1104 #define MBX_6 BIT_6 1105 #define MBX_5 BIT_5 1106 #define MBX_4 BIT_4 1107 #define MBX_3 BIT_3 1108 #define MBX_2 BIT_2 1109 #define MBX_1 BIT_1 1110 #define MBX_0 BIT_0 1111 1112 #define RNID_TYPE_PORT_LOGIN 0x7 1113 #define RNID_TYPE_SET_VERSION 0x9 1114 #define RNID_TYPE_ASIC_TEMP 0xC 1115 1116 /* 1117 * Firmware state codes from get firmware state mailbox command 1118 */ 1119 #define FSTATE_CONFIG_WAIT 0 1120 #define FSTATE_WAIT_AL_PA 1 1121 #define FSTATE_WAIT_LOGIN 2 1122 #define FSTATE_READY 3 1123 #define FSTATE_LOSS_OF_SYNC 4 1124 #define FSTATE_ERROR 5 1125 #define FSTATE_REINIT 6 1126 #define FSTATE_NON_PART 7 1127 1128 #define FSTATE_CONFIG_CORRECT 0 1129 #define FSTATE_P2P_RCV_LIP 1 1130 #define FSTATE_P2P_CHOOSE_LOOP 2 1131 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1132 #define FSTATE_FATAL_ERROR 4 1133 #define FSTATE_LOOP_BACK_CONN 5 1134 1135 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1136 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1137 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1138 #define QLA27XX_PRIMARY_IMAGE 1 1139 #define QLA27XX_SECONDARY_IMAGE 2 1140 1141 /* 1142 * Port Database structure definition 1143 * Little endian except where noted. 1144 */ 1145 #define PORT_DATABASE_SIZE 128 /* bytes */ 1146 typedef struct { 1147 uint8_t options; 1148 uint8_t control; 1149 uint8_t master_state; 1150 uint8_t slave_state; 1151 uint8_t reserved[2]; 1152 uint8_t hard_address; 1153 uint8_t reserved_1; 1154 uint8_t port_id[4]; 1155 uint8_t node_name[WWN_SIZE]; 1156 uint8_t port_name[WWN_SIZE]; 1157 uint16_t execution_throttle; 1158 uint16_t execution_count; 1159 uint8_t reset_count; 1160 uint8_t reserved_2; 1161 uint16_t resource_allocation; 1162 uint16_t current_allocation; 1163 uint16_t queue_head; 1164 uint16_t queue_tail; 1165 uint16_t transmit_execution_list_next; 1166 uint16_t transmit_execution_list_previous; 1167 uint16_t common_features; 1168 uint16_t total_concurrent_sequences; 1169 uint16_t RO_by_information_category; 1170 uint8_t recipient; 1171 uint8_t initiator; 1172 uint16_t receive_data_size; 1173 uint16_t concurrent_sequences; 1174 uint16_t open_sequences_per_exchange; 1175 uint16_t lun_abort_flags; 1176 uint16_t lun_stop_flags; 1177 uint16_t stop_queue_head; 1178 uint16_t stop_queue_tail; 1179 uint16_t port_retry_timer; 1180 uint16_t next_sequence_id; 1181 uint16_t frame_count; 1182 uint16_t PRLI_payload_length; 1183 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1184 /* Bits 15-0 of word 0 */ 1185 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1186 /* Bits 15-0 of word 3 */ 1187 uint16_t loop_id; 1188 uint16_t extended_lun_info_list_pointer; 1189 uint16_t extended_lun_stop_list_pointer; 1190 } port_database_t; 1191 1192 /* 1193 * Port database slave/master states 1194 */ 1195 #define PD_STATE_DISCOVERY 0 1196 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1197 #define PD_STATE_PORT_LOGIN 2 1198 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1199 #define PD_STATE_PROCESS_LOGIN 4 1200 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1201 #define PD_STATE_PORT_LOGGED_IN 6 1202 #define PD_STATE_PORT_UNAVAILABLE 7 1203 #define PD_STATE_PROCESS_LOGOUT 8 1204 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1205 #define PD_STATE_PORT_LOGOUT 10 1206 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1207 1208 1209 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1210 #define QLA_ZIO_DISABLED 0 1211 #define QLA_ZIO_DEFAULT_TIMER 2 1212 1213 /* 1214 * ISP Initialization Control Block. 1215 * Little endian except where noted. 1216 */ 1217 #define ICB_VERSION 1 1218 typedef struct { 1219 uint8_t version; 1220 uint8_t reserved_1; 1221 1222 /* 1223 * LSB BIT 0 = Enable Hard Loop Id 1224 * LSB BIT 1 = Enable Fairness 1225 * LSB BIT 2 = Enable Full-Duplex 1226 * LSB BIT 3 = Enable Fast Posting 1227 * LSB BIT 4 = Enable Target Mode 1228 * LSB BIT 5 = Disable Initiator Mode 1229 * LSB BIT 6 = Enable ADISC 1230 * LSB BIT 7 = Enable Target Inquiry Data 1231 * 1232 * MSB BIT 0 = Enable PDBC Notify 1233 * MSB BIT 1 = Non Participating LIP 1234 * MSB BIT 2 = Descending Loop ID Search 1235 * MSB BIT 3 = Acquire Loop ID in LIPA 1236 * MSB BIT 4 = Stop PortQ on Full Status 1237 * MSB BIT 5 = Full Login after LIP 1238 * MSB BIT 6 = Node Name Option 1239 * MSB BIT 7 = Ext IFWCB enable bit 1240 */ 1241 uint8_t firmware_options[2]; 1242 1243 uint16_t frame_payload_size; 1244 uint16_t max_iocb_allocation; 1245 uint16_t execution_throttle; 1246 uint8_t retry_count; 1247 uint8_t retry_delay; /* unused */ 1248 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1249 uint16_t hard_address; 1250 uint8_t inquiry_data; 1251 uint8_t login_timeout; 1252 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1253 1254 uint16_t request_q_outpointer; 1255 uint16_t response_q_inpointer; 1256 uint16_t request_q_length; 1257 uint16_t response_q_length; 1258 uint32_t request_q_address[2]; 1259 uint32_t response_q_address[2]; 1260 1261 uint16_t lun_enables; 1262 uint8_t command_resource_count; 1263 uint8_t immediate_notify_resource_count; 1264 uint16_t timeout; 1265 uint8_t reserved_2[2]; 1266 1267 /* 1268 * LSB BIT 0 = Timer Operation mode bit 0 1269 * LSB BIT 1 = Timer Operation mode bit 1 1270 * LSB BIT 2 = Timer Operation mode bit 2 1271 * LSB BIT 3 = Timer Operation mode bit 3 1272 * LSB BIT 4 = Init Config Mode bit 0 1273 * LSB BIT 5 = Init Config Mode bit 1 1274 * LSB BIT 6 = Init Config Mode bit 2 1275 * LSB BIT 7 = Enable Non part on LIHA failure 1276 * 1277 * MSB BIT 0 = Enable class 2 1278 * MSB BIT 1 = Enable ACK0 1279 * MSB BIT 2 = 1280 * MSB BIT 3 = 1281 * MSB BIT 4 = FC Tape Enable 1282 * MSB BIT 5 = Enable FC Confirm 1283 * MSB BIT 6 = Enable command queuing in target mode 1284 * MSB BIT 7 = No Logo On Link Down 1285 */ 1286 uint8_t add_firmware_options[2]; 1287 1288 uint8_t response_accumulation_timer; 1289 uint8_t interrupt_delay_timer; 1290 1291 /* 1292 * LSB BIT 0 = Enable Read xfr_rdy 1293 * LSB BIT 1 = Soft ID only 1294 * LSB BIT 2 = 1295 * LSB BIT 3 = 1296 * LSB BIT 4 = FCP RSP Payload [0] 1297 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1298 * LSB BIT 6 = Enable Out-of-Order frame handling 1299 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1300 * 1301 * MSB BIT 0 = Sbus enable - 2300 1302 * MSB BIT 1 = 1303 * MSB BIT 2 = 1304 * MSB BIT 3 = 1305 * MSB BIT 4 = LED mode 1306 * MSB BIT 5 = enable 50 ohm termination 1307 * MSB BIT 6 = Data Rate (2300 only) 1308 * MSB BIT 7 = Data Rate (2300 only) 1309 */ 1310 uint8_t special_options[2]; 1311 1312 uint8_t reserved_3[26]; 1313 } init_cb_t; 1314 1315 /* 1316 * Get Link Status mailbox command return buffer. 1317 */ 1318 #define GLSO_SEND_RPS BIT_0 1319 #define GLSO_USE_DID BIT_3 1320 1321 struct link_statistics { 1322 uint32_t link_fail_cnt; 1323 uint32_t loss_sync_cnt; 1324 uint32_t loss_sig_cnt; 1325 uint32_t prim_seq_err_cnt; 1326 uint32_t inval_xmit_word_cnt; 1327 uint32_t inval_crc_cnt; 1328 uint32_t lip_cnt; 1329 uint32_t link_up_cnt; 1330 uint32_t link_down_loop_init_tmo; 1331 uint32_t link_down_los; 1332 uint32_t link_down_loss_rcv_clk; 1333 uint32_t reserved0[5]; 1334 uint32_t port_cfg_chg; 1335 uint32_t reserved1[11]; 1336 uint32_t rsp_q_full; 1337 uint32_t atio_q_full; 1338 uint32_t drop_ae; 1339 uint32_t els_proto_err; 1340 uint32_t reserved2; 1341 uint32_t tx_frames; 1342 uint32_t rx_frames; 1343 uint32_t discarded_frames; 1344 uint32_t dropped_frames; 1345 uint32_t reserved3; 1346 uint32_t nos_rcvd; 1347 uint32_t reserved4[4]; 1348 uint32_t tx_prjt; 1349 uint32_t rcv_exfail; 1350 uint32_t rcv_abts; 1351 uint32_t seq_frm_miss; 1352 uint32_t corr_err; 1353 uint32_t mb_rqst; 1354 uint32_t nport_full; 1355 uint32_t eofa; 1356 uint32_t reserved5; 1357 uint32_t fpm_recv_word_cnt_lo; 1358 uint32_t fpm_recv_word_cnt_hi; 1359 uint32_t fpm_disc_word_cnt_lo; 1360 uint32_t fpm_disc_word_cnt_hi; 1361 uint32_t fpm_xmit_word_cnt_lo; 1362 uint32_t fpm_xmit_word_cnt_hi; 1363 uint32_t reserved6[70]; 1364 }; 1365 1366 /* 1367 * NVRAM Command values. 1368 */ 1369 #define NV_START_BIT BIT_2 1370 #define NV_WRITE_OP (BIT_26+BIT_24) 1371 #define NV_READ_OP (BIT_26+BIT_25) 1372 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1373 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1374 #define NV_DELAY_COUNT 10 1375 1376 /* 1377 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1378 */ 1379 typedef struct { 1380 /* 1381 * NVRAM header 1382 */ 1383 uint8_t id[4]; 1384 uint8_t nvram_version; 1385 uint8_t reserved_0; 1386 1387 /* 1388 * NVRAM RISC parameter block 1389 */ 1390 uint8_t parameter_block_version; 1391 uint8_t reserved_1; 1392 1393 /* 1394 * LSB BIT 0 = Enable Hard Loop Id 1395 * LSB BIT 1 = Enable Fairness 1396 * LSB BIT 2 = Enable Full-Duplex 1397 * LSB BIT 3 = Enable Fast Posting 1398 * LSB BIT 4 = Enable Target Mode 1399 * LSB BIT 5 = Disable Initiator Mode 1400 * LSB BIT 6 = Enable ADISC 1401 * LSB BIT 7 = Enable Target Inquiry Data 1402 * 1403 * MSB BIT 0 = Enable PDBC Notify 1404 * MSB BIT 1 = Non Participating LIP 1405 * MSB BIT 2 = Descending Loop ID Search 1406 * MSB BIT 3 = Acquire Loop ID in LIPA 1407 * MSB BIT 4 = Stop PortQ on Full Status 1408 * MSB BIT 5 = Full Login after LIP 1409 * MSB BIT 6 = Node Name Option 1410 * MSB BIT 7 = Ext IFWCB enable bit 1411 */ 1412 uint8_t firmware_options[2]; 1413 1414 uint16_t frame_payload_size; 1415 uint16_t max_iocb_allocation; 1416 uint16_t execution_throttle; 1417 uint8_t retry_count; 1418 uint8_t retry_delay; /* unused */ 1419 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1420 uint16_t hard_address; 1421 uint8_t inquiry_data; 1422 uint8_t login_timeout; 1423 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1424 1425 /* 1426 * LSB BIT 0 = Timer Operation mode bit 0 1427 * LSB BIT 1 = Timer Operation mode bit 1 1428 * LSB BIT 2 = Timer Operation mode bit 2 1429 * LSB BIT 3 = Timer Operation mode bit 3 1430 * LSB BIT 4 = Init Config Mode bit 0 1431 * LSB BIT 5 = Init Config Mode bit 1 1432 * LSB BIT 6 = Init Config Mode bit 2 1433 * LSB BIT 7 = Enable Non part on LIHA failure 1434 * 1435 * MSB BIT 0 = Enable class 2 1436 * MSB BIT 1 = Enable ACK0 1437 * MSB BIT 2 = 1438 * MSB BIT 3 = 1439 * MSB BIT 4 = FC Tape Enable 1440 * MSB BIT 5 = Enable FC Confirm 1441 * MSB BIT 6 = Enable command queuing in target mode 1442 * MSB BIT 7 = No Logo On Link Down 1443 */ 1444 uint8_t add_firmware_options[2]; 1445 1446 uint8_t response_accumulation_timer; 1447 uint8_t interrupt_delay_timer; 1448 1449 /* 1450 * LSB BIT 0 = Enable Read xfr_rdy 1451 * LSB BIT 1 = Soft ID only 1452 * LSB BIT 2 = 1453 * LSB BIT 3 = 1454 * LSB BIT 4 = FCP RSP Payload [0] 1455 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1456 * LSB BIT 6 = Enable Out-of-Order frame handling 1457 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1458 * 1459 * MSB BIT 0 = Sbus enable - 2300 1460 * MSB BIT 1 = 1461 * MSB BIT 2 = 1462 * MSB BIT 3 = 1463 * MSB BIT 4 = LED mode 1464 * MSB BIT 5 = enable 50 ohm termination 1465 * MSB BIT 6 = Data Rate (2300 only) 1466 * MSB BIT 7 = Data Rate (2300 only) 1467 */ 1468 uint8_t special_options[2]; 1469 1470 /* Reserved for expanded RISC parameter block */ 1471 uint8_t reserved_2[22]; 1472 1473 /* 1474 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1475 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1476 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1477 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1478 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1479 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1480 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1481 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1482 * 1483 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1484 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1485 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1486 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1487 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1488 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1489 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1490 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1491 * 1492 * LSB BIT 0 = Output Swing 1G bit 0 1493 * LSB BIT 1 = Output Swing 1G bit 1 1494 * LSB BIT 2 = Output Swing 1G bit 2 1495 * LSB BIT 3 = Output Emphasis 1G bit 0 1496 * LSB BIT 4 = Output Emphasis 1G bit 1 1497 * LSB BIT 5 = Output Swing 2G bit 0 1498 * LSB BIT 6 = Output Swing 2G bit 1 1499 * LSB BIT 7 = Output Swing 2G bit 2 1500 * 1501 * MSB BIT 0 = Output Emphasis 2G bit 0 1502 * MSB BIT 1 = Output Emphasis 2G bit 1 1503 * MSB BIT 2 = Output Enable 1504 * MSB BIT 3 = 1505 * MSB BIT 4 = 1506 * MSB BIT 5 = 1507 * MSB BIT 6 = 1508 * MSB BIT 7 = 1509 */ 1510 uint8_t seriallink_options[4]; 1511 1512 /* 1513 * NVRAM host parameter block 1514 * 1515 * LSB BIT 0 = Enable spinup delay 1516 * LSB BIT 1 = Disable BIOS 1517 * LSB BIT 2 = Enable Memory Map BIOS 1518 * LSB BIT 3 = Enable Selectable Boot 1519 * LSB BIT 4 = Disable RISC code load 1520 * LSB BIT 5 = Set cache line size 1 1521 * LSB BIT 6 = PCI Parity Disable 1522 * LSB BIT 7 = Enable extended logging 1523 * 1524 * MSB BIT 0 = Enable 64bit addressing 1525 * MSB BIT 1 = Enable lip reset 1526 * MSB BIT 2 = Enable lip full login 1527 * MSB BIT 3 = Enable target reset 1528 * MSB BIT 4 = Enable database storage 1529 * MSB BIT 5 = Enable cache flush read 1530 * MSB BIT 6 = Enable database load 1531 * MSB BIT 7 = Enable alternate WWN 1532 */ 1533 uint8_t host_p[2]; 1534 1535 uint8_t boot_node_name[WWN_SIZE]; 1536 uint8_t boot_lun_number; 1537 uint8_t reset_delay; 1538 uint8_t port_down_retry_count; 1539 uint8_t boot_id_number; 1540 uint16_t max_luns_per_target; 1541 uint8_t fcode_boot_port_name[WWN_SIZE]; 1542 uint8_t alternate_port_name[WWN_SIZE]; 1543 uint8_t alternate_node_name[WWN_SIZE]; 1544 1545 /* 1546 * BIT 0 = Selective Login 1547 * BIT 1 = Alt-Boot Enable 1548 * BIT 2 = 1549 * BIT 3 = Boot Order List 1550 * BIT 4 = 1551 * BIT 5 = Selective LUN 1552 * BIT 6 = 1553 * BIT 7 = unused 1554 */ 1555 uint8_t efi_parameters; 1556 1557 uint8_t link_down_timeout; 1558 1559 uint8_t adapter_id[16]; 1560 1561 uint8_t alt1_boot_node_name[WWN_SIZE]; 1562 uint16_t alt1_boot_lun_number; 1563 uint8_t alt2_boot_node_name[WWN_SIZE]; 1564 uint16_t alt2_boot_lun_number; 1565 uint8_t alt3_boot_node_name[WWN_SIZE]; 1566 uint16_t alt3_boot_lun_number; 1567 uint8_t alt4_boot_node_name[WWN_SIZE]; 1568 uint16_t alt4_boot_lun_number; 1569 uint8_t alt5_boot_node_name[WWN_SIZE]; 1570 uint16_t alt5_boot_lun_number; 1571 uint8_t alt6_boot_node_name[WWN_SIZE]; 1572 uint16_t alt6_boot_lun_number; 1573 uint8_t alt7_boot_node_name[WWN_SIZE]; 1574 uint16_t alt7_boot_lun_number; 1575 1576 uint8_t reserved_3[2]; 1577 1578 /* Offset 200-215 : Model Number */ 1579 uint8_t model_number[16]; 1580 1581 /* OEM related items */ 1582 uint8_t oem_specific[16]; 1583 1584 /* 1585 * NVRAM Adapter Features offset 232-239 1586 * 1587 * LSB BIT 0 = External GBIC 1588 * LSB BIT 1 = Risc RAM parity 1589 * LSB BIT 2 = Buffer Plus Module 1590 * LSB BIT 3 = Multi Chip Adapter 1591 * LSB BIT 4 = Internal connector 1592 * LSB BIT 5 = 1593 * LSB BIT 6 = 1594 * LSB BIT 7 = 1595 * 1596 * MSB BIT 0 = 1597 * MSB BIT 1 = 1598 * MSB BIT 2 = 1599 * MSB BIT 3 = 1600 * MSB BIT 4 = 1601 * MSB BIT 5 = 1602 * MSB BIT 6 = 1603 * MSB BIT 7 = 1604 */ 1605 uint8_t adapter_features[2]; 1606 1607 uint8_t reserved_4[16]; 1608 1609 /* Subsystem vendor ID for ISP2200 */ 1610 uint16_t subsystem_vendor_id_2200; 1611 1612 /* Subsystem device ID for ISP2200 */ 1613 uint16_t subsystem_device_id_2200; 1614 1615 uint8_t reserved_5; 1616 uint8_t checksum; 1617 } nvram_t; 1618 1619 /* 1620 * ISP queue - response queue entry definition. 1621 */ 1622 typedef struct { 1623 uint8_t entry_type; /* Entry type. */ 1624 uint8_t entry_count; /* Entry count. */ 1625 uint8_t sys_define; /* System defined. */ 1626 uint8_t entry_status; /* Entry Status. */ 1627 uint32_t handle; /* System defined handle */ 1628 uint8_t data[52]; 1629 uint32_t signature; 1630 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1631 } response_t; 1632 1633 /* 1634 * ISP queue - ATIO queue entry definition. 1635 */ 1636 struct atio { 1637 uint8_t entry_type; /* Entry type. */ 1638 uint8_t entry_count; /* Entry count. */ 1639 __le16 attr_n_length; 1640 uint8_t data[56]; 1641 uint32_t signature; 1642 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1643 }; 1644 1645 typedef union { 1646 uint16_t extended; 1647 struct { 1648 uint8_t reserved; 1649 uint8_t standard; 1650 } id; 1651 } target_id_t; 1652 1653 #define SET_TARGET_ID(ha, to, from) \ 1654 do { \ 1655 if (HAS_EXTENDED_IDS(ha)) \ 1656 to.extended = cpu_to_le16(from); \ 1657 else \ 1658 to.id.standard = (uint8_t)from; \ 1659 } while (0) 1660 1661 /* 1662 * ISP queue - command entry structure definition. 1663 */ 1664 #define COMMAND_TYPE 0x11 /* Command entry */ 1665 typedef struct { 1666 uint8_t entry_type; /* Entry type. */ 1667 uint8_t entry_count; /* Entry count. */ 1668 uint8_t sys_define; /* System defined. */ 1669 uint8_t entry_status; /* Entry Status. */ 1670 uint32_t handle; /* System handle. */ 1671 target_id_t target; /* SCSI ID */ 1672 uint16_t lun; /* SCSI LUN */ 1673 uint16_t control_flags; /* Control flags. */ 1674 #define CF_WRITE BIT_6 1675 #define CF_READ BIT_5 1676 #define CF_SIMPLE_TAG BIT_3 1677 #define CF_ORDERED_TAG BIT_2 1678 #define CF_HEAD_TAG BIT_1 1679 uint16_t reserved_1; 1680 uint16_t timeout; /* Command timeout. */ 1681 uint16_t dseg_count; /* Data segment count. */ 1682 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1683 uint32_t byte_count; /* Total byte count. */ 1684 uint32_t dseg_0_address; /* Data segment 0 address. */ 1685 uint32_t dseg_0_length; /* Data segment 0 length. */ 1686 uint32_t dseg_1_address; /* Data segment 1 address. */ 1687 uint32_t dseg_1_length; /* Data segment 1 length. */ 1688 uint32_t dseg_2_address; /* Data segment 2 address. */ 1689 uint32_t dseg_2_length; /* Data segment 2 length. */ 1690 } cmd_entry_t; 1691 1692 /* 1693 * ISP queue - 64-Bit addressing, command entry structure definition. 1694 */ 1695 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1696 typedef struct { 1697 uint8_t entry_type; /* Entry type. */ 1698 uint8_t entry_count; /* Entry count. */ 1699 uint8_t sys_define; /* System defined. */ 1700 uint8_t entry_status; /* Entry Status. */ 1701 uint32_t handle; /* System handle. */ 1702 target_id_t target; /* SCSI ID */ 1703 uint16_t lun; /* SCSI LUN */ 1704 uint16_t control_flags; /* Control flags. */ 1705 uint16_t reserved_1; 1706 uint16_t timeout; /* Command timeout. */ 1707 uint16_t dseg_count; /* Data segment count. */ 1708 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1709 uint32_t byte_count; /* Total byte count. */ 1710 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1711 uint32_t dseg_0_length; /* Data segment 0 length. */ 1712 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1713 uint32_t dseg_1_length; /* Data segment 1 length. */ 1714 } cmd_a64_entry_t, request_t; 1715 1716 /* 1717 * ISP queue - continuation entry structure definition. 1718 */ 1719 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1720 typedef struct { 1721 uint8_t entry_type; /* Entry type. */ 1722 uint8_t entry_count; /* Entry count. */ 1723 uint8_t sys_define; /* System defined. */ 1724 uint8_t entry_status; /* Entry Status. */ 1725 uint32_t reserved; 1726 uint32_t dseg_0_address; /* Data segment 0 address. */ 1727 uint32_t dseg_0_length; /* Data segment 0 length. */ 1728 uint32_t dseg_1_address; /* Data segment 1 address. */ 1729 uint32_t dseg_1_length; /* Data segment 1 length. */ 1730 uint32_t dseg_2_address; /* Data segment 2 address. */ 1731 uint32_t dseg_2_length; /* Data segment 2 length. */ 1732 uint32_t dseg_3_address; /* Data segment 3 address. */ 1733 uint32_t dseg_3_length; /* Data segment 3 length. */ 1734 uint32_t dseg_4_address; /* Data segment 4 address. */ 1735 uint32_t dseg_4_length; /* Data segment 4 length. */ 1736 uint32_t dseg_5_address; /* Data segment 5 address. */ 1737 uint32_t dseg_5_length; /* Data segment 5 length. */ 1738 uint32_t dseg_6_address; /* Data segment 6 address. */ 1739 uint32_t dseg_6_length; /* Data segment 6 length. */ 1740 } cont_entry_t; 1741 1742 /* 1743 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1744 */ 1745 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1746 typedef struct { 1747 uint8_t entry_type; /* Entry type. */ 1748 uint8_t entry_count; /* Entry count. */ 1749 uint8_t sys_define; /* System defined. */ 1750 uint8_t entry_status; /* Entry Status. */ 1751 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1752 uint32_t dseg_0_length; /* Data segment 0 length. */ 1753 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1754 uint32_t dseg_1_length; /* Data segment 1 length. */ 1755 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1756 uint32_t dseg_2_length; /* Data segment 2 length. */ 1757 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1758 uint32_t dseg_3_length; /* Data segment 3 length. */ 1759 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1760 uint32_t dseg_4_length; /* Data segment 4 length. */ 1761 } cont_a64_entry_t; 1762 1763 #define PO_MODE_DIF_INSERT 0 1764 #define PO_MODE_DIF_REMOVE 1 1765 #define PO_MODE_DIF_PASS 2 1766 #define PO_MODE_DIF_REPLACE 3 1767 #define PO_MODE_DIF_TCP_CKSUM 6 1768 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1769 #define PO_DISABLE_GUARD_CHECK BIT_4 1770 #define PO_DISABLE_INCR_REF_TAG BIT_5 1771 #define PO_DIS_HEADER_MODE BIT_7 1772 #define PO_ENABLE_DIF_BUNDLING BIT_8 1773 #define PO_DIS_FRAME_MODE BIT_9 1774 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1775 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1776 1777 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1778 #define PO_DIS_REF_TAG_REPL BIT_13 1779 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1780 #define PO_DIS_REF_TAG_VALD BIT_15 1781 1782 /* 1783 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1784 */ 1785 struct crc_context { 1786 uint32_t handle; /* System handle. */ 1787 __le32 ref_tag; 1788 __le16 app_tag; 1789 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1790 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1791 __le16 guard_seed; /* Initial Guard Seed */ 1792 __le16 prot_opts; /* Requested Data Protection Mode */ 1793 __le16 blk_size; /* Data size in bytes */ 1794 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1795 * only) */ 1796 __le32 byte_count; /* Total byte count/ total data 1797 * transfer count */ 1798 union { 1799 struct { 1800 uint32_t reserved_1; 1801 uint16_t reserved_2; 1802 uint16_t reserved_3; 1803 uint32_t reserved_4; 1804 uint32_t data_address[2]; 1805 uint32_t data_length; 1806 uint32_t reserved_5[2]; 1807 uint32_t reserved_6; 1808 } nobundling; 1809 struct { 1810 __le32 dif_byte_count; /* Total DIF byte 1811 * count */ 1812 uint16_t reserved_1; 1813 __le16 dseg_count; /* Data segment count */ 1814 uint32_t reserved_2; 1815 uint32_t data_address[2]; 1816 uint32_t data_length; 1817 uint32_t dif_address[2]; 1818 uint32_t dif_length; /* Data segment 0 1819 * length */ 1820 } bundling; 1821 } u; 1822 1823 struct fcp_cmnd fcp_cmnd; 1824 dma_addr_t crc_ctx_dma; 1825 /* List of DMA context transfers */ 1826 struct list_head dsd_list; 1827 1828 /* This structure should not exceed 512 bytes */ 1829 }; 1830 1831 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1832 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1833 1834 /* 1835 * ISP queue - status entry structure definition. 1836 */ 1837 #define STATUS_TYPE 0x03 /* Status entry. */ 1838 typedef struct { 1839 uint8_t entry_type; /* Entry type. */ 1840 uint8_t entry_count; /* Entry count. */ 1841 uint8_t sys_define; /* System defined. */ 1842 uint8_t entry_status; /* Entry Status. */ 1843 uint32_t handle; /* System handle. */ 1844 uint16_t scsi_status; /* SCSI status. */ 1845 uint16_t comp_status; /* Completion status. */ 1846 uint16_t state_flags; /* State flags. */ 1847 uint16_t status_flags; /* Status flags. */ 1848 uint16_t rsp_info_len; /* Response Info Length. */ 1849 uint16_t req_sense_length; /* Request sense data length. */ 1850 uint32_t residual_length; /* Residual transfer length. */ 1851 uint8_t rsp_info[8]; /* FCP response information. */ 1852 uint8_t req_sense_data[32]; /* Request sense data. */ 1853 } sts_entry_t; 1854 1855 /* 1856 * Status entry entry status 1857 */ 1858 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1859 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1860 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1861 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1862 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1863 #define RF_BUSY BIT_1 /* Busy */ 1864 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1865 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1866 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1867 RF_INV_E_TYPE) 1868 1869 /* 1870 * Status entry SCSI status bit definitions. 1871 */ 1872 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1873 #define SS_RESIDUAL_UNDER BIT_11 1874 #define SS_RESIDUAL_OVER BIT_10 1875 #define SS_SENSE_LEN_VALID BIT_9 1876 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1877 #define SS_SCSI_STATUS_BYTE 0xff 1878 1879 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1880 #define SS_BUSY_CONDITION BIT_3 1881 #define SS_CONDITION_MET BIT_2 1882 #define SS_CHECK_CONDITION BIT_1 1883 1884 /* 1885 * Status entry completion status 1886 */ 1887 #define CS_COMPLETE 0x0 /* No errors */ 1888 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1889 #define CS_DMA 0x2 /* A DMA direction error. */ 1890 #define CS_TRANSPORT 0x3 /* Transport error. */ 1891 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1892 #define CS_ABORTED 0x5 /* System aborted command. */ 1893 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1894 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1895 #define CS_DIF_ERROR 0xC /* DIF error detected */ 1896 1897 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1898 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1899 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1900 /* (selection timeout) */ 1901 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1902 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1903 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1904 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1905 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 1906 failure */ 1907 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1908 #define CS_UNKNOWN 0x81 /* Driver defined */ 1909 #define CS_RETRY 0x82 /* Driver defined */ 1910 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1911 1912 #define CS_BIDIR_RD_OVERRUN 0x700 1913 #define CS_BIDIR_RD_WR_OVERRUN 0x707 1914 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 1915 #define CS_BIDIR_RD_UNDERRUN 0x1500 1916 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 1917 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 1918 #define CS_BIDIR_DMA 0x200 1919 /* 1920 * Status entry status flags 1921 */ 1922 #define SF_ABTS_TERMINATED BIT_10 1923 #define SF_LOGOUT_SENT BIT_13 1924 1925 /* 1926 * ISP queue - status continuation entry structure definition. 1927 */ 1928 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1929 typedef struct { 1930 uint8_t entry_type; /* Entry type. */ 1931 uint8_t entry_count; /* Entry count. */ 1932 uint8_t sys_define; /* System defined. */ 1933 uint8_t entry_status; /* Entry Status. */ 1934 uint8_t data[60]; /* data */ 1935 } sts_cont_entry_t; 1936 1937 /* 1938 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1939 * structure definition. 1940 */ 1941 #define STATUS_TYPE_21 0x21 /* Status entry. */ 1942 typedef struct { 1943 uint8_t entry_type; /* Entry type. */ 1944 uint8_t entry_count; /* Entry count. */ 1945 uint8_t handle_count; /* Handle count. */ 1946 uint8_t entry_status; /* Entry Status. */ 1947 uint32_t handle[15]; /* System handles. */ 1948 } sts21_entry_t; 1949 1950 /* 1951 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1952 * structure definition. 1953 */ 1954 #define STATUS_TYPE_22 0x22 /* Status entry. */ 1955 typedef struct { 1956 uint8_t entry_type; /* Entry type. */ 1957 uint8_t entry_count; /* Entry count. */ 1958 uint8_t handle_count; /* Handle count. */ 1959 uint8_t entry_status; /* Entry Status. */ 1960 uint16_t handle[30]; /* System handles. */ 1961 } sts22_entry_t; 1962 1963 /* 1964 * ISP queue - marker entry structure definition. 1965 */ 1966 #define MARKER_TYPE 0x04 /* Marker entry. */ 1967 typedef struct { 1968 uint8_t entry_type; /* Entry type. */ 1969 uint8_t entry_count; /* Entry count. */ 1970 uint8_t handle_count; /* Handle count. */ 1971 uint8_t entry_status; /* Entry Status. */ 1972 uint32_t sys_define_2; /* System defined. */ 1973 target_id_t target; /* SCSI ID */ 1974 uint8_t modifier; /* Modifier (7-0). */ 1975 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1976 #define MK_SYNC_ID 1 /* Synchronize ID */ 1977 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1978 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 1979 /* clear port changed, */ 1980 /* use sequence number. */ 1981 uint8_t reserved_1; 1982 uint16_t sequence_number; /* Sequence number of event */ 1983 uint16_t lun; /* SCSI LUN */ 1984 uint8_t reserved_2[48]; 1985 } mrk_entry_t; 1986 1987 /* 1988 * ISP queue - Management Server entry structure definition. 1989 */ 1990 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 1991 typedef struct { 1992 uint8_t entry_type; /* Entry type. */ 1993 uint8_t entry_count; /* Entry count. */ 1994 uint8_t handle_count; /* Handle count. */ 1995 uint8_t entry_status; /* Entry Status. */ 1996 uint32_t handle1; /* System handle. */ 1997 target_id_t loop_id; 1998 uint16_t status; 1999 uint16_t control_flags; /* Control flags. */ 2000 uint16_t reserved2; 2001 uint16_t timeout; 2002 uint16_t cmd_dsd_count; 2003 uint16_t total_dsd_count; 2004 uint8_t type; 2005 uint8_t r_ctl; 2006 uint16_t rx_id; 2007 uint16_t reserved3; 2008 uint32_t handle2; 2009 uint32_t rsp_bytecount; 2010 uint32_t req_bytecount; 2011 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 2012 uint32_t dseg_req_length; /* Data segment 0 length. */ 2013 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 2014 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 2015 } ms_iocb_entry_t; 2016 2017 2018 /* 2019 * ISP queue - Mailbox Command entry structure definition. 2020 */ 2021 #define MBX_IOCB_TYPE 0x39 2022 struct mbx_entry { 2023 uint8_t entry_type; 2024 uint8_t entry_count; 2025 uint8_t sys_define1; 2026 /* Use sys_define1 for source type */ 2027 #define SOURCE_SCSI 0x00 2028 #define SOURCE_IP 0x01 2029 #define SOURCE_VI 0x02 2030 #define SOURCE_SCTP 0x03 2031 #define SOURCE_MP 0x04 2032 #define SOURCE_MPIOCTL 0x05 2033 #define SOURCE_ASYNC_IOCB 0x07 2034 2035 uint8_t entry_status; 2036 2037 uint32_t handle; 2038 target_id_t loop_id; 2039 2040 uint16_t status; 2041 uint16_t state_flags; 2042 uint16_t status_flags; 2043 2044 uint32_t sys_define2[2]; 2045 2046 uint16_t mb0; 2047 uint16_t mb1; 2048 uint16_t mb2; 2049 uint16_t mb3; 2050 uint16_t mb6; 2051 uint16_t mb7; 2052 uint16_t mb9; 2053 uint16_t mb10; 2054 uint32_t reserved_2[2]; 2055 uint8_t node_name[WWN_SIZE]; 2056 uint8_t port_name[WWN_SIZE]; 2057 }; 2058 2059 #ifndef IMMED_NOTIFY_TYPE 2060 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2061 /* 2062 * ISP queue - immediate notify entry structure definition. 2063 * This is sent by the ISP to the Target driver. 2064 * This IOCB would have report of events sent by the 2065 * initiator, that needs to be handled by the target 2066 * driver immediately. 2067 */ 2068 struct imm_ntfy_from_isp { 2069 uint8_t entry_type; /* Entry type. */ 2070 uint8_t entry_count; /* Entry count. */ 2071 uint8_t sys_define; /* System defined. */ 2072 uint8_t entry_status; /* Entry Status. */ 2073 union { 2074 struct { 2075 uint32_t sys_define_2; /* System defined. */ 2076 target_id_t target; 2077 uint16_t lun; 2078 uint8_t target_id; 2079 uint8_t reserved_1; 2080 uint16_t status_modifier; 2081 uint16_t status; 2082 uint16_t task_flags; 2083 uint16_t seq_id; 2084 uint16_t srr_rx_id; 2085 uint32_t srr_rel_offs; 2086 uint16_t srr_ui; 2087 #define SRR_IU_DATA_IN 0x1 2088 #define SRR_IU_DATA_OUT 0x5 2089 #define SRR_IU_STATUS 0x7 2090 uint16_t srr_ox_id; 2091 uint8_t reserved_2[28]; 2092 } isp2x; 2093 struct { 2094 uint32_t reserved; 2095 uint16_t nport_handle; 2096 uint16_t reserved_2; 2097 uint16_t flags; 2098 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2099 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2100 uint16_t srr_rx_id; 2101 uint16_t status; 2102 uint8_t status_subcode; 2103 uint8_t fw_handle; 2104 uint32_t exchange_address; 2105 uint32_t srr_rel_offs; 2106 uint16_t srr_ui; 2107 uint16_t srr_ox_id; 2108 union { 2109 struct { 2110 uint8_t node_name[8]; 2111 } plogi; /* PLOGI/ADISC/PDISC */ 2112 struct { 2113 /* PRLI word 3 bit 0-15 */ 2114 uint16_t wd3_lo; 2115 uint8_t resv0[6]; 2116 } prli; 2117 struct { 2118 uint8_t port_id[3]; 2119 uint8_t resv1; 2120 uint16_t nport_handle; 2121 uint16_t resv2; 2122 } req_els; 2123 } u; 2124 uint8_t port_name[8]; 2125 uint8_t resv3[3]; 2126 uint8_t vp_index; 2127 uint32_t reserved_5; 2128 uint8_t port_id[3]; 2129 uint8_t reserved_6; 2130 } isp24; 2131 } u; 2132 uint16_t reserved_7; 2133 uint16_t ox_id; 2134 } __packed; 2135 #endif 2136 2137 /* 2138 * ISP request and response queue entry sizes 2139 */ 2140 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2141 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2142 2143 2144 /* 2145 * 24 bit port ID type definition. 2146 */ 2147 typedef union { 2148 uint32_t b24 : 24; 2149 2150 struct { 2151 #ifdef __BIG_ENDIAN 2152 uint8_t domain; 2153 uint8_t area; 2154 uint8_t al_pa; 2155 #elif defined(__LITTLE_ENDIAN) 2156 uint8_t al_pa; 2157 uint8_t area; 2158 uint8_t domain; 2159 #else 2160 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 2161 #endif 2162 uint8_t rsvd_1; 2163 } b; 2164 } port_id_t; 2165 #define INVALID_PORT_ID 0xFFFFFF 2166 2167 /* 2168 * Switch info gathering structure. 2169 */ 2170 typedef struct { 2171 port_id_t d_id; 2172 uint8_t node_name[WWN_SIZE]; 2173 uint8_t port_name[WWN_SIZE]; 2174 uint8_t fabric_port_name[WWN_SIZE]; 2175 uint16_t fp_speed; 2176 uint8_t fc4_type; 2177 uint8_t fc4f_nvme; /* nvme fc4 feature bits */ 2178 } sw_info_t; 2179 2180 /* FCP-4 types */ 2181 #define FC4_TYPE_FCP_SCSI 0x08 2182 #define FC4_TYPE_OTHER 0x0 2183 #define FC4_TYPE_UNKNOWN 0xff 2184 2185 /* mailbox command 4G & above */ 2186 struct mbx_24xx_entry { 2187 uint8_t entry_type; 2188 uint8_t entry_count; 2189 uint8_t sys_define1; 2190 uint8_t entry_status; 2191 uint32_t handle; 2192 uint16_t mb[28]; 2193 }; 2194 2195 #define IOCB_SIZE 64 2196 2197 /* 2198 * Fibre channel port type. 2199 */ 2200 typedef enum { 2201 FCT_UNKNOWN, 2202 FCT_RSCN, 2203 FCT_SWITCH, 2204 FCT_BROADCAST, 2205 FCT_INITIATOR, 2206 FCT_TARGET, 2207 FCT_NVME 2208 } fc_port_type_t; 2209 2210 enum qla_sess_deletion { 2211 QLA_SESS_DELETION_NONE = 0, 2212 QLA_SESS_DELETION_IN_PROGRESS, 2213 QLA_SESS_DELETED, 2214 }; 2215 2216 enum qlt_plogi_link_t { 2217 QLT_PLOGI_LINK_SAME_WWN, 2218 QLT_PLOGI_LINK_CONFLICT, 2219 QLT_PLOGI_LINK_MAX 2220 }; 2221 2222 struct qlt_plogi_ack_t { 2223 struct list_head list; 2224 struct imm_ntfy_from_isp iocb; 2225 port_id_t id; 2226 int ref_count; 2227 void *fcport; 2228 }; 2229 2230 struct ct_sns_desc { 2231 struct ct_sns_pkt *ct_sns; 2232 dma_addr_t ct_sns_dma; 2233 }; 2234 2235 enum discovery_state { 2236 DSC_DELETED, 2237 DSC_GID_PN, 2238 DSC_GNL, 2239 DSC_LOGIN_PEND, 2240 DSC_LOGIN_FAILED, 2241 DSC_GPDB, 2242 DSC_GPSC, 2243 DSC_UPD_FCPORT, 2244 DSC_LOGIN_COMPLETE, 2245 DSC_DELETE_PEND, 2246 }; 2247 2248 enum login_state { /* FW control Target side */ 2249 DSC_LS_LLIOCB_SENT = 2, 2250 DSC_LS_PLOGI_PEND, 2251 DSC_LS_PLOGI_COMP, 2252 DSC_LS_PRLI_PEND, 2253 DSC_LS_PRLI_COMP, 2254 DSC_LS_PORT_UNAVAIL, 2255 DSC_LS_PRLO_PEND = 9, 2256 DSC_LS_LOGO_PEND, 2257 }; 2258 2259 enum fcport_mgt_event { 2260 FCME_RELOGIN = 1, 2261 FCME_RSCN, 2262 FCME_GIDPN_DONE, 2263 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */ 2264 FCME_PRLI_DONE, 2265 FCME_GNL_DONE, 2266 FCME_GPSC_DONE, 2267 FCME_GPDB_DONE, 2268 FCME_GPNID_DONE, 2269 FCME_GFFID_DONE, 2270 FCME_DELETE_DONE, 2271 }; 2272 2273 enum rscn_addr_format { 2274 RSCN_PORT_ADDR, 2275 RSCN_AREA_ADDR, 2276 RSCN_DOM_ADDR, 2277 RSCN_FAB_ADDR, 2278 }; 2279 2280 /* 2281 * Fibre channel port structure. 2282 */ 2283 typedef struct fc_port { 2284 struct list_head list; 2285 struct scsi_qla_host *vha; 2286 2287 uint8_t node_name[WWN_SIZE]; 2288 uint8_t port_name[WWN_SIZE]; 2289 port_id_t d_id; 2290 uint16_t loop_id; 2291 uint16_t old_loop_id; 2292 2293 unsigned int conf_compl_supported:1; 2294 unsigned int deleted:2; 2295 unsigned int local:1; 2296 unsigned int logout_on_delete:1; 2297 unsigned int logo_ack_needed:1; 2298 unsigned int keep_nport_handle:1; 2299 unsigned int send_els_logo:1; 2300 unsigned int login_pause:1; 2301 unsigned int login_succ:1; 2302 2303 struct work_struct nvme_del_work; 2304 atomic_t nvme_ref_count; 2305 wait_queue_head_t nvme_waitQ; 2306 uint32_t nvme_prli_service_param; 2307 #define NVME_PRLI_SP_CONF BIT_7 2308 #define NVME_PRLI_SP_INITIATOR BIT_5 2309 #define NVME_PRLI_SP_TARGET BIT_4 2310 #define NVME_PRLI_SP_DISCOVERY BIT_3 2311 uint8_t nvme_flag; 2312 #define NVME_FLAG_REGISTERED 4 2313 2314 struct fc_port *conflict; 2315 unsigned char logout_completed; 2316 int generation; 2317 2318 struct se_session *se_sess; 2319 struct kref sess_kref; 2320 struct qla_tgt *tgt; 2321 unsigned long expires; 2322 struct list_head del_list_entry; 2323 struct work_struct free_work; 2324 2325 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2326 2327 uint16_t tgt_id; 2328 uint16_t old_tgt_id; 2329 2330 uint8_t fcp_prio; 2331 2332 uint8_t fabric_port_name[WWN_SIZE]; 2333 uint16_t fp_speed; 2334 2335 fc_port_type_t port_type; 2336 2337 atomic_t state; 2338 uint32_t flags; 2339 2340 int login_retry; 2341 2342 struct fc_rport *rport, *drport; 2343 u32 supported_classes; 2344 2345 uint8_t fc4_type; 2346 uint8_t fc4f_nvme; 2347 uint8_t scan_state; 2348 2349 unsigned long last_queue_full; 2350 unsigned long last_ramp_up; 2351 2352 uint16_t port_id; 2353 2354 struct nvme_fc_remote_port *nvme_remote_port; 2355 2356 unsigned long retry_delay_timestamp; 2357 struct qla_tgt_sess *tgt_session; 2358 struct ct_sns_desc ct_desc; 2359 enum discovery_state disc_state; 2360 enum login_state fw_login_state; 2361 unsigned long plogi_nack_done_deadline; 2362 2363 u32 login_gen, last_login_gen; 2364 u32 rscn_gen, last_rscn_gen; 2365 u32 chip_reset; 2366 struct list_head gnl_entry; 2367 struct work_struct del_work; 2368 u8 iocb[IOCB_SIZE]; 2369 } fc_port_t; 2370 2371 #define QLA_FCPORT_SCAN 1 2372 #define QLA_FCPORT_FOUND 2 2373 2374 struct event_arg { 2375 enum fcport_mgt_event event; 2376 fc_port_t *fcport; 2377 srb_t *sp; 2378 port_id_t id; 2379 u16 data[2], rc; 2380 u8 port_name[WWN_SIZE]; 2381 u32 iop[2]; 2382 }; 2383 2384 #include "qla_mr.h" 2385 2386 /* 2387 * Fibre channel port/lun states. 2388 */ 2389 #define FCS_UNCONFIGURED 1 2390 #define FCS_DEVICE_DEAD 2 2391 #define FCS_DEVICE_LOST 3 2392 #define FCS_ONLINE 4 2393 2394 static const char * const port_state_str[] = { 2395 "Unknown", 2396 "UNCONFIGURED", 2397 "DEAD", 2398 "LOST", 2399 "ONLINE" 2400 }; 2401 2402 /* 2403 * FC port flags. 2404 */ 2405 #define FCF_FABRIC_DEVICE BIT_0 2406 #define FCF_LOGIN_NEEDED BIT_1 2407 #define FCF_FCP2_DEVICE BIT_2 2408 #define FCF_ASYNC_SENT BIT_3 2409 #define FCF_CONF_COMP_SUPPORTED BIT_4 2410 2411 /* No loop ID flag. */ 2412 #define FC_NO_LOOP_ID 0x1000 2413 2414 /* 2415 * FC-CT interface 2416 * 2417 * NOTE: All structures are big-endian in form. 2418 */ 2419 2420 #define CT_REJECT_RESPONSE 0x8001 2421 #define CT_ACCEPT_RESPONSE 0x8002 2422 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2423 #define CT_REASON_CANNOT_PERFORM 0x09 2424 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2425 #define CT_EXPL_ALREADY_REGISTERED 0x10 2426 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2427 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2428 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2429 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2430 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2431 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2432 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2433 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2434 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2435 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2436 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2437 2438 #define NS_N_PORT_TYPE 0x01 2439 #define NS_NL_PORT_TYPE 0x02 2440 #define NS_NX_PORT_TYPE 0x7F 2441 2442 #define GA_NXT_CMD 0x100 2443 #define GA_NXT_REQ_SIZE (16 + 4) 2444 #define GA_NXT_RSP_SIZE (16 + 620) 2445 2446 #define GID_PT_CMD 0x1A1 2447 #define GID_PT_REQ_SIZE (16 + 4) 2448 2449 #define GPN_ID_CMD 0x112 2450 #define GPN_ID_REQ_SIZE (16 + 4) 2451 #define GPN_ID_RSP_SIZE (16 + 8) 2452 2453 #define GNN_ID_CMD 0x113 2454 #define GNN_ID_REQ_SIZE (16 + 4) 2455 #define GNN_ID_RSP_SIZE (16 + 8) 2456 2457 #define GFT_ID_CMD 0x117 2458 #define GFT_ID_REQ_SIZE (16 + 4) 2459 #define GFT_ID_RSP_SIZE (16 + 32) 2460 2461 #define GID_PN_CMD 0x121 2462 #define GID_PN_REQ_SIZE (16 + 8) 2463 #define GID_PN_RSP_SIZE (16 + 4) 2464 2465 #define RFT_ID_CMD 0x217 2466 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2467 #define RFT_ID_RSP_SIZE 16 2468 2469 #define RFF_ID_CMD 0x21F 2470 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2471 #define RFF_ID_RSP_SIZE 16 2472 2473 #define RNN_ID_CMD 0x213 2474 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2475 #define RNN_ID_RSP_SIZE 16 2476 2477 #define RSNN_NN_CMD 0x239 2478 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2479 #define RSNN_NN_RSP_SIZE 16 2480 2481 #define GFPN_ID_CMD 0x11C 2482 #define GFPN_ID_REQ_SIZE (16 + 4) 2483 #define GFPN_ID_RSP_SIZE (16 + 8) 2484 2485 #define GPSC_CMD 0x127 2486 #define GPSC_REQ_SIZE (16 + 8) 2487 #define GPSC_RSP_SIZE (16 + 2 + 2) 2488 2489 #define GFF_ID_CMD 0x011F 2490 #define GFF_ID_REQ_SIZE (16 + 4) 2491 #define GFF_ID_RSP_SIZE (16 + 128) 2492 2493 /* 2494 * HBA attribute types. 2495 */ 2496 #define FDMI_HBA_ATTR_COUNT 9 2497 #define FDMIV2_HBA_ATTR_COUNT 17 2498 #define FDMI_HBA_NODE_NAME 0x1 2499 #define FDMI_HBA_MANUFACTURER 0x2 2500 #define FDMI_HBA_SERIAL_NUMBER 0x3 2501 #define FDMI_HBA_MODEL 0x4 2502 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2503 #define FDMI_HBA_HARDWARE_VERSION 0x6 2504 #define FDMI_HBA_DRIVER_VERSION 0x7 2505 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2506 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2507 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2508 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2509 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2510 #define FDMI_HBA_VENDOR_ID 0xd 2511 #define FDMI_HBA_NUM_PORTS 0xe 2512 #define FDMI_HBA_FABRIC_NAME 0xf 2513 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2514 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0 2515 2516 struct ct_fdmi_hba_attr { 2517 uint16_t type; 2518 uint16_t len; 2519 union { 2520 uint8_t node_name[WWN_SIZE]; 2521 uint8_t manufacturer[64]; 2522 uint8_t serial_num[32]; 2523 uint8_t model[16+1]; 2524 uint8_t model_desc[80]; 2525 uint8_t hw_version[32]; 2526 uint8_t driver_version[32]; 2527 uint8_t orom_version[16]; 2528 uint8_t fw_version[32]; 2529 uint8_t os_version[128]; 2530 uint32_t max_ct_len; 2531 } a; 2532 }; 2533 2534 struct ct_fdmi_hba_attributes { 2535 uint32_t count; 2536 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2537 }; 2538 2539 struct ct_fdmiv2_hba_attr { 2540 uint16_t type; 2541 uint16_t len; 2542 union { 2543 uint8_t node_name[WWN_SIZE]; 2544 uint8_t manufacturer[64]; 2545 uint8_t serial_num[32]; 2546 uint8_t model[16+1]; 2547 uint8_t model_desc[80]; 2548 uint8_t hw_version[16]; 2549 uint8_t driver_version[32]; 2550 uint8_t orom_version[16]; 2551 uint8_t fw_version[32]; 2552 uint8_t os_version[128]; 2553 uint32_t max_ct_len; 2554 uint8_t sym_name[256]; 2555 uint32_t vendor_id; 2556 uint32_t num_ports; 2557 uint8_t fabric_name[WWN_SIZE]; 2558 uint8_t bios_name[32]; 2559 uint8_t vendor_identifier[8]; 2560 } a; 2561 }; 2562 2563 struct ct_fdmiv2_hba_attributes { 2564 uint32_t count; 2565 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT]; 2566 }; 2567 2568 /* 2569 * Port attribute types. 2570 */ 2571 #define FDMI_PORT_ATTR_COUNT 6 2572 #define FDMIV2_PORT_ATTR_COUNT 16 2573 #define FDMI_PORT_FC4_TYPES 0x1 2574 #define FDMI_PORT_SUPPORT_SPEED 0x2 2575 #define FDMI_PORT_CURRENT_SPEED 0x3 2576 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2577 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2578 #define FDMI_PORT_HOST_NAME 0x6 2579 #define FDMI_PORT_NODE_NAME 0x7 2580 #define FDMI_PORT_NAME 0x8 2581 #define FDMI_PORT_SYM_NAME 0x9 2582 #define FDMI_PORT_TYPE 0xa 2583 #define FDMI_PORT_SUPP_COS 0xb 2584 #define FDMI_PORT_FABRIC_NAME 0xc 2585 #define FDMI_PORT_FC4_TYPE 0xd 2586 #define FDMI_PORT_STATE 0x101 2587 #define FDMI_PORT_COUNT 0x102 2588 #define FDMI_PORT_ID 0x103 2589 2590 #define FDMI_PORT_SPEED_1GB 0x1 2591 #define FDMI_PORT_SPEED_2GB 0x2 2592 #define FDMI_PORT_SPEED_10GB 0x4 2593 #define FDMI_PORT_SPEED_4GB 0x8 2594 #define FDMI_PORT_SPEED_8GB 0x10 2595 #define FDMI_PORT_SPEED_16GB 0x20 2596 #define FDMI_PORT_SPEED_32GB 0x40 2597 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2598 2599 #define FC_CLASS_2 0x04 2600 #define FC_CLASS_3 0x08 2601 #define FC_CLASS_2_3 0x0C 2602 2603 struct ct_fdmiv2_port_attr { 2604 uint16_t type; 2605 uint16_t len; 2606 union { 2607 uint8_t fc4_types[32]; 2608 uint32_t sup_speed; 2609 uint32_t cur_speed; 2610 uint32_t max_frame_size; 2611 uint8_t os_dev_name[32]; 2612 uint8_t host_name[256]; 2613 uint8_t node_name[WWN_SIZE]; 2614 uint8_t port_name[WWN_SIZE]; 2615 uint8_t port_sym_name[128]; 2616 uint32_t port_type; 2617 uint32_t port_supported_cos; 2618 uint8_t fabric_name[WWN_SIZE]; 2619 uint8_t port_fc4_type[32]; 2620 uint32_t port_state; 2621 uint32_t num_ports; 2622 uint32_t port_id; 2623 } a; 2624 }; 2625 2626 /* 2627 * Port Attribute Block. 2628 */ 2629 struct ct_fdmiv2_port_attributes { 2630 uint32_t count; 2631 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT]; 2632 }; 2633 2634 struct ct_fdmi_port_attr { 2635 uint16_t type; 2636 uint16_t len; 2637 union { 2638 uint8_t fc4_types[32]; 2639 uint32_t sup_speed; 2640 uint32_t cur_speed; 2641 uint32_t max_frame_size; 2642 uint8_t os_dev_name[32]; 2643 uint8_t host_name[256]; 2644 } a; 2645 }; 2646 2647 struct ct_fdmi_port_attributes { 2648 uint32_t count; 2649 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2650 }; 2651 2652 /* FDMI definitions. */ 2653 #define GRHL_CMD 0x100 2654 #define GHAT_CMD 0x101 2655 #define GRPL_CMD 0x102 2656 #define GPAT_CMD 0x110 2657 2658 #define RHBA_CMD 0x200 2659 #define RHBA_RSP_SIZE 16 2660 2661 #define RHAT_CMD 0x201 2662 #define RPRT_CMD 0x210 2663 2664 #define RPA_CMD 0x211 2665 #define RPA_RSP_SIZE 16 2666 2667 #define DHBA_CMD 0x300 2668 #define DHBA_REQ_SIZE (16 + 8) 2669 #define DHBA_RSP_SIZE 16 2670 2671 #define DHAT_CMD 0x301 2672 #define DPRT_CMD 0x310 2673 #define DPA_CMD 0x311 2674 2675 /* CT command header -- request/response common fields */ 2676 struct ct_cmd_hdr { 2677 uint8_t revision; 2678 uint8_t in_id[3]; 2679 uint8_t gs_type; 2680 uint8_t gs_subtype; 2681 uint8_t options; 2682 uint8_t reserved; 2683 }; 2684 2685 /* CT command request */ 2686 struct ct_sns_req { 2687 struct ct_cmd_hdr header; 2688 uint16_t command; 2689 uint16_t max_rsp_size; 2690 uint8_t fragment_id; 2691 uint8_t reserved[3]; 2692 2693 union { 2694 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2695 struct { 2696 uint8_t reserved; 2697 uint8_t port_id[3]; 2698 } port_id; 2699 2700 struct { 2701 uint8_t port_type; 2702 uint8_t domain; 2703 uint8_t area; 2704 uint8_t reserved; 2705 } gid_pt; 2706 2707 struct { 2708 uint8_t reserved; 2709 uint8_t port_id[3]; 2710 uint8_t fc4_types[32]; 2711 } rft_id; 2712 2713 struct { 2714 uint8_t reserved; 2715 uint8_t port_id[3]; 2716 uint16_t reserved2; 2717 uint8_t fc4_feature; 2718 uint8_t fc4_type; 2719 } rff_id; 2720 2721 struct { 2722 uint8_t reserved; 2723 uint8_t port_id[3]; 2724 uint8_t node_name[8]; 2725 } rnn_id; 2726 2727 struct { 2728 uint8_t node_name[8]; 2729 uint8_t name_len; 2730 uint8_t sym_node_name[255]; 2731 } rsnn_nn; 2732 2733 struct { 2734 uint8_t hba_identifier[8]; 2735 } ghat; 2736 2737 struct { 2738 uint8_t hba_identifier[8]; 2739 uint32_t entry_count; 2740 uint8_t port_name[8]; 2741 struct ct_fdmi_hba_attributes attrs; 2742 } rhba; 2743 2744 struct { 2745 uint8_t hba_identifier[8]; 2746 uint32_t entry_count; 2747 uint8_t port_name[8]; 2748 struct ct_fdmiv2_hba_attributes attrs; 2749 } rhba2; 2750 2751 struct { 2752 uint8_t hba_identifier[8]; 2753 struct ct_fdmi_hba_attributes attrs; 2754 } rhat; 2755 2756 struct { 2757 uint8_t port_name[8]; 2758 struct ct_fdmi_port_attributes attrs; 2759 } rpa; 2760 2761 struct { 2762 uint8_t port_name[8]; 2763 struct ct_fdmiv2_port_attributes attrs; 2764 } rpa2; 2765 2766 struct { 2767 uint8_t port_name[8]; 2768 } dhba; 2769 2770 struct { 2771 uint8_t port_name[8]; 2772 } dhat; 2773 2774 struct { 2775 uint8_t port_name[8]; 2776 } dprt; 2777 2778 struct { 2779 uint8_t port_name[8]; 2780 } dpa; 2781 2782 struct { 2783 uint8_t port_name[8]; 2784 } gpsc; 2785 2786 struct { 2787 uint8_t reserved; 2788 uint8_t port_id[3]; 2789 } gff_id; 2790 2791 struct { 2792 uint8_t port_name[8]; 2793 } gid_pn; 2794 } req; 2795 }; 2796 2797 /* CT command response header */ 2798 struct ct_rsp_hdr { 2799 struct ct_cmd_hdr header; 2800 uint16_t response; 2801 uint16_t residual; 2802 uint8_t fragment_id; 2803 uint8_t reason_code; 2804 uint8_t explanation_code; 2805 uint8_t vendor_unique; 2806 }; 2807 2808 struct ct_sns_gid_pt_data { 2809 uint8_t control_byte; 2810 uint8_t port_id[3]; 2811 }; 2812 2813 struct ct_sns_rsp { 2814 struct ct_rsp_hdr header; 2815 2816 union { 2817 struct { 2818 uint8_t port_type; 2819 uint8_t port_id[3]; 2820 uint8_t port_name[8]; 2821 uint8_t sym_port_name_len; 2822 uint8_t sym_port_name[255]; 2823 uint8_t node_name[8]; 2824 uint8_t sym_node_name_len; 2825 uint8_t sym_node_name[255]; 2826 uint8_t init_proc_assoc[8]; 2827 uint8_t node_ip_addr[16]; 2828 uint8_t class_of_service[4]; 2829 uint8_t fc4_types[32]; 2830 uint8_t ip_address[16]; 2831 uint8_t fabric_port_name[8]; 2832 uint8_t reserved; 2833 uint8_t hard_address[3]; 2834 } ga_nxt; 2835 2836 struct { 2837 /* Assume the largest number of targets for the union */ 2838 struct ct_sns_gid_pt_data 2839 entries[MAX_FIBRE_DEVICES_MAX]; 2840 } gid_pt; 2841 2842 struct { 2843 uint8_t port_name[8]; 2844 } gpn_id; 2845 2846 struct { 2847 uint8_t node_name[8]; 2848 } gnn_id; 2849 2850 struct { 2851 uint8_t fc4_types[32]; 2852 } gft_id; 2853 2854 struct { 2855 uint32_t entry_count; 2856 uint8_t port_name[8]; 2857 struct ct_fdmi_hba_attributes attrs; 2858 } ghat; 2859 2860 struct { 2861 uint8_t port_name[8]; 2862 } gfpn_id; 2863 2864 struct { 2865 uint16_t speeds; 2866 uint16_t speed; 2867 } gpsc; 2868 2869 #define GFF_FCP_SCSI_OFFSET 7 2870 #define GFF_NVME_OFFSET 23 /* type = 28h */ 2871 struct { 2872 uint8_t fc4_features[128]; 2873 } gff_id; 2874 struct { 2875 uint8_t reserved; 2876 uint8_t port_id[3]; 2877 } gid_pn; 2878 } rsp; 2879 }; 2880 2881 struct ct_sns_pkt { 2882 union { 2883 struct ct_sns_req req; 2884 struct ct_sns_rsp rsp; 2885 } p; 2886 }; 2887 2888 /* 2889 * SNS command structures -- for 2200 compatibility. 2890 */ 2891 #define RFT_ID_SNS_SCMD_LEN 22 2892 #define RFT_ID_SNS_CMD_SIZE 60 2893 #define RFT_ID_SNS_DATA_SIZE 16 2894 2895 #define RNN_ID_SNS_SCMD_LEN 10 2896 #define RNN_ID_SNS_CMD_SIZE 36 2897 #define RNN_ID_SNS_DATA_SIZE 16 2898 2899 #define GA_NXT_SNS_SCMD_LEN 6 2900 #define GA_NXT_SNS_CMD_SIZE 28 2901 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 2902 2903 #define GID_PT_SNS_SCMD_LEN 6 2904 #define GID_PT_SNS_CMD_SIZE 28 2905 /* 2906 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 2907 * adapters. 2908 */ 2909 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 2910 2911 #define GPN_ID_SNS_SCMD_LEN 6 2912 #define GPN_ID_SNS_CMD_SIZE 28 2913 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 2914 2915 #define GNN_ID_SNS_SCMD_LEN 6 2916 #define GNN_ID_SNS_CMD_SIZE 28 2917 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 2918 2919 struct sns_cmd_pkt { 2920 union { 2921 struct { 2922 uint16_t buffer_length; 2923 uint16_t reserved_1; 2924 uint32_t buffer_address[2]; 2925 uint16_t subcommand_length; 2926 uint16_t reserved_2; 2927 uint16_t subcommand; 2928 uint16_t size; 2929 uint32_t reserved_3; 2930 uint8_t param[36]; 2931 } cmd; 2932 2933 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 2934 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 2935 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 2936 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 2937 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 2938 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 2939 } p; 2940 }; 2941 2942 struct fw_blob { 2943 char *name; 2944 uint32_t segs[4]; 2945 const struct firmware *fw; 2946 }; 2947 2948 /* Return data from MBC_GET_ID_LIST call. */ 2949 struct gid_list_info { 2950 uint8_t al_pa; 2951 uint8_t area; 2952 uint8_t domain; 2953 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2954 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2955 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 2956 }; 2957 2958 /* NPIV */ 2959 typedef struct vport_info { 2960 uint8_t port_name[WWN_SIZE]; 2961 uint8_t node_name[WWN_SIZE]; 2962 int vp_id; 2963 uint16_t loop_id; 2964 unsigned long host_no; 2965 uint8_t port_id[3]; 2966 int loop_state; 2967 } vport_info_t; 2968 2969 typedef struct vport_params { 2970 uint8_t port_name[WWN_SIZE]; 2971 uint8_t node_name[WWN_SIZE]; 2972 uint32_t options; 2973 #define VP_OPTS_RETRY_ENABLE BIT_0 2974 #define VP_OPTS_VP_DISABLE BIT_1 2975 } vport_params_t; 2976 2977 /* NPIV - return codes of VP create and modify */ 2978 #define VP_RET_CODE_OK 0 2979 #define VP_RET_CODE_FATAL 1 2980 #define VP_RET_CODE_WRONG_ID 2 2981 #define VP_RET_CODE_WWPN 3 2982 #define VP_RET_CODE_RESOURCES 4 2983 #define VP_RET_CODE_NO_MEM 5 2984 #define VP_RET_CODE_NOT_FOUND 6 2985 2986 struct qla_hw_data; 2987 struct rsp_que; 2988 /* 2989 * ISP operations 2990 */ 2991 struct isp_operations { 2992 2993 int (*pci_config) (struct scsi_qla_host *); 2994 void (*reset_chip) (struct scsi_qla_host *); 2995 int (*chip_diag) (struct scsi_qla_host *); 2996 void (*config_rings) (struct scsi_qla_host *); 2997 void (*reset_adapter) (struct scsi_qla_host *); 2998 int (*nvram_config) (struct scsi_qla_host *); 2999 void (*update_fw_options) (struct scsi_qla_host *); 3000 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3001 3002 char * (*pci_info_str) (struct scsi_qla_host *, char *); 3003 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3004 3005 irq_handler_t intr_handler; 3006 void (*enable_intrs) (struct qla_hw_data *); 3007 void (*disable_intrs) (struct qla_hw_data *); 3008 3009 int (*abort_command) (srb_t *); 3010 int (*target_reset) (struct fc_port *, uint64_t, int); 3011 int (*lun_reset) (struct fc_port *, uint64_t, int); 3012 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3013 uint8_t, uint8_t, uint16_t *, uint8_t); 3014 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3015 uint8_t, uint8_t); 3016 3017 uint16_t (*calc_req_entries) (uint16_t); 3018 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3019 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3020 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3021 uint32_t); 3022 3023 uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *, 3024 uint32_t, uint32_t); 3025 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 3026 uint32_t); 3027 3028 void (*fw_dump) (struct scsi_qla_host *, int); 3029 3030 int (*beacon_on) (struct scsi_qla_host *); 3031 int (*beacon_off) (struct scsi_qla_host *); 3032 void (*beacon_blink) (struct scsi_qla_host *); 3033 3034 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 3035 uint32_t, uint32_t); 3036 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 3037 uint32_t); 3038 3039 int (*get_flash_version) (struct scsi_qla_host *, void *); 3040 int (*start_scsi) (srb_t *); 3041 int (*start_scsi_mq) (srb_t *); 3042 int (*abort_isp) (struct scsi_qla_host *); 3043 int (*iospace_config)(struct qla_hw_data*); 3044 int (*initialize_adapter)(struct scsi_qla_host *); 3045 }; 3046 3047 /* MSI-X Support *************************************************************/ 3048 3049 #define QLA_MSIX_CHIP_REV_24XX 3 3050 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3051 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3052 3053 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3054 #define QLA_MSIX_RSP_Q 0x01 3055 #define QLA_ATIO_VECTOR 0x02 3056 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3057 3058 #define QLA_MIDX_DEFAULT 0 3059 #define QLA_MIDX_RSP_Q 1 3060 #define QLA_PCI_MSIX_CONTROL 0xa2 3061 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3062 3063 struct scsi_qla_host; 3064 3065 3066 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3067 3068 struct qla_msix_entry { 3069 int have_irq; 3070 int in_use; 3071 uint32_t vector; 3072 uint16_t entry; 3073 char name[30]; 3074 void *handle; 3075 int cpuid; 3076 }; 3077 3078 #define WATCH_INTERVAL 1 /* number of seconds */ 3079 3080 /* Work events. */ 3081 enum qla_work_type { 3082 QLA_EVT_AEN, 3083 QLA_EVT_IDC_ACK, 3084 QLA_EVT_ASYNC_LOGIN, 3085 QLA_EVT_ASYNC_LOGOUT, 3086 QLA_EVT_ASYNC_LOGOUT_DONE, 3087 QLA_EVT_ASYNC_ADISC, 3088 QLA_EVT_ASYNC_ADISC_DONE, 3089 QLA_EVT_UEVENT, 3090 QLA_EVT_AENFX, 3091 QLA_EVT_GIDPN, 3092 QLA_EVT_GPNID, 3093 QLA_EVT_GPNID_DONE, 3094 QLA_EVT_NEW_SESS, 3095 QLA_EVT_GPDB, 3096 QLA_EVT_PRLI, 3097 QLA_EVT_GPSC, 3098 QLA_EVT_UPD_FCPORT, 3099 QLA_EVT_GNL, 3100 QLA_EVT_NACK, 3101 }; 3102 3103 3104 struct qla_work_evt { 3105 struct list_head list; 3106 enum qla_work_type type; 3107 u32 flags; 3108 #define QLA_EVT_FLAG_FREE 0x1 3109 3110 union { 3111 struct { 3112 enum fc_host_event_code code; 3113 u32 data; 3114 } aen; 3115 struct { 3116 #define QLA_IDC_ACK_REGS 7 3117 uint16_t mb[QLA_IDC_ACK_REGS]; 3118 } idc_ack; 3119 struct { 3120 struct fc_port *fcport; 3121 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3122 u16 data[2]; 3123 } logio; 3124 struct { 3125 u32 code; 3126 #define QLA_UEVENT_CODE_FW_DUMP 0 3127 } uevent; 3128 struct { 3129 uint32_t evtcode; 3130 uint32_t mbx[8]; 3131 uint32_t count; 3132 } aenfx; 3133 struct { 3134 srb_t *sp; 3135 } iosb; 3136 struct { 3137 port_id_t id; 3138 } gpnid; 3139 struct { 3140 port_id_t id; 3141 u8 port_name[8]; 3142 void *pla; 3143 } new_sess; 3144 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */ 3145 fc_port_t *fcport; 3146 u8 opt; 3147 } fcport; 3148 struct { 3149 fc_port_t *fcport; 3150 u8 iocb[IOCB_SIZE]; 3151 int type; 3152 } nack; 3153 } u; 3154 }; 3155 3156 struct qla_chip_state_84xx { 3157 struct list_head list; 3158 struct kref kref; 3159 3160 void *bus; 3161 spinlock_t access_lock; 3162 struct mutex fw_update_mutex; 3163 uint32_t fw_update; 3164 uint32_t op_fw_version; 3165 uint32_t op_fw_size; 3166 uint32_t op_fw_seq_size; 3167 uint32_t diag_fw_version; 3168 uint32_t gold_fw_version; 3169 }; 3170 3171 struct qla_dif_statistics { 3172 uint64_t dif_input_bytes; 3173 uint64_t dif_output_bytes; 3174 uint64_t dif_input_requests; 3175 uint64_t dif_output_requests; 3176 uint32_t dif_guard_err; 3177 uint32_t dif_ref_tag_err; 3178 uint32_t dif_app_tag_err; 3179 }; 3180 3181 struct qla_statistics { 3182 uint32_t total_isp_aborts; 3183 uint64_t input_bytes; 3184 uint64_t output_bytes; 3185 uint64_t input_requests; 3186 uint64_t output_requests; 3187 uint32_t control_requests; 3188 3189 uint64_t jiffies_at_last_reset; 3190 uint32_t stat_max_pend_cmds; 3191 uint32_t stat_max_qfull_cmds_alloc; 3192 uint32_t stat_max_qfull_cmds_dropped; 3193 3194 struct qla_dif_statistics qla_dif_stats; 3195 }; 3196 3197 struct bidi_statistics { 3198 unsigned long long io_count; 3199 unsigned long long transfer_bytes; 3200 }; 3201 3202 struct qla_tc_param { 3203 struct scsi_qla_host *vha; 3204 uint32_t blk_sz; 3205 uint32_t bufflen; 3206 struct scatterlist *sg; 3207 struct scatterlist *prot_sg; 3208 struct crc_context *ctx; 3209 uint8_t *ctx_dsd_alloced; 3210 }; 3211 3212 /* Multi queue support */ 3213 #define MBC_INITIALIZE_MULTIQ 0x1f 3214 #define QLA_QUE_PAGE 0X1000 3215 #define QLA_MQ_SIZE 32 3216 #define QLA_MAX_QUEUES 256 3217 #define ISP_QUE_REG(ha, id) \ 3218 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \ 3219 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3220 ((void __iomem *)ha->iobase)) 3221 #define QLA_REQ_QUE_ID(tag) \ 3222 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3223 #define QLA_DEFAULT_QUE_QOS 5 3224 #define QLA_PRECONFIG_VPORTS 32 3225 #define QLA_MAX_VPORTS_QLA24XX 128 3226 #define QLA_MAX_VPORTS_QLA25XX 256 3227 3228 struct qla_tgt_counters { 3229 uint64_t qla_core_sbt_cmd; 3230 uint64_t core_qla_que_buf; 3231 uint64_t qla_core_ret_ctio; 3232 uint64_t core_qla_snd_status; 3233 uint64_t qla_core_ret_sta_ctio; 3234 uint64_t core_qla_free_cmd; 3235 uint64_t num_q_full_sent; 3236 uint64_t num_alloc_iocb_failed; 3237 uint64_t num_term_xchg_sent; 3238 }; 3239 3240 struct qla_qpair; 3241 3242 /* Response queue data structure */ 3243 struct rsp_que { 3244 dma_addr_t dma; 3245 response_t *ring; 3246 response_t *ring_ptr; 3247 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 3248 uint32_t __iomem *rsp_q_out; 3249 uint16_t ring_index; 3250 uint16_t out_ptr; 3251 uint16_t *in_ptr; /* queue shadow in index */ 3252 uint16_t length; 3253 uint16_t options; 3254 uint16_t rid; 3255 uint16_t id; 3256 uint16_t vp_idx; 3257 struct qla_hw_data *hw; 3258 struct qla_msix_entry *msix; 3259 struct req_que *req; 3260 srb_t *status_srb; /* status continuation entry */ 3261 struct qla_qpair *qpair; 3262 3263 dma_addr_t dma_fx00; 3264 response_t *ring_fx00; 3265 uint16_t length_fx00; 3266 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3267 }; 3268 3269 /* Request queue data structure */ 3270 struct req_que { 3271 dma_addr_t dma; 3272 request_t *ring; 3273 request_t *ring_ptr; 3274 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 3275 uint32_t __iomem *req_q_out; 3276 uint16_t ring_index; 3277 uint16_t in_ptr; 3278 uint16_t *out_ptr; /* queue shadow out index */ 3279 uint16_t cnt; 3280 uint16_t length; 3281 uint16_t options; 3282 uint16_t rid; 3283 uint16_t id; 3284 uint16_t qos; 3285 uint16_t vp_idx; 3286 struct rsp_que *rsp; 3287 srb_t **outstanding_cmds; 3288 uint32_t current_outstanding_cmd; 3289 uint16_t num_outstanding_cmds; 3290 int max_q_depth; 3291 3292 dma_addr_t dma_fx00; 3293 request_t *ring_fx00; 3294 uint16_t length_fx00; 3295 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3296 }; 3297 3298 /*Queue pair data structure */ 3299 struct qla_qpair { 3300 spinlock_t qp_lock; 3301 atomic_t ref_count; 3302 uint32_t lun_cnt; 3303 /* 3304 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3305 * legacy code. For other Qpair(s), it will point at qp_lock. 3306 */ 3307 spinlock_t *qp_lock_ptr; 3308 struct scsi_qla_host *vha; 3309 u32 chip_reset; 3310 3311 /* distill these fields down to 'online=0/1' 3312 * ha->flags.eeh_busy 3313 * ha->flags.pci_channel_io_perm_failure 3314 * base_vha->loop_state 3315 */ 3316 uint32_t online:1; 3317 /* move vha->flags.difdix_supported here */ 3318 uint32_t difdix_supported:1; 3319 uint32_t delete_in_progress:1; 3320 uint32_t fw_started:1; 3321 uint32_t enable_class_2:1; 3322 uint32_t enable_explicit_conf:1; 3323 uint32_t use_shadow_reg:1; 3324 3325 uint16_t id; /* qp number used with FW */ 3326 uint16_t vp_idx; /* vport ID */ 3327 mempool_t *srb_mempool; 3328 3329 struct pci_dev *pdev; 3330 void (*reqq_start_iocbs)(struct qla_qpair *); 3331 3332 /* to do: New driver: move queues to here instead of pointers */ 3333 struct req_que *req; 3334 struct rsp_que *rsp; 3335 struct atio_que *atio; 3336 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3337 struct qla_hw_data *hw; 3338 struct work_struct q_work; 3339 struct list_head qp_list_elem; /* vha->qp_list */ 3340 struct list_head hints_list; 3341 uint16_t cpuid; 3342 struct qla_tgt_counters tgt_counters; 3343 }; 3344 3345 /* Place holder for FW buffer parameters */ 3346 struct qlfc_fw { 3347 void *fw_buf; 3348 dma_addr_t fw_dma; 3349 uint32_t len; 3350 }; 3351 3352 struct scsi_qlt_host { 3353 void *target_lport_ptr; 3354 struct mutex tgt_mutex; 3355 struct mutex tgt_host_action_mutex; 3356 struct qla_tgt *qla_tgt; 3357 }; 3358 3359 struct qlt_hw_data { 3360 /* Protected by hw lock */ 3361 uint32_t node_name_set:1; 3362 3363 dma_addr_t atio_dma; /* Physical address. */ 3364 struct atio *atio_ring; /* Base virtual address */ 3365 struct atio *atio_ring_ptr; /* Current address. */ 3366 uint16_t atio_ring_index; /* Current index. */ 3367 uint16_t atio_q_length; 3368 uint32_t __iomem *atio_q_in; 3369 uint32_t __iomem *atio_q_out; 3370 3371 struct qla_tgt_func_tmpl *tgt_ops; 3372 struct qla_tgt_vp_map *tgt_vp_map; 3373 3374 int saved_set; 3375 uint16_t saved_exchange_count; 3376 uint32_t saved_firmware_options_1; 3377 uint32_t saved_firmware_options_2; 3378 uint32_t saved_firmware_options_3; 3379 uint8_t saved_firmware_options[2]; 3380 uint8_t saved_add_firmware_options[2]; 3381 3382 uint8_t tgt_node_name[WWN_SIZE]; 3383 3384 struct dentry *dfs_tgt_sess; 3385 struct dentry *dfs_tgt_port_database; 3386 struct dentry *dfs_naqp; 3387 3388 struct list_head q_full_list; 3389 uint32_t num_pend_cmds; 3390 uint32_t num_qfull_cmds_alloc; 3391 uint32_t num_qfull_cmds_dropped; 3392 spinlock_t q_full_lock; 3393 uint32_t leak_exchg_thresh_hold; 3394 spinlock_t sess_lock; 3395 int num_act_qpairs; 3396 #define DEFAULT_NAQP 2 3397 spinlock_t atio_lock ____cacheline_aligned; 3398 struct btree_head32 host_map; 3399 }; 3400 3401 #define MAX_QFULL_CMDS_ALLOC 8192 3402 #define Q_FULL_THRESH_HOLD_PERCENT 90 3403 #define Q_FULL_THRESH_HOLD(ha) \ 3404 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3405 3406 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3407 3408 #define QLA_EARLY_LINKUP(_ha) \ 3409 ((_ha->flags.n2n_ae || _ha->flags.lip_ae) && \ 3410 _ha->flags.fw_started && !_ha->flags.fw_init_done) 3411 3412 /* 3413 * Qlogic host adapter specific data structure. 3414 */ 3415 struct qla_hw_data { 3416 struct pci_dev *pdev; 3417 /* SRB cache. */ 3418 #define SRB_MIN_REQ 128 3419 mempool_t *srb_mempool; 3420 3421 volatile struct { 3422 uint32_t mbox_int :1; 3423 uint32_t mbox_busy :1; 3424 uint32_t disable_risc_code_load :1; 3425 uint32_t enable_64bit_addressing :1; 3426 uint32_t enable_lip_reset :1; 3427 uint32_t enable_target_reset :1; 3428 uint32_t enable_lip_full_login :1; 3429 uint32_t enable_led_scheme :1; 3430 3431 uint32_t msi_enabled :1; 3432 uint32_t msix_enabled :1; 3433 uint32_t disable_serdes :1; 3434 uint32_t gpsc_supported :1; 3435 uint32_t npiv_supported :1; 3436 uint32_t pci_channel_io_perm_failure :1; 3437 uint32_t fce_enabled :1; 3438 uint32_t fac_supported :1; 3439 3440 uint32_t chip_reset_done :1; 3441 uint32_t running_gold_fw :1; 3442 uint32_t eeh_busy :1; 3443 uint32_t disable_msix_handshake :1; 3444 uint32_t fcp_prio_enabled :1; 3445 uint32_t isp82xx_fw_hung:1; 3446 uint32_t nic_core_hung:1; 3447 3448 uint32_t quiesce_owner:1; 3449 uint32_t nic_core_reset_hdlr_active:1; 3450 uint32_t nic_core_reset_owner:1; 3451 uint32_t isp82xx_no_md_cap:1; 3452 uint32_t host_shutting_down:1; 3453 uint32_t idc_compl_status:1; 3454 uint32_t mr_reset_hdlr_active:1; 3455 uint32_t mr_intr_valid:1; 3456 3457 uint32_t dport_enabled:1; 3458 uint32_t fawwpn_enabled:1; 3459 uint32_t exlogins_enabled:1; 3460 uint32_t exchoffld_enabled:1; 3461 3462 uint32_t lip_ae:1; 3463 uint32_t n2n_ae:1; 3464 uint32_t fw_started:1; 3465 uint32_t fw_init_done:1; 3466 } flags; 3467 3468 /* This spinlock is used to protect "io transactions", you must 3469 * acquire it before doing any IO to the card, eg with RD_REG*() and 3470 * WRT_REG*() for the duration of your entire commandtransaction. 3471 * 3472 * This spinlock is of lower priority than the io request lock. 3473 */ 3474 3475 spinlock_t hardware_lock ____cacheline_aligned; 3476 int bars; 3477 int mem_only; 3478 device_reg_t *iobase; /* Base I/O address */ 3479 resource_size_t pio_address; 3480 3481 #define MIN_IOBASE_LEN 0x100 3482 dma_addr_t bar0_hdl; 3483 3484 void __iomem *cregbase; 3485 dma_addr_t bar2_hdl; 3486 #define BAR0_LEN_FX00 (1024 * 1024) 3487 #define BAR2_LEN_FX00 (128 * 1024) 3488 3489 uint32_t rqstq_intr_code; 3490 uint32_t mbx_intr_code; 3491 uint32_t req_que_len; 3492 uint32_t rsp_que_len; 3493 uint32_t req_que_off; 3494 uint32_t rsp_que_off; 3495 3496 /* Multi queue data structs */ 3497 device_reg_t *mqiobase; 3498 device_reg_t *msixbase; 3499 uint16_t msix_count; 3500 uint8_t mqenable; 3501 struct req_que **req_q_map; 3502 struct rsp_que **rsp_q_map; 3503 struct qla_qpair **queue_pair_map; 3504 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3505 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3506 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 3507 / sizeof(unsigned long)]; 3508 uint8_t max_req_queues; 3509 uint8_t max_rsp_queues; 3510 uint8_t max_qpairs; 3511 uint8_t num_qpairs; 3512 struct qla_qpair *base_qpair; 3513 struct qla_npiv_entry *npiv_info; 3514 uint16_t nvram_npiv_size; 3515 3516 uint16_t switch_cap; 3517 #define FLOGI_SEQ_DEL BIT_8 3518 #define FLOGI_MID_SUPPORT BIT_10 3519 #define FLOGI_VSAN_SUPPORT BIT_12 3520 #define FLOGI_SP_SUPPORT BIT_13 3521 3522 uint8_t port_no; /* Physical port of adapter */ 3523 uint8_t exch_starvation; 3524 3525 /* Timeout timers. */ 3526 uint8_t loop_down_abort_time; /* port down timer */ 3527 atomic_t loop_down_timer; /* loop down timer */ 3528 uint8_t link_down_timeout; /* link down timeout */ 3529 uint16_t max_loop_id; 3530 uint16_t max_fibre_devices; /* Maximum number of targets */ 3531 3532 uint16_t fb_rev; 3533 uint16_t min_external_loopid; /* First external loop Id */ 3534 3535 #define PORT_SPEED_UNKNOWN 0xFFFF 3536 #define PORT_SPEED_1GB 0x00 3537 #define PORT_SPEED_2GB 0x01 3538 #define PORT_SPEED_4GB 0x03 3539 #define PORT_SPEED_8GB 0x04 3540 #define PORT_SPEED_16GB 0x05 3541 #define PORT_SPEED_32GB 0x06 3542 #define PORT_SPEED_10GB 0x13 3543 uint16_t link_data_rate; /* F/W operating speed */ 3544 3545 uint8_t current_topology; 3546 uint8_t prev_topology; 3547 #define ISP_CFG_NL 1 3548 #define ISP_CFG_N 2 3549 #define ISP_CFG_FL 4 3550 #define ISP_CFG_F 8 3551 3552 uint8_t operating_mode; /* F/W operating mode */ 3553 #define LOOP 0 3554 #define P2P 1 3555 #define LOOP_P2P 2 3556 #define P2P_LOOP 3 3557 uint8_t interrupts_on; 3558 uint32_t isp_abort_cnt; 3559 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 3560 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 3561 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 3562 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 3563 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 3564 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 3565 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 3566 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 3567 3568 uint32_t isp_type; 3569 #define DT_ISP2100 BIT_0 3570 #define DT_ISP2200 BIT_1 3571 #define DT_ISP2300 BIT_2 3572 #define DT_ISP2312 BIT_3 3573 #define DT_ISP2322 BIT_4 3574 #define DT_ISP6312 BIT_5 3575 #define DT_ISP6322 BIT_6 3576 #define DT_ISP2422 BIT_7 3577 #define DT_ISP2432 BIT_8 3578 #define DT_ISP5422 BIT_9 3579 #define DT_ISP5432 BIT_10 3580 #define DT_ISP2532 BIT_11 3581 #define DT_ISP8432 BIT_12 3582 #define DT_ISP8001 BIT_13 3583 #define DT_ISP8021 BIT_14 3584 #define DT_ISP2031 BIT_15 3585 #define DT_ISP8031 BIT_16 3586 #define DT_ISPFX00 BIT_17 3587 #define DT_ISP8044 BIT_18 3588 #define DT_ISP2071 BIT_19 3589 #define DT_ISP2271 BIT_20 3590 #define DT_ISP2261 BIT_21 3591 #define DT_ISP_LAST (DT_ISP2261 << 1) 3592 3593 uint32_t device_type; 3594 #define DT_T10_PI BIT_25 3595 #define DT_IIDMA BIT_26 3596 #define DT_FWI2 BIT_27 3597 #define DT_ZIO_SUPPORTED BIT_28 3598 #define DT_OEM_001 BIT_29 3599 #define DT_ISP2200A BIT_30 3600 #define DT_EXTENDED_IDS BIT_31 3601 3602 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 3603 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 3604 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 3605 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 3606 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 3607 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 3608 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 3609 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 3610 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 3611 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 3612 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 3613 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 3614 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 3615 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 3616 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 3617 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 3618 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 3619 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 3620 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 3621 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 3622 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 3623 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 3624 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 3625 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 3626 3627 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 3628 IS_QLA6312(ha) || IS_QLA6322(ha)) 3629 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 3630 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 3631 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 3632 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 3633 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 3634 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 3635 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 3636 IS_QLA84XX(ha)) 3637 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 3638 IS_QLA8031(ha) || IS_QLA8044(ha)) 3639 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 3640 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 3641 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 3642 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 3643 IS_QLA8044(ha) || IS_QLA27XX(ha)) 3644 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3645 IS_QLA27XX(ha)) 3646 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 3647 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3648 IS_QLA27XX(ha)) 3649 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3650 IS_QLA27XX(ha)) 3651 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 3652 3653 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 3654 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 3655 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 3656 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 3657 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 3658 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 3659 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 3660 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 3661 IS_QLA27XX(ha)) 3662 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) 3663 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 3664 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3665 ((ha)->fw_attributes_ext[0] & BIT_0)) 3666 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3667 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3668 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3669 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3670 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3671 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3672 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3673 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3674 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha)) 3675 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3676 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3677 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 3678 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3679 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 3680 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3681 3682 /* HBA serial number */ 3683 uint8_t serial0; 3684 uint8_t serial1; 3685 uint8_t serial2; 3686 3687 /* NVRAM configuration data */ 3688 #define MAX_NVRAM_SIZE 4096 3689 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 3690 uint16_t nvram_size; 3691 uint16_t nvram_base; 3692 void *nvram; 3693 uint16_t vpd_size; 3694 uint16_t vpd_base; 3695 void *vpd; 3696 3697 uint16_t loop_reset_delay; 3698 uint8_t retry_count; 3699 uint8_t login_timeout; 3700 uint16_t r_a_tov; 3701 int port_down_retry_count; 3702 uint8_t mbx_count; 3703 uint8_t aen_mbx_count; 3704 3705 uint32_t login_retry_count; 3706 /* SNS command interfaces. */ 3707 ms_iocb_entry_t *ms_iocb; 3708 dma_addr_t ms_iocb_dma; 3709 struct ct_sns_pkt *ct_sns; 3710 dma_addr_t ct_sns_dma; 3711 /* SNS command interfaces for 2200. */ 3712 struct sns_cmd_pkt *sns_cmd; 3713 dma_addr_t sns_cmd_dma; 3714 3715 #define SFP_DEV_SIZE 256 3716 #define SFP_BLOCK_SIZE 64 3717 void *sfp_data; 3718 dma_addr_t sfp_data_dma; 3719 3720 #define XGMAC_DATA_SIZE 4096 3721 void *xgmac_data; 3722 dma_addr_t xgmac_data_dma; 3723 3724 #define DCBX_TLV_DATA_SIZE 4096 3725 void *dcbx_tlv; 3726 dma_addr_t dcbx_tlv_dma; 3727 3728 struct task_struct *dpc_thread; 3729 uint8_t dpc_active; /* DPC routine is active */ 3730 3731 dma_addr_t gid_list_dma; 3732 struct gid_list_info *gid_list; 3733 int gid_list_info_size; 3734 3735 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3736 #define DMA_POOL_SIZE 256 3737 struct dma_pool *s_dma_pool; 3738 3739 dma_addr_t init_cb_dma; 3740 init_cb_t *init_cb; 3741 int init_cb_size; 3742 dma_addr_t ex_init_cb_dma; 3743 struct ex_init_cb_81xx *ex_init_cb; 3744 3745 void *async_pd; 3746 dma_addr_t async_pd_dma; 3747 3748 #define ENABLE_EXTENDED_LOGIN BIT_7 3749 3750 /* Extended Logins */ 3751 void *exlogin_buf; 3752 dma_addr_t exlogin_buf_dma; 3753 int exlogin_size; 3754 3755 #define ENABLE_EXCHANGE_OFFLD BIT_2 3756 3757 /* Exchange Offload */ 3758 void *exchoffld_buf; 3759 dma_addr_t exchoffld_buf_dma; 3760 int exchoffld_size; 3761 int exchoffld_count; 3762 3763 void *swl; 3764 3765 /* These are used by mailbox operations. */ 3766 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3767 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 3768 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 3769 3770 mbx_cmd_t *mcp; 3771 struct mbx_cmd_32 *mcp32; 3772 3773 unsigned long mbx_cmd_flags; 3774 #define MBX_INTERRUPT 1 3775 #define MBX_INTR_WAIT 2 3776 #define MBX_UPDATE_FLASH_ACTIVE 3 3777 3778 struct mutex vport_lock; /* Virtual port synchronization */ 3779 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 3780 struct mutex mq_lock; /* multi-queue synchronization */ 3781 struct completion mbx_cmd_comp; /* Serialize mbx access */ 3782 struct completion mbx_intr_comp; /* Used for completion notification */ 3783 struct completion dcbx_comp; /* For set port config notification */ 3784 struct completion lb_portup_comp; /* Used to wait for link up during 3785 * loopback */ 3786 #define DCBX_COMP_TIMEOUT 20 3787 #define LB_PORTUP_COMP_TIMEOUT 10 3788 3789 int notify_dcbx_comp; 3790 int notify_lb_portup_comp; 3791 struct mutex selflogin_lock; 3792 3793 /* Basic firmware related information. */ 3794 uint16_t fw_major_version; 3795 uint16_t fw_minor_version; 3796 uint16_t fw_subminor_version; 3797 uint16_t fw_attributes; 3798 uint16_t fw_attributes_h; 3799 uint16_t fw_attributes_ext[2]; 3800 uint32_t fw_memory_size; 3801 uint32_t fw_transfer_size; 3802 uint32_t fw_srisc_address; 3803 #define RISC_START_ADDRESS_2100 0x1000 3804 #define RISC_START_ADDRESS_2300 0x800 3805 #define RISC_START_ADDRESS_2400 0x100000 3806 3807 uint16_t orig_fw_tgt_xcb_count; 3808 uint16_t cur_fw_tgt_xcb_count; 3809 uint16_t orig_fw_xcb_count; 3810 uint16_t cur_fw_xcb_count; 3811 uint16_t orig_fw_iocb_count; 3812 uint16_t cur_fw_iocb_count; 3813 uint16_t fw_max_fcf_count; 3814 3815 uint32_t fw_shared_ram_start; 3816 uint32_t fw_shared_ram_end; 3817 uint32_t fw_ddr_ram_start; 3818 uint32_t fw_ddr_ram_end; 3819 3820 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 3821 uint8_t fw_seriallink_options[4]; 3822 uint16_t fw_seriallink_options24[4]; 3823 3824 uint8_t mpi_version[3]; 3825 uint32_t mpi_capabilities; 3826 uint8_t phy_version[3]; 3827 uint8_t pep_version[3]; 3828 3829 /* Firmware dump template */ 3830 void *fw_dump_template; 3831 uint32_t fw_dump_template_len; 3832 /* Firmware dump information. */ 3833 struct qla2xxx_fw_dump *fw_dump; 3834 uint32_t fw_dump_len; 3835 int fw_dumped; 3836 unsigned long fw_dump_cap_flags; 3837 #define RISC_PAUSE_CMPL 0 3838 #define DMA_SHUTDOWN_CMPL 1 3839 #define ISP_RESET_CMPL 2 3840 #define RISC_RDY_AFT_RESET 3 3841 #define RISC_SRAM_DUMP_CMPL 4 3842 #define RISC_EXT_MEM_DUMP_CMPL 5 3843 #define ISP_MBX_RDY 6 3844 #define ISP_SOFT_RESET_CMPL 7 3845 int fw_dump_reading; 3846 int prev_minidump_failed; 3847 dma_addr_t eft_dma; 3848 void *eft; 3849 /* Current size of mctp dump is 0x086064 bytes */ 3850 #define MCTP_DUMP_SIZE 0x086064 3851 dma_addr_t mctp_dump_dma; 3852 void *mctp_dump; 3853 int mctp_dumped; 3854 int mctp_dump_reading; 3855 uint32_t chain_offset; 3856 struct dentry *dfs_dir; 3857 struct dentry *dfs_fce; 3858 struct dentry *dfs_tgt_counters; 3859 struct dentry *dfs_fw_resource_cnt; 3860 3861 dma_addr_t fce_dma; 3862 void *fce; 3863 uint32_t fce_bufs; 3864 uint16_t fce_mb[8]; 3865 uint64_t fce_wr, fce_rd; 3866 struct mutex fce_mutex; 3867 3868 uint32_t pci_attr; 3869 uint16_t chip_revision; 3870 3871 uint16_t product_id[4]; 3872 3873 uint8_t model_number[16+1]; 3874 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 3875 char model_desc[80]; 3876 uint8_t adapter_id[16+1]; 3877 3878 /* Option ROM information. */ 3879 char *optrom_buffer; 3880 uint32_t optrom_size; 3881 int optrom_state; 3882 #define QLA_SWAITING 0 3883 #define QLA_SREADING 1 3884 #define QLA_SWRITING 2 3885 uint32_t optrom_region_start; 3886 uint32_t optrom_region_size; 3887 struct mutex optrom_mutex; 3888 3889 /* PCI expansion ROM image information. */ 3890 #define ROM_CODE_TYPE_BIOS 0 3891 #define ROM_CODE_TYPE_FCODE 1 3892 #define ROM_CODE_TYPE_EFI 3 3893 uint8_t bios_revision[2]; 3894 uint8_t efi_revision[2]; 3895 uint8_t fcode_revision[16]; 3896 uint32_t fw_revision[4]; 3897 3898 uint32_t gold_fw_version[4]; 3899 3900 /* Offsets for flash/nvram access (set to ~0 if not used). */ 3901 uint32_t flash_conf_off; 3902 uint32_t flash_data_off; 3903 uint32_t nvram_conf_off; 3904 uint32_t nvram_data_off; 3905 3906 uint32_t fdt_wrt_disable; 3907 uint32_t fdt_wrt_enable; 3908 uint32_t fdt_erase_cmd; 3909 uint32_t fdt_block_size; 3910 uint32_t fdt_unprotect_sec_cmd; 3911 uint32_t fdt_protect_sec_cmd; 3912 uint32_t fdt_wrt_sts_reg_cmd; 3913 3914 uint32_t flt_region_flt; 3915 uint32_t flt_region_fdt; 3916 uint32_t flt_region_boot; 3917 uint32_t flt_region_boot_sec; 3918 uint32_t flt_region_fw; 3919 uint32_t flt_region_fw_sec; 3920 uint32_t flt_region_vpd_nvram; 3921 uint32_t flt_region_vpd; 3922 uint32_t flt_region_vpd_sec; 3923 uint32_t flt_region_nvram; 3924 uint32_t flt_region_npiv_conf; 3925 uint32_t flt_region_gold_fw; 3926 uint32_t flt_region_fcp_prio; 3927 uint32_t flt_region_bootload; 3928 uint32_t flt_region_img_status_pri; 3929 uint32_t flt_region_img_status_sec; 3930 uint8_t active_image; 3931 3932 /* Needed for BEACON */ 3933 uint16_t beacon_blink_led; 3934 uint8_t beacon_color_state; 3935 #define QLA_LED_GRN_ON 0x01 3936 #define QLA_LED_YLW_ON 0x02 3937 #define QLA_LED_ABR_ON 0x04 3938 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 3939 /* ISP2322: red, green, amber. */ 3940 uint16_t zio_mode; 3941 uint16_t zio_timer; 3942 3943 struct qla_msix_entry *msix_entries; 3944 3945 struct list_head vp_list; /* list of VP */ 3946 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 3947 sizeof(unsigned long)]; 3948 uint16_t num_vhosts; /* number of vports created */ 3949 uint16_t num_vsans; /* number of vsan created */ 3950 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 3951 int cur_vport_count; 3952 3953 struct qla_chip_state_84xx *cs84xx; 3954 struct isp_operations *isp_ops; 3955 struct workqueue_struct *wq; 3956 struct qlfc_fw fw_buf; 3957 3958 /* FCP_CMND priority support */ 3959 struct qla_fcp_prio_cfg *fcp_prio_cfg; 3960 3961 struct dma_pool *dl_dma_pool; 3962 #define DSD_LIST_DMA_POOL_SIZE 512 3963 3964 struct dma_pool *fcp_cmnd_dma_pool; 3965 mempool_t *ctx_mempool; 3966 #define FCP_CMND_DMA_POOL_SIZE 512 3967 3968 void __iomem *nx_pcibase; /* Base I/O address */ 3969 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 3970 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 3971 3972 uint32_t crb_win; 3973 uint32_t curr_window; 3974 uint32_t ddr_mn_window; 3975 unsigned long mn_win_crb; 3976 unsigned long ms_win_crb; 3977 int qdr_sn_window; 3978 uint32_t fcoe_dev_init_timeout; 3979 uint32_t fcoe_reset_timeout; 3980 rwlock_t hw_lock; 3981 uint16_t portnum; /* port number */ 3982 int link_width; 3983 struct fw_blob *hablob; 3984 struct qla82xx_legacy_intr_set nx_legacy_intr; 3985 3986 uint16_t gbl_dsd_inuse; 3987 uint16_t gbl_dsd_avail; 3988 struct list_head gbl_dsd_list; 3989 #define NUM_DSD_CHAIN 4096 3990 3991 uint8_t fw_type; 3992 __le32 file_prd_off; /* File firmware product offset */ 3993 3994 uint32_t md_template_size; 3995 void *md_tmplt_hdr; 3996 dma_addr_t md_tmplt_hdr_dma; 3997 void *md_dump; 3998 uint32_t md_dump_size; 3999 4000 void *loop_id_map; 4001 4002 /* QLA83XX IDC specific fields */ 4003 uint32_t idc_audit_ts; 4004 uint32_t idc_extend_tmo; 4005 4006 /* DPC low-priority workqueue */ 4007 struct workqueue_struct *dpc_lp_wq; 4008 struct work_struct idc_aen; 4009 /* DPC high-priority workqueue */ 4010 struct workqueue_struct *dpc_hp_wq; 4011 struct work_struct nic_core_reset; 4012 struct work_struct idc_state_handler; 4013 struct work_struct nic_core_unrecoverable; 4014 struct work_struct board_disable; 4015 4016 struct mr_data_fx00 mr; 4017 4018 struct qlt_hw_data tgt; 4019 int allow_cna_fw_dump; 4020 }; 4021 4022 /* 4023 * Qlogic scsi host structure 4024 */ 4025 typedef struct scsi_qla_host { 4026 struct list_head list; 4027 struct list_head vp_fcports; /* list of fcports */ 4028 struct list_head work_list; 4029 spinlock_t work_lock; 4030 struct work_struct iocb_work; 4031 4032 /* Commonly used flags and state information. */ 4033 struct Scsi_Host *host; 4034 unsigned long host_no; 4035 uint8_t host_str[16]; 4036 4037 volatile struct { 4038 uint32_t init_done :1; 4039 uint32_t online :1; 4040 uint32_t reset_active :1; 4041 4042 uint32_t management_server_logged_in :1; 4043 uint32_t process_response_queue :1; 4044 uint32_t difdix_supported:1; 4045 uint32_t delete_progress:1; 4046 4047 uint32_t fw_tgt_reported:1; 4048 uint32_t bbcr_enable:1; 4049 uint32_t qpairs_available:1; 4050 uint32_t qpairs_req_created:1; 4051 uint32_t qpairs_rsp_created:1; 4052 uint32_t nvme_enabled:1; 4053 } flags; 4054 4055 atomic_t loop_state; 4056 #define LOOP_TIMEOUT 1 4057 #define LOOP_DOWN 2 4058 #define LOOP_UP 3 4059 #define LOOP_UPDATE 4 4060 #define LOOP_READY 5 4061 #define LOOP_DEAD 6 4062 4063 unsigned long dpc_flags; 4064 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4065 #define RESET_ACTIVE 1 4066 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4067 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4068 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4069 #define LOOP_RESYNC_ACTIVE 5 4070 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4071 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4072 #define RELOGIN_NEEDED 8 4073 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4074 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4075 #define BEACON_BLINK_NEEDED 11 4076 #define REGISTER_FDMI_NEEDED 12 4077 #define FCPORT_UPDATE_NEEDED 13 4078 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4079 #define UNLOADING 15 4080 #define NPIV_CONFIG_NEEDED 16 4081 #define ISP_UNRECOVERABLE 17 4082 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4083 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4084 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4085 #define FREE_BIT 21 4086 #define PORT_UPDATE_NEEDED 22 4087 #define FX00_RESET_RECOVERY 23 4088 #define FX00_TARGET_SCAN 24 4089 #define FX00_CRITEMP_RECOVERY 25 4090 #define FX00_HOST_INFO_RESEND 26 4091 #define QPAIR_ONLINE_CHECK_NEEDED 27 4092 4093 unsigned long pci_flags; 4094 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4095 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4096 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4097 4098 uint32_t device_flags; 4099 #define SWITCH_FOUND BIT_0 4100 #define DFLG_NO_CABLE BIT_1 4101 #define DFLG_DEV_FAILED BIT_5 4102 4103 /* ISP configuration data. */ 4104 uint16_t loop_id; /* Host adapter loop id */ 4105 uint16_t self_login_loop_id; /* host adapter loop id 4106 * get it on self login 4107 */ 4108 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4109 * no need of allocating it for 4110 * each command 4111 */ 4112 4113 port_id_t d_id; /* Host adapter port id */ 4114 uint8_t marker_needed; 4115 uint16_t mgmt_svr_loop_id; 4116 4117 4118 4119 /* Timeout timers. */ 4120 uint8_t loop_down_abort_time; /* port down timer */ 4121 atomic_t loop_down_timer; /* loop down timer */ 4122 uint8_t link_down_timeout; /* link down timeout */ 4123 4124 uint32_t timer_active; 4125 struct timer_list timer; 4126 4127 uint8_t node_name[WWN_SIZE]; 4128 uint8_t port_name[WWN_SIZE]; 4129 uint8_t fabric_node_name[WWN_SIZE]; 4130 4131 struct nvme_fc_local_port *nvme_local_port; 4132 atomic_t nvme_ref_count; 4133 wait_queue_head_t nvme_waitQ; 4134 struct list_head nvme_rport_list; 4135 atomic_t nvme_active_aen_cnt; 4136 uint16_t nvme_last_rptd_aen; 4137 4138 uint16_t fcoe_vlan_id; 4139 uint16_t fcoe_fcf_idx; 4140 uint8_t fcoe_vn_port_mac[6]; 4141 4142 /* list of commands waiting on workqueue */ 4143 struct list_head qla_cmd_list; 4144 struct list_head qla_sess_op_cmd_list; 4145 struct list_head unknown_atio_list; 4146 spinlock_t cmd_list_lock; 4147 struct delayed_work unknown_atio_work; 4148 4149 /* Counter to detect races between ELS and RSCN events */ 4150 atomic_t generation_tick; 4151 /* Time when global fcport update has been scheduled */ 4152 int total_fcport_update_gen; 4153 /* List of pending LOGOs, protected by tgt_mutex */ 4154 struct list_head logo_list; 4155 /* List of pending PLOGI acks, protected by hw lock */ 4156 struct list_head plogi_ack_list; 4157 4158 struct list_head qp_list; 4159 4160 uint32_t vp_abort_cnt; 4161 4162 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4163 uint16_t vp_idx; /* vport ID */ 4164 struct qla_qpair *qpair; /* base qpair */ 4165 4166 unsigned long vp_flags; 4167 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4168 #define VP_CREATE_NEEDED 1 4169 #define VP_BIND_NEEDED 2 4170 #define VP_DELETE_NEEDED 3 4171 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4172 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4173 atomic_t vp_state; 4174 #define VP_OFFLINE 0 4175 #define VP_ACTIVE 1 4176 #define VP_FAILED 2 4177 // #define VP_DISABLE 3 4178 uint16_t vp_err_state; 4179 uint16_t vp_prev_err_state; 4180 #define VP_ERR_UNKWN 0 4181 #define VP_ERR_PORTDWN 1 4182 #define VP_ERR_FAB_UNSUPPORTED 2 4183 #define VP_ERR_FAB_NORESOURCES 3 4184 #define VP_ERR_FAB_LOGOUT 4 4185 #define VP_ERR_ADAP_NORESOURCES 5 4186 struct qla_hw_data *hw; 4187 struct scsi_qlt_host vha_tgt; 4188 struct req_que *req; 4189 int fw_heartbeat_counter; 4190 int seconds_since_last_heartbeat; 4191 struct fc_host_statistics fc_host_stat; 4192 struct qla_statistics qla_stats; 4193 struct bidi_statistics bidi_stats; 4194 atomic_t vref_count; 4195 struct qla8044_reset_template reset_tmplt; 4196 uint16_t bbcr; 4197 struct name_list_extended gnl; 4198 /* Count of active session/fcport */ 4199 int fcport_count; 4200 wait_queue_head_t fcport_waitQ; 4201 wait_queue_head_t vref_waitq; 4202 } scsi_qla_host_t; 4203 4204 struct qla27xx_image_status { 4205 uint8_t image_status_mask; 4206 uint16_t generation_number; 4207 uint8_t reserved[3]; 4208 uint8_t ver_minor; 4209 uint8_t ver_major; 4210 uint32_t checksum; 4211 uint32_t signature; 4212 } __packed; 4213 4214 #define SET_VP_IDX 1 4215 #define SET_AL_PA 2 4216 #define RESET_VP_IDX 3 4217 #define RESET_AL_PA 4 4218 struct qla_tgt_vp_map { 4219 uint8_t idx; 4220 scsi_qla_host_t *vha; 4221 }; 4222 4223 struct qla2_sgx { 4224 dma_addr_t dma_addr; /* OUT */ 4225 uint32_t dma_len; /* OUT */ 4226 4227 uint32_t tot_bytes; /* IN */ 4228 struct scatterlist *cur_sg; /* IN */ 4229 4230 /* for book keeping, bzero on initial invocation */ 4231 uint32_t bytes_consumed; 4232 uint32_t num_bytes; 4233 uint32_t tot_partial; 4234 4235 /* for debugging */ 4236 uint32_t num_sg; 4237 srb_t *sp; 4238 }; 4239 4240 #define QLA_FW_STARTED(_ha) { \ 4241 int i; \ 4242 _ha->flags.fw_started = 1; \ 4243 _ha->base_qpair->fw_started = 1; \ 4244 for (i = 0; i < _ha->max_qpairs; i++) { \ 4245 if (_ha->queue_pair_map[i]) \ 4246 _ha->queue_pair_map[i]->fw_started = 1; \ 4247 } \ 4248 } 4249 4250 #define QLA_FW_STOPPED(_ha) { \ 4251 int i; \ 4252 _ha->flags.fw_started = 0; \ 4253 _ha->base_qpair->fw_started = 0; \ 4254 for (i = 0; i < _ha->max_qpairs; i++) { \ 4255 if (_ha->queue_pair_map[i]) \ 4256 _ha->queue_pair_map[i]->fw_started = 0; \ 4257 } \ 4258 } 4259 4260 /* 4261 * Macros to help code, maintain, etc. 4262 */ 4263 #define LOOP_TRANSITION(ha) \ 4264 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4265 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 4266 atomic_read(&ha->loop_state) == LOOP_DOWN) 4267 4268 #define STATE_TRANSITION(ha) \ 4269 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4270 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 4271 4272 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 4273 atomic_inc(&__vha->vref_count); \ 4274 mb(); \ 4275 if (__vha->flags.delete_progress) { \ 4276 atomic_dec(&__vha->vref_count); \ 4277 wake_up(&__vha->vref_waitq); \ 4278 __bail = 1; \ 4279 } else { \ 4280 __bail = 0; \ 4281 } \ 4282 } while (0) 4283 4284 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 4285 atomic_dec(&__vha->vref_count); \ 4286 wake_up(&__vha->vref_waitq); \ 4287 } while (0) \ 4288 4289 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 4290 atomic_inc(&__qpair->ref_count); \ 4291 mb(); \ 4292 if (__qpair->delete_in_progress) { \ 4293 atomic_dec(&__qpair->ref_count); \ 4294 __bail = 1; \ 4295 } else { \ 4296 __bail = 0; \ 4297 } \ 4298 } while (0) 4299 4300 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 4301 atomic_dec(&__qpair->ref_count); \ 4302 4303 4304 #define QLA_ENA_CONF(_ha) {\ 4305 int i;\ 4306 _ha->base_qpair->enable_explicit_conf = 1; \ 4307 for (i = 0; i < _ha->max_qpairs; i++) { \ 4308 if (_ha->queue_pair_map[i]) \ 4309 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 4310 } \ 4311 } 4312 4313 #define QLA_DIS_CONF(_ha) {\ 4314 int i;\ 4315 _ha->base_qpair->enable_explicit_conf = 0; \ 4316 for (i = 0; i < _ha->max_qpairs; i++) { \ 4317 if (_ha->queue_pair_map[i]) \ 4318 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 4319 } \ 4320 } 4321 4322 /* 4323 * qla2x00 local function return status codes 4324 */ 4325 #define MBS_MASK 0x3fff 4326 4327 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 4328 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 4329 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 4330 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 4331 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 4332 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 4333 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 4334 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 4335 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 4336 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 4337 4338 #define QLA_FUNCTION_TIMEOUT 0x100 4339 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 4340 #define QLA_FUNCTION_FAILED 0x102 4341 #define QLA_MEMORY_ALLOC_FAILED 0x103 4342 #define QLA_LOCK_TIMEOUT 0x104 4343 #define QLA_ABORTED 0x105 4344 #define QLA_SUSPENDED 0x106 4345 #define QLA_BUSY 0x107 4346 #define QLA_ALREADY_REGISTERED 0x109 4347 4348 #define NVRAM_DELAY() udelay(10) 4349 4350 /* 4351 * Flash support definitions 4352 */ 4353 #define OPTROM_SIZE_2300 0x20000 4354 #define OPTROM_SIZE_2322 0x100000 4355 #define OPTROM_SIZE_24XX 0x100000 4356 #define OPTROM_SIZE_25XX 0x200000 4357 #define OPTROM_SIZE_81XX 0x400000 4358 #define OPTROM_SIZE_82XX 0x800000 4359 #define OPTROM_SIZE_83XX 0x1000000 4360 4361 #define OPTROM_BURST_SIZE 0x1000 4362 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 4363 4364 #define QLA_DSDS_PER_IOCB 37 4365 4366 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 4367 4368 #define QLA_SG_ALL 1024 4369 4370 enum nexus_wait_type { 4371 WAIT_HOST = 0, 4372 WAIT_TARGET, 4373 WAIT_LUN, 4374 }; 4375 4376 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 4377 (IS_QLA27XX(_ha) || IS_QLA83XX(_ha))) 4378 4379 #include "qla_target.h" 4380 #include "qla_gbl.h" 4381 #include "qla_dbg.h" 4382 #include "qla_inline.h" 4383 #endif 4384