1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 #include <scsi/scsi_bsg_fc.h> 35 36 #include "qla_bsg.h" 37 #include "qla_nx.h" 38 #include "qla_nx2.h" 39 #define QLA2XXX_DRIVER_NAME "qla2xxx" 40 #define QLA2XXX_APIDEV "ql2xapidev" 41 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 42 43 /* 44 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 45 * but that's fine as we don't look at the last 24 ones for 46 * ISP2100 HBAs. 47 */ 48 #define MAILBOX_REGISTER_COUNT_2100 8 49 #define MAILBOX_REGISTER_COUNT_2200 24 50 #define MAILBOX_REGISTER_COUNT 32 51 52 #define QLA2200A_RISC_ROM_VER 4 53 #define FPM_2300 6 54 #define FPM_2310 7 55 56 #include "qla_settings.h" 57 58 /* 59 * Data bit definitions 60 */ 61 #define BIT_0 0x1 62 #define BIT_1 0x2 63 #define BIT_2 0x4 64 #define BIT_3 0x8 65 #define BIT_4 0x10 66 #define BIT_5 0x20 67 #define BIT_6 0x40 68 #define BIT_7 0x80 69 #define BIT_8 0x100 70 #define BIT_9 0x200 71 #define BIT_10 0x400 72 #define BIT_11 0x800 73 #define BIT_12 0x1000 74 #define BIT_13 0x2000 75 #define BIT_14 0x4000 76 #define BIT_15 0x8000 77 #define BIT_16 0x10000 78 #define BIT_17 0x20000 79 #define BIT_18 0x40000 80 #define BIT_19 0x80000 81 #define BIT_20 0x100000 82 #define BIT_21 0x200000 83 #define BIT_22 0x400000 84 #define BIT_23 0x800000 85 #define BIT_24 0x1000000 86 #define BIT_25 0x2000000 87 #define BIT_26 0x4000000 88 #define BIT_27 0x8000000 89 #define BIT_28 0x10000000 90 #define BIT_29 0x20000000 91 #define BIT_30 0x40000000 92 #define BIT_31 0x80000000 93 94 #define LSB(x) ((uint8_t)(x)) 95 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 96 97 #define LSW(x) ((uint16_t)(x)) 98 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 99 100 #define LSD(x) ((uint32_t)((uint64_t)(x))) 101 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 102 103 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 104 105 /* 106 * I/O register 107 */ 108 109 #define RD_REG_BYTE(addr) readb(addr) 110 #define RD_REG_WORD(addr) readw(addr) 111 #define RD_REG_DWORD(addr) readl(addr) 112 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 113 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 114 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 115 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 116 #define WRT_REG_WORD(addr, data) writew(data,addr) 117 #define WRT_REG_DWORD(addr, data) writel(data,addr) 118 119 /* 120 * ISP83XX specific remote register addresses 121 */ 122 #define QLA83XX_LED_PORT0 0x00201320 123 #define QLA83XX_LED_PORT1 0x00201328 124 #define QLA83XX_IDC_DEV_STATE 0x22102384 125 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 126 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 127 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 128 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 129 #define QLA83XX_IDC_CONTROL 0x22102390 130 #define QLA83XX_IDC_AUDIT 0x22102394 131 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 132 #define QLA83XX_DRIVER_LOCKID 0x22102104 133 #define QLA83XX_DRIVER_LOCK 0x8111c028 134 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 135 #define QLA83XX_FLASH_LOCKID 0x22102100 136 #define QLA83XX_FLASH_LOCK 0x8111c010 137 #define QLA83XX_FLASH_UNLOCK 0x8111c014 138 #define QLA83XX_DEV_PARTINFO1 0x221023e0 139 #define QLA83XX_DEV_PARTINFO2 0x221023e4 140 #define QLA83XX_FW_HEARTBEAT 0x221020b0 141 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 142 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 143 144 /* 83XX: Macros defining 8200 AEN Reason codes */ 145 #define IDC_DEVICE_STATE_CHANGE BIT_0 146 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 147 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 148 #define IDC_HEARTBEAT_FAILURE BIT_3 149 150 /* 83XX: Macros defining 8200 AEN Error-levels */ 151 #define ERR_LEVEL_NON_FATAL 0x1 152 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 153 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 154 155 /* 83XX: Macros for IDC Version */ 156 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 157 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 158 159 /* 83XX: Macros for scheduling dpc tasks */ 160 #define QLA83XX_NIC_CORE_RESET 0x1 161 #define QLA83XX_IDC_STATE_HANDLER 0x2 162 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 163 164 /* 83XX: Macros for defining IDC-Control bits */ 165 #define QLA83XX_IDC_RESET_DISABLED BIT_0 166 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 167 168 /* 83XX: Macros for different timeouts */ 169 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 170 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 171 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 172 173 /* 83XX: Macros for defining class in DEV-Partition Info register */ 174 #define QLA83XX_CLASS_TYPE_NONE 0x0 175 #define QLA83XX_CLASS_TYPE_NIC 0x1 176 #define QLA83XX_CLASS_TYPE_FCOE 0x2 177 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 178 179 /* 83XX: Macros for IDC Lock-Recovery stages */ 180 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 181 * lock-recovery 182 */ 183 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 184 185 /* 83XX: Macros for IDC Audit type */ 186 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 187 * dev-state change to NEED-RESET 188 * or NEED-QUIESCENT 189 */ 190 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 191 * reset-recovery completion is 192 * second 193 */ 194 195 /* 196 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 197 * 133Mhz slot. 198 */ 199 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 200 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 201 202 /* 203 * Fibre Channel device definitions. 204 */ 205 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 206 #define MAX_FIBRE_DEVICES_2100 512 207 #define MAX_FIBRE_DEVICES_2400 2048 208 #define MAX_FIBRE_DEVICES_LOOP 128 209 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 210 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 211 #define MAX_FIBRE_LUNS 0xFFFF 212 #define MAX_HOST_COUNT 16 213 214 /* 215 * Host adapter default definitions. 216 */ 217 #define MAX_BUSES 1 /* We only have one bus today */ 218 #define MIN_LUNS 8 219 #define MAX_LUNS MAX_FIBRE_LUNS 220 #define MAX_CMDS_PER_LUN 255 221 222 /* 223 * Fibre Channel device definitions. 224 */ 225 #define SNS_LAST_LOOP_ID_2100 0xfe 226 #define SNS_LAST_LOOP_ID_2300 0x7ff 227 228 #define LAST_LOCAL_LOOP_ID 0x7d 229 #define SNS_FL_PORT 0x7e 230 #define FABRIC_CONTROLLER 0x7f 231 #define SIMPLE_NAME_SERVER 0x80 232 #define SNS_FIRST_LOOP_ID 0x81 233 #define MANAGEMENT_SERVER 0xfe 234 #define BROADCAST 0xff 235 236 /* 237 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 238 * valid range of an N-PORT id is 0 through 0x7ef. 239 */ 240 #define NPH_LAST_HANDLE 0x7ef 241 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ 242 #define NPH_SNS 0x7fc /* FFFFFC */ 243 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 244 #define NPH_F_PORT 0x7fe /* FFFFFE */ 245 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 246 247 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 248 #include "qla_fw.h" 249 /* 250 * Timeout timer counts in seconds 251 */ 252 #define PORT_RETRY_TIME 1 253 #define LOOP_DOWN_TIMEOUT 60 254 #define LOOP_DOWN_TIME 255 /* 240 */ 255 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 256 257 #define DEFAULT_OUTSTANDING_COMMANDS 1024 258 #define MIN_OUTSTANDING_COMMANDS 128 259 260 /* ISP request and response entry counts (37-65535) */ 261 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 262 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 263 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 264 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 265 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 266 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 267 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 268 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 269 270 struct req_que; 271 272 /* 273 * (sd.h is not exported, hence local inclusion) 274 * Data Integrity Field tuple. 275 */ 276 struct sd_dif_tuple { 277 __be16 guard_tag; /* Checksum */ 278 __be16 app_tag; /* Opaque storage */ 279 __be32 ref_tag; /* Target LBA or indirect LBA */ 280 }; 281 282 /* 283 * SCSI Request Block 284 */ 285 struct srb_cmd { 286 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 287 uint32_t request_sense_length; 288 uint32_t fw_sense_length; 289 uint8_t *request_sense_ptr; 290 void *ctx; 291 }; 292 293 /* 294 * SRB flag definitions 295 */ 296 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 297 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 298 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 299 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 300 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 301 302 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 303 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 304 305 /* 306 * SRB extensions. 307 */ 308 struct srb_iocb { 309 union { 310 struct { 311 uint16_t flags; 312 #define SRB_LOGIN_RETRIED BIT_0 313 #define SRB_LOGIN_COND_PLOGI BIT_1 314 #define SRB_LOGIN_SKIP_PRLI BIT_2 315 uint16_t data[2]; 316 } logio; 317 struct { 318 /* 319 * Values for flags field below are as 320 * defined in tsk_mgmt_entry struct 321 * for control_flags field in qla_fw.h. 322 */ 323 uint32_t flags; 324 uint32_t lun; 325 uint32_t data; 326 struct completion comp; 327 __le16 comp_status; 328 } tmf; 329 struct { 330 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 331 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 332 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 333 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 334 #define FXDISC_TIMEOUT 20 335 uint8_t flags; 336 uint32_t req_len; 337 uint32_t rsp_len; 338 void *req_addr; 339 void *rsp_addr; 340 dma_addr_t req_dma_handle; 341 dma_addr_t rsp_dma_handle; 342 __le32 adapter_id; 343 __le32 adapter_id_hi; 344 __le16 req_func_type; 345 __le32 req_data; 346 __le32 req_data_extra; 347 __le32 result; 348 __le32 seq_number; 349 __le16 fw_flags; 350 struct completion fxiocb_comp; 351 __le32 reserved_0; 352 uint8_t reserved_1; 353 } fxiocb; 354 struct { 355 uint32_t cmd_hndl; 356 __le16 comp_status; 357 struct completion comp; 358 } abt; 359 } u; 360 361 struct timer_list timer; 362 void (*timeout)(void *); 363 }; 364 365 /* Values for srb_ctx type */ 366 #define SRB_LOGIN_CMD 1 367 #define SRB_LOGOUT_CMD 2 368 #define SRB_ELS_CMD_RPT 3 369 #define SRB_ELS_CMD_HST 4 370 #define SRB_CT_CMD 5 371 #define SRB_ADISC_CMD 6 372 #define SRB_TM_CMD 7 373 #define SRB_SCSI_CMD 8 374 #define SRB_BIDI_CMD 9 375 #define SRB_FXIOCB_DCMD 10 376 #define SRB_FXIOCB_BCMD 11 377 #define SRB_ABT_CMD 12 378 379 380 typedef struct srb { 381 atomic_t ref_count; 382 struct fc_port *fcport; 383 uint32_t handle; 384 uint16_t flags; 385 uint16_t type; 386 char *name; 387 int iocbs; 388 union { 389 struct srb_iocb iocb_cmd; 390 struct fc_bsg_job *bsg_job; 391 struct srb_cmd scmd; 392 } u; 393 void (*done)(void *, void *, int); 394 void (*free)(void *, void *); 395 } srb_t; 396 397 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 398 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 399 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 400 401 #define GET_CMD_SENSE_LEN(sp) \ 402 (sp->u.scmd.request_sense_length) 403 #define SET_CMD_SENSE_LEN(sp, len) \ 404 (sp->u.scmd.request_sense_length = len) 405 #define GET_CMD_SENSE_PTR(sp) \ 406 (sp->u.scmd.request_sense_ptr) 407 #define SET_CMD_SENSE_PTR(sp, ptr) \ 408 (sp->u.scmd.request_sense_ptr = ptr) 409 #define GET_FW_SENSE_LEN(sp) \ 410 (sp->u.scmd.fw_sense_length) 411 #define SET_FW_SENSE_LEN(sp, len) \ 412 (sp->u.scmd.fw_sense_length = len) 413 414 struct msg_echo_lb { 415 dma_addr_t send_dma; 416 dma_addr_t rcv_dma; 417 uint16_t req_sg_cnt; 418 uint16_t rsp_sg_cnt; 419 uint16_t options; 420 uint32_t transfer_size; 421 uint32_t iteration_count; 422 }; 423 424 /* 425 * ISP I/O Register Set structure definitions. 426 */ 427 struct device_reg_2xxx { 428 uint16_t flash_address; /* Flash BIOS address */ 429 uint16_t flash_data; /* Flash BIOS data */ 430 uint16_t unused_1[1]; /* Gap */ 431 uint16_t ctrl_status; /* Control/Status */ 432 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 433 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 434 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 435 436 uint16_t ictrl; /* Interrupt control */ 437 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 438 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 439 440 uint16_t istatus; /* Interrupt status */ 441 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 442 443 uint16_t semaphore; /* Semaphore */ 444 uint16_t nvram; /* NVRAM register. */ 445 #define NVR_DESELECT 0 446 #define NVR_BUSY BIT_15 447 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 448 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 449 #define NVR_DATA_IN BIT_3 450 #define NVR_DATA_OUT BIT_2 451 #define NVR_SELECT BIT_1 452 #define NVR_CLOCK BIT_0 453 454 #define NVR_WAIT_CNT 20000 455 456 union { 457 struct { 458 uint16_t mailbox0; 459 uint16_t mailbox1; 460 uint16_t mailbox2; 461 uint16_t mailbox3; 462 uint16_t mailbox4; 463 uint16_t mailbox5; 464 uint16_t mailbox6; 465 uint16_t mailbox7; 466 uint16_t unused_2[59]; /* Gap */ 467 } __attribute__((packed)) isp2100; 468 struct { 469 /* Request Queue */ 470 uint16_t req_q_in; /* In-Pointer */ 471 uint16_t req_q_out; /* Out-Pointer */ 472 /* Response Queue */ 473 uint16_t rsp_q_in; /* In-Pointer */ 474 uint16_t rsp_q_out; /* Out-Pointer */ 475 476 /* RISC to Host Status */ 477 uint32_t host_status; 478 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 479 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 480 481 /* Host to Host Semaphore */ 482 uint16_t host_semaphore; 483 uint16_t unused_3[17]; /* Gap */ 484 uint16_t mailbox0; 485 uint16_t mailbox1; 486 uint16_t mailbox2; 487 uint16_t mailbox3; 488 uint16_t mailbox4; 489 uint16_t mailbox5; 490 uint16_t mailbox6; 491 uint16_t mailbox7; 492 uint16_t mailbox8; 493 uint16_t mailbox9; 494 uint16_t mailbox10; 495 uint16_t mailbox11; 496 uint16_t mailbox12; 497 uint16_t mailbox13; 498 uint16_t mailbox14; 499 uint16_t mailbox15; 500 uint16_t mailbox16; 501 uint16_t mailbox17; 502 uint16_t mailbox18; 503 uint16_t mailbox19; 504 uint16_t mailbox20; 505 uint16_t mailbox21; 506 uint16_t mailbox22; 507 uint16_t mailbox23; 508 uint16_t mailbox24; 509 uint16_t mailbox25; 510 uint16_t mailbox26; 511 uint16_t mailbox27; 512 uint16_t mailbox28; 513 uint16_t mailbox29; 514 uint16_t mailbox30; 515 uint16_t mailbox31; 516 uint16_t fb_cmd; 517 uint16_t unused_4[10]; /* Gap */ 518 } __attribute__((packed)) isp2300; 519 } u; 520 521 uint16_t fpm_diag_config; 522 uint16_t unused_5[0x4]; /* Gap */ 523 uint16_t risc_hw; 524 uint16_t unused_5_1; /* Gap */ 525 uint16_t pcr; /* Processor Control Register. */ 526 uint16_t unused_6[0x5]; /* Gap */ 527 uint16_t mctr; /* Memory Configuration and Timing. */ 528 uint16_t unused_7[0x3]; /* Gap */ 529 uint16_t fb_cmd_2100; /* Unused on 23XX */ 530 uint16_t unused_8[0x3]; /* Gap */ 531 uint16_t hccr; /* Host command & control register. */ 532 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 533 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 534 /* HCCR commands */ 535 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 536 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 537 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 538 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 539 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 540 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 541 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 542 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 543 544 uint16_t unused_9[5]; /* Gap */ 545 uint16_t gpiod; /* GPIO Data register. */ 546 uint16_t gpioe; /* GPIO Enable register. */ 547 #define GPIO_LED_MASK 0x00C0 548 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 549 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 550 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 551 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 552 #define GPIO_LED_ALL_OFF 0x0000 553 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 554 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 555 556 union { 557 struct { 558 uint16_t unused_10[8]; /* Gap */ 559 uint16_t mailbox8; 560 uint16_t mailbox9; 561 uint16_t mailbox10; 562 uint16_t mailbox11; 563 uint16_t mailbox12; 564 uint16_t mailbox13; 565 uint16_t mailbox14; 566 uint16_t mailbox15; 567 uint16_t mailbox16; 568 uint16_t mailbox17; 569 uint16_t mailbox18; 570 uint16_t mailbox19; 571 uint16_t mailbox20; 572 uint16_t mailbox21; 573 uint16_t mailbox22; 574 uint16_t mailbox23; /* Also probe reg. */ 575 } __attribute__((packed)) isp2200; 576 } u_end; 577 }; 578 579 struct device_reg_25xxmq { 580 uint32_t req_q_in; 581 uint32_t req_q_out; 582 uint32_t rsp_q_in; 583 uint32_t rsp_q_out; 584 uint32_t atio_q_in; 585 uint32_t atio_q_out; 586 }; 587 588 589 struct device_reg_fx00 { 590 uint32_t mailbox0; /* 00 */ 591 uint32_t mailbox1; /* 04 */ 592 uint32_t mailbox2; /* 08 */ 593 uint32_t mailbox3; /* 0C */ 594 uint32_t mailbox4; /* 10 */ 595 uint32_t mailbox5; /* 14 */ 596 uint32_t mailbox6; /* 18 */ 597 uint32_t mailbox7; /* 1C */ 598 uint32_t mailbox8; /* 20 */ 599 uint32_t mailbox9; /* 24 */ 600 uint32_t mailbox10; /* 28 */ 601 uint32_t mailbox11; 602 uint32_t mailbox12; 603 uint32_t mailbox13; 604 uint32_t mailbox14; 605 uint32_t mailbox15; 606 uint32_t mailbox16; 607 uint32_t mailbox17; 608 uint32_t mailbox18; 609 uint32_t mailbox19; 610 uint32_t mailbox20; 611 uint32_t mailbox21; 612 uint32_t mailbox22; 613 uint32_t mailbox23; 614 uint32_t mailbox24; 615 uint32_t mailbox25; 616 uint32_t mailbox26; 617 uint32_t mailbox27; 618 uint32_t mailbox28; 619 uint32_t mailbox29; 620 uint32_t mailbox30; 621 uint32_t mailbox31; 622 uint32_t aenmailbox0; 623 uint32_t aenmailbox1; 624 uint32_t aenmailbox2; 625 uint32_t aenmailbox3; 626 uint32_t aenmailbox4; 627 uint32_t aenmailbox5; 628 uint32_t aenmailbox6; 629 uint32_t aenmailbox7; 630 /* Request Queue. */ 631 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 632 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 633 /* Response Queue. */ 634 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 635 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 636 /* Init values shadowed on FW Up Event */ 637 uint32_t initval0; /* B0 */ 638 uint32_t initval1; /* B4 */ 639 uint32_t initval2; /* B8 */ 640 uint32_t initval3; /* BC */ 641 uint32_t initval4; /* C0 */ 642 uint32_t initval5; /* C4 */ 643 uint32_t initval6; /* C8 */ 644 uint32_t initval7; /* CC */ 645 uint32_t fwheartbeat; /* D0 */ 646 uint32_t pseudoaen; /* D4 */ 647 }; 648 649 650 651 typedef union { 652 struct device_reg_2xxx isp; 653 struct device_reg_24xx isp24; 654 struct device_reg_25xxmq isp25mq; 655 struct device_reg_82xx isp82; 656 struct device_reg_fx00 ispfx00; 657 } device_reg_t; 658 659 #define ISP_REQ_Q_IN(ha, reg) \ 660 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 661 &(reg)->u.isp2100.mailbox4 : \ 662 &(reg)->u.isp2300.req_q_in) 663 #define ISP_REQ_Q_OUT(ha, reg) \ 664 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 665 &(reg)->u.isp2100.mailbox4 : \ 666 &(reg)->u.isp2300.req_q_out) 667 #define ISP_RSP_Q_IN(ha, reg) \ 668 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 669 &(reg)->u.isp2100.mailbox5 : \ 670 &(reg)->u.isp2300.rsp_q_in) 671 #define ISP_RSP_Q_OUT(ha, reg) \ 672 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 673 &(reg)->u.isp2100.mailbox5 : \ 674 &(reg)->u.isp2300.rsp_q_out) 675 676 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 677 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 678 679 #define MAILBOX_REG(ha, reg, num) \ 680 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 681 (num < 8 ? \ 682 &(reg)->u.isp2100.mailbox0 + (num) : \ 683 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 684 &(reg)->u.isp2300.mailbox0 + (num)) 685 #define RD_MAILBOX_REG(ha, reg, num) \ 686 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 687 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 688 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 689 690 #define FB_CMD_REG(ha, reg) \ 691 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 692 &(reg)->fb_cmd_2100 : \ 693 &(reg)->u.isp2300.fb_cmd) 694 #define RD_FB_CMD_REG(ha, reg) \ 695 RD_REG_WORD(FB_CMD_REG(ha, reg)) 696 #define WRT_FB_CMD_REG(ha, reg, data) \ 697 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 698 699 typedef struct { 700 uint32_t out_mb; /* outbound from driver */ 701 uint32_t in_mb; /* Incoming from RISC */ 702 uint16_t mb[MAILBOX_REGISTER_COUNT]; 703 long buf_size; 704 void *bufp; 705 uint32_t tov; 706 uint8_t flags; 707 #define MBX_DMA_IN BIT_0 708 #define MBX_DMA_OUT BIT_1 709 #define IOCTL_CMD BIT_2 710 } mbx_cmd_t; 711 712 struct mbx_cmd_32 { 713 uint32_t out_mb; /* outbound from driver */ 714 uint32_t in_mb; /* Incoming from RISC */ 715 uint32_t mb[MAILBOX_REGISTER_COUNT]; 716 long buf_size; 717 void *bufp; 718 uint32_t tov; 719 uint8_t flags; 720 #define MBX_DMA_IN BIT_0 721 #define MBX_DMA_OUT BIT_1 722 #define IOCTL_CMD BIT_2 723 }; 724 725 726 #define MBX_TOV_SECONDS 30 727 728 /* 729 * ISP product identification definitions in mailboxes after reset. 730 */ 731 #define PROD_ID_1 0x4953 732 #define PROD_ID_2 0x0000 733 #define PROD_ID_2a 0x5020 734 #define PROD_ID_3 0x2020 735 736 /* 737 * ISP mailbox Self-Test status codes 738 */ 739 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 740 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 741 #define MBS_BUSY 4 /* Busy. */ 742 743 /* 744 * ISP mailbox command complete status codes 745 */ 746 #define MBS_COMMAND_COMPLETE 0x4000 747 #define MBS_INVALID_COMMAND 0x4001 748 #define MBS_HOST_INTERFACE_ERROR 0x4002 749 #define MBS_TEST_FAILED 0x4003 750 #define MBS_COMMAND_ERROR 0x4005 751 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 752 #define MBS_PORT_ID_USED 0x4007 753 #define MBS_LOOP_ID_USED 0x4008 754 #define MBS_ALL_IDS_IN_USE 0x4009 755 #define MBS_NOT_LOGGED_IN 0x400A 756 #define MBS_LINK_DOWN_ERROR 0x400B 757 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 758 759 /* 760 * ISP mailbox asynchronous event status codes 761 */ 762 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 763 #define MBA_RESET 0x8001 /* Reset Detected. */ 764 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 765 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 766 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 767 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 768 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 769 /* occurred. */ 770 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 771 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 772 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 773 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 774 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 775 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 776 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 777 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 778 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 779 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 780 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 781 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 782 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 783 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 784 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 785 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 786 /* used. */ 787 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 788 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 789 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 790 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 791 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 792 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 793 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 794 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 795 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 796 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 797 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 798 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 799 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 800 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 801 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 802 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 803 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 804 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 805 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 806 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 807 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 808 Notification */ 809 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 810 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 811 812 /* 83XX FCoE specific */ 813 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 814 815 /* Interrupt type codes */ 816 #define INTR_ROM_MB_SUCCESS 0x1 817 #define INTR_ROM_MB_FAILED 0x2 818 #define INTR_MB_SUCCESS 0x10 819 #define INTR_MB_FAILED 0x11 820 #define INTR_ASYNC_EVENT 0x12 821 #define INTR_RSP_QUE_UPDATE 0x13 822 #define INTR_RSP_QUE_UPDATE_83XX 0x14 823 #define INTR_ATIO_QUE_UPDATE 0x1C 824 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 825 826 /* ISP mailbox loopback echo diagnostic error code */ 827 #define MBS_LB_RESET 0x17 828 /* 829 * Firmware options 1, 2, 3. 830 */ 831 #define FO1_AE_ON_LIPF8 BIT_0 832 #define FO1_AE_ALL_LIP_RESET BIT_1 833 #define FO1_CTIO_RETRY BIT_3 834 #define FO1_DISABLE_LIP_F7_SW BIT_4 835 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 836 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 837 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 838 #define FO1_SET_EMPHASIS_SWING BIT_8 839 #define FO1_AE_AUTO_BYPASS BIT_9 840 #define FO1_ENABLE_PURE_IOCB BIT_10 841 #define FO1_AE_PLOGI_RJT BIT_11 842 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 843 #define FO1_AE_QUEUE_FULL BIT_13 844 845 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 846 #define FO2_REV_LOOPBACK BIT_1 847 848 #define FO3_ENABLE_EMERG_IOCB BIT_0 849 #define FO3_AE_RND_ERROR BIT_1 850 851 /* 24XX additional firmware options */ 852 #define ADD_FO_COUNT 3 853 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 854 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 855 856 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 857 858 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 859 860 /* 861 * ISP mailbox commands 862 */ 863 #define MBC_LOAD_RAM 1 /* Load RAM. */ 864 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 865 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 866 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 867 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 868 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 869 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 870 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 871 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 872 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 873 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 874 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 875 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 876 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 877 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 878 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 879 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 880 #define MBC_RESET 0x18 /* Reset. */ 881 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 882 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 883 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 884 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 885 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 886 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 887 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 888 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 889 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 890 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 891 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 892 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 893 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 894 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 895 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 896 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 897 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 898 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 899 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 900 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 901 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 902 #define MBC_DATA_RATE 0x5d /* Data Rate */ 903 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 904 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 905 /* Initialization Procedure */ 906 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 907 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 908 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 909 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 910 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 911 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 912 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 913 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 914 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 915 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 916 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 917 /* commandd. */ 918 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 919 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 920 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 921 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 922 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 923 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 924 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 925 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 926 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 927 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 928 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 929 930 /* 931 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 932 * should be defined with MBC_MR_* 933 */ 934 #define MBC_MR_DRV_SHUTDOWN 0x6A 935 936 /* 937 * ISP24xx mailbox commands 938 */ 939 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 940 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 941 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 942 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 943 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 944 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 945 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 946 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 947 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 948 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 949 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 950 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 951 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 952 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 953 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 954 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 955 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 956 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 957 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 958 #define MBC_PORT_RESET 0x120 /* Port Reset */ 959 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 960 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 961 962 /* 963 * ISP81xx mailbox commands 964 */ 965 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 966 967 /* Firmware return data sizes */ 968 #define FCAL_MAP_SIZE 128 969 970 /* Mailbox bit definitions for out_mb and in_mb */ 971 #define MBX_31 BIT_31 972 #define MBX_30 BIT_30 973 #define MBX_29 BIT_29 974 #define MBX_28 BIT_28 975 #define MBX_27 BIT_27 976 #define MBX_26 BIT_26 977 #define MBX_25 BIT_25 978 #define MBX_24 BIT_24 979 #define MBX_23 BIT_23 980 #define MBX_22 BIT_22 981 #define MBX_21 BIT_21 982 #define MBX_20 BIT_20 983 #define MBX_19 BIT_19 984 #define MBX_18 BIT_18 985 #define MBX_17 BIT_17 986 #define MBX_16 BIT_16 987 #define MBX_15 BIT_15 988 #define MBX_14 BIT_14 989 #define MBX_13 BIT_13 990 #define MBX_12 BIT_12 991 #define MBX_11 BIT_11 992 #define MBX_10 BIT_10 993 #define MBX_9 BIT_9 994 #define MBX_8 BIT_8 995 #define MBX_7 BIT_7 996 #define MBX_6 BIT_6 997 #define MBX_5 BIT_5 998 #define MBX_4 BIT_4 999 #define MBX_3 BIT_3 1000 #define MBX_2 BIT_2 1001 #define MBX_1 BIT_1 1002 #define MBX_0 BIT_0 1003 1004 #define RNID_TYPE_SET_VERSION 0x9 1005 #define RNID_TYPE_ASIC_TEMP 0xC 1006 1007 /* 1008 * Firmware state codes from get firmware state mailbox command 1009 */ 1010 #define FSTATE_CONFIG_WAIT 0 1011 #define FSTATE_WAIT_AL_PA 1 1012 #define FSTATE_WAIT_LOGIN 2 1013 #define FSTATE_READY 3 1014 #define FSTATE_LOSS_OF_SYNC 4 1015 #define FSTATE_ERROR 5 1016 #define FSTATE_REINIT 6 1017 #define FSTATE_NON_PART 7 1018 1019 #define FSTATE_CONFIG_CORRECT 0 1020 #define FSTATE_P2P_RCV_LIP 1 1021 #define FSTATE_P2P_CHOOSE_LOOP 2 1022 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1023 #define FSTATE_FATAL_ERROR 4 1024 #define FSTATE_LOOP_BACK_CONN 5 1025 1026 /* 1027 * Port Database structure definition 1028 * Little endian except where noted. 1029 */ 1030 #define PORT_DATABASE_SIZE 128 /* bytes */ 1031 typedef struct { 1032 uint8_t options; 1033 uint8_t control; 1034 uint8_t master_state; 1035 uint8_t slave_state; 1036 uint8_t reserved[2]; 1037 uint8_t hard_address; 1038 uint8_t reserved_1; 1039 uint8_t port_id[4]; 1040 uint8_t node_name[WWN_SIZE]; 1041 uint8_t port_name[WWN_SIZE]; 1042 uint16_t execution_throttle; 1043 uint16_t execution_count; 1044 uint8_t reset_count; 1045 uint8_t reserved_2; 1046 uint16_t resource_allocation; 1047 uint16_t current_allocation; 1048 uint16_t queue_head; 1049 uint16_t queue_tail; 1050 uint16_t transmit_execution_list_next; 1051 uint16_t transmit_execution_list_previous; 1052 uint16_t common_features; 1053 uint16_t total_concurrent_sequences; 1054 uint16_t RO_by_information_category; 1055 uint8_t recipient; 1056 uint8_t initiator; 1057 uint16_t receive_data_size; 1058 uint16_t concurrent_sequences; 1059 uint16_t open_sequences_per_exchange; 1060 uint16_t lun_abort_flags; 1061 uint16_t lun_stop_flags; 1062 uint16_t stop_queue_head; 1063 uint16_t stop_queue_tail; 1064 uint16_t port_retry_timer; 1065 uint16_t next_sequence_id; 1066 uint16_t frame_count; 1067 uint16_t PRLI_payload_length; 1068 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1069 /* Bits 15-0 of word 0 */ 1070 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1071 /* Bits 15-0 of word 3 */ 1072 uint16_t loop_id; 1073 uint16_t extended_lun_info_list_pointer; 1074 uint16_t extended_lun_stop_list_pointer; 1075 } port_database_t; 1076 1077 /* 1078 * Port database slave/master states 1079 */ 1080 #define PD_STATE_DISCOVERY 0 1081 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1082 #define PD_STATE_PORT_LOGIN 2 1083 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1084 #define PD_STATE_PROCESS_LOGIN 4 1085 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1086 #define PD_STATE_PORT_LOGGED_IN 6 1087 #define PD_STATE_PORT_UNAVAILABLE 7 1088 #define PD_STATE_PROCESS_LOGOUT 8 1089 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1090 #define PD_STATE_PORT_LOGOUT 10 1091 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1092 1093 1094 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1095 #define QLA_ZIO_DISABLED 0 1096 #define QLA_ZIO_DEFAULT_TIMER 2 1097 1098 /* 1099 * ISP Initialization Control Block. 1100 * Little endian except where noted. 1101 */ 1102 #define ICB_VERSION 1 1103 typedef struct { 1104 uint8_t version; 1105 uint8_t reserved_1; 1106 1107 /* 1108 * LSB BIT 0 = Enable Hard Loop Id 1109 * LSB BIT 1 = Enable Fairness 1110 * LSB BIT 2 = Enable Full-Duplex 1111 * LSB BIT 3 = Enable Fast Posting 1112 * LSB BIT 4 = Enable Target Mode 1113 * LSB BIT 5 = Disable Initiator Mode 1114 * LSB BIT 6 = Enable ADISC 1115 * LSB BIT 7 = Enable Target Inquiry Data 1116 * 1117 * MSB BIT 0 = Enable PDBC Notify 1118 * MSB BIT 1 = Non Participating LIP 1119 * MSB BIT 2 = Descending Loop ID Search 1120 * MSB BIT 3 = Acquire Loop ID in LIPA 1121 * MSB BIT 4 = Stop PortQ on Full Status 1122 * MSB BIT 5 = Full Login after LIP 1123 * MSB BIT 6 = Node Name Option 1124 * MSB BIT 7 = Ext IFWCB enable bit 1125 */ 1126 uint8_t firmware_options[2]; 1127 1128 uint16_t frame_payload_size; 1129 uint16_t max_iocb_allocation; 1130 uint16_t execution_throttle; 1131 uint8_t retry_count; 1132 uint8_t retry_delay; /* unused */ 1133 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1134 uint16_t hard_address; 1135 uint8_t inquiry_data; 1136 uint8_t login_timeout; 1137 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1138 1139 uint16_t request_q_outpointer; 1140 uint16_t response_q_inpointer; 1141 uint16_t request_q_length; 1142 uint16_t response_q_length; 1143 uint32_t request_q_address[2]; 1144 uint32_t response_q_address[2]; 1145 1146 uint16_t lun_enables; 1147 uint8_t command_resource_count; 1148 uint8_t immediate_notify_resource_count; 1149 uint16_t timeout; 1150 uint8_t reserved_2[2]; 1151 1152 /* 1153 * LSB BIT 0 = Timer Operation mode bit 0 1154 * LSB BIT 1 = Timer Operation mode bit 1 1155 * LSB BIT 2 = Timer Operation mode bit 2 1156 * LSB BIT 3 = Timer Operation mode bit 3 1157 * LSB BIT 4 = Init Config Mode bit 0 1158 * LSB BIT 5 = Init Config Mode bit 1 1159 * LSB BIT 6 = Init Config Mode bit 2 1160 * LSB BIT 7 = Enable Non part on LIHA failure 1161 * 1162 * MSB BIT 0 = Enable class 2 1163 * MSB BIT 1 = Enable ACK0 1164 * MSB BIT 2 = 1165 * MSB BIT 3 = 1166 * MSB BIT 4 = FC Tape Enable 1167 * MSB BIT 5 = Enable FC Confirm 1168 * MSB BIT 6 = Enable command queuing in target mode 1169 * MSB BIT 7 = No Logo On Link Down 1170 */ 1171 uint8_t add_firmware_options[2]; 1172 1173 uint8_t response_accumulation_timer; 1174 uint8_t interrupt_delay_timer; 1175 1176 /* 1177 * LSB BIT 0 = Enable Read xfr_rdy 1178 * LSB BIT 1 = Soft ID only 1179 * LSB BIT 2 = 1180 * LSB BIT 3 = 1181 * LSB BIT 4 = FCP RSP Payload [0] 1182 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1183 * LSB BIT 6 = Enable Out-of-Order frame handling 1184 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1185 * 1186 * MSB BIT 0 = Sbus enable - 2300 1187 * MSB BIT 1 = 1188 * MSB BIT 2 = 1189 * MSB BIT 3 = 1190 * MSB BIT 4 = LED mode 1191 * MSB BIT 5 = enable 50 ohm termination 1192 * MSB BIT 6 = Data Rate (2300 only) 1193 * MSB BIT 7 = Data Rate (2300 only) 1194 */ 1195 uint8_t special_options[2]; 1196 1197 uint8_t reserved_3[26]; 1198 } init_cb_t; 1199 1200 1201 struct init_cb_fx { 1202 uint16_t version; 1203 uint16_t reserved_1[13]; 1204 __le16 request_q_outpointer; 1205 __le16 response_q_inpointer; 1206 uint16_t reserved_2[2]; 1207 __le16 response_q_length; 1208 __le16 request_q_length; 1209 uint16_t reserved_3[2]; 1210 __le32 request_q_address[2]; 1211 __le32 response_q_address[2]; 1212 uint16_t reserved_4[4]; 1213 uint8_t response_q_msivec; 1214 uint8_t reserved_5[19]; 1215 uint16_t interrupt_delay_timer; 1216 uint16_t reserved_6; 1217 uint32_t fwoptions1; 1218 uint32_t fwoptions2; 1219 uint32_t fwoptions3; 1220 uint8_t reserved_7[24]; 1221 }; 1222 1223 1224 /* 1225 * Get Link Status mailbox command return buffer. 1226 */ 1227 #define GLSO_SEND_RPS BIT_0 1228 #define GLSO_USE_DID BIT_3 1229 1230 struct link_statistics { 1231 uint32_t link_fail_cnt; 1232 uint32_t loss_sync_cnt; 1233 uint32_t loss_sig_cnt; 1234 uint32_t prim_seq_err_cnt; 1235 uint32_t inval_xmit_word_cnt; 1236 uint32_t inval_crc_cnt; 1237 uint32_t lip_cnt; 1238 uint32_t unused1[0x1a]; 1239 uint32_t tx_frames; 1240 uint32_t rx_frames; 1241 uint32_t discarded_frames; 1242 uint32_t dropped_frames; 1243 uint32_t unused2[1]; 1244 uint32_t nos_rcvd; 1245 }; 1246 1247 /* 1248 * NVRAM Command values. 1249 */ 1250 #define NV_START_BIT BIT_2 1251 #define NV_WRITE_OP (BIT_26+BIT_24) 1252 #define NV_READ_OP (BIT_26+BIT_25) 1253 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1254 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1255 #define NV_DELAY_COUNT 10 1256 1257 /* 1258 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1259 */ 1260 typedef struct { 1261 /* 1262 * NVRAM header 1263 */ 1264 uint8_t id[4]; 1265 uint8_t nvram_version; 1266 uint8_t reserved_0; 1267 1268 /* 1269 * NVRAM RISC parameter block 1270 */ 1271 uint8_t parameter_block_version; 1272 uint8_t reserved_1; 1273 1274 /* 1275 * LSB BIT 0 = Enable Hard Loop Id 1276 * LSB BIT 1 = Enable Fairness 1277 * LSB BIT 2 = Enable Full-Duplex 1278 * LSB BIT 3 = Enable Fast Posting 1279 * LSB BIT 4 = Enable Target Mode 1280 * LSB BIT 5 = Disable Initiator Mode 1281 * LSB BIT 6 = Enable ADISC 1282 * LSB BIT 7 = Enable Target Inquiry Data 1283 * 1284 * MSB BIT 0 = Enable PDBC Notify 1285 * MSB BIT 1 = Non Participating LIP 1286 * MSB BIT 2 = Descending Loop ID Search 1287 * MSB BIT 3 = Acquire Loop ID in LIPA 1288 * MSB BIT 4 = Stop PortQ on Full Status 1289 * MSB BIT 5 = Full Login after LIP 1290 * MSB BIT 6 = Node Name Option 1291 * MSB BIT 7 = Ext IFWCB enable bit 1292 */ 1293 uint8_t firmware_options[2]; 1294 1295 uint16_t frame_payload_size; 1296 uint16_t max_iocb_allocation; 1297 uint16_t execution_throttle; 1298 uint8_t retry_count; 1299 uint8_t retry_delay; /* unused */ 1300 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1301 uint16_t hard_address; 1302 uint8_t inquiry_data; 1303 uint8_t login_timeout; 1304 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1305 1306 /* 1307 * LSB BIT 0 = Timer Operation mode bit 0 1308 * LSB BIT 1 = Timer Operation mode bit 1 1309 * LSB BIT 2 = Timer Operation mode bit 2 1310 * LSB BIT 3 = Timer Operation mode bit 3 1311 * LSB BIT 4 = Init Config Mode bit 0 1312 * LSB BIT 5 = Init Config Mode bit 1 1313 * LSB BIT 6 = Init Config Mode bit 2 1314 * LSB BIT 7 = Enable Non part on LIHA failure 1315 * 1316 * MSB BIT 0 = Enable class 2 1317 * MSB BIT 1 = Enable ACK0 1318 * MSB BIT 2 = 1319 * MSB BIT 3 = 1320 * MSB BIT 4 = FC Tape Enable 1321 * MSB BIT 5 = Enable FC Confirm 1322 * MSB BIT 6 = Enable command queuing in target mode 1323 * MSB BIT 7 = No Logo On Link Down 1324 */ 1325 uint8_t add_firmware_options[2]; 1326 1327 uint8_t response_accumulation_timer; 1328 uint8_t interrupt_delay_timer; 1329 1330 /* 1331 * LSB BIT 0 = Enable Read xfr_rdy 1332 * LSB BIT 1 = Soft ID only 1333 * LSB BIT 2 = 1334 * LSB BIT 3 = 1335 * LSB BIT 4 = FCP RSP Payload [0] 1336 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1337 * LSB BIT 6 = Enable Out-of-Order frame handling 1338 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1339 * 1340 * MSB BIT 0 = Sbus enable - 2300 1341 * MSB BIT 1 = 1342 * MSB BIT 2 = 1343 * MSB BIT 3 = 1344 * MSB BIT 4 = LED mode 1345 * MSB BIT 5 = enable 50 ohm termination 1346 * MSB BIT 6 = Data Rate (2300 only) 1347 * MSB BIT 7 = Data Rate (2300 only) 1348 */ 1349 uint8_t special_options[2]; 1350 1351 /* Reserved for expanded RISC parameter block */ 1352 uint8_t reserved_2[22]; 1353 1354 /* 1355 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1356 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1357 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1358 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1359 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1360 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1361 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1362 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1363 * 1364 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1365 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1366 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1367 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1368 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1369 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1370 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1371 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1372 * 1373 * LSB BIT 0 = Output Swing 1G bit 0 1374 * LSB BIT 1 = Output Swing 1G bit 1 1375 * LSB BIT 2 = Output Swing 1G bit 2 1376 * LSB BIT 3 = Output Emphasis 1G bit 0 1377 * LSB BIT 4 = Output Emphasis 1G bit 1 1378 * LSB BIT 5 = Output Swing 2G bit 0 1379 * LSB BIT 6 = Output Swing 2G bit 1 1380 * LSB BIT 7 = Output Swing 2G bit 2 1381 * 1382 * MSB BIT 0 = Output Emphasis 2G bit 0 1383 * MSB BIT 1 = Output Emphasis 2G bit 1 1384 * MSB BIT 2 = Output Enable 1385 * MSB BIT 3 = 1386 * MSB BIT 4 = 1387 * MSB BIT 5 = 1388 * MSB BIT 6 = 1389 * MSB BIT 7 = 1390 */ 1391 uint8_t seriallink_options[4]; 1392 1393 /* 1394 * NVRAM host parameter block 1395 * 1396 * LSB BIT 0 = Enable spinup delay 1397 * LSB BIT 1 = Disable BIOS 1398 * LSB BIT 2 = Enable Memory Map BIOS 1399 * LSB BIT 3 = Enable Selectable Boot 1400 * LSB BIT 4 = Disable RISC code load 1401 * LSB BIT 5 = Set cache line size 1 1402 * LSB BIT 6 = PCI Parity Disable 1403 * LSB BIT 7 = Enable extended logging 1404 * 1405 * MSB BIT 0 = Enable 64bit addressing 1406 * MSB BIT 1 = Enable lip reset 1407 * MSB BIT 2 = Enable lip full login 1408 * MSB BIT 3 = Enable target reset 1409 * MSB BIT 4 = Enable database storage 1410 * MSB BIT 5 = Enable cache flush read 1411 * MSB BIT 6 = Enable database load 1412 * MSB BIT 7 = Enable alternate WWN 1413 */ 1414 uint8_t host_p[2]; 1415 1416 uint8_t boot_node_name[WWN_SIZE]; 1417 uint8_t boot_lun_number; 1418 uint8_t reset_delay; 1419 uint8_t port_down_retry_count; 1420 uint8_t boot_id_number; 1421 uint16_t max_luns_per_target; 1422 uint8_t fcode_boot_port_name[WWN_SIZE]; 1423 uint8_t alternate_port_name[WWN_SIZE]; 1424 uint8_t alternate_node_name[WWN_SIZE]; 1425 1426 /* 1427 * BIT 0 = Selective Login 1428 * BIT 1 = Alt-Boot Enable 1429 * BIT 2 = 1430 * BIT 3 = Boot Order List 1431 * BIT 4 = 1432 * BIT 5 = Selective LUN 1433 * BIT 6 = 1434 * BIT 7 = unused 1435 */ 1436 uint8_t efi_parameters; 1437 1438 uint8_t link_down_timeout; 1439 1440 uint8_t adapter_id[16]; 1441 1442 uint8_t alt1_boot_node_name[WWN_SIZE]; 1443 uint16_t alt1_boot_lun_number; 1444 uint8_t alt2_boot_node_name[WWN_SIZE]; 1445 uint16_t alt2_boot_lun_number; 1446 uint8_t alt3_boot_node_name[WWN_SIZE]; 1447 uint16_t alt3_boot_lun_number; 1448 uint8_t alt4_boot_node_name[WWN_SIZE]; 1449 uint16_t alt4_boot_lun_number; 1450 uint8_t alt5_boot_node_name[WWN_SIZE]; 1451 uint16_t alt5_boot_lun_number; 1452 uint8_t alt6_boot_node_name[WWN_SIZE]; 1453 uint16_t alt6_boot_lun_number; 1454 uint8_t alt7_boot_node_name[WWN_SIZE]; 1455 uint16_t alt7_boot_lun_number; 1456 1457 uint8_t reserved_3[2]; 1458 1459 /* Offset 200-215 : Model Number */ 1460 uint8_t model_number[16]; 1461 1462 /* OEM related items */ 1463 uint8_t oem_specific[16]; 1464 1465 /* 1466 * NVRAM Adapter Features offset 232-239 1467 * 1468 * LSB BIT 0 = External GBIC 1469 * LSB BIT 1 = Risc RAM parity 1470 * LSB BIT 2 = Buffer Plus Module 1471 * LSB BIT 3 = Multi Chip Adapter 1472 * LSB BIT 4 = Internal connector 1473 * LSB BIT 5 = 1474 * LSB BIT 6 = 1475 * LSB BIT 7 = 1476 * 1477 * MSB BIT 0 = 1478 * MSB BIT 1 = 1479 * MSB BIT 2 = 1480 * MSB BIT 3 = 1481 * MSB BIT 4 = 1482 * MSB BIT 5 = 1483 * MSB BIT 6 = 1484 * MSB BIT 7 = 1485 */ 1486 uint8_t adapter_features[2]; 1487 1488 uint8_t reserved_4[16]; 1489 1490 /* Subsystem vendor ID for ISP2200 */ 1491 uint16_t subsystem_vendor_id_2200; 1492 1493 /* Subsystem device ID for ISP2200 */ 1494 uint16_t subsystem_device_id_2200; 1495 1496 uint8_t reserved_5; 1497 uint8_t checksum; 1498 } nvram_t; 1499 1500 /* 1501 * ISP queue - response queue entry definition. 1502 */ 1503 typedef struct { 1504 uint8_t entry_type; /* Entry type. */ 1505 uint8_t entry_count; /* Entry count. */ 1506 uint8_t sys_define; /* System defined. */ 1507 uint8_t entry_status; /* Entry Status. */ 1508 uint32_t handle; /* System defined handle */ 1509 uint8_t data[52]; 1510 uint32_t signature; 1511 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1512 } response_t; 1513 1514 /* 1515 * ISP queue - ATIO queue entry definition. 1516 */ 1517 struct atio { 1518 uint8_t entry_type; /* Entry type. */ 1519 uint8_t entry_count; /* Entry count. */ 1520 uint8_t data[58]; 1521 uint32_t signature; 1522 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1523 }; 1524 1525 typedef union { 1526 uint16_t extended; 1527 struct { 1528 uint8_t reserved; 1529 uint8_t standard; 1530 } id; 1531 } target_id_t; 1532 1533 #define SET_TARGET_ID(ha, to, from) \ 1534 do { \ 1535 if (HAS_EXTENDED_IDS(ha)) \ 1536 to.extended = cpu_to_le16(from); \ 1537 else \ 1538 to.id.standard = (uint8_t)from; \ 1539 } while (0) 1540 1541 /* 1542 * ISP queue - command entry structure definition. 1543 */ 1544 #define COMMAND_TYPE 0x11 /* Command entry */ 1545 typedef struct { 1546 uint8_t entry_type; /* Entry type. */ 1547 uint8_t entry_count; /* Entry count. */ 1548 uint8_t sys_define; /* System defined. */ 1549 uint8_t entry_status; /* Entry Status. */ 1550 uint32_t handle; /* System handle. */ 1551 target_id_t target; /* SCSI ID */ 1552 uint16_t lun; /* SCSI LUN */ 1553 uint16_t control_flags; /* Control flags. */ 1554 #define CF_WRITE BIT_6 1555 #define CF_READ BIT_5 1556 #define CF_SIMPLE_TAG BIT_3 1557 #define CF_ORDERED_TAG BIT_2 1558 #define CF_HEAD_TAG BIT_1 1559 uint16_t reserved_1; 1560 uint16_t timeout; /* Command timeout. */ 1561 uint16_t dseg_count; /* Data segment count. */ 1562 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1563 uint32_t byte_count; /* Total byte count. */ 1564 uint32_t dseg_0_address; /* Data segment 0 address. */ 1565 uint32_t dseg_0_length; /* Data segment 0 length. */ 1566 uint32_t dseg_1_address; /* Data segment 1 address. */ 1567 uint32_t dseg_1_length; /* Data segment 1 length. */ 1568 uint32_t dseg_2_address; /* Data segment 2 address. */ 1569 uint32_t dseg_2_length; /* Data segment 2 length. */ 1570 } cmd_entry_t; 1571 1572 /* 1573 * ISP queue - 64-Bit addressing, command entry structure definition. 1574 */ 1575 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1576 typedef struct { 1577 uint8_t entry_type; /* Entry type. */ 1578 uint8_t entry_count; /* Entry count. */ 1579 uint8_t sys_define; /* System defined. */ 1580 uint8_t entry_status; /* Entry Status. */ 1581 uint32_t handle; /* System handle. */ 1582 target_id_t target; /* SCSI ID */ 1583 uint16_t lun; /* SCSI LUN */ 1584 uint16_t control_flags; /* Control flags. */ 1585 uint16_t reserved_1; 1586 uint16_t timeout; /* Command timeout. */ 1587 uint16_t dseg_count; /* Data segment count. */ 1588 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1589 uint32_t byte_count; /* Total byte count. */ 1590 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1591 uint32_t dseg_0_length; /* Data segment 0 length. */ 1592 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1593 uint32_t dseg_1_length; /* Data segment 1 length. */ 1594 } cmd_a64_entry_t, request_t; 1595 1596 /* 1597 * ISP queue - continuation entry structure definition. 1598 */ 1599 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1600 typedef struct { 1601 uint8_t entry_type; /* Entry type. */ 1602 uint8_t entry_count; /* Entry count. */ 1603 uint8_t sys_define; /* System defined. */ 1604 uint8_t entry_status; /* Entry Status. */ 1605 uint32_t reserved; 1606 uint32_t dseg_0_address; /* Data segment 0 address. */ 1607 uint32_t dseg_0_length; /* Data segment 0 length. */ 1608 uint32_t dseg_1_address; /* Data segment 1 address. */ 1609 uint32_t dseg_1_length; /* Data segment 1 length. */ 1610 uint32_t dseg_2_address; /* Data segment 2 address. */ 1611 uint32_t dseg_2_length; /* Data segment 2 length. */ 1612 uint32_t dseg_3_address; /* Data segment 3 address. */ 1613 uint32_t dseg_3_length; /* Data segment 3 length. */ 1614 uint32_t dseg_4_address; /* Data segment 4 address. */ 1615 uint32_t dseg_4_length; /* Data segment 4 length. */ 1616 uint32_t dseg_5_address; /* Data segment 5 address. */ 1617 uint32_t dseg_5_length; /* Data segment 5 length. */ 1618 uint32_t dseg_6_address; /* Data segment 6 address. */ 1619 uint32_t dseg_6_length; /* Data segment 6 length. */ 1620 } cont_entry_t; 1621 1622 /* 1623 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1624 */ 1625 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1626 typedef struct { 1627 uint8_t entry_type; /* Entry type. */ 1628 uint8_t entry_count; /* Entry count. */ 1629 uint8_t sys_define; /* System defined. */ 1630 uint8_t entry_status; /* Entry Status. */ 1631 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1632 uint32_t dseg_0_length; /* Data segment 0 length. */ 1633 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1634 uint32_t dseg_1_length; /* Data segment 1 length. */ 1635 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1636 uint32_t dseg_2_length; /* Data segment 2 length. */ 1637 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1638 uint32_t dseg_3_length; /* Data segment 3 length. */ 1639 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1640 uint32_t dseg_4_length; /* Data segment 4 length. */ 1641 } cont_a64_entry_t; 1642 1643 #define PO_MODE_DIF_INSERT 0 1644 #define PO_MODE_DIF_REMOVE 1 1645 #define PO_MODE_DIF_PASS 2 1646 #define PO_MODE_DIF_REPLACE 3 1647 #define PO_MODE_DIF_TCP_CKSUM 6 1648 #define PO_ENABLE_DIF_BUNDLING BIT_8 1649 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1650 #define PO_DISABLE_INCR_REF_TAG BIT_5 1651 #define PO_DISABLE_GUARD_CHECK BIT_4 1652 /* 1653 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1654 */ 1655 struct crc_context { 1656 uint32_t handle; /* System handle. */ 1657 uint32_t ref_tag; 1658 uint16_t app_tag; 1659 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1660 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1661 uint16_t guard_seed; /* Initial Guard Seed */ 1662 uint16_t prot_opts; /* Requested Data Protection Mode */ 1663 uint16_t blk_size; /* Data size in bytes */ 1664 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1665 * only) */ 1666 uint32_t byte_count; /* Total byte count/ total data 1667 * transfer count */ 1668 union { 1669 struct { 1670 uint32_t reserved_1; 1671 uint16_t reserved_2; 1672 uint16_t reserved_3; 1673 uint32_t reserved_4; 1674 uint32_t data_address[2]; 1675 uint32_t data_length; 1676 uint32_t reserved_5[2]; 1677 uint32_t reserved_6; 1678 } nobundling; 1679 struct { 1680 uint32_t dif_byte_count; /* Total DIF byte 1681 * count */ 1682 uint16_t reserved_1; 1683 uint16_t dseg_count; /* Data segment count */ 1684 uint32_t reserved_2; 1685 uint32_t data_address[2]; 1686 uint32_t data_length; 1687 uint32_t dif_address[2]; 1688 uint32_t dif_length; /* Data segment 0 1689 * length */ 1690 } bundling; 1691 } u; 1692 1693 struct fcp_cmnd fcp_cmnd; 1694 dma_addr_t crc_ctx_dma; 1695 /* List of DMA context transfers */ 1696 struct list_head dsd_list; 1697 1698 /* This structure should not exceed 512 bytes */ 1699 }; 1700 1701 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1702 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1703 1704 /* 1705 * ISP queue - status entry structure definition. 1706 */ 1707 #define STATUS_TYPE 0x03 /* Status entry. */ 1708 typedef struct { 1709 uint8_t entry_type; /* Entry type. */ 1710 uint8_t entry_count; /* Entry count. */ 1711 uint8_t sys_define; /* System defined. */ 1712 uint8_t entry_status; /* Entry Status. */ 1713 uint32_t handle; /* System handle. */ 1714 uint16_t scsi_status; /* SCSI status. */ 1715 uint16_t comp_status; /* Completion status. */ 1716 uint16_t state_flags; /* State flags. */ 1717 uint16_t status_flags; /* Status flags. */ 1718 uint16_t rsp_info_len; /* Response Info Length. */ 1719 uint16_t req_sense_length; /* Request sense data length. */ 1720 uint32_t residual_length; /* Residual transfer length. */ 1721 uint8_t rsp_info[8]; /* FCP response information. */ 1722 uint8_t req_sense_data[32]; /* Request sense data. */ 1723 } sts_entry_t; 1724 1725 /* 1726 * Status entry entry status 1727 */ 1728 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1729 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1730 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1731 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1732 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1733 #define RF_BUSY BIT_1 /* Busy */ 1734 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1735 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1736 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1737 RF_INV_E_TYPE) 1738 1739 /* 1740 * Status entry SCSI status bit definitions. 1741 */ 1742 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1743 #define SS_RESIDUAL_UNDER BIT_11 1744 #define SS_RESIDUAL_OVER BIT_10 1745 #define SS_SENSE_LEN_VALID BIT_9 1746 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1747 1748 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1749 #define SS_BUSY_CONDITION BIT_3 1750 #define SS_CONDITION_MET BIT_2 1751 #define SS_CHECK_CONDITION BIT_1 1752 1753 /* 1754 * Status entry completion status 1755 */ 1756 #define CS_COMPLETE 0x0 /* No errors */ 1757 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1758 #define CS_DMA 0x2 /* A DMA direction error. */ 1759 #define CS_TRANSPORT 0x3 /* Transport error. */ 1760 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1761 #define CS_ABORTED 0x5 /* System aborted command. */ 1762 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1763 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1764 #define CS_DIF_ERROR 0xC /* DIF error detected */ 1765 1766 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1767 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1768 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1769 /* (selection timeout) */ 1770 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1771 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1772 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1773 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1774 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1775 #define CS_UNKNOWN 0x81 /* Driver defined */ 1776 #define CS_RETRY 0x82 /* Driver defined */ 1777 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1778 1779 #define CS_BIDIR_RD_OVERRUN 0x700 1780 #define CS_BIDIR_RD_WR_OVERRUN 0x707 1781 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 1782 #define CS_BIDIR_RD_UNDERRUN 0x1500 1783 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 1784 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 1785 #define CS_BIDIR_DMA 0x200 1786 /* 1787 * Status entry status flags 1788 */ 1789 #define SF_ABTS_TERMINATED BIT_10 1790 #define SF_LOGOUT_SENT BIT_13 1791 1792 /* 1793 * ISP queue - status continuation entry structure definition. 1794 */ 1795 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1796 typedef struct { 1797 uint8_t entry_type; /* Entry type. */ 1798 uint8_t entry_count; /* Entry count. */ 1799 uint8_t sys_define; /* System defined. */ 1800 uint8_t entry_status; /* Entry Status. */ 1801 uint8_t data[60]; /* data */ 1802 } sts_cont_entry_t; 1803 1804 /* 1805 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1806 * structure definition. 1807 */ 1808 #define STATUS_TYPE_21 0x21 /* Status entry. */ 1809 typedef struct { 1810 uint8_t entry_type; /* Entry type. */ 1811 uint8_t entry_count; /* Entry count. */ 1812 uint8_t handle_count; /* Handle count. */ 1813 uint8_t entry_status; /* Entry Status. */ 1814 uint32_t handle[15]; /* System handles. */ 1815 } sts21_entry_t; 1816 1817 /* 1818 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1819 * structure definition. 1820 */ 1821 #define STATUS_TYPE_22 0x22 /* Status entry. */ 1822 typedef struct { 1823 uint8_t entry_type; /* Entry type. */ 1824 uint8_t entry_count; /* Entry count. */ 1825 uint8_t handle_count; /* Handle count. */ 1826 uint8_t entry_status; /* Entry Status. */ 1827 uint16_t handle[30]; /* System handles. */ 1828 } sts22_entry_t; 1829 1830 /* 1831 * ISP queue - marker entry structure definition. 1832 */ 1833 #define MARKER_TYPE 0x04 /* Marker entry. */ 1834 typedef struct { 1835 uint8_t entry_type; /* Entry type. */ 1836 uint8_t entry_count; /* Entry count. */ 1837 uint8_t handle_count; /* Handle count. */ 1838 uint8_t entry_status; /* Entry Status. */ 1839 uint32_t sys_define_2; /* System defined. */ 1840 target_id_t target; /* SCSI ID */ 1841 uint8_t modifier; /* Modifier (7-0). */ 1842 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1843 #define MK_SYNC_ID 1 /* Synchronize ID */ 1844 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1845 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 1846 /* clear port changed, */ 1847 /* use sequence number. */ 1848 uint8_t reserved_1; 1849 uint16_t sequence_number; /* Sequence number of event */ 1850 uint16_t lun; /* SCSI LUN */ 1851 uint8_t reserved_2[48]; 1852 } mrk_entry_t; 1853 1854 /* 1855 * ISP queue - Management Server entry structure definition. 1856 */ 1857 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 1858 typedef struct { 1859 uint8_t entry_type; /* Entry type. */ 1860 uint8_t entry_count; /* Entry count. */ 1861 uint8_t handle_count; /* Handle count. */ 1862 uint8_t entry_status; /* Entry Status. */ 1863 uint32_t handle1; /* System handle. */ 1864 target_id_t loop_id; 1865 uint16_t status; 1866 uint16_t control_flags; /* Control flags. */ 1867 uint16_t reserved2; 1868 uint16_t timeout; 1869 uint16_t cmd_dsd_count; 1870 uint16_t total_dsd_count; 1871 uint8_t type; 1872 uint8_t r_ctl; 1873 uint16_t rx_id; 1874 uint16_t reserved3; 1875 uint32_t handle2; 1876 uint32_t rsp_bytecount; 1877 uint32_t req_bytecount; 1878 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 1879 uint32_t dseg_req_length; /* Data segment 0 length. */ 1880 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 1881 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 1882 } ms_iocb_entry_t; 1883 1884 1885 /* 1886 * ISP queue - Mailbox Command entry structure definition. 1887 */ 1888 #define MBX_IOCB_TYPE 0x39 1889 struct mbx_entry { 1890 uint8_t entry_type; 1891 uint8_t entry_count; 1892 uint8_t sys_define1; 1893 /* Use sys_define1 for source type */ 1894 #define SOURCE_SCSI 0x00 1895 #define SOURCE_IP 0x01 1896 #define SOURCE_VI 0x02 1897 #define SOURCE_SCTP 0x03 1898 #define SOURCE_MP 0x04 1899 #define SOURCE_MPIOCTL 0x05 1900 #define SOURCE_ASYNC_IOCB 0x07 1901 1902 uint8_t entry_status; 1903 1904 uint32_t handle; 1905 target_id_t loop_id; 1906 1907 uint16_t status; 1908 uint16_t state_flags; 1909 uint16_t status_flags; 1910 1911 uint32_t sys_define2[2]; 1912 1913 uint16_t mb0; 1914 uint16_t mb1; 1915 uint16_t mb2; 1916 uint16_t mb3; 1917 uint16_t mb6; 1918 uint16_t mb7; 1919 uint16_t mb9; 1920 uint16_t mb10; 1921 uint32_t reserved_2[2]; 1922 uint8_t node_name[WWN_SIZE]; 1923 uint8_t port_name[WWN_SIZE]; 1924 }; 1925 1926 /* 1927 * ISP request and response queue entry sizes 1928 */ 1929 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 1930 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 1931 1932 1933 /* 1934 * 24 bit port ID type definition. 1935 */ 1936 typedef union { 1937 uint32_t b24 : 24; 1938 1939 struct { 1940 #ifdef __BIG_ENDIAN 1941 uint8_t domain; 1942 uint8_t area; 1943 uint8_t al_pa; 1944 #elif defined(__LITTLE_ENDIAN) 1945 uint8_t al_pa; 1946 uint8_t area; 1947 uint8_t domain; 1948 #else 1949 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 1950 #endif 1951 uint8_t rsvd_1; 1952 } b; 1953 } port_id_t; 1954 #define INVALID_PORT_ID 0xFFFFFF 1955 1956 /* 1957 * Switch info gathering structure. 1958 */ 1959 typedef struct { 1960 port_id_t d_id; 1961 uint8_t node_name[WWN_SIZE]; 1962 uint8_t port_name[WWN_SIZE]; 1963 uint8_t fabric_port_name[WWN_SIZE]; 1964 uint16_t fp_speed; 1965 uint8_t fc4_type; 1966 } sw_info_t; 1967 1968 /* FCP-4 types */ 1969 #define FC4_TYPE_FCP_SCSI 0x08 1970 #define FC4_TYPE_OTHER 0x0 1971 #define FC4_TYPE_UNKNOWN 0xff 1972 1973 /* 1974 * Fibre channel port type. 1975 */ 1976 typedef enum { 1977 FCT_UNKNOWN, 1978 FCT_RSCN, 1979 FCT_SWITCH, 1980 FCT_BROADCAST, 1981 FCT_INITIATOR, 1982 FCT_TARGET 1983 } fc_port_type_t; 1984 1985 /* 1986 * Fibre channel port structure. 1987 */ 1988 typedef struct fc_port { 1989 struct list_head list; 1990 struct scsi_qla_host *vha; 1991 1992 uint8_t node_name[WWN_SIZE]; 1993 uint8_t port_name[WWN_SIZE]; 1994 port_id_t d_id; 1995 uint16_t loop_id; 1996 uint16_t old_loop_id; 1997 1998 uint16_t tgt_id; 1999 uint16_t old_tgt_id; 2000 2001 uint8_t fcp_prio; 2002 2003 uint8_t fabric_port_name[WWN_SIZE]; 2004 uint16_t fp_speed; 2005 2006 fc_port_type_t port_type; 2007 2008 atomic_t state; 2009 uint32_t flags; 2010 2011 int login_retry; 2012 2013 struct fc_rport *rport, *drport; 2014 u32 supported_classes; 2015 2016 uint8_t fc4_type; 2017 uint8_t scan_state; 2018 2019 unsigned long last_queue_full; 2020 unsigned long last_ramp_up; 2021 2022 uint16_t port_id; 2023 } fc_port_t; 2024 2025 #include "qla_mr.h" 2026 2027 /* 2028 * Fibre channel port/lun states. 2029 */ 2030 #define FCS_UNCONFIGURED 1 2031 #define FCS_DEVICE_DEAD 2 2032 #define FCS_DEVICE_LOST 3 2033 #define FCS_ONLINE 4 2034 2035 static const char * const port_state_str[] = { 2036 "Unknown", 2037 "UNCONFIGURED", 2038 "DEAD", 2039 "LOST", 2040 "ONLINE" 2041 }; 2042 2043 /* 2044 * FC port flags. 2045 */ 2046 #define FCF_FABRIC_DEVICE BIT_0 2047 #define FCF_LOGIN_NEEDED BIT_1 2048 #define FCF_FCP2_DEVICE BIT_2 2049 #define FCF_ASYNC_SENT BIT_3 2050 #define FCF_CONF_COMP_SUPPORTED BIT_4 2051 2052 /* No loop ID flag. */ 2053 #define FC_NO_LOOP_ID 0x1000 2054 2055 /* 2056 * FC-CT interface 2057 * 2058 * NOTE: All structures are big-endian in form. 2059 */ 2060 2061 #define CT_REJECT_RESPONSE 0x8001 2062 #define CT_ACCEPT_RESPONSE 0x8002 2063 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2064 #define CT_REASON_CANNOT_PERFORM 0x09 2065 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2066 #define CT_EXPL_ALREADY_REGISTERED 0x10 2067 2068 #define NS_N_PORT_TYPE 0x01 2069 #define NS_NL_PORT_TYPE 0x02 2070 #define NS_NX_PORT_TYPE 0x7F 2071 2072 #define GA_NXT_CMD 0x100 2073 #define GA_NXT_REQ_SIZE (16 + 4) 2074 #define GA_NXT_RSP_SIZE (16 + 620) 2075 2076 #define GID_PT_CMD 0x1A1 2077 #define GID_PT_REQ_SIZE (16 + 4) 2078 2079 #define GPN_ID_CMD 0x112 2080 #define GPN_ID_REQ_SIZE (16 + 4) 2081 #define GPN_ID_RSP_SIZE (16 + 8) 2082 2083 #define GNN_ID_CMD 0x113 2084 #define GNN_ID_REQ_SIZE (16 + 4) 2085 #define GNN_ID_RSP_SIZE (16 + 8) 2086 2087 #define GFT_ID_CMD 0x117 2088 #define GFT_ID_REQ_SIZE (16 + 4) 2089 #define GFT_ID_RSP_SIZE (16 + 32) 2090 2091 #define RFT_ID_CMD 0x217 2092 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2093 #define RFT_ID_RSP_SIZE 16 2094 2095 #define RFF_ID_CMD 0x21F 2096 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2097 #define RFF_ID_RSP_SIZE 16 2098 2099 #define RNN_ID_CMD 0x213 2100 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2101 #define RNN_ID_RSP_SIZE 16 2102 2103 #define RSNN_NN_CMD 0x239 2104 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2105 #define RSNN_NN_RSP_SIZE 16 2106 2107 #define GFPN_ID_CMD 0x11C 2108 #define GFPN_ID_REQ_SIZE (16 + 4) 2109 #define GFPN_ID_RSP_SIZE (16 + 8) 2110 2111 #define GPSC_CMD 0x127 2112 #define GPSC_REQ_SIZE (16 + 8) 2113 #define GPSC_RSP_SIZE (16 + 2 + 2) 2114 2115 #define GFF_ID_CMD 0x011F 2116 #define GFF_ID_REQ_SIZE (16 + 4) 2117 #define GFF_ID_RSP_SIZE (16 + 128) 2118 2119 /* 2120 * HBA attribute types. 2121 */ 2122 #define FDMI_HBA_ATTR_COUNT 9 2123 #define FDMI_HBA_NODE_NAME 1 2124 #define FDMI_HBA_MANUFACTURER 2 2125 #define FDMI_HBA_SERIAL_NUMBER 3 2126 #define FDMI_HBA_MODEL 4 2127 #define FDMI_HBA_MODEL_DESCRIPTION 5 2128 #define FDMI_HBA_HARDWARE_VERSION 6 2129 #define FDMI_HBA_DRIVER_VERSION 7 2130 #define FDMI_HBA_OPTION_ROM_VERSION 8 2131 #define FDMI_HBA_FIRMWARE_VERSION 9 2132 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2133 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2134 2135 struct ct_fdmi_hba_attr { 2136 uint16_t type; 2137 uint16_t len; 2138 union { 2139 uint8_t node_name[WWN_SIZE]; 2140 uint8_t manufacturer[32]; 2141 uint8_t serial_num[8]; 2142 uint8_t model[16]; 2143 uint8_t model_desc[80]; 2144 uint8_t hw_version[16]; 2145 uint8_t driver_version[32]; 2146 uint8_t orom_version[16]; 2147 uint8_t fw_version[16]; 2148 uint8_t os_version[128]; 2149 uint8_t max_ct_len[4]; 2150 } a; 2151 }; 2152 2153 struct ct_fdmi_hba_attributes { 2154 uint32_t count; 2155 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2156 }; 2157 2158 /* 2159 * Port attribute types. 2160 */ 2161 #define FDMI_PORT_ATTR_COUNT 6 2162 #define FDMI_PORT_FC4_TYPES 1 2163 #define FDMI_PORT_SUPPORT_SPEED 2 2164 #define FDMI_PORT_CURRENT_SPEED 3 2165 #define FDMI_PORT_MAX_FRAME_SIZE 4 2166 #define FDMI_PORT_OS_DEVICE_NAME 5 2167 #define FDMI_PORT_HOST_NAME 6 2168 2169 #define FDMI_PORT_SPEED_1GB 0x1 2170 #define FDMI_PORT_SPEED_2GB 0x2 2171 #define FDMI_PORT_SPEED_10GB 0x4 2172 #define FDMI_PORT_SPEED_4GB 0x8 2173 #define FDMI_PORT_SPEED_8GB 0x10 2174 #define FDMI_PORT_SPEED_16GB 0x20 2175 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2176 2177 struct ct_fdmi_port_attr { 2178 uint16_t type; 2179 uint16_t len; 2180 union { 2181 uint8_t fc4_types[32]; 2182 uint32_t sup_speed; 2183 uint32_t cur_speed; 2184 uint32_t max_frame_size; 2185 uint8_t os_dev_name[32]; 2186 uint8_t host_name[32]; 2187 } a; 2188 }; 2189 2190 /* 2191 * Port Attribute Block. 2192 */ 2193 struct ct_fdmi_port_attributes { 2194 uint32_t count; 2195 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2196 }; 2197 2198 /* FDMI definitions. */ 2199 #define GRHL_CMD 0x100 2200 #define GHAT_CMD 0x101 2201 #define GRPL_CMD 0x102 2202 #define GPAT_CMD 0x110 2203 2204 #define RHBA_CMD 0x200 2205 #define RHBA_RSP_SIZE 16 2206 2207 #define RHAT_CMD 0x201 2208 #define RPRT_CMD 0x210 2209 2210 #define RPA_CMD 0x211 2211 #define RPA_RSP_SIZE 16 2212 2213 #define DHBA_CMD 0x300 2214 #define DHBA_REQ_SIZE (16 + 8) 2215 #define DHBA_RSP_SIZE 16 2216 2217 #define DHAT_CMD 0x301 2218 #define DPRT_CMD 0x310 2219 #define DPA_CMD 0x311 2220 2221 /* CT command header -- request/response common fields */ 2222 struct ct_cmd_hdr { 2223 uint8_t revision; 2224 uint8_t in_id[3]; 2225 uint8_t gs_type; 2226 uint8_t gs_subtype; 2227 uint8_t options; 2228 uint8_t reserved; 2229 }; 2230 2231 /* CT command request */ 2232 struct ct_sns_req { 2233 struct ct_cmd_hdr header; 2234 uint16_t command; 2235 uint16_t max_rsp_size; 2236 uint8_t fragment_id; 2237 uint8_t reserved[3]; 2238 2239 union { 2240 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2241 struct { 2242 uint8_t reserved; 2243 uint8_t port_id[3]; 2244 } port_id; 2245 2246 struct { 2247 uint8_t port_type; 2248 uint8_t domain; 2249 uint8_t area; 2250 uint8_t reserved; 2251 } gid_pt; 2252 2253 struct { 2254 uint8_t reserved; 2255 uint8_t port_id[3]; 2256 uint8_t fc4_types[32]; 2257 } rft_id; 2258 2259 struct { 2260 uint8_t reserved; 2261 uint8_t port_id[3]; 2262 uint16_t reserved2; 2263 uint8_t fc4_feature; 2264 uint8_t fc4_type; 2265 } rff_id; 2266 2267 struct { 2268 uint8_t reserved; 2269 uint8_t port_id[3]; 2270 uint8_t node_name[8]; 2271 } rnn_id; 2272 2273 struct { 2274 uint8_t node_name[8]; 2275 uint8_t name_len; 2276 uint8_t sym_node_name[255]; 2277 } rsnn_nn; 2278 2279 struct { 2280 uint8_t hba_indentifier[8]; 2281 } ghat; 2282 2283 struct { 2284 uint8_t hba_identifier[8]; 2285 uint32_t entry_count; 2286 uint8_t port_name[8]; 2287 struct ct_fdmi_hba_attributes attrs; 2288 } rhba; 2289 2290 struct { 2291 uint8_t hba_identifier[8]; 2292 struct ct_fdmi_hba_attributes attrs; 2293 } rhat; 2294 2295 struct { 2296 uint8_t port_name[8]; 2297 struct ct_fdmi_port_attributes attrs; 2298 } rpa; 2299 2300 struct { 2301 uint8_t port_name[8]; 2302 } dhba; 2303 2304 struct { 2305 uint8_t port_name[8]; 2306 } dhat; 2307 2308 struct { 2309 uint8_t port_name[8]; 2310 } dprt; 2311 2312 struct { 2313 uint8_t port_name[8]; 2314 } dpa; 2315 2316 struct { 2317 uint8_t port_name[8]; 2318 } gpsc; 2319 2320 struct { 2321 uint8_t reserved; 2322 uint8_t port_name[3]; 2323 } gff_id; 2324 } req; 2325 }; 2326 2327 /* CT command response header */ 2328 struct ct_rsp_hdr { 2329 struct ct_cmd_hdr header; 2330 uint16_t response; 2331 uint16_t residual; 2332 uint8_t fragment_id; 2333 uint8_t reason_code; 2334 uint8_t explanation_code; 2335 uint8_t vendor_unique; 2336 }; 2337 2338 struct ct_sns_gid_pt_data { 2339 uint8_t control_byte; 2340 uint8_t port_id[3]; 2341 }; 2342 2343 struct ct_sns_rsp { 2344 struct ct_rsp_hdr header; 2345 2346 union { 2347 struct { 2348 uint8_t port_type; 2349 uint8_t port_id[3]; 2350 uint8_t port_name[8]; 2351 uint8_t sym_port_name_len; 2352 uint8_t sym_port_name[255]; 2353 uint8_t node_name[8]; 2354 uint8_t sym_node_name_len; 2355 uint8_t sym_node_name[255]; 2356 uint8_t init_proc_assoc[8]; 2357 uint8_t node_ip_addr[16]; 2358 uint8_t class_of_service[4]; 2359 uint8_t fc4_types[32]; 2360 uint8_t ip_address[16]; 2361 uint8_t fabric_port_name[8]; 2362 uint8_t reserved; 2363 uint8_t hard_address[3]; 2364 } ga_nxt; 2365 2366 struct { 2367 /* Assume the largest number of targets for the union */ 2368 struct ct_sns_gid_pt_data 2369 entries[MAX_FIBRE_DEVICES_MAX]; 2370 } gid_pt; 2371 2372 struct { 2373 uint8_t port_name[8]; 2374 } gpn_id; 2375 2376 struct { 2377 uint8_t node_name[8]; 2378 } gnn_id; 2379 2380 struct { 2381 uint8_t fc4_types[32]; 2382 } gft_id; 2383 2384 struct { 2385 uint32_t entry_count; 2386 uint8_t port_name[8]; 2387 struct ct_fdmi_hba_attributes attrs; 2388 } ghat; 2389 2390 struct { 2391 uint8_t port_name[8]; 2392 } gfpn_id; 2393 2394 struct { 2395 uint16_t speeds; 2396 uint16_t speed; 2397 } gpsc; 2398 2399 #define GFF_FCP_SCSI_OFFSET 7 2400 struct { 2401 uint8_t fc4_features[128]; 2402 } gff_id; 2403 } rsp; 2404 }; 2405 2406 struct ct_sns_pkt { 2407 union { 2408 struct ct_sns_req req; 2409 struct ct_sns_rsp rsp; 2410 } p; 2411 }; 2412 2413 /* 2414 * SNS command structures -- for 2200 compatibility. 2415 */ 2416 #define RFT_ID_SNS_SCMD_LEN 22 2417 #define RFT_ID_SNS_CMD_SIZE 60 2418 #define RFT_ID_SNS_DATA_SIZE 16 2419 2420 #define RNN_ID_SNS_SCMD_LEN 10 2421 #define RNN_ID_SNS_CMD_SIZE 36 2422 #define RNN_ID_SNS_DATA_SIZE 16 2423 2424 #define GA_NXT_SNS_SCMD_LEN 6 2425 #define GA_NXT_SNS_CMD_SIZE 28 2426 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 2427 2428 #define GID_PT_SNS_SCMD_LEN 6 2429 #define GID_PT_SNS_CMD_SIZE 28 2430 /* 2431 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 2432 * adapters. 2433 */ 2434 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 2435 2436 #define GPN_ID_SNS_SCMD_LEN 6 2437 #define GPN_ID_SNS_CMD_SIZE 28 2438 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 2439 2440 #define GNN_ID_SNS_SCMD_LEN 6 2441 #define GNN_ID_SNS_CMD_SIZE 28 2442 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 2443 2444 struct sns_cmd_pkt { 2445 union { 2446 struct { 2447 uint16_t buffer_length; 2448 uint16_t reserved_1; 2449 uint32_t buffer_address[2]; 2450 uint16_t subcommand_length; 2451 uint16_t reserved_2; 2452 uint16_t subcommand; 2453 uint16_t size; 2454 uint32_t reserved_3; 2455 uint8_t param[36]; 2456 } cmd; 2457 2458 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 2459 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 2460 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 2461 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 2462 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 2463 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 2464 } p; 2465 }; 2466 2467 struct fw_blob { 2468 char *name; 2469 uint32_t segs[4]; 2470 const struct firmware *fw; 2471 }; 2472 2473 /* Return data from MBC_GET_ID_LIST call. */ 2474 struct gid_list_info { 2475 uint8_t al_pa; 2476 uint8_t area; 2477 uint8_t domain; 2478 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2479 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2480 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 2481 }; 2482 2483 /* NPIV */ 2484 typedef struct vport_info { 2485 uint8_t port_name[WWN_SIZE]; 2486 uint8_t node_name[WWN_SIZE]; 2487 int vp_id; 2488 uint16_t loop_id; 2489 unsigned long host_no; 2490 uint8_t port_id[3]; 2491 int loop_state; 2492 } vport_info_t; 2493 2494 typedef struct vport_params { 2495 uint8_t port_name[WWN_SIZE]; 2496 uint8_t node_name[WWN_SIZE]; 2497 uint32_t options; 2498 #define VP_OPTS_RETRY_ENABLE BIT_0 2499 #define VP_OPTS_VP_DISABLE BIT_1 2500 } vport_params_t; 2501 2502 /* NPIV - return codes of VP create and modify */ 2503 #define VP_RET_CODE_OK 0 2504 #define VP_RET_CODE_FATAL 1 2505 #define VP_RET_CODE_WRONG_ID 2 2506 #define VP_RET_CODE_WWPN 3 2507 #define VP_RET_CODE_RESOURCES 4 2508 #define VP_RET_CODE_NO_MEM 5 2509 #define VP_RET_CODE_NOT_FOUND 6 2510 2511 struct qla_hw_data; 2512 struct rsp_que; 2513 /* 2514 * ISP operations 2515 */ 2516 struct isp_operations { 2517 2518 int (*pci_config) (struct scsi_qla_host *); 2519 void (*reset_chip) (struct scsi_qla_host *); 2520 int (*chip_diag) (struct scsi_qla_host *); 2521 void (*config_rings) (struct scsi_qla_host *); 2522 void (*reset_adapter) (struct scsi_qla_host *); 2523 int (*nvram_config) (struct scsi_qla_host *); 2524 void (*update_fw_options) (struct scsi_qla_host *); 2525 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 2526 2527 char * (*pci_info_str) (struct scsi_qla_host *, char *); 2528 char * (*fw_version_str) (struct scsi_qla_host *, char *); 2529 2530 irq_handler_t intr_handler; 2531 void (*enable_intrs) (struct qla_hw_data *); 2532 void (*disable_intrs) (struct qla_hw_data *); 2533 2534 int (*abort_command) (srb_t *); 2535 int (*target_reset) (struct fc_port *, unsigned int, int); 2536 int (*lun_reset) (struct fc_port *, unsigned int, int); 2537 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 2538 uint8_t, uint8_t, uint16_t *, uint8_t); 2539 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 2540 uint8_t, uint8_t); 2541 2542 uint16_t (*calc_req_entries) (uint16_t); 2543 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 2544 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t); 2545 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 2546 uint32_t); 2547 2548 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *, 2549 uint32_t, uint32_t); 2550 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 2551 uint32_t); 2552 2553 void (*fw_dump) (struct scsi_qla_host *, int); 2554 2555 int (*beacon_on) (struct scsi_qla_host *); 2556 int (*beacon_off) (struct scsi_qla_host *); 2557 void (*beacon_blink) (struct scsi_qla_host *); 2558 2559 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 2560 uint32_t, uint32_t); 2561 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 2562 uint32_t); 2563 2564 int (*get_flash_version) (struct scsi_qla_host *, void *); 2565 int (*start_scsi) (srb_t *); 2566 int (*abort_isp) (struct scsi_qla_host *); 2567 int (*iospace_config)(struct qla_hw_data*); 2568 int (*initialize_adapter)(struct scsi_qla_host *); 2569 }; 2570 2571 /* MSI-X Support *************************************************************/ 2572 2573 #define QLA_MSIX_CHIP_REV_24XX 3 2574 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 2575 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 2576 2577 #define QLA_MSIX_DEFAULT 0x00 2578 #define QLA_MSIX_RSP_Q 0x01 2579 2580 #define QLA_MIDX_DEFAULT 0 2581 #define QLA_MIDX_RSP_Q 1 2582 #define QLA_PCI_MSIX_CONTROL 0xa2 2583 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 2584 2585 struct scsi_qla_host; 2586 2587 struct qla_msix_entry { 2588 int have_irq; 2589 uint32_t vector; 2590 uint16_t entry; 2591 struct rsp_que *rsp; 2592 }; 2593 2594 #define WATCH_INTERVAL 1 /* number of seconds */ 2595 2596 /* Work events. */ 2597 enum qla_work_type { 2598 QLA_EVT_AEN, 2599 QLA_EVT_IDC_ACK, 2600 QLA_EVT_ASYNC_LOGIN, 2601 QLA_EVT_ASYNC_LOGIN_DONE, 2602 QLA_EVT_ASYNC_LOGOUT, 2603 QLA_EVT_ASYNC_LOGOUT_DONE, 2604 QLA_EVT_ASYNC_ADISC, 2605 QLA_EVT_ASYNC_ADISC_DONE, 2606 QLA_EVT_UEVENT, 2607 QLA_EVT_AENFX, 2608 }; 2609 2610 2611 struct qla_work_evt { 2612 struct list_head list; 2613 enum qla_work_type type; 2614 u32 flags; 2615 #define QLA_EVT_FLAG_FREE 0x1 2616 2617 union { 2618 struct { 2619 enum fc_host_event_code code; 2620 u32 data; 2621 } aen; 2622 struct { 2623 #define QLA_IDC_ACK_REGS 7 2624 uint16_t mb[QLA_IDC_ACK_REGS]; 2625 } idc_ack; 2626 struct { 2627 struct fc_port *fcport; 2628 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 2629 u16 data[2]; 2630 } logio; 2631 struct { 2632 u32 code; 2633 #define QLA_UEVENT_CODE_FW_DUMP 0 2634 } uevent; 2635 struct { 2636 uint32_t evtcode; 2637 uint32_t mbx[8]; 2638 uint32_t count; 2639 } aenfx; 2640 struct { 2641 srb_t *sp; 2642 } iosb; 2643 } u; 2644 }; 2645 2646 struct qla_chip_state_84xx { 2647 struct list_head list; 2648 struct kref kref; 2649 2650 void *bus; 2651 spinlock_t access_lock; 2652 struct mutex fw_update_mutex; 2653 uint32_t fw_update; 2654 uint32_t op_fw_version; 2655 uint32_t op_fw_size; 2656 uint32_t op_fw_seq_size; 2657 uint32_t diag_fw_version; 2658 uint32_t gold_fw_version; 2659 }; 2660 2661 struct qla_statistics { 2662 uint32_t total_isp_aborts; 2663 uint64_t input_bytes; 2664 uint64_t output_bytes; 2665 uint64_t input_requests; 2666 uint64_t output_requests; 2667 uint32_t control_requests; 2668 2669 uint64_t jiffies_at_last_reset; 2670 }; 2671 2672 struct bidi_statistics { 2673 unsigned long long io_count; 2674 unsigned long long transfer_bytes; 2675 }; 2676 2677 /* Multi queue support */ 2678 #define MBC_INITIALIZE_MULTIQ 0x1f 2679 #define QLA_QUE_PAGE 0X1000 2680 #define QLA_MQ_SIZE 32 2681 #define QLA_MAX_QUEUES 256 2682 #define ISP_QUE_REG(ha, id) \ 2683 ((ha->mqenable || IS_QLA83XX(ha)) ? \ 2684 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 2685 ((void __iomem *)ha->iobase)) 2686 #define QLA_REQ_QUE_ID(tag) \ 2687 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 2688 #define QLA_DEFAULT_QUE_QOS 5 2689 #define QLA_PRECONFIG_VPORTS 32 2690 #define QLA_MAX_VPORTS_QLA24XX 128 2691 #define QLA_MAX_VPORTS_QLA25XX 256 2692 /* Response queue data structure */ 2693 struct rsp_que { 2694 dma_addr_t dma; 2695 response_t *ring; 2696 response_t *ring_ptr; 2697 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 2698 uint32_t __iomem *rsp_q_out; 2699 uint16_t ring_index; 2700 uint16_t out_ptr; 2701 uint16_t length; 2702 uint16_t options; 2703 uint16_t rid; 2704 uint16_t id; 2705 uint16_t vp_idx; 2706 struct qla_hw_data *hw; 2707 struct qla_msix_entry *msix; 2708 struct req_que *req; 2709 srb_t *status_srb; /* status continuation entry */ 2710 struct work_struct q_work; 2711 2712 dma_addr_t dma_fx00; 2713 response_t *ring_fx00; 2714 uint16_t length_fx00; 2715 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 2716 }; 2717 2718 /* Request queue data structure */ 2719 struct req_que { 2720 dma_addr_t dma; 2721 request_t *ring; 2722 request_t *ring_ptr; 2723 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 2724 uint32_t __iomem *req_q_out; 2725 uint16_t ring_index; 2726 uint16_t in_ptr; 2727 uint16_t cnt; 2728 uint16_t length; 2729 uint16_t options; 2730 uint16_t rid; 2731 uint16_t id; 2732 uint16_t qos; 2733 uint16_t vp_idx; 2734 struct rsp_que *rsp; 2735 srb_t **outstanding_cmds; 2736 uint32_t current_outstanding_cmd; 2737 uint16_t num_outstanding_cmds; 2738 int max_q_depth; 2739 2740 dma_addr_t dma_fx00; 2741 request_t *ring_fx00; 2742 uint16_t length_fx00; 2743 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 2744 }; 2745 2746 /* Place holder for FW buffer parameters */ 2747 struct qlfc_fw { 2748 void *fw_buf; 2749 dma_addr_t fw_dma; 2750 uint32_t len; 2751 }; 2752 2753 struct scsi_qlt_host { 2754 void *target_lport_ptr; 2755 struct mutex tgt_mutex; 2756 struct mutex tgt_host_action_mutex; 2757 struct qla_tgt *qla_tgt; 2758 }; 2759 2760 struct qlt_hw_data { 2761 /* Protected by hw lock */ 2762 uint32_t enable_class_2:1; 2763 uint32_t enable_explicit_conf:1; 2764 uint32_t ini_mode_force_reverse:1; 2765 uint32_t node_name_set:1; 2766 2767 dma_addr_t atio_dma; /* Physical address. */ 2768 struct atio *atio_ring; /* Base virtual address */ 2769 struct atio *atio_ring_ptr; /* Current address. */ 2770 uint16_t atio_ring_index; /* Current index. */ 2771 uint16_t atio_q_length; 2772 uint32_t __iomem *atio_q_in; 2773 uint32_t __iomem *atio_q_out; 2774 2775 struct qla_tgt_func_tmpl *tgt_ops; 2776 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS]; 2777 uint16_t current_handle; 2778 2779 struct qla_tgt_vp_map *tgt_vp_map; 2780 2781 int saved_set; 2782 uint16_t saved_exchange_count; 2783 uint32_t saved_firmware_options_1; 2784 uint32_t saved_firmware_options_2; 2785 uint32_t saved_firmware_options_3; 2786 uint8_t saved_firmware_options[2]; 2787 uint8_t saved_add_firmware_options[2]; 2788 2789 uint8_t tgt_node_name[WWN_SIZE]; 2790 }; 2791 2792 /* 2793 * Qlogic host adapter specific data structure. 2794 */ 2795 struct qla_hw_data { 2796 struct pci_dev *pdev; 2797 /* SRB cache. */ 2798 #define SRB_MIN_REQ 128 2799 mempool_t *srb_mempool; 2800 2801 volatile struct { 2802 uint32_t mbox_int :1; 2803 uint32_t mbox_busy :1; 2804 uint32_t disable_risc_code_load :1; 2805 uint32_t enable_64bit_addressing :1; 2806 uint32_t enable_lip_reset :1; 2807 uint32_t enable_target_reset :1; 2808 uint32_t enable_lip_full_login :1; 2809 uint32_t enable_led_scheme :1; 2810 2811 uint32_t msi_enabled :1; 2812 uint32_t msix_enabled :1; 2813 uint32_t disable_serdes :1; 2814 uint32_t gpsc_supported :1; 2815 uint32_t npiv_supported :1; 2816 uint32_t pci_channel_io_perm_failure :1; 2817 uint32_t fce_enabled :1; 2818 uint32_t fac_supported :1; 2819 2820 uint32_t chip_reset_done :1; 2821 uint32_t port0 :1; 2822 uint32_t running_gold_fw :1; 2823 uint32_t eeh_busy :1; 2824 uint32_t cpu_affinity_enabled :1; 2825 uint32_t disable_msix_handshake :1; 2826 uint32_t fcp_prio_enabled :1; 2827 uint32_t isp82xx_fw_hung:1; 2828 uint32_t nic_core_hung:1; 2829 2830 uint32_t quiesce_owner:1; 2831 uint32_t nic_core_reset_hdlr_active:1; 2832 uint32_t nic_core_reset_owner:1; 2833 uint32_t isp82xx_no_md_cap:1; 2834 uint32_t host_shutting_down:1; 2835 uint32_t idc_compl_status:1; 2836 2837 uint32_t mr_reset_hdlr_active:1; 2838 uint32_t mr_intr_valid:1; 2839 /* 34 bits */ 2840 } flags; 2841 2842 /* This spinlock is used to protect "io transactions", you must 2843 * acquire it before doing any IO to the card, eg with RD_REG*() and 2844 * WRT_REG*() for the duration of your entire commandtransaction. 2845 * 2846 * This spinlock is of lower priority than the io request lock. 2847 */ 2848 2849 spinlock_t hardware_lock ____cacheline_aligned; 2850 int bars; 2851 int mem_only; 2852 device_reg_t __iomem *iobase; /* Base I/O address */ 2853 resource_size_t pio_address; 2854 2855 #define MIN_IOBASE_LEN 0x100 2856 dma_addr_t bar0_hdl; 2857 2858 void __iomem *cregbase; 2859 dma_addr_t bar2_hdl; 2860 #define BAR0_LEN_FX00 (1024 * 1024) 2861 #define BAR2_LEN_FX00 (128 * 1024) 2862 2863 uint32_t rqstq_intr_code; 2864 uint32_t mbx_intr_code; 2865 uint32_t req_que_len; 2866 uint32_t rsp_que_len; 2867 uint32_t req_que_off; 2868 uint32_t rsp_que_off; 2869 2870 /* Multi queue data structs */ 2871 device_reg_t __iomem *mqiobase; 2872 device_reg_t __iomem *msixbase; 2873 uint16_t msix_count; 2874 uint8_t mqenable; 2875 struct req_que **req_q_map; 2876 struct rsp_que **rsp_q_map; 2877 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 2878 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 2879 uint8_t max_req_queues; 2880 uint8_t max_rsp_queues; 2881 struct qla_npiv_entry *npiv_info; 2882 uint16_t nvram_npiv_size; 2883 2884 uint16_t switch_cap; 2885 #define FLOGI_SEQ_DEL BIT_8 2886 #define FLOGI_MID_SUPPORT BIT_10 2887 #define FLOGI_VSAN_SUPPORT BIT_12 2888 #define FLOGI_SP_SUPPORT BIT_13 2889 2890 uint8_t port_no; /* Physical port of adapter */ 2891 2892 /* Timeout timers. */ 2893 uint8_t loop_down_abort_time; /* port down timer */ 2894 atomic_t loop_down_timer; /* loop down timer */ 2895 uint8_t link_down_timeout; /* link down timeout */ 2896 uint16_t max_loop_id; 2897 uint16_t max_fibre_devices; /* Maximum number of targets */ 2898 2899 uint16_t fb_rev; 2900 uint16_t min_external_loopid; /* First external loop Id */ 2901 2902 #define PORT_SPEED_UNKNOWN 0xFFFF 2903 #define PORT_SPEED_1GB 0x00 2904 #define PORT_SPEED_2GB 0x01 2905 #define PORT_SPEED_4GB 0x03 2906 #define PORT_SPEED_8GB 0x04 2907 #define PORT_SPEED_16GB 0x05 2908 #define PORT_SPEED_10GB 0x13 2909 uint16_t link_data_rate; /* F/W operating speed */ 2910 2911 uint8_t current_topology; 2912 uint8_t prev_topology; 2913 #define ISP_CFG_NL 1 2914 #define ISP_CFG_N 2 2915 #define ISP_CFG_FL 4 2916 #define ISP_CFG_F 8 2917 2918 uint8_t operating_mode; /* F/W operating mode */ 2919 #define LOOP 0 2920 #define P2P 1 2921 #define LOOP_P2P 2 2922 #define P2P_LOOP 3 2923 uint8_t interrupts_on; 2924 uint32_t isp_abort_cnt; 2925 2926 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 2927 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 2928 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 2929 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 2930 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 2931 uint32_t device_type; 2932 #define DT_ISP2100 BIT_0 2933 #define DT_ISP2200 BIT_1 2934 #define DT_ISP2300 BIT_2 2935 #define DT_ISP2312 BIT_3 2936 #define DT_ISP2322 BIT_4 2937 #define DT_ISP6312 BIT_5 2938 #define DT_ISP6322 BIT_6 2939 #define DT_ISP2422 BIT_7 2940 #define DT_ISP2432 BIT_8 2941 #define DT_ISP5422 BIT_9 2942 #define DT_ISP5432 BIT_10 2943 #define DT_ISP2532 BIT_11 2944 #define DT_ISP8432 BIT_12 2945 #define DT_ISP8001 BIT_13 2946 #define DT_ISP8021 BIT_14 2947 #define DT_ISP2031 BIT_15 2948 #define DT_ISP8031 BIT_16 2949 #define DT_ISPFX00 BIT_17 2950 #define DT_ISP8044 BIT_18 2951 #define DT_ISP_LAST (DT_ISP8044 << 1) 2952 2953 #define DT_T10_PI BIT_25 2954 #define DT_IIDMA BIT_26 2955 #define DT_FWI2 BIT_27 2956 #define DT_ZIO_SUPPORTED BIT_28 2957 #define DT_OEM_001 BIT_29 2958 #define DT_ISP2200A BIT_30 2959 #define DT_EXTENDED_IDS BIT_31 2960 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1)) 2961 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 2962 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 2963 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 2964 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 2965 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 2966 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 2967 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 2968 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 2969 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 2970 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 2971 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 2972 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 2973 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 2974 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 2975 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 2976 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 2977 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 2978 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 2979 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 2980 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 2981 2982 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 2983 IS_QLA6312(ha) || IS_QLA6322(ha)) 2984 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 2985 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 2986 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 2987 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 2988 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 2989 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 2990 IS_QLA84XX(ha)) 2991 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 2992 IS_QLA8031(ha) || IS_QLA8044(ha)) 2993 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 2994 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 2995 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 2996 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 2997 IS_QLA8044(ha)) 2998 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) 2999 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 3000 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) 3001 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha)) 3002 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 3003 3004 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 3005 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 3006 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 3007 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 3008 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 3009 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 3010 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 3011 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha)) 3012 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) 3013 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 3014 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3015 ((ha)->fw_attributes_ext[0] & BIT_0)) 3016 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha)) 3017 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha)) 3018 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3019 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha)) 3020 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3021 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3022 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha)) 3023 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3024 3025 /* HBA serial number */ 3026 uint8_t serial0; 3027 uint8_t serial1; 3028 uint8_t serial2; 3029 3030 /* NVRAM configuration data */ 3031 #define MAX_NVRAM_SIZE 4096 3032 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 3033 uint16_t nvram_size; 3034 uint16_t nvram_base; 3035 void *nvram; 3036 uint16_t vpd_size; 3037 uint16_t vpd_base; 3038 void *vpd; 3039 3040 uint16_t loop_reset_delay; 3041 uint8_t retry_count; 3042 uint8_t login_timeout; 3043 uint16_t r_a_tov; 3044 int port_down_retry_count; 3045 uint8_t mbx_count; 3046 uint8_t aen_mbx_count; 3047 3048 uint32_t login_retry_count; 3049 /* SNS command interfaces. */ 3050 ms_iocb_entry_t *ms_iocb; 3051 dma_addr_t ms_iocb_dma; 3052 struct ct_sns_pkt *ct_sns; 3053 dma_addr_t ct_sns_dma; 3054 /* SNS command interfaces for 2200. */ 3055 struct sns_cmd_pkt *sns_cmd; 3056 dma_addr_t sns_cmd_dma; 3057 3058 #define SFP_DEV_SIZE 256 3059 #define SFP_BLOCK_SIZE 64 3060 void *sfp_data; 3061 dma_addr_t sfp_data_dma; 3062 3063 #define XGMAC_DATA_SIZE 4096 3064 void *xgmac_data; 3065 dma_addr_t xgmac_data_dma; 3066 3067 #define DCBX_TLV_DATA_SIZE 4096 3068 void *dcbx_tlv; 3069 dma_addr_t dcbx_tlv_dma; 3070 3071 struct task_struct *dpc_thread; 3072 uint8_t dpc_active; /* DPC routine is active */ 3073 3074 dma_addr_t gid_list_dma; 3075 struct gid_list_info *gid_list; 3076 int gid_list_info_size; 3077 3078 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3079 #define DMA_POOL_SIZE 256 3080 struct dma_pool *s_dma_pool; 3081 3082 dma_addr_t init_cb_dma; 3083 init_cb_t *init_cb; 3084 int init_cb_size; 3085 dma_addr_t ex_init_cb_dma; 3086 struct ex_init_cb_81xx *ex_init_cb; 3087 3088 void *async_pd; 3089 dma_addr_t async_pd_dma; 3090 3091 void *swl; 3092 3093 /* These are used by mailbox operations. */ 3094 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3095 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 3096 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 3097 3098 mbx_cmd_t *mcp; 3099 struct mbx_cmd_32 *mcp32; 3100 3101 unsigned long mbx_cmd_flags; 3102 #define MBX_INTERRUPT 1 3103 #define MBX_INTR_WAIT 2 3104 #define MBX_UPDATE_FLASH_ACTIVE 3 3105 3106 struct mutex vport_lock; /* Virtual port synchronization */ 3107 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 3108 struct completion mbx_cmd_comp; /* Serialize mbx access */ 3109 struct completion mbx_intr_comp; /* Used for completion notification */ 3110 struct completion dcbx_comp; /* For set port config notification */ 3111 struct completion lb_portup_comp; /* Used to wait for link up during 3112 * loopback */ 3113 #define DCBX_COMP_TIMEOUT 20 3114 #define LB_PORTUP_COMP_TIMEOUT 10 3115 3116 int notify_dcbx_comp; 3117 int notify_lb_portup_comp; 3118 struct mutex selflogin_lock; 3119 3120 /* Basic firmware related information. */ 3121 uint16_t fw_major_version; 3122 uint16_t fw_minor_version; 3123 uint16_t fw_subminor_version; 3124 uint16_t fw_attributes; 3125 uint16_t fw_attributes_h; 3126 uint16_t fw_attributes_ext[2]; 3127 uint32_t fw_memory_size; 3128 uint32_t fw_transfer_size; 3129 uint32_t fw_srisc_address; 3130 #define RISC_START_ADDRESS_2100 0x1000 3131 #define RISC_START_ADDRESS_2300 0x800 3132 #define RISC_START_ADDRESS_2400 0x100000 3133 uint16_t fw_xcb_count; 3134 uint16_t fw_iocb_count; 3135 3136 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 3137 uint8_t fw_seriallink_options[4]; 3138 uint16_t fw_seriallink_options24[4]; 3139 3140 uint8_t mpi_version[3]; 3141 uint32_t mpi_capabilities; 3142 uint8_t phy_version[3]; 3143 3144 /* Firmware dump information. */ 3145 struct qla2xxx_fw_dump *fw_dump; 3146 uint32_t fw_dump_len; 3147 int fw_dumped; 3148 int fw_dump_reading; 3149 dma_addr_t eft_dma; 3150 void *eft; 3151 /* Current size of mctp dump is 0x086064 bytes */ 3152 #define MCTP_DUMP_SIZE 0x086064 3153 dma_addr_t mctp_dump_dma; 3154 void *mctp_dump; 3155 int mctp_dumped; 3156 int mctp_dump_reading; 3157 uint32_t chain_offset; 3158 struct dentry *dfs_dir; 3159 struct dentry *dfs_fce; 3160 dma_addr_t fce_dma; 3161 void *fce; 3162 uint32_t fce_bufs; 3163 uint16_t fce_mb[8]; 3164 uint64_t fce_wr, fce_rd; 3165 struct mutex fce_mutex; 3166 3167 uint32_t pci_attr; 3168 uint16_t chip_revision; 3169 3170 uint16_t product_id[4]; 3171 3172 uint8_t model_number[16+1]; 3173 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 3174 char model_desc[80]; 3175 uint8_t adapter_id[16+1]; 3176 3177 /* Option ROM information. */ 3178 char *optrom_buffer; 3179 uint32_t optrom_size; 3180 int optrom_state; 3181 #define QLA_SWAITING 0 3182 #define QLA_SREADING 1 3183 #define QLA_SWRITING 2 3184 uint32_t optrom_region_start; 3185 uint32_t optrom_region_size; 3186 3187 /* PCI expansion ROM image information. */ 3188 #define ROM_CODE_TYPE_BIOS 0 3189 #define ROM_CODE_TYPE_FCODE 1 3190 #define ROM_CODE_TYPE_EFI 3 3191 uint8_t bios_revision[2]; 3192 uint8_t efi_revision[2]; 3193 uint8_t fcode_revision[16]; 3194 uint32_t fw_revision[4]; 3195 3196 uint32_t gold_fw_version[4]; 3197 3198 /* Offsets for flash/nvram access (set to ~0 if not used). */ 3199 uint32_t flash_conf_off; 3200 uint32_t flash_data_off; 3201 uint32_t nvram_conf_off; 3202 uint32_t nvram_data_off; 3203 3204 uint32_t fdt_wrt_disable; 3205 uint32_t fdt_wrt_enable; 3206 uint32_t fdt_erase_cmd; 3207 uint32_t fdt_block_size; 3208 uint32_t fdt_unprotect_sec_cmd; 3209 uint32_t fdt_protect_sec_cmd; 3210 uint32_t fdt_wrt_sts_reg_cmd; 3211 3212 uint32_t flt_region_flt; 3213 uint32_t flt_region_fdt; 3214 uint32_t flt_region_boot; 3215 uint32_t flt_region_fw; 3216 uint32_t flt_region_vpd_nvram; 3217 uint32_t flt_region_vpd; 3218 uint32_t flt_region_nvram; 3219 uint32_t flt_region_npiv_conf; 3220 uint32_t flt_region_gold_fw; 3221 uint32_t flt_region_fcp_prio; 3222 uint32_t flt_region_bootload; 3223 3224 /* Needed for BEACON */ 3225 uint16_t beacon_blink_led; 3226 uint8_t beacon_color_state; 3227 #define QLA_LED_GRN_ON 0x01 3228 #define QLA_LED_YLW_ON 0x02 3229 #define QLA_LED_ABR_ON 0x04 3230 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 3231 /* ISP2322: red, green, amber. */ 3232 uint16_t zio_mode; 3233 uint16_t zio_timer; 3234 3235 struct qla_msix_entry *msix_entries; 3236 3237 struct list_head vp_list; /* list of VP */ 3238 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 3239 sizeof(unsigned long)]; 3240 uint16_t num_vhosts; /* number of vports created */ 3241 uint16_t num_vsans; /* number of vsan created */ 3242 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 3243 int cur_vport_count; 3244 3245 struct qla_chip_state_84xx *cs84xx; 3246 struct qla_statistics qla_stats; 3247 struct isp_operations *isp_ops; 3248 struct workqueue_struct *wq; 3249 struct qlfc_fw fw_buf; 3250 3251 /* FCP_CMND priority support */ 3252 struct qla_fcp_prio_cfg *fcp_prio_cfg; 3253 3254 struct dma_pool *dl_dma_pool; 3255 #define DSD_LIST_DMA_POOL_SIZE 512 3256 3257 struct dma_pool *fcp_cmnd_dma_pool; 3258 mempool_t *ctx_mempool; 3259 #define FCP_CMND_DMA_POOL_SIZE 512 3260 3261 unsigned long nx_pcibase; /* Base I/O address */ 3262 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */ 3263 unsigned long nxdb_wr_ptr; /* Door bell write pointer */ 3264 3265 uint32_t crb_win; 3266 uint32_t curr_window; 3267 uint32_t ddr_mn_window; 3268 unsigned long mn_win_crb; 3269 unsigned long ms_win_crb; 3270 int qdr_sn_window; 3271 uint32_t fcoe_dev_init_timeout; 3272 uint32_t fcoe_reset_timeout; 3273 rwlock_t hw_lock; 3274 uint16_t portnum; /* port number */ 3275 int link_width; 3276 struct fw_blob *hablob; 3277 struct qla82xx_legacy_intr_set nx_legacy_intr; 3278 3279 uint16_t gbl_dsd_inuse; 3280 uint16_t gbl_dsd_avail; 3281 struct list_head gbl_dsd_list; 3282 #define NUM_DSD_CHAIN 4096 3283 3284 uint8_t fw_type; 3285 __le32 file_prd_off; /* File firmware product offset */ 3286 3287 uint32_t md_template_size; 3288 void *md_tmplt_hdr; 3289 dma_addr_t md_tmplt_hdr_dma; 3290 void *md_dump; 3291 uint32_t md_dump_size; 3292 3293 void *loop_id_map; 3294 3295 /* QLA83XX IDC specific fields */ 3296 uint32_t idc_audit_ts; 3297 uint32_t idc_extend_tmo; 3298 3299 /* DPC low-priority workqueue */ 3300 struct workqueue_struct *dpc_lp_wq; 3301 struct work_struct idc_aen; 3302 /* DPC high-priority workqueue */ 3303 struct workqueue_struct *dpc_hp_wq; 3304 struct work_struct nic_core_reset; 3305 struct work_struct idc_state_handler; 3306 struct work_struct nic_core_unrecoverable; 3307 struct work_struct board_disable; 3308 3309 struct mr_data_fx00 mr; 3310 3311 struct qlt_hw_data tgt; 3312 }; 3313 3314 /* 3315 * Qlogic scsi host structure 3316 */ 3317 typedef struct scsi_qla_host { 3318 struct list_head list; 3319 struct list_head vp_fcports; /* list of fcports */ 3320 struct list_head work_list; 3321 spinlock_t work_lock; 3322 3323 /* Commonly used flags and state information. */ 3324 struct Scsi_Host *host; 3325 unsigned long host_no; 3326 uint8_t host_str[16]; 3327 3328 volatile struct { 3329 uint32_t init_done :1; 3330 uint32_t online :1; 3331 uint32_t reset_active :1; 3332 3333 uint32_t management_server_logged_in :1; 3334 uint32_t process_response_queue :1; 3335 uint32_t difdix_supported:1; 3336 uint32_t delete_progress:1; 3337 3338 uint32_t fw_tgt_reported:1; 3339 } flags; 3340 3341 atomic_t loop_state; 3342 #define LOOP_TIMEOUT 1 3343 #define LOOP_DOWN 2 3344 #define LOOP_UP 3 3345 #define LOOP_UPDATE 4 3346 #define LOOP_READY 5 3347 #define LOOP_DEAD 6 3348 3349 unsigned long dpc_flags; 3350 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 3351 #define RESET_ACTIVE 1 3352 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 3353 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 3354 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 3355 #define LOOP_RESYNC_ACTIVE 5 3356 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 3357 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 3358 #define RELOGIN_NEEDED 8 3359 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 3360 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 3361 #define BEACON_BLINK_NEEDED 11 3362 #define REGISTER_FDMI_NEEDED 12 3363 #define FCPORT_UPDATE_NEEDED 13 3364 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 3365 #define UNLOADING 15 3366 #define NPIV_CONFIG_NEEDED 16 3367 #define ISP_UNRECOVERABLE 17 3368 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 3369 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 3370 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 3371 #define SCR_PENDING 21 /* SCR in target mode */ 3372 #define PORT_UPDATE_NEEDED 22 3373 #define FX00_RESET_RECOVERY 23 3374 #define FX00_TARGET_SCAN 24 3375 #define FX00_CRITEMP_RECOVERY 25 3376 #define FX00_HOST_INFO_RESEND 26 3377 3378 uint32_t device_flags; 3379 #define SWITCH_FOUND BIT_0 3380 #define DFLG_NO_CABLE BIT_1 3381 #define DFLG_DEV_FAILED BIT_5 3382 3383 /* ISP configuration data. */ 3384 uint16_t loop_id; /* Host adapter loop id */ 3385 uint16_t self_login_loop_id; /* host adapter loop id 3386 * get it on self login 3387 */ 3388 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 3389 * no need of allocating it for 3390 * each command 3391 */ 3392 3393 port_id_t d_id; /* Host adapter port id */ 3394 uint8_t marker_needed; 3395 uint16_t mgmt_svr_loop_id; 3396 3397 3398 3399 /* Timeout timers. */ 3400 uint8_t loop_down_abort_time; /* port down timer */ 3401 atomic_t loop_down_timer; /* loop down timer */ 3402 uint8_t link_down_timeout; /* link down timeout */ 3403 3404 uint32_t timer_active; 3405 struct timer_list timer; 3406 3407 uint8_t node_name[WWN_SIZE]; 3408 uint8_t port_name[WWN_SIZE]; 3409 uint8_t fabric_node_name[WWN_SIZE]; 3410 3411 uint16_t fcoe_vlan_id; 3412 uint16_t fcoe_fcf_idx; 3413 uint8_t fcoe_vn_port_mac[6]; 3414 3415 uint32_t vp_abort_cnt; 3416 3417 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 3418 uint16_t vp_idx; /* vport ID */ 3419 3420 unsigned long vp_flags; 3421 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 3422 #define VP_CREATE_NEEDED 1 3423 #define VP_BIND_NEEDED 2 3424 #define VP_DELETE_NEEDED 3 3425 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 3426 atomic_t vp_state; 3427 #define VP_OFFLINE 0 3428 #define VP_ACTIVE 1 3429 #define VP_FAILED 2 3430 // #define VP_DISABLE 3 3431 uint16_t vp_err_state; 3432 uint16_t vp_prev_err_state; 3433 #define VP_ERR_UNKWN 0 3434 #define VP_ERR_PORTDWN 1 3435 #define VP_ERR_FAB_UNSUPPORTED 2 3436 #define VP_ERR_FAB_NORESOURCES 3 3437 #define VP_ERR_FAB_LOGOUT 4 3438 #define VP_ERR_ADAP_NORESOURCES 5 3439 struct qla_hw_data *hw; 3440 struct scsi_qlt_host vha_tgt; 3441 struct req_que *req; 3442 int fw_heartbeat_counter; 3443 int seconds_since_last_heartbeat; 3444 struct fc_host_statistics fc_host_stat; 3445 struct qla_statistics qla_stats; 3446 struct bidi_statistics bidi_stats; 3447 3448 atomic_t vref_count; 3449 struct qla8044_reset_template reset_tmplt; 3450 } scsi_qla_host_t; 3451 3452 #define SET_VP_IDX 1 3453 #define SET_AL_PA 2 3454 #define RESET_VP_IDX 3 3455 #define RESET_AL_PA 4 3456 struct qla_tgt_vp_map { 3457 uint8_t idx; 3458 scsi_qla_host_t *vha; 3459 }; 3460 3461 /* 3462 * Macros to help code, maintain, etc. 3463 */ 3464 #define LOOP_TRANSITION(ha) \ 3465 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3466 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 3467 atomic_read(&ha->loop_state) == LOOP_DOWN) 3468 3469 #define STATE_TRANSITION(ha) \ 3470 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3471 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 3472 3473 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 3474 atomic_inc(&__vha->vref_count); \ 3475 mb(); \ 3476 if (__vha->flags.delete_progress) { \ 3477 atomic_dec(&__vha->vref_count); \ 3478 __bail = 1; \ 3479 } else { \ 3480 __bail = 0; \ 3481 } \ 3482 } while (0) 3483 3484 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 3485 atomic_dec(&__vha->vref_count); \ 3486 } while (0) 3487 3488 /* 3489 * qla2x00 local function return status codes 3490 */ 3491 #define MBS_MASK 0x3fff 3492 3493 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 3494 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 3495 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 3496 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 3497 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 3498 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 3499 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 3500 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 3501 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 3502 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 3503 3504 #define QLA_FUNCTION_TIMEOUT 0x100 3505 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 3506 #define QLA_FUNCTION_FAILED 0x102 3507 #define QLA_MEMORY_ALLOC_FAILED 0x103 3508 #define QLA_LOCK_TIMEOUT 0x104 3509 #define QLA_ABORTED 0x105 3510 #define QLA_SUSPENDED 0x106 3511 #define QLA_BUSY 0x107 3512 #define QLA_ALREADY_REGISTERED 0x109 3513 3514 #define NVRAM_DELAY() udelay(10) 3515 3516 /* 3517 * Flash support definitions 3518 */ 3519 #define OPTROM_SIZE_2300 0x20000 3520 #define OPTROM_SIZE_2322 0x100000 3521 #define OPTROM_SIZE_24XX 0x100000 3522 #define OPTROM_SIZE_25XX 0x200000 3523 #define OPTROM_SIZE_81XX 0x400000 3524 #define OPTROM_SIZE_82XX 0x800000 3525 #define OPTROM_SIZE_83XX 0x1000000 3526 3527 #define OPTROM_BURST_SIZE 0x1000 3528 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3529 3530 #define QLA_DSDS_PER_IOCB 37 3531 3532 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 3533 3534 #define QLA_SG_ALL 1024 3535 3536 enum nexus_wait_type { 3537 WAIT_HOST = 0, 3538 WAIT_TARGET, 3539 WAIT_LUN, 3540 }; 3541 3542 #include "qla_gbl.h" 3543 #include "qla_dbg.h" 3544 #include "qla_inline.h" 3545 #endif 3546