1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 #include <scsi/scsi_bsg_fc.h> 35 36 #include "qla_bsg.h" 37 #include "qla_nx.h" 38 #include "qla_nx2.h" 39 #define QLA2XXX_DRIVER_NAME "qla2xxx" 40 #define QLA2XXX_APIDEV "ql2xapidev" 41 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 42 43 /* 44 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 45 * but that's fine as we don't look at the last 24 ones for 46 * ISP2100 HBAs. 47 */ 48 #define MAILBOX_REGISTER_COUNT_2100 8 49 #define MAILBOX_REGISTER_COUNT_2200 24 50 #define MAILBOX_REGISTER_COUNT 32 51 52 #define QLA2200A_RISC_ROM_VER 4 53 #define FPM_2300 6 54 #define FPM_2310 7 55 56 #include "qla_settings.h" 57 58 /* 59 * Data bit definitions 60 */ 61 #define BIT_0 0x1 62 #define BIT_1 0x2 63 #define BIT_2 0x4 64 #define BIT_3 0x8 65 #define BIT_4 0x10 66 #define BIT_5 0x20 67 #define BIT_6 0x40 68 #define BIT_7 0x80 69 #define BIT_8 0x100 70 #define BIT_9 0x200 71 #define BIT_10 0x400 72 #define BIT_11 0x800 73 #define BIT_12 0x1000 74 #define BIT_13 0x2000 75 #define BIT_14 0x4000 76 #define BIT_15 0x8000 77 #define BIT_16 0x10000 78 #define BIT_17 0x20000 79 #define BIT_18 0x40000 80 #define BIT_19 0x80000 81 #define BIT_20 0x100000 82 #define BIT_21 0x200000 83 #define BIT_22 0x400000 84 #define BIT_23 0x800000 85 #define BIT_24 0x1000000 86 #define BIT_25 0x2000000 87 #define BIT_26 0x4000000 88 #define BIT_27 0x8000000 89 #define BIT_28 0x10000000 90 #define BIT_29 0x20000000 91 #define BIT_30 0x40000000 92 #define BIT_31 0x80000000 93 94 #define LSB(x) ((uint8_t)(x)) 95 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 96 97 #define LSW(x) ((uint16_t)(x)) 98 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 99 100 #define LSD(x) ((uint32_t)((uint64_t)(x))) 101 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 102 103 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 104 105 /* 106 * I/O register 107 */ 108 109 #define RD_REG_BYTE(addr) readb(addr) 110 #define RD_REG_WORD(addr) readw(addr) 111 #define RD_REG_DWORD(addr) readl(addr) 112 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 113 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 114 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 115 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 116 #define WRT_REG_WORD(addr, data) writew(data,addr) 117 #define WRT_REG_DWORD(addr, data) writel(data,addr) 118 119 /* 120 * ISP83XX specific remote register addresses 121 */ 122 #define QLA83XX_LED_PORT0 0x00201320 123 #define QLA83XX_LED_PORT1 0x00201328 124 #define QLA83XX_IDC_DEV_STATE 0x22102384 125 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 126 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 127 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 128 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 129 #define QLA83XX_IDC_CONTROL 0x22102390 130 #define QLA83XX_IDC_AUDIT 0x22102394 131 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 132 #define QLA83XX_DRIVER_LOCKID 0x22102104 133 #define QLA83XX_DRIVER_LOCK 0x8111c028 134 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 135 #define QLA83XX_FLASH_LOCKID 0x22102100 136 #define QLA83XX_FLASH_LOCK 0x8111c010 137 #define QLA83XX_FLASH_UNLOCK 0x8111c014 138 #define QLA83XX_DEV_PARTINFO1 0x221023e0 139 #define QLA83XX_DEV_PARTINFO2 0x221023e4 140 #define QLA83XX_FW_HEARTBEAT 0x221020b0 141 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 142 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 143 144 /* 83XX: Macros defining 8200 AEN Reason codes */ 145 #define IDC_DEVICE_STATE_CHANGE BIT_0 146 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 147 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 148 #define IDC_HEARTBEAT_FAILURE BIT_3 149 150 /* 83XX: Macros defining 8200 AEN Error-levels */ 151 #define ERR_LEVEL_NON_FATAL 0x1 152 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 153 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 154 155 /* 83XX: Macros for IDC Version */ 156 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 157 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 158 159 /* 83XX: Macros for scheduling dpc tasks */ 160 #define QLA83XX_NIC_CORE_RESET 0x1 161 #define QLA83XX_IDC_STATE_HANDLER 0x2 162 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 163 164 /* 83XX: Macros for defining IDC-Control bits */ 165 #define QLA83XX_IDC_RESET_DISABLED BIT_0 166 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 167 168 /* 83XX: Macros for different timeouts */ 169 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 170 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 171 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 172 173 /* 83XX: Macros for defining class in DEV-Partition Info register */ 174 #define QLA83XX_CLASS_TYPE_NONE 0x0 175 #define QLA83XX_CLASS_TYPE_NIC 0x1 176 #define QLA83XX_CLASS_TYPE_FCOE 0x2 177 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 178 179 /* 83XX: Macros for IDC Lock-Recovery stages */ 180 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 181 * lock-recovery 182 */ 183 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 184 185 /* 83XX: Macros for IDC Audit type */ 186 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 187 * dev-state change to NEED-RESET 188 * or NEED-QUIESCENT 189 */ 190 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 191 * reset-recovery completion is 192 * second 193 */ 194 /* ISP2031: Values for laser on/off */ 195 #define PORT_0_2031 0x00201340 196 #define PORT_1_2031 0x00201350 197 #define LASER_ON_2031 0x01800100 198 #define LASER_OFF_2031 0x01800180 199 200 /* 201 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 202 * 133Mhz slot. 203 */ 204 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 205 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 206 207 /* 208 * Fibre Channel device definitions. 209 */ 210 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 211 #define MAX_FIBRE_DEVICES_2100 512 212 #define MAX_FIBRE_DEVICES_2400 2048 213 #define MAX_FIBRE_DEVICES_LOOP 128 214 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 215 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 216 #define MAX_FIBRE_LUNS 0xFFFF 217 #define MAX_HOST_COUNT 16 218 219 /* 220 * Host adapter default definitions. 221 */ 222 #define MAX_BUSES 1 /* We only have one bus today */ 223 #define MIN_LUNS 8 224 #define MAX_LUNS MAX_FIBRE_LUNS 225 #define MAX_CMDS_PER_LUN 255 226 227 /* 228 * Fibre Channel device definitions. 229 */ 230 #define SNS_LAST_LOOP_ID_2100 0xfe 231 #define SNS_LAST_LOOP_ID_2300 0x7ff 232 233 #define LAST_LOCAL_LOOP_ID 0x7d 234 #define SNS_FL_PORT 0x7e 235 #define FABRIC_CONTROLLER 0x7f 236 #define SIMPLE_NAME_SERVER 0x80 237 #define SNS_FIRST_LOOP_ID 0x81 238 #define MANAGEMENT_SERVER 0xfe 239 #define BROADCAST 0xff 240 241 /* 242 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 243 * valid range of an N-PORT id is 0 through 0x7ef. 244 */ 245 #define NPH_LAST_HANDLE 0x7ef 246 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ 247 #define NPH_SNS 0x7fc /* FFFFFC */ 248 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 249 #define NPH_F_PORT 0x7fe /* FFFFFE */ 250 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 251 252 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 253 #include "qla_fw.h" 254 /* 255 * Timeout timer counts in seconds 256 */ 257 #define PORT_RETRY_TIME 1 258 #define LOOP_DOWN_TIMEOUT 60 259 #define LOOP_DOWN_TIME 255 /* 240 */ 260 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 261 262 #define DEFAULT_OUTSTANDING_COMMANDS 1024 263 #define MIN_OUTSTANDING_COMMANDS 128 264 265 /* ISP request and response entry counts (37-65535) */ 266 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 267 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 268 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 269 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 270 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 271 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 272 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 273 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 274 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 275 276 struct req_que; 277 struct qla_tgt_sess; 278 279 /* 280 * (sd.h is not exported, hence local inclusion) 281 * Data Integrity Field tuple. 282 */ 283 struct sd_dif_tuple { 284 __be16 guard_tag; /* Checksum */ 285 __be16 app_tag; /* Opaque storage */ 286 __be32 ref_tag; /* Target LBA or indirect LBA */ 287 }; 288 289 /* 290 * SCSI Request Block 291 */ 292 struct srb_cmd { 293 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 294 uint32_t request_sense_length; 295 uint32_t fw_sense_length; 296 uint8_t *request_sense_ptr; 297 void *ctx; 298 }; 299 300 /* 301 * SRB flag definitions 302 */ 303 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 304 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 305 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 306 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 307 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 308 309 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 310 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 311 312 /* 313 * SRB extensions. 314 */ 315 struct srb_iocb { 316 union { 317 struct { 318 uint16_t flags; 319 #define SRB_LOGIN_RETRIED BIT_0 320 #define SRB_LOGIN_COND_PLOGI BIT_1 321 #define SRB_LOGIN_SKIP_PRLI BIT_2 322 uint16_t data[2]; 323 } logio; 324 struct { 325 /* 326 * Values for flags field below are as 327 * defined in tsk_mgmt_entry struct 328 * for control_flags field in qla_fw.h. 329 */ 330 uint64_t lun; 331 uint32_t flags; 332 uint32_t data; 333 struct completion comp; 334 __le16 comp_status; 335 } tmf; 336 struct { 337 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 338 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 339 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 340 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 341 #define FXDISC_TIMEOUT 20 342 uint8_t flags; 343 uint32_t req_len; 344 uint32_t rsp_len; 345 void *req_addr; 346 void *rsp_addr; 347 dma_addr_t req_dma_handle; 348 dma_addr_t rsp_dma_handle; 349 __le32 adapter_id; 350 __le32 adapter_id_hi; 351 __le16 req_func_type; 352 __le32 req_data; 353 __le32 req_data_extra; 354 __le32 result; 355 __le32 seq_number; 356 __le16 fw_flags; 357 struct completion fxiocb_comp; 358 __le32 reserved_0; 359 uint8_t reserved_1; 360 } fxiocb; 361 struct { 362 uint32_t cmd_hndl; 363 __le16 comp_status; 364 struct completion comp; 365 } abt; 366 } u; 367 368 struct timer_list timer; 369 void (*timeout)(void *); 370 }; 371 372 /* Values for srb_ctx type */ 373 #define SRB_LOGIN_CMD 1 374 #define SRB_LOGOUT_CMD 2 375 #define SRB_ELS_CMD_RPT 3 376 #define SRB_ELS_CMD_HST 4 377 #define SRB_CT_CMD 5 378 #define SRB_ADISC_CMD 6 379 #define SRB_TM_CMD 7 380 #define SRB_SCSI_CMD 8 381 #define SRB_BIDI_CMD 9 382 #define SRB_FXIOCB_DCMD 10 383 #define SRB_FXIOCB_BCMD 11 384 #define SRB_ABT_CMD 12 385 386 387 typedef struct srb { 388 atomic_t ref_count; 389 struct fc_port *fcport; 390 uint32_t handle; 391 uint16_t flags; 392 uint16_t type; 393 char *name; 394 int iocbs; 395 union { 396 struct srb_iocb iocb_cmd; 397 struct fc_bsg_job *bsg_job; 398 struct srb_cmd scmd; 399 } u; 400 void (*done)(void *, void *, int); 401 void (*free)(void *, void *); 402 } srb_t; 403 404 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 405 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 406 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 407 408 #define GET_CMD_SENSE_LEN(sp) \ 409 (sp->u.scmd.request_sense_length) 410 #define SET_CMD_SENSE_LEN(sp, len) \ 411 (sp->u.scmd.request_sense_length = len) 412 #define GET_CMD_SENSE_PTR(sp) \ 413 (sp->u.scmd.request_sense_ptr) 414 #define SET_CMD_SENSE_PTR(sp, ptr) \ 415 (sp->u.scmd.request_sense_ptr = ptr) 416 #define GET_FW_SENSE_LEN(sp) \ 417 (sp->u.scmd.fw_sense_length) 418 #define SET_FW_SENSE_LEN(sp, len) \ 419 (sp->u.scmd.fw_sense_length = len) 420 421 struct msg_echo_lb { 422 dma_addr_t send_dma; 423 dma_addr_t rcv_dma; 424 uint16_t req_sg_cnt; 425 uint16_t rsp_sg_cnt; 426 uint16_t options; 427 uint32_t transfer_size; 428 uint32_t iteration_count; 429 }; 430 431 /* 432 * ISP I/O Register Set structure definitions. 433 */ 434 struct device_reg_2xxx { 435 uint16_t flash_address; /* Flash BIOS address */ 436 uint16_t flash_data; /* Flash BIOS data */ 437 uint16_t unused_1[1]; /* Gap */ 438 uint16_t ctrl_status; /* Control/Status */ 439 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 440 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 441 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 442 443 uint16_t ictrl; /* Interrupt control */ 444 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 445 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 446 447 uint16_t istatus; /* Interrupt status */ 448 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 449 450 uint16_t semaphore; /* Semaphore */ 451 uint16_t nvram; /* NVRAM register. */ 452 #define NVR_DESELECT 0 453 #define NVR_BUSY BIT_15 454 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 455 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 456 #define NVR_DATA_IN BIT_3 457 #define NVR_DATA_OUT BIT_2 458 #define NVR_SELECT BIT_1 459 #define NVR_CLOCK BIT_0 460 461 #define NVR_WAIT_CNT 20000 462 463 union { 464 struct { 465 uint16_t mailbox0; 466 uint16_t mailbox1; 467 uint16_t mailbox2; 468 uint16_t mailbox3; 469 uint16_t mailbox4; 470 uint16_t mailbox5; 471 uint16_t mailbox6; 472 uint16_t mailbox7; 473 uint16_t unused_2[59]; /* Gap */ 474 } __attribute__((packed)) isp2100; 475 struct { 476 /* Request Queue */ 477 uint16_t req_q_in; /* In-Pointer */ 478 uint16_t req_q_out; /* Out-Pointer */ 479 /* Response Queue */ 480 uint16_t rsp_q_in; /* In-Pointer */ 481 uint16_t rsp_q_out; /* Out-Pointer */ 482 483 /* RISC to Host Status */ 484 uint32_t host_status; 485 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 486 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 487 488 /* Host to Host Semaphore */ 489 uint16_t host_semaphore; 490 uint16_t unused_3[17]; /* Gap */ 491 uint16_t mailbox0; 492 uint16_t mailbox1; 493 uint16_t mailbox2; 494 uint16_t mailbox3; 495 uint16_t mailbox4; 496 uint16_t mailbox5; 497 uint16_t mailbox6; 498 uint16_t mailbox7; 499 uint16_t mailbox8; 500 uint16_t mailbox9; 501 uint16_t mailbox10; 502 uint16_t mailbox11; 503 uint16_t mailbox12; 504 uint16_t mailbox13; 505 uint16_t mailbox14; 506 uint16_t mailbox15; 507 uint16_t mailbox16; 508 uint16_t mailbox17; 509 uint16_t mailbox18; 510 uint16_t mailbox19; 511 uint16_t mailbox20; 512 uint16_t mailbox21; 513 uint16_t mailbox22; 514 uint16_t mailbox23; 515 uint16_t mailbox24; 516 uint16_t mailbox25; 517 uint16_t mailbox26; 518 uint16_t mailbox27; 519 uint16_t mailbox28; 520 uint16_t mailbox29; 521 uint16_t mailbox30; 522 uint16_t mailbox31; 523 uint16_t fb_cmd; 524 uint16_t unused_4[10]; /* Gap */ 525 } __attribute__((packed)) isp2300; 526 } u; 527 528 uint16_t fpm_diag_config; 529 uint16_t unused_5[0x4]; /* Gap */ 530 uint16_t risc_hw; 531 uint16_t unused_5_1; /* Gap */ 532 uint16_t pcr; /* Processor Control Register. */ 533 uint16_t unused_6[0x5]; /* Gap */ 534 uint16_t mctr; /* Memory Configuration and Timing. */ 535 uint16_t unused_7[0x3]; /* Gap */ 536 uint16_t fb_cmd_2100; /* Unused on 23XX */ 537 uint16_t unused_8[0x3]; /* Gap */ 538 uint16_t hccr; /* Host command & control register. */ 539 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 540 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 541 /* HCCR commands */ 542 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 543 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 544 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 545 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 546 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 547 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 548 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 549 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 550 551 uint16_t unused_9[5]; /* Gap */ 552 uint16_t gpiod; /* GPIO Data register. */ 553 uint16_t gpioe; /* GPIO Enable register. */ 554 #define GPIO_LED_MASK 0x00C0 555 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 556 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 557 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 558 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 559 #define GPIO_LED_ALL_OFF 0x0000 560 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 561 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 562 563 union { 564 struct { 565 uint16_t unused_10[8]; /* Gap */ 566 uint16_t mailbox8; 567 uint16_t mailbox9; 568 uint16_t mailbox10; 569 uint16_t mailbox11; 570 uint16_t mailbox12; 571 uint16_t mailbox13; 572 uint16_t mailbox14; 573 uint16_t mailbox15; 574 uint16_t mailbox16; 575 uint16_t mailbox17; 576 uint16_t mailbox18; 577 uint16_t mailbox19; 578 uint16_t mailbox20; 579 uint16_t mailbox21; 580 uint16_t mailbox22; 581 uint16_t mailbox23; /* Also probe reg. */ 582 } __attribute__((packed)) isp2200; 583 } u_end; 584 }; 585 586 struct device_reg_25xxmq { 587 uint32_t req_q_in; 588 uint32_t req_q_out; 589 uint32_t rsp_q_in; 590 uint32_t rsp_q_out; 591 uint32_t atio_q_in; 592 uint32_t atio_q_out; 593 }; 594 595 596 struct device_reg_fx00 { 597 uint32_t mailbox0; /* 00 */ 598 uint32_t mailbox1; /* 04 */ 599 uint32_t mailbox2; /* 08 */ 600 uint32_t mailbox3; /* 0C */ 601 uint32_t mailbox4; /* 10 */ 602 uint32_t mailbox5; /* 14 */ 603 uint32_t mailbox6; /* 18 */ 604 uint32_t mailbox7; /* 1C */ 605 uint32_t mailbox8; /* 20 */ 606 uint32_t mailbox9; /* 24 */ 607 uint32_t mailbox10; /* 28 */ 608 uint32_t mailbox11; 609 uint32_t mailbox12; 610 uint32_t mailbox13; 611 uint32_t mailbox14; 612 uint32_t mailbox15; 613 uint32_t mailbox16; 614 uint32_t mailbox17; 615 uint32_t mailbox18; 616 uint32_t mailbox19; 617 uint32_t mailbox20; 618 uint32_t mailbox21; 619 uint32_t mailbox22; 620 uint32_t mailbox23; 621 uint32_t mailbox24; 622 uint32_t mailbox25; 623 uint32_t mailbox26; 624 uint32_t mailbox27; 625 uint32_t mailbox28; 626 uint32_t mailbox29; 627 uint32_t mailbox30; 628 uint32_t mailbox31; 629 uint32_t aenmailbox0; 630 uint32_t aenmailbox1; 631 uint32_t aenmailbox2; 632 uint32_t aenmailbox3; 633 uint32_t aenmailbox4; 634 uint32_t aenmailbox5; 635 uint32_t aenmailbox6; 636 uint32_t aenmailbox7; 637 /* Request Queue. */ 638 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 639 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 640 /* Response Queue. */ 641 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 642 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 643 /* Init values shadowed on FW Up Event */ 644 uint32_t initval0; /* B0 */ 645 uint32_t initval1; /* B4 */ 646 uint32_t initval2; /* B8 */ 647 uint32_t initval3; /* BC */ 648 uint32_t initval4; /* C0 */ 649 uint32_t initval5; /* C4 */ 650 uint32_t initval6; /* C8 */ 651 uint32_t initval7; /* CC */ 652 uint32_t fwheartbeat; /* D0 */ 653 uint32_t pseudoaen; /* D4 */ 654 }; 655 656 657 658 typedef union { 659 struct device_reg_2xxx isp; 660 struct device_reg_24xx isp24; 661 struct device_reg_25xxmq isp25mq; 662 struct device_reg_82xx isp82; 663 struct device_reg_fx00 ispfx00; 664 } __iomem device_reg_t; 665 666 #define ISP_REQ_Q_IN(ha, reg) \ 667 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 668 &(reg)->u.isp2100.mailbox4 : \ 669 &(reg)->u.isp2300.req_q_in) 670 #define ISP_REQ_Q_OUT(ha, reg) \ 671 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 672 &(reg)->u.isp2100.mailbox4 : \ 673 &(reg)->u.isp2300.req_q_out) 674 #define ISP_RSP_Q_IN(ha, reg) \ 675 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 676 &(reg)->u.isp2100.mailbox5 : \ 677 &(reg)->u.isp2300.rsp_q_in) 678 #define ISP_RSP_Q_OUT(ha, reg) \ 679 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 680 &(reg)->u.isp2100.mailbox5 : \ 681 &(reg)->u.isp2300.rsp_q_out) 682 683 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 684 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 685 686 #define MAILBOX_REG(ha, reg, num) \ 687 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 688 (num < 8 ? \ 689 &(reg)->u.isp2100.mailbox0 + (num) : \ 690 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 691 &(reg)->u.isp2300.mailbox0 + (num)) 692 #define RD_MAILBOX_REG(ha, reg, num) \ 693 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 694 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 695 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 696 697 #define FB_CMD_REG(ha, reg) \ 698 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 699 &(reg)->fb_cmd_2100 : \ 700 &(reg)->u.isp2300.fb_cmd) 701 #define RD_FB_CMD_REG(ha, reg) \ 702 RD_REG_WORD(FB_CMD_REG(ha, reg)) 703 #define WRT_FB_CMD_REG(ha, reg, data) \ 704 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 705 706 typedef struct { 707 uint32_t out_mb; /* outbound from driver */ 708 uint32_t in_mb; /* Incoming from RISC */ 709 uint16_t mb[MAILBOX_REGISTER_COUNT]; 710 long buf_size; 711 void *bufp; 712 uint32_t tov; 713 uint8_t flags; 714 #define MBX_DMA_IN BIT_0 715 #define MBX_DMA_OUT BIT_1 716 #define IOCTL_CMD BIT_2 717 } mbx_cmd_t; 718 719 struct mbx_cmd_32 { 720 uint32_t out_mb; /* outbound from driver */ 721 uint32_t in_mb; /* Incoming from RISC */ 722 uint32_t mb[MAILBOX_REGISTER_COUNT]; 723 long buf_size; 724 void *bufp; 725 uint32_t tov; 726 uint8_t flags; 727 #define MBX_DMA_IN BIT_0 728 #define MBX_DMA_OUT BIT_1 729 #define IOCTL_CMD BIT_2 730 }; 731 732 733 #define MBX_TOV_SECONDS 30 734 735 /* 736 * ISP product identification definitions in mailboxes after reset. 737 */ 738 #define PROD_ID_1 0x4953 739 #define PROD_ID_2 0x0000 740 #define PROD_ID_2a 0x5020 741 #define PROD_ID_3 0x2020 742 743 /* 744 * ISP mailbox Self-Test status codes 745 */ 746 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 747 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 748 #define MBS_BUSY 4 /* Busy. */ 749 750 /* 751 * ISP mailbox command complete status codes 752 */ 753 #define MBS_COMMAND_COMPLETE 0x4000 754 #define MBS_INVALID_COMMAND 0x4001 755 #define MBS_HOST_INTERFACE_ERROR 0x4002 756 #define MBS_TEST_FAILED 0x4003 757 #define MBS_COMMAND_ERROR 0x4005 758 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 759 #define MBS_PORT_ID_USED 0x4007 760 #define MBS_LOOP_ID_USED 0x4008 761 #define MBS_ALL_IDS_IN_USE 0x4009 762 #define MBS_NOT_LOGGED_IN 0x400A 763 #define MBS_LINK_DOWN_ERROR 0x400B 764 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 765 766 /* 767 * ISP mailbox asynchronous event status codes 768 */ 769 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 770 #define MBA_RESET 0x8001 /* Reset Detected. */ 771 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 772 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 773 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 774 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 775 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 776 /* occurred. */ 777 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 778 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 779 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 780 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 781 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 782 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 783 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 784 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 785 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 786 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 787 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 788 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 789 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 790 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 791 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 792 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 793 /* used. */ 794 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 795 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 796 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 797 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 798 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 799 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 800 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 801 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 802 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 803 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 804 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 805 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 806 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 807 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 808 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 809 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 810 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 811 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 812 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 813 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 814 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 815 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 816 Notification */ 817 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 818 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 819 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 820 /* 83XX FCoE specific */ 821 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 822 823 /* Interrupt type codes */ 824 #define INTR_ROM_MB_SUCCESS 0x1 825 #define INTR_ROM_MB_FAILED 0x2 826 #define INTR_MB_SUCCESS 0x10 827 #define INTR_MB_FAILED 0x11 828 #define INTR_ASYNC_EVENT 0x12 829 #define INTR_RSP_QUE_UPDATE 0x13 830 #define INTR_RSP_QUE_UPDATE_83XX 0x14 831 #define INTR_ATIO_QUE_UPDATE 0x1C 832 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 833 834 /* ISP mailbox loopback echo diagnostic error code */ 835 #define MBS_LB_RESET 0x17 836 /* 837 * Firmware options 1, 2, 3. 838 */ 839 #define FO1_AE_ON_LIPF8 BIT_0 840 #define FO1_AE_ALL_LIP_RESET BIT_1 841 #define FO1_CTIO_RETRY BIT_3 842 #define FO1_DISABLE_LIP_F7_SW BIT_4 843 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 844 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 845 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 846 #define FO1_SET_EMPHASIS_SWING BIT_8 847 #define FO1_AE_AUTO_BYPASS BIT_9 848 #define FO1_ENABLE_PURE_IOCB BIT_10 849 #define FO1_AE_PLOGI_RJT BIT_11 850 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 851 #define FO1_AE_QUEUE_FULL BIT_13 852 853 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 854 #define FO2_REV_LOOPBACK BIT_1 855 856 #define FO3_ENABLE_EMERG_IOCB BIT_0 857 #define FO3_AE_RND_ERROR BIT_1 858 859 /* 24XX additional firmware options */ 860 #define ADD_FO_COUNT 3 861 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 862 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 863 864 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 865 866 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 867 868 /* 869 * ISP mailbox commands 870 */ 871 #define MBC_LOAD_RAM 1 /* Load RAM. */ 872 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 873 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 874 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 875 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 876 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 877 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 878 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 879 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 880 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 881 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 882 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 883 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 884 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 885 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 886 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 887 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 888 #define MBC_RESET 0x18 /* Reset. */ 889 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 890 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 891 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 892 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 893 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 894 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 895 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 896 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 897 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 898 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 899 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 900 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 901 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 902 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 903 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 904 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 905 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 906 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 907 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 908 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 909 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 910 #define MBC_DATA_RATE 0x5d /* Data Rate */ 911 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 912 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 913 /* Initialization Procedure */ 914 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 915 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 916 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 917 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 918 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 919 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 920 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 921 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 922 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 923 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 924 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 925 /* commandd. */ 926 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 927 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 928 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 929 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 930 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 931 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 932 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 933 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 934 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 935 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 936 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 937 938 /* 939 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 940 * should be defined with MBC_MR_* 941 */ 942 #define MBC_MR_DRV_SHUTDOWN 0x6A 943 944 /* 945 * ISP24xx mailbox commands 946 */ 947 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 948 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 949 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 950 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 951 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 952 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 953 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 954 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 955 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 956 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 957 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 958 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 959 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 960 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 961 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 962 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 963 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 964 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 965 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 966 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 967 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 968 #define MBC_PORT_RESET 0x120 /* Port Reset */ 969 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 970 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 971 972 /* 973 * ISP81xx mailbox commands 974 */ 975 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 976 977 /* 978 * ISP8044 mailbox commands 979 */ 980 #define MBC_SET_GET_ETH_SERDES_REG 0x150 981 #define HCS_WRITE_SERDES 0x3 982 #define HCS_READ_SERDES 0x4 983 984 /* Firmware return data sizes */ 985 #define FCAL_MAP_SIZE 128 986 987 /* Mailbox bit definitions for out_mb and in_mb */ 988 #define MBX_31 BIT_31 989 #define MBX_30 BIT_30 990 #define MBX_29 BIT_29 991 #define MBX_28 BIT_28 992 #define MBX_27 BIT_27 993 #define MBX_26 BIT_26 994 #define MBX_25 BIT_25 995 #define MBX_24 BIT_24 996 #define MBX_23 BIT_23 997 #define MBX_22 BIT_22 998 #define MBX_21 BIT_21 999 #define MBX_20 BIT_20 1000 #define MBX_19 BIT_19 1001 #define MBX_18 BIT_18 1002 #define MBX_17 BIT_17 1003 #define MBX_16 BIT_16 1004 #define MBX_15 BIT_15 1005 #define MBX_14 BIT_14 1006 #define MBX_13 BIT_13 1007 #define MBX_12 BIT_12 1008 #define MBX_11 BIT_11 1009 #define MBX_10 BIT_10 1010 #define MBX_9 BIT_9 1011 #define MBX_8 BIT_8 1012 #define MBX_7 BIT_7 1013 #define MBX_6 BIT_6 1014 #define MBX_5 BIT_5 1015 #define MBX_4 BIT_4 1016 #define MBX_3 BIT_3 1017 #define MBX_2 BIT_2 1018 #define MBX_1 BIT_1 1019 #define MBX_0 BIT_0 1020 1021 #define RNID_TYPE_SET_VERSION 0x9 1022 #define RNID_TYPE_ASIC_TEMP 0xC 1023 1024 /* 1025 * Firmware state codes from get firmware state mailbox command 1026 */ 1027 #define FSTATE_CONFIG_WAIT 0 1028 #define FSTATE_WAIT_AL_PA 1 1029 #define FSTATE_WAIT_LOGIN 2 1030 #define FSTATE_READY 3 1031 #define FSTATE_LOSS_OF_SYNC 4 1032 #define FSTATE_ERROR 5 1033 #define FSTATE_REINIT 6 1034 #define FSTATE_NON_PART 7 1035 1036 #define FSTATE_CONFIG_CORRECT 0 1037 #define FSTATE_P2P_RCV_LIP 1 1038 #define FSTATE_P2P_CHOOSE_LOOP 2 1039 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1040 #define FSTATE_FATAL_ERROR 4 1041 #define FSTATE_LOOP_BACK_CONN 5 1042 1043 /* 1044 * Port Database structure definition 1045 * Little endian except where noted. 1046 */ 1047 #define PORT_DATABASE_SIZE 128 /* bytes */ 1048 typedef struct { 1049 uint8_t options; 1050 uint8_t control; 1051 uint8_t master_state; 1052 uint8_t slave_state; 1053 uint8_t reserved[2]; 1054 uint8_t hard_address; 1055 uint8_t reserved_1; 1056 uint8_t port_id[4]; 1057 uint8_t node_name[WWN_SIZE]; 1058 uint8_t port_name[WWN_SIZE]; 1059 uint16_t execution_throttle; 1060 uint16_t execution_count; 1061 uint8_t reset_count; 1062 uint8_t reserved_2; 1063 uint16_t resource_allocation; 1064 uint16_t current_allocation; 1065 uint16_t queue_head; 1066 uint16_t queue_tail; 1067 uint16_t transmit_execution_list_next; 1068 uint16_t transmit_execution_list_previous; 1069 uint16_t common_features; 1070 uint16_t total_concurrent_sequences; 1071 uint16_t RO_by_information_category; 1072 uint8_t recipient; 1073 uint8_t initiator; 1074 uint16_t receive_data_size; 1075 uint16_t concurrent_sequences; 1076 uint16_t open_sequences_per_exchange; 1077 uint16_t lun_abort_flags; 1078 uint16_t lun_stop_flags; 1079 uint16_t stop_queue_head; 1080 uint16_t stop_queue_tail; 1081 uint16_t port_retry_timer; 1082 uint16_t next_sequence_id; 1083 uint16_t frame_count; 1084 uint16_t PRLI_payload_length; 1085 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1086 /* Bits 15-0 of word 0 */ 1087 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1088 /* Bits 15-0 of word 3 */ 1089 uint16_t loop_id; 1090 uint16_t extended_lun_info_list_pointer; 1091 uint16_t extended_lun_stop_list_pointer; 1092 } port_database_t; 1093 1094 /* 1095 * Port database slave/master states 1096 */ 1097 #define PD_STATE_DISCOVERY 0 1098 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1099 #define PD_STATE_PORT_LOGIN 2 1100 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1101 #define PD_STATE_PROCESS_LOGIN 4 1102 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1103 #define PD_STATE_PORT_LOGGED_IN 6 1104 #define PD_STATE_PORT_UNAVAILABLE 7 1105 #define PD_STATE_PROCESS_LOGOUT 8 1106 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1107 #define PD_STATE_PORT_LOGOUT 10 1108 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1109 1110 1111 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1112 #define QLA_ZIO_DISABLED 0 1113 #define QLA_ZIO_DEFAULT_TIMER 2 1114 1115 /* 1116 * ISP Initialization Control Block. 1117 * Little endian except where noted. 1118 */ 1119 #define ICB_VERSION 1 1120 typedef struct { 1121 uint8_t version; 1122 uint8_t reserved_1; 1123 1124 /* 1125 * LSB BIT 0 = Enable Hard Loop Id 1126 * LSB BIT 1 = Enable Fairness 1127 * LSB BIT 2 = Enable Full-Duplex 1128 * LSB BIT 3 = Enable Fast Posting 1129 * LSB BIT 4 = Enable Target Mode 1130 * LSB BIT 5 = Disable Initiator Mode 1131 * LSB BIT 6 = Enable ADISC 1132 * LSB BIT 7 = Enable Target Inquiry Data 1133 * 1134 * MSB BIT 0 = Enable PDBC Notify 1135 * MSB BIT 1 = Non Participating LIP 1136 * MSB BIT 2 = Descending Loop ID Search 1137 * MSB BIT 3 = Acquire Loop ID in LIPA 1138 * MSB BIT 4 = Stop PortQ on Full Status 1139 * MSB BIT 5 = Full Login after LIP 1140 * MSB BIT 6 = Node Name Option 1141 * MSB BIT 7 = Ext IFWCB enable bit 1142 */ 1143 uint8_t firmware_options[2]; 1144 1145 uint16_t frame_payload_size; 1146 uint16_t max_iocb_allocation; 1147 uint16_t execution_throttle; 1148 uint8_t retry_count; 1149 uint8_t retry_delay; /* unused */ 1150 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1151 uint16_t hard_address; 1152 uint8_t inquiry_data; 1153 uint8_t login_timeout; 1154 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1155 1156 uint16_t request_q_outpointer; 1157 uint16_t response_q_inpointer; 1158 uint16_t request_q_length; 1159 uint16_t response_q_length; 1160 uint32_t request_q_address[2]; 1161 uint32_t response_q_address[2]; 1162 1163 uint16_t lun_enables; 1164 uint8_t command_resource_count; 1165 uint8_t immediate_notify_resource_count; 1166 uint16_t timeout; 1167 uint8_t reserved_2[2]; 1168 1169 /* 1170 * LSB BIT 0 = Timer Operation mode bit 0 1171 * LSB BIT 1 = Timer Operation mode bit 1 1172 * LSB BIT 2 = Timer Operation mode bit 2 1173 * LSB BIT 3 = Timer Operation mode bit 3 1174 * LSB BIT 4 = Init Config Mode bit 0 1175 * LSB BIT 5 = Init Config Mode bit 1 1176 * LSB BIT 6 = Init Config Mode bit 2 1177 * LSB BIT 7 = Enable Non part on LIHA failure 1178 * 1179 * MSB BIT 0 = Enable class 2 1180 * MSB BIT 1 = Enable ACK0 1181 * MSB BIT 2 = 1182 * MSB BIT 3 = 1183 * MSB BIT 4 = FC Tape Enable 1184 * MSB BIT 5 = Enable FC Confirm 1185 * MSB BIT 6 = Enable command queuing in target mode 1186 * MSB BIT 7 = No Logo On Link Down 1187 */ 1188 uint8_t add_firmware_options[2]; 1189 1190 uint8_t response_accumulation_timer; 1191 uint8_t interrupt_delay_timer; 1192 1193 /* 1194 * LSB BIT 0 = Enable Read xfr_rdy 1195 * LSB BIT 1 = Soft ID only 1196 * LSB BIT 2 = 1197 * LSB BIT 3 = 1198 * LSB BIT 4 = FCP RSP Payload [0] 1199 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1200 * LSB BIT 6 = Enable Out-of-Order frame handling 1201 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1202 * 1203 * MSB BIT 0 = Sbus enable - 2300 1204 * MSB BIT 1 = 1205 * MSB BIT 2 = 1206 * MSB BIT 3 = 1207 * MSB BIT 4 = LED mode 1208 * MSB BIT 5 = enable 50 ohm termination 1209 * MSB BIT 6 = Data Rate (2300 only) 1210 * MSB BIT 7 = Data Rate (2300 only) 1211 */ 1212 uint8_t special_options[2]; 1213 1214 uint8_t reserved_3[26]; 1215 } init_cb_t; 1216 1217 /* 1218 * Get Link Status mailbox command return buffer. 1219 */ 1220 #define GLSO_SEND_RPS BIT_0 1221 #define GLSO_USE_DID BIT_3 1222 1223 struct link_statistics { 1224 uint32_t link_fail_cnt; 1225 uint32_t loss_sync_cnt; 1226 uint32_t loss_sig_cnt; 1227 uint32_t prim_seq_err_cnt; 1228 uint32_t inval_xmit_word_cnt; 1229 uint32_t inval_crc_cnt; 1230 uint32_t lip_cnt; 1231 uint32_t unused1[0x1a]; 1232 uint32_t tx_frames; 1233 uint32_t rx_frames; 1234 uint32_t discarded_frames; 1235 uint32_t dropped_frames; 1236 uint32_t unused2[1]; 1237 uint32_t nos_rcvd; 1238 }; 1239 1240 /* 1241 * NVRAM Command values. 1242 */ 1243 #define NV_START_BIT BIT_2 1244 #define NV_WRITE_OP (BIT_26+BIT_24) 1245 #define NV_READ_OP (BIT_26+BIT_25) 1246 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1247 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1248 #define NV_DELAY_COUNT 10 1249 1250 /* 1251 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1252 */ 1253 typedef struct { 1254 /* 1255 * NVRAM header 1256 */ 1257 uint8_t id[4]; 1258 uint8_t nvram_version; 1259 uint8_t reserved_0; 1260 1261 /* 1262 * NVRAM RISC parameter block 1263 */ 1264 uint8_t parameter_block_version; 1265 uint8_t reserved_1; 1266 1267 /* 1268 * LSB BIT 0 = Enable Hard Loop Id 1269 * LSB BIT 1 = Enable Fairness 1270 * LSB BIT 2 = Enable Full-Duplex 1271 * LSB BIT 3 = Enable Fast Posting 1272 * LSB BIT 4 = Enable Target Mode 1273 * LSB BIT 5 = Disable Initiator Mode 1274 * LSB BIT 6 = Enable ADISC 1275 * LSB BIT 7 = Enable Target Inquiry Data 1276 * 1277 * MSB BIT 0 = Enable PDBC Notify 1278 * MSB BIT 1 = Non Participating LIP 1279 * MSB BIT 2 = Descending Loop ID Search 1280 * MSB BIT 3 = Acquire Loop ID in LIPA 1281 * MSB BIT 4 = Stop PortQ on Full Status 1282 * MSB BIT 5 = Full Login after LIP 1283 * MSB BIT 6 = Node Name Option 1284 * MSB BIT 7 = Ext IFWCB enable bit 1285 */ 1286 uint8_t firmware_options[2]; 1287 1288 uint16_t frame_payload_size; 1289 uint16_t max_iocb_allocation; 1290 uint16_t execution_throttle; 1291 uint8_t retry_count; 1292 uint8_t retry_delay; /* unused */ 1293 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1294 uint16_t hard_address; 1295 uint8_t inquiry_data; 1296 uint8_t login_timeout; 1297 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1298 1299 /* 1300 * LSB BIT 0 = Timer Operation mode bit 0 1301 * LSB BIT 1 = Timer Operation mode bit 1 1302 * LSB BIT 2 = Timer Operation mode bit 2 1303 * LSB BIT 3 = Timer Operation mode bit 3 1304 * LSB BIT 4 = Init Config Mode bit 0 1305 * LSB BIT 5 = Init Config Mode bit 1 1306 * LSB BIT 6 = Init Config Mode bit 2 1307 * LSB BIT 7 = Enable Non part on LIHA failure 1308 * 1309 * MSB BIT 0 = Enable class 2 1310 * MSB BIT 1 = Enable ACK0 1311 * MSB BIT 2 = 1312 * MSB BIT 3 = 1313 * MSB BIT 4 = FC Tape Enable 1314 * MSB BIT 5 = Enable FC Confirm 1315 * MSB BIT 6 = Enable command queuing in target mode 1316 * MSB BIT 7 = No Logo On Link Down 1317 */ 1318 uint8_t add_firmware_options[2]; 1319 1320 uint8_t response_accumulation_timer; 1321 uint8_t interrupt_delay_timer; 1322 1323 /* 1324 * LSB BIT 0 = Enable Read xfr_rdy 1325 * LSB BIT 1 = Soft ID only 1326 * LSB BIT 2 = 1327 * LSB BIT 3 = 1328 * LSB BIT 4 = FCP RSP Payload [0] 1329 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1330 * LSB BIT 6 = Enable Out-of-Order frame handling 1331 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1332 * 1333 * MSB BIT 0 = Sbus enable - 2300 1334 * MSB BIT 1 = 1335 * MSB BIT 2 = 1336 * MSB BIT 3 = 1337 * MSB BIT 4 = LED mode 1338 * MSB BIT 5 = enable 50 ohm termination 1339 * MSB BIT 6 = Data Rate (2300 only) 1340 * MSB BIT 7 = Data Rate (2300 only) 1341 */ 1342 uint8_t special_options[2]; 1343 1344 /* Reserved for expanded RISC parameter block */ 1345 uint8_t reserved_2[22]; 1346 1347 /* 1348 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1349 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1350 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1351 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1352 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1353 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1354 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1355 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1356 * 1357 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1358 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1359 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1360 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1361 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1362 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1363 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1364 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1365 * 1366 * LSB BIT 0 = Output Swing 1G bit 0 1367 * LSB BIT 1 = Output Swing 1G bit 1 1368 * LSB BIT 2 = Output Swing 1G bit 2 1369 * LSB BIT 3 = Output Emphasis 1G bit 0 1370 * LSB BIT 4 = Output Emphasis 1G bit 1 1371 * LSB BIT 5 = Output Swing 2G bit 0 1372 * LSB BIT 6 = Output Swing 2G bit 1 1373 * LSB BIT 7 = Output Swing 2G bit 2 1374 * 1375 * MSB BIT 0 = Output Emphasis 2G bit 0 1376 * MSB BIT 1 = Output Emphasis 2G bit 1 1377 * MSB BIT 2 = Output Enable 1378 * MSB BIT 3 = 1379 * MSB BIT 4 = 1380 * MSB BIT 5 = 1381 * MSB BIT 6 = 1382 * MSB BIT 7 = 1383 */ 1384 uint8_t seriallink_options[4]; 1385 1386 /* 1387 * NVRAM host parameter block 1388 * 1389 * LSB BIT 0 = Enable spinup delay 1390 * LSB BIT 1 = Disable BIOS 1391 * LSB BIT 2 = Enable Memory Map BIOS 1392 * LSB BIT 3 = Enable Selectable Boot 1393 * LSB BIT 4 = Disable RISC code load 1394 * LSB BIT 5 = Set cache line size 1 1395 * LSB BIT 6 = PCI Parity Disable 1396 * LSB BIT 7 = Enable extended logging 1397 * 1398 * MSB BIT 0 = Enable 64bit addressing 1399 * MSB BIT 1 = Enable lip reset 1400 * MSB BIT 2 = Enable lip full login 1401 * MSB BIT 3 = Enable target reset 1402 * MSB BIT 4 = Enable database storage 1403 * MSB BIT 5 = Enable cache flush read 1404 * MSB BIT 6 = Enable database load 1405 * MSB BIT 7 = Enable alternate WWN 1406 */ 1407 uint8_t host_p[2]; 1408 1409 uint8_t boot_node_name[WWN_SIZE]; 1410 uint8_t boot_lun_number; 1411 uint8_t reset_delay; 1412 uint8_t port_down_retry_count; 1413 uint8_t boot_id_number; 1414 uint16_t max_luns_per_target; 1415 uint8_t fcode_boot_port_name[WWN_SIZE]; 1416 uint8_t alternate_port_name[WWN_SIZE]; 1417 uint8_t alternate_node_name[WWN_SIZE]; 1418 1419 /* 1420 * BIT 0 = Selective Login 1421 * BIT 1 = Alt-Boot Enable 1422 * BIT 2 = 1423 * BIT 3 = Boot Order List 1424 * BIT 4 = 1425 * BIT 5 = Selective LUN 1426 * BIT 6 = 1427 * BIT 7 = unused 1428 */ 1429 uint8_t efi_parameters; 1430 1431 uint8_t link_down_timeout; 1432 1433 uint8_t adapter_id[16]; 1434 1435 uint8_t alt1_boot_node_name[WWN_SIZE]; 1436 uint16_t alt1_boot_lun_number; 1437 uint8_t alt2_boot_node_name[WWN_SIZE]; 1438 uint16_t alt2_boot_lun_number; 1439 uint8_t alt3_boot_node_name[WWN_SIZE]; 1440 uint16_t alt3_boot_lun_number; 1441 uint8_t alt4_boot_node_name[WWN_SIZE]; 1442 uint16_t alt4_boot_lun_number; 1443 uint8_t alt5_boot_node_name[WWN_SIZE]; 1444 uint16_t alt5_boot_lun_number; 1445 uint8_t alt6_boot_node_name[WWN_SIZE]; 1446 uint16_t alt6_boot_lun_number; 1447 uint8_t alt7_boot_node_name[WWN_SIZE]; 1448 uint16_t alt7_boot_lun_number; 1449 1450 uint8_t reserved_3[2]; 1451 1452 /* Offset 200-215 : Model Number */ 1453 uint8_t model_number[16]; 1454 1455 /* OEM related items */ 1456 uint8_t oem_specific[16]; 1457 1458 /* 1459 * NVRAM Adapter Features offset 232-239 1460 * 1461 * LSB BIT 0 = External GBIC 1462 * LSB BIT 1 = Risc RAM parity 1463 * LSB BIT 2 = Buffer Plus Module 1464 * LSB BIT 3 = Multi Chip Adapter 1465 * LSB BIT 4 = Internal connector 1466 * LSB BIT 5 = 1467 * LSB BIT 6 = 1468 * LSB BIT 7 = 1469 * 1470 * MSB BIT 0 = 1471 * MSB BIT 1 = 1472 * MSB BIT 2 = 1473 * MSB BIT 3 = 1474 * MSB BIT 4 = 1475 * MSB BIT 5 = 1476 * MSB BIT 6 = 1477 * MSB BIT 7 = 1478 */ 1479 uint8_t adapter_features[2]; 1480 1481 uint8_t reserved_4[16]; 1482 1483 /* Subsystem vendor ID for ISP2200 */ 1484 uint16_t subsystem_vendor_id_2200; 1485 1486 /* Subsystem device ID for ISP2200 */ 1487 uint16_t subsystem_device_id_2200; 1488 1489 uint8_t reserved_5; 1490 uint8_t checksum; 1491 } nvram_t; 1492 1493 /* 1494 * ISP queue - response queue entry definition. 1495 */ 1496 typedef struct { 1497 uint8_t entry_type; /* Entry type. */ 1498 uint8_t entry_count; /* Entry count. */ 1499 uint8_t sys_define; /* System defined. */ 1500 uint8_t entry_status; /* Entry Status. */ 1501 uint32_t handle; /* System defined handle */ 1502 uint8_t data[52]; 1503 uint32_t signature; 1504 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1505 } response_t; 1506 1507 /* 1508 * ISP queue - ATIO queue entry definition. 1509 */ 1510 struct atio { 1511 uint8_t entry_type; /* Entry type. */ 1512 uint8_t entry_count; /* Entry count. */ 1513 uint8_t data[58]; 1514 uint32_t signature; 1515 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1516 }; 1517 1518 typedef union { 1519 uint16_t extended; 1520 struct { 1521 uint8_t reserved; 1522 uint8_t standard; 1523 } id; 1524 } target_id_t; 1525 1526 #define SET_TARGET_ID(ha, to, from) \ 1527 do { \ 1528 if (HAS_EXTENDED_IDS(ha)) \ 1529 to.extended = cpu_to_le16(from); \ 1530 else \ 1531 to.id.standard = (uint8_t)from; \ 1532 } while (0) 1533 1534 /* 1535 * ISP queue - command entry structure definition. 1536 */ 1537 #define COMMAND_TYPE 0x11 /* Command entry */ 1538 typedef struct { 1539 uint8_t entry_type; /* Entry type. */ 1540 uint8_t entry_count; /* Entry count. */ 1541 uint8_t sys_define; /* System defined. */ 1542 uint8_t entry_status; /* Entry Status. */ 1543 uint32_t handle; /* System handle. */ 1544 target_id_t target; /* SCSI ID */ 1545 uint16_t lun; /* SCSI LUN */ 1546 uint16_t control_flags; /* Control flags. */ 1547 #define CF_WRITE BIT_6 1548 #define CF_READ BIT_5 1549 #define CF_SIMPLE_TAG BIT_3 1550 #define CF_ORDERED_TAG BIT_2 1551 #define CF_HEAD_TAG BIT_1 1552 uint16_t reserved_1; 1553 uint16_t timeout; /* Command timeout. */ 1554 uint16_t dseg_count; /* Data segment count. */ 1555 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1556 uint32_t byte_count; /* Total byte count. */ 1557 uint32_t dseg_0_address; /* Data segment 0 address. */ 1558 uint32_t dseg_0_length; /* Data segment 0 length. */ 1559 uint32_t dseg_1_address; /* Data segment 1 address. */ 1560 uint32_t dseg_1_length; /* Data segment 1 length. */ 1561 uint32_t dseg_2_address; /* Data segment 2 address. */ 1562 uint32_t dseg_2_length; /* Data segment 2 length. */ 1563 } cmd_entry_t; 1564 1565 /* 1566 * ISP queue - 64-Bit addressing, command entry structure definition. 1567 */ 1568 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1569 typedef struct { 1570 uint8_t entry_type; /* Entry type. */ 1571 uint8_t entry_count; /* Entry count. */ 1572 uint8_t sys_define; /* System defined. */ 1573 uint8_t entry_status; /* Entry Status. */ 1574 uint32_t handle; /* System handle. */ 1575 target_id_t target; /* SCSI ID */ 1576 uint16_t lun; /* SCSI LUN */ 1577 uint16_t control_flags; /* Control flags. */ 1578 uint16_t reserved_1; 1579 uint16_t timeout; /* Command timeout. */ 1580 uint16_t dseg_count; /* Data segment count. */ 1581 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1582 uint32_t byte_count; /* Total byte count. */ 1583 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1584 uint32_t dseg_0_length; /* Data segment 0 length. */ 1585 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1586 uint32_t dseg_1_length; /* Data segment 1 length. */ 1587 } cmd_a64_entry_t, request_t; 1588 1589 /* 1590 * ISP queue - continuation entry structure definition. 1591 */ 1592 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1593 typedef struct { 1594 uint8_t entry_type; /* Entry type. */ 1595 uint8_t entry_count; /* Entry count. */ 1596 uint8_t sys_define; /* System defined. */ 1597 uint8_t entry_status; /* Entry Status. */ 1598 uint32_t reserved; 1599 uint32_t dseg_0_address; /* Data segment 0 address. */ 1600 uint32_t dseg_0_length; /* Data segment 0 length. */ 1601 uint32_t dseg_1_address; /* Data segment 1 address. */ 1602 uint32_t dseg_1_length; /* Data segment 1 length. */ 1603 uint32_t dseg_2_address; /* Data segment 2 address. */ 1604 uint32_t dseg_2_length; /* Data segment 2 length. */ 1605 uint32_t dseg_3_address; /* Data segment 3 address. */ 1606 uint32_t dseg_3_length; /* Data segment 3 length. */ 1607 uint32_t dseg_4_address; /* Data segment 4 address. */ 1608 uint32_t dseg_4_length; /* Data segment 4 length. */ 1609 uint32_t dseg_5_address; /* Data segment 5 address. */ 1610 uint32_t dseg_5_length; /* Data segment 5 length. */ 1611 uint32_t dseg_6_address; /* Data segment 6 address. */ 1612 uint32_t dseg_6_length; /* Data segment 6 length. */ 1613 } cont_entry_t; 1614 1615 /* 1616 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1617 */ 1618 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1619 typedef struct { 1620 uint8_t entry_type; /* Entry type. */ 1621 uint8_t entry_count; /* Entry count. */ 1622 uint8_t sys_define; /* System defined. */ 1623 uint8_t entry_status; /* Entry Status. */ 1624 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1625 uint32_t dseg_0_length; /* Data segment 0 length. */ 1626 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1627 uint32_t dseg_1_length; /* Data segment 1 length. */ 1628 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1629 uint32_t dseg_2_length; /* Data segment 2 length. */ 1630 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1631 uint32_t dseg_3_length; /* Data segment 3 length. */ 1632 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1633 uint32_t dseg_4_length; /* Data segment 4 length. */ 1634 } cont_a64_entry_t; 1635 1636 #define PO_MODE_DIF_INSERT 0 1637 #define PO_MODE_DIF_REMOVE 1 1638 #define PO_MODE_DIF_PASS 2 1639 #define PO_MODE_DIF_REPLACE 3 1640 #define PO_MODE_DIF_TCP_CKSUM 6 1641 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1642 #define PO_DISABLE_GUARD_CHECK BIT_4 1643 #define PO_DISABLE_INCR_REF_TAG BIT_5 1644 #define PO_DIS_HEADER_MODE BIT_7 1645 #define PO_ENABLE_DIF_BUNDLING BIT_8 1646 #define PO_DIS_FRAME_MODE BIT_9 1647 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1648 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1649 1650 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1651 #define PO_DIS_REF_TAG_REPL BIT_13 1652 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1653 #define PO_DIS_REF_TAG_VALD BIT_15 1654 1655 /* 1656 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1657 */ 1658 struct crc_context { 1659 uint32_t handle; /* System handle. */ 1660 __le32 ref_tag; 1661 __le16 app_tag; 1662 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1663 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1664 __le16 guard_seed; /* Initial Guard Seed */ 1665 __le16 prot_opts; /* Requested Data Protection Mode */ 1666 __le16 blk_size; /* Data size in bytes */ 1667 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1668 * only) */ 1669 __le32 byte_count; /* Total byte count/ total data 1670 * transfer count */ 1671 union { 1672 struct { 1673 uint32_t reserved_1; 1674 uint16_t reserved_2; 1675 uint16_t reserved_3; 1676 uint32_t reserved_4; 1677 uint32_t data_address[2]; 1678 uint32_t data_length; 1679 uint32_t reserved_5[2]; 1680 uint32_t reserved_6; 1681 } nobundling; 1682 struct { 1683 __le32 dif_byte_count; /* Total DIF byte 1684 * count */ 1685 uint16_t reserved_1; 1686 __le16 dseg_count; /* Data segment count */ 1687 uint32_t reserved_2; 1688 uint32_t data_address[2]; 1689 uint32_t data_length; 1690 uint32_t dif_address[2]; 1691 uint32_t dif_length; /* Data segment 0 1692 * length */ 1693 } bundling; 1694 } u; 1695 1696 struct fcp_cmnd fcp_cmnd; 1697 dma_addr_t crc_ctx_dma; 1698 /* List of DMA context transfers */ 1699 struct list_head dsd_list; 1700 1701 /* This structure should not exceed 512 bytes */ 1702 }; 1703 1704 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1705 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1706 1707 /* 1708 * ISP queue - status entry structure definition. 1709 */ 1710 #define STATUS_TYPE 0x03 /* Status entry. */ 1711 typedef struct { 1712 uint8_t entry_type; /* Entry type. */ 1713 uint8_t entry_count; /* Entry count. */ 1714 uint8_t sys_define; /* System defined. */ 1715 uint8_t entry_status; /* Entry Status. */ 1716 uint32_t handle; /* System handle. */ 1717 uint16_t scsi_status; /* SCSI status. */ 1718 uint16_t comp_status; /* Completion status. */ 1719 uint16_t state_flags; /* State flags. */ 1720 uint16_t status_flags; /* Status flags. */ 1721 uint16_t rsp_info_len; /* Response Info Length. */ 1722 uint16_t req_sense_length; /* Request sense data length. */ 1723 uint32_t residual_length; /* Residual transfer length. */ 1724 uint8_t rsp_info[8]; /* FCP response information. */ 1725 uint8_t req_sense_data[32]; /* Request sense data. */ 1726 } sts_entry_t; 1727 1728 /* 1729 * Status entry entry status 1730 */ 1731 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1732 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1733 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1734 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1735 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1736 #define RF_BUSY BIT_1 /* Busy */ 1737 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1738 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1739 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1740 RF_INV_E_TYPE) 1741 1742 /* 1743 * Status entry SCSI status bit definitions. 1744 */ 1745 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1746 #define SS_RESIDUAL_UNDER BIT_11 1747 #define SS_RESIDUAL_OVER BIT_10 1748 #define SS_SENSE_LEN_VALID BIT_9 1749 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1750 1751 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1752 #define SS_BUSY_CONDITION BIT_3 1753 #define SS_CONDITION_MET BIT_2 1754 #define SS_CHECK_CONDITION BIT_1 1755 1756 /* 1757 * Status entry completion status 1758 */ 1759 #define CS_COMPLETE 0x0 /* No errors */ 1760 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1761 #define CS_DMA 0x2 /* A DMA direction error. */ 1762 #define CS_TRANSPORT 0x3 /* Transport error. */ 1763 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1764 #define CS_ABORTED 0x5 /* System aborted command. */ 1765 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1766 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1767 #define CS_DIF_ERROR 0xC /* DIF error detected */ 1768 1769 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1770 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1771 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1772 /* (selection timeout) */ 1773 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1774 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1775 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1776 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1777 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 1778 failure */ 1779 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1780 #define CS_UNKNOWN 0x81 /* Driver defined */ 1781 #define CS_RETRY 0x82 /* Driver defined */ 1782 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1783 1784 #define CS_BIDIR_RD_OVERRUN 0x700 1785 #define CS_BIDIR_RD_WR_OVERRUN 0x707 1786 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 1787 #define CS_BIDIR_RD_UNDERRUN 0x1500 1788 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 1789 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 1790 #define CS_BIDIR_DMA 0x200 1791 /* 1792 * Status entry status flags 1793 */ 1794 #define SF_ABTS_TERMINATED BIT_10 1795 #define SF_LOGOUT_SENT BIT_13 1796 1797 /* 1798 * ISP queue - status continuation entry structure definition. 1799 */ 1800 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1801 typedef struct { 1802 uint8_t entry_type; /* Entry type. */ 1803 uint8_t entry_count; /* Entry count. */ 1804 uint8_t sys_define; /* System defined. */ 1805 uint8_t entry_status; /* Entry Status. */ 1806 uint8_t data[60]; /* data */ 1807 } sts_cont_entry_t; 1808 1809 /* 1810 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1811 * structure definition. 1812 */ 1813 #define STATUS_TYPE_21 0x21 /* Status entry. */ 1814 typedef struct { 1815 uint8_t entry_type; /* Entry type. */ 1816 uint8_t entry_count; /* Entry count. */ 1817 uint8_t handle_count; /* Handle count. */ 1818 uint8_t entry_status; /* Entry Status. */ 1819 uint32_t handle[15]; /* System handles. */ 1820 } sts21_entry_t; 1821 1822 /* 1823 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1824 * structure definition. 1825 */ 1826 #define STATUS_TYPE_22 0x22 /* Status entry. */ 1827 typedef struct { 1828 uint8_t entry_type; /* Entry type. */ 1829 uint8_t entry_count; /* Entry count. */ 1830 uint8_t handle_count; /* Handle count. */ 1831 uint8_t entry_status; /* Entry Status. */ 1832 uint16_t handle[30]; /* System handles. */ 1833 } sts22_entry_t; 1834 1835 /* 1836 * ISP queue - marker entry structure definition. 1837 */ 1838 #define MARKER_TYPE 0x04 /* Marker entry. */ 1839 typedef struct { 1840 uint8_t entry_type; /* Entry type. */ 1841 uint8_t entry_count; /* Entry count. */ 1842 uint8_t handle_count; /* Handle count. */ 1843 uint8_t entry_status; /* Entry Status. */ 1844 uint32_t sys_define_2; /* System defined. */ 1845 target_id_t target; /* SCSI ID */ 1846 uint8_t modifier; /* Modifier (7-0). */ 1847 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1848 #define MK_SYNC_ID 1 /* Synchronize ID */ 1849 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1850 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 1851 /* clear port changed, */ 1852 /* use sequence number. */ 1853 uint8_t reserved_1; 1854 uint16_t sequence_number; /* Sequence number of event */ 1855 uint16_t lun; /* SCSI LUN */ 1856 uint8_t reserved_2[48]; 1857 } mrk_entry_t; 1858 1859 /* 1860 * ISP queue - Management Server entry structure definition. 1861 */ 1862 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 1863 typedef struct { 1864 uint8_t entry_type; /* Entry type. */ 1865 uint8_t entry_count; /* Entry count. */ 1866 uint8_t handle_count; /* Handle count. */ 1867 uint8_t entry_status; /* Entry Status. */ 1868 uint32_t handle1; /* System handle. */ 1869 target_id_t loop_id; 1870 uint16_t status; 1871 uint16_t control_flags; /* Control flags. */ 1872 uint16_t reserved2; 1873 uint16_t timeout; 1874 uint16_t cmd_dsd_count; 1875 uint16_t total_dsd_count; 1876 uint8_t type; 1877 uint8_t r_ctl; 1878 uint16_t rx_id; 1879 uint16_t reserved3; 1880 uint32_t handle2; 1881 uint32_t rsp_bytecount; 1882 uint32_t req_bytecount; 1883 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 1884 uint32_t dseg_req_length; /* Data segment 0 length. */ 1885 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 1886 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 1887 } ms_iocb_entry_t; 1888 1889 1890 /* 1891 * ISP queue - Mailbox Command entry structure definition. 1892 */ 1893 #define MBX_IOCB_TYPE 0x39 1894 struct mbx_entry { 1895 uint8_t entry_type; 1896 uint8_t entry_count; 1897 uint8_t sys_define1; 1898 /* Use sys_define1 for source type */ 1899 #define SOURCE_SCSI 0x00 1900 #define SOURCE_IP 0x01 1901 #define SOURCE_VI 0x02 1902 #define SOURCE_SCTP 0x03 1903 #define SOURCE_MP 0x04 1904 #define SOURCE_MPIOCTL 0x05 1905 #define SOURCE_ASYNC_IOCB 0x07 1906 1907 uint8_t entry_status; 1908 1909 uint32_t handle; 1910 target_id_t loop_id; 1911 1912 uint16_t status; 1913 uint16_t state_flags; 1914 uint16_t status_flags; 1915 1916 uint32_t sys_define2[2]; 1917 1918 uint16_t mb0; 1919 uint16_t mb1; 1920 uint16_t mb2; 1921 uint16_t mb3; 1922 uint16_t mb6; 1923 uint16_t mb7; 1924 uint16_t mb9; 1925 uint16_t mb10; 1926 uint32_t reserved_2[2]; 1927 uint8_t node_name[WWN_SIZE]; 1928 uint8_t port_name[WWN_SIZE]; 1929 }; 1930 1931 /* 1932 * ISP request and response queue entry sizes 1933 */ 1934 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 1935 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 1936 1937 1938 /* 1939 * 24 bit port ID type definition. 1940 */ 1941 typedef union { 1942 uint32_t b24 : 24; 1943 1944 struct { 1945 #ifdef __BIG_ENDIAN 1946 uint8_t domain; 1947 uint8_t area; 1948 uint8_t al_pa; 1949 #elif defined(__LITTLE_ENDIAN) 1950 uint8_t al_pa; 1951 uint8_t area; 1952 uint8_t domain; 1953 #else 1954 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 1955 #endif 1956 uint8_t rsvd_1; 1957 } b; 1958 } port_id_t; 1959 #define INVALID_PORT_ID 0xFFFFFF 1960 1961 /* 1962 * Switch info gathering structure. 1963 */ 1964 typedef struct { 1965 port_id_t d_id; 1966 uint8_t node_name[WWN_SIZE]; 1967 uint8_t port_name[WWN_SIZE]; 1968 uint8_t fabric_port_name[WWN_SIZE]; 1969 uint16_t fp_speed; 1970 uint8_t fc4_type; 1971 } sw_info_t; 1972 1973 /* FCP-4 types */ 1974 #define FC4_TYPE_FCP_SCSI 0x08 1975 #define FC4_TYPE_OTHER 0x0 1976 #define FC4_TYPE_UNKNOWN 0xff 1977 1978 /* 1979 * Fibre channel port type. 1980 */ 1981 typedef enum { 1982 FCT_UNKNOWN, 1983 FCT_RSCN, 1984 FCT_SWITCH, 1985 FCT_BROADCAST, 1986 FCT_INITIATOR, 1987 FCT_TARGET 1988 } fc_port_type_t; 1989 1990 /* 1991 * Fibre channel port structure. 1992 */ 1993 typedef struct fc_port { 1994 struct list_head list; 1995 struct scsi_qla_host *vha; 1996 1997 uint8_t node_name[WWN_SIZE]; 1998 uint8_t port_name[WWN_SIZE]; 1999 port_id_t d_id; 2000 uint16_t loop_id; 2001 uint16_t old_loop_id; 2002 2003 uint16_t tgt_id; 2004 uint16_t old_tgt_id; 2005 2006 uint8_t fcp_prio; 2007 2008 uint8_t fabric_port_name[WWN_SIZE]; 2009 uint16_t fp_speed; 2010 2011 fc_port_type_t port_type; 2012 2013 atomic_t state; 2014 uint32_t flags; 2015 2016 int login_retry; 2017 2018 struct fc_rport *rport, *drport; 2019 u32 supported_classes; 2020 2021 uint8_t fc4_type; 2022 uint8_t scan_state; 2023 2024 unsigned long last_queue_full; 2025 unsigned long last_ramp_up; 2026 2027 uint16_t port_id; 2028 2029 unsigned long retry_delay_timestamp; 2030 struct qla_tgt_sess *tgt_session; 2031 } fc_port_t; 2032 2033 #include "qla_mr.h" 2034 2035 /* 2036 * Fibre channel port/lun states. 2037 */ 2038 #define FCS_UNCONFIGURED 1 2039 #define FCS_DEVICE_DEAD 2 2040 #define FCS_DEVICE_LOST 3 2041 #define FCS_ONLINE 4 2042 2043 static const char * const port_state_str[] = { 2044 "Unknown", 2045 "UNCONFIGURED", 2046 "DEAD", 2047 "LOST", 2048 "ONLINE" 2049 }; 2050 2051 /* 2052 * FC port flags. 2053 */ 2054 #define FCF_FABRIC_DEVICE BIT_0 2055 #define FCF_LOGIN_NEEDED BIT_1 2056 #define FCF_FCP2_DEVICE BIT_2 2057 #define FCF_ASYNC_SENT BIT_3 2058 #define FCF_CONF_COMP_SUPPORTED BIT_4 2059 2060 /* No loop ID flag. */ 2061 #define FC_NO_LOOP_ID 0x1000 2062 2063 /* 2064 * FC-CT interface 2065 * 2066 * NOTE: All structures are big-endian in form. 2067 */ 2068 2069 #define CT_REJECT_RESPONSE 0x8001 2070 #define CT_ACCEPT_RESPONSE 0x8002 2071 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2072 #define CT_REASON_CANNOT_PERFORM 0x09 2073 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2074 #define CT_EXPL_ALREADY_REGISTERED 0x10 2075 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2076 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2077 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2078 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2079 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2080 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2081 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2082 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2083 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2084 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2085 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2086 2087 #define NS_N_PORT_TYPE 0x01 2088 #define NS_NL_PORT_TYPE 0x02 2089 #define NS_NX_PORT_TYPE 0x7F 2090 2091 #define GA_NXT_CMD 0x100 2092 #define GA_NXT_REQ_SIZE (16 + 4) 2093 #define GA_NXT_RSP_SIZE (16 + 620) 2094 2095 #define GID_PT_CMD 0x1A1 2096 #define GID_PT_REQ_SIZE (16 + 4) 2097 2098 #define GPN_ID_CMD 0x112 2099 #define GPN_ID_REQ_SIZE (16 + 4) 2100 #define GPN_ID_RSP_SIZE (16 + 8) 2101 2102 #define GNN_ID_CMD 0x113 2103 #define GNN_ID_REQ_SIZE (16 + 4) 2104 #define GNN_ID_RSP_SIZE (16 + 8) 2105 2106 #define GFT_ID_CMD 0x117 2107 #define GFT_ID_REQ_SIZE (16 + 4) 2108 #define GFT_ID_RSP_SIZE (16 + 32) 2109 2110 #define RFT_ID_CMD 0x217 2111 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2112 #define RFT_ID_RSP_SIZE 16 2113 2114 #define RFF_ID_CMD 0x21F 2115 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2116 #define RFF_ID_RSP_SIZE 16 2117 2118 #define RNN_ID_CMD 0x213 2119 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2120 #define RNN_ID_RSP_SIZE 16 2121 2122 #define RSNN_NN_CMD 0x239 2123 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2124 #define RSNN_NN_RSP_SIZE 16 2125 2126 #define GFPN_ID_CMD 0x11C 2127 #define GFPN_ID_REQ_SIZE (16 + 4) 2128 #define GFPN_ID_RSP_SIZE (16 + 8) 2129 2130 #define GPSC_CMD 0x127 2131 #define GPSC_REQ_SIZE (16 + 8) 2132 #define GPSC_RSP_SIZE (16 + 2 + 2) 2133 2134 #define GFF_ID_CMD 0x011F 2135 #define GFF_ID_REQ_SIZE (16 + 4) 2136 #define GFF_ID_RSP_SIZE (16 + 128) 2137 2138 /* 2139 * HBA attribute types. 2140 */ 2141 #define FDMI_HBA_ATTR_COUNT 9 2142 #define FDMIV2_HBA_ATTR_COUNT 17 2143 #define FDMI_HBA_NODE_NAME 0x1 2144 #define FDMI_HBA_MANUFACTURER 0x2 2145 #define FDMI_HBA_SERIAL_NUMBER 0x3 2146 #define FDMI_HBA_MODEL 0x4 2147 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2148 #define FDMI_HBA_HARDWARE_VERSION 0x6 2149 #define FDMI_HBA_DRIVER_VERSION 0x7 2150 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2151 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2152 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2153 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2154 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2155 #define FDMI_HBA_VENDOR_ID 0xd 2156 #define FDMI_HBA_NUM_PORTS 0xe 2157 #define FDMI_HBA_FABRIC_NAME 0xf 2158 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2159 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0 2160 2161 struct ct_fdmi_hba_attr { 2162 uint16_t type; 2163 uint16_t len; 2164 union { 2165 uint8_t node_name[WWN_SIZE]; 2166 uint8_t manufacturer[64]; 2167 uint8_t serial_num[32]; 2168 uint8_t model[16+1]; 2169 uint8_t model_desc[80]; 2170 uint8_t hw_version[32]; 2171 uint8_t driver_version[32]; 2172 uint8_t orom_version[16]; 2173 uint8_t fw_version[32]; 2174 uint8_t os_version[128]; 2175 uint32_t max_ct_len; 2176 } a; 2177 }; 2178 2179 struct ct_fdmi_hba_attributes { 2180 uint32_t count; 2181 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2182 }; 2183 2184 struct ct_fdmiv2_hba_attr { 2185 uint16_t type; 2186 uint16_t len; 2187 union { 2188 uint8_t node_name[WWN_SIZE]; 2189 uint8_t manufacturer[64]; 2190 uint8_t serial_num[32]; 2191 uint8_t model[16+1]; 2192 uint8_t model_desc[80]; 2193 uint8_t hw_version[16]; 2194 uint8_t driver_version[32]; 2195 uint8_t orom_version[16]; 2196 uint8_t fw_version[32]; 2197 uint8_t os_version[128]; 2198 uint32_t max_ct_len; 2199 uint8_t sym_name[256]; 2200 uint32_t vendor_id; 2201 uint32_t num_ports; 2202 uint8_t fabric_name[WWN_SIZE]; 2203 uint8_t bios_name[32]; 2204 uint8_t vendor_indentifer[8]; 2205 } a; 2206 }; 2207 2208 struct ct_fdmiv2_hba_attributes { 2209 uint32_t count; 2210 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT]; 2211 }; 2212 2213 /* 2214 * Port attribute types. 2215 */ 2216 #define FDMI_PORT_ATTR_COUNT 6 2217 #define FDMIV2_PORT_ATTR_COUNT 16 2218 #define FDMI_PORT_FC4_TYPES 0x1 2219 #define FDMI_PORT_SUPPORT_SPEED 0x2 2220 #define FDMI_PORT_CURRENT_SPEED 0x3 2221 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2222 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2223 #define FDMI_PORT_HOST_NAME 0x6 2224 #define FDMI_PORT_NODE_NAME 0x7 2225 #define FDMI_PORT_NAME 0x8 2226 #define FDMI_PORT_SYM_NAME 0x9 2227 #define FDMI_PORT_TYPE 0xa 2228 #define FDMI_PORT_SUPP_COS 0xb 2229 #define FDMI_PORT_FABRIC_NAME 0xc 2230 #define FDMI_PORT_FC4_TYPE 0xd 2231 #define FDMI_PORT_STATE 0x101 2232 #define FDMI_PORT_COUNT 0x102 2233 #define FDMI_PORT_ID 0x103 2234 2235 #define FDMI_PORT_SPEED_1GB 0x1 2236 #define FDMI_PORT_SPEED_2GB 0x2 2237 #define FDMI_PORT_SPEED_10GB 0x4 2238 #define FDMI_PORT_SPEED_4GB 0x8 2239 #define FDMI_PORT_SPEED_8GB 0x10 2240 #define FDMI_PORT_SPEED_16GB 0x20 2241 #define FDMI_PORT_SPEED_32GB 0x40 2242 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2243 2244 #define FC_CLASS_2 0x04 2245 #define FC_CLASS_3 0x08 2246 #define FC_CLASS_2_3 0x0C 2247 2248 struct ct_fdmiv2_port_attr { 2249 uint16_t type; 2250 uint16_t len; 2251 union { 2252 uint8_t fc4_types[32]; 2253 uint32_t sup_speed; 2254 uint32_t cur_speed; 2255 uint32_t max_frame_size; 2256 uint8_t os_dev_name[32]; 2257 uint8_t host_name[256]; 2258 uint8_t node_name[WWN_SIZE]; 2259 uint8_t port_name[WWN_SIZE]; 2260 uint8_t port_sym_name[128]; 2261 uint32_t port_type; 2262 uint32_t port_supported_cos; 2263 uint8_t fabric_name[WWN_SIZE]; 2264 uint8_t port_fc4_type[32]; 2265 uint32_t port_state; 2266 uint32_t num_ports; 2267 uint32_t port_id; 2268 } a; 2269 }; 2270 2271 /* 2272 * Port Attribute Block. 2273 */ 2274 struct ct_fdmiv2_port_attributes { 2275 uint32_t count; 2276 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT]; 2277 }; 2278 2279 struct ct_fdmi_port_attr { 2280 uint16_t type; 2281 uint16_t len; 2282 union { 2283 uint8_t fc4_types[32]; 2284 uint32_t sup_speed; 2285 uint32_t cur_speed; 2286 uint32_t max_frame_size; 2287 uint8_t os_dev_name[32]; 2288 uint8_t host_name[256]; 2289 } a; 2290 }; 2291 2292 struct ct_fdmi_port_attributes { 2293 uint32_t count; 2294 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2295 }; 2296 2297 /* FDMI definitions. */ 2298 #define GRHL_CMD 0x100 2299 #define GHAT_CMD 0x101 2300 #define GRPL_CMD 0x102 2301 #define GPAT_CMD 0x110 2302 2303 #define RHBA_CMD 0x200 2304 #define RHBA_RSP_SIZE 16 2305 2306 #define RHAT_CMD 0x201 2307 #define RPRT_CMD 0x210 2308 2309 #define RPA_CMD 0x211 2310 #define RPA_RSP_SIZE 16 2311 2312 #define DHBA_CMD 0x300 2313 #define DHBA_REQ_SIZE (16 + 8) 2314 #define DHBA_RSP_SIZE 16 2315 2316 #define DHAT_CMD 0x301 2317 #define DPRT_CMD 0x310 2318 #define DPA_CMD 0x311 2319 2320 /* CT command header -- request/response common fields */ 2321 struct ct_cmd_hdr { 2322 uint8_t revision; 2323 uint8_t in_id[3]; 2324 uint8_t gs_type; 2325 uint8_t gs_subtype; 2326 uint8_t options; 2327 uint8_t reserved; 2328 }; 2329 2330 /* CT command request */ 2331 struct ct_sns_req { 2332 struct ct_cmd_hdr header; 2333 uint16_t command; 2334 uint16_t max_rsp_size; 2335 uint8_t fragment_id; 2336 uint8_t reserved[3]; 2337 2338 union { 2339 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2340 struct { 2341 uint8_t reserved; 2342 uint8_t port_id[3]; 2343 } port_id; 2344 2345 struct { 2346 uint8_t port_type; 2347 uint8_t domain; 2348 uint8_t area; 2349 uint8_t reserved; 2350 } gid_pt; 2351 2352 struct { 2353 uint8_t reserved; 2354 uint8_t port_id[3]; 2355 uint8_t fc4_types[32]; 2356 } rft_id; 2357 2358 struct { 2359 uint8_t reserved; 2360 uint8_t port_id[3]; 2361 uint16_t reserved2; 2362 uint8_t fc4_feature; 2363 uint8_t fc4_type; 2364 } rff_id; 2365 2366 struct { 2367 uint8_t reserved; 2368 uint8_t port_id[3]; 2369 uint8_t node_name[8]; 2370 } rnn_id; 2371 2372 struct { 2373 uint8_t node_name[8]; 2374 uint8_t name_len; 2375 uint8_t sym_node_name[255]; 2376 } rsnn_nn; 2377 2378 struct { 2379 uint8_t hba_indentifier[8]; 2380 } ghat; 2381 2382 struct { 2383 uint8_t hba_identifier[8]; 2384 uint32_t entry_count; 2385 uint8_t port_name[8]; 2386 struct ct_fdmi_hba_attributes attrs; 2387 } rhba; 2388 2389 struct { 2390 uint8_t hba_identifier[8]; 2391 uint32_t entry_count; 2392 uint8_t port_name[8]; 2393 struct ct_fdmiv2_hba_attributes attrs; 2394 } rhba2; 2395 2396 struct { 2397 uint8_t hba_identifier[8]; 2398 struct ct_fdmi_hba_attributes attrs; 2399 } rhat; 2400 2401 struct { 2402 uint8_t port_name[8]; 2403 struct ct_fdmi_port_attributes attrs; 2404 } rpa; 2405 2406 struct { 2407 uint8_t port_name[8]; 2408 struct ct_fdmiv2_port_attributes attrs; 2409 } rpa2; 2410 2411 struct { 2412 uint8_t port_name[8]; 2413 } dhba; 2414 2415 struct { 2416 uint8_t port_name[8]; 2417 } dhat; 2418 2419 struct { 2420 uint8_t port_name[8]; 2421 } dprt; 2422 2423 struct { 2424 uint8_t port_name[8]; 2425 } dpa; 2426 2427 struct { 2428 uint8_t port_name[8]; 2429 } gpsc; 2430 2431 struct { 2432 uint8_t reserved; 2433 uint8_t port_name[3]; 2434 } gff_id; 2435 } req; 2436 }; 2437 2438 /* CT command response header */ 2439 struct ct_rsp_hdr { 2440 struct ct_cmd_hdr header; 2441 uint16_t response; 2442 uint16_t residual; 2443 uint8_t fragment_id; 2444 uint8_t reason_code; 2445 uint8_t explanation_code; 2446 uint8_t vendor_unique; 2447 }; 2448 2449 struct ct_sns_gid_pt_data { 2450 uint8_t control_byte; 2451 uint8_t port_id[3]; 2452 }; 2453 2454 struct ct_sns_rsp { 2455 struct ct_rsp_hdr header; 2456 2457 union { 2458 struct { 2459 uint8_t port_type; 2460 uint8_t port_id[3]; 2461 uint8_t port_name[8]; 2462 uint8_t sym_port_name_len; 2463 uint8_t sym_port_name[255]; 2464 uint8_t node_name[8]; 2465 uint8_t sym_node_name_len; 2466 uint8_t sym_node_name[255]; 2467 uint8_t init_proc_assoc[8]; 2468 uint8_t node_ip_addr[16]; 2469 uint8_t class_of_service[4]; 2470 uint8_t fc4_types[32]; 2471 uint8_t ip_address[16]; 2472 uint8_t fabric_port_name[8]; 2473 uint8_t reserved; 2474 uint8_t hard_address[3]; 2475 } ga_nxt; 2476 2477 struct { 2478 /* Assume the largest number of targets for the union */ 2479 struct ct_sns_gid_pt_data 2480 entries[MAX_FIBRE_DEVICES_MAX]; 2481 } gid_pt; 2482 2483 struct { 2484 uint8_t port_name[8]; 2485 } gpn_id; 2486 2487 struct { 2488 uint8_t node_name[8]; 2489 } gnn_id; 2490 2491 struct { 2492 uint8_t fc4_types[32]; 2493 } gft_id; 2494 2495 struct { 2496 uint32_t entry_count; 2497 uint8_t port_name[8]; 2498 struct ct_fdmi_hba_attributes attrs; 2499 } ghat; 2500 2501 struct { 2502 uint8_t port_name[8]; 2503 } gfpn_id; 2504 2505 struct { 2506 uint16_t speeds; 2507 uint16_t speed; 2508 } gpsc; 2509 2510 #define GFF_FCP_SCSI_OFFSET 7 2511 struct { 2512 uint8_t fc4_features[128]; 2513 } gff_id; 2514 } rsp; 2515 }; 2516 2517 struct ct_sns_pkt { 2518 union { 2519 struct ct_sns_req req; 2520 struct ct_sns_rsp rsp; 2521 } p; 2522 }; 2523 2524 /* 2525 * SNS command structures -- for 2200 compatibility. 2526 */ 2527 #define RFT_ID_SNS_SCMD_LEN 22 2528 #define RFT_ID_SNS_CMD_SIZE 60 2529 #define RFT_ID_SNS_DATA_SIZE 16 2530 2531 #define RNN_ID_SNS_SCMD_LEN 10 2532 #define RNN_ID_SNS_CMD_SIZE 36 2533 #define RNN_ID_SNS_DATA_SIZE 16 2534 2535 #define GA_NXT_SNS_SCMD_LEN 6 2536 #define GA_NXT_SNS_CMD_SIZE 28 2537 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 2538 2539 #define GID_PT_SNS_SCMD_LEN 6 2540 #define GID_PT_SNS_CMD_SIZE 28 2541 /* 2542 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 2543 * adapters. 2544 */ 2545 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 2546 2547 #define GPN_ID_SNS_SCMD_LEN 6 2548 #define GPN_ID_SNS_CMD_SIZE 28 2549 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 2550 2551 #define GNN_ID_SNS_SCMD_LEN 6 2552 #define GNN_ID_SNS_CMD_SIZE 28 2553 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 2554 2555 struct sns_cmd_pkt { 2556 union { 2557 struct { 2558 uint16_t buffer_length; 2559 uint16_t reserved_1; 2560 uint32_t buffer_address[2]; 2561 uint16_t subcommand_length; 2562 uint16_t reserved_2; 2563 uint16_t subcommand; 2564 uint16_t size; 2565 uint32_t reserved_3; 2566 uint8_t param[36]; 2567 } cmd; 2568 2569 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 2570 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 2571 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 2572 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 2573 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 2574 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 2575 } p; 2576 }; 2577 2578 struct fw_blob { 2579 char *name; 2580 uint32_t segs[4]; 2581 const struct firmware *fw; 2582 }; 2583 2584 /* Return data from MBC_GET_ID_LIST call. */ 2585 struct gid_list_info { 2586 uint8_t al_pa; 2587 uint8_t area; 2588 uint8_t domain; 2589 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2590 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2591 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 2592 }; 2593 2594 /* NPIV */ 2595 typedef struct vport_info { 2596 uint8_t port_name[WWN_SIZE]; 2597 uint8_t node_name[WWN_SIZE]; 2598 int vp_id; 2599 uint16_t loop_id; 2600 unsigned long host_no; 2601 uint8_t port_id[3]; 2602 int loop_state; 2603 } vport_info_t; 2604 2605 typedef struct vport_params { 2606 uint8_t port_name[WWN_SIZE]; 2607 uint8_t node_name[WWN_SIZE]; 2608 uint32_t options; 2609 #define VP_OPTS_RETRY_ENABLE BIT_0 2610 #define VP_OPTS_VP_DISABLE BIT_1 2611 } vport_params_t; 2612 2613 /* NPIV - return codes of VP create and modify */ 2614 #define VP_RET_CODE_OK 0 2615 #define VP_RET_CODE_FATAL 1 2616 #define VP_RET_CODE_WRONG_ID 2 2617 #define VP_RET_CODE_WWPN 3 2618 #define VP_RET_CODE_RESOURCES 4 2619 #define VP_RET_CODE_NO_MEM 5 2620 #define VP_RET_CODE_NOT_FOUND 6 2621 2622 struct qla_hw_data; 2623 struct rsp_que; 2624 /* 2625 * ISP operations 2626 */ 2627 struct isp_operations { 2628 2629 int (*pci_config) (struct scsi_qla_host *); 2630 void (*reset_chip) (struct scsi_qla_host *); 2631 int (*chip_diag) (struct scsi_qla_host *); 2632 void (*config_rings) (struct scsi_qla_host *); 2633 void (*reset_adapter) (struct scsi_qla_host *); 2634 int (*nvram_config) (struct scsi_qla_host *); 2635 void (*update_fw_options) (struct scsi_qla_host *); 2636 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 2637 2638 char * (*pci_info_str) (struct scsi_qla_host *, char *); 2639 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 2640 2641 irq_handler_t intr_handler; 2642 void (*enable_intrs) (struct qla_hw_data *); 2643 void (*disable_intrs) (struct qla_hw_data *); 2644 2645 int (*abort_command) (srb_t *); 2646 int (*target_reset) (struct fc_port *, uint64_t, int); 2647 int (*lun_reset) (struct fc_port *, uint64_t, int); 2648 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 2649 uint8_t, uint8_t, uint16_t *, uint8_t); 2650 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 2651 uint8_t, uint8_t); 2652 2653 uint16_t (*calc_req_entries) (uint16_t); 2654 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 2655 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t); 2656 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 2657 uint32_t); 2658 2659 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *, 2660 uint32_t, uint32_t); 2661 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 2662 uint32_t); 2663 2664 void (*fw_dump) (struct scsi_qla_host *, int); 2665 2666 int (*beacon_on) (struct scsi_qla_host *); 2667 int (*beacon_off) (struct scsi_qla_host *); 2668 void (*beacon_blink) (struct scsi_qla_host *); 2669 2670 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 2671 uint32_t, uint32_t); 2672 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 2673 uint32_t); 2674 2675 int (*get_flash_version) (struct scsi_qla_host *, void *); 2676 int (*start_scsi) (srb_t *); 2677 int (*abort_isp) (struct scsi_qla_host *); 2678 int (*iospace_config)(struct qla_hw_data*); 2679 int (*initialize_adapter)(struct scsi_qla_host *); 2680 }; 2681 2682 /* MSI-X Support *************************************************************/ 2683 2684 #define QLA_MSIX_CHIP_REV_24XX 3 2685 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 2686 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 2687 2688 #define QLA_MSIX_DEFAULT 0x00 2689 #define QLA_MSIX_RSP_Q 0x01 2690 2691 #define QLA_MIDX_DEFAULT 0 2692 #define QLA_MIDX_RSP_Q 1 2693 #define QLA_PCI_MSIX_CONTROL 0xa2 2694 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 2695 2696 struct scsi_qla_host; 2697 2698 struct qla_msix_entry { 2699 int have_irq; 2700 uint32_t vector; 2701 uint16_t entry; 2702 struct rsp_que *rsp; 2703 }; 2704 2705 #define WATCH_INTERVAL 1 /* number of seconds */ 2706 2707 /* Work events. */ 2708 enum qla_work_type { 2709 QLA_EVT_AEN, 2710 QLA_EVT_IDC_ACK, 2711 QLA_EVT_ASYNC_LOGIN, 2712 QLA_EVT_ASYNC_LOGIN_DONE, 2713 QLA_EVT_ASYNC_LOGOUT, 2714 QLA_EVT_ASYNC_LOGOUT_DONE, 2715 QLA_EVT_ASYNC_ADISC, 2716 QLA_EVT_ASYNC_ADISC_DONE, 2717 QLA_EVT_UEVENT, 2718 QLA_EVT_AENFX, 2719 }; 2720 2721 2722 struct qla_work_evt { 2723 struct list_head list; 2724 enum qla_work_type type; 2725 u32 flags; 2726 #define QLA_EVT_FLAG_FREE 0x1 2727 2728 union { 2729 struct { 2730 enum fc_host_event_code code; 2731 u32 data; 2732 } aen; 2733 struct { 2734 #define QLA_IDC_ACK_REGS 7 2735 uint16_t mb[QLA_IDC_ACK_REGS]; 2736 } idc_ack; 2737 struct { 2738 struct fc_port *fcport; 2739 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 2740 u16 data[2]; 2741 } logio; 2742 struct { 2743 u32 code; 2744 #define QLA_UEVENT_CODE_FW_DUMP 0 2745 } uevent; 2746 struct { 2747 uint32_t evtcode; 2748 uint32_t mbx[8]; 2749 uint32_t count; 2750 } aenfx; 2751 struct { 2752 srb_t *sp; 2753 } iosb; 2754 } u; 2755 }; 2756 2757 struct qla_chip_state_84xx { 2758 struct list_head list; 2759 struct kref kref; 2760 2761 void *bus; 2762 spinlock_t access_lock; 2763 struct mutex fw_update_mutex; 2764 uint32_t fw_update; 2765 uint32_t op_fw_version; 2766 uint32_t op_fw_size; 2767 uint32_t op_fw_seq_size; 2768 uint32_t diag_fw_version; 2769 uint32_t gold_fw_version; 2770 }; 2771 2772 struct qla_statistics { 2773 uint32_t total_isp_aborts; 2774 uint64_t input_bytes; 2775 uint64_t output_bytes; 2776 uint64_t input_requests; 2777 uint64_t output_requests; 2778 uint32_t control_requests; 2779 2780 uint64_t jiffies_at_last_reset; 2781 uint32_t stat_max_pend_cmds; 2782 uint32_t stat_max_qfull_cmds_alloc; 2783 uint32_t stat_max_qfull_cmds_dropped; 2784 }; 2785 2786 struct bidi_statistics { 2787 unsigned long long io_count; 2788 unsigned long long transfer_bytes; 2789 }; 2790 2791 /* Multi queue support */ 2792 #define MBC_INITIALIZE_MULTIQ 0x1f 2793 #define QLA_QUE_PAGE 0X1000 2794 #define QLA_MQ_SIZE 32 2795 #define QLA_MAX_QUEUES 256 2796 #define ISP_QUE_REG(ha, id) \ 2797 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \ 2798 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 2799 ((void __iomem *)ha->iobase)) 2800 #define QLA_REQ_QUE_ID(tag) \ 2801 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 2802 #define QLA_DEFAULT_QUE_QOS 5 2803 #define QLA_PRECONFIG_VPORTS 32 2804 #define QLA_MAX_VPORTS_QLA24XX 128 2805 #define QLA_MAX_VPORTS_QLA25XX 256 2806 /* Response queue data structure */ 2807 struct rsp_que { 2808 dma_addr_t dma; 2809 response_t *ring; 2810 response_t *ring_ptr; 2811 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 2812 uint32_t __iomem *rsp_q_out; 2813 uint16_t ring_index; 2814 uint16_t out_ptr; 2815 uint16_t *in_ptr; /* queue shadow in index */ 2816 uint16_t length; 2817 uint16_t options; 2818 uint16_t rid; 2819 uint16_t id; 2820 uint16_t vp_idx; 2821 struct qla_hw_data *hw; 2822 struct qla_msix_entry *msix; 2823 struct req_que *req; 2824 srb_t *status_srb; /* status continuation entry */ 2825 struct work_struct q_work; 2826 2827 dma_addr_t dma_fx00; 2828 response_t *ring_fx00; 2829 uint16_t length_fx00; 2830 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 2831 }; 2832 2833 /* Request queue data structure */ 2834 struct req_que { 2835 dma_addr_t dma; 2836 request_t *ring; 2837 request_t *ring_ptr; 2838 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 2839 uint32_t __iomem *req_q_out; 2840 uint16_t ring_index; 2841 uint16_t in_ptr; 2842 uint16_t *out_ptr; /* queue shadow out index */ 2843 uint16_t cnt; 2844 uint16_t length; 2845 uint16_t options; 2846 uint16_t rid; 2847 uint16_t id; 2848 uint16_t qos; 2849 uint16_t vp_idx; 2850 struct rsp_que *rsp; 2851 srb_t **outstanding_cmds; 2852 uint32_t current_outstanding_cmd; 2853 uint16_t num_outstanding_cmds; 2854 int max_q_depth; 2855 2856 dma_addr_t dma_fx00; 2857 request_t *ring_fx00; 2858 uint16_t length_fx00; 2859 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 2860 }; 2861 2862 /* Place holder for FW buffer parameters */ 2863 struct qlfc_fw { 2864 void *fw_buf; 2865 dma_addr_t fw_dma; 2866 uint32_t len; 2867 }; 2868 2869 struct scsi_qlt_host { 2870 void *target_lport_ptr; 2871 struct mutex tgt_mutex; 2872 struct mutex tgt_host_action_mutex; 2873 struct qla_tgt *qla_tgt; 2874 }; 2875 2876 struct qlt_hw_data { 2877 /* Protected by hw lock */ 2878 uint32_t enable_class_2:1; 2879 uint32_t enable_explicit_conf:1; 2880 uint32_t ini_mode_force_reverse:1; 2881 uint32_t node_name_set:1; 2882 2883 dma_addr_t atio_dma; /* Physical address. */ 2884 struct atio *atio_ring; /* Base virtual address */ 2885 struct atio *atio_ring_ptr; /* Current address. */ 2886 uint16_t atio_ring_index; /* Current index. */ 2887 uint16_t atio_q_length; 2888 uint32_t __iomem *atio_q_in; 2889 uint32_t __iomem *atio_q_out; 2890 2891 struct qla_tgt_func_tmpl *tgt_ops; 2892 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS]; 2893 uint16_t current_handle; 2894 2895 struct qla_tgt_vp_map *tgt_vp_map; 2896 2897 int saved_set; 2898 uint16_t saved_exchange_count; 2899 uint32_t saved_firmware_options_1; 2900 uint32_t saved_firmware_options_2; 2901 uint32_t saved_firmware_options_3; 2902 uint8_t saved_firmware_options[2]; 2903 uint8_t saved_add_firmware_options[2]; 2904 2905 uint8_t tgt_node_name[WWN_SIZE]; 2906 2907 struct list_head q_full_list; 2908 uint32_t num_pend_cmds; 2909 uint32_t num_qfull_cmds_alloc; 2910 uint32_t num_qfull_cmds_dropped; 2911 spinlock_t q_full_lock; 2912 uint32_t leak_exchg_thresh_hold; 2913 }; 2914 2915 #define MAX_QFULL_CMDS_ALLOC 8192 2916 #define Q_FULL_THRESH_HOLD_PERCENT 90 2917 #define Q_FULL_THRESH_HOLD(ha) \ 2918 ((ha->fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 2919 2920 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 2921 2922 /* 2923 * Qlogic host adapter specific data structure. 2924 */ 2925 struct qla_hw_data { 2926 struct pci_dev *pdev; 2927 /* SRB cache. */ 2928 #define SRB_MIN_REQ 128 2929 mempool_t *srb_mempool; 2930 2931 volatile struct { 2932 uint32_t mbox_int :1; 2933 uint32_t mbox_busy :1; 2934 uint32_t disable_risc_code_load :1; 2935 uint32_t enable_64bit_addressing :1; 2936 uint32_t enable_lip_reset :1; 2937 uint32_t enable_target_reset :1; 2938 uint32_t enable_lip_full_login :1; 2939 uint32_t enable_led_scheme :1; 2940 2941 uint32_t msi_enabled :1; 2942 uint32_t msix_enabled :1; 2943 uint32_t disable_serdes :1; 2944 uint32_t gpsc_supported :1; 2945 uint32_t npiv_supported :1; 2946 uint32_t pci_channel_io_perm_failure :1; 2947 uint32_t fce_enabled :1; 2948 uint32_t fac_supported :1; 2949 2950 uint32_t chip_reset_done :1; 2951 uint32_t running_gold_fw :1; 2952 uint32_t eeh_busy :1; 2953 uint32_t cpu_affinity_enabled :1; 2954 uint32_t disable_msix_handshake :1; 2955 uint32_t fcp_prio_enabled :1; 2956 uint32_t isp82xx_fw_hung:1; 2957 uint32_t nic_core_hung:1; 2958 2959 uint32_t quiesce_owner:1; 2960 uint32_t nic_core_reset_hdlr_active:1; 2961 uint32_t nic_core_reset_owner:1; 2962 uint32_t isp82xx_no_md_cap:1; 2963 uint32_t host_shutting_down:1; 2964 uint32_t idc_compl_status:1; 2965 2966 uint32_t mr_reset_hdlr_active:1; 2967 uint32_t mr_intr_valid:1; 2968 uint32_t fawwpn_enabled:1; 2969 /* 35 bits */ 2970 } flags; 2971 2972 /* This spinlock is used to protect "io transactions", you must 2973 * acquire it before doing any IO to the card, eg with RD_REG*() and 2974 * WRT_REG*() for the duration of your entire commandtransaction. 2975 * 2976 * This spinlock is of lower priority than the io request lock. 2977 */ 2978 2979 spinlock_t hardware_lock ____cacheline_aligned; 2980 int bars; 2981 int mem_only; 2982 device_reg_t *iobase; /* Base I/O address */ 2983 resource_size_t pio_address; 2984 2985 #define MIN_IOBASE_LEN 0x100 2986 dma_addr_t bar0_hdl; 2987 2988 void __iomem *cregbase; 2989 dma_addr_t bar2_hdl; 2990 #define BAR0_LEN_FX00 (1024 * 1024) 2991 #define BAR2_LEN_FX00 (128 * 1024) 2992 2993 uint32_t rqstq_intr_code; 2994 uint32_t mbx_intr_code; 2995 uint32_t req_que_len; 2996 uint32_t rsp_que_len; 2997 uint32_t req_que_off; 2998 uint32_t rsp_que_off; 2999 3000 /* Multi queue data structs */ 3001 device_reg_t *mqiobase; 3002 device_reg_t *msixbase; 3003 uint16_t msix_count; 3004 uint8_t mqenable; 3005 struct req_que **req_q_map; 3006 struct rsp_que **rsp_q_map; 3007 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3008 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3009 uint8_t max_req_queues; 3010 uint8_t max_rsp_queues; 3011 struct qla_npiv_entry *npiv_info; 3012 uint16_t nvram_npiv_size; 3013 3014 uint16_t switch_cap; 3015 #define FLOGI_SEQ_DEL BIT_8 3016 #define FLOGI_MID_SUPPORT BIT_10 3017 #define FLOGI_VSAN_SUPPORT BIT_12 3018 #define FLOGI_SP_SUPPORT BIT_13 3019 3020 uint8_t port_no; /* Physical port of adapter */ 3021 3022 /* Timeout timers. */ 3023 uint8_t loop_down_abort_time; /* port down timer */ 3024 atomic_t loop_down_timer; /* loop down timer */ 3025 uint8_t link_down_timeout; /* link down timeout */ 3026 uint16_t max_loop_id; 3027 uint16_t max_fibre_devices; /* Maximum number of targets */ 3028 3029 uint16_t fb_rev; 3030 uint16_t min_external_loopid; /* First external loop Id */ 3031 3032 #define PORT_SPEED_UNKNOWN 0xFFFF 3033 #define PORT_SPEED_1GB 0x00 3034 #define PORT_SPEED_2GB 0x01 3035 #define PORT_SPEED_4GB 0x03 3036 #define PORT_SPEED_8GB 0x04 3037 #define PORT_SPEED_16GB 0x05 3038 #define PORT_SPEED_32GB 0x06 3039 #define PORT_SPEED_10GB 0x13 3040 uint16_t link_data_rate; /* F/W operating speed */ 3041 3042 uint8_t current_topology; 3043 uint8_t prev_topology; 3044 #define ISP_CFG_NL 1 3045 #define ISP_CFG_N 2 3046 #define ISP_CFG_FL 4 3047 #define ISP_CFG_F 8 3048 3049 uint8_t operating_mode; /* F/W operating mode */ 3050 #define LOOP 0 3051 #define P2P 1 3052 #define LOOP_P2P 2 3053 #define P2P_LOOP 3 3054 uint8_t interrupts_on; 3055 uint32_t isp_abort_cnt; 3056 3057 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 3058 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 3059 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 3060 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 3061 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 3062 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 3063 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 3064 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 3065 3066 uint32_t device_type; 3067 #define DT_ISP2100 BIT_0 3068 #define DT_ISP2200 BIT_1 3069 #define DT_ISP2300 BIT_2 3070 #define DT_ISP2312 BIT_3 3071 #define DT_ISP2322 BIT_4 3072 #define DT_ISP6312 BIT_5 3073 #define DT_ISP6322 BIT_6 3074 #define DT_ISP2422 BIT_7 3075 #define DT_ISP2432 BIT_8 3076 #define DT_ISP5422 BIT_9 3077 #define DT_ISP5432 BIT_10 3078 #define DT_ISP2532 BIT_11 3079 #define DT_ISP8432 BIT_12 3080 #define DT_ISP8001 BIT_13 3081 #define DT_ISP8021 BIT_14 3082 #define DT_ISP2031 BIT_15 3083 #define DT_ISP8031 BIT_16 3084 #define DT_ISPFX00 BIT_17 3085 #define DT_ISP8044 BIT_18 3086 #define DT_ISP2071 BIT_19 3087 #define DT_ISP2271 BIT_20 3088 #define DT_ISP2261 BIT_21 3089 #define DT_ISP_LAST (DT_ISP2261 << 1) 3090 3091 #define DT_T10_PI BIT_25 3092 #define DT_IIDMA BIT_26 3093 #define DT_FWI2 BIT_27 3094 #define DT_ZIO_SUPPORTED BIT_28 3095 #define DT_OEM_001 BIT_29 3096 #define DT_ISP2200A BIT_30 3097 #define DT_EXTENDED_IDS BIT_31 3098 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1)) 3099 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 3100 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 3101 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 3102 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 3103 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 3104 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 3105 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 3106 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 3107 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 3108 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 3109 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 3110 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 3111 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 3112 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 3113 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 3114 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 3115 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 3116 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 3117 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 3118 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 3119 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 3120 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 3121 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 3122 3123 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 3124 IS_QLA6312(ha) || IS_QLA6322(ha)) 3125 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 3126 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 3127 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 3128 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 3129 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 3130 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 3131 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 3132 IS_QLA84XX(ha)) 3133 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 3134 IS_QLA8031(ha) || IS_QLA8044(ha)) 3135 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 3136 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 3137 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 3138 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 3139 IS_QLA8044(ha) || IS_QLA27XX(ha)) 3140 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3141 IS_QLA27XX(ha)) 3142 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 3143 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3144 IS_QLA27XX(ha)) 3145 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3146 IS_QLA27XX(ha)) 3147 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 3148 3149 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 3150 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 3151 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 3152 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 3153 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 3154 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 3155 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 3156 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 3157 IS_QLA27XX(ha)) 3158 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) 3159 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 3160 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3161 ((ha)->fw_attributes_ext[0] & BIT_0)) 3162 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3163 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3164 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3165 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3166 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3167 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3168 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3169 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3170 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha)) 3171 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3172 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3173 3174 /* HBA serial number */ 3175 uint8_t serial0; 3176 uint8_t serial1; 3177 uint8_t serial2; 3178 3179 /* NVRAM configuration data */ 3180 #define MAX_NVRAM_SIZE 4096 3181 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 3182 uint16_t nvram_size; 3183 uint16_t nvram_base; 3184 void *nvram; 3185 uint16_t vpd_size; 3186 uint16_t vpd_base; 3187 void *vpd; 3188 3189 uint16_t loop_reset_delay; 3190 uint8_t retry_count; 3191 uint8_t login_timeout; 3192 uint16_t r_a_tov; 3193 int port_down_retry_count; 3194 uint8_t mbx_count; 3195 uint8_t aen_mbx_count; 3196 3197 uint32_t login_retry_count; 3198 /* SNS command interfaces. */ 3199 ms_iocb_entry_t *ms_iocb; 3200 dma_addr_t ms_iocb_dma; 3201 struct ct_sns_pkt *ct_sns; 3202 dma_addr_t ct_sns_dma; 3203 /* SNS command interfaces for 2200. */ 3204 struct sns_cmd_pkt *sns_cmd; 3205 dma_addr_t sns_cmd_dma; 3206 3207 #define SFP_DEV_SIZE 256 3208 #define SFP_BLOCK_SIZE 64 3209 void *sfp_data; 3210 dma_addr_t sfp_data_dma; 3211 3212 #define XGMAC_DATA_SIZE 4096 3213 void *xgmac_data; 3214 dma_addr_t xgmac_data_dma; 3215 3216 #define DCBX_TLV_DATA_SIZE 4096 3217 void *dcbx_tlv; 3218 dma_addr_t dcbx_tlv_dma; 3219 3220 struct task_struct *dpc_thread; 3221 uint8_t dpc_active; /* DPC routine is active */ 3222 3223 dma_addr_t gid_list_dma; 3224 struct gid_list_info *gid_list; 3225 int gid_list_info_size; 3226 3227 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3228 #define DMA_POOL_SIZE 256 3229 struct dma_pool *s_dma_pool; 3230 3231 dma_addr_t init_cb_dma; 3232 init_cb_t *init_cb; 3233 int init_cb_size; 3234 dma_addr_t ex_init_cb_dma; 3235 struct ex_init_cb_81xx *ex_init_cb; 3236 3237 void *async_pd; 3238 dma_addr_t async_pd_dma; 3239 3240 void *swl; 3241 3242 /* These are used by mailbox operations. */ 3243 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3244 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 3245 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 3246 3247 mbx_cmd_t *mcp; 3248 struct mbx_cmd_32 *mcp32; 3249 3250 unsigned long mbx_cmd_flags; 3251 #define MBX_INTERRUPT 1 3252 #define MBX_INTR_WAIT 2 3253 #define MBX_UPDATE_FLASH_ACTIVE 3 3254 3255 struct mutex vport_lock; /* Virtual port synchronization */ 3256 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 3257 struct completion mbx_cmd_comp; /* Serialize mbx access */ 3258 struct completion mbx_intr_comp; /* Used for completion notification */ 3259 struct completion dcbx_comp; /* For set port config notification */ 3260 struct completion lb_portup_comp; /* Used to wait for link up during 3261 * loopback */ 3262 #define DCBX_COMP_TIMEOUT 20 3263 #define LB_PORTUP_COMP_TIMEOUT 10 3264 3265 int notify_dcbx_comp; 3266 int notify_lb_portup_comp; 3267 struct mutex selflogin_lock; 3268 3269 /* Basic firmware related information. */ 3270 uint16_t fw_major_version; 3271 uint16_t fw_minor_version; 3272 uint16_t fw_subminor_version; 3273 uint16_t fw_attributes; 3274 uint16_t fw_attributes_h; 3275 uint16_t fw_attributes_ext[2]; 3276 uint32_t fw_memory_size; 3277 uint32_t fw_transfer_size; 3278 uint32_t fw_srisc_address; 3279 #define RISC_START_ADDRESS_2100 0x1000 3280 #define RISC_START_ADDRESS_2300 0x800 3281 #define RISC_START_ADDRESS_2400 0x100000 3282 uint16_t fw_xcb_count; 3283 uint16_t fw_iocb_count; 3284 3285 uint32_t fw_shared_ram_start; 3286 uint32_t fw_shared_ram_end; 3287 3288 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 3289 uint8_t fw_seriallink_options[4]; 3290 uint16_t fw_seriallink_options24[4]; 3291 3292 uint8_t mpi_version[3]; 3293 uint32_t mpi_capabilities; 3294 uint8_t phy_version[3]; 3295 uint8_t pep_version[3]; 3296 3297 /* Firmware dump template */ 3298 void *fw_dump_template; 3299 uint32_t fw_dump_template_len; 3300 /* Firmware dump information. */ 3301 struct qla2xxx_fw_dump *fw_dump; 3302 uint32_t fw_dump_len; 3303 int fw_dumped; 3304 unsigned long fw_dump_cap_flags; 3305 #define RISC_PAUSE_CMPL 0 3306 #define DMA_SHUTDOWN_CMPL 1 3307 #define ISP_RESET_CMPL 2 3308 #define RISC_RDY_AFT_RESET 3 3309 #define RISC_SRAM_DUMP_CMPL 4 3310 #define RISC_EXT_MEM_DUMP_CMPL 5 3311 #define ISP_MBX_RDY 6 3312 #define ISP_SOFT_RESET_CMPL 7 3313 int fw_dump_reading; 3314 int prev_minidump_failed; 3315 dma_addr_t eft_dma; 3316 void *eft; 3317 /* Current size of mctp dump is 0x086064 bytes */ 3318 #define MCTP_DUMP_SIZE 0x086064 3319 dma_addr_t mctp_dump_dma; 3320 void *mctp_dump; 3321 int mctp_dumped; 3322 int mctp_dump_reading; 3323 uint32_t chain_offset; 3324 struct dentry *dfs_dir; 3325 struct dentry *dfs_fce; 3326 dma_addr_t fce_dma; 3327 void *fce; 3328 uint32_t fce_bufs; 3329 uint16_t fce_mb[8]; 3330 uint64_t fce_wr, fce_rd; 3331 struct mutex fce_mutex; 3332 3333 uint32_t pci_attr; 3334 uint16_t chip_revision; 3335 3336 uint16_t product_id[4]; 3337 3338 uint8_t model_number[16+1]; 3339 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 3340 char model_desc[80]; 3341 uint8_t adapter_id[16+1]; 3342 3343 /* Option ROM information. */ 3344 char *optrom_buffer; 3345 uint32_t optrom_size; 3346 int optrom_state; 3347 #define QLA_SWAITING 0 3348 #define QLA_SREADING 1 3349 #define QLA_SWRITING 2 3350 uint32_t optrom_region_start; 3351 uint32_t optrom_region_size; 3352 struct mutex optrom_mutex; 3353 3354 /* PCI expansion ROM image information. */ 3355 #define ROM_CODE_TYPE_BIOS 0 3356 #define ROM_CODE_TYPE_FCODE 1 3357 #define ROM_CODE_TYPE_EFI 3 3358 uint8_t bios_revision[2]; 3359 uint8_t efi_revision[2]; 3360 uint8_t fcode_revision[16]; 3361 uint32_t fw_revision[4]; 3362 3363 uint32_t gold_fw_version[4]; 3364 3365 /* Offsets for flash/nvram access (set to ~0 if not used). */ 3366 uint32_t flash_conf_off; 3367 uint32_t flash_data_off; 3368 uint32_t nvram_conf_off; 3369 uint32_t nvram_data_off; 3370 3371 uint32_t fdt_wrt_disable; 3372 uint32_t fdt_wrt_enable; 3373 uint32_t fdt_erase_cmd; 3374 uint32_t fdt_block_size; 3375 uint32_t fdt_unprotect_sec_cmd; 3376 uint32_t fdt_protect_sec_cmd; 3377 uint32_t fdt_wrt_sts_reg_cmd; 3378 3379 uint32_t flt_region_flt; 3380 uint32_t flt_region_fdt; 3381 uint32_t flt_region_boot; 3382 uint32_t flt_region_fw; 3383 uint32_t flt_region_vpd_nvram; 3384 uint32_t flt_region_vpd; 3385 uint32_t flt_region_nvram; 3386 uint32_t flt_region_npiv_conf; 3387 uint32_t flt_region_gold_fw; 3388 uint32_t flt_region_fcp_prio; 3389 uint32_t flt_region_bootload; 3390 3391 /* Needed for BEACON */ 3392 uint16_t beacon_blink_led; 3393 uint8_t beacon_color_state; 3394 #define QLA_LED_GRN_ON 0x01 3395 #define QLA_LED_YLW_ON 0x02 3396 #define QLA_LED_ABR_ON 0x04 3397 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 3398 /* ISP2322: red, green, amber. */ 3399 uint16_t zio_mode; 3400 uint16_t zio_timer; 3401 3402 struct qla_msix_entry *msix_entries; 3403 3404 struct list_head vp_list; /* list of VP */ 3405 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 3406 sizeof(unsigned long)]; 3407 uint16_t num_vhosts; /* number of vports created */ 3408 uint16_t num_vsans; /* number of vsan created */ 3409 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 3410 int cur_vport_count; 3411 3412 struct qla_chip_state_84xx *cs84xx; 3413 struct qla_statistics qla_stats; 3414 struct isp_operations *isp_ops; 3415 struct workqueue_struct *wq; 3416 struct qlfc_fw fw_buf; 3417 3418 /* FCP_CMND priority support */ 3419 struct qla_fcp_prio_cfg *fcp_prio_cfg; 3420 3421 struct dma_pool *dl_dma_pool; 3422 #define DSD_LIST_DMA_POOL_SIZE 512 3423 3424 struct dma_pool *fcp_cmnd_dma_pool; 3425 mempool_t *ctx_mempool; 3426 #define FCP_CMND_DMA_POOL_SIZE 512 3427 3428 void __iomem *nx_pcibase; /* Base I/O address */ 3429 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 3430 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 3431 3432 uint32_t crb_win; 3433 uint32_t curr_window; 3434 uint32_t ddr_mn_window; 3435 unsigned long mn_win_crb; 3436 unsigned long ms_win_crb; 3437 int qdr_sn_window; 3438 uint32_t fcoe_dev_init_timeout; 3439 uint32_t fcoe_reset_timeout; 3440 rwlock_t hw_lock; 3441 uint16_t portnum; /* port number */ 3442 int link_width; 3443 struct fw_blob *hablob; 3444 struct qla82xx_legacy_intr_set nx_legacy_intr; 3445 3446 uint16_t gbl_dsd_inuse; 3447 uint16_t gbl_dsd_avail; 3448 struct list_head gbl_dsd_list; 3449 #define NUM_DSD_CHAIN 4096 3450 3451 uint8_t fw_type; 3452 __le32 file_prd_off; /* File firmware product offset */ 3453 3454 uint32_t md_template_size; 3455 void *md_tmplt_hdr; 3456 dma_addr_t md_tmplt_hdr_dma; 3457 void *md_dump; 3458 uint32_t md_dump_size; 3459 3460 void *loop_id_map; 3461 3462 /* QLA83XX IDC specific fields */ 3463 uint32_t idc_audit_ts; 3464 uint32_t idc_extend_tmo; 3465 3466 /* DPC low-priority workqueue */ 3467 struct workqueue_struct *dpc_lp_wq; 3468 struct work_struct idc_aen; 3469 /* DPC high-priority workqueue */ 3470 struct workqueue_struct *dpc_hp_wq; 3471 struct work_struct nic_core_reset; 3472 struct work_struct idc_state_handler; 3473 struct work_struct nic_core_unrecoverable; 3474 struct work_struct board_disable; 3475 3476 struct mr_data_fx00 mr; 3477 uint32_t chip_reset; 3478 3479 struct qlt_hw_data tgt; 3480 int allow_cna_fw_dump; 3481 }; 3482 3483 /* 3484 * Qlogic scsi host structure 3485 */ 3486 typedef struct scsi_qla_host { 3487 struct list_head list; 3488 struct list_head vp_fcports; /* list of fcports */ 3489 struct list_head work_list; 3490 spinlock_t work_lock; 3491 3492 /* Commonly used flags and state information. */ 3493 struct Scsi_Host *host; 3494 unsigned long host_no; 3495 uint8_t host_str[16]; 3496 3497 volatile struct { 3498 uint32_t init_done :1; 3499 uint32_t online :1; 3500 uint32_t reset_active :1; 3501 3502 uint32_t management_server_logged_in :1; 3503 uint32_t process_response_queue :1; 3504 uint32_t difdix_supported:1; 3505 uint32_t delete_progress:1; 3506 3507 uint32_t fw_tgt_reported:1; 3508 } flags; 3509 3510 atomic_t loop_state; 3511 #define LOOP_TIMEOUT 1 3512 #define LOOP_DOWN 2 3513 #define LOOP_UP 3 3514 #define LOOP_UPDATE 4 3515 #define LOOP_READY 5 3516 #define LOOP_DEAD 6 3517 3518 unsigned long dpc_flags; 3519 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 3520 #define RESET_ACTIVE 1 3521 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 3522 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 3523 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 3524 #define LOOP_RESYNC_ACTIVE 5 3525 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 3526 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 3527 #define RELOGIN_NEEDED 8 3528 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 3529 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 3530 #define BEACON_BLINK_NEEDED 11 3531 #define REGISTER_FDMI_NEEDED 12 3532 #define FCPORT_UPDATE_NEEDED 13 3533 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 3534 #define UNLOADING 15 3535 #define NPIV_CONFIG_NEEDED 16 3536 #define ISP_UNRECOVERABLE 17 3537 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 3538 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 3539 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 3540 #define SCR_PENDING 21 /* SCR in target mode */ 3541 #define PORT_UPDATE_NEEDED 22 3542 #define FX00_RESET_RECOVERY 23 3543 #define FX00_TARGET_SCAN 24 3544 #define FX00_CRITEMP_RECOVERY 25 3545 #define FX00_HOST_INFO_RESEND 26 3546 3547 unsigned long pci_flags; 3548 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 3549 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 3550 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 3551 3552 uint32_t device_flags; 3553 #define SWITCH_FOUND BIT_0 3554 #define DFLG_NO_CABLE BIT_1 3555 #define DFLG_DEV_FAILED BIT_5 3556 3557 /* ISP configuration data. */ 3558 uint16_t loop_id; /* Host adapter loop id */ 3559 uint16_t self_login_loop_id; /* host adapter loop id 3560 * get it on self login 3561 */ 3562 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 3563 * no need of allocating it for 3564 * each command 3565 */ 3566 3567 port_id_t d_id; /* Host adapter port id */ 3568 uint8_t marker_needed; 3569 uint16_t mgmt_svr_loop_id; 3570 3571 3572 3573 /* Timeout timers. */ 3574 uint8_t loop_down_abort_time; /* port down timer */ 3575 atomic_t loop_down_timer; /* loop down timer */ 3576 uint8_t link_down_timeout; /* link down timeout */ 3577 3578 uint32_t timer_active; 3579 struct timer_list timer; 3580 3581 uint8_t node_name[WWN_SIZE]; 3582 uint8_t port_name[WWN_SIZE]; 3583 uint8_t fabric_node_name[WWN_SIZE]; 3584 3585 uint16_t fcoe_vlan_id; 3586 uint16_t fcoe_fcf_idx; 3587 uint8_t fcoe_vn_port_mac[6]; 3588 3589 /* list of commands waiting on workqueue */ 3590 struct list_head qla_cmd_list; 3591 struct list_head qla_sess_op_cmd_list; 3592 spinlock_t cmd_list_lock; 3593 3594 /* Counter to detect races between ELS and RSCN events */ 3595 atomic_t generation_tick; 3596 /* Time when global fcport update has been scheduled */ 3597 int total_fcport_update_gen; 3598 3599 uint32_t vp_abort_cnt; 3600 3601 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 3602 uint16_t vp_idx; /* vport ID */ 3603 3604 unsigned long vp_flags; 3605 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 3606 #define VP_CREATE_NEEDED 1 3607 #define VP_BIND_NEEDED 2 3608 #define VP_DELETE_NEEDED 3 3609 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 3610 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 3611 atomic_t vp_state; 3612 #define VP_OFFLINE 0 3613 #define VP_ACTIVE 1 3614 #define VP_FAILED 2 3615 // #define VP_DISABLE 3 3616 uint16_t vp_err_state; 3617 uint16_t vp_prev_err_state; 3618 #define VP_ERR_UNKWN 0 3619 #define VP_ERR_PORTDWN 1 3620 #define VP_ERR_FAB_UNSUPPORTED 2 3621 #define VP_ERR_FAB_NORESOURCES 3 3622 #define VP_ERR_FAB_LOGOUT 4 3623 #define VP_ERR_ADAP_NORESOURCES 5 3624 struct qla_hw_data *hw; 3625 struct scsi_qlt_host vha_tgt; 3626 struct req_que *req; 3627 int fw_heartbeat_counter; 3628 int seconds_since_last_heartbeat; 3629 struct fc_host_statistics fc_host_stat; 3630 struct qla_statistics qla_stats; 3631 struct bidi_statistics bidi_stats; 3632 3633 atomic_t vref_count; 3634 struct qla8044_reset_template reset_tmplt; 3635 } scsi_qla_host_t; 3636 3637 #define SET_VP_IDX 1 3638 #define SET_AL_PA 2 3639 #define RESET_VP_IDX 3 3640 #define RESET_AL_PA 4 3641 struct qla_tgt_vp_map { 3642 uint8_t idx; 3643 scsi_qla_host_t *vha; 3644 }; 3645 3646 /* 3647 * Macros to help code, maintain, etc. 3648 */ 3649 #define LOOP_TRANSITION(ha) \ 3650 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3651 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 3652 atomic_read(&ha->loop_state) == LOOP_DOWN) 3653 3654 #define STATE_TRANSITION(ha) \ 3655 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3656 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 3657 3658 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 3659 atomic_inc(&__vha->vref_count); \ 3660 mb(); \ 3661 if (__vha->flags.delete_progress) { \ 3662 atomic_dec(&__vha->vref_count); \ 3663 __bail = 1; \ 3664 } else { \ 3665 __bail = 0; \ 3666 } \ 3667 } while (0) 3668 3669 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 3670 atomic_dec(&__vha->vref_count); \ 3671 } while (0) 3672 3673 /* 3674 * qla2x00 local function return status codes 3675 */ 3676 #define MBS_MASK 0x3fff 3677 3678 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 3679 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 3680 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 3681 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 3682 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 3683 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 3684 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 3685 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 3686 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 3687 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 3688 3689 #define QLA_FUNCTION_TIMEOUT 0x100 3690 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 3691 #define QLA_FUNCTION_FAILED 0x102 3692 #define QLA_MEMORY_ALLOC_FAILED 0x103 3693 #define QLA_LOCK_TIMEOUT 0x104 3694 #define QLA_ABORTED 0x105 3695 #define QLA_SUSPENDED 0x106 3696 #define QLA_BUSY 0x107 3697 #define QLA_ALREADY_REGISTERED 0x109 3698 3699 #define NVRAM_DELAY() udelay(10) 3700 3701 /* 3702 * Flash support definitions 3703 */ 3704 #define OPTROM_SIZE_2300 0x20000 3705 #define OPTROM_SIZE_2322 0x100000 3706 #define OPTROM_SIZE_24XX 0x100000 3707 #define OPTROM_SIZE_25XX 0x200000 3708 #define OPTROM_SIZE_81XX 0x400000 3709 #define OPTROM_SIZE_82XX 0x800000 3710 #define OPTROM_SIZE_83XX 0x1000000 3711 3712 #define OPTROM_BURST_SIZE 0x1000 3713 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3714 3715 #define QLA_DSDS_PER_IOCB 37 3716 3717 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 3718 3719 #define QLA_SG_ALL 1024 3720 3721 enum nexus_wait_type { 3722 WAIT_HOST = 0, 3723 WAIT_TARGET, 3724 WAIT_LUN, 3725 }; 3726 3727 #include "qla_gbl.h" 3728 #include "qla_dbg.h" 3729 #include "qla_inline.h" 3730 #endif 3731