1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2008 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 35 #define QLA2XXX_DRIVER_NAME "qla2xxx" 36 37 /* 38 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 39 * but that's fine as we don't look at the last 24 ones for 40 * ISP2100 HBAs. 41 */ 42 #define MAILBOX_REGISTER_COUNT_2100 8 43 #define MAILBOX_REGISTER_COUNT 32 44 45 #define QLA2200A_RISC_ROM_VER 4 46 #define FPM_2300 6 47 #define FPM_2310 7 48 49 #include "qla_settings.h" 50 51 /* 52 * Data bit definitions 53 */ 54 #define BIT_0 0x1 55 #define BIT_1 0x2 56 #define BIT_2 0x4 57 #define BIT_3 0x8 58 #define BIT_4 0x10 59 #define BIT_5 0x20 60 #define BIT_6 0x40 61 #define BIT_7 0x80 62 #define BIT_8 0x100 63 #define BIT_9 0x200 64 #define BIT_10 0x400 65 #define BIT_11 0x800 66 #define BIT_12 0x1000 67 #define BIT_13 0x2000 68 #define BIT_14 0x4000 69 #define BIT_15 0x8000 70 #define BIT_16 0x10000 71 #define BIT_17 0x20000 72 #define BIT_18 0x40000 73 #define BIT_19 0x80000 74 #define BIT_20 0x100000 75 #define BIT_21 0x200000 76 #define BIT_22 0x400000 77 #define BIT_23 0x800000 78 #define BIT_24 0x1000000 79 #define BIT_25 0x2000000 80 #define BIT_26 0x4000000 81 #define BIT_27 0x8000000 82 #define BIT_28 0x10000000 83 #define BIT_29 0x20000000 84 #define BIT_30 0x40000000 85 #define BIT_31 0x80000000 86 87 #define LSB(x) ((uint8_t)(x)) 88 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 89 90 #define LSW(x) ((uint16_t)(x)) 91 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 92 93 #define LSD(x) ((uint32_t)((uint64_t)(x))) 94 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 95 96 97 /* 98 * I/O register 99 */ 100 101 #define RD_REG_BYTE(addr) readb(addr) 102 #define RD_REG_WORD(addr) readw(addr) 103 #define RD_REG_DWORD(addr) readl(addr) 104 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 105 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 106 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 107 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 108 #define WRT_REG_WORD(addr, data) writew(data,addr) 109 #define WRT_REG_DWORD(addr, data) writel(data,addr) 110 111 /* 112 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 113 * 133Mhz slot. 114 */ 115 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 116 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 117 118 /* 119 * Fibre Channel device definitions. 120 */ 121 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 122 #define MAX_FIBRE_DEVICES 512 123 #define MAX_FIBRE_LUNS 0xFFFF 124 #define MAX_RSCN_COUNT 32 125 #define MAX_HOST_COUNT 16 126 127 /* 128 * Host adapter default definitions. 129 */ 130 #define MAX_BUSES 1 /* We only have one bus today */ 131 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES 132 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES 133 #define MIN_LUNS 8 134 #define MAX_LUNS MAX_FIBRE_LUNS 135 #define MAX_CMDS_PER_LUN 255 136 137 /* 138 * Fibre Channel device definitions. 139 */ 140 #define SNS_LAST_LOOP_ID_2100 0xfe 141 #define SNS_LAST_LOOP_ID_2300 0x7ff 142 143 #define LAST_LOCAL_LOOP_ID 0x7d 144 #define SNS_FL_PORT 0x7e 145 #define FABRIC_CONTROLLER 0x7f 146 #define SIMPLE_NAME_SERVER 0x80 147 #define SNS_FIRST_LOOP_ID 0x81 148 #define MANAGEMENT_SERVER 0xfe 149 #define BROADCAST 0xff 150 151 /* 152 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 153 * valid range of an N-PORT id is 0 through 0x7ef. 154 */ 155 #define NPH_LAST_HANDLE 0x7ef 156 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ 157 #define NPH_SNS 0x7fc /* FFFFFC */ 158 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 159 #define NPH_F_PORT 0x7fe /* FFFFFE */ 160 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 161 162 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 163 #include "qla_fw.h" 164 165 /* 166 * Timeout timer counts in seconds 167 */ 168 #define PORT_RETRY_TIME 1 169 #define LOOP_DOWN_TIMEOUT 60 170 #define LOOP_DOWN_TIME 255 /* 240 */ 171 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 172 173 /* Maximum outstanding commands in ISP queues (1-65535) */ 174 #define MAX_OUTSTANDING_COMMANDS 1024 175 176 /* ISP request and response entry counts (37-65535) */ 177 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 178 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 179 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 180 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 181 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 182 183 struct req_que; 184 185 /* 186 * SCSI Request Block 187 */ 188 typedef struct srb { 189 struct req_que *que; 190 struct fc_port *fcport; 191 192 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 193 194 uint16_t flags; 195 196 uint32_t request_sense_length; 197 uint8_t *request_sense_ptr; 198 } srb_t; 199 200 /* 201 * SRB flag definitions 202 */ 203 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 204 205 /* 206 * ISP I/O Register Set structure definitions. 207 */ 208 struct device_reg_2xxx { 209 uint16_t flash_address; /* Flash BIOS address */ 210 uint16_t flash_data; /* Flash BIOS data */ 211 uint16_t unused_1[1]; /* Gap */ 212 uint16_t ctrl_status; /* Control/Status */ 213 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 214 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 215 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 216 217 uint16_t ictrl; /* Interrupt control */ 218 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 219 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 220 221 uint16_t istatus; /* Interrupt status */ 222 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 223 224 uint16_t semaphore; /* Semaphore */ 225 uint16_t nvram; /* NVRAM register. */ 226 #define NVR_DESELECT 0 227 #define NVR_BUSY BIT_15 228 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 229 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 230 #define NVR_DATA_IN BIT_3 231 #define NVR_DATA_OUT BIT_2 232 #define NVR_SELECT BIT_1 233 #define NVR_CLOCK BIT_0 234 235 #define NVR_WAIT_CNT 20000 236 237 union { 238 struct { 239 uint16_t mailbox0; 240 uint16_t mailbox1; 241 uint16_t mailbox2; 242 uint16_t mailbox3; 243 uint16_t mailbox4; 244 uint16_t mailbox5; 245 uint16_t mailbox6; 246 uint16_t mailbox7; 247 uint16_t unused_2[59]; /* Gap */ 248 } __attribute__((packed)) isp2100; 249 struct { 250 /* Request Queue */ 251 uint16_t req_q_in; /* In-Pointer */ 252 uint16_t req_q_out; /* Out-Pointer */ 253 /* Response Queue */ 254 uint16_t rsp_q_in; /* In-Pointer */ 255 uint16_t rsp_q_out; /* Out-Pointer */ 256 257 /* RISC to Host Status */ 258 uint32_t host_status; 259 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 260 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 261 262 /* Host to Host Semaphore */ 263 uint16_t host_semaphore; 264 uint16_t unused_3[17]; /* Gap */ 265 uint16_t mailbox0; 266 uint16_t mailbox1; 267 uint16_t mailbox2; 268 uint16_t mailbox3; 269 uint16_t mailbox4; 270 uint16_t mailbox5; 271 uint16_t mailbox6; 272 uint16_t mailbox7; 273 uint16_t mailbox8; 274 uint16_t mailbox9; 275 uint16_t mailbox10; 276 uint16_t mailbox11; 277 uint16_t mailbox12; 278 uint16_t mailbox13; 279 uint16_t mailbox14; 280 uint16_t mailbox15; 281 uint16_t mailbox16; 282 uint16_t mailbox17; 283 uint16_t mailbox18; 284 uint16_t mailbox19; 285 uint16_t mailbox20; 286 uint16_t mailbox21; 287 uint16_t mailbox22; 288 uint16_t mailbox23; 289 uint16_t mailbox24; 290 uint16_t mailbox25; 291 uint16_t mailbox26; 292 uint16_t mailbox27; 293 uint16_t mailbox28; 294 uint16_t mailbox29; 295 uint16_t mailbox30; 296 uint16_t mailbox31; 297 uint16_t fb_cmd; 298 uint16_t unused_4[10]; /* Gap */ 299 } __attribute__((packed)) isp2300; 300 } u; 301 302 uint16_t fpm_diag_config; 303 uint16_t unused_5[0x4]; /* Gap */ 304 uint16_t risc_hw; 305 uint16_t unused_5_1; /* Gap */ 306 uint16_t pcr; /* Processor Control Register. */ 307 uint16_t unused_6[0x5]; /* Gap */ 308 uint16_t mctr; /* Memory Configuration and Timing. */ 309 uint16_t unused_7[0x3]; /* Gap */ 310 uint16_t fb_cmd_2100; /* Unused on 23XX */ 311 uint16_t unused_8[0x3]; /* Gap */ 312 uint16_t hccr; /* Host command & control register. */ 313 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 314 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 315 /* HCCR commands */ 316 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 317 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 318 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 319 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 320 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 321 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 322 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 323 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 324 325 uint16_t unused_9[5]; /* Gap */ 326 uint16_t gpiod; /* GPIO Data register. */ 327 uint16_t gpioe; /* GPIO Enable register. */ 328 #define GPIO_LED_MASK 0x00C0 329 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 330 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 331 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 332 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 333 #define GPIO_LED_ALL_OFF 0x0000 334 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 335 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 336 337 union { 338 struct { 339 uint16_t unused_10[8]; /* Gap */ 340 uint16_t mailbox8; 341 uint16_t mailbox9; 342 uint16_t mailbox10; 343 uint16_t mailbox11; 344 uint16_t mailbox12; 345 uint16_t mailbox13; 346 uint16_t mailbox14; 347 uint16_t mailbox15; 348 uint16_t mailbox16; 349 uint16_t mailbox17; 350 uint16_t mailbox18; 351 uint16_t mailbox19; 352 uint16_t mailbox20; 353 uint16_t mailbox21; 354 uint16_t mailbox22; 355 uint16_t mailbox23; /* Also probe reg. */ 356 } __attribute__((packed)) isp2200; 357 } u_end; 358 }; 359 360 struct device_reg_25xxmq { 361 uint32_t req_q_in; 362 uint32_t req_q_out; 363 uint32_t rsp_q_in; 364 uint32_t rsp_q_out; 365 }; 366 367 typedef union { 368 struct device_reg_2xxx isp; 369 struct device_reg_24xx isp24; 370 struct device_reg_25xxmq isp25mq; 371 } device_reg_t; 372 373 #define ISP_REQ_Q_IN(ha, reg) \ 374 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 375 &(reg)->u.isp2100.mailbox4 : \ 376 &(reg)->u.isp2300.req_q_in) 377 #define ISP_REQ_Q_OUT(ha, reg) \ 378 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 379 &(reg)->u.isp2100.mailbox4 : \ 380 &(reg)->u.isp2300.req_q_out) 381 #define ISP_RSP_Q_IN(ha, reg) \ 382 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 383 &(reg)->u.isp2100.mailbox5 : \ 384 &(reg)->u.isp2300.rsp_q_in) 385 #define ISP_RSP_Q_OUT(ha, reg) \ 386 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 387 &(reg)->u.isp2100.mailbox5 : \ 388 &(reg)->u.isp2300.rsp_q_out) 389 390 #define MAILBOX_REG(ha, reg, num) \ 391 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 392 (num < 8 ? \ 393 &(reg)->u.isp2100.mailbox0 + (num) : \ 394 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 395 &(reg)->u.isp2300.mailbox0 + (num)) 396 #define RD_MAILBOX_REG(ha, reg, num) \ 397 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 398 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 399 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 400 401 #define FB_CMD_REG(ha, reg) \ 402 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 403 &(reg)->fb_cmd_2100 : \ 404 &(reg)->u.isp2300.fb_cmd) 405 #define RD_FB_CMD_REG(ha, reg) \ 406 RD_REG_WORD(FB_CMD_REG(ha, reg)) 407 #define WRT_FB_CMD_REG(ha, reg, data) \ 408 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 409 410 typedef struct { 411 uint32_t out_mb; /* outbound from driver */ 412 uint32_t in_mb; /* Incoming from RISC */ 413 uint16_t mb[MAILBOX_REGISTER_COUNT]; 414 long buf_size; 415 void *bufp; 416 uint32_t tov; 417 uint8_t flags; 418 #define MBX_DMA_IN BIT_0 419 #define MBX_DMA_OUT BIT_1 420 #define IOCTL_CMD BIT_2 421 } mbx_cmd_t; 422 423 #define MBX_TOV_SECONDS 30 424 425 /* 426 * ISP product identification definitions in mailboxes after reset. 427 */ 428 #define PROD_ID_1 0x4953 429 #define PROD_ID_2 0x0000 430 #define PROD_ID_2a 0x5020 431 #define PROD_ID_3 0x2020 432 433 /* 434 * ISP mailbox Self-Test status codes 435 */ 436 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 437 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 438 #define MBS_BUSY 4 /* Busy. */ 439 440 /* 441 * ISP mailbox command complete status codes 442 */ 443 #define MBS_COMMAND_COMPLETE 0x4000 444 #define MBS_INVALID_COMMAND 0x4001 445 #define MBS_HOST_INTERFACE_ERROR 0x4002 446 #define MBS_TEST_FAILED 0x4003 447 #define MBS_COMMAND_ERROR 0x4005 448 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 449 #define MBS_PORT_ID_USED 0x4007 450 #define MBS_LOOP_ID_USED 0x4008 451 #define MBS_ALL_IDS_IN_USE 0x4009 452 #define MBS_NOT_LOGGED_IN 0x400A 453 #define MBS_LINK_DOWN_ERROR 0x400B 454 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 455 456 /* 457 * ISP mailbox asynchronous event status codes 458 */ 459 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 460 #define MBA_RESET 0x8001 /* Reset Detected. */ 461 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 462 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 463 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 464 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 465 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 466 /* occurred. */ 467 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 468 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 469 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 470 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 471 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 472 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 473 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 474 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 475 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 476 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 477 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 478 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 479 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 480 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 481 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 482 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 483 /* used. */ 484 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 485 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 486 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 487 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 488 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 489 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 490 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 491 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 492 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 493 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 494 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 495 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 496 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 497 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 498 499 /* 500 * Firmware options 1, 2, 3. 501 */ 502 #define FO1_AE_ON_LIPF8 BIT_0 503 #define FO1_AE_ALL_LIP_RESET BIT_1 504 #define FO1_CTIO_RETRY BIT_3 505 #define FO1_DISABLE_LIP_F7_SW BIT_4 506 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 507 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 508 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 509 #define FO1_SET_EMPHASIS_SWING BIT_8 510 #define FO1_AE_AUTO_BYPASS BIT_9 511 #define FO1_ENABLE_PURE_IOCB BIT_10 512 #define FO1_AE_PLOGI_RJT BIT_11 513 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 514 #define FO1_AE_QUEUE_FULL BIT_13 515 516 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 517 #define FO2_REV_LOOPBACK BIT_1 518 519 #define FO3_ENABLE_EMERG_IOCB BIT_0 520 #define FO3_AE_RND_ERROR BIT_1 521 522 /* 24XX additional firmware options */ 523 #define ADD_FO_COUNT 3 524 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 525 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 526 527 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 528 529 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 530 531 /* 532 * ISP mailbox commands 533 */ 534 #define MBC_LOAD_RAM 1 /* Load RAM. */ 535 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 536 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ 537 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 538 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 539 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 540 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 541 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 542 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 543 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 544 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 545 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 546 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 547 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 548 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 549 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 550 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 551 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 552 #define MBC_RESET 0x18 /* Reset. */ 553 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 554 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 555 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 556 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 557 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 558 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 559 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 560 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 561 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 562 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 563 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 564 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 565 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 566 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 567 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 568 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 569 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 570 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 571 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */ 572 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */ 573 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 574 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 575 /* Initialization Procedure */ 576 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 577 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 578 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 579 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 580 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 581 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 582 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 583 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 584 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 585 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 586 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 587 /* commandd. */ 588 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 589 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 590 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 591 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 592 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 593 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 594 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 595 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 596 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 597 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 598 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 599 600 /* 601 * ISP24xx mailbox commands 602 */ 603 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 604 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 605 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 606 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 607 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 608 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 609 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 610 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 611 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 612 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 613 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 614 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 615 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 616 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 617 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 618 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 619 620 /* Firmware return data sizes */ 621 #define FCAL_MAP_SIZE 128 622 623 /* Mailbox bit definitions for out_mb and in_mb */ 624 #define MBX_31 BIT_31 625 #define MBX_30 BIT_30 626 #define MBX_29 BIT_29 627 #define MBX_28 BIT_28 628 #define MBX_27 BIT_27 629 #define MBX_26 BIT_26 630 #define MBX_25 BIT_25 631 #define MBX_24 BIT_24 632 #define MBX_23 BIT_23 633 #define MBX_22 BIT_22 634 #define MBX_21 BIT_21 635 #define MBX_20 BIT_20 636 #define MBX_19 BIT_19 637 #define MBX_18 BIT_18 638 #define MBX_17 BIT_17 639 #define MBX_16 BIT_16 640 #define MBX_15 BIT_15 641 #define MBX_14 BIT_14 642 #define MBX_13 BIT_13 643 #define MBX_12 BIT_12 644 #define MBX_11 BIT_11 645 #define MBX_10 BIT_10 646 #define MBX_9 BIT_9 647 #define MBX_8 BIT_8 648 #define MBX_7 BIT_7 649 #define MBX_6 BIT_6 650 #define MBX_5 BIT_5 651 #define MBX_4 BIT_4 652 #define MBX_3 BIT_3 653 #define MBX_2 BIT_2 654 #define MBX_1 BIT_1 655 #define MBX_0 BIT_0 656 657 /* 658 * Firmware state codes from get firmware state mailbox command 659 */ 660 #define FSTATE_CONFIG_WAIT 0 661 #define FSTATE_WAIT_AL_PA 1 662 #define FSTATE_WAIT_LOGIN 2 663 #define FSTATE_READY 3 664 #define FSTATE_LOSS_OF_SYNC 4 665 #define FSTATE_ERROR 5 666 #define FSTATE_REINIT 6 667 #define FSTATE_NON_PART 7 668 669 #define FSTATE_CONFIG_CORRECT 0 670 #define FSTATE_P2P_RCV_LIP 1 671 #define FSTATE_P2P_CHOOSE_LOOP 2 672 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 673 #define FSTATE_FATAL_ERROR 4 674 #define FSTATE_LOOP_BACK_CONN 5 675 676 /* 677 * Port Database structure definition 678 * Little endian except where noted. 679 */ 680 #define PORT_DATABASE_SIZE 128 /* bytes */ 681 typedef struct { 682 uint8_t options; 683 uint8_t control; 684 uint8_t master_state; 685 uint8_t slave_state; 686 uint8_t reserved[2]; 687 uint8_t hard_address; 688 uint8_t reserved_1; 689 uint8_t port_id[4]; 690 uint8_t node_name[WWN_SIZE]; 691 uint8_t port_name[WWN_SIZE]; 692 uint16_t execution_throttle; 693 uint16_t execution_count; 694 uint8_t reset_count; 695 uint8_t reserved_2; 696 uint16_t resource_allocation; 697 uint16_t current_allocation; 698 uint16_t queue_head; 699 uint16_t queue_tail; 700 uint16_t transmit_execution_list_next; 701 uint16_t transmit_execution_list_previous; 702 uint16_t common_features; 703 uint16_t total_concurrent_sequences; 704 uint16_t RO_by_information_category; 705 uint8_t recipient; 706 uint8_t initiator; 707 uint16_t receive_data_size; 708 uint16_t concurrent_sequences; 709 uint16_t open_sequences_per_exchange; 710 uint16_t lun_abort_flags; 711 uint16_t lun_stop_flags; 712 uint16_t stop_queue_head; 713 uint16_t stop_queue_tail; 714 uint16_t port_retry_timer; 715 uint16_t next_sequence_id; 716 uint16_t frame_count; 717 uint16_t PRLI_payload_length; 718 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 719 /* Bits 15-0 of word 0 */ 720 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 721 /* Bits 15-0 of word 3 */ 722 uint16_t loop_id; 723 uint16_t extended_lun_info_list_pointer; 724 uint16_t extended_lun_stop_list_pointer; 725 } port_database_t; 726 727 /* 728 * Port database slave/master states 729 */ 730 #define PD_STATE_DISCOVERY 0 731 #define PD_STATE_WAIT_DISCOVERY_ACK 1 732 #define PD_STATE_PORT_LOGIN 2 733 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 734 #define PD_STATE_PROCESS_LOGIN 4 735 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 736 #define PD_STATE_PORT_LOGGED_IN 6 737 #define PD_STATE_PORT_UNAVAILABLE 7 738 #define PD_STATE_PROCESS_LOGOUT 8 739 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 740 #define PD_STATE_PORT_LOGOUT 10 741 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 742 743 744 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 745 #define QLA_ZIO_DISABLED 0 746 #define QLA_ZIO_DEFAULT_TIMER 2 747 748 /* 749 * ISP Initialization Control Block. 750 * Little endian except where noted. 751 */ 752 #define ICB_VERSION 1 753 typedef struct { 754 uint8_t version; 755 uint8_t reserved_1; 756 757 /* 758 * LSB BIT 0 = Enable Hard Loop Id 759 * LSB BIT 1 = Enable Fairness 760 * LSB BIT 2 = Enable Full-Duplex 761 * LSB BIT 3 = Enable Fast Posting 762 * LSB BIT 4 = Enable Target Mode 763 * LSB BIT 5 = Disable Initiator Mode 764 * LSB BIT 6 = Enable ADISC 765 * LSB BIT 7 = Enable Target Inquiry Data 766 * 767 * MSB BIT 0 = Enable PDBC Notify 768 * MSB BIT 1 = Non Participating LIP 769 * MSB BIT 2 = Descending Loop ID Search 770 * MSB BIT 3 = Acquire Loop ID in LIPA 771 * MSB BIT 4 = Stop PortQ on Full Status 772 * MSB BIT 5 = Full Login after LIP 773 * MSB BIT 6 = Node Name Option 774 * MSB BIT 7 = Ext IFWCB enable bit 775 */ 776 uint8_t firmware_options[2]; 777 778 uint16_t frame_payload_size; 779 uint16_t max_iocb_allocation; 780 uint16_t execution_throttle; 781 uint8_t retry_count; 782 uint8_t retry_delay; /* unused */ 783 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 784 uint16_t hard_address; 785 uint8_t inquiry_data; 786 uint8_t login_timeout; 787 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 788 789 uint16_t request_q_outpointer; 790 uint16_t response_q_inpointer; 791 uint16_t request_q_length; 792 uint16_t response_q_length; 793 uint32_t request_q_address[2]; 794 uint32_t response_q_address[2]; 795 796 uint16_t lun_enables; 797 uint8_t command_resource_count; 798 uint8_t immediate_notify_resource_count; 799 uint16_t timeout; 800 uint8_t reserved_2[2]; 801 802 /* 803 * LSB BIT 0 = Timer Operation mode bit 0 804 * LSB BIT 1 = Timer Operation mode bit 1 805 * LSB BIT 2 = Timer Operation mode bit 2 806 * LSB BIT 3 = Timer Operation mode bit 3 807 * LSB BIT 4 = Init Config Mode bit 0 808 * LSB BIT 5 = Init Config Mode bit 1 809 * LSB BIT 6 = Init Config Mode bit 2 810 * LSB BIT 7 = Enable Non part on LIHA failure 811 * 812 * MSB BIT 0 = Enable class 2 813 * MSB BIT 1 = Enable ACK0 814 * MSB BIT 2 = 815 * MSB BIT 3 = 816 * MSB BIT 4 = FC Tape Enable 817 * MSB BIT 5 = Enable FC Confirm 818 * MSB BIT 6 = Enable command queuing in target mode 819 * MSB BIT 7 = No Logo On Link Down 820 */ 821 uint8_t add_firmware_options[2]; 822 823 uint8_t response_accumulation_timer; 824 uint8_t interrupt_delay_timer; 825 826 /* 827 * LSB BIT 0 = Enable Read xfr_rdy 828 * LSB BIT 1 = Soft ID only 829 * LSB BIT 2 = 830 * LSB BIT 3 = 831 * LSB BIT 4 = FCP RSP Payload [0] 832 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 833 * LSB BIT 6 = Enable Out-of-Order frame handling 834 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 835 * 836 * MSB BIT 0 = Sbus enable - 2300 837 * MSB BIT 1 = 838 * MSB BIT 2 = 839 * MSB BIT 3 = 840 * MSB BIT 4 = LED mode 841 * MSB BIT 5 = enable 50 ohm termination 842 * MSB BIT 6 = Data Rate (2300 only) 843 * MSB BIT 7 = Data Rate (2300 only) 844 */ 845 uint8_t special_options[2]; 846 847 uint8_t reserved_3[26]; 848 } init_cb_t; 849 850 /* 851 * Get Link Status mailbox command return buffer. 852 */ 853 #define GLSO_SEND_RPS BIT_0 854 #define GLSO_USE_DID BIT_3 855 856 struct link_statistics { 857 uint32_t link_fail_cnt; 858 uint32_t loss_sync_cnt; 859 uint32_t loss_sig_cnt; 860 uint32_t prim_seq_err_cnt; 861 uint32_t inval_xmit_word_cnt; 862 uint32_t inval_crc_cnt; 863 uint32_t lip_cnt; 864 uint32_t unused1[0x1a]; 865 uint32_t tx_frames; 866 uint32_t rx_frames; 867 uint32_t dumped_frames; 868 uint32_t unused2[2]; 869 uint32_t nos_rcvd; 870 }; 871 872 /* 873 * NVRAM Command values. 874 */ 875 #define NV_START_BIT BIT_2 876 #define NV_WRITE_OP (BIT_26+BIT_24) 877 #define NV_READ_OP (BIT_26+BIT_25) 878 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 879 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 880 #define NV_DELAY_COUNT 10 881 882 /* 883 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 884 */ 885 typedef struct { 886 /* 887 * NVRAM header 888 */ 889 uint8_t id[4]; 890 uint8_t nvram_version; 891 uint8_t reserved_0; 892 893 /* 894 * NVRAM RISC parameter block 895 */ 896 uint8_t parameter_block_version; 897 uint8_t reserved_1; 898 899 /* 900 * LSB BIT 0 = Enable Hard Loop Id 901 * LSB BIT 1 = Enable Fairness 902 * LSB BIT 2 = Enable Full-Duplex 903 * LSB BIT 3 = Enable Fast Posting 904 * LSB BIT 4 = Enable Target Mode 905 * LSB BIT 5 = Disable Initiator Mode 906 * LSB BIT 6 = Enable ADISC 907 * LSB BIT 7 = Enable Target Inquiry Data 908 * 909 * MSB BIT 0 = Enable PDBC Notify 910 * MSB BIT 1 = Non Participating LIP 911 * MSB BIT 2 = Descending Loop ID Search 912 * MSB BIT 3 = Acquire Loop ID in LIPA 913 * MSB BIT 4 = Stop PortQ on Full Status 914 * MSB BIT 5 = Full Login after LIP 915 * MSB BIT 6 = Node Name Option 916 * MSB BIT 7 = Ext IFWCB enable bit 917 */ 918 uint8_t firmware_options[2]; 919 920 uint16_t frame_payload_size; 921 uint16_t max_iocb_allocation; 922 uint16_t execution_throttle; 923 uint8_t retry_count; 924 uint8_t retry_delay; /* unused */ 925 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 926 uint16_t hard_address; 927 uint8_t inquiry_data; 928 uint8_t login_timeout; 929 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 930 931 /* 932 * LSB BIT 0 = Timer Operation mode bit 0 933 * LSB BIT 1 = Timer Operation mode bit 1 934 * LSB BIT 2 = Timer Operation mode bit 2 935 * LSB BIT 3 = Timer Operation mode bit 3 936 * LSB BIT 4 = Init Config Mode bit 0 937 * LSB BIT 5 = Init Config Mode bit 1 938 * LSB BIT 6 = Init Config Mode bit 2 939 * LSB BIT 7 = Enable Non part on LIHA failure 940 * 941 * MSB BIT 0 = Enable class 2 942 * MSB BIT 1 = Enable ACK0 943 * MSB BIT 2 = 944 * MSB BIT 3 = 945 * MSB BIT 4 = FC Tape Enable 946 * MSB BIT 5 = Enable FC Confirm 947 * MSB BIT 6 = Enable command queuing in target mode 948 * MSB BIT 7 = No Logo On Link Down 949 */ 950 uint8_t add_firmware_options[2]; 951 952 uint8_t response_accumulation_timer; 953 uint8_t interrupt_delay_timer; 954 955 /* 956 * LSB BIT 0 = Enable Read xfr_rdy 957 * LSB BIT 1 = Soft ID only 958 * LSB BIT 2 = 959 * LSB BIT 3 = 960 * LSB BIT 4 = FCP RSP Payload [0] 961 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 962 * LSB BIT 6 = Enable Out-of-Order frame handling 963 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 964 * 965 * MSB BIT 0 = Sbus enable - 2300 966 * MSB BIT 1 = 967 * MSB BIT 2 = 968 * MSB BIT 3 = 969 * MSB BIT 4 = LED mode 970 * MSB BIT 5 = enable 50 ohm termination 971 * MSB BIT 6 = Data Rate (2300 only) 972 * MSB BIT 7 = Data Rate (2300 only) 973 */ 974 uint8_t special_options[2]; 975 976 /* Reserved for expanded RISC parameter block */ 977 uint8_t reserved_2[22]; 978 979 /* 980 * LSB BIT 0 = Tx Sensitivity 1G bit 0 981 * LSB BIT 1 = Tx Sensitivity 1G bit 1 982 * LSB BIT 2 = Tx Sensitivity 1G bit 2 983 * LSB BIT 3 = Tx Sensitivity 1G bit 3 984 * LSB BIT 4 = Rx Sensitivity 1G bit 0 985 * LSB BIT 5 = Rx Sensitivity 1G bit 1 986 * LSB BIT 6 = Rx Sensitivity 1G bit 2 987 * LSB BIT 7 = Rx Sensitivity 1G bit 3 988 * 989 * MSB BIT 0 = Tx Sensitivity 2G bit 0 990 * MSB BIT 1 = Tx Sensitivity 2G bit 1 991 * MSB BIT 2 = Tx Sensitivity 2G bit 2 992 * MSB BIT 3 = Tx Sensitivity 2G bit 3 993 * MSB BIT 4 = Rx Sensitivity 2G bit 0 994 * MSB BIT 5 = Rx Sensitivity 2G bit 1 995 * MSB BIT 6 = Rx Sensitivity 2G bit 2 996 * MSB BIT 7 = Rx Sensitivity 2G bit 3 997 * 998 * LSB BIT 0 = Output Swing 1G bit 0 999 * LSB BIT 1 = Output Swing 1G bit 1 1000 * LSB BIT 2 = Output Swing 1G bit 2 1001 * LSB BIT 3 = Output Emphasis 1G bit 0 1002 * LSB BIT 4 = Output Emphasis 1G bit 1 1003 * LSB BIT 5 = Output Swing 2G bit 0 1004 * LSB BIT 6 = Output Swing 2G bit 1 1005 * LSB BIT 7 = Output Swing 2G bit 2 1006 * 1007 * MSB BIT 0 = Output Emphasis 2G bit 0 1008 * MSB BIT 1 = Output Emphasis 2G bit 1 1009 * MSB BIT 2 = Output Enable 1010 * MSB BIT 3 = 1011 * MSB BIT 4 = 1012 * MSB BIT 5 = 1013 * MSB BIT 6 = 1014 * MSB BIT 7 = 1015 */ 1016 uint8_t seriallink_options[4]; 1017 1018 /* 1019 * NVRAM host parameter block 1020 * 1021 * LSB BIT 0 = Enable spinup delay 1022 * LSB BIT 1 = Disable BIOS 1023 * LSB BIT 2 = Enable Memory Map BIOS 1024 * LSB BIT 3 = Enable Selectable Boot 1025 * LSB BIT 4 = Disable RISC code load 1026 * LSB BIT 5 = Set cache line size 1 1027 * LSB BIT 6 = PCI Parity Disable 1028 * LSB BIT 7 = Enable extended logging 1029 * 1030 * MSB BIT 0 = Enable 64bit addressing 1031 * MSB BIT 1 = Enable lip reset 1032 * MSB BIT 2 = Enable lip full login 1033 * MSB BIT 3 = Enable target reset 1034 * MSB BIT 4 = Enable database storage 1035 * MSB BIT 5 = Enable cache flush read 1036 * MSB BIT 6 = Enable database load 1037 * MSB BIT 7 = Enable alternate WWN 1038 */ 1039 uint8_t host_p[2]; 1040 1041 uint8_t boot_node_name[WWN_SIZE]; 1042 uint8_t boot_lun_number; 1043 uint8_t reset_delay; 1044 uint8_t port_down_retry_count; 1045 uint8_t boot_id_number; 1046 uint16_t max_luns_per_target; 1047 uint8_t fcode_boot_port_name[WWN_SIZE]; 1048 uint8_t alternate_port_name[WWN_SIZE]; 1049 uint8_t alternate_node_name[WWN_SIZE]; 1050 1051 /* 1052 * BIT 0 = Selective Login 1053 * BIT 1 = Alt-Boot Enable 1054 * BIT 2 = 1055 * BIT 3 = Boot Order List 1056 * BIT 4 = 1057 * BIT 5 = Selective LUN 1058 * BIT 6 = 1059 * BIT 7 = unused 1060 */ 1061 uint8_t efi_parameters; 1062 1063 uint8_t link_down_timeout; 1064 1065 uint8_t adapter_id[16]; 1066 1067 uint8_t alt1_boot_node_name[WWN_SIZE]; 1068 uint16_t alt1_boot_lun_number; 1069 uint8_t alt2_boot_node_name[WWN_SIZE]; 1070 uint16_t alt2_boot_lun_number; 1071 uint8_t alt3_boot_node_name[WWN_SIZE]; 1072 uint16_t alt3_boot_lun_number; 1073 uint8_t alt4_boot_node_name[WWN_SIZE]; 1074 uint16_t alt4_boot_lun_number; 1075 uint8_t alt5_boot_node_name[WWN_SIZE]; 1076 uint16_t alt5_boot_lun_number; 1077 uint8_t alt6_boot_node_name[WWN_SIZE]; 1078 uint16_t alt6_boot_lun_number; 1079 uint8_t alt7_boot_node_name[WWN_SIZE]; 1080 uint16_t alt7_boot_lun_number; 1081 1082 uint8_t reserved_3[2]; 1083 1084 /* Offset 200-215 : Model Number */ 1085 uint8_t model_number[16]; 1086 1087 /* OEM related items */ 1088 uint8_t oem_specific[16]; 1089 1090 /* 1091 * NVRAM Adapter Features offset 232-239 1092 * 1093 * LSB BIT 0 = External GBIC 1094 * LSB BIT 1 = Risc RAM parity 1095 * LSB BIT 2 = Buffer Plus Module 1096 * LSB BIT 3 = Multi Chip Adapter 1097 * LSB BIT 4 = Internal connector 1098 * LSB BIT 5 = 1099 * LSB BIT 6 = 1100 * LSB BIT 7 = 1101 * 1102 * MSB BIT 0 = 1103 * MSB BIT 1 = 1104 * MSB BIT 2 = 1105 * MSB BIT 3 = 1106 * MSB BIT 4 = 1107 * MSB BIT 5 = 1108 * MSB BIT 6 = 1109 * MSB BIT 7 = 1110 */ 1111 uint8_t adapter_features[2]; 1112 1113 uint8_t reserved_4[16]; 1114 1115 /* Subsystem vendor ID for ISP2200 */ 1116 uint16_t subsystem_vendor_id_2200; 1117 1118 /* Subsystem device ID for ISP2200 */ 1119 uint16_t subsystem_device_id_2200; 1120 1121 uint8_t reserved_5; 1122 uint8_t checksum; 1123 } nvram_t; 1124 1125 /* 1126 * ISP queue - response queue entry definition. 1127 */ 1128 typedef struct { 1129 uint8_t data[60]; 1130 uint32_t signature; 1131 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1132 } response_t; 1133 1134 typedef union { 1135 uint16_t extended; 1136 struct { 1137 uint8_t reserved; 1138 uint8_t standard; 1139 } id; 1140 } target_id_t; 1141 1142 #define SET_TARGET_ID(ha, to, from) \ 1143 do { \ 1144 if (HAS_EXTENDED_IDS(ha)) \ 1145 to.extended = cpu_to_le16(from); \ 1146 else \ 1147 to.id.standard = (uint8_t)from; \ 1148 } while (0) 1149 1150 /* 1151 * ISP queue - command entry structure definition. 1152 */ 1153 #define COMMAND_TYPE 0x11 /* Command entry */ 1154 typedef struct { 1155 uint8_t entry_type; /* Entry type. */ 1156 uint8_t entry_count; /* Entry count. */ 1157 uint8_t sys_define; /* System defined. */ 1158 uint8_t entry_status; /* Entry Status. */ 1159 uint32_t handle; /* System handle. */ 1160 target_id_t target; /* SCSI ID */ 1161 uint16_t lun; /* SCSI LUN */ 1162 uint16_t control_flags; /* Control flags. */ 1163 #define CF_WRITE BIT_6 1164 #define CF_READ BIT_5 1165 #define CF_SIMPLE_TAG BIT_3 1166 #define CF_ORDERED_TAG BIT_2 1167 #define CF_HEAD_TAG BIT_1 1168 uint16_t reserved_1; 1169 uint16_t timeout; /* Command timeout. */ 1170 uint16_t dseg_count; /* Data segment count. */ 1171 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1172 uint32_t byte_count; /* Total byte count. */ 1173 uint32_t dseg_0_address; /* Data segment 0 address. */ 1174 uint32_t dseg_0_length; /* Data segment 0 length. */ 1175 uint32_t dseg_1_address; /* Data segment 1 address. */ 1176 uint32_t dseg_1_length; /* Data segment 1 length. */ 1177 uint32_t dseg_2_address; /* Data segment 2 address. */ 1178 uint32_t dseg_2_length; /* Data segment 2 length. */ 1179 } cmd_entry_t; 1180 1181 /* 1182 * ISP queue - 64-Bit addressing, command entry structure definition. 1183 */ 1184 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1185 typedef struct { 1186 uint8_t entry_type; /* Entry type. */ 1187 uint8_t entry_count; /* Entry count. */ 1188 uint8_t sys_define; /* System defined. */ 1189 uint8_t entry_status; /* Entry Status. */ 1190 uint32_t handle; /* System handle. */ 1191 target_id_t target; /* SCSI ID */ 1192 uint16_t lun; /* SCSI LUN */ 1193 uint16_t control_flags; /* Control flags. */ 1194 uint16_t reserved_1; 1195 uint16_t timeout; /* Command timeout. */ 1196 uint16_t dseg_count; /* Data segment count. */ 1197 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1198 uint32_t byte_count; /* Total byte count. */ 1199 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1200 uint32_t dseg_0_length; /* Data segment 0 length. */ 1201 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1202 uint32_t dseg_1_length; /* Data segment 1 length. */ 1203 } cmd_a64_entry_t, request_t; 1204 1205 /* 1206 * ISP queue - continuation entry structure definition. 1207 */ 1208 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1209 typedef struct { 1210 uint8_t entry_type; /* Entry type. */ 1211 uint8_t entry_count; /* Entry count. */ 1212 uint8_t sys_define; /* System defined. */ 1213 uint8_t entry_status; /* Entry Status. */ 1214 uint32_t reserved; 1215 uint32_t dseg_0_address; /* Data segment 0 address. */ 1216 uint32_t dseg_0_length; /* Data segment 0 length. */ 1217 uint32_t dseg_1_address; /* Data segment 1 address. */ 1218 uint32_t dseg_1_length; /* Data segment 1 length. */ 1219 uint32_t dseg_2_address; /* Data segment 2 address. */ 1220 uint32_t dseg_2_length; /* Data segment 2 length. */ 1221 uint32_t dseg_3_address; /* Data segment 3 address. */ 1222 uint32_t dseg_3_length; /* Data segment 3 length. */ 1223 uint32_t dseg_4_address; /* Data segment 4 address. */ 1224 uint32_t dseg_4_length; /* Data segment 4 length. */ 1225 uint32_t dseg_5_address; /* Data segment 5 address. */ 1226 uint32_t dseg_5_length; /* Data segment 5 length. */ 1227 uint32_t dseg_6_address; /* Data segment 6 address. */ 1228 uint32_t dseg_6_length; /* Data segment 6 length. */ 1229 } cont_entry_t; 1230 1231 /* 1232 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1233 */ 1234 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1235 typedef struct { 1236 uint8_t entry_type; /* Entry type. */ 1237 uint8_t entry_count; /* Entry count. */ 1238 uint8_t sys_define; /* System defined. */ 1239 uint8_t entry_status; /* Entry Status. */ 1240 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1241 uint32_t dseg_0_length; /* Data segment 0 length. */ 1242 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1243 uint32_t dseg_1_length; /* Data segment 1 length. */ 1244 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1245 uint32_t dseg_2_length; /* Data segment 2 length. */ 1246 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1247 uint32_t dseg_3_length; /* Data segment 3 length. */ 1248 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1249 uint32_t dseg_4_length; /* Data segment 4 length. */ 1250 } cont_a64_entry_t; 1251 1252 /* 1253 * ISP queue - status entry structure definition. 1254 */ 1255 #define STATUS_TYPE 0x03 /* Status entry. */ 1256 typedef struct { 1257 uint8_t entry_type; /* Entry type. */ 1258 uint8_t entry_count; /* Entry count. */ 1259 uint8_t sys_define; /* System defined. */ 1260 uint8_t entry_status; /* Entry Status. */ 1261 uint32_t handle; /* System handle. */ 1262 uint16_t scsi_status; /* SCSI status. */ 1263 uint16_t comp_status; /* Completion status. */ 1264 uint16_t state_flags; /* State flags. */ 1265 uint16_t status_flags; /* Status flags. */ 1266 uint16_t rsp_info_len; /* Response Info Length. */ 1267 uint16_t req_sense_length; /* Request sense data length. */ 1268 uint32_t residual_length; /* Residual transfer length. */ 1269 uint8_t rsp_info[8]; /* FCP response information. */ 1270 uint8_t req_sense_data[32]; /* Request sense data. */ 1271 } sts_entry_t; 1272 1273 /* 1274 * Status entry entry status 1275 */ 1276 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1277 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1278 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1279 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1280 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1281 #define RF_BUSY BIT_1 /* Busy */ 1282 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1283 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1284 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1285 RF_INV_E_TYPE) 1286 1287 /* 1288 * Status entry SCSI status bit definitions. 1289 */ 1290 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1291 #define SS_RESIDUAL_UNDER BIT_11 1292 #define SS_RESIDUAL_OVER BIT_10 1293 #define SS_SENSE_LEN_VALID BIT_9 1294 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1295 1296 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1297 #define SS_BUSY_CONDITION BIT_3 1298 #define SS_CONDITION_MET BIT_2 1299 #define SS_CHECK_CONDITION BIT_1 1300 1301 /* 1302 * Status entry completion status 1303 */ 1304 #define CS_COMPLETE 0x0 /* No errors */ 1305 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1306 #define CS_DMA 0x2 /* A DMA direction error. */ 1307 #define CS_TRANSPORT 0x3 /* Transport error. */ 1308 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1309 #define CS_ABORTED 0x5 /* System aborted command. */ 1310 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1311 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1312 1313 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1314 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1315 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1316 /* (selection timeout) */ 1317 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1318 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1319 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1320 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1321 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1322 #define CS_UNKNOWN 0x81 /* Driver defined */ 1323 #define CS_RETRY 0x82 /* Driver defined */ 1324 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1325 1326 /* 1327 * Status entry status flags 1328 */ 1329 #define SF_ABTS_TERMINATED BIT_10 1330 #define SF_LOGOUT_SENT BIT_13 1331 1332 /* 1333 * ISP queue - status continuation entry structure definition. 1334 */ 1335 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1336 typedef struct { 1337 uint8_t entry_type; /* Entry type. */ 1338 uint8_t entry_count; /* Entry count. */ 1339 uint8_t sys_define; /* System defined. */ 1340 uint8_t entry_status; /* Entry Status. */ 1341 uint8_t data[60]; /* data */ 1342 } sts_cont_entry_t; 1343 1344 /* 1345 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1346 * structure definition. 1347 */ 1348 #define STATUS_TYPE_21 0x21 /* Status entry. */ 1349 typedef struct { 1350 uint8_t entry_type; /* Entry type. */ 1351 uint8_t entry_count; /* Entry count. */ 1352 uint8_t handle_count; /* Handle count. */ 1353 uint8_t entry_status; /* Entry Status. */ 1354 uint32_t handle[15]; /* System handles. */ 1355 } sts21_entry_t; 1356 1357 /* 1358 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1359 * structure definition. 1360 */ 1361 #define STATUS_TYPE_22 0x22 /* Status entry. */ 1362 typedef struct { 1363 uint8_t entry_type; /* Entry type. */ 1364 uint8_t entry_count; /* Entry count. */ 1365 uint8_t handle_count; /* Handle count. */ 1366 uint8_t entry_status; /* Entry Status. */ 1367 uint16_t handle[30]; /* System handles. */ 1368 } sts22_entry_t; 1369 1370 /* 1371 * ISP queue - marker entry structure definition. 1372 */ 1373 #define MARKER_TYPE 0x04 /* Marker entry. */ 1374 typedef struct { 1375 uint8_t entry_type; /* Entry type. */ 1376 uint8_t entry_count; /* Entry count. */ 1377 uint8_t handle_count; /* Handle count. */ 1378 uint8_t entry_status; /* Entry Status. */ 1379 uint32_t sys_define_2; /* System defined. */ 1380 target_id_t target; /* SCSI ID */ 1381 uint8_t modifier; /* Modifier (7-0). */ 1382 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1383 #define MK_SYNC_ID 1 /* Synchronize ID */ 1384 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1385 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 1386 /* clear port changed, */ 1387 /* use sequence number. */ 1388 uint8_t reserved_1; 1389 uint16_t sequence_number; /* Sequence number of event */ 1390 uint16_t lun; /* SCSI LUN */ 1391 uint8_t reserved_2[48]; 1392 } mrk_entry_t; 1393 1394 /* 1395 * ISP queue - Management Server entry structure definition. 1396 */ 1397 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 1398 typedef struct { 1399 uint8_t entry_type; /* Entry type. */ 1400 uint8_t entry_count; /* Entry count. */ 1401 uint8_t handle_count; /* Handle count. */ 1402 uint8_t entry_status; /* Entry Status. */ 1403 uint32_t handle1; /* System handle. */ 1404 target_id_t loop_id; 1405 uint16_t status; 1406 uint16_t control_flags; /* Control flags. */ 1407 uint16_t reserved2; 1408 uint16_t timeout; 1409 uint16_t cmd_dsd_count; 1410 uint16_t total_dsd_count; 1411 uint8_t type; 1412 uint8_t r_ctl; 1413 uint16_t rx_id; 1414 uint16_t reserved3; 1415 uint32_t handle2; 1416 uint32_t rsp_bytecount; 1417 uint32_t req_bytecount; 1418 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 1419 uint32_t dseg_req_length; /* Data segment 0 length. */ 1420 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 1421 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 1422 } ms_iocb_entry_t; 1423 1424 1425 /* 1426 * ISP queue - Mailbox Command entry structure definition. 1427 */ 1428 #define MBX_IOCB_TYPE 0x39 1429 struct mbx_entry { 1430 uint8_t entry_type; 1431 uint8_t entry_count; 1432 uint8_t sys_define1; 1433 /* Use sys_define1 for source type */ 1434 #define SOURCE_SCSI 0x00 1435 #define SOURCE_IP 0x01 1436 #define SOURCE_VI 0x02 1437 #define SOURCE_SCTP 0x03 1438 #define SOURCE_MP 0x04 1439 #define SOURCE_MPIOCTL 0x05 1440 #define SOURCE_ASYNC_IOCB 0x07 1441 1442 uint8_t entry_status; 1443 1444 uint32_t handle; 1445 target_id_t loop_id; 1446 1447 uint16_t status; 1448 uint16_t state_flags; 1449 uint16_t status_flags; 1450 1451 uint32_t sys_define2[2]; 1452 1453 uint16_t mb0; 1454 uint16_t mb1; 1455 uint16_t mb2; 1456 uint16_t mb3; 1457 uint16_t mb6; 1458 uint16_t mb7; 1459 uint16_t mb9; 1460 uint16_t mb10; 1461 uint32_t reserved_2[2]; 1462 uint8_t node_name[WWN_SIZE]; 1463 uint8_t port_name[WWN_SIZE]; 1464 }; 1465 1466 /* 1467 * ISP request and response queue entry sizes 1468 */ 1469 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 1470 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 1471 1472 1473 /* 1474 * 24 bit port ID type definition. 1475 */ 1476 typedef union { 1477 uint32_t b24 : 24; 1478 1479 struct { 1480 #ifdef __BIG_ENDIAN 1481 uint8_t domain; 1482 uint8_t area; 1483 uint8_t al_pa; 1484 #elif __LITTLE_ENDIAN 1485 uint8_t al_pa; 1486 uint8_t area; 1487 uint8_t domain; 1488 #else 1489 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 1490 #endif 1491 uint8_t rsvd_1; 1492 } b; 1493 } port_id_t; 1494 #define INVALID_PORT_ID 0xFFFFFF 1495 1496 /* 1497 * Switch info gathering structure. 1498 */ 1499 typedef struct { 1500 port_id_t d_id; 1501 uint8_t node_name[WWN_SIZE]; 1502 uint8_t port_name[WWN_SIZE]; 1503 uint8_t fabric_port_name[WWN_SIZE]; 1504 uint16_t fp_speed; 1505 } sw_info_t; 1506 1507 /* 1508 * Fibre channel port type. 1509 */ 1510 typedef enum { 1511 FCT_UNKNOWN, 1512 FCT_RSCN, 1513 FCT_SWITCH, 1514 FCT_BROADCAST, 1515 FCT_INITIATOR, 1516 FCT_TARGET 1517 } fc_port_type_t; 1518 1519 /* 1520 * Fibre channel port structure. 1521 */ 1522 typedef struct fc_port { 1523 struct list_head list; 1524 struct scsi_qla_host *vha; 1525 1526 uint8_t node_name[WWN_SIZE]; 1527 uint8_t port_name[WWN_SIZE]; 1528 port_id_t d_id; 1529 uint16_t loop_id; 1530 uint16_t old_loop_id; 1531 1532 uint8_t fabric_port_name[WWN_SIZE]; 1533 uint16_t fp_speed; 1534 1535 fc_port_type_t port_type; 1536 1537 atomic_t state; 1538 uint32_t flags; 1539 1540 int port_login_retry_count; 1541 int login_retry; 1542 atomic_t port_down_timer; 1543 1544 struct fc_rport *rport, *drport; 1545 u32 supported_classes; 1546 1547 unsigned long last_queue_full; 1548 unsigned long last_ramp_up; 1549 1550 uint16_t vp_idx; 1551 } fc_port_t; 1552 1553 /* 1554 * Fibre channel port/lun states. 1555 */ 1556 #define FCS_UNCONFIGURED 1 1557 #define FCS_DEVICE_DEAD 2 1558 #define FCS_DEVICE_LOST 3 1559 #define FCS_ONLINE 4 1560 1561 /* 1562 * FC port flags. 1563 */ 1564 #define FCF_FABRIC_DEVICE BIT_0 1565 #define FCF_LOGIN_NEEDED BIT_1 1566 #define FCF_TAPE_PRESENT BIT_2 1567 1568 /* No loop ID flag. */ 1569 #define FC_NO_LOOP_ID 0x1000 1570 1571 /* 1572 * FC-CT interface 1573 * 1574 * NOTE: All structures are big-endian in form. 1575 */ 1576 1577 #define CT_REJECT_RESPONSE 0x8001 1578 #define CT_ACCEPT_RESPONSE 0x8002 1579 #define CT_REASON_INVALID_COMMAND_CODE 0x01 1580 #define CT_REASON_CANNOT_PERFORM 0x09 1581 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 1582 #define CT_EXPL_ALREADY_REGISTERED 0x10 1583 1584 #define NS_N_PORT_TYPE 0x01 1585 #define NS_NL_PORT_TYPE 0x02 1586 #define NS_NX_PORT_TYPE 0x7F 1587 1588 #define GA_NXT_CMD 0x100 1589 #define GA_NXT_REQ_SIZE (16 + 4) 1590 #define GA_NXT_RSP_SIZE (16 + 620) 1591 1592 #define GID_PT_CMD 0x1A1 1593 #define GID_PT_REQ_SIZE (16 + 4) 1594 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4)) 1595 1596 #define GPN_ID_CMD 0x112 1597 #define GPN_ID_REQ_SIZE (16 + 4) 1598 #define GPN_ID_RSP_SIZE (16 + 8) 1599 1600 #define GNN_ID_CMD 0x113 1601 #define GNN_ID_REQ_SIZE (16 + 4) 1602 #define GNN_ID_RSP_SIZE (16 + 8) 1603 1604 #define GFT_ID_CMD 0x117 1605 #define GFT_ID_REQ_SIZE (16 + 4) 1606 #define GFT_ID_RSP_SIZE (16 + 32) 1607 1608 #define RFT_ID_CMD 0x217 1609 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 1610 #define RFT_ID_RSP_SIZE 16 1611 1612 #define RFF_ID_CMD 0x21F 1613 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 1614 #define RFF_ID_RSP_SIZE 16 1615 1616 #define RNN_ID_CMD 0x213 1617 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 1618 #define RNN_ID_RSP_SIZE 16 1619 1620 #define RSNN_NN_CMD 0x239 1621 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 1622 #define RSNN_NN_RSP_SIZE 16 1623 1624 #define GFPN_ID_CMD 0x11C 1625 #define GFPN_ID_REQ_SIZE (16 + 4) 1626 #define GFPN_ID_RSP_SIZE (16 + 8) 1627 1628 #define GPSC_CMD 0x127 1629 #define GPSC_REQ_SIZE (16 + 8) 1630 #define GPSC_RSP_SIZE (16 + 2 + 2) 1631 1632 1633 /* 1634 * HBA attribute types. 1635 */ 1636 #define FDMI_HBA_ATTR_COUNT 9 1637 #define FDMI_HBA_NODE_NAME 1 1638 #define FDMI_HBA_MANUFACTURER 2 1639 #define FDMI_HBA_SERIAL_NUMBER 3 1640 #define FDMI_HBA_MODEL 4 1641 #define FDMI_HBA_MODEL_DESCRIPTION 5 1642 #define FDMI_HBA_HARDWARE_VERSION 6 1643 #define FDMI_HBA_DRIVER_VERSION 7 1644 #define FDMI_HBA_OPTION_ROM_VERSION 8 1645 #define FDMI_HBA_FIRMWARE_VERSION 9 1646 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 1647 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 1648 1649 struct ct_fdmi_hba_attr { 1650 uint16_t type; 1651 uint16_t len; 1652 union { 1653 uint8_t node_name[WWN_SIZE]; 1654 uint8_t manufacturer[32]; 1655 uint8_t serial_num[8]; 1656 uint8_t model[16]; 1657 uint8_t model_desc[80]; 1658 uint8_t hw_version[16]; 1659 uint8_t driver_version[32]; 1660 uint8_t orom_version[16]; 1661 uint8_t fw_version[16]; 1662 uint8_t os_version[128]; 1663 uint8_t max_ct_len[4]; 1664 } a; 1665 }; 1666 1667 struct ct_fdmi_hba_attributes { 1668 uint32_t count; 1669 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 1670 }; 1671 1672 /* 1673 * Port attribute types. 1674 */ 1675 #define FDMI_PORT_ATTR_COUNT 6 1676 #define FDMI_PORT_FC4_TYPES 1 1677 #define FDMI_PORT_SUPPORT_SPEED 2 1678 #define FDMI_PORT_CURRENT_SPEED 3 1679 #define FDMI_PORT_MAX_FRAME_SIZE 4 1680 #define FDMI_PORT_OS_DEVICE_NAME 5 1681 #define FDMI_PORT_HOST_NAME 6 1682 1683 #define FDMI_PORT_SPEED_1GB 0x1 1684 #define FDMI_PORT_SPEED_2GB 0x2 1685 #define FDMI_PORT_SPEED_10GB 0x4 1686 #define FDMI_PORT_SPEED_4GB 0x8 1687 #define FDMI_PORT_SPEED_8GB 0x10 1688 #define FDMI_PORT_SPEED_16GB 0x20 1689 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 1690 1691 struct ct_fdmi_port_attr { 1692 uint16_t type; 1693 uint16_t len; 1694 union { 1695 uint8_t fc4_types[32]; 1696 uint32_t sup_speed; 1697 uint32_t cur_speed; 1698 uint32_t max_frame_size; 1699 uint8_t os_dev_name[32]; 1700 uint8_t host_name[32]; 1701 } a; 1702 }; 1703 1704 /* 1705 * Port Attribute Block. 1706 */ 1707 struct ct_fdmi_port_attributes { 1708 uint32_t count; 1709 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 1710 }; 1711 1712 /* FDMI definitions. */ 1713 #define GRHL_CMD 0x100 1714 #define GHAT_CMD 0x101 1715 #define GRPL_CMD 0x102 1716 #define GPAT_CMD 0x110 1717 1718 #define RHBA_CMD 0x200 1719 #define RHBA_RSP_SIZE 16 1720 1721 #define RHAT_CMD 0x201 1722 #define RPRT_CMD 0x210 1723 1724 #define RPA_CMD 0x211 1725 #define RPA_RSP_SIZE 16 1726 1727 #define DHBA_CMD 0x300 1728 #define DHBA_REQ_SIZE (16 + 8) 1729 #define DHBA_RSP_SIZE 16 1730 1731 #define DHAT_CMD 0x301 1732 #define DPRT_CMD 0x310 1733 #define DPA_CMD 0x311 1734 1735 /* CT command header -- request/response common fields */ 1736 struct ct_cmd_hdr { 1737 uint8_t revision; 1738 uint8_t in_id[3]; 1739 uint8_t gs_type; 1740 uint8_t gs_subtype; 1741 uint8_t options; 1742 uint8_t reserved; 1743 }; 1744 1745 /* CT command request */ 1746 struct ct_sns_req { 1747 struct ct_cmd_hdr header; 1748 uint16_t command; 1749 uint16_t max_rsp_size; 1750 uint8_t fragment_id; 1751 uint8_t reserved[3]; 1752 1753 union { 1754 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 1755 struct { 1756 uint8_t reserved; 1757 uint8_t port_id[3]; 1758 } port_id; 1759 1760 struct { 1761 uint8_t port_type; 1762 uint8_t domain; 1763 uint8_t area; 1764 uint8_t reserved; 1765 } gid_pt; 1766 1767 struct { 1768 uint8_t reserved; 1769 uint8_t port_id[3]; 1770 uint8_t fc4_types[32]; 1771 } rft_id; 1772 1773 struct { 1774 uint8_t reserved; 1775 uint8_t port_id[3]; 1776 uint16_t reserved2; 1777 uint8_t fc4_feature; 1778 uint8_t fc4_type; 1779 } rff_id; 1780 1781 struct { 1782 uint8_t reserved; 1783 uint8_t port_id[3]; 1784 uint8_t node_name[8]; 1785 } rnn_id; 1786 1787 struct { 1788 uint8_t node_name[8]; 1789 uint8_t name_len; 1790 uint8_t sym_node_name[255]; 1791 } rsnn_nn; 1792 1793 struct { 1794 uint8_t hba_indentifier[8]; 1795 } ghat; 1796 1797 struct { 1798 uint8_t hba_identifier[8]; 1799 uint32_t entry_count; 1800 uint8_t port_name[8]; 1801 struct ct_fdmi_hba_attributes attrs; 1802 } rhba; 1803 1804 struct { 1805 uint8_t hba_identifier[8]; 1806 struct ct_fdmi_hba_attributes attrs; 1807 } rhat; 1808 1809 struct { 1810 uint8_t port_name[8]; 1811 struct ct_fdmi_port_attributes attrs; 1812 } rpa; 1813 1814 struct { 1815 uint8_t port_name[8]; 1816 } dhba; 1817 1818 struct { 1819 uint8_t port_name[8]; 1820 } dhat; 1821 1822 struct { 1823 uint8_t port_name[8]; 1824 } dprt; 1825 1826 struct { 1827 uint8_t port_name[8]; 1828 } dpa; 1829 1830 struct { 1831 uint8_t port_name[8]; 1832 } gpsc; 1833 } req; 1834 }; 1835 1836 /* CT command response header */ 1837 struct ct_rsp_hdr { 1838 struct ct_cmd_hdr header; 1839 uint16_t response; 1840 uint16_t residual; 1841 uint8_t fragment_id; 1842 uint8_t reason_code; 1843 uint8_t explanation_code; 1844 uint8_t vendor_unique; 1845 }; 1846 1847 struct ct_sns_gid_pt_data { 1848 uint8_t control_byte; 1849 uint8_t port_id[3]; 1850 }; 1851 1852 struct ct_sns_rsp { 1853 struct ct_rsp_hdr header; 1854 1855 union { 1856 struct { 1857 uint8_t port_type; 1858 uint8_t port_id[3]; 1859 uint8_t port_name[8]; 1860 uint8_t sym_port_name_len; 1861 uint8_t sym_port_name[255]; 1862 uint8_t node_name[8]; 1863 uint8_t sym_node_name_len; 1864 uint8_t sym_node_name[255]; 1865 uint8_t init_proc_assoc[8]; 1866 uint8_t node_ip_addr[16]; 1867 uint8_t class_of_service[4]; 1868 uint8_t fc4_types[32]; 1869 uint8_t ip_address[16]; 1870 uint8_t fabric_port_name[8]; 1871 uint8_t reserved; 1872 uint8_t hard_address[3]; 1873 } ga_nxt; 1874 1875 struct { 1876 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES]; 1877 } gid_pt; 1878 1879 struct { 1880 uint8_t port_name[8]; 1881 } gpn_id; 1882 1883 struct { 1884 uint8_t node_name[8]; 1885 } gnn_id; 1886 1887 struct { 1888 uint8_t fc4_types[32]; 1889 } gft_id; 1890 1891 struct { 1892 uint32_t entry_count; 1893 uint8_t port_name[8]; 1894 struct ct_fdmi_hba_attributes attrs; 1895 } ghat; 1896 1897 struct { 1898 uint8_t port_name[8]; 1899 } gfpn_id; 1900 1901 struct { 1902 uint16_t speeds; 1903 uint16_t speed; 1904 } gpsc; 1905 } rsp; 1906 }; 1907 1908 struct ct_sns_pkt { 1909 union { 1910 struct ct_sns_req req; 1911 struct ct_sns_rsp rsp; 1912 } p; 1913 }; 1914 1915 /* 1916 * SNS command structures -- for 2200 compatability. 1917 */ 1918 #define RFT_ID_SNS_SCMD_LEN 22 1919 #define RFT_ID_SNS_CMD_SIZE 60 1920 #define RFT_ID_SNS_DATA_SIZE 16 1921 1922 #define RNN_ID_SNS_SCMD_LEN 10 1923 #define RNN_ID_SNS_CMD_SIZE 36 1924 #define RNN_ID_SNS_DATA_SIZE 16 1925 1926 #define GA_NXT_SNS_SCMD_LEN 6 1927 #define GA_NXT_SNS_CMD_SIZE 28 1928 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 1929 1930 #define GID_PT_SNS_SCMD_LEN 6 1931 #define GID_PT_SNS_CMD_SIZE 28 1932 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16) 1933 1934 #define GPN_ID_SNS_SCMD_LEN 6 1935 #define GPN_ID_SNS_CMD_SIZE 28 1936 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 1937 1938 #define GNN_ID_SNS_SCMD_LEN 6 1939 #define GNN_ID_SNS_CMD_SIZE 28 1940 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 1941 1942 struct sns_cmd_pkt { 1943 union { 1944 struct { 1945 uint16_t buffer_length; 1946 uint16_t reserved_1; 1947 uint32_t buffer_address[2]; 1948 uint16_t subcommand_length; 1949 uint16_t reserved_2; 1950 uint16_t subcommand; 1951 uint16_t size; 1952 uint32_t reserved_3; 1953 uint8_t param[36]; 1954 } cmd; 1955 1956 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 1957 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 1958 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 1959 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 1960 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 1961 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 1962 } p; 1963 }; 1964 1965 struct fw_blob { 1966 char *name; 1967 uint32_t segs[4]; 1968 const struct firmware *fw; 1969 }; 1970 1971 /* Return data from MBC_GET_ID_LIST call. */ 1972 struct gid_list_info { 1973 uint8_t al_pa; 1974 uint8_t area; 1975 uint8_t domain; 1976 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 1977 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 1978 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 1979 }; 1980 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES) 1981 1982 /* NPIV */ 1983 typedef struct vport_info { 1984 uint8_t port_name[WWN_SIZE]; 1985 uint8_t node_name[WWN_SIZE]; 1986 int vp_id; 1987 uint16_t loop_id; 1988 unsigned long host_no; 1989 uint8_t port_id[3]; 1990 int loop_state; 1991 } vport_info_t; 1992 1993 typedef struct vport_params { 1994 uint8_t port_name[WWN_SIZE]; 1995 uint8_t node_name[WWN_SIZE]; 1996 uint32_t options; 1997 #define VP_OPTS_RETRY_ENABLE BIT_0 1998 #define VP_OPTS_VP_DISABLE BIT_1 1999 } vport_params_t; 2000 2001 /* NPIV - return codes of VP create and modify */ 2002 #define VP_RET_CODE_OK 0 2003 #define VP_RET_CODE_FATAL 1 2004 #define VP_RET_CODE_WRONG_ID 2 2005 #define VP_RET_CODE_WWPN 3 2006 #define VP_RET_CODE_RESOURCES 4 2007 #define VP_RET_CODE_NO_MEM 5 2008 #define VP_RET_CODE_NOT_FOUND 6 2009 2010 struct qla_hw_data; 2011 2012 /* 2013 * ISP operations 2014 */ 2015 struct isp_operations { 2016 2017 int (*pci_config) (struct scsi_qla_host *); 2018 void (*reset_chip) (struct scsi_qla_host *); 2019 int (*chip_diag) (struct scsi_qla_host *); 2020 void (*config_rings) (struct scsi_qla_host *); 2021 void (*reset_adapter) (struct scsi_qla_host *); 2022 int (*nvram_config) (struct scsi_qla_host *); 2023 void (*update_fw_options) (struct scsi_qla_host *); 2024 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 2025 2026 char * (*pci_info_str) (struct scsi_qla_host *, char *); 2027 char * (*fw_version_str) (struct scsi_qla_host *, char *); 2028 2029 irq_handler_t intr_handler; 2030 void (*enable_intrs) (struct qla_hw_data *); 2031 void (*disable_intrs) (struct qla_hw_data *); 2032 2033 int (*abort_command) (struct scsi_qla_host *, srb_t *, 2034 struct req_que *); 2035 int (*target_reset) (struct fc_port *, unsigned int); 2036 int (*lun_reset) (struct fc_port *, unsigned int); 2037 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 2038 uint8_t, uint8_t, uint16_t *, uint8_t); 2039 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 2040 uint8_t, uint8_t); 2041 2042 uint16_t (*calc_req_entries) (uint16_t); 2043 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 2044 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t); 2045 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 2046 uint32_t); 2047 2048 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *, 2049 uint32_t, uint32_t); 2050 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 2051 uint32_t); 2052 2053 void (*fw_dump) (struct scsi_qla_host *, int); 2054 2055 int (*beacon_on) (struct scsi_qla_host *); 2056 int (*beacon_off) (struct scsi_qla_host *); 2057 void (*beacon_blink) (struct scsi_qla_host *); 2058 2059 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 2060 uint32_t, uint32_t); 2061 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 2062 uint32_t); 2063 2064 int (*get_flash_version) (struct scsi_qla_host *, void *); 2065 int (*start_scsi) (srb_t *); 2066 }; 2067 2068 /* MSI-X Support *************************************************************/ 2069 2070 #define QLA_MSIX_CHIP_REV_24XX 3 2071 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 2072 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 2073 2074 #define QLA_MSIX_DEFAULT 0x00 2075 #define QLA_MSIX_RSP_Q 0x01 2076 2077 #define QLA_MIDX_DEFAULT 0 2078 #define QLA_MIDX_RSP_Q 1 2079 #define QLA_PCI_MSIX_CONTROL 0xa2 2080 2081 struct scsi_qla_host; 2082 struct rsp_que; 2083 2084 struct qla_msix_entry { 2085 int have_irq; 2086 uint32_t vector; 2087 uint16_t entry; 2088 struct rsp_que *rsp; 2089 }; 2090 2091 #define WATCH_INTERVAL 1 /* number of seconds */ 2092 2093 /* Work events. */ 2094 enum qla_work_type { 2095 QLA_EVT_AEN, 2096 QLA_EVT_IDC_ACK, 2097 }; 2098 2099 2100 struct qla_work_evt { 2101 struct list_head list; 2102 enum qla_work_type type; 2103 u32 flags; 2104 #define QLA_EVT_FLAG_FREE 0x1 2105 2106 union { 2107 struct { 2108 enum fc_host_event_code code; 2109 u32 data; 2110 } aen; 2111 struct { 2112 #define QLA_IDC_ACK_REGS 7 2113 uint16_t mb[QLA_IDC_ACK_REGS]; 2114 } idc_ack; 2115 } u; 2116 }; 2117 2118 struct qla_chip_state_84xx { 2119 struct list_head list; 2120 struct kref kref; 2121 2122 void *bus; 2123 spinlock_t access_lock; 2124 struct mutex fw_update_mutex; 2125 uint32_t fw_update; 2126 uint32_t op_fw_version; 2127 uint32_t op_fw_size; 2128 uint32_t op_fw_seq_size; 2129 uint32_t diag_fw_version; 2130 uint32_t gold_fw_version; 2131 }; 2132 2133 struct qla_statistics { 2134 uint32_t total_isp_aborts; 2135 uint64_t input_bytes; 2136 uint64_t output_bytes; 2137 }; 2138 2139 /* Multi queue support */ 2140 #define MBC_INITIALIZE_MULTIQ 0x1f 2141 #define QLA_QUE_PAGE 0X1000 2142 #define QLA_MQ_SIZE 32 2143 #define QLA_MAX_HOST_QUES 16 2144 #define QLA_MAX_QUEUES 256 2145 #define ISP_QUE_REG(ha, id) \ 2146 ((ha->mqenable) ? \ 2147 ((void *)(ha->mqiobase) +\ 2148 (QLA_QUE_PAGE * id)) :\ 2149 ((void *)(ha->iobase))) 2150 #define QLA_REQ_QUE_ID(tag) \ 2151 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 2152 #define QLA_DEFAULT_QUE_QOS 5 2153 #define QLA_PRECONFIG_VPORTS 32 2154 #define QLA_MAX_VPORTS_QLA24XX 128 2155 #define QLA_MAX_VPORTS_QLA25XX 256 2156 /* Response queue data structure */ 2157 struct rsp_que { 2158 dma_addr_t dma; 2159 response_t *ring; 2160 response_t *ring_ptr; 2161 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 2162 uint32_t __iomem *rsp_q_out; 2163 uint16_t ring_index; 2164 uint16_t out_ptr; 2165 uint16_t length; 2166 uint16_t options; 2167 uint16_t rid; 2168 uint16_t id; 2169 uint16_t vp_idx; 2170 struct qla_hw_data *hw; 2171 struct qla_msix_entry *msix; 2172 struct req_que *req; 2173 }; 2174 2175 /* Request queue data structure */ 2176 struct req_que { 2177 dma_addr_t dma; 2178 request_t *ring; 2179 request_t *ring_ptr; 2180 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 2181 uint32_t __iomem *req_q_out; 2182 uint16_t ring_index; 2183 uint16_t in_ptr; 2184 uint16_t cnt; 2185 uint16_t length; 2186 uint16_t options; 2187 uint16_t rid; 2188 uint16_t id; 2189 uint16_t qos; 2190 uint16_t vp_idx; 2191 struct rsp_que *rsp; 2192 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; 2193 uint32_t current_outstanding_cmd; 2194 int max_q_depth; 2195 }; 2196 2197 /* 2198 * Qlogic host adapter specific data structure. 2199 */ 2200 struct qla_hw_data { 2201 struct pci_dev *pdev; 2202 /* SRB cache. */ 2203 #define SRB_MIN_REQ 128 2204 mempool_t *srb_mempool; 2205 2206 volatile struct { 2207 uint32_t mbox_int :1; 2208 uint32_t mbox_busy :1; 2209 2210 uint32_t disable_risc_code_load :1; 2211 uint32_t enable_64bit_addressing :1; 2212 uint32_t enable_lip_reset :1; 2213 uint32_t enable_target_reset :1; 2214 uint32_t enable_lip_full_login :1; 2215 uint32_t enable_led_scheme :1; 2216 uint32_t inta_enabled :1; 2217 uint32_t msi_enabled :1; 2218 uint32_t msix_enabled :1; 2219 uint32_t disable_serdes :1; 2220 uint32_t gpsc_supported :1; 2221 uint32_t npiv_supported :1; 2222 uint32_t fce_enabled :1; 2223 uint32_t fac_supported :1; 2224 uint32_t chip_reset_done :1; 2225 } flags; 2226 2227 /* This spinlock is used to protect "io transactions", you must 2228 * acquire it before doing any IO to the card, eg with RD_REG*() and 2229 * WRT_REG*() for the duration of your entire commandtransaction. 2230 * 2231 * This spinlock is of lower priority than the io request lock. 2232 */ 2233 2234 spinlock_t hardware_lock ____cacheline_aligned; 2235 int bars; 2236 int mem_only; 2237 device_reg_t __iomem *iobase; /* Base I/O address */ 2238 resource_size_t pio_address; 2239 2240 #define MIN_IOBASE_LEN 0x100 2241 /* Multi queue data structs */ 2242 device_reg_t __iomem *mqiobase; 2243 uint16_t msix_count; 2244 uint8_t mqenable; 2245 struct req_que **req_q_map; 2246 struct rsp_que **rsp_q_map; 2247 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 2248 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 2249 uint16_t max_queues; 2250 struct qla_npiv_entry *npiv_info; 2251 uint16_t nvram_npiv_size; 2252 2253 uint16_t switch_cap; 2254 #define FLOGI_SEQ_DEL BIT_8 2255 #define FLOGI_MID_SUPPORT BIT_10 2256 #define FLOGI_VSAN_SUPPORT BIT_12 2257 #define FLOGI_SP_SUPPORT BIT_13 2258 /* Timeout timers. */ 2259 uint8_t loop_down_abort_time; /* port down timer */ 2260 atomic_t loop_down_timer; /* loop down timer */ 2261 uint8_t link_down_timeout; /* link down timeout */ 2262 uint16_t max_loop_id; 2263 2264 uint16_t fb_rev; 2265 uint16_t min_external_loopid; /* First external loop Id */ 2266 2267 #define PORT_SPEED_UNKNOWN 0xFFFF 2268 #define PORT_SPEED_1GB 0x00 2269 #define PORT_SPEED_2GB 0x01 2270 #define PORT_SPEED_4GB 0x03 2271 #define PORT_SPEED_8GB 0x04 2272 #define PORT_SPEED_10GB 0x13 2273 uint16_t link_data_rate; /* F/W operating speed */ 2274 2275 uint8_t current_topology; 2276 uint8_t prev_topology; 2277 #define ISP_CFG_NL 1 2278 #define ISP_CFG_N 2 2279 #define ISP_CFG_FL 4 2280 #define ISP_CFG_F 8 2281 2282 uint8_t operating_mode; /* F/W operating mode */ 2283 #define LOOP 0 2284 #define P2P 1 2285 #define LOOP_P2P 2 2286 #define P2P_LOOP 3 2287 uint8_t interrupts_on; 2288 uint32_t isp_abort_cnt; 2289 2290 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 2291 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 2292 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 2293 uint32_t device_type; 2294 #define DT_ISP2100 BIT_0 2295 #define DT_ISP2200 BIT_1 2296 #define DT_ISP2300 BIT_2 2297 #define DT_ISP2312 BIT_3 2298 #define DT_ISP2322 BIT_4 2299 #define DT_ISP6312 BIT_5 2300 #define DT_ISP6322 BIT_6 2301 #define DT_ISP2422 BIT_7 2302 #define DT_ISP2432 BIT_8 2303 #define DT_ISP5422 BIT_9 2304 #define DT_ISP5432 BIT_10 2305 #define DT_ISP2532 BIT_11 2306 #define DT_ISP8432 BIT_12 2307 #define DT_ISP8001 BIT_13 2308 #define DT_ISP_LAST (DT_ISP8001 << 1) 2309 2310 #define DT_IIDMA BIT_26 2311 #define DT_FWI2 BIT_27 2312 #define DT_ZIO_SUPPORTED BIT_28 2313 #define DT_OEM_001 BIT_29 2314 #define DT_ISP2200A BIT_30 2315 #define DT_EXTENDED_IDS BIT_31 2316 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1)) 2317 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 2318 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 2319 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 2320 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 2321 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 2322 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 2323 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 2324 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 2325 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 2326 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 2327 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 2328 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 2329 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 2330 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 2331 2332 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 2333 IS_QLA6312(ha) || IS_QLA6322(ha)) 2334 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 2335 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 2336 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 2337 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 2338 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 2339 IS_QLA84XX(ha)) 2340 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 2341 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 2342 IS_QLA25XX(ha) || IS_QLA81XX(ha)) 2343 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \ 2344 (ha)->flags.msix_enabled) 2345 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha)) 2346 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha)) 2347 2348 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 2349 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 2350 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 2351 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 2352 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 2353 2354 /* HBA serial number */ 2355 uint8_t serial0; 2356 uint8_t serial1; 2357 uint8_t serial2; 2358 2359 /* NVRAM configuration data */ 2360 #define MAX_NVRAM_SIZE 4096 2361 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 2362 uint16_t nvram_size; 2363 uint16_t nvram_base; 2364 void *nvram; 2365 uint16_t vpd_size; 2366 uint16_t vpd_base; 2367 void *vpd; 2368 2369 uint16_t loop_reset_delay; 2370 uint8_t retry_count; 2371 uint8_t login_timeout; 2372 uint16_t r_a_tov; 2373 int port_down_retry_count; 2374 uint8_t mbx_count; 2375 2376 uint32_t login_retry_count; 2377 /* SNS command interfaces. */ 2378 ms_iocb_entry_t *ms_iocb; 2379 dma_addr_t ms_iocb_dma; 2380 struct ct_sns_pkt *ct_sns; 2381 dma_addr_t ct_sns_dma; 2382 /* SNS command interfaces for 2200. */ 2383 struct sns_cmd_pkt *sns_cmd; 2384 dma_addr_t sns_cmd_dma; 2385 2386 #define SFP_DEV_SIZE 256 2387 #define SFP_BLOCK_SIZE 64 2388 void *sfp_data; 2389 dma_addr_t sfp_data_dma; 2390 2391 uint8_t *edc_data; 2392 dma_addr_t edc_data_dma; 2393 uint16_t edc_data_len; 2394 2395 struct task_struct *dpc_thread; 2396 uint8_t dpc_active; /* DPC routine is active */ 2397 2398 dma_addr_t gid_list_dma; 2399 struct gid_list_info *gid_list; 2400 int gid_list_info_size; 2401 2402 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 2403 #define DMA_POOL_SIZE 256 2404 struct dma_pool *s_dma_pool; 2405 2406 dma_addr_t init_cb_dma; 2407 init_cb_t *init_cb; 2408 int init_cb_size; 2409 dma_addr_t ex_init_cb_dma; 2410 struct ex_init_cb_81xx *ex_init_cb; 2411 2412 /* These are used by mailbox operations. */ 2413 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 2414 2415 mbx_cmd_t *mcp; 2416 unsigned long mbx_cmd_flags; 2417 #define MBX_INTERRUPT 1 2418 #define MBX_INTR_WAIT 2 2419 #define MBX_UPDATE_FLASH_ACTIVE 3 2420 2421 struct mutex vport_lock; /* Virtual port synchronization */ 2422 struct completion mbx_cmd_comp; /* Serialize mbx access */ 2423 struct completion mbx_intr_comp; /* Used for completion notification */ 2424 2425 /* Basic firmware related information. */ 2426 uint16_t fw_major_version; 2427 uint16_t fw_minor_version; 2428 uint16_t fw_subminor_version; 2429 uint16_t fw_attributes; 2430 uint32_t fw_memory_size; 2431 uint32_t fw_transfer_size; 2432 uint32_t fw_srisc_address; 2433 #define RISC_START_ADDRESS_2100 0x1000 2434 #define RISC_START_ADDRESS_2300 0x800 2435 #define RISC_START_ADDRESS_2400 0x100000 2436 uint16_t fw_xcb_count; 2437 2438 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 2439 uint8_t fw_seriallink_options[4]; 2440 uint16_t fw_seriallink_options24[4]; 2441 2442 uint8_t mpi_version[3]; 2443 uint32_t mpi_capabilities; 2444 uint8_t phy_version[3]; 2445 2446 /* Firmware dump information. */ 2447 struct qla2xxx_fw_dump *fw_dump; 2448 uint32_t fw_dump_len; 2449 int fw_dumped; 2450 int fw_dump_reading; 2451 dma_addr_t eft_dma; 2452 void *eft; 2453 2454 uint32_t chain_offset; 2455 struct dentry *dfs_dir; 2456 struct dentry *dfs_fce; 2457 dma_addr_t fce_dma; 2458 void *fce; 2459 uint32_t fce_bufs; 2460 uint16_t fce_mb[8]; 2461 uint64_t fce_wr, fce_rd; 2462 struct mutex fce_mutex; 2463 2464 uint32_t pci_attr; 2465 uint16_t chip_revision; 2466 2467 uint16_t product_id[4]; 2468 2469 uint8_t model_number[16+1]; 2470 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 2471 char model_desc[80]; 2472 uint8_t adapter_id[16+1]; 2473 2474 /* Option ROM information. */ 2475 char *optrom_buffer; 2476 uint32_t optrom_size; 2477 int optrom_state; 2478 #define QLA_SWAITING 0 2479 #define QLA_SREADING 1 2480 #define QLA_SWRITING 2 2481 uint32_t optrom_region_start; 2482 uint32_t optrom_region_size; 2483 2484 /* PCI expansion ROM image information. */ 2485 #define ROM_CODE_TYPE_BIOS 0 2486 #define ROM_CODE_TYPE_FCODE 1 2487 #define ROM_CODE_TYPE_EFI 3 2488 uint8_t bios_revision[2]; 2489 uint8_t efi_revision[2]; 2490 uint8_t fcode_revision[16]; 2491 uint32_t fw_revision[4]; 2492 2493 /* Offsets for flash/nvram access (set to ~0 if not used). */ 2494 uint32_t flash_conf_off; 2495 uint32_t flash_data_off; 2496 uint32_t nvram_conf_off; 2497 uint32_t nvram_data_off; 2498 2499 uint32_t fdt_wrt_disable; 2500 uint32_t fdt_erase_cmd; 2501 uint32_t fdt_block_size; 2502 uint32_t fdt_unprotect_sec_cmd; 2503 uint32_t fdt_protect_sec_cmd; 2504 2505 uint32_t flt_region_flt; 2506 uint32_t flt_region_fdt; 2507 uint32_t flt_region_boot; 2508 uint32_t flt_region_fw; 2509 uint32_t flt_region_vpd_nvram; 2510 uint32_t flt_region_vpd; 2511 uint32_t flt_region_nvram; 2512 uint32_t flt_region_npiv_conf; 2513 2514 /* Needed for BEACON */ 2515 uint16_t beacon_blink_led; 2516 uint8_t beacon_color_state; 2517 #define QLA_LED_GRN_ON 0x01 2518 #define QLA_LED_YLW_ON 0x02 2519 #define QLA_LED_ABR_ON 0x04 2520 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 2521 /* ISP2322: red, green, amber. */ 2522 uint16_t zio_mode; 2523 uint16_t zio_timer; 2524 struct fc_host_statistics fc_host_stat; 2525 2526 struct qla_msix_entry *msix_entries; 2527 2528 struct list_head vp_list; /* list of VP */ 2529 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 2530 sizeof(unsigned long)]; 2531 uint16_t num_vhosts; /* number of vports created */ 2532 uint16_t num_vsans; /* number of vsan created */ 2533 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 2534 int cur_vport_count; 2535 2536 struct qla_chip_state_84xx *cs84xx; 2537 struct qla_statistics qla_stats; 2538 struct isp_operations *isp_ops; 2539 }; 2540 2541 /* 2542 * Qlogic scsi host structure 2543 */ 2544 typedef struct scsi_qla_host { 2545 struct list_head list; 2546 struct list_head vp_fcports; /* list of fcports */ 2547 struct list_head work_list; 2548 /* Commonly used flags and state information. */ 2549 struct Scsi_Host *host; 2550 unsigned long host_no; 2551 uint8_t host_str[16]; 2552 2553 volatile struct { 2554 uint32_t init_done :1; 2555 uint32_t online :1; 2556 uint32_t rscn_queue_overflow :1; 2557 uint32_t reset_active :1; 2558 2559 uint32_t management_server_logged_in :1; 2560 uint32_t process_response_queue :1; 2561 } flags; 2562 2563 atomic_t loop_state; 2564 #define LOOP_TIMEOUT 1 2565 #define LOOP_DOWN 2 2566 #define LOOP_UP 3 2567 #define LOOP_UPDATE 4 2568 #define LOOP_READY 5 2569 #define LOOP_DEAD 6 2570 2571 unsigned long dpc_flags; 2572 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 2573 #define RESET_ACTIVE 1 2574 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 2575 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 2576 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 2577 #define LOOP_RESYNC_ACTIVE 5 2578 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 2579 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 2580 #define RELOGIN_NEEDED 8 2581 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 2582 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 2583 #define BEACON_BLINK_NEEDED 11 2584 #define REGISTER_FDMI_NEEDED 12 2585 #define FCPORT_UPDATE_NEEDED 13 2586 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 2587 #define UNLOADING 15 2588 #define NPIV_CONFIG_NEEDED 16 2589 2590 uint32_t device_flags; 2591 #define SWITCH_FOUND BIT_0 2592 #define DFLG_NO_CABLE BIT_1 2593 2594 srb_t *status_srb; /* Status continuation entry. */ 2595 2596 /* ISP configuration data. */ 2597 uint16_t loop_id; /* Host adapter loop id */ 2598 2599 port_id_t d_id; /* Host adapter port id */ 2600 uint8_t marker_needed; 2601 uint16_t mgmt_svr_loop_id; 2602 2603 2604 2605 /* RSCN queue. */ 2606 uint32_t rscn_queue[MAX_RSCN_COUNT]; 2607 uint8_t rscn_in_ptr; 2608 uint8_t rscn_out_ptr; 2609 2610 /* Timeout timers. */ 2611 uint8_t loop_down_abort_time; /* port down timer */ 2612 atomic_t loop_down_timer; /* loop down timer */ 2613 uint8_t link_down_timeout; /* link down timeout */ 2614 2615 uint32_t timer_active; 2616 struct timer_list timer; 2617 2618 uint8_t node_name[WWN_SIZE]; 2619 uint8_t port_name[WWN_SIZE]; 2620 uint8_t fabric_node_name[WWN_SIZE]; 2621 uint32_t vp_abort_cnt; 2622 2623 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 2624 uint16_t vp_idx; /* vport ID */ 2625 2626 unsigned long vp_flags; 2627 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 2628 #define VP_CREATE_NEEDED 1 2629 #define VP_BIND_NEEDED 2 2630 #define VP_DELETE_NEEDED 3 2631 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 2632 atomic_t vp_state; 2633 #define VP_OFFLINE 0 2634 #define VP_ACTIVE 1 2635 #define VP_FAILED 2 2636 // #define VP_DISABLE 3 2637 uint16_t vp_err_state; 2638 uint16_t vp_prev_err_state; 2639 #define VP_ERR_UNKWN 0 2640 #define VP_ERR_PORTDWN 1 2641 #define VP_ERR_FAB_UNSUPPORTED 2 2642 #define VP_ERR_FAB_NORESOURCES 3 2643 #define VP_ERR_FAB_LOGOUT 4 2644 #define VP_ERR_ADAP_NORESOURCES 5 2645 struct qla_hw_data *hw; 2646 int req_ques[QLA_MAX_HOST_QUES]; 2647 } scsi_qla_host_t; 2648 2649 /* 2650 * Macros to help code, maintain, etc. 2651 */ 2652 #define LOOP_TRANSITION(ha) \ 2653 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 2654 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 2655 atomic_read(&ha->loop_state) == LOOP_DOWN) 2656 2657 #define qla_printk(level, ha, format, arg...) \ 2658 dev_printk(level , &((ha)->pdev->dev) , format , ## arg) 2659 2660 /* 2661 * qla2x00 local function return status codes 2662 */ 2663 #define MBS_MASK 0x3fff 2664 2665 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 2666 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 2667 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 2668 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 2669 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 2670 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 2671 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 2672 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 2673 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 2674 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 2675 2676 #define QLA_FUNCTION_TIMEOUT 0x100 2677 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 2678 #define QLA_FUNCTION_FAILED 0x102 2679 #define QLA_MEMORY_ALLOC_FAILED 0x103 2680 #define QLA_LOCK_TIMEOUT 0x104 2681 #define QLA_ABORTED 0x105 2682 #define QLA_SUSPENDED 0x106 2683 #define QLA_BUSY 0x107 2684 #define QLA_RSCNS_HANDLED 0x108 2685 #define QLA_ALREADY_REGISTERED 0x109 2686 2687 #define NVRAM_DELAY() udelay(10) 2688 2689 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1) 2690 2691 /* 2692 * Flash support definitions 2693 */ 2694 #define OPTROM_SIZE_2300 0x20000 2695 #define OPTROM_SIZE_2322 0x100000 2696 #define OPTROM_SIZE_24XX 0x100000 2697 #define OPTROM_SIZE_25XX 0x200000 2698 #define OPTROM_SIZE_81XX 0x400000 2699 2700 #include "qla_gbl.h" 2701 #include "qla_dbg.h" 2702 #include "qla_inline.h" 2703 2704 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 2705 2706 #endif 2707