1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #ifndef __QLA_DEF_H 7 #define __QLA_DEF_H 8 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/types.h> 12 #include <linux/module.h> 13 #include <linux/list.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/sched.h> 17 #include <linux/slab.h> 18 #include <linux/dmapool.h> 19 #include <linux/mempool.h> 20 #include <linux/spinlock.h> 21 #include <linux/completion.h> 22 #include <linux/interrupt.h> 23 #include <linux/workqueue.h> 24 #include <linux/firmware.h> 25 #include <linux/aer.h> 26 #include <linux/mutex.h> 27 #include <linux/btree.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 #include <scsi/scsi_bsg_fc.h> 35 36 #include <uapi/scsi/fc/fc_els.h> 37 38 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 39 typedef struct { 40 uint8_t domain; 41 uint8_t area; 42 uint8_t al_pa; 43 } be_id_t; 44 45 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 46 typedef struct { 47 uint8_t al_pa; 48 uint8_t area; 49 uint8_t domain; 50 } le_id_t; 51 52 #include "qla_bsg.h" 53 #include "qla_dsd.h" 54 #include "qla_nx.h" 55 #include "qla_nx2.h" 56 #include "qla_nvme.h" 57 #define QLA2XXX_DRIVER_NAME "qla2xxx" 58 #define QLA2XXX_APIDEV "ql2xapidev" 59 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 60 61 /* 62 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 63 * but that's fine as we don't look at the last 24 ones for 64 * ISP2100 HBAs. 65 */ 66 #define MAILBOX_REGISTER_COUNT_2100 8 67 #define MAILBOX_REGISTER_COUNT_2200 24 68 #define MAILBOX_REGISTER_COUNT 32 69 70 #define QLA2200A_RISC_ROM_VER 4 71 #define FPM_2300 6 72 #define FPM_2310 7 73 74 #include "qla_settings.h" 75 76 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 77 78 /* 79 * Data bit definitions 80 */ 81 #define BIT_0 0x1 82 #define BIT_1 0x2 83 #define BIT_2 0x4 84 #define BIT_3 0x8 85 #define BIT_4 0x10 86 #define BIT_5 0x20 87 #define BIT_6 0x40 88 #define BIT_7 0x80 89 #define BIT_8 0x100 90 #define BIT_9 0x200 91 #define BIT_10 0x400 92 #define BIT_11 0x800 93 #define BIT_12 0x1000 94 #define BIT_13 0x2000 95 #define BIT_14 0x4000 96 #define BIT_15 0x8000 97 #define BIT_16 0x10000 98 #define BIT_17 0x20000 99 #define BIT_18 0x40000 100 #define BIT_19 0x80000 101 #define BIT_20 0x100000 102 #define BIT_21 0x200000 103 #define BIT_22 0x400000 104 #define BIT_23 0x800000 105 #define BIT_24 0x1000000 106 #define BIT_25 0x2000000 107 #define BIT_26 0x4000000 108 #define BIT_27 0x8000000 109 #define BIT_28 0x10000000 110 #define BIT_29 0x20000000 111 #define BIT_30 0x40000000 112 #define BIT_31 0x80000000 113 114 #define LSB(x) ((uint8_t)(x)) 115 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 116 117 #define LSW(x) ((uint16_t)(x)) 118 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 119 120 #define LSD(x) ((uint32_t)((uint64_t)(x))) 121 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 122 123 static inline uint32_t make_handle(uint16_t x, uint16_t y) 124 { 125 return ((uint32_t)x << 16) | y; 126 } 127 128 /* 129 * I/O register 130 */ 131 132 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr) 133 { 134 return readb(addr); 135 } 136 137 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr) 138 { 139 return readw(addr); 140 } 141 142 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr) 143 { 144 return readl(addr); 145 } 146 147 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr) 148 { 149 return readb_relaxed(addr); 150 } 151 152 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr) 153 { 154 return readw_relaxed(addr); 155 } 156 157 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr) 158 { 159 return readl_relaxed(addr); 160 } 161 162 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data) 163 { 164 return writeb(data, addr); 165 } 166 167 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data) 168 { 169 return writew(data, addr); 170 } 171 172 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data) 173 { 174 return writel(data, addr); 175 } 176 177 /* 178 * ISP83XX specific remote register addresses 179 */ 180 #define QLA83XX_LED_PORT0 0x00201320 181 #define QLA83XX_LED_PORT1 0x00201328 182 #define QLA83XX_IDC_DEV_STATE 0x22102384 183 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 184 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 185 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 186 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 187 #define QLA83XX_IDC_CONTROL 0x22102390 188 #define QLA83XX_IDC_AUDIT 0x22102394 189 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 190 #define QLA83XX_DRIVER_LOCKID 0x22102104 191 #define QLA83XX_DRIVER_LOCK 0x8111c028 192 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 193 #define QLA83XX_FLASH_LOCKID 0x22102100 194 #define QLA83XX_FLASH_LOCK 0x8111c010 195 #define QLA83XX_FLASH_UNLOCK 0x8111c014 196 #define QLA83XX_DEV_PARTINFO1 0x221023e0 197 #define QLA83XX_DEV_PARTINFO2 0x221023e4 198 #define QLA83XX_FW_HEARTBEAT 0x221020b0 199 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 200 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 201 202 /* 83XX: Macros defining 8200 AEN Reason codes */ 203 #define IDC_DEVICE_STATE_CHANGE BIT_0 204 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 205 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 206 #define IDC_HEARTBEAT_FAILURE BIT_3 207 208 /* 83XX: Macros defining 8200 AEN Error-levels */ 209 #define ERR_LEVEL_NON_FATAL 0x1 210 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 211 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 212 213 /* 83XX: Macros for IDC Version */ 214 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 215 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 216 217 /* 83XX: Macros for scheduling dpc tasks */ 218 #define QLA83XX_NIC_CORE_RESET 0x1 219 #define QLA83XX_IDC_STATE_HANDLER 0x2 220 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 221 222 /* 83XX: Macros for defining IDC-Control bits */ 223 #define QLA83XX_IDC_RESET_DISABLED BIT_0 224 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 225 226 /* 83XX: Macros for different timeouts */ 227 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 228 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 229 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 230 231 /* 83XX: Macros for defining class in DEV-Partition Info register */ 232 #define QLA83XX_CLASS_TYPE_NONE 0x0 233 #define QLA83XX_CLASS_TYPE_NIC 0x1 234 #define QLA83XX_CLASS_TYPE_FCOE 0x2 235 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 236 237 /* 83XX: Macros for IDC Lock-Recovery stages */ 238 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 239 * lock-recovery 240 */ 241 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 242 243 /* 83XX: Macros for IDC Audit type */ 244 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 245 * dev-state change to NEED-RESET 246 * or NEED-QUIESCENT 247 */ 248 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 249 * reset-recovery completion is 250 * second 251 */ 252 /* ISP2031: Values for laser on/off */ 253 #define PORT_0_2031 0x00201340 254 #define PORT_1_2031 0x00201350 255 #define LASER_ON_2031 0x01800100 256 #define LASER_OFF_2031 0x01800180 257 258 /* 259 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 260 * 133Mhz slot. 261 */ 262 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 263 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr)) 264 265 /* 266 * Fibre Channel device definitions. 267 */ 268 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 269 #define MAX_FIBRE_DEVICES_2100 512 270 #define MAX_FIBRE_DEVICES_2400 2048 271 #define MAX_FIBRE_DEVICES_LOOP 128 272 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 273 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 274 #define MAX_FIBRE_LUNS 0xFFFF 275 #define MAX_HOST_COUNT 16 276 277 /* 278 * Host adapter default definitions. 279 */ 280 #define MAX_BUSES 1 /* We only have one bus today */ 281 #define MIN_LUNS 8 282 #define MAX_LUNS MAX_FIBRE_LUNS 283 #define MAX_CMDS_PER_LUN 255 284 285 /* 286 * Fibre Channel device definitions. 287 */ 288 #define SNS_LAST_LOOP_ID_2100 0xfe 289 #define SNS_LAST_LOOP_ID_2300 0x7ff 290 291 #define LAST_LOCAL_LOOP_ID 0x7d 292 #define SNS_FL_PORT 0x7e 293 #define FABRIC_CONTROLLER 0x7f 294 #define SIMPLE_NAME_SERVER 0x80 295 #define SNS_FIRST_LOOP_ID 0x81 296 #define MANAGEMENT_SERVER 0xfe 297 #define BROADCAST 0xff 298 299 /* 300 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 301 * valid range of an N-PORT id is 0 through 0x7ef. 302 */ 303 #define NPH_LAST_HANDLE 0x7ee 304 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ 305 #define NPH_SNS 0x7fc /* FFFFFC */ 306 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 307 #define NPH_F_PORT 0x7fe /* FFFFFE */ 308 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 309 310 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 311 312 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 313 #include "qla_fw.h" 314 315 struct name_list_extended { 316 struct get_name_list_extended *l; 317 dma_addr_t ldma; 318 struct list_head fcports; 319 u32 size; 320 u8 sent; 321 }; 322 /* 323 * Timeout timer counts in seconds 324 */ 325 #define PORT_RETRY_TIME 1 326 #define LOOP_DOWN_TIMEOUT 60 327 #define LOOP_DOWN_TIME 255 /* 240 */ 328 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 329 330 #define DEFAULT_OUTSTANDING_COMMANDS 4096 331 #define MIN_OUTSTANDING_COMMANDS 128 332 333 /* ISP request and response entry counts (37-65535) */ 334 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 335 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 336 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 337 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 338 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 339 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 340 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 341 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 342 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 343 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 344 #define FW_DEF_EXCHANGES_CNT 2048 345 #define FW_MAX_EXCHANGES_CNT (32 * 1024) 346 #define REDUCE_EXCHANGES_CNT (8 * 1024) 347 348 struct req_que; 349 struct qla_tgt_sess; 350 351 /* 352 * SCSI Request Block 353 */ 354 struct srb_cmd { 355 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 356 uint32_t request_sense_length; 357 uint32_t fw_sense_length; 358 uint8_t *request_sense_ptr; 359 struct ct6_dsd *ct6_ctx; 360 struct crc_context *crc_ctx; 361 }; 362 363 /* 364 * SRB flag definitions 365 */ 366 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 367 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 368 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 369 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 370 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 371 #define SRB_WAKEUP_ON_COMP BIT_6 372 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */ 373 374 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 375 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 376 377 /* 378 * 24 bit port ID type definition. 379 */ 380 typedef union { 381 uint32_t b24 : 24; 382 383 struct { 384 #ifdef __BIG_ENDIAN 385 uint8_t domain; 386 uint8_t area; 387 uint8_t al_pa; 388 #elif defined(__LITTLE_ENDIAN) 389 uint8_t al_pa; 390 uint8_t area; 391 uint8_t domain; 392 #else 393 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 394 #endif 395 uint8_t rsvd_1; 396 } b; 397 } port_id_t; 398 #define INVALID_PORT_ID 0xFFFFFF 399 400 static inline le_id_t be_id_to_le(be_id_t id) 401 { 402 le_id_t res; 403 404 res.domain = id.domain; 405 res.area = id.area; 406 res.al_pa = id.al_pa; 407 408 return res; 409 } 410 411 static inline be_id_t le_id_to_be(le_id_t id) 412 { 413 be_id_t res; 414 415 res.domain = id.domain; 416 res.area = id.area; 417 res.al_pa = id.al_pa; 418 419 return res; 420 } 421 422 static inline port_id_t be_to_port_id(be_id_t id) 423 { 424 port_id_t res; 425 426 res.b.domain = id.domain; 427 res.b.area = id.area; 428 res.b.al_pa = id.al_pa; 429 res.b.rsvd_1 = 0; 430 431 return res; 432 } 433 434 static inline be_id_t port_id_to_be_id(port_id_t port_id) 435 { 436 be_id_t res; 437 438 res.domain = port_id.b.domain; 439 res.area = port_id.b.area; 440 res.al_pa = port_id.b.al_pa; 441 442 return res; 443 } 444 445 struct els_logo_payload { 446 uint8_t opcode; 447 uint8_t rsvd[3]; 448 uint8_t s_id[3]; 449 uint8_t rsvd1[1]; 450 uint8_t wwpn[WWN_SIZE]; 451 }; 452 453 struct els_plogi_payload { 454 uint8_t opcode; 455 uint8_t rsvd[3]; 456 __be32 data[112 / 4]; 457 }; 458 459 struct ct_arg { 460 void *iocb; 461 u16 nport_handle; 462 dma_addr_t req_dma; 463 dma_addr_t rsp_dma; 464 u32 req_size; 465 u32 rsp_size; 466 u32 req_allocated_size; 467 u32 rsp_allocated_size; 468 void *req; 469 void *rsp; 470 port_id_t id; 471 }; 472 473 /* 474 * SRB extensions. 475 */ 476 struct srb_iocb { 477 union { 478 struct { 479 uint16_t flags; 480 #define SRB_LOGIN_RETRIED BIT_0 481 #define SRB_LOGIN_COND_PLOGI BIT_1 482 #define SRB_LOGIN_SKIP_PRLI BIT_2 483 #define SRB_LOGIN_NVME_PRLI BIT_3 484 #define SRB_LOGIN_PRLI_ONLY BIT_4 485 uint16_t data[2]; 486 u32 iop[2]; 487 } logio; 488 struct { 489 #define ELS_DCMD_TIMEOUT 20 490 #define ELS_DCMD_LOGO 0x5 491 uint32_t flags; 492 uint32_t els_cmd; 493 struct completion comp; 494 struct els_logo_payload *els_logo_pyld; 495 dma_addr_t els_logo_pyld_dma; 496 } els_logo; 497 struct els_plogi { 498 #define ELS_DCMD_PLOGI 0x3 499 uint32_t flags; 500 uint32_t els_cmd; 501 struct completion comp; 502 struct els_plogi_payload *els_plogi_pyld; 503 struct els_plogi_payload *els_resp_pyld; 504 u32 tx_size; 505 u32 rx_size; 506 dma_addr_t els_plogi_pyld_dma; 507 dma_addr_t els_resp_pyld_dma; 508 __le32 fw_status[3]; 509 __le16 comp_status; 510 __le16 len; 511 } els_plogi; 512 struct { 513 /* 514 * Values for flags field below are as 515 * defined in tsk_mgmt_entry struct 516 * for control_flags field in qla_fw.h. 517 */ 518 uint64_t lun; 519 uint32_t flags; 520 uint32_t data; 521 struct completion comp; 522 __le16 comp_status; 523 } tmf; 524 struct { 525 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 526 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 527 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 528 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 529 #define FXDISC_TIMEOUT 20 530 uint8_t flags; 531 uint32_t req_len; 532 uint32_t rsp_len; 533 void *req_addr; 534 void *rsp_addr; 535 dma_addr_t req_dma_handle; 536 dma_addr_t rsp_dma_handle; 537 __le32 adapter_id; 538 __le32 adapter_id_hi; 539 __le16 req_func_type; 540 __le32 req_data; 541 __le32 req_data_extra; 542 __le32 result; 543 __le32 seq_number; 544 __le16 fw_flags; 545 struct completion fxiocb_comp; 546 __le32 reserved_0; 547 uint8_t reserved_1; 548 } fxiocb; 549 struct { 550 uint32_t cmd_hndl; 551 __le16 comp_status; 552 __le16 req_que_no; 553 struct completion comp; 554 } abt; 555 struct ct_arg ctarg; 556 #define MAX_IOCB_MB_REG 28 557 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 558 struct { 559 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 560 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 561 void *out, *in; 562 dma_addr_t out_dma, in_dma; 563 struct completion comp; 564 int rc; 565 } mbx; 566 struct { 567 struct imm_ntfy_from_isp *ntfy; 568 } nack; 569 struct { 570 __le16 comp_status; 571 __le16 rsp_pyld_len; 572 uint8_t aen_op; 573 void *desc; 574 575 /* These are only used with ls4 requests */ 576 int cmd_len; 577 int rsp_len; 578 dma_addr_t cmd_dma; 579 dma_addr_t rsp_dma; 580 enum nvmefc_fcp_datadir dir; 581 uint32_t dl; 582 uint32_t timeout_sec; 583 struct list_head entry; 584 } nvme; 585 struct { 586 u16 cmd; 587 u16 vp_index; 588 } ctrlvp; 589 } u; 590 591 struct timer_list timer; 592 void (*timeout)(void *); 593 }; 594 595 /* Values for srb_ctx type */ 596 #define SRB_LOGIN_CMD 1 597 #define SRB_LOGOUT_CMD 2 598 #define SRB_ELS_CMD_RPT 3 599 #define SRB_ELS_CMD_HST 4 600 #define SRB_CT_CMD 5 601 #define SRB_ADISC_CMD 6 602 #define SRB_TM_CMD 7 603 #define SRB_SCSI_CMD 8 604 #define SRB_BIDI_CMD 9 605 #define SRB_FXIOCB_DCMD 10 606 #define SRB_FXIOCB_BCMD 11 607 #define SRB_ABT_CMD 12 608 #define SRB_ELS_DCMD 13 609 #define SRB_MB_IOCB 14 610 #define SRB_CT_PTHRU_CMD 15 611 #define SRB_NACK_PLOGI 16 612 #define SRB_NACK_PRLI 17 613 #define SRB_NACK_LOGO 18 614 #define SRB_NVME_CMD 19 615 #define SRB_NVME_LS 20 616 #define SRB_PRLI_CMD 21 617 #define SRB_CTRL_VP 22 618 #define SRB_PRLO_CMD 23 619 620 enum { 621 TYPE_SRB, 622 TYPE_TGT_CMD, 623 TYPE_TGT_TMCMD, /* task management */ 624 }; 625 626 struct iocb_resource { 627 u8 res_type; 628 u8 pad; 629 u16 iocb_cnt; 630 }; 631 632 typedef struct srb { 633 /* 634 * Do not move cmd_type field, it needs to 635 * line up with qla_tgt_cmd->cmd_type 636 */ 637 uint8_t cmd_type; 638 uint8_t pad[3]; 639 struct iocb_resource iores; 640 struct kref cmd_kref; /* need to migrate ref_count over to this */ 641 void *priv; 642 wait_queue_head_t nvme_ls_waitq; 643 struct fc_port *fcport; 644 struct scsi_qla_host *vha; 645 unsigned int start_timer:1; 646 647 uint32_t handle; 648 uint16_t flags; 649 uint16_t type; 650 const char *name; 651 int iocbs; 652 struct qla_qpair *qpair; 653 struct srb *cmd_sp; 654 struct list_head elem; 655 u32 gen1; /* scratch */ 656 u32 gen2; /* scratch */ 657 int rc; 658 int retry_count; 659 struct completion *comp; 660 union { 661 struct srb_iocb iocb_cmd; 662 struct bsg_job *bsg_job; 663 struct srb_cmd scmd; 664 } u; 665 /* 666 * Report completion status @res and call sp_put(@sp). @res is 667 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a 668 * QLA_* status value. 669 */ 670 void (*done)(struct srb *sp, int res); 671 /* Stop the timer and free @sp. Only used by the FCP code. */ 672 void (*free)(struct srb *sp); 673 /* 674 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe 675 * code. 676 */ 677 void (*put_fn)(struct kref *kref); 678 } srb_t; 679 680 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 681 682 #define GET_CMD_SENSE_LEN(sp) \ 683 (sp->u.scmd.request_sense_length) 684 #define SET_CMD_SENSE_LEN(sp, len) \ 685 (sp->u.scmd.request_sense_length = len) 686 #define GET_CMD_SENSE_PTR(sp) \ 687 (sp->u.scmd.request_sense_ptr) 688 #define SET_CMD_SENSE_PTR(sp, ptr) \ 689 (sp->u.scmd.request_sense_ptr = ptr) 690 #define GET_FW_SENSE_LEN(sp) \ 691 (sp->u.scmd.fw_sense_length) 692 #define SET_FW_SENSE_LEN(sp, len) \ 693 (sp->u.scmd.fw_sense_length = len) 694 695 struct msg_echo_lb { 696 dma_addr_t send_dma; 697 dma_addr_t rcv_dma; 698 uint16_t req_sg_cnt; 699 uint16_t rsp_sg_cnt; 700 uint16_t options; 701 uint32_t transfer_size; 702 uint32_t iteration_count; 703 }; 704 705 /* 706 * ISP I/O Register Set structure definitions. 707 */ 708 struct device_reg_2xxx { 709 __le16 flash_address; /* Flash BIOS address */ 710 __le16 flash_data; /* Flash BIOS data */ 711 __le16 unused_1[1]; /* Gap */ 712 __le16 ctrl_status; /* Control/Status */ 713 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 714 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 715 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 716 717 __le16 ictrl; /* Interrupt control */ 718 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 719 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 720 721 __le16 istatus; /* Interrupt status */ 722 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 723 724 __le16 semaphore; /* Semaphore */ 725 __le16 nvram; /* NVRAM register. */ 726 #define NVR_DESELECT 0 727 #define NVR_BUSY BIT_15 728 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 729 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 730 #define NVR_DATA_IN BIT_3 731 #define NVR_DATA_OUT BIT_2 732 #define NVR_SELECT BIT_1 733 #define NVR_CLOCK BIT_0 734 735 #define NVR_WAIT_CNT 20000 736 737 union { 738 struct { 739 __le16 mailbox0; 740 __le16 mailbox1; 741 __le16 mailbox2; 742 __le16 mailbox3; 743 __le16 mailbox4; 744 __le16 mailbox5; 745 __le16 mailbox6; 746 __le16 mailbox7; 747 __le16 unused_2[59]; /* Gap */ 748 } __attribute__((packed)) isp2100; 749 struct { 750 /* Request Queue */ 751 __le16 req_q_in; /* In-Pointer */ 752 __le16 req_q_out; /* Out-Pointer */ 753 /* Response Queue */ 754 __le16 rsp_q_in; /* In-Pointer */ 755 __le16 rsp_q_out; /* Out-Pointer */ 756 757 /* RISC to Host Status */ 758 __le32 host_status; 759 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 760 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 761 762 /* Host to Host Semaphore */ 763 __le16 host_semaphore; 764 __le16 unused_3[17]; /* Gap */ 765 __le16 mailbox0; 766 __le16 mailbox1; 767 __le16 mailbox2; 768 __le16 mailbox3; 769 __le16 mailbox4; 770 __le16 mailbox5; 771 __le16 mailbox6; 772 __le16 mailbox7; 773 __le16 mailbox8; 774 __le16 mailbox9; 775 __le16 mailbox10; 776 __le16 mailbox11; 777 __le16 mailbox12; 778 __le16 mailbox13; 779 __le16 mailbox14; 780 __le16 mailbox15; 781 __le16 mailbox16; 782 __le16 mailbox17; 783 __le16 mailbox18; 784 __le16 mailbox19; 785 __le16 mailbox20; 786 __le16 mailbox21; 787 __le16 mailbox22; 788 __le16 mailbox23; 789 __le16 mailbox24; 790 __le16 mailbox25; 791 __le16 mailbox26; 792 __le16 mailbox27; 793 __le16 mailbox28; 794 __le16 mailbox29; 795 __le16 mailbox30; 796 __le16 mailbox31; 797 __le16 fb_cmd; 798 __le16 unused_4[10]; /* Gap */ 799 } __attribute__((packed)) isp2300; 800 } u; 801 802 __le16 fpm_diag_config; 803 __le16 unused_5[0x4]; /* Gap */ 804 __le16 risc_hw; 805 __le16 unused_5_1; /* Gap */ 806 __le16 pcr; /* Processor Control Register. */ 807 __le16 unused_6[0x5]; /* Gap */ 808 __le16 mctr; /* Memory Configuration and Timing. */ 809 __le16 unused_7[0x3]; /* Gap */ 810 __le16 fb_cmd_2100; /* Unused on 23XX */ 811 __le16 unused_8[0x3]; /* Gap */ 812 __le16 hccr; /* Host command & control register. */ 813 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 814 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 815 /* HCCR commands */ 816 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 817 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 818 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 819 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 820 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 821 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 822 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 823 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 824 825 __le16 unused_9[5]; /* Gap */ 826 __le16 gpiod; /* GPIO Data register. */ 827 __le16 gpioe; /* GPIO Enable register. */ 828 #define GPIO_LED_MASK 0x00C0 829 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 830 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 831 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 832 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 833 #define GPIO_LED_ALL_OFF 0x0000 834 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 835 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 836 837 union { 838 struct { 839 __le16 unused_10[8]; /* Gap */ 840 __le16 mailbox8; 841 __le16 mailbox9; 842 __le16 mailbox10; 843 __le16 mailbox11; 844 __le16 mailbox12; 845 __le16 mailbox13; 846 __le16 mailbox14; 847 __le16 mailbox15; 848 __le16 mailbox16; 849 __le16 mailbox17; 850 __le16 mailbox18; 851 __le16 mailbox19; 852 __le16 mailbox20; 853 __le16 mailbox21; 854 __le16 mailbox22; 855 __le16 mailbox23; /* Also probe reg. */ 856 } __attribute__((packed)) isp2200; 857 } u_end; 858 }; 859 860 struct device_reg_25xxmq { 861 __le32 req_q_in; 862 __le32 req_q_out; 863 __le32 rsp_q_in; 864 __le32 rsp_q_out; 865 __le32 atio_q_in; 866 __le32 atio_q_out; 867 }; 868 869 870 struct device_reg_fx00 { 871 __le32 mailbox0; /* 00 */ 872 __le32 mailbox1; /* 04 */ 873 __le32 mailbox2; /* 08 */ 874 __le32 mailbox3; /* 0C */ 875 __le32 mailbox4; /* 10 */ 876 __le32 mailbox5; /* 14 */ 877 __le32 mailbox6; /* 18 */ 878 __le32 mailbox7; /* 1C */ 879 __le32 mailbox8; /* 20 */ 880 __le32 mailbox9; /* 24 */ 881 __le32 mailbox10; /* 28 */ 882 __le32 mailbox11; 883 __le32 mailbox12; 884 __le32 mailbox13; 885 __le32 mailbox14; 886 __le32 mailbox15; 887 __le32 mailbox16; 888 __le32 mailbox17; 889 __le32 mailbox18; 890 __le32 mailbox19; 891 __le32 mailbox20; 892 __le32 mailbox21; 893 __le32 mailbox22; 894 __le32 mailbox23; 895 __le32 mailbox24; 896 __le32 mailbox25; 897 __le32 mailbox26; 898 __le32 mailbox27; 899 __le32 mailbox28; 900 __le32 mailbox29; 901 __le32 mailbox30; 902 __le32 mailbox31; 903 __le32 aenmailbox0; 904 __le32 aenmailbox1; 905 __le32 aenmailbox2; 906 __le32 aenmailbox3; 907 __le32 aenmailbox4; 908 __le32 aenmailbox5; 909 __le32 aenmailbox6; 910 __le32 aenmailbox7; 911 /* Request Queue. */ 912 __le32 req_q_in; /* A0 - Request Queue In-Pointer */ 913 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */ 914 /* Response Queue. */ 915 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */ 916 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */ 917 /* Init values shadowed on FW Up Event */ 918 __le32 initval0; /* B0 */ 919 __le32 initval1; /* B4 */ 920 __le32 initval2; /* B8 */ 921 __le32 initval3; /* BC */ 922 __le32 initval4; /* C0 */ 923 __le32 initval5; /* C4 */ 924 __le32 initval6; /* C8 */ 925 __le32 initval7; /* CC */ 926 __le32 fwheartbeat; /* D0 */ 927 __le32 pseudoaen; /* D4 */ 928 }; 929 930 931 932 typedef union { 933 struct device_reg_2xxx isp; 934 struct device_reg_24xx isp24; 935 struct device_reg_25xxmq isp25mq; 936 struct device_reg_82xx isp82; 937 struct device_reg_fx00 ispfx00; 938 } __iomem device_reg_t; 939 940 #define ISP_REQ_Q_IN(ha, reg) \ 941 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 942 &(reg)->u.isp2100.mailbox4 : \ 943 &(reg)->u.isp2300.req_q_in) 944 #define ISP_REQ_Q_OUT(ha, reg) \ 945 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 946 &(reg)->u.isp2100.mailbox4 : \ 947 &(reg)->u.isp2300.req_q_out) 948 #define ISP_RSP_Q_IN(ha, reg) \ 949 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 950 &(reg)->u.isp2100.mailbox5 : \ 951 &(reg)->u.isp2300.rsp_q_in) 952 #define ISP_RSP_Q_OUT(ha, reg) \ 953 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 954 &(reg)->u.isp2100.mailbox5 : \ 955 &(reg)->u.isp2300.rsp_q_out) 956 957 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 958 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 959 960 #define MAILBOX_REG(ha, reg, num) \ 961 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 962 (num < 8 ? \ 963 &(reg)->u.isp2100.mailbox0 + (num) : \ 964 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 965 &(reg)->u.isp2300.mailbox0 + (num)) 966 #define RD_MAILBOX_REG(ha, reg, num) \ 967 rd_reg_word(MAILBOX_REG(ha, reg, num)) 968 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 969 wrt_reg_word(MAILBOX_REG(ha, reg, num), data) 970 971 #define FB_CMD_REG(ha, reg) \ 972 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 973 &(reg)->fb_cmd_2100 : \ 974 &(reg)->u.isp2300.fb_cmd) 975 #define RD_FB_CMD_REG(ha, reg) \ 976 rd_reg_word(FB_CMD_REG(ha, reg)) 977 #define WRT_FB_CMD_REG(ha, reg, data) \ 978 wrt_reg_word(FB_CMD_REG(ha, reg), data) 979 980 typedef struct { 981 uint32_t out_mb; /* outbound from driver */ 982 uint32_t in_mb; /* Incoming from RISC */ 983 uint16_t mb[MAILBOX_REGISTER_COUNT]; 984 long buf_size; 985 void *bufp; 986 uint32_t tov; 987 uint8_t flags; 988 #define MBX_DMA_IN BIT_0 989 #define MBX_DMA_OUT BIT_1 990 #define IOCTL_CMD BIT_2 991 } mbx_cmd_t; 992 993 struct mbx_cmd_32 { 994 uint32_t out_mb; /* outbound from driver */ 995 uint32_t in_mb; /* Incoming from RISC */ 996 uint32_t mb[MAILBOX_REGISTER_COUNT]; 997 long buf_size; 998 void *bufp; 999 uint32_t tov; 1000 uint8_t flags; 1001 #define MBX_DMA_IN BIT_0 1002 #define MBX_DMA_OUT BIT_1 1003 #define IOCTL_CMD BIT_2 1004 }; 1005 1006 1007 #define MBX_TOV_SECONDS 30 1008 1009 /* 1010 * ISP product identification definitions in mailboxes after reset. 1011 */ 1012 #define PROD_ID_1 0x4953 1013 #define PROD_ID_2 0x0000 1014 #define PROD_ID_2a 0x5020 1015 #define PROD_ID_3 0x2020 1016 1017 /* 1018 * ISP mailbox Self-Test status codes 1019 */ 1020 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 1021 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 1022 #define MBS_BUSY 4 /* Busy. */ 1023 1024 /* 1025 * ISP mailbox command complete status codes 1026 */ 1027 #define MBS_COMMAND_COMPLETE 0x4000 1028 #define MBS_INVALID_COMMAND 0x4001 1029 #define MBS_HOST_INTERFACE_ERROR 0x4002 1030 #define MBS_TEST_FAILED 0x4003 1031 #define MBS_COMMAND_ERROR 0x4005 1032 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 1033 #define MBS_PORT_ID_USED 0x4007 1034 #define MBS_LOOP_ID_USED 0x4008 1035 #define MBS_ALL_IDS_IN_USE 0x4009 1036 #define MBS_NOT_LOGGED_IN 0x400A 1037 #define MBS_LINK_DOWN_ERROR 0x400B 1038 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 1039 1040 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs) 1041 { 1042 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR; 1043 } 1044 1045 /* 1046 * ISP mailbox asynchronous event status codes 1047 */ 1048 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 1049 #define MBA_RESET 0x8001 /* Reset Detected. */ 1050 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 1051 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 1052 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 1053 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 1054 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 1055 /* occurred. */ 1056 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 1057 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 1058 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 1059 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 1060 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 1061 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 1062 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 1063 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 1064 #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */ 1065 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 1066 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 1067 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 1068 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 1069 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 1070 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 1071 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 1072 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 1073 /* used. */ 1074 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 1075 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 1076 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 1077 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 1078 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 1079 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 1080 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 1081 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 1082 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 1083 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 1084 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 1085 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 1086 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 1087 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 1088 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 1089 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 1090 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 1091 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 1092 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 1093 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 1094 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 1095 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 1096 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */ 1097 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 1098 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 1099 Notification */ 1100 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 1101 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 1102 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 1103 /* 83XX FCoE specific */ 1104 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 1105 1106 /* Interrupt type codes */ 1107 #define INTR_ROM_MB_SUCCESS 0x1 1108 #define INTR_ROM_MB_FAILED 0x2 1109 #define INTR_MB_SUCCESS 0x10 1110 #define INTR_MB_FAILED 0x11 1111 #define INTR_ASYNC_EVENT 0x12 1112 #define INTR_RSP_QUE_UPDATE 0x13 1113 #define INTR_RSP_QUE_UPDATE_83XX 0x14 1114 #define INTR_ATIO_QUE_UPDATE 0x1C 1115 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 1116 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 1117 1118 /* ISP mailbox loopback echo diagnostic error code */ 1119 #define MBS_LB_RESET 0x17 1120 /* 1121 * Firmware options 1, 2, 3. 1122 */ 1123 #define FO1_AE_ON_LIPF8 BIT_0 1124 #define FO1_AE_ALL_LIP_RESET BIT_1 1125 #define FO1_CTIO_RETRY BIT_3 1126 #define FO1_DISABLE_LIP_F7_SW BIT_4 1127 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 1128 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 1129 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 1130 #define FO1_SET_EMPHASIS_SWING BIT_8 1131 #define FO1_AE_AUTO_BYPASS BIT_9 1132 #define FO1_ENABLE_PURE_IOCB BIT_10 1133 #define FO1_AE_PLOGI_RJT BIT_11 1134 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 1135 #define FO1_AE_QUEUE_FULL BIT_13 1136 1137 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 1138 #define FO2_REV_LOOPBACK BIT_1 1139 1140 #define FO3_ENABLE_EMERG_IOCB BIT_0 1141 #define FO3_AE_RND_ERROR BIT_1 1142 1143 /* 24XX additional firmware options */ 1144 #define ADD_FO_COUNT 3 1145 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 1146 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 1147 1148 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 1149 1150 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 1151 1152 /* 1153 * ISP mailbox commands 1154 */ 1155 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1156 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1157 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 1158 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 1159 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1160 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 1161 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 1162 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 1163 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */ 1164 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 1165 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 1166 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 1167 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 1168 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 1169 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 1170 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 1171 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 1172 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1173 #define MBC_RESET 0x18 /* Reset. */ 1174 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1175 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1176 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1177 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1178 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1179 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1180 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1181 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1182 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */ 1183 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1184 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1185 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1186 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1187 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1188 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1189 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1190 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1191 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1192 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1193 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1194 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1195 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1196 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1197 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1198 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1199 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1200 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1201 /* Initialization Procedure */ 1202 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1203 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1204 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1205 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1206 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1207 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1208 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1209 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1210 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1211 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1212 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1213 /* commandd. */ 1214 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1215 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1216 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1217 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1218 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1219 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1220 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1221 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1222 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1223 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1224 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1225 1226 /* 1227 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1228 * should be defined with MBC_MR_* 1229 */ 1230 #define MBC_MR_DRV_SHUTDOWN 0x6A 1231 1232 /* 1233 * ISP24xx mailbox commands 1234 */ 1235 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1236 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1237 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1238 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1239 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1240 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1241 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1242 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1243 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1244 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1245 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1246 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1247 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1248 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1249 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1250 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1251 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1252 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1253 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1254 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1255 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1256 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1257 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1258 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1259 1260 /* 1261 * ISP81xx mailbox commands 1262 */ 1263 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1264 1265 /* 1266 * ISP8044 mailbox commands 1267 */ 1268 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1269 #define HCS_WRITE_SERDES 0x3 1270 #define HCS_READ_SERDES 0x4 1271 1272 /* Firmware return data sizes */ 1273 #define FCAL_MAP_SIZE 128 1274 1275 /* Mailbox bit definitions for out_mb and in_mb */ 1276 #define MBX_31 BIT_31 1277 #define MBX_30 BIT_30 1278 #define MBX_29 BIT_29 1279 #define MBX_28 BIT_28 1280 #define MBX_27 BIT_27 1281 #define MBX_26 BIT_26 1282 #define MBX_25 BIT_25 1283 #define MBX_24 BIT_24 1284 #define MBX_23 BIT_23 1285 #define MBX_22 BIT_22 1286 #define MBX_21 BIT_21 1287 #define MBX_20 BIT_20 1288 #define MBX_19 BIT_19 1289 #define MBX_18 BIT_18 1290 #define MBX_17 BIT_17 1291 #define MBX_16 BIT_16 1292 #define MBX_15 BIT_15 1293 #define MBX_14 BIT_14 1294 #define MBX_13 BIT_13 1295 #define MBX_12 BIT_12 1296 #define MBX_11 BIT_11 1297 #define MBX_10 BIT_10 1298 #define MBX_9 BIT_9 1299 #define MBX_8 BIT_8 1300 #define MBX_7 BIT_7 1301 #define MBX_6 BIT_6 1302 #define MBX_5 BIT_5 1303 #define MBX_4 BIT_4 1304 #define MBX_3 BIT_3 1305 #define MBX_2 BIT_2 1306 #define MBX_1 BIT_1 1307 #define MBX_0 BIT_0 1308 1309 #define RNID_TYPE_ELS_CMD 0x5 1310 #define RNID_TYPE_PORT_LOGIN 0x7 1311 #define RNID_BUFFER_CREDITS 0x8 1312 #define RNID_TYPE_SET_VERSION 0x9 1313 #define RNID_TYPE_ASIC_TEMP 0xC 1314 1315 #define ELS_CMD_MAP_SIZE 32 1316 1317 /* 1318 * Firmware state codes from get firmware state mailbox command 1319 */ 1320 #define FSTATE_CONFIG_WAIT 0 1321 #define FSTATE_WAIT_AL_PA 1 1322 #define FSTATE_WAIT_LOGIN 2 1323 #define FSTATE_READY 3 1324 #define FSTATE_LOSS_OF_SYNC 4 1325 #define FSTATE_ERROR 5 1326 #define FSTATE_REINIT 6 1327 #define FSTATE_NON_PART 7 1328 1329 #define FSTATE_CONFIG_CORRECT 0 1330 #define FSTATE_P2P_RCV_LIP 1 1331 #define FSTATE_P2P_CHOOSE_LOOP 2 1332 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1333 #define FSTATE_FATAL_ERROR 4 1334 #define FSTATE_LOOP_BACK_CONN 5 1335 1336 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1337 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1338 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1339 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1340 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1341 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED 1342 #define QLA27XX_DEFAULT_IMAGE 0 1343 #define QLA27XX_PRIMARY_IMAGE 1 1344 #define QLA27XX_SECONDARY_IMAGE 2 1345 1346 /* 1347 * Port Database structure definition 1348 * Little endian except where noted. 1349 */ 1350 #define PORT_DATABASE_SIZE 128 /* bytes */ 1351 typedef struct { 1352 uint8_t options; 1353 uint8_t control; 1354 uint8_t master_state; 1355 uint8_t slave_state; 1356 uint8_t reserved[2]; 1357 uint8_t hard_address; 1358 uint8_t reserved_1; 1359 uint8_t port_id[4]; 1360 uint8_t node_name[WWN_SIZE]; 1361 uint8_t port_name[WWN_SIZE]; 1362 __le16 execution_throttle; 1363 uint16_t execution_count; 1364 uint8_t reset_count; 1365 uint8_t reserved_2; 1366 uint16_t resource_allocation; 1367 uint16_t current_allocation; 1368 uint16_t queue_head; 1369 uint16_t queue_tail; 1370 uint16_t transmit_execution_list_next; 1371 uint16_t transmit_execution_list_previous; 1372 uint16_t common_features; 1373 uint16_t total_concurrent_sequences; 1374 uint16_t RO_by_information_category; 1375 uint8_t recipient; 1376 uint8_t initiator; 1377 uint16_t receive_data_size; 1378 uint16_t concurrent_sequences; 1379 uint16_t open_sequences_per_exchange; 1380 uint16_t lun_abort_flags; 1381 uint16_t lun_stop_flags; 1382 uint16_t stop_queue_head; 1383 uint16_t stop_queue_tail; 1384 uint16_t port_retry_timer; 1385 uint16_t next_sequence_id; 1386 uint16_t frame_count; 1387 uint16_t PRLI_payload_length; 1388 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1389 /* Bits 15-0 of word 0 */ 1390 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1391 /* Bits 15-0 of word 3 */ 1392 uint16_t loop_id; 1393 uint16_t extended_lun_info_list_pointer; 1394 uint16_t extended_lun_stop_list_pointer; 1395 } port_database_t; 1396 1397 /* 1398 * Port database slave/master states 1399 */ 1400 #define PD_STATE_DISCOVERY 0 1401 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1402 #define PD_STATE_PORT_LOGIN 2 1403 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1404 #define PD_STATE_PROCESS_LOGIN 4 1405 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1406 #define PD_STATE_PORT_LOGGED_IN 6 1407 #define PD_STATE_PORT_UNAVAILABLE 7 1408 #define PD_STATE_PROCESS_LOGOUT 8 1409 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1410 #define PD_STATE_PORT_LOGOUT 10 1411 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1412 1413 1414 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1415 #define QLA_ZIO_DISABLED 0 1416 #define QLA_ZIO_DEFAULT_TIMER 2 1417 1418 /* 1419 * ISP Initialization Control Block. 1420 * Little endian except where noted. 1421 */ 1422 #define ICB_VERSION 1 1423 typedef struct { 1424 uint8_t version; 1425 uint8_t reserved_1; 1426 1427 /* 1428 * LSB BIT 0 = Enable Hard Loop Id 1429 * LSB BIT 1 = Enable Fairness 1430 * LSB BIT 2 = Enable Full-Duplex 1431 * LSB BIT 3 = Enable Fast Posting 1432 * LSB BIT 4 = Enable Target Mode 1433 * LSB BIT 5 = Disable Initiator Mode 1434 * LSB BIT 6 = Enable ADISC 1435 * LSB BIT 7 = Enable Target Inquiry Data 1436 * 1437 * MSB BIT 0 = Enable PDBC Notify 1438 * MSB BIT 1 = Non Participating LIP 1439 * MSB BIT 2 = Descending Loop ID Search 1440 * MSB BIT 3 = Acquire Loop ID in LIPA 1441 * MSB BIT 4 = Stop PortQ on Full Status 1442 * MSB BIT 5 = Full Login after LIP 1443 * MSB BIT 6 = Node Name Option 1444 * MSB BIT 7 = Ext IFWCB enable bit 1445 */ 1446 uint8_t firmware_options[2]; 1447 1448 __le16 frame_payload_size; 1449 __le16 max_iocb_allocation; 1450 __le16 execution_throttle; 1451 uint8_t retry_count; 1452 uint8_t retry_delay; /* unused */ 1453 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1454 uint16_t hard_address; 1455 uint8_t inquiry_data; 1456 uint8_t login_timeout; 1457 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1458 1459 __le16 request_q_outpointer; 1460 __le16 response_q_inpointer; 1461 __le16 request_q_length; 1462 __le16 response_q_length; 1463 __le64 request_q_address __packed; 1464 __le64 response_q_address __packed; 1465 1466 __le16 lun_enables; 1467 uint8_t command_resource_count; 1468 uint8_t immediate_notify_resource_count; 1469 __le16 timeout; 1470 uint8_t reserved_2[2]; 1471 1472 /* 1473 * LSB BIT 0 = Timer Operation mode bit 0 1474 * LSB BIT 1 = Timer Operation mode bit 1 1475 * LSB BIT 2 = Timer Operation mode bit 2 1476 * LSB BIT 3 = Timer Operation mode bit 3 1477 * LSB BIT 4 = Init Config Mode bit 0 1478 * LSB BIT 5 = Init Config Mode bit 1 1479 * LSB BIT 6 = Init Config Mode bit 2 1480 * LSB BIT 7 = Enable Non part on LIHA failure 1481 * 1482 * MSB BIT 0 = Enable class 2 1483 * MSB BIT 1 = Enable ACK0 1484 * MSB BIT 2 = 1485 * MSB BIT 3 = 1486 * MSB BIT 4 = FC Tape Enable 1487 * MSB BIT 5 = Enable FC Confirm 1488 * MSB BIT 6 = Enable command queuing in target mode 1489 * MSB BIT 7 = No Logo On Link Down 1490 */ 1491 uint8_t add_firmware_options[2]; 1492 1493 uint8_t response_accumulation_timer; 1494 uint8_t interrupt_delay_timer; 1495 1496 /* 1497 * LSB BIT 0 = Enable Read xfr_rdy 1498 * LSB BIT 1 = Soft ID only 1499 * LSB BIT 2 = 1500 * LSB BIT 3 = 1501 * LSB BIT 4 = FCP RSP Payload [0] 1502 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1503 * LSB BIT 6 = Enable Out-of-Order frame handling 1504 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1505 * 1506 * MSB BIT 0 = Sbus enable - 2300 1507 * MSB BIT 1 = 1508 * MSB BIT 2 = 1509 * MSB BIT 3 = 1510 * MSB BIT 4 = LED mode 1511 * MSB BIT 5 = enable 50 ohm termination 1512 * MSB BIT 6 = Data Rate (2300 only) 1513 * MSB BIT 7 = Data Rate (2300 only) 1514 */ 1515 uint8_t special_options[2]; 1516 1517 uint8_t reserved_3[26]; 1518 } init_cb_t; 1519 1520 /* Special Features Control Block */ 1521 struct init_sf_cb { 1522 uint8_t format; 1523 uint8_t reserved0; 1524 /* 1525 * BIT 15-14 = Reserved 1526 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled) 1527 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled) 1528 * BIT 11-0 = Reserved 1529 */ 1530 uint16_t flags; 1531 uint8_t reserved1[32]; 1532 uint16_t discard_OHRB_timeout_value; 1533 uint16_t remote_write_opt_queue_num; 1534 uint8_t reserved2[40]; 1535 uint8_t scm_related_parameter[16]; 1536 uint8_t reserved3[32]; 1537 }; 1538 1539 /* 1540 * Get Link Status mailbox command return buffer. 1541 */ 1542 #define GLSO_SEND_RPS BIT_0 1543 #define GLSO_USE_DID BIT_3 1544 1545 struct link_statistics { 1546 __le32 link_fail_cnt; 1547 __le32 loss_sync_cnt; 1548 __le32 loss_sig_cnt; 1549 __le32 prim_seq_err_cnt; 1550 __le32 inval_xmit_word_cnt; 1551 __le32 inval_crc_cnt; 1552 __le32 lip_cnt; 1553 __le32 link_up_cnt; 1554 __le32 link_down_loop_init_tmo; 1555 __le32 link_down_los; 1556 __le32 link_down_loss_rcv_clk; 1557 uint32_t reserved0[5]; 1558 __le32 port_cfg_chg; 1559 uint32_t reserved1[11]; 1560 __le32 rsp_q_full; 1561 __le32 atio_q_full; 1562 __le32 drop_ae; 1563 __le32 els_proto_err; 1564 __le32 reserved2; 1565 __le32 tx_frames; 1566 __le32 rx_frames; 1567 __le32 discarded_frames; 1568 __le32 dropped_frames; 1569 uint32_t reserved3; 1570 __le32 nos_rcvd; 1571 uint32_t reserved4[4]; 1572 __le32 tx_prjt; 1573 __le32 rcv_exfail; 1574 __le32 rcv_abts; 1575 __le32 seq_frm_miss; 1576 __le32 corr_err; 1577 __le32 mb_rqst; 1578 __le32 nport_full; 1579 __le32 eofa; 1580 uint32_t reserved5; 1581 __le64 fpm_recv_word_cnt; 1582 __le64 fpm_disc_word_cnt; 1583 __le64 fpm_xmit_word_cnt; 1584 uint32_t reserved6[70]; 1585 }; 1586 1587 /* 1588 * NVRAM Command values. 1589 */ 1590 #define NV_START_BIT BIT_2 1591 #define NV_WRITE_OP (BIT_26+BIT_24) 1592 #define NV_READ_OP (BIT_26+BIT_25) 1593 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1594 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1595 #define NV_DELAY_COUNT 10 1596 1597 /* 1598 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1599 */ 1600 typedef struct { 1601 /* 1602 * NVRAM header 1603 */ 1604 uint8_t id[4]; 1605 uint8_t nvram_version; 1606 uint8_t reserved_0; 1607 1608 /* 1609 * NVRAM RISC parameter block 1610 */ 1611 uint8_t parameter_block_version; 1612 uint8_t reserved_1; 1613 1614 /* 1615 * LSB BIT 0 = Enable Hard Loop Id 1616 * LSB BIT 1 = Enable Fairness 1617 * LSB BIT 2 = Enable Full-Duplex 1618 * LSB BIT 3 = Enable Fast Posting 1619 * LSB BIT 4 = Enable Target Mode 1620 * LSB BIT 5 = Disable Initiator Mode 1621 * LSB BIT 6 = Enable ADISC 1622 * LSB BIT 7 = Enable Target Inquiry Data 1623 * 1624 * MSB BIT 0 = Enable PDBC Notify 1625 * MSB BIT 1 = Non Participating LIP 1626 * MSB BIT 2 = Descending Loop ID Search 1627 * MSB BIT 3 = Acquire Loop ID in LIPA 1628 * MSB BIT 4 = Stop PortQ on Full Status 1629 * MSB BIT 5 = Full Login after LIP 1630 * MSB BIT 6 = Node Name Option 1631 * MSB BIT 7 = Ext IFWCB enable bit 1632 */ 1633 uint8_t firmware_options[2]; 1634 1635 __le16 frame_payload_size; 1636 __le16 max_iocb_allocation; 1637 __le16 execution_throttle; 1638 uint8_t retry_count; 1639 uint8_t retry_delay; /* unused */ 1640 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1641 uint16_t hard_address; 1642 uint8_t inquiry_data; 1643 uint8_t login_timeout; 1644 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1645 1646 /* 1647 * LSB BIT 0 = Timer Operation mode bit 0 1648 * LSB BIT 1 = Timer Operation mode bit 1 1649 * LSB BIT 2 = Timer Operation mode bit 2 1650 * LSB BIT 3 = Timer Operation mode bit 3 1651 * LSB BIT 4 = Init Config Mode bit 0 1652 * LSB BIT 5 = Init Config Mode bit 1 1653 * LSB BIT 6 = Init Config Mode bit 2 1654 * LSB BIT 7 = Enable Non part on LIHA failure 1655 * 1656 * MSB BIT 0 = Enable class 2 1657 * MSB BIT 1 = Enable ACK0 1658 * MSB BIT 2 = 1659 * MSB BIT 3 = 1660 * MSB BIT 4 = FC Tape Enable 1661 * MSB BIT 5 = Enable FC Confirm 1662 * MSB BIT 6 = Enable command queuing in target mode 1663 * MSB BIT 7 = No Logo On Link Down 1664 */ 1665 uint8_t add_firmware_options[2]; 1666 1667 uint8_t response_accumulation_timer; 1668 uint8_t interrupt_delay_timer; 1669 1670 /* 1671 * LSB BIT 0 = Enable Read xfr_rdy 1672 * LSB BIT 1 = Soft ID only 1673 * LSB BIT 2 = 1674 * LSB BIT 3 = 1675 * LSB BIT 4 = FCP RSP Payload [0] 1676 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1677 * LSB BIT 6 = Enable Out-of-Order frame handling 1678 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1679 * 1680 * MSB BIT 0 = Sbus enable - 2300 1681 * MSB BIT 1 = 1682 * MSB BIT 2 = 1683 * MSB BIT 3 = 1684 * MSB BIT 4 = LED mode 1685 * MSB BIT 5 = enable 50 ohm termination 1686 * MSB BIT 6 = Data Rate (2300 only) 1687 * MSB BIT 7 = Data Rate (2300 only) 1688 */ 1689 uint8_t special_options[2]; 1690 1691 /* Reserved for expanded RISC parameter block */ 1692 uint8_t reserved_2[22]; 1693 1694 /* 1695 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1696 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1697 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1698 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1699 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1700 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1701 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1702 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1703 * 1704 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1705 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1706 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1707 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1708 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1709 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1710 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1711 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1712 * 1713 * LSB BIT 0 = Output Swing 1G bit 0 1714 * LSB BIT 1 = Output Swing 1G bit 1 1715 * LSB BIT 2 = Output Swing 1G bit 2 1716 * LSB BIT 3 = Output Emphasis 1G bit 0 1717 * LSB BIT 4 = Output Emphasis 1G bit 1 1718 * LSB BIT 5 = Output Swing 2G bit 0 1719 * LSB BIT 6 = Output Swing 2G bit 1 1720 * LSB BIT 7 = Output Swing 2G bit 2 1721 * 1722 * MSB BIT 0 = Output Emphasis 2G bit 0 1723 * MSB BIT 1 = Output Emphasis 2G bit 1 1724 * MSB BIT 2 = Output Enable 1725 * MSB BIT 3 = 1726 * MSB BIT 4 = 1727 * MSB BIT 5 = 1728 * MSB BIT 6 = 1729 * MSB BIT 7 = 1730 */ 1731 uint8_t seriallink_options[4]; 1732 1733 /* 1734 * NVRAM host parameter block 1735 * 1736 * LSB BIT 0 = Enable spinup delay 1737 * LSB BIT 1 = Disable BIOS 1738 * LSB BIT 2 = Enable Memory Map BIOS 1739 * LSB BIT 3 = Enable Selectable Boot 1740 * LSB BIT 4 = Disable RISC code load 1741 * LSB BIT 5 = Set cache line size 1 1742 * LSB BIT 6 = PCI Parity Disable 1743 * LSB BIT 7 = Enable extended logging 1744 * 1745 * MSB BIT 0 = Enable 64bit addressing 1746 * MSB BIT 1 = Enable lip reset 1747 * MSB BIT 2 = Enable lip full login 1748 * MSB BIT 3 = Enable target reset 1749 * MSB BIT 4 = Enable database storage 1750 * MSB BIT 5 = Enable cache flush read 1751 * MSB BIT 6 = Enable database load 1752 * MSB BIT 7 = Enable alternate WWN 1753 */ 1754 uint8_t host_p[2]; 1755 1756 uint8_t boot_node_name[WWN_SIZE]; 1757 uint8_t boot_lun_number; 1758 uint8_t reset_delay; 1759 uint8_t port_down_retry_count; 1760 uint8_t boot_id_number; 1761 __le16 max_luns_per_target; 1762 uint8_t fcode_boot_port_name[WWN_SIZE]; 1763 uint8_t alternate_port_name[WWN_SIZE]; 1764 uint8_t alternate_node_name[WWN_SIZE]; 1765 1766 /* 1767 * BIT 0 = Selective Login 1768 * BIT 1 = Alt-Boot Enable 1769 * BIT 2 = 1770 * BIT 3 = Boot Order List 1771 * BIT 4 = 1772 * BIT 5 = Selective LUN 1773 * BIT 6 = 1774 * BIT 7 = unused 1775 */ 1776 uint8_t efi_parameters; 1777 1778 uint8_t link_down_timeout; 1779 1780 uint8_t adapter_id[16]; 1781 1782 uint8_t alt1_boot_node_name[WWN_SIZE]; 1783 uint16_t alt1_boot_lun_number; 1784 uint8_t alt2_boot_node_name[WWN_SIZE]; 1785 uint16_t alt2_boot_lun_number; 1786 uint8_t alt3_boot_node_name[WWN_SIZE]; 1787 uint16_t alt3_boot_lun_number; 1788 uint8_t alt4_boot_node_name[WWN_SIZE]; 1789 uint16_t alt4_boot_lun_number; 1790 uint8_t alt5_boot_node_name[WWN_SIZE]; 1791 uint16_t alt5_boot_lun_number; 1792 uint8_t alt6_boot_node_name[WWN_SIZE]; 1793 uint16_t alt6_boot_lun_number; 1794 uint8_t alt7_boot_node_name[WWN_SIZE]; 1795 uint16_t alt7_boot_lun_number; 1796 1797 uint8_t reserved_3[2]; 1798 1799 /* Offset 200-215 : Model Number */ 1800 uint8_t model_number[16]; 1801 1802 /* OEM related items */ 1803 uint8_t oem_specific[16]; 1804 1805 /* 1806 * NVRAM Adapter Features offset 232-239 1807 * 1808 * LSB BIT 0 = External GBIC 1809 * LSB BIT 1 = Risc RAM parity 1810 * LSB BIT 2 = Buffer Plus Module 1811 * LSB BIT 3 = Multi Chip Adapter 1812 * LSB BIT 4 = Internal connector 1813 * LSB BIT 5 = 1814 * LSB BIT 6 = 1815 * LSB BIT 7 = 1816 * 1817 * MSB BIT 0 = 1818 * MSB BIT 1 = 1819 * MSB BIT 2 = 1820 * MSB BIT 3 = 1821 * MSB BIT 4 = 1822 * MSB BIT 5 = 1823 * MSB BIT 6 = 1824 * MSB BIT 7 = 1825 */ 1826 uint8_t adapter_features[2]; 1827 1828 uint8_t reserved_4[16]; 1829 1830 /* Subsystem vendor ID for ISP2200 */ 1831 uint16_t subsystem_vendor_id_2200; 1832 1833 /* Subsystem device ID for ISP2200 */ 1834 uint16_t subsystem_device_id_2200; 1835 1836 uint8_t reserved_5; 1837 uint8_t checksum; 1838 } nvram_t; 1839 1840 /* 1841 * ISP queue - response queue entry definition. 1842 */ 1843 typedef struct { 1844 uint8_t entry_type; /* Entry type. */ 1845 uint8_t entry_count; /* Entry count. */ 1846 uint8_t sys_define; /* System defined. */ 1847 uint8_t entry_status; /* Entry Status. */ 1848 uint32_t handle; /* System defined handle */ 1849 uint8_t data[52]; 1850 uint32_t signature; 1851 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1852 } response_t; 1853 1854 /* 1855 * ISP queue - ATIO queue entry definition. 1856 */ 1857 struct atio { 1858 uint8_t entry_type; /* Entry type. */ 1859 uint8_t entry_count; /* Entry count. */ 1860 __le16 attr_n_length; 1861 uint8_t data[56]; 1862 uint32_t signature; 1863 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1864 }; 1865 1866 typedef union { 1867 __le16 extended; 1868 struct { 1869 uint8_t reserved; 1870 uint8_t standard; 1871 } id; 1872 } target_id_t; 1873 1874 #define SET_TARGET_ID(ha, to, from) \ 1875 do { \ 1876 if (HAS_EXTENDED_IDS(ha)) \ 1877 to.extended = cpu_to_le16(from); \ 1878 else \ 1879 to.id.standard = (uint8_t)from; \ 1880 } while (0) 1881 1882 /* 1883 * ISP queue - command entry structure definition. 1884 */ 1885 #define COMMAND_TYPE 0x11 /* Command entry */ 1886 typedef struct { 1887 uint8_t entry_type; /* Entry type. */ 1888 uint8_t entry_count; /* Entry count. */ 1889 uint8_t sys_define; /* System defined. */ 1890 uint8_t entry_status; /* Entry Status. */ 1891 uint32_t handle; /* System handle. */ 1892 target_id_t target; /* SCSI ID */ 1893 __le16 lun; /* SCSI LUN */ 1894 __le16 control_flags; /* Control flags. */ 1895 #define CF_WRITE BIT_6 1896 #define CF_READ BIT_5 1897 #define CF_SIMPLE_TAG BIT_3 1898 #define CF_ORDERED_TAG BIT_2 1899 #define CF_HEAD_TAG BIT_1 1900 uint16_t reserved_1; 1901 __le16 timeout; /* Command timeout. */ 1902 __le16 dseg_count; /* Data segment count. */ 1903 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1904 __le32 byte_count; /* Total byte count. */ 1905 union { 1906 struct dsd32 dsd32[3]; 1907 struct dsd64 dsd64[2]; 1908 }; 1909 } cmd_entry_t; 1910 1911 /* 1912 * ISP queue - 64-Bit addressing, command entry structure definition. 1913 */ 1914 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1915 typedef struct { 1916 uint8_t entry_type; /* Entry type. */ 1917 uint8_t entry_count; /* Entry count. */ 1918 uint8_t sys_define; /* System defined. */ 1919 uint8_t entry_status; /* Entry Status. */ 1920 uint32_t handle; /* System handle. */ 1921 target_id_t target; /* SCSI ID */ 1922 __le16 lun; /* SCSI LUN */ 1923 __le16 control_flags; /* Control flags. */ 1924 uint16_t reserved_1; 1925 __le16 timeout; /* Command timeout. */ 1926 __le16 dseg_count; /* Data segment count. */ 1927 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1928 uint32_t byte_count; /* Total byte count. */ 1929 struct dsd64 dsd[2]; 1930 } cmd_a64_entry_t, request_t; 1931 1932 /* 1933 * ISP queue - continuation entry structure definition. 1934 */ 1935 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1936 typedef struct { 1937 uint8_t entry_type; /* Entry type. */ 1938 uint8_t entry_count; /* Entry count. */ 1939 uint8_t sys_define; /* System defined. */ 1940 uint8_t entry_status; /* Entry Status. */ 1941 uint32_t reserved; 1942 struct dsd32 dsd[7]; 1943 } cont_entry_t; 1944 1945 /* 1946 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1947 */ 1948 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1949 typedef struct { 1950 uint8_t entry_type; /* Entry type. */ 1951 uint8_t entry_count; /* Entry count. */ 1952 uint8_t sys_define; /* System defined. */ 1953 uint8_t entry_status; /* Entry Status. */ 1954 struct dsd64 dsd[5]; 1955 } cont_a64_entry_t; 1956 1957 #define PO_MODE_DIF_INSERT 0 1958 #define PO_MODE_DIF_REMOVE 1 1959 #define PO_MODE_DIF_PASS 2 1960 #define PO_MODE_DIF_REPLACE 3 1961 #define PO_MODE_DIF_TCP_CKSUM 6 1962 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1963 #define PO_DISABLE_GUARD_CHECK BIT_4 1964 #define PO_DISABLE_INCR_REF_TAG BIT_5 1965 #define PO_DIS_HEADER_MODE BIT_7 1966 #define PO_ENABLE_DIF_BUNDLING BIT_8 1967 #define PO_DIS_FRAME_MODE BIT_9 1968 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1969 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1970 1971 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1972 #define PO_DIS_REF_TAG_REPL BIT_13 1973 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1974 #define PO_DIS_REF_TAG_VALD BIT_15 1975 1976 /* 1977 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1978 */ 1979 struct crc_context { 1980 uint32_t handle; /* System handle. */ 1981 __le32 ref_tag; 1982 __le16 app_tag; 1983 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1984 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1985 __le16 guard_seed; /* Initial Guard Seed */ 1986 __le16 prot_opts; /* Requested Data Protection Mode */ 1987 __le16 blk_size; /* Data size in bytes */ 1988 __le16 runt_blk_guard; /* Guard value for runt block (tape 1989 * only) */ 1990 __le32 byte_count; /* Total byte count/ total data 1991 * transfer count */ 1992 union { 1993 struct { 1994 uint32_t reserved_1; 1995 uint16_t reserved_2; 1996 uint16_t reserved_3; 1997 uint32_t reserved_4; 1998 struct dsd64 data_dsd[1]; 1999 uint32_t reserved_5[2]; 2000 uint32_t reserved_6; 2001 } nobundling; 2002 struct { 2003 __le32 dif_byte_count; /* Total DIF byte 2004 * count */ 2005 uint16_t reserved_1; 2006 __le16 dseg_count; /* Data segment count */ 2007 uint32_t reserved_2; 2008 struct dsd64 data_dsd[1]; 2009 struct dsd64 dif_dsd; 2010 } bundling; 2011 } u; 2012 2013 struct fcp_cmnd fcp_cmnd; 2014 dma_addr_t crc_ctx_dma; 2015 /* List of DMA context transfers */ 2016 struct list_head dsd_list; 2017 2018 /* List of DIF Bundling context DMA address */ 2019 struct list_head ldif_dsd_list; 2020 u8 no_ldif_dsd; 2021 2022 struct list_head ldif_dma_hndl_list; 2023 u32 dif_bundl_len; 2024 u8 no_dif_bundl; 2025 /* This structure should not exceed 512 bytes */ 2026 }; 2027 2028 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 2029 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 2030 2031 /* 2032 * ISP queue - status entry structure definition. 2033 */ 2034 #define STATUS_TYPE 0x03 /* Status entry. */ 2035 typedef struct { 2036 uint8_t entry_type; /* Entry type. */ 2037 uint8_t entry_count; /* Entry count. */ 2038 uint8_t sys_define; /* System defined. */ 2039 uint8_t entry_status; /* Entry Status. */ 2040 uint32_t handle; /* System handle. */ 2041 __le16 scsi_status; /* SCSI status. */ 2042 __le16 comp_status; /* Completion status. */ 2043 __le16 state_flags; /* State flags. */ 2044 __le16 status_flags; /* Status flags. */ 2045 __le16 rsp_info_len; /* Response Info Length. */ 2046 __le16 req_sense_length; /* Request sense data length. */ 2047 __le32 residual_length; /* Residual transfer length. */ 2048 uint8_t rsp_info[8]; /* FCP response information. */ 2049 uint8_t req_sense_data[32]; /* Request sense data. */ 2050 } sts_entry_t; 2051 2052 /* 2053 * Status entry entry status 2054 */ 2055 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 2056 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 2057 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 2058 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 2059 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 2060 #define RF_BUSY BIT_1 /* Busy */ 2061 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 2062 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 2063 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 2064 RF_INV_E_TYPE) 2065 2066 /* 2067 * Status entry SCSI status bit definitions. 2068 */ 2069 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 2070 #define SS_RESIDUAL_UNDER BIT_11 2071 #define SS_RESIDUAL_OVER BIT_10 2072 #define SS_SENSE_LEN_VALID BIT_9 2073 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 2074 #define SS_SCSI_STATUS_BYTE 0xff 2075 2076 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 2077 #define SS_BUSY_CONDITION BIT_3 2078 #define SS_CONDITION_MET BIT_2 2079 #define SS_CHECK_CONDITION BIT_1 2080 2081 /* 2082 * Status entry completion status 2083 */ 2084 #define CS_COMPLETE 0x0 /* No errors */ 2085 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 2086 #define CS_DMA 0x2 /* A DMA direction error. */ 2087 #define CS_TRANSPORT 0x3 /* Transport error. */ 2088 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 2089 #define CS_ABORTED 0x5 /* System aborted command. */ 2090 #define CS_TIMEOUT 0x6 /* Timeout error. */ 2091 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 2092 #define CS_DIF_ERROR 0xC /* DIF error detected */ 2093 2094 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 2095 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 2096 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 2097 /* (selection timeout) */ 2098 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 2099 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 2100 #define CS_PORT_BUSY 0x2B /* Port Busy */ 2101 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 2102 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 2103 failure */ 2104 #define CS_REJECT_RECEIVED 0x4E /* Reject received */ 2105 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 2106 #define CS_UNKNOWN 0x81 /* Driver defined */ 2107 #define CS_RETRY 0x82 /* Driver defined */ 2108 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 2109 2110 #define CS_BIDIR_RD_OVERRUN 0x700 2111 #define CS_BIDIR_RD_WR_OVERRUN 0x707 2112 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 2113 #define CS_BIDIR_RD_UNDERRUN 0x1500 2114 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 2115 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 2116 #define CS_BIDIR_DMA 0x200 2117 /* 2118 * Status entry status flags 2119 */ 2120 #define SF_ABTS_TERMINATED BIT_10 2121 #define SF_LOGOUT_SENT BIT_13 2122 2123 /* 2124 * ISP queue - status continuation entry structure definition. 2125 */ 2126 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 2127 typedef struct { 2128 uint8_t entry_type; /* Entry type. */ 2129 uint8_t entry_count; /* Entry count. */ 2130 uint8_t sys_define; /* System defined. */ 2131 uint8_t entry_status; /* Entry Status. */ 2132 uint8_t data[60]; /* data */ 2133 } sts_cont_entry_t; 2134 2135 /* 2136 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 2137 * structure definition. 2138 */ 2139 #define STATUS_TYPE_21 0x21 /* Status entry. */ 2140 typedef struct { 2141 uint8_t entry_type; /* Entry type. */ 2142 uint8_t entry_count; /* Entry count. */ 2143 uint8_t handle_count; /* Handle count. */ 2144 uint8_t entry_status; /* Entry Status. */ 2145 uint32_t handle[15]; /* System handles. */ 2146 } sts21_entry_t; 2147 2148 /* 2149 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 2150 * structure definition. 2151 */ 2152 #define STATUS_TYPE_22 0x22 /* Status entry. */ 2153 typedef struct { 2154 uint8_t entry_type; /* Entry type. */ 2155 uint8_t entry_count; /* Entry count. */ 2156 uint8_t handle_count; /* Handle count. */ 2157 uint8_t entry_status; /* Entry Status. */ 2158 uint16_t handle[30]; /* System handles. */ 2159 } sts22_entry_t; 2160 2161 /* 2162 * ISP queue - marker entry structure definition. 2163 */ 2164 #define MARKER_TYPE 0x04 /* Marker entry. */ 2165 typedef struct { 2166 uint8_t entry_type; /* Entry type. */ 2167 uint8_t entry_count; /* Entry count. */ 2168 uint8_t handle_count; /* Handle count. */ 2169 uint8_t entry_status; /* Entry Status. */ 2170 uint32_t sys_define_2; /* System defined. */ 2171 target_id_t target; /* SCSI ID */ 2172 uint8_t modifier; /* Modifier (7-0). */ 2173 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 2174 #define MK_SYNC_ID 1 /* Synchronize ID */ 2175 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2176 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2177 /* clear port changed, */ 2178 /* use sequence number. */ 2179 uint8_t reserved_1; 2180 __le16 sequence_number; /* Sequence number of event */ 2181 __le16 lun; /* SCSI LUN */ 2182 uint8_t reserved_2[48]; 2183 } mrk_entry_t; 2184 2185 /* 2186 * ISP queue - Management Server entry structure definition. 2187 */ 2188 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2189 typedef struct { 2190 uint8_t entry_type; /* Entry type. */ 2191 uint8_t entry_count; /* Entry count. */ 2192 uint8_t handle_count; /* Handle count. */ 2193 uint8_t entry_status; /* Entry Status. */ 2194 uint32_t handle1; /* System handle. */ 2195 target_id_t loop_id; 2196 __le16 status; 2197 __le16 control_flags; /* Control flags. */ 2198 uint16_t reserved2; 2199 __le16 timeout; 2200 __le16 cmd_dsd_count; 2201 __le16 total_dsd_count; 2202 uint8_t type; 2203 uint8_t r_ctl; 2204 __le16 rx_id; 2205 uint16_t reserved3; 2206 uint32_t handle2; 2207 __le32 rsp_bytecount; 2208 __le32 req_bytecount; 2209 struct dsd64 req_dsd; 2210 struct dsd64 rsp_dsd; 2211 } ms_iocb_entry_t; 2212 2213 #define SCM_EDC_ACC_RECEIVED BIT_6 2214 #define SCM_RDF_ACC_RECEIVED BIT_7 2215 2216 /* 2217 * ISP queue - Mailbox Command entry structure definition. 2218 */ 2219 #define MBX_IOCB_TYPE 0x39 2220 struct mbx_entry { 2221 uint8_t entry_type; 2222 uint8_t entry_count; 2223 uint8_t sys_define1; 2224 /* Use sys_define1 for source type */ 2225 #define SOURCE_SCSI 0x00 2226 #define SOURCE_IP 0x01 2227 #define SOURCE_VI 0x02 2228 #define SOURCE_SCTP 0x03 2229 #define SOURCE_MP 0x04 2230 #define SOURCE_MPIOCTL 0x05 2231 #define SOURCE_ASYNC_IOCB 0x07 2232 2233 uint8_t entry_status; 2234 2235 uint32_t handle; 2236 target_id_t loop_id; 2237 2238 __le16 status; 2239 __le16 state_flags; 2240 __le16 status_flags; 2241 2242 uint32_t sys_define2[2]; 2243 2244 __le16 mb0; 2245 __le16 mb1; 2246 __le16 mb2; 2247 __le16 mb3; 2248 __le16 mb6; 2249 __le16 mb7; 2250 __le16 mb9; 2251 __le16 mb10; 2252 uint32_t reserved_2[2]; 2253 uint8_t node_name[WWN_SIZE]; 2254 uint8_t port_name[WWN_SIZE]; 2255 }; 2256 2257 #ifndef IMMED_NOTIFY_TYPE 2258 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2259 /* 2260 * ISP queue - immediate notify entry structure definition. 2261 * This is sent by the ISP to the Target driver. 2262 * This IOCB would have report of events sent by the 2263 * initiator, that needs to be handled by the target 2264 * driver immediately. 2265 */ 2266 struct imm_ntfy_from_isp { 2267 uint8_t entry_type; /* Entry type. */ 2268 uint8_t entry_count; /* Entry count. */ 2269 uint8_t sys_define; /* System defined. */ 2270 uint8_t entry_status; /* Entry Status. */ 2271 union { 2272 struct { 2273 __le32 sys_define_2; /* System defined. */ 2274 target_id_t target; 2275 __le16 lun; 2276 uint8_t target_id; 2277 uint8_t reserved_1; 2278 __le16 status_modifier; 2279 __le16 status; 2280 __le16 task_flags; 2281 __le16 seq_id; 2282 __le16 srr_rx_id; 2283 __le32 srr_rel_offs; 2284 __le16 srr_ui; 2285 #define SRR_IU_DATA_IN 0x1 2286 #define SRR_IU_DATA_OUT 0x5 2287 #define SRR_IU_STATUS 0x7 2288 __le16 srr_ox_id; 2289 uint8_t reserved_2[28]; 2290 } isp2x; 2291 struct { 2292 uint32_t reserved; 2293 __le16 nport_handle; 2294 uint16_t reserved_2; 2295 __le16 flags; 2296 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2297 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2298 __le16 srr_rx_id; 2299 __le16 status; 2300 uint8_t status_subcode; 2301 uint8_t fw_handle; 2302 __le32 exchange_address; 2303 __le32 srr_rel_offs; 2304 __le16 srr_ui; 2305 __le16 srr_ox_id; 2306 union { 2307 struct { 2308 uint8_t node_name[8]; 2309 } plogi; /* PLOGI/ADISC/PDISC */ 2310 struct { 2311 /* PRLI word 3 bit 0-15 */ 2312 __le16 wd3_lo; 2313 uint8_t resv0[6]; 2314 } prli; 2315 struct { 2316 uint8_t port_id[3]; 2317 uint8_t resv1; 2318 __le16 nport_handle; 2319 uint16_t resv2; 2320 } req_els; 2321 } u; 2322 uint8_t port_name[8]; 2323 uint8_t resv3[3]; 2324 uint8_t vp_index; 2325 uint32_t reserved_5; 2326 uint8_t port_id[3]; 2327 uint8_t reserved_6; 2328 } isp24; 2329 } u; 2330 uint16_t reserved_7; 2331 __le16 ox_id; 2332 } __packed; 2333 #endif 2334 2335 /* 2336 * ISP request and response queue entry sizes 2337 */ 2338 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2339 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2340 2341 2342 2343 /* 2344 * Switch info gathering structure. 2345 */ 2346 typedef struct { 2347 port_id_t d_id; 2348 uint8_t node_name[WWN_SIZE]; 2349 uint8_t port_name[WWN_SIZE]; 2350 uint8_t fabric_port_name[WWN_SIZE]; 2351 uint16_t fp_speed; 2352 uint8_t fc4_type; 2353 uint8_t fc4_features; 2354 } sw_info_t; 2355 2356 /* FCP-4 types */ 2357 #define FC4_TYPE_FCP_SCSI 0x08 2358 #define FC4_TYPE_NVME 0x28 2359 #define FC4_TYPE_OTHER 0x0 2360 #define FC4_TYPE_UNKNOWN 0xff 2361 2362 /* mailbox command 4G & above */ 2363 struct mbx_24xx_entry { 2364 uint8_t entry_type; 2365 uint8_t entry_count; 2366 uint8_t sys_define1; 2367 uint8_t entry_status; 2368 uint32_t handle; 2369 uint16_t mb[28]; 2370 }; 2371 2372 #define IOCB_SIZE 64 2373 2374 /* 2375 * Fibre channel port type. 2376 */ 2377 typedef enum { 2378 FCT_UNKNOWN, 2379 FCT_RSCN, 2380 FCT_SWITCH, 2381 FCT_BROADCAST, 2382 FCT_INITIATOR, 2383 FCT_TARGET, 2384 FCT_NVME_INITIATOR = 0x10, 2385 FCT_NVME_TARGET = 0x20, 2386 FCT_NVME_DISCOVERY = 0x40, 2387 FCT_NVME = 0xf0, 2388 } fc_port_type_t; 2389 2390 enum qla_sess_deletion { 2391 QLA_SESS_DELETION_NONE = 0, 2392 QLA_SESS_DELETION_IN_PROGRESS, 2393 QLA_SESS_DELETED, 2394 }; 2395 2396 enum qlt_plogi_link_t { 2397 QLT_PLOGI_LINK_SAME_WWN, 2398 QLT_PLOGI_LINK_CONFLICT, 2399 QLT_PLOGI_LINK_MAX 2400 }; 2401 2402 struct qlt_plogi_ack_t { 2403 struct list_head list; 2404 struct imm_ntfy_from_isp iocb; 2405 port_id_t id; 2406 int ref_count; 2407 void *fcport; 2408 }; 2409 2410 struct ct_sns_desc { 2411 struct ct_sns_pkt *ct_sns; 2412 dma_addr_t ct_sns_dma; 2413 }; 2414 2415 enum discovery_state { 2416 DSC_DELETED, 2417 DSC_GNN_ID, 2418 DSC_GNL, 2419 DSC_LOGIN_PEND, 2420 DSC_LOGIN_FAILED, 2421 DSC_GPDB, 2422 DSC_UPD_FCPORT, 2423 DSC_LOGIN_COMPLETE, 2424 DSC_ADISC, 2425 DSC_DELETE_PEND, 2426 }; 2427 2428 enum login_state { /* FW control Target side */ 2429 DSC_LS_LLIOCB_SENT = 2, 2430 DSC_LS_PLOGI_PEND, 2431 DSC_LS_PLOGI_COMP, 2432 DSC_LS_PRLI_PEND, 2433 DSC_LS_PRLI_COMP, 2434 DSC_LS_PORT_UNAVAIL, 2435 DSC_LS_PRLO_PEND = 9, 2436 DSC_LS_LOGO_PEND, 2437 }; 2438 2439 enum rscn_addr_format { 2440 RSCN_PORT_ADDR, 2441 RSCN_AREA_ADDR, 2442 RSCN_DOM_ADDR, 2443 RSCN_FAB_ADDR, 2444 }; 2445 2446 /* 2447 * Fibre channel port structure. 2448 */ 2449 typedef struct fc_port { 2450 struct list_head list; 2451 struct scsi_qla_host *vha; 2452 2453 unsigned int conf_compl_supported:1; 2454 unsigned int deleted:2; 2455 unsigned int free_pending:1; 2456 unsigned int local:1; 2457 unsigned int logout_on_delete:1; 2458 unsigned int logo_ack_needed:1; 2459 unsigned int keep_nport_handle:1; 2460 unsigned int send_els_logo:1; 2461 unsigned int login_pause:1; 2462 unsigned int login_succ:1; 2463 unsigned int query:1; 2464 unsigned int id_changed:1; 2465 unsigned int scan_needed:1; 2466 unsigned int n2n_flag:1; 2467 unsigned int explicit_logout:1; 2468 unsigned int prli_pend_timer:1; 2469 uint8_t nvme_flag; 2470 2471 uint8_t node_name[WWN_SIZE]; 2472 uint8_t port_name[WWN_SIZE]; 2473 port_id_t d_id; 2474 uint16_t loop_id; 2475 uint16_t old_loop_id; 2476 2477 struct completion nvme_del_done; 2478 uint32_t nvme_prli_service_param; 2479 #define NVME_PRLI_SP_PI_CTRL BIT_9 2480 #define NVME_PRLI_SP_SLER BIT_8 2481 #define NVME_PRLI_SP_CONF BIT_7 2482 #define NVME_PRLI_SP_INITIATOR BIT_5 2483 #define NVME_PRLI_SP_TARGET BIT_4 2484 #define NVME_PRLI_SP_DISCOVERY BIT_3 2485 #define NVME_PRLI_SP_FIRST_BURST BIT_0 2486 2487 uint32_t nvme_first_burst_size; 2488 #define NVME_FLAG_REGISTERED 4 2489 #define NVME_FLAG_DELETING 2 2490 #define NVME_FLAG_RESETTING 1 2491 2492 struct fc_port *conflict; 2493 unsigned char logout_completed; 2494 int generation; 2495 2496 struct se_session *se_sess; 2497 struct list_head sess_cmd_list; 2498 spinlock_t sess_cmd_lock; 2499 struct kref sess_kref; 2500 struct qla_tgt *tgt; 2501 unsigned long expires; 2502 struct list_head del_list_entry; 2503 struct work_struct free_work; 2504 struct work_struct reg_work; 2505 uint64_t jiffies_at_registration; 2506 unsigned long prli_expired; 2507 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2508 2509 uint16_t tgt_id; 2510 uint16_t old_tgt_id; 2511 uint16_t sec_since_registration; 2512 2513 uint8_t fcp_prio; 2514 2515 uint8_t fabric_port_name[WWN_SIZE]; 2516 uint16_t fp_speed; 2517 2518 fc_port_type_t port_type; 2519 2520 atomic_t state; 2521 uint32_t flags; 2522 2523 int login_retry; 2524 2525 struct fc_rport *rport, *drport; 2526 u32 supported_classes; 2527 2528 uint8_t fc4_type; 2529 uint8_t fc4_features; 2530 uint8_t scan_state; 2531 2532 unsigned long last_queue_full; 2533 unsigned long last_ramp_up; 2534 2535 uint16_t port_id; 2536 2537 struct nvme_fc_remote_port *nvme_remote_port; 2538 2539 unsigned long retry_delay_timestamp; 2540 struct qla_tgt_sess *tgt_session; 2541 struct ct_sns_desc ct_desc; 2542 enum discovery_state disc_state; 2543 atomic_t shadow_disc_state; 2544 enum discovery_state next_disc_state; 2545 enum login_state fw_login_state; 2546 unsigned long dm_login_expire; 2547 unsigned long plogi_nack_done_deadline; 2548 2549 u32 login_gen, last_login_gen; 2550 u32 rscn_gen, last_rscn_gen; 2551 u32 chip_reset; 2552 struct list_head gnl_entry; 2553 struct work_struct del_work; 2554 u8 iocb[IOCB_SIZE]; 2555 u8 current_login_state; 2556 u8 last_login_state; 2557 u16 n2n_link_reset_cnt; 2558 u16 n2n_chip_reset; 2559 2560 struct dentry *dfs_rport_dir; 2561 2562 u64 tgt_short_link_down_cnt; 2563 u64 tgt_link_down_time; 2564 u64 dev_loss_tmo; 2565 } fc_port_t; 2566 2567 enum { 2568 FC4_PRIORITY_NVME = 1, 2569 FC4_PRIORITY_FCP = 2, 2570 }; 2571 2572 #define QLA_FCPORT_SCAN 1 2573 #define QLA_FCPORT_FOUND 2 2574 2575 struct event_arg { 2576 fc_port_t *fcport; 2577 srb_t *sp; 2578 port_id_t id; 2579 u16 data[2], rc; 2580 u8 port_name[WWN_SIZE]; 2581 u32 iop[2]; 2582 }; 2583 2584 #include "qla_mr.h" 2585 2586 /* 2587 * Fibre channel port/lun states. 2588 */ 2589 #define FCS_UNCONFIGURED 1 2590 #define FCS_DEVICE_DEAD 2 2591 #define FCS_DEVICE_LOST 3 2592 #define FCS_ONLINE 4 2593 2594 extern const char *const port_state_str[5]; 2595 2596 static const char * const port_dstate_str[] = { 2597 "DELETED", 2598 "GNN_ID", 2599 "GNL", 2600 "LOGIN_PEND", 2601 "LOGIN_FAILED", 2602 "GPDB", 2603 "UPD_FCPORT", 2604 "LOGIN_COMPLETE", 2605 "ADISC", 2606 "DELETE_PEND" 2607 }; 2608 2609 /* 2610 * FC port flags. 2611 */ 2612 #define FCF_FABRIC_DEVICE BIT_0 2613 #define FCF_LOGIN_NEEDED BIT_1 2614 #define FCF_FCP2_DEVICE BIT_2 2615 #define FCF_ASYNC_SENT BIT_3 2616 #define FCF_CONF_COMP_SUPPORTED BIT_4 2617 #define FCF_ASYNC_ACTIVE BIT_5 2618 2619 /* No loop ID flag. */ 2620 #define FC_NO_LOOP_ID 0x1000 2621 2622 /* 2623 * FC-CT interface 2624 * 2625 * NOTE: All structures are big-endian in form. 2626 */ 2627 2628 #define CT_REJECT_RESPONSE 0x8001 2629 #define CT_ACCEPT_RESPONSE 0x8002 2630 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2631 #define CT_REASON_CANNOT_PERFORM 0x09 2632 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2633 #define CT_EXPL_ALREADY_REGISTERED 0x10 2634 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2635 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2636 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2637 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2638 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2639 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2640 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2641 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2642 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2643 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2644 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2645 2646 #define NS_N_PORT_TYPE 0x01 2647 #define NS_NL_PORT_TYPE 0x02 2648 #define NS_NX_PORT_TYPE 0x7F 2649 2650 #define GA_NXT_CMD 0x100 2651 #define GA_NXT_REQ_SIZE (16 + 4) 2652 #define GA_NXT_RSP_SIZE (16 + 620) 2653 2654 #define GPN_FT_CMD 0x172 2655 #define GPN_FT_REQ_SIZE (16 + 4) 2656 #define GNN_FT_CMD 0x173 2657 #define GNN_FT_REQ_SIZE (16 + 4) 2658 2659 #define GID_PT_CMD 0x1A1 2660 #define GID_PT_REQ_SIZE (16 + 4) 2661 2662 #define GPN_ID_CMD 0x112 2663 #define GPN_ID_REQ_SIZE (16 + 4) 2664 #define GPN_ID_RSP_SIZE (16 + 8) 2665 2666 #define GNN_ID_CMD 0x113 2667 #define GNN_ID_REQ_SIZE (16 + 4) 2668 #define GNN_ID_RSP_SIZE (16 + 8) 2669 2670 #define GFT_ID_CMD 0x117 2671 #define GFT_ID_REQ_SIZE (16 + 4) 2672 #define GFT_ID_RSP_SIZE (16 + 32) 2673 2674 #define GID_PN_CMD 0x121 2675 #define GID_PN_REQ_SIZE (16 + 8) 2676 #define GID_PN_RSP_SIZE (16 + 4) 2677 2678 #define RFT_ID_CMD 0x217 2679 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2680 #define RFT_ID_RSP_SIZE 16 2681 2682 #define RFF_ID_CMD 0x21F 2683 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2684 #define RFF_ID_RSP_SIZE 16 2685 2686 #define RNN_ID_CMD 0x213 2687 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2688 #define RNN_ID_RSP_SIZE 16 2689 2690 #define RSNN_NN_CMD 0x239 2691 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2692 #define RSNN_NN_RSP_SIZE 16 2693 2694 #define GFPN_ID_CMD 0x11C 2695 #define GFPN_ID_REQ_SIZE (16 + 4) 2696 #define GFPN_ID_RSP_SIZE (16 + 8) 2697 2698 #define GPSC_CMD 0x127 2699 #define GPSC_REQ_SIZE (16 + 8) 2700 #define GPSC_RSP_SIZE (16 + 2 + 2) 2701 2702 #define GFF_ID_CMD 0x011F 2703 #define GFF_ID_REQ_SIZE (16 + 4) 2704 #define GFF_ID_RSP_SIZE (16 + 128) 2705 2706 /* 2707 * FDMI HBA attribute types. 2708 */ 2709 #define FDMI1_HBA_ATTR_COUNT 9 2710 #define FDMI2_HBA_ATTR_COUNT 17 2711 2712 #define FDMI_HBA_NODE_NAME 0x1 2713 #define FDMI_HBA_MANUFACTURER 0x2 2714 #define FDMI_HBA_SERIAL_NUMBER 0x3 2715 #define FDMI_HBA_MODEL 0x4 2716 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2717 #define FDMI_HBA_HARDWARE_VERSION 0x6 2718 #define FDMI_HBA_DRIVER_VERSION 0x7 2719 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2720 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2721 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2722 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2723 2724 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2725 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd 2726 #define FDMI_HBA_NUM_PORTS 0xe 2727 #define FDMI_HBA_FABRIC_NAME 0xf 2728 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2729 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0 2730 2731 struct ct_fdmi_hba_attr { 2732 __be16 type; 2733 __be16 len; 2734 union { 2735 uint8_t node_name[WWN_SIZE]; 2736 uint8_t manufacturer[64]; 2737 uint8_t serial_num[32]; 2738 uint8_t model[16+1]; 2739 uint8_t model_desc[80]; 2740 uint8_t hw_version[32]; 2741 uint8_t driver_version[32]; 2742 uint8_t orom_version[16]; 2743 uint8_t fw_version[32]; 2744 uint8_t os_version[128]; 2745 __be32 max_ct_len; 2746 2747 uint8_t sym_name[256]; 2748 __be32 vendor_specific_info; 2749 __be32 num_ports; 2750 uint8_t fabric_name[WWN_SIZE]; 2751 uint8_t bios_name[32]; 2752 uint8_t vendor_identifier[8]; 2753 } a; 2754 }; 2755 2756 struct ct_fdmi1_hba_attributes { 2757 __be32 count; 2758 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT]; 2759 }; 2760 2761 struct ct_fdmi2_hba_attributes { 2762 __be32 count; 2763 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT]; 2764 }; 2765 2766 /* 2767 * FDMI Port attribute types. 2768 */ 2769 #define FDMI1_PORT_ATTR_COUNT 6 2770 #define FDMI2_PORT_ATTR_COUNT 16 2771 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23 2772 2773 #define FDMI_PORT_FC4_TYPES 0x1 2774 #define FDMI_PORT_SUPPORT_SPEED 0x2 2775 #define FDMI_PORT_CURRENT_SPEED 0x3 2776 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2777 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2778 #define FDMI_PORT_HOST_NAME 0x6 2779 2780 #define FDMI_PORT_NODE_NAME 0x7 2781 #define FDMI_PORT_NAME 0x8 2782 #define FDMI_PORT_SYM_NAME 0x9 2783 #define FDMI_PORT_TYPE 0xa 2784 #define FDMI_PORT_SUPP_COS 0xb 2785 #define FDMI_PORT_FABRIC_NAME 0xc 2786 #define FDMI_PORT_FC4_TYPE 0xd 2787 #define FDMI_PORT_STATE 0x101 2788 #define FDMI_PORT_COUNT 0x102 2789 #define FDMI_PORT_IDENTIFIER 0x103 2790 2791 #define FDMI_SMARTSAN_SERVICE 0xF100 2792 #define FDMI_SMARTSAN_GUID 0xF101 2793 #define FDMI_SMARTSAN_VERSION 0xF102 2794 #define FDMI_SMARTSAN_PROD_NAME 0xF103 2795 #define FDMI_SMARTSAN_PORT_INFO 0xF104 2796 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105 2797 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106 2798 2799 #define FDMI_PORT_SPEED_1GB 0x1 2800 #define FDMI_PORT_SPEED_2GB 0x2 2801 #define FDMI_PORT_SPEED_10GB 0x4 2802 #define FDMI_PORT_SPEED_4GB 0x8 2803 #define FDMI_PORT_SPEED_8GB 0x10 2804 #define FDMI_PORT_SPEED_16GB 0x20 2805 #define FDMI_PORT_SPEED_32GB 0x40 2806 #define FDMI_PORT_SPEED_64GB 0x80 2807 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2808 2809 #define FC_CLASS_2 0x04 2810 #define FC_CLASS_3 0x08 2811 #define FC_CLASS_2_3 0x0C 2812 2813 struct ct_fdmi_port_attr { 2814 __be16 type; 2815 __be16 len; 2816 union { 2817 uint8_t fc4_types[32]; 2818 __be32 sup_speed; 2819 __be32 cur_speed; 2820 __be32 max_frame_size; 2821 uint8_t os_dev_name[32]; 2822 uint8_t host_name[256]; 2823 2824 uint8_t node_name[WWN_SIZE]; 2825 uint8_t port_name[WWN_SIZE]; 2826 uint8_t port_sym_name[128]; 2827 __be32 port_type; 2828 __be32 port_supported_cos; 2829 uint8_t fabric_name[WWN_SIZE]; 2830 uint8_t port_fc4_type[32]; 2831 __be32 port_state; 2832 __be32 num_ports; 2833 __be32 port_id; 2834 2835 uint8_t smartsan_service[24]; 2836 uint8_t smartsan_guid[16]; 2837 uint8_t smartsan_version[24]; 2838 uint8_t smartsan_prod_name[16]; 2839 __be32 smartsan_port_info; 2840 __be32 smartsan_qos_support; 2841 __be32 smartsan_security_support; 2842 } a; 2843 }; 2844 2845 struct ct_fdmi1_port_attributes { 2846 __be32 count; 2847 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT]; 2848 }; 2849 2850 struct ct_fdmi2_port_attributes { 2851 __be32 count; 2852 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT]; 2853 }; 2854 2855 #define FDMI_ATTR_TYPELEN(obj) \ 2856 (sizeof((obj)->type) + sizeof((obj)->len)) 2857 2858 #define FDMI_ATTR_ALIGNMENT(len) \ 2859 (4 - ((len) & 3)) 2860 2861 /* FDMI register call options */ 2862 #define CALLOPT_FDMI1 0 2863 #define CALLOPT_FDMI2 1 2864 #define CALLOPT_FDMI2_SMARTSAN 2 2865 2866 /* FDMI definitions. */ 2867 #define GRHL_CMD 0x100 2868 #define GHAT_CMD 0x101 2869 #define GRPL_CMD 0x102 2870 #define GPAT_CMD 0x110 2871 2872 #define RHBA_CMD 0x200 2873 #define RHBA_RSP_SIZE 16 2874 2875 #define RHAT_CMD 0x201 2876 2877 #define RPRT_CMD 0x210 2878 #define RPRT_RSP_SIZE 24 2879 2880 #define RPA_CMD 0x211 2881 #define RPA_RSP_SIZE 16 2882 #define SMARTSAN_RPA_RSP_SIZE 24 2883 2884 #define DHBA_CMD 0x300 2885 #define DHBA_REQ_SIZE (16 + 8) 2886 #define DHBA_RSP_SIZE 16 2887 2888 #define DHAT_CMD 0x301 2889 #define DPRT_CMD 0x310 2890 #define DPA_CMD 0x311 2891 2892 /* CT command header -- request/response common fields */ 2893 struct ct_cmd_hdr { 2894 uint8_t revision; 2895 uint8_t in_id[3]; 2896 uint8_t gs_type; 2897 uint8_t gs_subtype; 2898 uint8_t options; 2899 uint8_t reserved; 2900 }; 2901 2902 /* CT command request */ 2903 struct ct_sns_req { 2904 struct ct_cmd_hdr header; 2905 __be16 command; 2906 __be16 max_rsp_size; 2907 uint8_t fragment_id; 2908 uint8_t reserved[3]; 2909 2910 union { 2911 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2912 struct { 2913 uint8_t reserved; 2914 be_id_t port_id; 2915 } port_id; 2916 2917 struct { 2918 uint8_t reserved; 2919 uint8_t domain; 2920 uint8_t area; 2921 uint8_t port_type; 2922 } gpn_ft; 2923 2924 struct { 2925 uint8_t port_type; 2926 uint8_t domain; 2927 uint8_t area; 2928 uint8_t reserved; 2929 } gid_pt; 2930 2931 struct { 2932 uint8_t reserved; 2933 be_id_t port_id; 2934 uint8_t fc4_types[32]; 2935 } rft_id; 2936 2937 struct { 2938 uint8_t reserved; 2939 be_id_t port_id; 2940 uint16_t reserved2; 2941 uint8_t fc4_feature; 2942 uint8_t fc4_type; 2943 } rff_id; 2944 2945 struct { 2946 uint8_t reserved; 2947 be_id_t port_id; 2948 uint8_t node_name[8]; 2949 } rnn_id; 2950 2951 struct { 2952 uint8_t node_name[8]; 2953 uint8_t name_len; 2954 uint8_t sym_node_name[255]; 2955 } rsnn_nn; 2956 2957 struct { 2958 uint8_t hba_identifier[8]; 2959 } ghat; 2960 2961 struct { 2962 uint8_t hba_identifier[8]; 2963 __be32 entry_count; 2964 uint8_t port_name[8]; 2965 struct ct_fdmi2_hba_attributes attrs; 2966 } rhba; 2967 2968 struct { 2969 uint8_t hba_identifier[8]; 2970 struct ct_fdmi1_hba_attributes attrs; 2971 } rhat; 2972 2973 struct { 2974 uint8_t port_name[8]; 2975 struct ct_fdmi2_port_attributes attrs; 2976 } rpa; 2977 2978 struct { 2979 uint8_t hba_identifier[8]; 2980 uint8_t port_name[8]; 2981 struct ct_fdmi2_port_attributes attrs; 2982 } rprt; 2983 2984 struct { 2985 uint8_t port_name[8]; 2986 } dhba; 2987 2988 struct { 2989 uint8_t port_name[8]; 2990 } dhat; 2991 2992 struct { 2993 uint8_t port_name[8]; 2994 } dprt; 2995 2996 struct { 2997 uint8_t port_name[8]; 2998 } dpa; 2999 3000 struct { 3001 uint8_t port_name[8]; 3002 } gpsc; 3003 3004 struct { 3005 uint8_t reserved; 3006 uint8_t port_id[3]; 3007 } gff_id; 3008 3009 struct { 3010 uint8_t port_name[8]; 3011 } gid_pn; 3012 } req; 3013 }; 3014 3015 /* CT command response header */ 3016 struct ct_rsp_hdr { 3017 struct ct_cmd_hdr header; 3018 __be16 response; 3019 uint16_t residual; 3020 uint8_t fragment_id; 3021 uint8_t reason_code; 3022 uint8_t explanation_code; 3023 uint8_t vendor_unique; 3024 }; 3025 3026 struct ct_sns_gid_pt_data { 3027 uint8_t control_byte; 3028 be_id_t port_id; 3029 }; 3030 3031 /* It's the same for both GPN_FT and GNN_FT */ 3032 struct ct_sns_gpnft_rsp { 3033 struct { 3034 struct ct_cmd_hdr header; 3035 uint16_t response; 3036 uint16_t residual; 3037 uint8_t fragment_id; 3038 uint8_t reason_code; 3039 uint8_t explanation_code; 3040 uint8_t vendor_unique; 3041 }; 3042 /* Assume the largest number of targets for the union */ 3043 struct ct_sns_gpn_ft_data { 3044 u8 control_byte; 3045 u8 port_id[3]; 3046 u32 reserved; 3047 u8 port_name[8]; 3048 } entries[1]; 3049 }; 3050 3051 /* CT command response */ 3052 struct ct_sns_rsp { 3053 struct ct_rsp_hdr header; 3054 3055 union { 3056 struct { 3057 uint8_t port_type; 3058 be_id_t port_id; 3059 uint8_t port_name[8]; 3060 uint8_t sym_port_name_len; 3061 uint8_t sym_port_name[255]; 3062 uint8_t node_name[8]; 3063 uint8_t sym_node_name_len; 3064 uint8_t sym_node_name[255]; 3065 uint8_t init_proc_assoc[8]; 3066 uint8_t node_ip_addr[16]; 3067 uint8_t class_of_service[4]; 3068 uint8_t fc4_types[32]; 3069 uint8_t ip_address[16]; 3070 uint8_t fabric_port_name[8]; 3071 uint8_t reserved; 3072 uint8_t hard_address[3]; 3073 } ga_nxt; 3074 3075 struct { 3076 /* Assume the largest number of targets for the union */ 3077 struct ct_sns_gid_pt_data 3078 entries[MAX_FIBRE_DEVICES_MAX]; 3079 } gid_pt; 3080 3081 struct { 3082 uint8_t port_name[8]; 3083 } gpn_id; 3084 3085 struct { 3086 uint8_t node_name[8]; 3087 } gnn_id; 3088 3089 struct { 3090 uint8_t fc4_types[32]; 3091 } gft_id; 3092 3093 struct { 3094 uint32_t entry_count; 3095 uint8_t port_name[8]; 3096 struct ct_fdmi1_hba_attributes attrs; 3097 } ghat; 3098 3099 struct { 3100 uint8_t port_name[8]; 3101 } gfpn_id; 3102 3103 struct { 3104 __be16 speeds; 3105 __be16 speed; 3106 } gpsc; 3107 3108 #define GFF_FCP_SCSI_OFFSET 7 3109 #define GFF_NVME_OFFSET 23 /* type = 28h */ 3110 struct { 3111 uint8_t fc4_features[128]; 3112 } gff_id; 3113 struct { 3114 uint8_t reserved; 3115 uint8_t port_id[3]; 3116 } gid_pn; 3117 } rsp; 3118 }; 3119 3120 struct ct_sns_pkt { 3121 union { 3122 struct ct_sns_req req; 3123 struct ct_sns_rsp rsp; 3124 } p; 3125 }; 3126 3127 struct ct_sns_gpnft_pkt { 3128 union { 3129 struct ct_sns_req req; 3130 struct ct_sns_gpnft_rsp rsp; 3131 } p; 3132 }; 3133 3134 enum scan_flags_t { 3135 SF_SCANNING = BIT_0, 3136 SF_QUEUED = BIT_1, 3137 }; 3138 3139 enum fc4type_t { 3140 FS_FC4TYPE_FCP = BIT_0, 3141 FS_FC4TYPE_NVME = BIT_1, 3142 FS_FCP_IS_N2N = BIT_7, 3143 }; 3144 3145 struct fab_scan_rp { 3146 port_id_t id; 3147 enum fc4type_t fc4type; 3148 u8 port_name[8]; 3149 u8 node_name[8]; 3150 }; 3151 3152 struct fab_scan { 3153 struct fab_scan_rp *l; 3154 u32 size; 3155 u16 scan_retry; 3156 #define MAX_SCAN_RETRIES 5 3157 enum scan_flags_t scan_flags; 3158 struct delayed_work scan_work; 3159 }; 3160 3161 /* 3162 * SNS command structures -- for 2200 compatibility. 3163 */ 3164 #define RFT_ID_SNS_SCMD_LEN 22 3165 #define RFT_ID_SNS_CMD_SIZE 60 3166 #define RFT_ID_SNS_DATA_SIZE 16 3167 3168 #define RNN_ID_SNS_SCMD_LEN 10 3169 #define RNN_ID_SNS_CMD_SIZE 36 3170 #define RNN_ID_SNS_DATA_SIZE 16 3171 3172 #define GA_NXT_SNS_SCMD_LEN 6 3173 #define GA_NXT_SNS_CMD_SIZE 28 3174 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 3175 3176 #define GID_PT_SNS_SCMD_LEN 6 3177 #define GID_PT_SNS_CMD_SIZE 28 3178 /* 3179 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 3180 * adapters. 3181 */ 3182 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 3183 3184 #define GPN_ID_SNS_SCMD_LEN 6 3185 #define GPN_ID_SNS_CMD_SIZE 28 3186 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 3187 3188 #define GNN_ID_SNS_SCMD_LEN 6 3189 #define GNN_ID_SNS_CMD_SIZE 28 3190 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 3191 3192 struct sns_cmd_pkt { 3193 union { 3194 struct { 3195 __le16 buffer_length; 3196 __le16 reserved_1; 3197 __le64 buffer_address __packed; 3198 __le16 subcommand_length; 3199 __le16 reserved_2; 3200 __le16 subcommand; 3201 __le16 size; 3202 uint32_t reserved_3; 3203 uint8_t param[36]; 3204 } cmd; 3205 3206 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 3207 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 3208 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 3209 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 3210 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 3211 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 3212 } p; 3213 }; 3214 3215 struct fw_blob { 3216 char *name; 3217 uint32_t segs[4]; 3218 const struct firmware *fw; 3219 }; 3220 3221 /* Return data from MBC_GET_ID_LIST call. */ 3222 struct gid_list_info { 3223 uint8_t al_pa; 3224 uint8_t area; 3225 uint8_t domain; 3226 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 3227 __le16 loop_id; /* ISP23XX -- 6 bytes. */ 3228 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 3229 }; 3230 3231 /* NPIV */ 3232 typedef struct vport_info { 3233 uint8_t port_name[WWN_SIZE]; 3234 uint8_t node_name[WWN_SIZE]; 3235 int vp_id; 3236 uint16_t loop_id; 3237 unsigned long host_no; 3238 uint8_t port_id[3]; 3239 int loop_state; 3240 } vport_info_t; 3241 3242 typedef struct vport_params { 3243 uint8_t port_name[WWN_SIZE]; 3244 uint8_t node_name[WWN_SIZE]; 3245 uint32_t options; 3246 #define VP_OPTS_RETRY_ENABLE BIT_0 3247 #define VP_OPTS_VP_DISABLE BIT_1 3248 } vport_params_t; 3249 3250 /* NPIV - return codes of VP create and modify */ 3251 #define VP_RET_CODE_OK 0 3252 #define VP_RET_CODE_FATAL 1 3253 #define VP_RET_CODE_WRONG_ID 2 3254 #define VP_RET_CODE_WWPN 3 3255 #define VP_RET_CODE_RESOURCES 4 3256 #define VP_RET_CODE_NO_MEM 5 3257 #define VP_RET_CODE_NOT_FOUND 6 3258 3259 struct qla_hw_data; 3260 struct rsp_que; 3261 /* 3262 * ISP operations 3263 */ 3264 struct isp_operations { 3265 3266 int (*pci_config) (struct scsi_qla_host *); 3267 int (*reset_chip)(struct scsi_qla_host *); 3268 int (*chip_diag) (struct scsi_qla_host *); 3269 void (*config_rings) (struct scsi_qla_host *); 3270 int (*reset_adapter)(struct scsi_qla_host *); 3271 int (*nvram_config) (struct scsi_qla_host *); 3272 void (*update_fw_options) (struct scsi_qla_host *); 3273 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3274 3275 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t); 3276 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3277 3278 irq_handler_t intr_handler; 3279 void (*enable_intrs) (struct qla_hw_data *); 3280 void (*disable_intrs) (struct qla_hw_data *); 3281 3282 int (*abort_command) (srb_t *); 3283 int (*target_reset) (struct fc_port *, uint64_t, int); 3284 int (*lun_reset) (struct fc_port *, uint64_t, int); 3285 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3286 uint8_t, uint8_t, uint16_t *, uint8_t); 3287 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3288 uint8_t, uint8_t); 3289 3290 uint16_t (*calc_req_entries) (uint16_t); 3291 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3292 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3293 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3294 uint32_t); 3295 3296 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *, 3297 uint32_t, uint32_t); 3298 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t, 3299 uint32_t); 3300 3301 void (*fw_dump)(struct scsi_qla_host *vha); 3302 void (*mpi_fw_dump)(struct scsi_qla_host *, int); 3303 3304 /* Context: task, might sleep */ 3305 int (*beacon_on) (struct scsi_qla_host *); 3306 int (*beacon_off) (struct scsi_qla_host *); 3307 3308 void (*beacon_blink) (struct scsi_qla_host *); 3309 3310 void *(*read_optrom)(struct scsi_qla_host *, void *, 3311 uint32_t, uint32_t); 3312 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t, 3313 uint32_t); 3314 3315 int (*get_flash_version) (struct scsi_qla_host *, void *); 3316 int (*start_scsi) (srb_t *); 3317 int (*start_scsi_mq) (srb_t *); 3318 3319 /* Context: task, might sleep */ 3320 int (*abort_isp) (struct scsi_qla_host *); 3321 3322 int (*iospace_config)(struct qla_hw_data *); 3323 int (*initialize_adapter)(struct scsi_qla_host *); 3324 }; 3325 3326 /* MSI-X Support *************************************************************/ 3327 3328 #define QLA_MSIX_CHIP_REV_24XX 3 3329 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3330 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3331 3332 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3333 #define QLA_MSIX_RSP_Q 0x01 3334 #define QLA_ATIO_VECTOR 0x02 3335 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3336 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04 3337 3338 #define QLA_MIDX_DEFAULT 0 3339 #define QLA_MIDX_RSP_Q 1 3340 #define QLA_PCI_MSIX_CONTROL 0xa2 3341 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3342 3343 struct scsi_qla_host; 3344 3345 3346 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3347 3348 struct qla_msix_entry { 3349 int have_irq; 3350 int in_use; 3351 uint32_t vector; 3352 uint16_t entry; 3353 char name[30]; 3354 void *handle; 3355 int cpuid; 3356 }; 3357 3358 #define WATCH_INTERVAL 1 /* number of seconds */ 3359 3360 /* Work events. */ 3361 enum qla_work_type { 3362 QLA_EVT_AEN, 3363 QLA_EVT_IDC_ACK, 3364 QLA_EVT_ASYNC_LOGIN, 3365 QLA_EVT_ASYNC_LOGOUT, 3366 QLA_EVT_ASYNC_ADISC, 3367 QLA_EVT_UEVENT, 3368 QLA_EVT_AENFX, 3369 QLA_EVT_GPNID, 3370 QLA_EVT_UNMAP, 3371 QLA_EVT_NEW_SESS, 3372 QLA_EVT_GPDB, 3373 QLA_EVT_PRLI, 3374 QLA_EVT_GPSC, 3375 QLA_EVT_GNL, 3376 QLA_EVT_NACK, 3377 QLA_EVT_RELOGIN, 3378 QLA_EVT_ASYNC_PRLO, 3379 QLA_EVT_ASYNC_PRLO_DONE, 3380 QLA_EVT_GPNFT, 3381 QLA_EVT_GPNFT_DONE, 3382 QLA_EVT_GNNFT_DONE, 3383 QLA_EVT_GNNID, 3384 QLA_EVT_GFPNID, 3385 QLA_EVT_SP_RETRY, 3386 QLA_EVT_IIDMA, 3387 QLA_EVT_ELS_PLOGI, 3388 }; 3389 3390 3391 struct qla_work_evt { 3392 struct list_head list; 3393 enum qla_work_type type; 3394 u32 flags; 3395 #define QLA_EVT_FLAG_FREE 0x1 3396 3397 union { 3398 struct { 3399 enum fc_host_event_code code; 3400 u32 data; 3401 } aen; 3402 struct { 3403 #define QLA_IDC_ACK_REGS 7 3404 uint16_t mb[QLA_IDC_ACK_REGS]; 3405 } idc_ack; 3406 struct { 3407 struct fc_port *fcport; 3408 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3409 u16 data[2]; 3410 } logio; 3411 struct { 3412 u32 code; 3413 #define QLA_UEVENT_CODE_FW_DUMP 0 3414 } uevent; 3415 struct { 3416 uint32_t evtcode; 3417 uint32_t mbx[8]; 3418 uint32_t count; 3419 } aenfx; 3420 struct { 3421 srb_t *sp; 3422 } iosb; 3423 struct { 3424 port_id_t id; 3425 } gpnid; 3426 struct { 3427 port_id_t id; 3428 u8 port_name[8]; 3429 u8 node_name[8]; 3430 void *pla; 3431 u8 fc4_type; 3432 } new_sess; 3433 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */ 3434 fc_port_t *fcport; 3435 u8 opt; 3436 } fcport; 3437 struct { 3438 fc_port_t *fcport; 3439 u8 iocb[IOCB_SIZE]; 3440 int type; 3441 } nack; 3442 struct { 3443 u8 fc4_type; 3444 srb_t *sp; 3445 } gpnft; 3446 } u; 3447 }; 3448 3449 struct qla_chip_state_84xx { 3450 struct list_head list; 3451 struct kref kref; 3452 3453 void *bus; 3454 spinlock_t access_lock; 3455 struct mutex fw_update_mutex; 3456 uint32_t fw_update; 3457 uint32_t op_fw_version; 3458 uint32_t op_fw_size; 3459 uint32_t op_fw_seq_size; 3460 uint32_t diag_fw_version; 3461 uint32_t gold_fw_version; 3462 }; 3463 3464 struct qla_dif_statistics { 3465 uint64_t dif_input_bytes; 3466 uint64_t dif_output_bytes; 3467 uint64_t dif_input_requests; 3468 uint64_t dif_output_requests; 3469 uint32_t dif_guard_err; 3470 uint32_t dif_ref_tag_err; 3471 uint32_t dif_app_tag_err; 3472 }; 3473 3474 struct qla_statistics { 3475 uint32_t total_isp_aborts; 3476 uint64_t input_bytes; 3477 uint64_t output_bytes; 3478 uint64_t input_requests; 3479 uint64_t output_requests; 3480 uint32_t control_requests; 3481 3482 uint64_t jiffies_at_last_reset; 3483 uint32_t stat_max_pend_cmds; 3484 uint32_t stat_max_qfull_cmds_alloc; 3485 uint32_t stat_max_qfull_cmds_dropped; 3486 3487 struct qla_dif_statistics qla_dif_stats; 3488 }; 3489 3490 struct bidi_statistics { 3491 unsigned long long io_count; 3492 unsigned long long transfer_bytes; 3493 }; 3494 3495 struct qla_tc_param { 3496 struct scsi_qla_host *vha; 3497 uint32_t blk_sz; 3498 uint32_t bufflen; 3499 struct scatterlist *sg; 3500 struct scatterlist *prot_sg; 3501 struct crc_context *ctx; 3502 uint8_t *ctx_dsd_alloced; 3503 }; 3504 3505 /* Multi queue support */ 3506 #define MBC_INITIALIZE_MULTIQ 0x1f 3507 #define QLA_QUE_PAGE 0X1000 3508 #define QLA_MQ_SIZE 32 3509 #define QLA_MAX_QUEUES 256 3510 #define ISP_QUE_REG(ha, id) \ 3511 ((ha->mqenable || IS_QLA83XX(ha) || \ 3512 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \ 3513 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3514 ((void __iomem *)ha->iobase)) 3515 #define QLA_REQ_QUE_ID(tag) \ 3516 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3517 #define QLA_DEFAULT_QUE_QOS 5 3518 #define QLA_PRECONFIG_VPORTS 32 3519 #define QLA_MAX_VPORTS_QLA24XX 128 3520 #define QLA_MAX_VPORTS_QLA25XX 256 3521 3522 struct qla_tgt_counters { 3523 uint64_t qla_core_sbt_cmd; 3524 uint64_t core_qla_que_buf; 3525 uint64_t qla_core_ret_ctio; 3526 uint64_t core_qla_snd_status; 3527 uint64_t qla_core_ret_sta_ctio; 3528 uint64_t core_qla_free_cmd; 3529 uint64_t num_q_full_sent; 3530 uint64_t num_alloc_iocb_failed; 3531 uint64_t num_term_xchg_sent; 3532 }; 3533 3534 struct qla_counters { 3535 uint64_t input_bytes; 3536 uint64_t input_requests; 3537 uint64_t output_bytes; 3538 uint64_t output_requests; 3539 3540 }; 3541 3542 struct qla_qpair; 3543 3544 /* Response queue data structure */ 3545 struct rsp_que { 3546 dma_addr_t dma; 3547 response_t *ring; 3548 response_t *ring_ptr; 3549 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */ 3550 __le32 __iomem *rsp_q_out; 3551 uint16_t ring_index; 3552 uint16_t out_ptr; 3553 uint16_t *in_ptr; /* queue shadow in index */ 3554 uint16_t length; 3555 uint16_t options; 3556 uint16_t rid; 3557 uint16_t id; 3558 uint16_t vp_idx; 3559 struct qla_hw_data *hw; 3560 struct qla_msix_entry *msix; 3561 struct req_que *req; 3562 srb_t *status_srb; /* status continuation entry */ 3563 struct qla_qpair *qpair; 3564 3565 dma_addr_t dma_fx00; 3566 response_t *ring_fx00; 3567 uint16_t length_fx00; 3568 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3569 }; 3570 3571 /* Request queue data structure */ 3572 struct req_que { 3573 dma_addr_t dma; 3574 request_t *ring; 3575 request_t *ring_ptr; 3576 __le32 __iomem *req_q_in; /* FWI2-capable only. */ 3577 __le32 __iomem *req_q_out; 3578 uint16_t ring_index; 3579 uint16_t in_ptr; 3580 uint16_t *out_ptr; /* queue shadow out index */ 3581 uint16_t cnt; 3582 uint16_t length; 3583 uint16_t options; 3584 uint16_t rid; 3585 uint16_t id; 3586 uint16_t qos; 3587 uint16_t vp_idx; 3588 struct rsp_que *rsp; 3589 srb_t **outstanding_cmds; 3590 uint32_t current_outstanding_cmd; 3591 uint16_t num_outstanding_cmds; 3592 int max_q_depth; 3593 3594 dma_addr_t dma_fx00; 3595 request_t *ring_fx00; 3596 uint16_t length_fx00; 3597 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3598 }; 3599 3600 struct qla_fw_resources { 3601 u16 iocbs_total; 3602 u16 iocbs_limit; 3603 u16 iocbs_qp_limit; 3604 u16 iocbs_used; 3605 }; 3606 3607 #define QLA_IOCB_PCT_LIMIT 95 3608 3609 /*Queue pair data structure */ 3610 struct qla_qpair { 3611 spinlock_t qp_lock; 3612 atomic_t ref_count; 3613 uint32_t lun_cnt; 3614 /* 3615 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3616 * legacy code. For other Qpair(s), it will point at qp_lock. 3617 */ 3618 spinlock_t *qp_lock_ptr; 3619 struct scsi_qla_host *vha; 3620 u32 chip_reset; 3621 3622 /* distill these fields down to 'online=0/1' 3623 * ha->flags.eeh_busy 3624 * ha->flags.pci_channel_io_perm_failure 3625 * base_vha->loop_state 3626 */ 3627 uint32_t online:1; 3628 /* move vha->flags.difdix_supported here */ 3629 uint32_t difdix_supported:1; 3630 uint32_t delete_in_progress:1; 3631 uint32_t fw_started:1; 3632 uint32_t enable_class_2:1; 3633 uint32_t enable_explicit_conf:1; 3634 uint32_t use_shadow_reg:1; 3635 uint32_t rcv_intr:1; 3636 3637 uint16_t id; /* qp number used with FW */ 3638 uint16_t vp_idx; /* vport ID */ 3639 mempool_t *srb_mempool; 3640 3641 struct pci_dev *pdev; 3642 void (*reqq_start_iocbs)(struct qla_qpair *); 3643 3644 /* to do: New driver: move queues to here instead of pointers */ 3645 struct req_que *req; 3646 struct rsp_que *rsp; 3647 struct atio_que *atio; 3648 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3649 struct qla_hw_data *hw; 3650 struct work_struct q_work; 3651 struct qla_counters counters; 3652 3653 struct list_head qp_list_elem; /* vha->qp_list */ 3654 struct list_head hints_list; 3655 3656 uint16_t retry_term_cnt; 3657 __le32 retry_term_exchg_addr; 3658 uint64_t retry_term_jiff; 3659 struct qla_tgt_counters tgt_counters; 3660 uint16_t cpuid; 3661 struct qla_fw_resources fwres ____cacheline_aligned; 3662 }; 3663 3664 /* Place holder for FW buffer parameters */ 3665 struct qlfc_fw { 3666 void *fw_buf; 3667 dma_addr_t fw_dma; 3668 uint32_t len; 3669 }; 3670 3671 struct rdp_req_payload { 3672 uint32_t els_request; 3673 uint32_t desc_list_len; 3674 3675 /* NPIV descriptor */ 3676 struct { 3677 uint32_t desc_tag; 3678 uint32_t desc_len; 3679 uint8_t reserved; 3680 uint8_t nport_id[3]; 3681 } npiv_desc; 3682 }; 3683 3684 struct rdp_rsp_payload { 3685 struct { 3686 __be32 cmd; 3687 __be32 len; 3688 } hdr; 3689 3690 /* LS Request Info descriptor */ 3691 struct { 3692 __be32 desc_tag; 3693 __be32 desc_len; 3694 __be32 req_payload_word_0; 3695 } ls_req_info_desc; 3696 3697 /* LS Request Info descriptor */ 3698 struct { 3699 __be32 desc_tag; 3700 __be32 desc_len; 3701 __be32 req_payload_word_0; 3702 } ls_req_info_desc2; 3703 3704 /* SFP diagnostic param descriptor */ 3705 struct { 3706 __be32 desc_tag; 3707 __be32 desc_len; 3708 __be16 temperature; 3709 __be16 vcc; 3710 __be16 tx_bias; 3711 __be16 tx_power; 3712 __be16 rx_power; 3713 __be16 sfp_flags; 3714 } sfp_diag_desc; 3715 3716 /* Port Speed Descriptor */ 3717 struct { 3718 __be32 desc_tag; 3719 __be32 desc_len; 3720 __be16 speed_capab; 3721 __be16 operating_speed; 3722 } port_speed_desc; 3723 3724 /* Link Error Status Descriptor */ 3725 struct { 3726 __be32 desc_tag; 3727 __be32 desc_len; 3728 __be32 link_fail_cnt; 3729 __be32 loss_sync_cnt; 3730 __be32 loss_sig_cnt; 3731 __be32 prim_seq_err_cnt; 3732 __be32 inval_xmit_word_cnt; 3733 __be32 inval_crc_cnt; 3734 uint8_t pn_port_phy_type; 3735 uint8_t reserved[3]; 3736 } ls_err_desc; 3737 3738 /* Port name description with diag param */ 3739 struct { 3740 __be32 desc_tag; 3741 __be32 desc_len; 3742 uint8_t WWNN[WWN_SIZE]; 3743 uint8_t WWPN[WWN_SIZE]; 3744 } port_name_diag_desc; 3745 3746 /* Port Name desc for Direct attached Fx_Port or Nx_Port */ 3747 struct { 3748 __be32 desc_tag; 3749 __be32 desc_len; 3750 uint8_t WWNN[WWN_SIZE]; 3751 uint8_t WWPN[WWN_SIZE]; 3752 } port_name_direct_desc; 3753 3754 /* Buffer Credit descriptor */ 3755 struct { 3756 __be32 desc_tag; 3757 __be32 desc_len; 3758 __be32 fcport_b2b; 3759 __be32 attached_fcport_b2b; 3760 __be32 fcport_rtt; 3761 } buffer_credit_desc; 3762 3763 /* Optical Element Data Descriptor */ 3764 struct { 3765 __be32 desc_tag; 3766 __be32 desc_len; 3767 __be16 high_alarm; 3768 __be16 low_alarm; 3769 __be16 high_warn; 3770 __be16 low_warn; 3771 __be32 element_flags; 3772 } optical_elmt_desc[5]; 3773 3774 /* Optical Product Data Descriptor */ 3775 struct { 3776 __be32 desc_tag; 3777 __be32 desc_len; 3778 uint8_t vendor_name[16]; 3779 uint8_t part_number[16]; 3780 uint8_t serial_number[16]; 3781 uint8_t revision[4]; 3782 uint8_t date[8]; 3783 } optical_prod_desc; 3784 }; 3785 3786 #define RDP_DESC_LEN(obj) \ 3787 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len)) 3788 3789 #define RDP_PORT_SPEED_1GB BIT_15 3790 #define RDP_PORT_SPEED_2GB BIT_14 3791 #define RDP_PORT_SPEED_4GB BIT_13 3792 #define RDP_PORT_SPEED_10GB BIT_12 3793 #define RDP_PORT_SPEED_8GB BIT_11 3794 #define RDP_PORT_SPEED_16GB BIT_10 3795 #define RDP_PORT_SPEED_32GB BIT_9 3796 #define RDP_PORT_SPEED_64GB BIT_8 3797 #define RDP_PORT_SPEED_UNKNOWN BIT_0 3798 3799 struct scsi_qlt_host { 3800 void *target_lport_ptr; 3801 struct mutex tgt_mutex; 3802 struct mutex tgt_host_action_mutex; 3803 struct qla_tgt *qla_tgt; 3804 }; 3805 3806 struct qlt_hw_data { 3807 /* Protected by hw lock */ 3808 uint32_t node_name_set:1; 3809 3810 dma_addr_t atio_dma; /* Physical address. */ 3811 struct atio *atio_ring; /* Base virtual address */ 3812 struct atio *atio_ring_ptr; /* Current address. */ 3813 uint16_t atio_ring_index; /* Current index. */ 3814 uint16_t atio_q_length; 3815 __le32 __iomem *atio_q_in; 3816 __le32 __iomem *atio_q_out; 3817 3818 struct qla_tgt_func_tmpl *tgt_ops; 3819 struct qla_tgt_vp_map *tgt_vp_map; 3820 3821 int saved_set; 3822 __le16 saved_exchange_count; 3823 __le32 saved_firmware_options_1; 3824 __le32 saved_firmware_options_2; 3825 __le32 saved_firmware_options_3; 3826 uint8_t saved_firmware_options[2]; 3827 uint8_t saved_add_firmware_options[2]; 3828 3829 uint8_t tgt_node_name[WWN_SIZE]; 3830 3831 struct dentry *dfs_tgt_sess; 3832 struct dentry *dfs_tgt_port_database; 3833 struct dentry *dfs_naqp; 3834 3835 struct list_head q_full_list; 3836 uint32_t num_pend_cmds; 3837 uint32_t num_qfull_cmds_alloc; 3838 uint32_t num_qfull_cmds_dropped; 3839 spinlock_t q_full_lock; 3840 uint32_t leak_exchg_thresh_hold; 3841 spinlock_t sess_lock; 3842 int num_act_qpairs; 3843 #define DEFAULT_NAQP 2 3844 spinlock_t atio_lock ____cacheline_aligned; 3845 struct btree_head32 host_map; 3846 }; 3847 3848 #define MAX_QFULL_CMDS_ALLOC 8192 3849 #define Q_FULL_THRESH_HOLD_PERCENT 90 3850 #define Q_FULL_THRESH_HOLD(ha) \ 3851 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3852 3853 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3854 3855 struct qla_hw_data_stat { 3856 u32 num_fw_dump; 3857 u32 num_mpi_reset; 3858 }; 3859 3860 /* 3861 * Qlogic host adapter specific data structure. 3862 */ 3863 struct qla_hw_data { 3864 struct pci_dev *pdev; 3865 /* SRB cache. */ 3866 #define SRB_MIN_REQ 128 3867 mempool_t *srb_mempool; 3868 3869 volatile struct { 3870 uint32_t mbox_int :1; 3871 uint32_t mbox_busy :1; 3872 uint32_t disable_risc_code_load :1; 3873 uint32_t enable_64bit_addressing :1; 3874 uint32_t enable_lip_reset :1; 3875 uint32_t enable_target_reset :1; 3876 uint32_t enable_lip_full_login :1; 3877 uint32_t enable_led_scheme :1; 3878 3879 uint32_t msi_enabled :1; 3880 uint32_t msix_enabled :1; 3881 uint32_t disable_serdes :1; 3882 uint32_t gpsc_supported :1; 3883 uint32_t npiv_supported :1; 3884 uint32_t pci_channel_io_perm_failure :1; 3885 uint32_t fce_enabled :1; 3886 uint32_t fac_supported :1; 3887 3888 uint32_t chip_reset_done :1; 3889 uint32_t running_gold_fw :1; 3890 uint32_t eeh_busy :1; 3891 uint32_t disable_msix_handshake :1; 3892 uint32_t fcp_prio_enabled :1; 3893 uint32_t isp82xx_fw_hung:1; 3894 uint32_t nic_core_hung:1; 3895 3896 uint32_t quiesce_owner:1; 3897 uint32_t nic_core_reset_hdlr_active:1; 3898 uint32_t nic_core_reset_owner:1; 3899 uint32_t isp82xx_no_md_cap:1; 3900 uint32_t host_shutting_down:1; 3901 uint32_t idc_compl_status:1; 3902 uint32_t mr_reset_hdlr_active:1; 3903 uint32_t mr_intr_valid:1; 3904 3905 uint32_t dport_enabled:1; 3906 uint32_t fawwpn_enabled:1; 3907 uint32_t exlogins_enabled:1; 3908 uint32_t exchoffld_enabled:1; 3909 3910 uint32_t lip_ae:1; 3911 uint32_t n2n_ae:1; 3912 uint32_t fw_started:1; 3913 uint32_t fw_init_done:1; 3914 3915 uint32_t lr_detected:1; 3916 3917 uint32_t rida_fmt2:1; 3918 uint32_t purge_mbox:1; 3919 uint32_t n2n_bigger:1; 3920 uint32_t secure_adapter:1; 3921 uint32_t secure_fw:1; 3922 /* Supported by Adapter */ 3923 uint32_t scm_supported_a:1; 3924 /* Supported by Firmware */ 3925 uint32_t scm_supported_f:1; 3926 /* Enabled in Driver */ 3927 uint32_t scm_enabled:1; 3928 uint32_t max_req_queue_warned:1; 3929 uint32_t plogi_template_valid:1; 3930 uint32_t port_isolated:1; 3931 } flags; 3932 3933 uint16_t max_exchg; 3934 uint16_t lr_distance; /* 32G & above */ 3935 #define LR_DISTANCE_5K 1 3936 #define LR_DISTANCE_10K 0 3937 3938 /* This spinlock is used to protect "io transactions", you must 3939 * acquire it before doing any IO to the card, eg with RD_REG*() and 3940 * WRT_REG*() for the duration of your entire commandtransaction. 3941 * 3942 * This spinlock is of lower priority than the io request lock. 3943 */ 3944 3945 spinlock_t hardware_lock ____cacheline_aligned; 3946 int bars; 3947 int mem_only; 3948 device_reg_t *iobase; /* Base I/O address */ 3949 resource_size_t pio_address; 3950 3951 #define MIN_IOBASE_LEN 0x100 3952 dma_addr_t bar0_hdl; 3953 3954 void __iomem *cregbase; 3955 dma_addr_t bar2_hdl; 3956 #define BAR0_LEN_FX00 (1024 * 1024) 3957 #define BAR2_LEN_FX00 (128 * 1024) 3958 3959 uint32_t rqstq_intr_code; 3960 uint32_t mbx_intr_code; 3961 uint32_t req_que_len; 3962 uint32_t rsp_que_len; 3963 uint32_t req_que_off; 3964 uint32_t rsp_que_off; 3965 3966 /* Multi queue data structs */ 3967 device_reg_t *mqiobase; 3968 device_reg_t *msixbase; 3969 uint16_t msix_count; 3970 uint8_t mqenable; 3971 struct req_que **req_q_map; 3972 struct rsp_que **rsp_q_map; 3973 struct qla_qpair **queue_pair_map; 3974 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3975 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3976 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 3977 / sizeof(unsigned long)]; 3978 uint8_t max_req_queues; 3979 uint8_t max_rsp_queues; 3980 uint8_t max_qpairs; 3981 uint8_t num_qpairs; 3982 struct qla_qpair *base_qpair; 3983 struct qla_npiv_entry *npiv_info; 3984 uint16_t nvram_npiv_size; 3985 3986 uint16_t switch_cap; 3987 #define FLOGI_SEQ_DEL BIT_8 3988 #define FLOGI_MID_SUPPORT BIT_10 3989 #define FLOGI_VSAN_SUPPORT BIT_12 3990 #define FLOGI_SP_SUPPORT BIT_13 3991 3992 uint8_t port_no; /* Physical port of adapter */ 3993 uint8_t exch_starvation; 3994 3995 /* Timeout timers. */ 3996 uint8_t loop_down_abort_time; /* port down timer */ 3997 atomic_t loop_down_timer; /* loop down timer */ 3998 uint8_t link_down_timeout; /* link down timeout */ 3999 uint16_t max_loop_id; 4000 uint16_t max_fibre_devices; /* Maximum number of targets */ 4001 4002 uint16_t fb_rev; 4003 uint16_t min_external_loopid; /* First external loop Id */ 4004 4005 #define PORT_SPEED_UNKNOWN 0xFFFF 4006 #define PORT_SPEED_1GB 0x00 4007 #define PORT_SPEED_2GB 0x01 4008 #define PORT_SPEED_AUTO 0x02 4009 #define PORT_SPEED_4GB 0x03 4010 #define PORT_SPEED_8GB 0x04 4011 #define PORT_SPEED_16GB 0x05 4012 #define PORT_SPEED_32GB 0x06 4013 #define PORT_SPEED_64GB 0x07 4014 #define PORT_SPEED_10GB 0x13 4015 uint16_t link_data_rate; /* F/W operating speed */ 4016 uint16_t set_data_rate; /* Set by user */ 4017 4018 uint8_t current_topology; 4019 uint8_t prev_topology; 4020 #define ISP_CFG_NL 1 4021 #define ISP_CFG_N 2 4022 #define ISP_CFG_FL 4 4023 #define ISP_CFG_F 8 4024 4025 uint8_t operating_mode; /* F/W operating mode */ 4026 #define LOOP 0 4027 #define P2P 1 4028 #define LOOP_P2P 2 4029 #define P2P_LOOP 3 4030 uint8_t interrupts_on; 4031 uint32_t isp_abort_cnt; 4032 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 4033 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 4034 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 4035 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 4036 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 4037 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 4038 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 4039 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 4040 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061 4041 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081 4042 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089 4043 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281 4044 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289 4045 4046 uint32_t isp_type; 4047 #define DT_ISP2100 BIT_0 4048 #define DT_ISP2200 BIT_1 4049 #define DT_ISP2300 BIT_2 4050 #define DT_ISP2312 BIT_3 4051 #define DT_ISP2322 BIT_4 4052 #define DT_ISP6312 BIT_5 4053 #define DT_ISP6322 BIT_6 4054 #define DT_ISP2422 BIT_7 4055 #define DT_ISP2432 BIT_8 4056 #define DT_ISP5422 BIT_9 4057 #define DT_ISP5432 BIT_10 4058 #define DT_ISP2532 BIT_11 4059 #define DT_ISP8432 BIT_12 4060 #define DT_ISP8001 BIT_13 4061 #define DT_ISP8021 BIT_14 4062 #define DT_ISP2031 BIT_15 4063 #define DT_ISP8031 BIT_16 4064 #define DT_ISPFX00 BIT_17 4065 #define DT_ISP8044 BIT_18 4066 #define DT_ISP2071 BIT_19 4067 #define DT_ISP2271 BIT_20 4068 #define DT_ISP2261 BIT_21 4069 #define DT_ISP2061 BIT_22 4070 #define DT_ISP2081 BIT_23 4071 #define DT_ISP2089 BIT_24 4072 #define DT_ISP2281 BIT_25 4073 #define DT_ISP2289 BIT_26 4074 #define DT_ISP_LAST (DT_ISP2289 << 1) 4075 4076 uint32_t device_type; 4077 #define DT_T10_PI BIT_25 4078 #define DT_IIDMA BIT_26 4079 #define DT_FWI2 BIT_27 4080 #define DT_ZIO_SUPPORTED BIT_28 4081 #define DT_OEM_001 BIT_29 4082 #define DT_ISP2200A BIT_30 4083 #define DT_EXTENDED_IDS BIT_31 4084 4085 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 4086 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 4087 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 4088 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 4089 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 4090 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 4091 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 4092 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 4093 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 4094 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 4095 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 4096 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 4097 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 4098 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 4099 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 4100 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 4101 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 4102 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 4103 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 4104 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 4105 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 4106 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 4107 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 4108 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 4109 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081) 4110 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281) 4111 4112 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 4113 IS_QLA6312(ha) || IS_QLA6322(ha)) 4114 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 4115 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 4116 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 4117 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 4118 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 4119 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 4120 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha)) 4121 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 4122 IS_QLA84XX(ha)) 4123 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 4124 IS_QLA8031(ha) || IS_QLA8044(ha)) 4125 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 4126 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 4127 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 4128 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 4129 IS_QLA8044(ha) || IS_QLA27XX(ha) || \ 4130 IS_QLA28XX(ha)) 4131 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4132 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4133 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 4134 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4135 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4136 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4137 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4138 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 4139 4140 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 4141 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 4142 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 4143 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 4144 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 4145 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 4146 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 4147 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 4148 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4149 #define IS_BIDI_CAPABLE(ha) \ 4150 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4151 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 4152 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 4153 ((ha)->fw_attributes_ext[0] & BIT_0)) 4154 #define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14) 4155 #define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS) 4156 #define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD) 4157 #define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp)) 4158 #define QLA_LS_ABTS_WAIT_ENABLED(_sp) \ 4159 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4160 #define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \ 4161 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4162 #define QLA_ABTS_WAIT_ENABLED(_sp) \ 4163 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4164 4165 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4166 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 4167 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 4168 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4169 IS_QLA28XX(ha)) 4170 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 4171 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 4172 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4173 IS_QLA28XX(ha)) 4174 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 4175 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4176 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4177 IS_QLA28XX(ha)) 4178 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4179 IS_QLA28XX(ha)) 4180 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 4181 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4182 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 4183 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4184 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4185 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ 4186 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4187 4188 #define IS_ZIO_THRESHOLD_CAPABLE(ha) \ 4189 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\ 4190 (ha->zio_mode == QLA_ZIO_MODE_6)) 4191 4192 /* HBA serial number */ 4193 uint8_t serial0; 4194 uint8_t serial1; 4195 uint8_t serial2; 4196 4197 /* NVRAM configuration data */ 4198 #define MAX_NVRAM_SIZE 4096 4199 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2) 4200 uint16_t nvram_size; 4201 uint16_t nvram_base; 4202 void *nvram; 4203 uint16_t vpd_size; 4204 uint16_t vpd_base; 4205 void *vpd; 4206 4207 uint16_t loop_reset_delay; 4208 uint8_t retry_count; 4209 uint8_t login_timeout; 4210 uint16_t r_a_tov; 4211 int port_down_retry_count; 4212 uint8_t mbx_count; 4213 uint8_t aen_mbx_count; 4214 atomic_t num_pend_mbx_stage1; 4215 atomic_t num_pend_mbx_stage2; 4216 atomic_t num_pend_mbx_stage3; 4217 uint16_t frame_payload_size; 4218 4219 uint32_t login_retry_count; 4220 /* SNS command interfaces. */ 4221 ms_iocb_entry_t *ms_iocb; 4222 dma_addr_t ms_iocb_dma; 4223 struct ct_sns_pkt *ct_sns; 4224 dma_addr_t ct_sns_dma; 4225 /* SNS command interfaces for 2200. */ 4226 struct sns_cmd_pkt *sns_cmd; 4227 dma_addr_t sns_cmd_dma; 4228 4229 #define SFP_DEV_SIZE 512 4230 #define SFP_BLOCK_SIZE 64 4231 #define SFP_RTDI_LEN SFP_BLOCK_SIZE 4232 4233 void *sfp_data; 4234 dma_addr_t sfp_data_dma; 4235 4236 struct qla_flt_header *flt; 4237 dma_addr_t flt_dma; 4238 4239 #define XGMAC_DATA_SIZE 4096 4240 void *xgmac_data; 4241 dma_addr_t xgmac_data_dma; 4242 4243 #define DCBX_TLV_DATA_SIZE 4096 4244 void *dcbx_tlv; 4245 dma_addr_t dcbx_tlv_dma; 4246 4247 struct task_struct *dpc_thread; 4248 uint8_t dpc_active; /* DPC routine is active */ 4249 4250 dma_addr_t gid_list_dma; 4251 struct gid_list_info *gid_list; 4252 int gid_list_info_size; 4253 4254 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 4255 #define DMA_POOL_SIZE 256 4256 struct dma_pool *s_dma_pool; 4257 4258 dma_addr_t init_cb_dma; 4259 init_cb_t *init_cb; 4260 int init_cb_size; 4261 dma_addr_t ex_init_cb_dma; 4262 struct ex_init_cb_81xx *ex_init_cb; 4263 dma_addr_t sf_init_cb_dma; 4264 struct init_sf_cb *sf_init_cb; 4265 4266 void *scm_fpin_els_buff; 4267 uint64_t scm_fpin_els_buff_size; 4268 bool scm_fpin_valid; 4269 bool scm_fpin_payload_size; 4270 4271 void *async_pd; 4272 dma_addr_t async_pd_dma; 4273 4274 #define ENABLE_EXTENDED_LOGIN BIT_7 4275 4276 /* Extended Logins */ 4277 void *exlogin_buf; 4278 dma_addr_t exlogin_buf_dma; 4279 uint32_t exlogin_size; 4280 4281 #define ENABLE_EXCHANGE_OFFLD BIT_2 4282 4283 /* Exchange Offload */ 4284 void *exchoffld_buf; 4285 dma_addr_t exchoffld_buf_dma; 4286 int exchoffld_size; 4287 int exchoffld_count; 4288 4289 /* n2n */ 4290 struct fc_els_flogi plogi_els_payld; 4291 #define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4) 4292 4293 void *swl; 4294 4295 /* These are used by mailbox operations. */ 4296 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 4297 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 4298 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 4299 4300 mbx_cmd_t *mcp; 4301 struct mbx_cmd_32 *mcp32; 4302 4303 unsigned long mbx_cmd_flags; 4304 #define MBX_INTERRUPT 1 4305 #define MBX_INTR_WAIT 2 4306 #define MBX_UPDATE_FLASH_ACTIVE 3 4307 4308 struct mutex vport_lock; /* Virtual port synchronization */ 4309 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 4310 struct mutex mq_lock; /* multi-queue synchronization */ 4311 struct completion mbx_cmd_comp; /* Serialize mbx access */ 4312 struct completion mbx_intr_comp; /* Used for completion notification */ 4313 struct completion dcbx_comp; /* For set port config notification */ 4314 struct completion lb_portup_comp; /* Used to wait for link up during 4315 * loopback */ 4316 #define DCBX_COMP_TIMEOUT 20 4317 #define LB_PORTUP_COMP_TIMEOUT 10 4318 4319 int notify_dcbx_comp; 4320 int notify_lb_portup_comp; 4321 struct mutex selflogin_lock; 4322 4323 /* Basic firmware related information. */ 4324 uint16_t fw_major_version; 4325 uint16_t fw_minor_version; 4326 uint16_t fw_subminor_version; 4327 uint16_t fw_attributes; 4328 uint16_t fw_attributes_h; 4329 #define FW_ATTR_H_NVME_FBURST BIT_1 4330 #define FW_ATTR_H_NVME BIT_10 4331 #define FW_ATTR_H_NVME_UPDATED BIT_14 4332 4333 /* About firmware SCM support */ 4334 #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12 4335 /* Brocade fabric attached */ 4336 #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000 4337 /* Cisco fabric attached */ 4338 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000 4339 #define FW_ATTR_EXT0_NVME2 BIT_13 4340 uint16_t fw_attributes_ext[2]; 4341 uint32_t fw_memory_size; 4342 uint32_t fw_transfer_size; 4343 uint32_t fw_srisc_address; 4344 #define RISC_START_ADDRESS_2100 0x1000 4345 #define RISC_START_ADDRESS_2300 0x800 4346 #define RISC_START_ADDRESS_2400 0x100000 4347 4348 uint16_t orig_fw_tgt_xcb_count; 4349 uint16_t cur_fw_tgt_xcb_count; 4350 uint16_t orig_fw_xcb_count; 4351 uint16_t cur_fw_xcb_count; 4352 uint16_t orig_fw_iocb_count; 4353 uint16_t cur_fw_iocb_count; 4354 uint16_t fw_max_fcf_count; 4355 4356 uint32_t fw_shared_ram_start; 4357 uint32_t fw_shared_ram_end; 4358 uint32_t fw_ddr_ram_start; 4359 uint32_t fw_ddr_ram_end; 4360 4361 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 4362 uint8_t fw_seriallink_options[4]; 4363 __le16 fw_seriallink_options24[4]; 4364 4365 uint8_t serdes_version[3]; 4366 uint8_t mpi_version[3]; 4367 uint32_t mpi_capabilities; 4368 uint8_t phy_version[3]; 4369 uint8_t pep_version[3]; 4370 4371 /* Firmware dump template */ 4372 struct fwdt { 4373 void *template; 4374 ulong length; 4375 ulong dump_size; 4376 } fwdt[2]; 4377 struct qla2xxx_fw_dump *fw_dump; 4378 uint32_t fw_dump_len; 4379 u32 fw_dump_alloc_len; 4380 bool fw_dumped; 4381 unsigned long fw_dump_cap_flags; 4382 #define RISC_PAUSE_CMPL 0 4383 #define DMA_SHUTDOWN_CMPL 1 4384 #define ISP_RESET_CMPL 2 4385 #define RISC_RDY_AFT_RESET 3 4386 #define RISC_SRAM_DUMP_CMPL 4 4387 #define RISC_EXT_MEM_DUMP_CMPL 5 4388 #define ISP_MBX_RDY 6 4389 #define ISP_SOFT_RESET_CMPL 7 4390 int fw_dump_reading; 4391 void *mpi_fw_dump; 4392 u32 mpi_fw_dump_len; 4393 unsigned int mpi_fw_dump_reading:1; 4394 unsigned int mpi_fw_dumped:1; 4395 int prev_minidump_failed; 4396 dma_addr_t eft_dma; 4397 void *eft; 4398 /* Current size of mctp dump is 0x086064 bytes */ 4399 #define MCTP_DUMP_SIZE 0x086064 4400 dma_addr_t mctp_dump_dma; 4401 void *mctp_dump; 4402 int mctp_dumped; 4403 int mctp_dump_reading; 4404 uint32_t chain_offset; 4405 struct dentry *dfs_dir; 4406 struct dentry *dfs_fce; 4407 struct dentry *dfs_tgt_counters; 4408 struct dentry *dfs_fw_resource_cnt; 4409 4410 dma_addr_t fce_dma; 4411 void *fce; 4412 uint32_t fce_bufs; 4413 uint16_t fce_mb[8]; 4414 uint64_t fce_wr, fce_rd; 4415 struct mutex fce_mutex; 4416 4417 uint32_t pci_attr; 4418 uint16_t chip_revision; 4419 4420 uint16_t product_id[4]; 4421 4422 uint8_t model_number[16+1]; 4423 char model_desc[80]; 4424 uint8_t adapter_id[16+1]; 4425 4426 /* Option ROM information. */ 4427 char *optrom_buffer; 4428 uint32_t optrom_size; 4429 int optrom_state; 4430 #define QLA_SWAITING 0 4431 #define QLA_SREADING 1 4432 #define QLA_SWRITING 2 4433 uint32_t optrom_region_start; 4434 uint32_t optrom_region_size; 4435 struct mutex optrom_mutex; 4436 4437 /* PCI expansion ROM image information. */ 4438 #define ROM_CODE_TYPE_BIOS 0 4439 #define ROM_CODE_TYPE_FCODE 1 4440 #define ROM_CODE_TYPE_EFI 3 4441 uint8_t bios_revision[2]; 4442 uint8_t efi_revision[2]; 4443 uint8_t fcode_revision[16]; 4444 uint32_t fw_revision[4]; 4445 4446 uint32_t gold_fw_version[4]; 4447 4448 /* Offsets for flash/nvram access (set to ~0 if not used). */ 4449 uint32_t flash_conf_off; 4450 uint32_t flash_data_off; 4451 uint32_t nvram_conf_off; 4452 uint32_t nvram_data_off; 4453 4454 uint32_t fdt_wrt_disable; 4455 uint32_t fdt_wrt_enable; 4456 uint32_t fdt_erase_cmd; 4457 uint32_t fdt_block_size; 4458 uint32_t fdt_unprotect_sec_cmd; 4459 uint32_t fdt_protect_sec_cmd; 4460 uint32_t fdt_wrt_sts_reg_cmd; 4461 4462 struct { 4463 uint32_t flt_region_flt; 4464 uint32_t flt_region_fdt; 4465 uint32_t flt_region_boot; 4466 uint32_t flt_region_boot_sec; 4467 uint32_t flt_region_fw; 4468 uint32_t flt_region_fw_sec; 4469 uint32_t flt_region_vpd_nvram; 4470 uint32_t flt_region_vpd_nvram_sec; 4471 uint32_t flt_region_vpd; 4472 uint32_t flt_region_vpd_sec; 4473 uint32_t flt_region_nvram; 4474 uint32_t flt_region_nvram_sec; 4475 uint32_t flt_region_npiv_conf; 4476 uint32_t flt_region_gold_fw; 4477 uint32_t flt_region_fcp_prio; 4478 uint32_t flt_region_bootload; 4479 uint32_t flt_region_img_status_pri; 4480 uint32_t flt_region_img_status_sec; 4481 uint32_t flt_region_aux_img_status_pri; 4482 uint32_t flt_region_aux_img_status_sec; 4483 }; 4484 uint8_t active_image; 4485 4486 /* Needed for BEACON */ 4487 uint16_t beacon_blink_led; 4488 uint8_t beacon_color_state; 4489 #define QLA_LED_GRN_ON 0x01 4490 #define QLA_LED_YLW_ON 0x02 4491 #define QLA_LED_ABR_ON 0x04 4492 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 4493 /* ISP2322: red, green, amber. */ 4494 uint16_t zio_mode; 4495 uint16_t zio_timer; 4496 4497 struct qla_msix_entry *msix_entries; 4498 4499 struct list_head vp_list; /* list of VP */ 4500 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 4501 sizeof(unsigned long)]; 4502 uint16_t num_vhosts; /* number of vports created */ 4503 uint16_t num_vsans; /* number of vsan created */ 4504 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 4505 int cur_vport_count; 4506 4507 struct qla_chip_state_84xx *cs84xx; 4508 struct isp_operations *isp_ops; 4509 struct workqueue_struct *wq; 4510 struct qlfc_fw fw_buf; 4511 4512 /* FCP_CMND priority support */ 4513 struct qla_fcp_prio_cfg *fcp_prio_cfg; 4514 4515 struct dma_pool *dl_dma_pool; 4516 #define DSD_LIST_DMA_POOL_SIZE 512 4517 4518 struct dma_pool *fcp_cmnd_dma_pool; 4519 mempool_t *ctx_mempool; 4520 #define FCP_CMND_DMA_POOL_SIZE 512 4521 4522 void __iomem *nx_pcibase; /* Base I/O address */ 4523 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4524 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4525 4526 uint32_t crb_win; 4527 uint32_t curr_window; 4528 uint32_t ddr_mn_window; 4529 unsigned long mn_win_crb; 4530 unsigned long ms_win_crb; 4531 int qdr_sn_window; 4532 uint32_t fcoe_dev_init_timeout; 4533 uint32_t fcoe_reset_timeout; 4534 rwlock_t hw_lock; 4535 uint16_t portnum; /* port number */ 4536 int link_width; 4537 struct fw_blob *hablob; 4538 struct qla82xx_legacy_intr_set nx_legacy_intr; 4539 4540 uint16_t gbl_dsd_inuse; 4541 uint16_t gbl_dsd_avail; 4542 struct list_head gbl_dsd_list; 4543 #define NUM_DSD_CHAIN 4096 4544 4545 uint8_t fw_type; 4546 uint32_t file_prd_off; /* File firmware product offset */ 4547 4548 uint32_t md_template_size; 4549 void *md_tmplt_hdr; 4550 dma_addr_t md_tmplt_hdr_dma; 4551 void *md_dump; 4552 uint32_t md_dump_size; 4553 4554 void *loop_id_map; 4555 4556 /* QLA83XX IDC specific fields */ 4557 uint32_t idc_audit_ts; 4558 uint32_t idc_extend_tmo; 4559 4560 /* DPC low-priority workqueue */ 4561 struct workqueue_struct *dpc_lp_wq; 4562 struct work_struct idc_aen; 4563 /* DPC high-priority workqueue */ 4564 struct workqueue_struct *dpc_hp_wq; 4565 struct work_struct nic_core_reset; 4566 struct work_struct idc_state_handler; 4567 struct work_struct nic_core_unrecoverable; 4568 struct work_struct board_disable; 4569 4570 struct mr_data_fx00 mr; 4571 uint32_t chip_reset; 4572 4573 struct qlt_hw_data tgt; 4574 int allow_cna_fw_dump; 4575 uint32_t fw_ability_mask; 4576 uint16_t min_supported_speed; 4577 uint16_t max_supported_speed; 4578 4579 /* DMA pool for the DIF bundling buffers */ 4580 struct dma_pool *dif_bundl_pool; 4581 #define DIF_BUNDLING_DMA_POOL_SIZE 1024 4582 struct { 4583 struct { 4584 struct list_head head; 4585 uint count; 4586 } good; 4587 struct { 4588 struct list_head head; 4589 uint count; 4590 } unusable; 4591 } pool; 4592 4593 unsigned long long dif_bundle_crossed_pages; 4594 unsigned long long dif_bundle_reads; 4595 unsigned long long dif_bundle_writes; 4596 unsigned long long dif_bundle_kallocs; 4597 unsigned long long dif_bundle_dma_allocs; 4598 4599 atomic_t nvme_active_aen_cnt; 4600 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4601 4602 uint8_t fc4_type_priority; 4603 4604 atomic_t zio_threshold; 4605 uint16_t last_zio_threshold; 4606 4607 #define DEFAULT_ZIO_THRESHOLD 5 4608 4609 struct qla_hw_data_stat stat; 4610 }; 4611 4612 struct active_regions { 4613 uint8_t global; 4614 struct { 4615 uint8_t board_config; 4616 uint8_t vpd_nvram; 4617 uint8_t npiv_config_0_1; 4618 uint8_t npiv_config_2_3; 4619 } aux; 4620 }; 4621 4622 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4623 #define FW_ABILITY_MAX_SPEED_16G 0x0 4624 #define FW_ABILITY_MAX_SPEED_32G 0x1 4625 #define FW_ABILITY_MAX_SPEED(ha) \ 4626 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4627 4628 #define QLA_GET_DATA_RATE 0 4629 #define QLA_SET_DATA_RATE_NOLR 1 4630 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */ 4631 4632 #define QLA_DEFAULT_PAYLOAD_SIZE 64 4633 /* 4634 * This item might be allocated with a size > sizeof(struct purex_item). 4635 * The "size" variable gives the size of the payload (which 4636 * is variable) starting at "iocb". 4637 */ 4638 struct purex_item { 4639 struct list_head list; 4640 struct scsi_qla_host *vha; 4641 void (*process_item)(struct scsi_qla_host *vha, 4642 struct purex_item *pkt); 4643 atomic_t in_use; 4644 uint16_t size; 4645 struct { 4646 uint8_t iocb[64]; 4647 } iocb; 4648 }; 4649 4650 #define SCM_FLAG_RDF_REJECT 0x00 4651 #define SCM_FLAG_RDF_COMPLETED 0x01 4652 4653 #define QLA_CON_PRIMITIVE_RECEIVED 0x1 4654 #define QLA_CONGESTION_ARB_WARNING 0x1 4655 #define QLA_CONGESTION_ARB_ALARM 0X2 4656 4657 /* 4658 * Qlogic scsi host structure 4659 */ 4660 typedef struct scsi_qla_host { 4661 struct list_head list; 4662 struct list_head vp_fcports; /* list of fcports */ 4663 struct list_head work_list; 4664 spinlock_t work_lock; 4665 struct work_struct iocb_work; 4666 4667 /* Commonly used flags and state information. */ 4668 struct Scsi_Host *host; 4669 unsigned long host_no; 4670 uint8_t host_str[16]; 4671 4672 volatile struct { 4673 uint32_t init_done :1; 4674 uint32_t online :1; 4675 uint32_t reset_active :1; 4676 4677 uint32_t management_server_logged_in :1; 4678 uint32_t process_response_queue :1; 4679 uint32_t difdix_supported:1; 4680 uint32_t delete_progress:1; 4681 4682 uint32_t fw_tgt_reported:1; 4683 uint32_t bbcr_enable:1; 4684 uint32_t qpairs_available:1; 4685 uint32_t qpairs_req_created:1; 4686 uint32_t qpairs_rsp_created:1; 4687 uint32_t nvme_enabled:1; 4688 uint32_t nvme_first_burst:1; 4689 uint32_t nvme2_enabled:1; 4690 } flags; 4691 4692 atomic_t loop_state; 4693 #define LOOP_TIMEOUT 1 4694 #define LOOP_DOWN 2 4695 #define LOOP_UP 3 4696 #define LOOP_UPDATE 4 4697 #define LOOP_READY 5 4698 #define LOOP_DEAD 6 4699 4700 unsigned long relogin_jif; 4701 unsigned long dpc_flags; 4702 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4703 #define RESET_ACTIVE 1 4704 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4705 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4706 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4707 #define LOOP_RESYNC_ACTIVE 5 4708 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4709 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4710 #define RELOGIN_NEEDED 8 4711 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4712 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4713 #define BEACON_BLINK_NEEDED 11 4714 #define REGISTER_FDMI_NEEDED 12 4715 #define FCPORT_UPDATE_NEEDED 13 4716 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4717 #define UNLOADING 15 4718 #define NPIV_CONFIG_NEEDED 16 4719 #define ISP_UNRECOVERABLE 17 4720 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4721 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4722 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4723 #define N2N_LINK_RESET 21 4724 #define PORT_UPDATE_NEEDED 22 4725 #define FX00_RESET_RECOVERY 23 4726 #define FX00_TARGET_SCAN 24 4727 #define FX00_CRITEMP_RECOVERY 25 4728 #define FX00_HOST_INFO_RESEND 26 4729 #define QPAIR_ONLINE_CHECK_NEEDED 27 4730 #define SET_NVME_ZIO_THRESHOLD_NEEDED 28 4731 #define DETECT_SFP_CHANGE 29 4732 #define N2N_LOGIN_NEEDED 30 4733 #define IOCB_WORK_ACTIVE 31 4734 #define SET_ZIO_THRESHOLD_NEEDED 32 4735 #define ISP_ABORT_TO_ROM 33 4736 #define VPORT_DELETE 34 4737 4738 #define PROCESS_PUREX_IOCB 63 4739 4740 unsigned long pci_flags; 4741 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4742 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4743 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4744 4745 uint32_t device_flags; 4746 #define SWITCH_FOUND BIT_0 4747 #define DFLG_NO_CABLE BIT_1 4748 #define DFLG_DEV_FAILED BIT_5 4749 4750 /* ISP configuration data. */ 4751 uint16_t loop_id; /* Host adapter loop id */ 4752 uint16_t self_login_loop_id; /* host adapter loop id 4753 * get it on self login 4754 */ 4755 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4756 * no need of allocating it for 4757 * each command 4758 */ 4759 4760 port_id_t d_id; /* Host adapter port id */ 4761 uint8_t marker_needed; 4762 uint16_t mgmt_svr_loop_id; 4763 4764 4765 4766 /* Timeout timers. */ 4767 uint8_t loop_down_abort_time; /* port down timer */ 4768 atomic_t loop_down_timer; /* loop down timer */ 4769 uint8_t link_down_timeout; /* link down timeout */ 4770 4771 uint32_t timer_active; 4772 struct timer_list timer; 4773 4774 uint8_t node_name[WWN_SIZE]; 4775 uint8_t port_name[WWN_SIZE]; 4776 uint8_t fabric_node_name[WWN_SIZE]; 4777 uint8_t fabric_port_name[WWN_SIZE]; 4778 4779 struct nvme_fc_local_port *nvme_local_port; 4780 struct completion nvme_del_done; 4781 4782 uint16_t fcoe_vlan_id; 4783 uint16_t fcoe_fcf_idx; 4784 uint8_t fcoe_vn_port_mac[6]; 4785 4786 /* list of commands waiting on workqueue */ 4787 struct list_head qla_cmd_list; 4788 struct list_head qla_sess_op_cmd_list; 4789 struct list_head unknown_atio_list; 4790 spinlock_t cmd_list_lock; 4791 struct delayed_work unknown_atio_work; 4792 4793 /* Counter to detect races between ELS and RSCN events */ 4794 atomic_t generation_tick; 4795 /* Time when global fcport update has been scheduled */ 4796 int total_fcport_update_gen; 4797 /* List of pending LOGOs, protected by tgt_mutex */ 4798 struct list_head logo_list; 4799 /* List of pending PLOGI acks, protected by hw lock */ 4800 struct list_head plogi_ack_list; 4801 4802 struct list_head qp_list; 4803 4804 uint32_t vp_abort_cnt; 4805 4806 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4807 uint16_t vp_idx; /* vport ID */ 4808 struct qla_qpair *qpair; /* base qpair */ 4809 4810 unsigned long vp_flags; 4811 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4812 #define VP_CREATE_NEEDED 1 4813 #define VP_BIND_NEEDED 2 4814 #define VP_DELETE_NEEDED 3 4815 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4816 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4817 atomic_t vp_state; 4818 #define VP_OFFLINE 0 4819 #define VP_ACTIVE 1 4820 #define VP_FAILED 2 4821 // #define VP_DISABLE 3 4822 uint16_t vp_err_state; 4823 uint16_t vp_prev_err_state; 4824 #define VP_ERR_UNKWN 0 4825 #define VP_ERR_PORTDWN 1 4826 #define VP_ERR_FAB_UNSUPPORTED 2 4827 #define VP_ERR_FAB_NORESOURCES 3 4828 #define VP_ERR_FAB_LOGOUT 4 4829 #define VP_ERR_ADAP_NORESOURCES 5 4830 struct qla_hw_data *hw; 4831 struct scsi_qlt_host vha_tgt; 4832 struct req_que *req; 4833 int fw_heartbeat_counter; 4834 int seconds_since_last_heartbeat; 4835 struct fc_host_statistics fc_host_stat; 4836 struct qla_statistics qla_stats; 4837 struct bidi_statistics bidi_stats; 4838 atomic_t vref_count; 4839 struct qla8044_reset_template reset_tmplt; 4840 uint16_t bbcr; 4841 4842 uint16_t u_ql2xexchoffld; 4843 uint16_t u_ql2xiniexchg; 4844 uint16_t qlini_mode; 4845 uint16_t ql2xexchoffld; 4846 uint16_t ql2xiniexchg; 4847 4848 struct dentry *dfs_rport_root; 4849 4850 struct purex_list { 4851 struct list_head head; 4852 spinlock_t lock; 4853 } purex_list; 4854 struct purex_item default_item; 4855 4856 struct name_list_extended gnl; 4857 /* Count of active session/fcport */ 4858 int fcport_count; 4859 wait_queue_head_t fcport_waitQ; 4860 wait_queue_head_t vref_waitq; 4861 uint8_t min_supported_speed; 4862 uint8_t n2n_node_name[WWN_SIZE]; 4863 uint8_t n2n_port_name[WWN_SIZE]; 4864 uint16_t n2n_id; 4865 __le16 dport_data[4]; 4866 struct list_head gpnid_list; 4867 struct fab_scan scan; 4868 uint8_t scm_fabric_connection_flags; 4869 4870 unsigned int irq_offset; 4871 4872 u64 hw_err_cnt; 4873 u64 interface_err_cnt; 4874 u64 cmd_timeout_cnt; 4875 u64 reset_cmd_err_cnt; 4876 u64 link_down_time; 4877 u64 short_link_down_cnt; 4878 } scsi_qla_host_t; 4879 4880 struct qla27xx_image_status { 4881 uint8_t image_status_mask; 4882 __le16 generation; 4883 uint8_t ver_major; 4884 uint8_t ver_minor; 4885 uint8_t bitmap; /* 28xx only */ 4886 uint8_t reserved[2]; 4887 __le32 checksum; 4888 __le32 signature; 4889 } __packed; 4890 4891 /* 28xx aux image status bimap values */ 4892 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0 4893 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1 4894 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2 4895 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3 4896 4897 #define SET_VP_IDX 1 4898 #define SET_AL_PA 2 4899 #define RESET_VP_IDX 3 4900 #define RESET_AL_PA 4 4901 struct qla_tgt_vp_map { 4902 uint8_t idx; 4903 scsi_qla_host_t *vha; 4904 }; 4905 4906 struct qla2_sgx { 4907 dma_addr_t dma_addr; /* OUT */ 4908 uint32_t dma_len; /* OUT */ 4909 4910 uint32_t tot_bytes; /* IN */ 4911 struct scatterlist *cur_sg; /* IN */ 4912 4913 /* for book keeping, bzero on initial invocation */ 4914 uint32_t bytes_consumed; 4915 uint32_t num_bytes; 4916 uint32_t tot_partial; 4917 4918 /* for debugging */ 4919 uint32_t num_sg; 4920 srb_t *sp; 4921 }; 4922 4923 #define QLA_FW_STARTED(_ha) { \ 4924 int i; \ 4925 _ha->flags.fw_started = 1; \ 4926 _ha->base_qpair->fw_started = 1; \ 4927 for (i = 0; i < _ha->max_qpairs; i++) { \ 4928 if (_ha->queue_pair_map[i]) \ 4929 _ha->queue_pair_map[i]->fw_started = 1; \ 4930 } \ 4931 } 4932 4933 #define QLA_FW_STOPPED(_ha) { \ 4934 int i; \ 4935 _ha->flags.fw_started = 0; \ 4936 _ha->base_qpair->fw_started = 0; \ 4937 for (i = 0; i < _ha->max_qpairs; i++) { \ 4938 if (_ha->queue_pair_map[i]) \ 4939 _ha->queue_pair_map[i]->fw_started = 0; \ 4940 } \ 4941 } 4942 4943 4944 #define SFUB_CHECKSUM_SIZE 4 4945 4946 struct secure_flash_update_block { 4947 uint32_t block_info; 4948 uint32_t signature_lo; 4949 uint32_t signature_hi; 4950 uint32_t signature_upper[0x3e]; 4951 }; 4952 4953 struct secure_flash_update_block_pk { 4954 uint32_t block_info; 4955 uint32_t signature_lo; 4956 uint32_t signature_hi; 4957 uint32_t signature_upper[0x3e]; 4958 uint32_t public_key[0x41]; 4959 }; 4960 4961 /* 4962 * Macros to help code, maintain, etc. 4963 */ 4964 #define LOOP_TRANSITION(ha) \ 4965 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4966 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 4967 atomic_read(&ha->loop_state) == LOOP_DOWN) 4968 4969 #define STATE_TRANSITION(ha) \ 4970 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4971 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 4972 4973 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 4974 atomic_inc(&__vha->vref_count); \ 4975 mb(); \ 4976 if (__vha->flags.delete_progress) { \ 4977 atomic_dec(&__vha->vref_count); \ 4978 wake_up(&__vha->vref_waitq); \ 4979 __bail = 1; \ 4980 } else { \ 4981 __bail = 0; \ 4982 } \ 4983 } while (0) 4984 4985 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 4986 atomic_dec(&__vha->vref_count); \ 4987 wake_up(&__vha->vref_waitq); \ 4988 } while (0) \ 4989 4990 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 4991 atomic_inc(&__qpair->ref_count); \ 4992 mb(); \ 4993 if (__qpair->delete_in_progress) { \ 4994 atomic_dec(&__qpair->ref_count); \ 4995 __bail = 1; \ 4996 } else { \ 4997 __bail = 0; \ 4998 } \ 4999 } while (0) 5000 5001 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 5002 atomic_dec(&__qpair->ref_count) 5003 5004 #define QLA_ENA_CONF(_ha) {\ 5005 int i;\ 5006 _ha->base_qpair->enable_explicit_conf = 1; \ 5007 for (i = 0; i < _ha->max_qpairs; i++) { \ 5008 if (_ha->queue_pair_map[i]) \ 5009 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 5010 } \ 5011 } 5012 5013 #define QLA_DIS_CONF(_ha) {\ 5014 int i;\ 5015 _ha->base_qpair->enable_explicit_conf = 0; \ 5016 for (i = 0; i < _ha->max_qpairs; i++) { \ 5017 if (_ha->queue_pair_map[i]) \ 5018 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 5019 } \ 5020 } 5021 5022 /* 5023 * qla2x00 local function return status codes 5024 */ 5025 #define MBS_MASK 0x3fff 5026 5027 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 5028 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 5029 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 5030 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 5031 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 5032 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 5033 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 5034 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 5035 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 5036 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 5037 5038 #define QLA_FUNCTION_TIMEOUT 0x100 5039 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 5040 #define QLA_FUNCTION_FAILED 0x102 5041 #define QLA_MEMORY_ALLOC_FAILED 0x103 5042 #define QLA_LOCK_TIMEOUT 0x104 5043 #define QLA_ABORTED 0x105 5044 #define QLA_SUSPENDED 0x106 5045 #define QLA_BUSY 0x107 5046 #define QLA_ALREADY_REGISTERED 0x109 5047 #define QLA_OS_TIMER_EXPIRED 0x10a 5048 5049 #define NVRAM_DELAY() udelay(10) 5050 5051 /* 5052 * Flash support definitions 5053 */ 5054 #define OPTROM_SIZE_2300 0x20000 5055 #define OPTROM_SIZE_2322 0x100000 5056 #define OPTROM_SIZE_24XX 0x100000 5057 #define OPTROM_SIZE_25XX 0x200000 5058 #define OPTROM_SIZE_81XX 0x400000 5059 #define OPTROM_SIZE_82XX 0x800000 5060 #define OPTROM_SIZE_83XX 0x1000000 5061 #define OPTROM_SIZE_28XX 0x2000000 5062 5063 #define OPTROM_BURST_SIZE 0x1000 5064 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 5065 5066 #define QLA_DSDS_PER_IOCB 37 5067 5068 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 5069 5070 #define QLA_SG_ALL 1024 5071 5072 enum nexus_wait_type { 5073 WAIT_HOST = 0, 5074 WAIT_TARGET, 5075 WAIT_LUN, 5076 }; 5077 5078 /* Refer to SNIA SFF 8247 */ 5079 struct sff_8247_a0 { 5080 u8 txid; /* transceiver id */ 5081 u8 ext_txid; 5082 u8 connector; 5083 /* compliance code */ 5084 u8 eth_infi_cc3; /* ethernet, inifiband */ 5085 u8 sonet_cc4[2]; 5086 u8 eth_cc6; 5087 /* link length */ 5088 #define FC_LL_VL BIT_7 /* very long */ 5089 #define FC_LL_S BIT_6 /* Short */ 5090 #define FC_LL_I BIT_5 /* Intermidiate*/ 5091 #define FC_LL_L BIT_4 /* Long */ 5092 #define FC_LL_M BIT_3 /* Medium */ 5093 #define FC_LL_SA BIT_2 /* ShortWave laser */ 5094 #define FC_LL_LC BIT_1 /* LongWave laser */ 5095 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 5096 u8 fc_ll_cc7; 5097 /* FC technology */ 5098 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 5099 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 5100 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 5101 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 5102 #define FC_TEC_ACT BIT_3 /* Active cable */ 5103 #define FC_TEC_PAS BIT_2 /* Passive cable */ 5104 u8 fc_tec_cc8; 5105 /* Transmission Media */ 5106 #define FC_MED_TW BIT_7 /* Twin Ax */ 5107 #define FC_MED_TP BIT_6 /* Twited Pair */ 5108 #define FC_MED_MI BIT_5 /* Min Coax */ 5109 #define FC_MED_TV BIT_4 /* Video Coax */ 5110 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 5111 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 5112 #define FC_MED_SM BIT_0 /* Single Mode */ 5113 u8 fc_med_cc9; 5114 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 5115 #define FC_SP_12 BIT_7 5116 #define FC_SP_8 BIT_6 5117 #define FC_SP_16 BIT_5 5118 #define FC_SP_4 BIT_4 5119 #define FC_SP_32 BIT_3 5120 #define FC_SP_2 BIT_2 5121 #define FC_SP_1 BIT_0 5122 u8 fc_sp_cc10; 5123 u8 encode; 5124 u8 bitrate; 5125 u8 rate_id; 5126 u8 length_km; /* offset 14/eh */ 5127 u8 length_100m; 5128 u8 length_50um_10m; 5129 u8 length_62um_10m; 5130 u8 length_om4_10m; 5131 u8 length_om3_10m; 5132 #define SFF_VEN_NAME_LEN 16 5133 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 5134 u8 tx_compat; 5135 u8 vendor_oui[3]; 5136 #define SFF_PART_NAME_LEN 16 5137 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 5138 u8 vendor_rev[4]; 5139 u8 wavelength[2]; 5140 u8 resv; 5141 u8 cc_base; 5142 u8 options[2]; /* offset 64 */ 5143 u8 br_max; 5144 u8 br_min; 5145 u8 vendor_sn[16]; 5146 u8 date_code[8]; 5147 u8 diag; 5148 u8 enh_options; 5149 u8 sff_revision; 5150 u8 cc_ext; 5151 u8 vendor_specific[32]; 5152 u8 resv2[128]; 5153 }; 5154 5155 /* BPM -- Buffer Plus Management support. */ 5156 #define IS_BPM_CAPABLE(ha) \ 5157 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 5158 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5159 #define IS_BPM_RANGE_CAPABLE(ha) \ 5160 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5161 #define IS_BPM_ENABLED(vha) \ 5162 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw)) 5163 5164 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016 5165 5166 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 5167 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha))) 5168 5169 #define SAVE_TOPO(_ha) { \ 5170 if (_ha->current_topology) \ 5171 _ha->prev_topology = _ha->current_topology; \ 5172 } 5173 5174 #define N2N_TOPO(ha) \ 5175 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ 5176 ha->current_topology == ISP_CFG_N || \ 5177 !ha->current_topology) 5178 5179 #define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */ 5180 5181 #define NVME_TYPE(fcport) \ 5182 (fcport->fc4_type & FS_FC4TYPE_NVME) \ 5183 5184 #define FCP_TYPE(fcport) \ 5185 (fcport->fc4_type & FS_FC4TYPE_FCP) \ 5186 5187 #define NVME_ONLY_TARGET(fcport) \ 5188 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \ 5189 5190 #define NVME_FCP_TARGET(fcport) \ 5191 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \ 5192 5193 #define NVME_TARGET(ha, fcport) \ 5194 ((NVME_FCP_TARGET(fcport) && \ 5195 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) || \ 5196 NVME_ONLY_TARGET(fcport)) \ 5197 5198 #define PRLI_PHASE(_cls) \ 5199 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP)) 5200 5201 enum ql_vnd_host_stat_action { 5202 QLA_STOP = 0, 5203 QLA_START, 5204 QLA_CLEAR, 5205 }; 5206 5207 struct ql_vnd_mng_host_stats_param { 5208 u32 stat_type; 5209 enum ql_vnd_host_stat_action action; 5210 } __packed; 5211 5212 struct ql_vnd_mng_host_stats_resp { 5213 u32 status; 5214 } __packed; 5215 5216 struct ql_vnd_stats_param { 5217 u32 stat_type; 5218 } __packed; 5219 5220 struct ql_vnd_tgt_stats_param { 5221 s32 tgt_id; 5222 u32 stat_type; 5223 } __packed; 5224 5225 enum ql_vnd_host_port_action { 5226 QLA_ENABLE = 0, 5227 QLA_DISABLE, 5228 }; 5229 5230 struct ql_vnd_mng_host_port_param { 5231 enum ql_vnd_host_port_action action; 5232 } __packed; 5233 5234 struct ql_vnd_mng_host_port_resp { 5235 u32 status; 5236 } __packed; 5237 5238 struct ql_vnd_stat_entry { 5239 u32 stat_type; /* Failure type */ 5240 u32 tgt_num; /* Target Num */ 5241 u64 cnt; /* Counter value */ 5242 } __packed; 5243 5244 struct ql_vnd_stats { 5245 u64 entry_count; /* Num of entries */ 5246 u64 rservd; 5247 struct ql_vnd_stat_entry entry[0]; /* Place holder of entries */ 5248 } __packed; 5249 5250 struct ql_vnd_host_stats_resp { 5251 u32 status; 5252 struct ql_vnd_stats stats; 5253 } __packed; 5254 5255 struct ql_vnd_tgt_stats_resp { 5256 u32 status; 5257 struct ql_vnd_stats stats; 5258 } __packed; 5259 5260 #include "qla_target.h" 5261 #include "qla_gbl.h" 5262 #include "qla_dbg.h" 5263 #include "qla_inline.h" 5264 #endif 5265