1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 #include <linux/btree.h> 29 30 #include <scsi/scsi.h> 31 #include <scsi/scsi_host.h> 32 #include <scsi/scsi_device.h> 33 #include <scsi/scsi_cmnd.h> 34 #include <scsi/scsi_transport_fc.h> 35 #include <scsi/scsi_bsg_fc.h> 36 37 #include "qla_bsg.h" 38 #include "qla_nx.h" 39 #include "qla_nx2.h" 40 #include "qla_nvme.h" 41 #define QLA2XXX_DRIVER_NAME "qla2xxx" 42 #define QLA2XXX_APIDEV "ql2xapidev" 43 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 44 45 /* 46 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 47 * but that's fine as we don't look at the last 24 ones for 48 * ISP2100 HBAs. 49 */ 50 #define MAILBOX_REGISTER_COUNT_2100 8 51 #define MAILBOX_REGISTER_COUNT_2200 24 52 #define MAILBOX_REGISTER_COUNT 32 53 54 #define QLA2200A_RISC_ROM_VER 4 55 #define FPM_2300 6 56 #define FPM_2310 7 57 58 #include "qla_settings.h" 59 60 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 61 62 /* 63 * Data bit definitions 64 */ 65 #define BIT_0 0x1 66 #define BIT_1 0x2 67 #define BIT_2 0x4 68 #define BIT_3 0x8 69 #define BIT_4 0x10 70 #define BIT_5 0x20 71 #define BIT_6 0x40 72 #define BIT_7 0x80 73 #define BIT_8 0x100 74 #define BIT_9 0x200 75 #define BIT_10 0x400 76 #define BIT_11 0x800 77 #define BIT_12 0x1000 78 #define BIT_13 0x2000 79 #define BIT_14 0x4000 80 #define BIT_15 0x8000 81 #define BIT_16 0x10000 82 #define BIT_17 0x20000 83 #define BIT_18 0x40000 84 #define BIT_19 0x80000 85 #define BIT_20 0x100000 86 #define BIT_21 0x200000 87 #define BIT_22 0x400000 88 #define BIT_23 0x800000 89 #define BIT_24 0x1000000 90 #define BIT_25 0x2000000 91 #define BIT_26 0x4000000 92 #define BIT_27 0x8000000 93 #define BIT_28 0x10000000 94 #define BIT_29 0x20000000 95 #define BIT_30 0x40000000 96 #define BIT_31 0x80000000 97 98 #define LSB(x) ((uint8_t)(x)) 99 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 100 101 #define LSW(x) ((uint16_t)(x)) 102 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 103 104 #define LSD(x) ((uint32_t)((uint64_t)(x))) 105 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 106 107 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 108 109 /* 110 * I/O register 111 */ 112 113 #define RD_REG_BYTE(addr) readb(addr) 114 #define RD_REG_WORD(addr) readw(addr) 115 #define RD_REG_DWORD(addr) readl(addr) 116 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 117 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 118 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 119 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 120 #define WRT_REG_WORD(addr, data) writew(data,addr) 121 #define WRT_REG_DWORD(addr, data) writel(data,addr) 122 123 /* 124 * ISP83XX specific remote register addresses 125 */ 126 #define QLA83XX_LED_PORT0 0x00201320 127 #define QLA83XX_LED_PORT1 0x00201328 128 #define QLA83XX_IDC_DEV_STATE 0x22102384 129 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 130 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 131 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 132 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 133 #define QLA83XX_IDC_CONTROL 0x22102390 134 #define QLA83XX_IDC_AUDIT 0x22102394 135 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 136 #define QLA83XX_DRIVER_LOCKID 0x22102104 137 #define QLA83XX_DRIVER_LOCK 0x8111c028 138 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 139 #define QLA83XX_FLASH_LOCKID 0x22102100 140 #define QLA83XX_FLASH_LOCK 0x8111c010 141 #define QLA83XX_FLASH_UNLOCK 0x8111c014 142 #define QLA83XX_DEV_PARTINFO1 0x221023e0 143 #define QLA83XX_DEV_PARTINFO2 0x221023e4 144 #define QLA83XX_FW_HEARTBEAT 0x221020b0 145 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 146 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 147 148 /* 83XX: Macros defining 8200 AEN Reason codes */ 149 #define IDC_DEVICE_STATE_CHANGE BIT_0 150 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 151 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 152 #define IDC_HEARTBEAT_FAILURE BIT_3 153 154 /* 83XX: Macros defining 8200 AEN Error-levels */ 155 #define ERR_LEVEL_NON_FATAL 0x1 156 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 157 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 158 159 /* 83XX: Macros for IDC Version */ 160 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 161 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 162 163 /* 83XX: Macros for scheduling dpc tasks */ 164 #define QLA83XX_NIC_CORE_RESET 0x1 165 #define QLA83XX_IDC_STATE_HANDLER 0x2 166 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 167 168 /* 83XX: Macros for defining IDC-Control bits */ 169 #define QLA83XX_IDC_RESET_DISABLED BIT_0 170 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 171 172 /* 83XX: Macros for different timeouts */ 173 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 174 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 175 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 176 177 /* 83XX: Macros for defining class in DEV-Partition Info register */ 178 #define QLA83XX_CLASS_TYPE_NONE 0x0 179 #define QLA83XX_CLASS_TYPE_NIC 0x1 180 #define QLA83XX_CLASS_TYPE_FCOE 0x2 181 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 182 183 /* 83XX: Macros for IDC Lock-Recovery stages */ 184 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 185 * lock-recovery 186 */ 187 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 188 189 /* 83XX: Macros for IDC Audit type */ 190 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 191 * dev-state change to NEED-RESET 192 * or NEED-QUIESCENT 193 */ 194 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 195 * reset-recovery completion is 196 * second 197 */ 198 /* ISP2031: Values for laser on/off */ 199 #define PORT_0_2031 0x00201340 200 #define PORT_1_2031 0x00201350 201 #define LASER_ON_2031 0x01800100 202 #define LASER_OFF_2031 0x01800180 203 204 /* 205 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 206 * 133Mhz slot. 207 */ 208 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 209 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 210 211 /* 212 * Fibre Channel device definitions. 213 */ 214 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 215 #define MAX_FIBRE_DEVICES_2100 512 216 #define MAX_FIBRE_DEVICES_2400 2048 217 #define MAX_FIBRE_DEVICES_LOOP 128 218 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 219 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 220 #define MAX_FIBRE_LUNS 0xFFFF 221 #define MAX_HOST_COUNT 16 222 223 /* 224 * Host adapter default definitions. 225 */ 226 #define MAX_BUSES 1 /* We only have one bus today */ 227 #define MIN_LUNS 8 228 #define MAX_LUNS MAX_FIBRE_LUNS 229 #define MAX_CMDS_PER_LUN 255 230 231 /* 232 * Fibre Channel device definitions. 233 */ 234 #define SNS_LAST_LOOP_ID_2100 0xfe 235 #define SNS_LAST_LOOP_ID_2300 0x7ff 236 237 #define LAST_LOCAL_LOOP_ID 0x7d 238 #define SNS_FL_PORT 0x7e 239 #define FABRIC_CONTROLLER 0x7f 240 #define SIMPLE_NAME_SERVER 0x80 241 #define SNS_FIRST_LOOP_ID 0x81 242 #define MANAGEMENT_SERVER 0xfe 243 #define BROADCAST 0xff 244 245 /* 246 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 247 * valid range of an N-PORT id is 0 through 0x7ef. 248 */ 249 #define NPH_LAST_HANDLE 0x7ef 250 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ 251 #define NPH_SNS 0x7fc /* FFFFFC */ 252 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 253 #define NPH_F_PORT 0x7fe /* FFFFFE */ 254 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 255 256 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 257 258 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 259 #include "qla_fw.h" 260 261 struct name_list_extended { 262 struct get_name_list_extended *l; 263 dma_addr_t ldma; 264 struct list_head fcports; /* protect by sess_list */ 265 u32 size; 266 u8 sent; 267 }; 268 /* 269 * Timeout timer counts in seconds 270 */ 271 #define PORT_RETRY_TIME 1 272 #define LOOP_DOWN_TIMEOUT 60 273 #define LOOP_DOWN_TIME 255 /* 240 */ 274 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 275 276 #define DEFAULT_OUTSTANDING_COMMANDS 4096 277 #define MIN_OUTSTANDING_COMMANDS 128 278 279 /* ISP request and response entry counts (37-65535) */ 280 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 281 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 282 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 283 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 284 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 285 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 286 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 287 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 288 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 289 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 290 #define FW_DEF_EXCHANGES_CNT 2048 291 292 struct req_que; 293 struct qla_tgt_sess; 294 295 /* 296 * SCSI Request Block 297 */ 298 struct srb_cmd { 299 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 300 uint32_t request_sense_length; 301 uint32_t fw_sense_length; 302 uint8_t *request_sense_ptr; 303 void *ctx; 304 }; 305 306 /* 307 * SRB flag definitions 308 */ 309 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 310 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 311 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 312 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 313 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 314 315 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 316 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 317 318 struct els_logo_payload { 319 uint8_t opcode; 320 uint8_t rsvd[3]; 321 uint8_t s_id[3]; 322 uint8_t rsvd1[1]; 323 uint8_t wwpn[WWN_SIZE]; 324 }; 325 326 struct els_plogi_payload { 327 uint8_t opcode; 328 uint8_t rsvd[3]; 329 uint8_t data[112]; 330 }; 331 332 struct ct_arg { 333 void *iocb; 334 u16 nport_handle; 335 dma_addr_t req_dma; 336 dma_addr_t rsp_dma; 337 u32 req_size; 338 u32 rsp_size; 339 void *req; 340 void *rsp; 341 }; 342 343 /* 344 * SRB extensions. 345 */ 346 struct srb_iocb { 347 union { 348 struct { 349 uint16_t flags; 350 #define SRB_LOGIN_RETRIED BIT_0 351 #define SRB_LOGIN_COND_PLOGI BIT_1 352 #define SRB_LOGIN_SKIP_PRLI BIT_2 353 #define SRB_LOGIN_NVME_PRLI BIT_3 354 uint16_t data[2]; 355 u32 iop[2]; 356 } logio; 357 struct { 358 #define ELS_DCMD_TIMEOUT 20 359 #define ELS_DCMD_LOGO 0x5 360 uint32_t flags; 361 uint32_t els_cmd; 362 struct completion comp; 363 struct els_logo_payload *els_logo_pyld; 364 dma_addr_t els_logo_pyld_dma; 365 } els_logo; 366 struct { 367 #define ELS_DCMD_PLOGI 0x3 368 uint32_t flags; 369 uint32_t els_cmd; 370 struct completion comp; 371 struct els_plogi_payload *els_plogi_pyld; 372 struct els_plogi_payload *els_resp_pyld; 373 dma_addr_t els_plogi_pyld_dma; 374 dma_addr_t els_resp_pyld_dma; 375 uint32_t fw_status[3]; 376 __le16 comp_status; 377 __le16 len; 378 } els_plogi; 379 struct { 380 /* 381 * Values for flags field below are as 382 * defined in tsk_mgmt_entry struct 383 * for control_flags field in qla_fw.h. 384 */ 385 uint64_t lun; 386 uint32_t flags; 387 uint32_t data; 388 struct completion comp; 389 __le16 comp_status; 390 } tmf; 391 struct { 392 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 393 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 394 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 395 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 396 #define FXDISC_TIMEOUT 20 397 uint8_t flags; 398 uint32_t req_len; 399 uint32_t rsp_len; 400 void *req_addr; 401 void *rsp_addr; 402 dma_addr_t req_dma_handle; 403 dma_addr_t rsp_dma_handle; 404 __le32 adapter_id; 405 __le32 adapter_id_hi; 406 __le16 req_func_type; 407 __le32 req_data; 408 __le32 req_data_extra; 409 __le32 result; 410 __le32 seq_number; 411 __le16 fw_flags; 412 struct completion fxiocb_comp; 413 __le32 reserved_0; 414 uint8_t reserved_1; 415 } fxiocb; 416 struct { 417 uint32_t cmd_hndl; 418 __le16 comp_status; 419 struct completion comp; 420 } abt; 421 struct ct_arg ctarg; 422 #define MAX_IOCB_MB_REG 28 423 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 424 struct { 425 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 426 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 427 void *out, *in; 428 dma_addr_t out_dma, in_dma; 429 struct completion comp; 430 int rc; 431 } mbx; 432 struct { 433 struct imm_ntfy_from_isp *ntfy; 434 } nack; 435 struct { 436 __le16 comp_status; 437 uint16_t rsp_pyld_len; 438 uint8_t aen_op; 439 void *desc; 440 441 /* These are only used with ls4 requests */ 442 int cmd_len; 443 int rsp_len; 444 dma_addr_t cmd_dma; 445 dma_addr_t rsp_dma; 446 enum nvmefc_fcp_datadir dir; 447 uint32_t dl; 448 uint32_t timeout_sec; 449 struct list_head entry; 450 } nvme; 451 } u; 452 453 struct timer_list timer; 454 void (*timeout)(void *); 455 }; 456 457 /* Values for srb_ctx type */ 458 #define SRB_LOGIN_CMD 1 459 #define SRB_LOGOUT_CMD 2 460 #define SRB_ELS_CMD_RPT 3 461 #define SRB_ELS_CMD_HST 4 462 #define SRB_CT_CMD 5 463 #define SRB_ADISC_CMD 6 464 #define SRB_TM_CMD 7 465 #define SRB_SCSI_CMD 8 466 #define SRB_BIDI_CMD 9 467 #define SRB_FXIOCB_DCMD 10 468 #define SRB_FXIOCB_BCMD 11 469 #define SRB_ABT_CMD 12 470 #define SRB_ELS_DCMD 13 471 #define SRB_MB_IOCB 14 472 #define SRB_CT_PTHRU_CMD 15 473 #define SRB_NACK_PLOGI 16 474 #define SRB_NACK_PRLI 17 475 #define SRB_NACK_LOGO 18 476 #define SRB_NVME_CMD 19 477 #define SRB_NVME_LS 20 478 #define SRB_PRLI_CMD 21 479 480 enum { 481 TYPE_SRB, 482 TYPE_TGT_CMD, 483 }; 484 485 typedef struct srb { 486 /* 487 * Do not move cmd_type field, it needs to 488 * line up with qla_tgt_cmd->cmd_type 489 */ 490 uint8_t cmd_type; 491 uint8_t pad[3]; 492 atomic_t ref_count; 493 wait_queue_head_t nvme_ls_waitq; 494 struct fc_port *fcport; 495 struct scsi_qla_host *vha; 496 uint32_t handle; 497 uint16_t flags; 498 uint16_t type; 499 const char *name; 500 int iocbs; 501 struct qla_qpair *qpair; 502 u32 gen1; /* scratch */ 503 u32 gen2; /* scratch */ 504 union { 505 struct srb_iocb iocb_cmd; 506 struct bsg_job *bsg_job; 507 struct srb_cmd scmd; 508 } u; 509 void (*done)(void *, int); 510 void (*free)(void *); 511 } srb_t; 512 513 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 514 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 515 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 516 517 #define GET_CMD_SENSE_LEN(sp) \ 518 (sp->u.scmd.request_sense_length) 519 #define SET_CMD_SENSE_LEN(sp, len) \ 520 (sp->u.scmd.request_sense_length = len) 521 #define GET_CMD_SENSE_PTR(sp) \ 522 (sp->u.scmd.request_sense_ptr) 523 #define SET_CMD_SENSE_PTR(sp, ptr) \ 524 (sp->u.scmd.request_sense_ptr = ptr) 525 #define GET_FW_SENSE_LEN(sp) \ 526 (sp->u.scmd.fw_sense_length) 527 #define SET_FW_SENSE_LEN(sp, len) \ 528 (sp->u.scmd.fw_sense_length = len) 529 530 struct msg_echo_lb { 531 dma_addr_t send_dma; 532 dma_addr_t rcv_dma; 533 uint16_t req_sg_cnt; 534 uint16_t rsp_sg_cnt; 535 uint16_t options; 536 uint32_t transfer_size; 537 uint32_t iteration_count; 538 }; 539 540 /* 541 * ISP I/O Register Set structure definitions. 542 */ 543 struct device_reg_2xxx { 544 uint16_t flash_address; /* Flash BIOS address */ 545 uint16_t flash_data; /* Flash BIOS data */ 546 uint16_t unused_1[1]; /* Gap */ 547 uint16_t ctrl_status; /* Control/Status */ 548 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 549 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 550 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 551 552 uint16_t ictrl; /* Interrupt control */ 553 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 554 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 555 556 uint16_t istatus; /* Interrupt status */ 557 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 558 559 uint16_t semaphore; /* Semaphore */ 560 uint16_t nvram; /* NVRAM register. */ 561 #define NVR_DESELECT 0 562 #define NVR_BUSY BIT_15 563 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 564 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 565 #define NVR_DATA_IN BIT_3 566 #define NVR_DATA_OUT BIT_2 567 #define NVR_SELECT BIT_1 568 #define NVR_CLOCK BIT_0 569 570 #define NVR_WAIT_CNT 20000 571 572 union { 573 struct { 574 uint16_t mailbox0; 575 uint16_t mailbox1; 576 uint16_t mailbox2; 577 uint16_t mailbox3; 578 uint16_t mailbox4; 579 uint16_t mailbox5; 580 uint16_t mailbox6; 581 uint16_t mailbox7; 582 uint16_t unused_2[59]; /* Gap */ 583 } __attribute__((packed)) isp2100; 584 struct { 585 /* Request Queue */ 586 uint16_t req_q_in; /* In-Pointer */ 587 uint16_t req_q_out; /* Out-Pointer */ 588 /* Response Queue */ 589 uint16_t rsp_q_in; /* In-Pointer */ 590 uint16_t rsp_q_out; /* Out-Pointer */ 591 592 /* RISC to Host Status */ 593 uint32_t host_status; 594 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 595 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 596 597 /* Host to Host Semaphore */ 598 uint16_t host_semaphore; 599 uint16_t unused_3[17]; /* Gap */ 600 uint16_t mailbox0; 601 uint16_t mailbox1; 602 uint16_t mailbox2; 603 uint16_t mailbox3; 604 uint16_t mailbox4; 605 uint16_t mailbox5; 606 uint16_t mailbox6; 607 uint16_t mailbox7; 608 uint16_t mailbox8; 609 uint16_t mailbox9; 610 uint16_t mailbox10; 611 uint16_t mailbox11; 612 uint16_t mailbox12; 613 uint16_t mailbox13; 614 uint16_t mailbox14; 615 uint16_t mailbox15; 616 uint16_t mailbox16; 617 uint16_t mailbox17; 618 uint16_t mailbox18; 619 uint16_t mailbox19; 620 uint16_t mailbox20; 621 uint16_t mailbox21; 622 uint16_t mailbox22; 623 uint16_t mailbox23; 624 uint16_t mailbox24; 625 uint16_t mailbox25; 626 uint16_t mailbox26; 627 uint16_t mailbox27; 628 uint16_t mailbox28; 629 uint16_t mailbox29; 630 uint16_t mailbox30; 631 uint16_t mailbox31; 632 uint16_t fb_cmd; 633 uint16_t unused_4[10]; /* Gap */ 634 } __attribute__((packed)) isp2300; 635 } u; 636 637 uint16_t fpm_diag_config; 638 uint16_t unused_5[0x4]; /* Gap */ 639 uint16_t risc_hw; 640 uint16_t unused_5_1; /* Gap */ 641 uint16_t pcr; /* Processor Control Register. */ 642 uint16_t unused_6[0x5]; /* Gap */ 643 uint16_t mctr; /* Memory Configuration and Timing. */ 644 uint16_t unused_7[0x3]; /* Gap */ 645 uint16_t fb_cmd_2100; /* Unused on 23XX */ 646 uint16_t unused_8[0x3]; /* Gap */ 647 uint16_t hccr; /* Host command & control register. */ 648 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 649 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 650 /* HCCR commands */ 651 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 652 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 653 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 654 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 655 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 656 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 657 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 658 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 659 660 uint16_t unused_9[5]; /* Gap */ 661 uint16_t gpiod; /* GPIO Data register. */ 662 uint16_t gpioe; /* GPIO Enable register. */ 663 #define GPIO_LED_MASK 0x00C0 664 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 665 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 666 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 667 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 668 #define GPIO_LED_ALL_OFF 0x0000 669 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 670 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 671 672 union { 673 struct { 674 uint16_t unused_10[8]; /* Gap */ 675 uint16_t mailbox8; 676 uint16_t mailbox9; 677 uint16_t mailbox10; 678 uint16_t mailbox11; 679 uint16_t mailbox12; 680 uint16_t mailbox13; 681 uint16_t mailbox14; 682 uint16_t mailbox15; 683 uint16_t mailbox16; 684 uint16_t mailbox17; 685 uint16_t mailbox18; 686 uint16_t mailbox19; 687 uint16_t mailbox20; 688 uint16_t mailbox21; 689 uint16_t mailbox22; 690 uint16_t mailbox23; /* Also probe reg. */ 691 } __attribute__((packed)) isp2200; 692 } u_end; 693 }; 694 695 struct device_reg_25xxmq { 696 uint32_t req_q_in; 697 uint32_t req_q_out; 698 uint32_t rsp_q_in; 699 uint32_t rsp_q_out; 700 uint32_t atio_q_in; 701 uint32_t atio_q_out; 702 }; 703 704 705 struct device_reg_fx00 { 706 uint32_t mailbox0; /* 00 */ 707 uint32_t mailbox1; /* 04 */ 708 uint32_t mailbox2; /* 08 */ 709 uint32_t mailbox3; /* 0C */ 710 uint32_t mailbox4; /* 10 */ 711 uint32_t mailbox5; /* 14 */ 712 uint32_t mailbox6; /* 18 */ 713 uint32_t mailbox7; /* 1C */ 714 uint32_t mailbox8; /* 20 */ 715 uint32_t mailbox9; /* 24 */ 716 uint32_t mailbox10; /* 28 */ 717 uint32_t mailbox11; 718 uint32_t mailbox12; 719 uint32_t mailbox13; 720 uint32_t mailbox14; 721 uint32_t mailbox15; 722 uint32_t mailbox16; 723 uint32_t mailbox17; 724 uint32_t mailbox18; 725 uint32_t mailbox19; 726 uint32_t mailbox20; 727 uint32_t mailbox21; 728 uint32_t mailbox22; 729 uint32_t mailbox23; 730 uint32_t mailbox24; 731 uint32_t mailbox25; 732 uint32_t mailbox26; 733 uint32_t mailbox27; 734 uint32_t mailbox28; 735 uint32_t mailbox29; 736 uint32_t mailbox30; 737 uint32_t mailbox31; 738 uint32_t aenmailbox0; 739 uint32_t aenmailbox1; 740 uint32_t aenmailbox2; 741 uint32_t aenmailbox3; 742 uint32_t aenmailbox4; 743 uint32_t aenmailbox5; 744 uint32_t aenmailbox6; 745 uint32_t aenmailbox7; 746 /* Request Queue. */ 747 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 748 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 749 /* Response Queue. */ 750 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 751 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 752 /* Init values shadowed on FW Up Event */ 753 uint32_t initval0; /* B0 */ 754 uint32_t initval1; /* B4 */ 755 uint32_t initval2; /* B8 */ 756 uint32_t initval3; /* BC */ 757 uint32_t initval4; /* C0 */ 758 uint32_t initval5; /* C4 */ 759 uint32_t initval6; /* C8 */ 760 uint32_t initval7; /* CC */ 761 uint32_t fwheartbeat; /* D0 */ 762 uint32_t pseudoaen; /* D4 */ 763 }; 764 765 766 767 typedef union { 768 struct device_reg_2xxx isp; 769 struct device_reg_24xx isp24; 770 struct device_reg_25xxmq isp25mq; 771 struct device_reg_82xx isp82; 772 struct device_reg_fx00 ispfx00; 773 } __iomem device_reg_t; 774 775 #define ISP_REQ_Q_IN(ha, reg) \ 776 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 777 &(reg)->u.isp2100.mailbox4 : \ 778 &(reg)->u.isp2300.req_q_in) 779 #define ISP_REQ_Q_OUT(ha, reg) \ 780 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 781 &(reg)->u.isp2100.mailbox4 : \ 782 &(reg)->u.isp2300.req_q_out) 783 #define ISP_RSP_Q_IN(ha, reg) \ 784 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 785 &(reg)->u.isp2100.mailbox5 : \ 786 &(reg)->u.isp2300.rsp_q_in) 787 #define ISP_RSP_Q_OUT(ha, reg) \ 788 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 789 &(reg)->u.isp2100.mailbox5 : \ 790 &(reg)->u.isp2300.rsp_q_out) 791 792 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 793 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 794 795 #define MAILBOX_REG(ha, reg, num) \ 796 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 797 (num < 8 ? \ 798 &(reg)->u.isp2100.mailbox0 + (num) : \ 799 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 800 &(reg)->u.isp2300.mailbox0 + (num)) 801 #define RD_MAILBOX_REG(ha, reg, num) \ 802 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 803 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 804 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 805 806 #define FB_CMD_REG(ha, reg) \ 807 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 808 &(reg)->fb_cmd_2100 : \ 809 &(reg)->u.isp2300.fb_cmd) 810 #define RD_FB_CMD_REG(ha, reg) \ 811 RD_REG_WORD(FB_CMD_REG(ha, reg)) 812 #define WRT_FB_CMD_REG(ha, reg, data) \ 813 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 814 815 typedef struct { 816 uint32_t out_mb; /* outbound from driver */ 817 uint32_t in_mb; /* Incoming from RISC */ 818 uint16_t mb[MAILBOX_REGISTER_COUNT]; 819 long buf_size; 820 void *bufp; 821 uint32_t tov; 822 uint8_t flags; 823 #define MBX_DMA_IN BIT_0 824 #define MBX_DMA_OUT BIT_1 825 #define IOCTL_CMD BIT_2 826 } mbx_cmd_t; 827 828 struct mbx_cmd_32 { 829 uint32_t out_mb; /* outbound from driver */ 830 uint32_t in_mb; /* Incoming from RISC */ 831 uint32_t mb[MAILBOX_REGISTER_COUNT]; 832 long buf_size; 833 void *bufp; 834 uint32_t tov; 835 uint8_t flags; 836 #define MBX_DMA_IN BIT_0 837 #define MBX_DMA_OUT BIT_1 838 #define IOCTL_CMD BIT_2 839 }; 840 841 842 #define MBX_TOV_SECONDS 30 843 844 /* 845 * ISP product identification definitions in mailboxes after reset. 846 */ 847 #define PROD_ID_1 0x4953 848 #define PROD_ID_2 0x0000 849 #define PROD_ID_2a 0x5020 850 #define PROD_ID_3 0x2020 851 852 /* 853 * ISP mailbox Self-Test status codes 854 */ 855 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 856 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 857 #define MBS_BUSY 4 /* Busy. */ 858 859 /* 860 * ISP mailbox command complete status codes 861 */ 862 #define MBS_COMMAND_COMPLETE 0x4000 863 #define MBS_INVALID_COMMAND 0x4001 864 #define MBS_HOST_INTERFACE_ERROR 0x4002 865 #define MBS_TEST_FAILED 0x4003 866 #define MBS_COMMAND_ERROR 0x4005 867 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 868 #define MBS_PORT_ID_USED 0x4007 869 #define MBS_LOOP_ID_USED 0x4008 870 #define MBS_ALL_IDS_IN_USE 0x4009 871 #define MBS_NOT_LOGGED_IN 0x400A 872 #define MBS_LINK_DOWN_ERROR 0x400B 873 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 874 875 /* 876 * ISP mailbox asynchronous event status codes 877 */ 878 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 879 #define MBA_RESET 0x8001 /* Reset Detected. */ 880 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 881 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 882 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 883 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 884 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 885 /* occurred. */ 886 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 887 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 888 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 889 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 890 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 891 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 892 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 893 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 894 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 895 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 896 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 897 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 898 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 899 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 900 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 901 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 902 /* used. */ 903 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 904 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 905 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 906 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 907 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 908 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 909 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 910 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 911 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 912 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 913 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 914 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 915 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 916 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 917 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 918 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 919 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 920 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 921 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 922 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 923 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 924 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 925 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 926 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 927 Notification */ 928 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 929 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 930 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 931 /* 83XX FCoE specific */ 932 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 933 934 /* Interrupt type codes */ 935 #define INTR_ROM_MB_SUCCESS 0x1 936 #define INTR_ROM_MB_FAILED 0x2 937 #define INTR_MB_SUCCESS 0x10 938 #define INTR_MB_FAILED 0x11 939 #define INTR_ASYNC_EVENT 0x12 940 #define INTR_RSP_QUE_UPDATE 0x13 941 #define INTR_RSP_QUE_UPDATE_83XX 0x14 942 #define INTR_ATIO_QUE_UPDATE 0x1C 943 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 944 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 945 946 /* ISP mailbox loopback echo diagnostic error code */ 947 #define MBS_LB_RESET 0x17 948 /* 949 * Firmware options 1, 2, 3. 950 */ 951 #define FO1_AE_ON_LIPF8 BIT_0 952 #define FO1_AE_ALL_LIP_RESET BIT_1 953 #define FO1_CTIO_RETRY BIT_3 954 #define FO1_DISABLE_LIP_F7_SW BIT_4 955 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 956 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 957 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 958 #define FO1_SET_EMPHASIS_SWING BIT_8 959 #define FO1_AE_AUTO_BYPASS BIT_9 960 #define FO1_ENABLE_PURE_IOCB BIT_10 961 #define FO1_AE_PLOGI_RJT BIT_11 962 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 963 #define FO1_AE_QUEUE_FULL BIT_13 964 965 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 966 #define FO2_REV_LOOPBACK BIT_1 967 968 #define FO3_ENABLE_EMERG_IOCB BIT_0 969 #define FO3_AE_RND_ERROR BIT_1 970 971 /* 24XX additional firmware options */ 972 #define ADD_FO_COUNT 3 973 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 974 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 975 976 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 977 978 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 979 980 /* 981 * ISP mailbox commands 982 */ 983 #define MBC_LOAD_RAM 1 /* Load RAM. */ 984 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 985 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 986 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 987 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 988 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 989 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 990 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 991 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 992 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 993 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 994 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 995 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 996 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 997 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 998 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 999 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1000 #define MBC_RESET 0x18 /* Reset. */ 1001 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1002 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1003 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1004 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1005 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1006 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1007 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1008 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1009 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1010 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1011 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1012 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1013 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1014 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1015 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1016 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1017 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1018 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1019 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1020 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1021 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1022 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1023 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1024 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1025 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1026 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1027 /* Initialization Procedure */ 1028 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1029 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1030 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1031 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1032 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1033 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1034 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1035 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1036 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1037 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1038 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1039 /* commandd. */ 1040 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1041 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1042 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1043 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1044 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1045 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1046 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1047 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1048 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1049 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1050 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1051 1052 /* 1053 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1054 * should be defined with MBC_MR_* 1055 */ 1056 #define MBC_MR_DRV_SHUTDOWN 0x6A 1057 1058 /* 1059 * ISP24xx mailbox commands 1060 */ 1061 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1062 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1063 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1064 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1065 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1066 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1067 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1068 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1069 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1070 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1071 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1072 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1073 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1074 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1075 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1076 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1077 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1078 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1079 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1080 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1081 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1082 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1083 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1084 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1085 1086 /* 1087 * ISP81xx mailbox commands 1088 */ 1089 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1090 1091 /* 1092 * ISP8044 mailbox commands 1093 */ 1094 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1095 #define HCS_WRITE_SERDES 0x3 1096 #define HCS_READ_SERDES 0x4 1097 1098 /* Firmware return data sizes */ 1099 #define FCAL_MAP_SIZE 128 1100 1101 /* Mailbox bit definitions for out_mb and in_mb */ 1102 #define MBX_31 BIT_31 1103 #define MBX_30 BIT_30 1104 #define MBX_29 BIT_29 1105 #define MBX_28 BIT_28 1106 #define MBX_27 BIT_27 1107 #define MBX_26 BIT_26 1108 #define MBX_25 BIT_25 1109 #define MBX_24 BIT_24 1110 #define MBX_23 BIT_23 1111 #define MBX_22 BIT_22 1112 #define MBX_21 BIT_21 1113 #define MBX_20 BIT_20 1114 #define MBX_19 BIT_19 1115 #define MBX_18 BIT_18 1116 #define MBX_17 BIT_17 1117 #define MBX_16 BIT_16 1118 #define MBX_15 BIT_15 1119 #define MBX_14 BIT_14 1120 #define MBX_13 BIT_13 1121 #define MBX_12 BIT_12 1122 #define MBX_11 BIT_11 1123 #define MBX_10 BIT_10 1124 #define MBX_9 BIT_9 1125 #define MBX_8 BIT_8 1126 #define MBX_7 BIT_7 1127 #define MBX_6 BIT_6 1128 #define MBX_5 BIT_5 1129 #define MBX_4 BIT_4 1130 #define MBX_3 BIT_3 1131 #define MBX_2 BIT_2 1132 #define MBX_1 BIT_1 1133 #define MBX_0 BIT_0 1134 1135 #define RNID_TYPE_PORT_LOGIN 0x7 1136 #define RNID_TYPE_SET_VERSION 0x9 1137 #define RNID_TYPE_ASIC_TEMP 0xC 1138 1139 /* 1140 * Firmware state codes from get firmware state mailbox command 1141 */ 1142 #define FSTATE_CONFIG_WAIT 0 1143 #define FSTATE_WAIT_AL_PA 1 1144 #define FSTATE_WAIT_LOGIN 2 1145 #define FSTATE_READY 3 1146 #define FSTATE_LOSS_OF_SYNC 4 1147 #define FSTATE_ERROR 5 1148 #define FSTATE_REINIT 6 1149 #define FSTATE_NON_PART 7 1150 1151 #define FSTATE_CONFIG_CORRECT 0 1152 #define FSTATE_P2P_RCV_LIP 1 1153 #define FSTATE_P2P_CHOOSE_LOOP 2 1154 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1155 #define FSTATE_FATAL_ERROR 4 1156 #define FSTATE_LOOP_BACK_CONN 5 1157 1158 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1159 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1160 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1161 #define QLA27XX_PRIMARY_IMAGE 1 1162 #define QLA27XX_SECONDARY_IMAGE 2 1163 1164 /* 1165 * Port Database structure definition 1166 * Little endian except where noted. 1167 */ 1168 #define PORT_DATABASE_SIZE 128 /* bytes */ 1169 typedef struct { 1170 uint8_t options; 1171 uint8_t control; 1172 uint8_t master_state; 1173 uint8_t slave_state; 1174 uint8_t reserved[2]; 1175 uint8_t hard_address; 1176 uint8_t reserved_1; 1177 uint8_t port_id[4]; 1178 uint8_t node_name[WWN_SIZE]; 1179 uint8_t port_name[WWN_SIZE]; 1180 uint16_t execution_throttle; 1181 uint16_t execution_count; 1182 uint8_t reset_count; 1183 uint8_t reserved_2; 1184 uint16_t resource_allocation; 1185 uint16_t current_allocation; 1186 uint16_t queue_head; 1187 uint16_t queue_tail; 1188 uint16_t transmit_execution_list_next; 1189 uint16_t transmit_execution_list_previous; 1190 uint16_t common_features; 1191 uint16_t total_concurrent_sequences; 1192 uint16_t RO_by_information_category; 1193 uint8_t recipient; 1194 uint8_t initiator; 1195 uint16_t receive_data_size; 1196 uint16_t concurrent_sequences; 1197 uint16_t open_sequences_per_exchange; 1198 uint16_t lun_abort_flags; 1199 uint16_t lun_stop_flags; 1200 uint16_t stop_queue_head; 1201 uint16_t stop_queue_tail; 1202 uint16_t port_retry_timer; 1203 uint16_t next_sequence_id; 1204 uint16_t frame_count; 1205 uint16_t PRLI_payload_length; 1206 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1207 /* Bits 15-0 of word 0 */ 1208 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1209 /* Bits 15-0 of word 3 */ 1210 uint16_t loop_id; 1211 uint16_t extended_lun_info_list_pointer; 1212 uint16_t extended_lun_stop_list_pointer; 1213 } port_database_t; 1214 1215 /* 1216 * Port database slave/master states 1217 */ 1218 #define PD_STATE_DISCOVERY 0 1219 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1220 #define PD_STATE_PORT_LOGIN 2 1221 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1222 #define PD_STATE_PROCESS_LOGIN 4 1223 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1224 #define PD_STATE_PORT_LOGGED_IN 6 1225 #define PD_STATE_PORT_UNAVAILABLE 7 1226 #define PD_STATE_PROCESS_LOGOUT 8 1227 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1228 #define PD_STATE_PORT_LOGOUT 10 1229 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1230 1231 1232 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1233 #define QLA_ZIO_DISABLED 0 1234 #define QLA_ZIO_DEFAULT_TIMER 2 1235 1236 /* 1237 * ISP Initialization Control Block. 1238 * Little endian except where noted. 1239 */ 1240 #define ICB_VERSION 1 1241 typedef struct { 1242 uint8_t version; 1243 uint8_t reserved_1; 1244 1245 /* 1246 * LSB BIT 0 = Enable Hard Loop Id 1247 * LSB BIT 1 = Enable Fairness 1248 * LSB BIT 2 = Enable Full-Duplex 1249 * LSB BIT 3 = Enable Fast Posting 1250 * LSB BIT 4 = Enable Target Mode 1251 * LSB BIT 5 = Disable Initiator Mode 1252 * LSB BIT 6 = Enable ADISC 1253 * LSB BIT 7 = Enable Target Inquiry Data 1254 * 1255 * MSB BIT 0 = Enable PDBC Notify 1256 * MSB BIT 1 = Non Participating LIP 1257 * MSB BIT 2 = Descending Loop ID Search 1258 * MSB BIT 3 = Acquire Loop ID in LIPA 1259 * MSB BIT 4 = Stop PortQ on Full Status 1260 * MSB BIT 5 = Full Login after LIP 1261 * MSB BIT 6 = Node Name Option 1262 * MSB BIT 7 = Ext IFWCB enable bit 1263 */ 1264 uint8_t firmware_options[2]; 1265 1266 uint16_t frame_payload_size; 1267 uint16_t max_iocb_allocation; 1268 uint16_t execution_throttle; 1269 uint8_t retry_count; 1270 uint8_t retry_delay; /* unused */ 1271 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1272 uint16_t hard_address; 1273 uint8_t inquiry_data; 1274 uint8_t login_timeout; 1275 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1276 1277 uint16_t request_q_outpointer; 1278 uint16_t response_q_inpointer; 1279 uint16_t request_q_length; 1280 uint16_t response_q_length; 1281 uint32_t request_q_address[2]; 1282 uint32_t response_q_address[2]; 1283 1284 uint16_t lun_enables; 1285 uint8_t command_resource_count; 1286 uint8_t immediate_notify_resource_count; 1287 uint16_t timeout; 1288 uint8_t reserved_2[2]; 1289 1290 /* 1291 * LSB BIT 0 = Timer Operation mode bit 0 1292 * LSB BIT 1 = Timer Operation mode bit 1 1293 * LSB BIT 2 = Timer Operation mode bit 2 1294 * LSB BIT 3 = Timer Operation mode bit 3 1295 * LSB BIT 4 = Init Config Mode bit 0 1296 * LSB BIT 5 = Init Config Mode bit 1 1297 * LSB BIT 6 = Init Config Mode bit 2 1298 * LSB BIT 7 = Enable Non part on LIHA failure 1299 * 1300 * MSB BIT 0 = Enable class 2 1301 * MSB BIT 1 = Enable ACK0 1302 * MSB BIT 2 = 1303 * MSB BIT 3 = 1304 * MSB BIT 4 = FC Tape Enable 1305 * MSB BIT 5 = Enable FC Confirm 1306 * MSB BIT 6 = Enable command queuing in target mode 1307 * MSB BIT 7 = No Logo On Link Down 1308 */ 1309 uint8_t add_firmware_options[2]; 1310 1311 uint8_t response_accumulation_timer; 1312 uint8_t interrupt_delay_timer; 1313 1314 /* 1315 * LSB BIT 0 = Enable Read xfr_rdy 1316 * LSB BIT 1 = Soft ID only 1317 * LSB BIT 2 = 1318 * LSB BIT 3 = 1319 * LSB BIT 4 = FCP RSP Payload [0] 1320 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1321 * LSB BIT 6 = Enable Out-of-Order frame handling 1322 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1323 * 1324 * MSB BIT 0 = Sbus enable - 2300 1325 * MSB BIT 1 = 1326 * MSB BIT 2 = 1327 * MSB BIT 3 = 1328 * MSB BIT 4 = LED mode 1329 * MSB BIT 5 = enable 50 ohm termination 1330 * MSB BIT 6 = Data Rate (2300 only) 1331 * MSB BIT 7 = Data Rate (2300 only) 1332 */ 1333 uint8_t special_options[2]; 1334 1335 uint8_t reserved_3[26]; 1336 } init_cb_t; 1337 1338 /* 1339 * Get Link Status mailbox command return buffer. 1340 */ 1341 #define GLSO_SEND_RPS BIT_0 1342 #define GLSO_USE_DID BIT_3 1343 1344 struct link_statistics { 1345 uint32_t link_fail_cnt; 1346 uint32_t loss_sync_cnt; 1347 uint32_t loss_sig_cnt; 1348 uint32_t prim_seq_err_cnt; 1349 uint32_t inval_xmit_word_cnt; 1350 uint32_t inval_crc_cnt; 1351 uint32_t lip_cnt; 1352 uint32_t link_up_cnt; 1353 uint32_t link_down_loop_init_tmo; 1354 uint32_t link_down_los; 1355 uint32_t link_down_loss_rcv_clk; 1356 uint32_t reserved0[5]; 1357 uint32_t port_cfg_chg; 1358 uint32_t reserved1[11]; 1359 uint32_t rsp_q_full; 1360 uint32_t atio_q_full; 1361 uint32_t drop_ae; 1362 uint32_t els_proto_err; 1363 uint32_t reserved2; 1364 uint32_t tx_frames; 1365 uint32_t rx_frames; 1366 uint32_t discarded_frames; 1367 uint32_t dropped_frames; 1368 uint32_t reserved3; 1369 uint32_t nos_rcvd; 1370 uint32_t reserved4[4]; 1371 uint32_t tx_prjt; 1372 uint32_t rcv_exfail; 1373 uint32_t rcv_abts; 1374 uint32_t seq_frm_miss; 1375 uint32_t corr_err; 1376 uint32_t mb_rqst; 1377 uint32_t nport_full; 1378 uint32_t eofa; 1379 uint32_t reserved5; 1380 uint32_t fpm_recv_word_cnt_lo; 1381 uint32_t fpm_recv_word_cnt_hi; 1382 uint32_t fpm_disc_word_cnt_lo; 1383 uint32_t fpm_disc_word_cnt_hi; 1384 uint32_t fpm_xmit_word_cnt_lo; 1385 uint32_t fpm_xmit_word_cnt_hi; 1386 uint32_t reserved6[70]; 1387 }; 1388 1389 /* 1390 * NVRAM Command values. 1391 */ 1392 #define NV_START_BIT BIT_2 1393 #define NV_WRITE_OP (BIT_26+BIT_24) 1394 #define NV_READ_OP (BIT_26+BIT_25) 1395 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1396 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1397 #define NV_DELAY_COUNT 10 1398 1399 /* 1400 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1401 */ 1402 typedef struct { 1403 /* 1404 * NVRAM header 1405 */ 1406 uint8_t id[4]; 1407 uint8_t nvram_version; 1408 uint8_t reserved_0; 1409 1410 /* 1411 * NVRAM RISC parameter block 1412 */ 1413 uint8_t parameter_block_version; 1414 uint8_t reserved_1; 1415 1416 /* 1417 * LSB BIT 0 = Enable Hard Loop Id 1418 * LSB BIT 1 = Enable Fairness 1419 * LSB BIT 2 = Enable Full-Duplex 1420 * LSB BIT 3 = Enable Fast Posting 1421 * LSB BIT 4 = Enable Target Mode 1422 * LSB BIT 5 = Disable Initiator Mode 1423 * LSB BIT 6 = Enable ADISC 1424 * LSB BIT 7 = Enable Target Inquiry Data 1425 * 1426 * MSB BIT 0 = Enable PDBC Notify 1427 * MSB BIT 1 = Non Participating LIP 1428 * MSB BIT 2 = Descending Loop ID Search 1429 * MSB BIT 3 = Acquire Loop ID in LIPA 1430 * MSB BIT 4 = Stop PortQ on Full Status 1431 * MSB BIT 5 = Full Login after LIP 1432 * MSB BIT 6 = Node Name Option 1433 * MSB BIT 7 = Ext IFWCB enable bit 1434 */ 1435 uint8_t firmware_options[2]; 1436 1437 uint16_t frame_payload_size; 1438 uint16_t max_iocb_allocation; 1439 uint16_t execution_throttle; 1440 uint8_t retry_count; 1441 uint8_t retry_delay; /* unused */ 1442 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1443 uint16_t hard_address; 1444 uint8_t inquiry_data; 1445 uint8_t login_timeout; 1446 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1447 1448 /* 1449 * LSB BIT 0 = Timer Operation mode bit 0 1450 * LSB BIT 1 = Timer Operation mode bit 1 1451 * LSB BIT 2 = Timer Operation mode bit 2 1452 * LSB BIT 3 = Timer Operation mode bit 3 1453 * LSB BIT 4 = Init Config Mode bit 0 1454 * LSB BIT 5 = Init Config Mode bit 1 1455 * LSB BIT 6 = Init Config Mode bit 2 1456 * LSB BIT 7 = Enable Non part on LIHA failure 1457 * 1458 * MSB BIT 0 = Enable class 2 1459 * MSB BIT 1 = Enable ACK0 1460 * MSB BIT 2 = 1461 * MSB BIT 3 = 1462 * MSB BIT 4 = FC Tape Enable 1463 * MSB BIT 5 = Enable FC Confirm 1464 * MSB BIT 6 = Enable command queuing in target mode 1465 * MSB BIT 7 = No Logo On Link Down 1466 */ 1467 uint8_t add_firmware_options[2]; 1468 1469 uint8_t response_accumulation_timer; 1470 uint8_t interrupt_delay_timer; 1471 1472 /* 1473 * LSB BIT 0 = Enable Read xfr_rdy 1474 * LSB BIT 1 = Soft ID only 1475 * LSB BIT 2 = 1476 * LSB BIT 3 = 1477 * LSB BIT 4 = FCP RSP Payload [0] 1478 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1479 * LSB BIT 6 = Enable Out-of-Order frame handling 1480 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1481 * 1482 * MSB BIT 0 = Sbus enable - 2300 1483 * MSB BIT 1 = 1484 * MSB BIT 2 = 1485 * MSB BIT 3 = 1486 * MSB BIT 4 = LED mode 1487 * MSB BIT 5 = enable 50 ohm termination 1488 * MSB BIT 6 = Data Rate (2300 only) 1489 * MSB BIT 7 = Data Rate (2300 only) 1490 */ 1491 uint8_t special_options[2]; 1492 1493 /* Reserved for expanded RISC parameter block */ 1494 uint8_t reserved_2[22]; 1495 1496 /* 1497 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1498 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1499 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1500 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1501 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1502 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1503 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1504 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1505 * 1506 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1507 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1508 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1509 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1510 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1511 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1512 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1513 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1514 * 1515 * LSB BIT 0 = Output Swing 1G bit 0 1516 * LSB BIT 1 = Output Swing 1G bit 1 1517 * LSB BIT 2 = Output Swing 1G bit 2 1518 * LSB BIT 3 = Output Emphasis 1G bit 0 1519 * LSB BIT 4 = Output Emphasis 1G bit 1 1520 * LSB BIT 5 = Output Swing 2G bit 0 1521 * LSB BIT 6 = Output Swing 2G bit 1 1522 * LSB BIT 7 = Output Swing 2G bit 2 1523 * 1524 * MSB BIT 0 = Output Emphasis 2G bit 0 1525 * MSB BIT 1 = Output Emphasis 2G bit 1 1526 * MSB BIT 2 = Output Enable 1527 * MSB BIT 3 = 1528 * MSB BIT 4 = 1529 * MSB BIT 5 = 1530 * MSB BIT 6 = 1531 * MSB BIT 7 = 1532 */ 1533 uint8_t seriallink_options[4]; 1534 1535 /* 1536 * NVRAM host parameter block 1537 * 1538 * LSB BIT 0 = Enable spinup delay 1539 * LSB BIT 1 = Disable BIOS 1540 * LSB BIT 2 = Enable Memory Map BIOS 1541 * LSB BIT 3 = Enable Selectable Boot 1542 * LSB BIT 4 = Disable RISC code load 1543 * LSB BIT 5 = Set cache line size 1 1544 * LSB BIT 6 = PCI Parity Disable 1545 * LSB BIT 7 = Enable extended logging 1546 * 1547 * MSB BIT 0 = Enable 64bit addressing 1548 * MSB BIT 1 = Enable lip reset 1549 * MSB BIT 2 = Enable lip full login 1550 * MSB BIT 3 = Enable target reset 1551 * MSB BIT 4 = Enable database storage 1552 * MSB BIT 5 = Enable cache flush read 1553 * MSB BIT 6 = Enable database load 1554 * MSB BIT 7 = Enable alternate WWN 1555 */ 1556 uint8_t host_p[2]; 1557 1558 uint8_t boot_node_name[WWN_SIZE]; 1559 uint8_t boot_lun_number; 1560 uint8_t reset_delay; 1561 uint8_t port_down_retry_count; 1562 uint8_t boot_id_number; 1563 uint16_t max_luns_per_target; 1564 uint8_t fcode_boot_port_name[WWN_SIZE]; 1565 uint8_t alternate_port_name[WWN_SIZE]; 1566 uint8_t alternate_node_name[WWN_SIZE]; 1567 1568 /* 1569 * BIT 0 = Selective Login 1570 * BIT 1 = Alt-Boot Enable 1571 * BIT 2 = 1572 * BIT 3 = Boot Order List 1573 * BIT 4 = 1574 * BIT 5 = Selective LUN 1575 * BIT 6 = 1576 * BIT 7 = unused 1577 */ 1578 uint8_t efi_parameters; 1579 1580 uint8_t link_down_timeout; 1581 1582 uint8_t adapter_id[16]; 1583 1584 uint8_t alt1_boot_node_name[WWN_SIZE]; 1585 uint16_t alt1_boot_lun_number; 1586 uint8_t alt2_boot_node_name[WWN_SIZE]; 1587 uint16_t alt2_boot_lun_number; 1588 uint8_t alt3_boot_node_name[WWN_SIZE]; 1589 uint16_t alt3_boot_lun_number; 1590 uint8_t alt4_boot_node_name[WWN_SIZE]; 1591 uint16_t alt4_boot_lun_number; 1592 uint8_t alt5_boot_node_name[WWN_SIZE]; 1593 uint16_t alt5_boot_lun_number; 1594 uint8_t alt6_boot_node_name[WWN_SIZE]; 1595 uint16_t alt6_boot_lun_number; 1596 uint8_t alt7_boot_node_name[WWN_SIZE]; 1597 uint16_t alt7_boot_lun_number; 1598 1599 uint8_t reserved_3[2]; 1600 1601 /* Offset 200-215 : Model Number */ 1602 uint8_t model_number[16]; 1603 1604 /* OEM related items */ 1605 uint8_t oem_specific[16]; 1606 1607 /* 1608 * NVRAM Adapter Features offset 232-239 1609 * 1610 * LSB BIT 0 = External GBIC 1611 * LSB BIT 1 = Risc RAM parity 1612 * LSB BIT 2 = Buffer Plus Module 1613 * LSB BIT 3 = Multi Chip Adapter 1614 * LSB BIT 4 = Internal connector 1615 * LSB BIT 5 = 1616 * LSB BIT 6 = 1617 * LSB BIT 7 = 1618 * 1619 * MSB BIT 0 = 1620 * MSB BIT 1 = 1621 * MSB BIT 2 = 1622 * MSB BIT 3 = 1623 * MSB BIT 4 = 1624 * MSB BIT 5 = 1625 * MSB BIT 6 = 1626 * MSB BIT 7 = 1627 */ 1628 uint8_t adapter_features[2]; 1629 1630 uint8_t reserved_4[16]; 1631 1632 /* Subsystem vendor ID for ISP2200 */ 1633 uint16_t subsystem_vendor_id_2200; 1634 1635 /* Subsystem device ID for ISP2200 */ 1636 uint16_t subsystem_device_id_2200; 1637 1638 uint8_t reserved_5; 1639 uint8_t checksum; 1640 } nvram_t; 1641 1642 /* 1643 * ISP queue - response queue entry definition. 1644 */ 1645 typedef struct { 1646 uint8_t entry_type; /* Entry type. */ 1647 uint8_t entry_count; /* Entry count. */ 1648 uint8_t sys_define; /* System defined. */ 1649 uint8_t entry_status; /* Entry Status. */ 1650 uint32_t handle; /* System defined handle */ 1651 uint8_t data[52]; 1652 uint32_t signature; 1653 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1654 } response_t; 1655 1656 /* 1657 * ISP queue - ATIO queue entry definition. 1658 */ 1659 struct atio { 1660 uint8_t entry_type; /* Entry type. */ 1661 uint8_t entry_count; /* Entry count. */ 1662 __le16 attr_n_length; 1663 uint8_t data[56]; 1664 uint32_t signature; 1665 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1666 }; 1667 1668 typedef union { 1669 uint16_t extended; 1670 struct { 1671 uint8_t reserved; 1672 uint8_t standard; 1673 } id; 1674 } target_id_t; 1675 1676 #define SET_TARGET_ID(ha, to, from) \ 1677 do { \ 1678 if (HAS_EXTENDED_IDS(ha)) \ 1679 to.extended = cpu_to_le16(from); \ 1680 else \ 1681 to.id.standard = (uint8_t)from; \ 1682 } while (0) 1683 1684 /* 1685 * ISP queue - command entry structure definition. 1686 */ 1687 #define COMMAND_TYPE 0x11 /* Command entry */ 1688 typedef struct { 1689 uint8_t entry_type; /* Entry type. */ 1690 uint8_t entry_count; /* Entry count. */ 1691 uint8_t sys_define; /* System defined. */ 1692 uint8_t entry_status; /* Entry Status. */ 1693 uint32_t handle; /* System handle. */ 1694 target_id_t target; /* SCSI ID */ 1695 uint16_t lun; /* SCSI LUN */ 1696 uint16_t control_flags; /* Control flags. */ 1697 #define CF_WRITE BIT_6 1698 #define CF_READ BIT_5 1699 #define CF_SIMPLE_TAG BIT_3 1700 #define CF_ORDERED_TAG BIT_2 1701 #define CF_HEAD_TAG BIT_1 1702 uint16_t reserved_1; 1703 uint16_t timeout; /* Command timeout. */ 1704 uint16_t dseg_count; /* Data segment count. */ 1705 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1706 uint32_t byte_count; /* Total byte count. */ 1707 uint32_t dseg_0_address; /* Data segment 0 address. */ 1708 uint32_t dseg_0_length; /* Data segment 0 length. */ 1709 uint32_t dseg_1_address; /* Data segment 1 address. */ 1710 uint32_t dseg_1_length; /* Data segment 1 length. */ 1711 uint32_t dseg_2_address; /* Data segment 2 address. */ 1712 uint32_t dseg_2_length; /* Data segment 2 length. */ 1713 } cmd_entry_t; 1714 1715 /* 1716 * ISP queue - 64-Bit addressing, command entry structure definition. 1717 */ 1718 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1719 typedef struct { 1720 uint8_t entry_type; /* Entry type. */ 1721 uint8_t entry_count; /* Entry count. */ 1722 uint8_t sys_define; /* System defined. */ 1723 uint8_t entry_status; /* Entry Status. */ 1724 uint32_t handle; /* System handle. */ 1725 target_id_t target; /* SCSI ID */ 1726 uint16_t lun; /* SCSI LUN */ 1727 uint16_t control_flags; /* Control flags. */ 1728 uint16_t reserved_1; 1729 uint16_t timeout; /* Command timeout. */ 1730 uint16_t dseg_count; /* Data segment count. */ 1731 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1732 uint32_t byte_count; /* Total byte count. */ 1733 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1734 uint32_t dseg_0_length; /* Data segment 0 length. */ 1735 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1736 uint32_t dseg_1_length; /* Data segment 1 length. */ 1737 } cmd_a64_entry_t, request_t; 1738 1739 /* 1740 * ISP queue - continuation entry structure definition. 1741 */ 1742 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1743 typedef struct { 1744 uint8_t entry_type; /* Entry type. */ 1745 uint8_t entry_count; /* Entry count. */ 1746 uint8_t sys_define; /* System defined. */ 1747 uint8_t entry_status; /* Entry Status. */ 1748 uint32_t reserved; 1749 uint32_t dseg_0_address; /* Data segment 0 address. */ 1750 uint32_t dseg_0_length; /* Data segment 0 length. */ 1751 uint32_t dseg_1_address; /* Data segment 1 address. */ 1752 uint32_t dseg_1_length; /* Data segment 1 length. */ 1753 uint32_t dseg_2_address; /* Data segment 2 address. */ 1754 uint32_t dseg_2_length; /* Data segment 2 length. */ 1755 uint32_t dseg_3_address; /* Data segment 3 address. */ 1756 uint32_t dseg_3_length; /* Data segment 3 length. */ 1757 uint32_t dseg_4_address; /* Data segment 4 address. */ 1758 uint32_t dseg_4_length; /* Data segment 4 length. */ 1759 uint32_t dseg_5_address; /* Data segment 5 address. */ 1760 uint32_t dseg_5_length; /* Data segment 5 length. */ 1761 uint32_t dseg_6_address; /* Data segment 6 address. */ 1762 uint32_t dseg_6_length; /* Data segment 6 length. */ 1763 } cont_entry_t; 1764 1765 /* 1766 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1767 */ 1768 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1769 typedef struct { 1770 uint8_t entry_type; /* Entry type. */ 1771 uint8_t entry_count; /* Entry count. */ 1772 uint8_t sys_define; /* System defined. */ 1773 uint8_t entry_status; /* Entry Status. */ 1774 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1775 uint32_t dseg_0_length; /* Data segment 0 length. */ 1776 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1777 uint32_t dseg_1_length; /* Data segment 1 length. */ 1778 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1779 uint32_t dseg_2_length; /* Data segment 2 length. */ 1780 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1781 uint32_t dseg_3_length; /* Data segment 3 length. */ 1782 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1783 uint32_t dseg_4_length; /* Data segment 4 length. */ 1784 } cont_a64_entry_t; 1785 1786 #define PO_MODE_DIF_INSERT 0 1787 #define PO_MODE_DIF_REMOVE 1 1788 #define PO_MODE_DIF_PASS 2 1789 #define PO_MODE_DIF_REPLACE 3 1790 #define PO_MODE_DIF_TCP_CKSUM 6 1791 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1792 #define PO_DISABLE_GUARD_CHECK BIT_4 1793 #define PO_DISABLE_INCR_REF_TAG BIT_5 1794 #define PO_DIS_HEADER_MODE BIT_7 1795 #define PO_ENABLE_DIF_BUNDLING BIT_8 1796 #define PO_DIS_FRAME_MODE BIT_9 1797 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1798 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1799 1800 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1801 #define PO_DIS_REF_TAG_REPL BIT_13 1802 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1803 #define PO_DIS_REF_TAG_VALD BIT_15 1804 1805 /* 1806 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1807 */ 1808 struct crc_context { 1809 uint32_t handle; /* System handle. */ 1810 __le32 ref_tag; 1811 __le16 app_tag; 1812 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1813 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1814 __le16 guard_seed; /* Initial Guard Seed */ 1815 __le16 prot_opts; /* Requested Data Protection Mode */ 1816 __le16 blk_size; /* Data size in bytes */ 1817 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1818 * only) */ 1819 __le32 byte_count; /* Total byte count/ total data 1820 * transfer count */ 1821 union { 1822 struct { 1823 uint32_t reserved_1; 1824 uint16_t reserved_2; 1825 uint16_t reserved_3; 1826 uint32_t reserved_4; 1827 uint32_t data_address[2]; 1828 uint32_t data_length; 1829 uint32_t reserved_5[2]; 1830 uint32_t reserved_6; 1831 } nobundling; 1832 struct { 1833 __le32 dif_byte_count; /* Total DIF byte 1834 * count */ 1835 uint16_t reserved_1; 1836 __le16 dseg_count; /* Data segment count */ 1837 uint32_t reserved_2; 1838 uint32_t data_address[2]; 1839 uint32_t data_length; 1840 uint32_t dif_address[2]; 1841 uint32_t dif_length; /* Data segment 0 1842 * length */ 1843 } bundling; 1844 } u; 1845 1846 struct fcp_cmnd fcp_cmnd; 1847 dma_addr_t crc_ctx_dma; 1848 /* List of DMA context transfers */ 1849 struct list_head dsd_list; 1850 1851 /* This structure should not exceed 512 bytes */ 1852 }; 1853 1854 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1855 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1856 1857 /* 1858 * ISP queue - status entry structure definition. 1859 */ 1860 #define STATUS_TYPE 0x03 /* Status entry. */ 1861 typedef struct { 1862 uint8_t entry_type; /* Entry type. */ 1863 uint8_t entry_count; /* Entry count. */ 1864 uint8_t sys_define; /* System defined. */ 1865 uint8_t entry_status; /* Entry Status. */ 1866 uint32_t handle; /* System handle. */ 1867 uint16_t scsi_status; /* SCSI status. */ 1868 uint16_t comp_status; /* Completion status. */ 1869 uint16_t state_flags; /* State flags. */ 1870 uint16_t status_flags; /* Status flags. */ 1871 uint16_t rsp_info_len; /* Response Info Length. */ 1872 uint16_t req_sense_length; /* Request sense data length. */ 1873 uint32_t residual_length; /* Residual transfer length. */ 1874 uint8_t rsp_info[8]; /* FCP response information. */ 1875 uint8_t req_sense_data[32]; /* Request sense data. */ 1876 } sts_entry_t; 1877 1878 /* 1879 * Status entry entry status 1880 */ 1881 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1882 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1883 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1884 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1885 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1886 #define RF_BUSY BIT_1 /* Busy */ 1887 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1888 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1889 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1890 RF_INV_E_TYPE) 1891 1892 /* 1893 * Status entry SCSI status bit definitions. 1894 */ 1895 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1896 #define SS_RESIDUAL_UNDER BIT_11 1897 #define SS_RESIDUAL_OVER BIT_10 1898 #define SS_SENSE_LEN_VALID BIT_9 1899 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1900 #define SS_SCSI_STATUS_BYTE 0xff 1901 1902 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1903 #define SS_BUSY_CONDITION BIT_3 1904 #define SS_CONDITION_MET BIT_2 1905 #define SS_CHECK_CONDITION BIT_1 1906 1907 /* 1908 * Status entry completion status 1909 */ 1910 #define CS_COMPLETE 0x0 /* No errors */ 1911 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1912 #define CS_DMA 0x2 /* A DMA direction error. */ 1913 #define CS_TRANSPORT 0x3 /* Transport error. */ 1914 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1915 #define CS_ABORTED 0x5 /* System aborted command. */ 1916 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1917 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1918 #define CS_DIF_ERROR 0xC /* DIF error detected */ 1919 1920 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1921 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1922 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1923 /* (selection timeout) */ 1924 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1925 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1926 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1927 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1928 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 1929 failure */ 1930 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1931 #define CS_UNKNOWN 0x81 /* Driver defined */ 1932 #define CS_RETRY 0x82 /* Driver defined */ 1933 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1934 1935 #define CS_BIDIR_RD_OVERRUN 0x700 1936 #define CS_BIDIR_RD_WR_OVERRUN 0x707 1937 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 1938 #define CS_BIDIR_RD_UNDERRUN 0x1500 1939 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 1940 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 1941 #define CS_BIDIR_DMA 0x200 1942 /* 1943 * Status entry status flags 1944 */ 1945 #define SF_ABTS_TERMINATED BIT_10 1946 #define SF_LOGOUT_SENT BIT_13 1947 1948 /* 1949 * ISP queue - status continuation entry structure definition. 1950 */ 1951 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1952 typedef struct { 1953 uint8_t entry_type; /* Entry type. */ 1954 uint8_t entry_count; /* Entry count. */ 1955 uint8_t sys_define; /* System defined. */ 1956 uint8_t entry_status; /* Entry Status. */ 1957 uint8_t data[60]; /* data */ 1958 } sts_cont_entry_t; 1959 1960 /* 1961 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1962 * structure definition. 1963 */ 1964 #define STATUS_TYPE_21 0x21 /* Status entry. */ 1965 typedef struct { 1966 uint8_t entry_type; /* Entry type. */ 1967 uint8_t entry_count; /* Entry count. */ 1968 uint8_t handle_count; /* Handle count. */ 1969 uint8_t entry_status; /* Entry Status. */ 1970 uint32_t handle[15]; /* System handles. */ 1971 } sts21_entry_t; 1972 1973 /* 1974 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1975 * structure definition. 1976 */ 1977 #define STATUS_TYPE_22 0x22 /* Status entry. */ 1978 typedef struct { 1979 uint8_t entry_type; /* Entry type. */ 1980 uint8_t entry_count; /* Entry count. */ 1981 uint8_t handle_count; /* Handle count. */ 1982 uint8_t entry_status; /* Entry Status. */ 1983 uint16_t handle[30]; /* System handles. */ 1984 } sts22_entry_t; 1985 1986 /* 1987 * ISP queue - marker entry structure definition. 1988 */ 1989 #define MARKER_TYPE 0x04 /* Marker entry. */ 1990 typedef struct { 1991 uint8_t entry_type; /* Entry type. */ 1992 uint8_t entry_count; /* Entry count. */ 1993 uint8_t handle_count; /* Handle count. */ 1994 uint8_t entry_status; /* Entry Status. */ 1995 uint32_t sys_define_2; /* System defined. */ 1996 target_id_t target; /* SCSI ID */ 1997 uint8_t modifier; /* Modifier (7-0). */ 1998 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1999 #define MK_SYNC_ID 1 /* Synchronize ID */ 2000 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2001 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2002 /* clear port changed, */ 2003 /* use sequence number. */ 2004 uint8_t reserved_1; 2005 uint16_t sequence_number; /* Sequence number of event */ 2006 uint16_t lun; /* SCSI LUN */ 2007 uint8_t reserved_2[48]; 2008 } mrk_entry_t; 2009 2010 /* 2011 * ISP queue - Management Server entry structure definition. 2012 */ 2013 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2014 typedef struct { 2015 uint8_t entry_type; /* Entry type. */ 2016 uint8_t entry_count; /* Entry count. */ 2017 uint8_t handle_count; /* Handle count. */ 2018 uint8_t entry_status; /* Entry Status. */ 2019 uint32_t handle1; /* System handle. */ 2020 target_id_t loop_id; 2021 uint16_t status; 2022 uint16_t control_flags; /* Control flags. */ 2023 uint16_t reserved2; 2024 uint16_t timeout; 2025 uint16_t cmd_dsd_count; 2026 uint16_t total_dsd_count; 2027 uint8_t type; 2028 uint8_t r_ctl; 2029 uint16_t rx_id; 2030 uint16_t reserved3; 2031 uint32_t handle2; 2032 uint32_t rsp_bytecount; 2033 uint32_t req_bytecount; 2034 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 2035 uint32_t dseg_req_length; /* Data segment 0 length. */ 2036 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 2037 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 2038 } ms_iocb_entry_t; 2039 2040 2041 /* 2042 * ISP queue - Mailbox Command entry structure definition. 2043 */ 2044 #define MBX_IOCB_TYPE 0x39 2045 struct mbx_entry { 2046 uint8_t entry_type; 2047 uint8_t entry_count; 2048 uint8_t sys_define1; 2049 /* Use sys_define1 for source type */ 2050 #define SOURCE_SCSI 0x00 2051 #define SOURCE_IP 0x01 2052 #define SOURCE_VI 0x02 2053 #define SOURCE_SCTP 0x03 2054 #define SOURCE_MP 0x04 2055 #define SOURCE_MPIOCTL 0x05 2056 #define SOURCE_ASYNC_IOCB 0x07 2057 2058 uint8_t entry_status; 2059 2060 uint32_t handle; 2061 target_id_t loop_id; 2062 2063 uint16_t status; 2064 uint16_t state_flags; 2065 uint16_t status_flags; 2066 2067 uint32_t sys_define2[2]; 2068 2069 uint16_t mb0; 2070 uint16_t mb1; 2071 uint16_t mb2; 2072 uint16_t mb3; 2073 uint16_t mb6; 2074 uint16_t mb7; 2075 uint16_t mb9; 2076 uint16_t mb10; 2077 uint32_t reserved_2[2]; 2078 uint8_t node_name[WWN_SIZE]; 2079 uint8_t port_name[WWN_SIZE]; 2080 }; 2081 2082 #ifndef IMMED_NOTIFY_TYPE 2083 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2084 /* 2085 * ISP queue - immediate notify entry structure definition. 2086 * This is sent by the ISP to the Target driver. 2087 * This IOCB would have report of events sent by the 2088 * initiator, that needs to be handled by the target 2089 * driver immediately. 2090 */ 2091 struct imm_ntfy_from_isp { 2092 uint8_t entry_type; /* Entry type. */ 2093 uint8_t entry_count; /* Entry count. */ 2094 uint8_t sys_define; /* System defined. */ 2095 uint8_t entry_status; /* Entry Status. */ 2096 union { 2097 struct { 2098 uint32_t sys_define_2; /* System defined. */ 2099 target_id_t target; 2100 uint16_t lun; 2101 uint8_t target_id; 2102 uint8_t reserved_1; 2103 uint16_t status_modifier; 2104 uint16_t status; 2105 uint16_t task_flags; 2106 uint16_t seq_id; 2107 uint16_t srr_rx_id; 2108 uint32_t srr_rel_offs; 2109 uint16_t srr_ui; 2110 #define SRR_IU_DATA_IN 0x1 2111 #define SRR_IU_DATA_OUT 0x5 2112 #define SRR_IU_STATUS 0x7 2113 uint16_t srr_ox_id; 2114 uint8_t reserved_2[28]; 2115 } isp2x; 2116 struct { 2117 uint32_t reserved; 2118 uint16_t nport_handle; 2119 uint16_t reserved_2; 2120 uint16_t flags; 2121 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2122 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2123 uint16_t srr_rx_id; 2124 uint16_t status; 2125 uint8_t status_subcode; 2126 uint8_t fw_handle; 2127 uint32_t exchange_address; 2128 uint32_t srr_rel_offs; 2129 uint16_t srr_ui; 2130 uint16_t srr_ox_id; 2131 union { 2132 struct { 2133 uint8_t node_name[8]; 2134 } plogi; /* PLOGI/ADISC/PDISC */ 2135 struct { 2136 /* PRLI word 3 bit 0-15 */ 2137 uint16_t wd3_lo; 2138 uint8_t resv0[6]; 2139 } prli; 2140 struct { 2141 uint8_t port_id[3]; 2142 uint8_t resv1; 2143 uint16_t nport_handle; 2144 uint16_t resv2; 2145 } req_els; 2146 } u; 2147 uint8_t port_name[8]; 2148 uint8_t resv3[3]; 2149 uint8_t vp_index; 2150 uint32_t reserved_5; 2151 uint8_t port_id[3]; 2152 uint8_t reserved_6; 2153 } isp24; 2154 } u; 2155 uint16_t reserved_7; 2156 uint16_t ox_id; 2157 } __packed; 2158 #endif 2159 2160 /* 2161 * ISP request and response queue entry sizes 2162 */ 2163 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2164 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2165 2166 2167 /* 2168 * 24 bit port ID type definition. 2169 */ 2170 typedef union { 2171 uint32_t b24 : 24; 2172 2173 struct { 2174 #ifdef __BIG_ENDIAN 2175 uint8_t domain; 2176 uint8_t area; 2177 uint8_t al_pa; 2178 #elif defined(__LITTLE_ENDIAN) 2179 uint8_t al_pa; 2180 uint8_t area; 2181 uint8_t domain; 2182 #else 2183 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 2184 #endif 2185 uint8_t rsvd_1; 2186 } b; 2187 } port_id_t; 2188 #define INVALID_PORT_ID 0xFFFFFF 2189 2190 /* 2191 * Switch info gathering structure. 2192 */ 2193 typedef struct { 2194 port_id_t d_id; 2195 uint8_t node_name[WWN_SIZE]; 2196 uint8_t port_name[WWN_SIZE]; 2197 uint8_t fabric_port_name[WWN_SIZE]; 2198 uint16_t fp_speed; 2199 uint8_t fc4_type; 2200 uint8_t fc4f_nvme; /* nvme fc4 feature bits */ 2201 } sw_info_t; 2202 2203 /* FCP-4 types */ 2204 #define FC4_TYPE_FCP_SCSI 0x08 2205 #define FC4_TYPE_OTHER 0x0 2206 #define FC4_TYPE_UNKNOWN 0xff 2207 2208 /* mailbox command 4G & above */ 2209 struct mbx_24xx_entry { 2210 uint8_t entry_type; 2211 uint8_t entry_count; 2212 uint8_t sys_define1; 2213 uint8_t entry_status; 2214 uint32_t handle; 2215 uint16_t mb[28]; 2216 }; 2217 2218 #define IOCB_SIZE 64 2219 2220 /* 2221 * Fibre channel port type. 2222 */ 2223 typedef enum { 2224 FCT_UNKNOWN, 2225 FCT_RSCN, 2226 FCT_SWITCH, 2227 FCT_BROADCAST, 2228 FCT_INITIATOR, 2229 FCT_TARGET, 2230 FCT_NVME 2231 } fc_port_type_t; 2232 2233 enum qla_sess_deletion { 2234 QLA_SESS_DELETION_NONE = 0, 2235 QLA_SESS_DELETION_IN_PROGRESS, 2236 QLA_SESS_DELETED, 2237 }; 2238 2239 enum qlt_plogi_link_t { 2240 QLT_PLOGI_LINK_SAME_WWN, 2241 QLT_PLOGI_LINK_CONFLICT, 2242 QLT_PLOGI_LINK_MAX 2243 }; 2244 2245 struct qlt_plogi_ack_t { 2246 struct list_head list; 2247 struct imm_ntfy_from_isp iocb; 2248 port_id_t id; 2249 int ref_count; 2250 void *fcport; 2251 }; 2252 2253 struct ct_sns_desc { 2254 struct ct_sns_pkt *ct_sns; 2255 dma_addr_t ct_sns_dma; 2256 }; 2257 2258 enum discovery_state { 2259 DSC_DELETED, 2260 DSC_GID_PN, 2261 DSC_GNL, 2262 DSC_LOGIN_PEND, 2263 DSC_LOGIN_FAILED, 2264 DSC_GPDB, 2265 DSC_GPSC, 2266 DSC_UPD_FCPORT, 2267 DSC_LOGIN_COMPLETE, 2268 DSC_DELETE_PEND, 2269 }; 2270 2271 enum login_state { /* FW control Target side */ 2272 DSC_LS_LLIOCB_SENT = 2, 2273 DSC_LS_PLOGI_PEND, 2274 DSC_LS_PLOGI_COMP, 2275 DSC_LS_PRLI_PEND, 2276 DSC_LS_PRLI_COMP, 2277 DSC_LS_PORT_UNAVAIL, 2278 DSC_LS_PRLO_PEND = 9, 2279 DSC_LS_LOGO_PEND, 2280 }; 2281 2282 enum fcport_mgt_event { 2283 FCME_RELOGIN = 1, 2284 FCME_RSCN, 2285 FCME_GIDPN_DONE, 2286 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */ 2287 FCME_PRLI_DONE, 2288 FCME_GNL_DONE, 2289 FCME_GPSC_DONE, 2290 FCME_GPDB_DONE, 2291 FCME_GPNID_DONE, 2292 FCME_GFFID_DONE, 2293 FCME_DELETE_DONE, 2294 }; 2295 2296 enum rscn_addr_format { 2297 RSCN_PORT_ADDR, 2298 RSCN_AREA_ADDR, 2299 RSCN_DOM_ADDR, 2300 RSCN_FAB_ADDR, 2301 }; 2302 2303 /* 2304 * Fibre channel port structure. 2305 */ 2306 typedef struct fc_port { 2307 struct list_head list; 2308 struct scsi_qla_host *vha; 2309 2310 uint8_t node_name[WWN_SIZE]; 2311 uint8_t port_name[WWN_SIZE]; 2312 port_id_t d_id; 2313 uint16_t loop_id; 2314 uint16_t old_loop_id; 2315 2316 unsigned int conf_compl_supported:1; 2317 unsigned int deleted:2; 2318 unsigned int local:1; 2319 unsigned int logout_on_delete:1; 2320 unsigned int logo_ack_needed:1; 2321 unsigned int keep_nport_handle:1; 2322 unsigned int send_els_logo:1; 2323 unsigned int login_pause:1; 2324 unsigned int login_succ:1; 2325 unsigned int query:1; 2326 2327 struct work_struct nvme_del_work; 2328 struct completion nvme_del_done; 2329 uint32_t nvme_prli_service_param; 2330 #define NVME_PRLI_SP_CONF BIT_7 2331 #define NVME_PRLI_SP_INITIATOR BIT_5 2332 #define NVME_PRLI_SP_TARGET BIT_4 2333 #define NVME_PRLI_SP_DISCOVERY BIT_3 2334 uint8_t nvme_flag; 2335 #define NVME_FLAG_REGISTERED 4 2336 2337 struct fc_port *conflict; 2338 unsigned char logout_completed; 2339 int generation; 2340 2341 struct se_session *se_sess; 2342 struct kref sess_kref; 2343 struct qla_tgt *tgt; 2344 unsigned long expires; 2345 struct list_head del_list_entry; 2346 struct work_struct free_work; 2347 2348 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2349 2350 uint16_t tgt_id; 2351 uint16_t old_tgt_id; 2352 2353 uint8_t fcp_prio; 2354 2355 uint8_t fabric_port_name[WWN_SIZE]; 2356 uint16_t fp_speed; 2357 2358 fc_port_type_t port_type; 2359 2360 atomic_t state; 2361 uint32_t flags; 2362 2363 int login_retry; 2364 2365 struct fc_rport *rport, *drport; 2366 u32 supported_classes; 2367 2368 uint8_t fc4_type; 2369 uint8_t fc4f_nvme; 2370 uint8_t scan_state; 2371 uint8_t n2n_flag; 2372 2373 unsigned long last_queue_full; 2374 unsigned long last_ramp_up; 2375 2376 uint16_t port_id; 2377 2378 struct nvme_fc_remote_port *nvme_remote_port; 2379 2380 unsigned long retry_delay_timestamp; 2381 struct qla_tgt_sess *tgt_session; 2382 struct ct_sns_desc ct_desc; 2383 enum discovery_state disc_state; 2384 enum login_state fw_login_state; 2385 unsigned long plogi_nack_done_deadline; 2386 2387 u32 login_gen, last_login_gen; 2388 u32 rscn_gen, last_rscn_gen; 2389 u32 chip_reset; 2390 struct list_head gnl_entry; 2391 struct work_struct del_work; 2392 u8 iocb[IOCB_SIZE]; 2393 u8 current_login_state; 2394 u8 last_login_state; 2395 struct completion n2n_done; 2396 } fc_port_t; 2397 2398 #define QLA_FCPORT_SCAN 1 2399 #define QLA_FCPORT_FOUND 2 2400 2401 struct event_arg { 2402 enum fcport_mgt_event event; 2403 fc_port_t *fcport; 2404 srb_t *sp; 2405 port_id_t id; 2406 u16 data[2], rc; 2407 u8 port_name[WWN_SIZE]; 2408 u32 iop[2]; 2409 }; 2410 2411 #include "qla_mr.h" 2412 2413 /* 2414 * Fibre channel port/lun states. 2415 */ 2416 #define FCS_UNCONFIGURED 1 2417 #define FCS_DEVICE_DEAD 2 2418 #define FCS_DEVICE_LOST 3 2419 #define FCS_ONLINE 4 2420 2421 static const char * const port_state_str[] = { 2422 "Unknown", 2423 "UNCONFIGURED", 2424 "DEAD", 2425 "LOST", 2426 "ONLINE" 2427 }; 2428 2429 /* 2430 * FC port flags. 2431 */ 2432 #define FCF_FABRIC_DEVICE BIT_0 2433 #define FCF_LOGIN_NEEDED BIT_1 2434 #define FCF_FCP2_DEVICE BIT_2 2435 #define FCF_ASYNC_SENT BIT_3 2436 #define FCF_CONF_COMP_SUPPORTED BIT_4 2437 2438 /* No loop ID flag. */ 2439 #define FC_NO_LOOP_ID 0x1000 2440 2441 /* 2442 * FC-CT interface 2443 * 2444 * NOTE: All structures are big-endian in form. 2445 */ 2446 2447 #define CT_REJECT_RESPONSE 0x8001 2448 #define CT_ACCEPT_RESPONSE 0x8002 2449 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2450 #define CT_REASON_CANNOT_PERFORM 0x09 2451 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2452 #define CT_EXPL_ALREADY_REGISTERED 0x10 2453 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2454 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2455 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2456 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2457 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2458 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2459 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2460 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2461 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2462 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2463 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2464 2465 #define NS_N_PORT_TYPE 0x01 2466 #define NS_NL_PORT_TYPE 0x02 2467 #define NS_NX_PORT_TYPE 0x7F 2468 2469 #define GA_NXT_CMD 0x100 2470 #define GA_NXT_REQ_SIZE (16 + 4) 2471 #define GA_NXT_RSP_SIZE (16 + 620) 2472 2473 #define GID_PT_CMD 0x1A1 2474 #define GID_PT_REQ_SIZE (16 + 4) 2475 2476 #define GPN_ID_CMD 0x112 2477 #define GPN_ID_REQ_SIZE (16 + 4) 2478 #define GPN_ID_RSP_SIZE (16 + 8) 2479 2480 #define GNN_ID_CMD 0x113 2481 #define GNN_ID_REQ_SIZE (16 + 4) 2482 #define GNN_ID_RSP_SIZE (16 + 8) 2483 2484 #define GFT_ID_CMD 0x117 2485 #define GFT_ID_REQ_SIZE (16 + 4) 2486 #define GFT_ID_RSP_SIZE (16 + 32) 2487 2488 #define GID_PN_CMD 0x121 2489 #define GID_PN_REQ_SIZE (16 + 8) 2490 #define GID_PN_RSP_SIZE (16 + 4) 2491 2492 #define RFT_ID_CMD 0x217 2493 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2494 #define RFT_ID_RSP_SIZE 16 2495 2496 #define RFF_ID_CMD 0x21F 2497 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2498 #define RFF_ID_RSP_SIZE 16 2499 2500 #define RNN_ID_CMD 0x213 2501 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2502 #define RNN_ID_RSP_SIZE 16 2503 2504 #define RSNN_NN_CMD 0x239 2505 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2506 #define RSNN_NN_RSP_SIZE 16 2507 2508 #define GFPN_ID_CMD 0x11C 2509 #define GFPN_ID_REQ_SIZE (16 + 4) 2510 #define GFPN_ID_RSP_SIZE (16 + 8) 2511 2512 #define GPSC_CMD 0x127 2513 #define GPSC_REQ_SIZE (16 + 8) 2514 #define GPSC_RSP_SIZE (16 + 2 + 2) 2515 2516 #define GFF_ID_CMD 0x011F 2517 #define GFF_ID_REQ_SIZE (16 + 4) 2518 #define GFF_ID_RSP_SIZE (16 + 128) 2519 2520 /* 2521 * HBA attribute types. 2522 */ 2523 #define FDMI_HBA_ATTR_COUNT 9 2524 #define FDMIV2_HBA_ATTR_COUNT 17 2525 #define FDMI_HBA_NODE_NAME 0x1 2526 #define FDMI_HBA_MANUFACTURER 0x2 2527 #define FDMI_HBA_SERIAL_NUMBER 0x3 2528 #define FDMI_HBA_MODEL 0x4 2529 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2530 #define FDMI_HBA_HARDWARE_VERSION 0x6 2531 #define FDMI_HBA_DRIVER_VERSION 0x7 2532 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2533 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2534 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2535 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2536 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2537 #define FDMI_HBA_VENDOR_ID 0xd 2538 #define FDMI_HBA_NUM_PORTS 0xe 2539 #define FDMI_HBA_FABRIC_NAME 0xf 2540 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2541 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0 2542 2543 struct ct_fdmi_hba_attr { 2544 uint16_t type; 2545 uint16_t len; 2546 union { 2547 uint8_t node_name[WWN_SIZE]; 2548 uint8_t manufacturer[64]; 2549 uint8_t serial_num[32]; 2550 uint8_t model[16+1]; 2551 uint8_t model_desc[80]; 2552 uint8_t hw_version[32]; 2553 uint8_t driver_version[32]; 2554 uint8_t orom_version[16]; 2555 uint8_t fw_version[32]; 2556 uint8_t os_version[128]; 2557 uint32_t max_ct_len; 2558 } a; 2559 }; 2560 2561 struct ct_fdmi_hba_attributes { 2562 uint32_t count; 2563 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2564 }; 2565 2566 struct ct_fdmiv2_hba_attr { 2567 uint16_t type; 2568 uint16_t len; 2569 union { 2570 uint8_t node_name[WWN_SIZE]; 2571 uint8_t manufacturer[64]; 2572 uint8_t serial_num[32]; 2573 uint8_t model[16+1]; 2574 uint8_t model_desc[80]; 2575 uint8_t hw_version[16]; 2576 uint8_t driver_version[32]; 2577 uint8_t orom_version[16]; 2578 uint8_t fw_version[32]; 2579 uint8_t os_version[128]; 2580 uint32_t max_ct_len; 2581 uint8_t sym_name[256]; 2582 uint32_t vendor_id; 2583 uint32_t num_ports; 2584 uint8_t fabric_name[WWN_SIZE]; 2585 uint8_t bios_name[32]; 2586 uint8_t vendor_identifier[8]; 2587 } a; 2588 }; 2589 2590 struct ct_fdmiv2_hba_attributes { 2591 uint32_t count; 2592 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT]; 2593 }; 2594 2595 /* 2596 * Port attribute types. 2597 */ 2598 #define FDMI_PORT_ATTR_COUNT 6 2599 #define FDMIV2_PORT_ATTR_COUNT 16 2600 #define FDMI_PORT_FC4_TYPES 0x1 2601 #define FDMI_PORT_SUPPORT_SPEED 0x2 2602 #define FDMI_PORT_CURRENT_SPEED 0x3 2603 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2604 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2605 #define FDMI_PORT_HOST_NAME 0x6 2606 #define FDMI_PORT_NODE_NAME 0x7 2607 #define FDMI_PORT_NAME 0x8 2608 #define FDMI_PORT_SYM_NAME 0x9 2609 #define FDMI_PORT_TYPE 0xa 2610 #define FDMI_PORT_SUPP_COS 0xb 2611 #define FDMI_PORT_FABRIC_NAME 0xc 2612 #define FDMI_PORT_FC4_TYPE 0xd 2613 #define FDMI_PORT_STATE 0x101 2614 #define FDMI_PORT_COUNT 0x102 2615 #define FDMI_PORT_ID 0x103 2616 2617 #define FDMI_PORT_SPEED_1GB 0x1 2618 #define FDMI_PORT_SPEED_2GB 0x2 2619 #define FDMI_PORT_SPEED_10GB 0x4 2620 #define FDMI_PORT_SPEED_4GB 0x8 2621 #define FDMI_PORT_SPEED_8GB 0x10 2622 #define FDMI_PORT_SPEED_16GB 0x20 2623 #define FDMI_PORT_SPEED_32GB 0x40 2624 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2625 2626 #define FC_CLASS_2 0x04 2627 #define FC_CLASS_3 0x08 2628 #define FC_CLASS_2_3 0x0C 2629 2630 struct ct_fdmiv2_port_attr { 2631 uint16_t type; 2632 uint16_t len; 2633 union { 2634 uint8_t fc4_types[32]; 2635 uint32_t sup_speed; 2636 uint32_t cur_speed; 2637 uint32_t max_frame_size; 2638 uint8_t os_dev_name[32]; 2639 uint8_t host_name[256]; 2640 uint8_t node_name[WWN_SIZE]; 2641 uint8_t port_name[WWN_SIZE]; 2642 uint8_t port_sym_name[128]; 2643 uint32_t port_type; 2644 uint32_t port_supported_cos; 2645 uint8_t fabric_name[WWN_SIZE]; 2646 uint8_t port_fc4_type[32]; 2647 uint32_t port_state; 2648 uint32_t num_ports; 2649 uint32_t port_id; 2650 } a; 2651 }; 2652 2653 /* 2654 * Port Attribute Block. 2655 */ 2656 struct ct_fdmiv2_port_attributes { 2657 uint32_t count; 2658 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT]; 2659 }; 2660 2661 struct ct_fdmi_port_attr { 2662 uint16_t type; 2663 uint16_t len; 2664 union { 2665 uint8_t fc4_types[32]; 2666 uint32_t sup_speed; 2667 uint32_t cur_speed; 2668 uint32_t max_frame_size; 2669 uint8_t os_dev_name[32]; 2670 uint8_t host_name[256]; 2671 } a; 2672 }; 2673 2674 struct ct_fdmi_port_attributes { 2675 uint32_t count; 2676 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2677 }; 2678 2679 /* FDMI definitions. */ 2680 #define GRHL_CMD 0x100 2681 #define GHAT_CMD 0x101 2682 #define GRPL_CMD 0x102 2683 #define GPAT_CMD 0x110 2684 2685 #define RHBA_CMD 0x200 2686 #define RHBA_RSP_SIZE 16 2687 2688 #define RHAT_CMD 0x201 2689 #define RPRT_CMD 0x210 2690 2691 #define RPA_CMD 0x211 2692 #define RPA_RSP_SIZE 16 2693 2694 #define DHBA_CMD 0x300 2695 #define DHBA_REQ_SIZE (16 + 8) 2696 #define DHBA_RSP_SIZE 16 2697 2698 #define DHAT_CMD 0x301 2699 #define DPRT_CMD 0x310 2700 #define DPA_CMD 0x311 2701 2702 /* CT command header -- request/response common fields */ 2703 struct ct_cmd_hdr { 2704 uint8_t revision; 2705 uint8_t in_id[3]; 2706 uint8_t gs_type; 2707 uint8_t gs_subtype; 2708 uint8_t options; 2709 uint8_t reserved; 2710 }; 2711 2712 /* CT command request */ 2713 struct ct_sns_req { 2714 struct ct_cmd_hdr header; 2715 uint16_t command; 2716 uint16_t max_rsp_size; 2717 uint8_t fragment_id; 2718 uint8_t reserved[3]; 2719 2720 union { 2721 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2722 struct { 2723 uint8_t reserved; 2724 uint8_t port_id[3]; 2725 } port_id; 2726 2727 struct { 2728 uint8_t port_type; 2729 uint8_t domain; 2730 uint8_t area; 2731 uint8_t reserved; 2732 } gid_pt; 2733 2734 struct { 2735 uint8_t reserved; 2736 uint8_t port_id[3]; 2737 uint8_t fc4_types[32]; 2738 } rft_id; 2739 2740 struct { 2741 uint8_t reserved; 2742 uint8_t port_id[3]; 2743 uint16_t reserved2; 2744 uint8_t fc4_feature; 2745 uint8_t fc4_type; 2746 } rff_id; 2747 2748 struct { 2749 uint8_t reserved; 2750 uint8_t port_id[3]; 2751 uint8_t node_name[8]; 2752 } rnn_id; 2753 2754 struct { 2755 uint8_t node_name[8]; 2756 uint8_t name_len; 2757 uint8_t sym_node_name[255]; 2758 } rsnn_nn; 2759 2760 struct { 2761 uint8_t hba_identifier[8]; 2762 } ghat; 2763 2764 struct { 2765 uint8_t hba_identifier[8]; 2766 uint32_t entry_count; 2767 uint8_t port_name[8]; 2768 struct ct_fdmi_hba_attributes attrs; 2769 } rhba; 2770 2771 struct { 2772 uint8_t hba_identifier[8]; 2773 uint32_t entry_count; 2774 uint8_t port_name[8]; 2775 struct ct_fdmiv2_hba_attributes attrs; 2776 } rhba2; 2777 2778 struct { 2779 uint8_t hba_identifier[8]; 2780 struct ct_fdmi_hba_attributes attrs; 2781 } rhat; 2782 2783 struct { 2784 uint8_t port_name[8]; 2785 struct ct_fdmi_port_attributes attrs; 2786 } rpa; 2787 2788 struct { 2789 uint8_t port_name[8]; 2790 struct ct_fdmiv2_port_attributes attrs; 2791 } rpa2; 2792 2793 struct { 2794 uint8_t port_name[8]; 2795 } dhba; 2796 2797 struct { 2798 uint8_t port_name[8]; 2799 } dhat; 2800 2801 struct { 2802 uint8_t port_name[8]; 2803 } dprt; 2804 2805 struct { 2806 uint8_t port_name[8]; 2807 } dpa; 2808 2809 struct { 2810 uint8_t port_name[8]; 2811 } gpsc; 2812 2813 struct { 2814 uint8_t reserved; 2815 uint8_t port_id[3]; 2816 } gff_id; 2817 2818 struct { 2819 uint8_t port_name[8]; 2820 } gid_pn; 2821 } req; 2822 }; 2823 2824 /* CT command response header */ 2825 struct ct_rsp_hdr { 2826 struct ct_cmd_hdr header; 2827 uint16_t response; 2828 uint16_t residual; 2829 uint8_t fragment_id; 2830 uint8_t reason_code; 2831 uint8_t explanation_code; 2832 uint8_t vendor_unique; 2833 }; 2834 2835 struct ct_sns_gid_pt_data { 2836 uint8_t control_byte; 2837 uint8_t port_id[3]; 2838 }; 2839 2840 struct ct_sns_rsp { 2841 struct ct_rsp_hdr header; 2842 2843 union { 2844 struct { 2845 uint8_t port_type; 2846 uint8_t port_id[3]; 2847 uint8_t port_name[8]; 2848 uint8_t sym_port_name_len; 2849 uint8_t sym_port_name[255]; 2850 uint8_t node_name[8]; 2851 uint8_t sym_node_name_len; 2852 uint8_t sym_node_name[255]; 2853 uint8_t init_proc_assoc[8]; 2854 uint8_t node_ip_addr[16]; 2855 uint8_t class_of_service[4]; 2856 uint8_t fc4_types[32]; 2857 uint8_t ip_address[16]; 2858 uint8_t fabric_port_name[8]; 2859 uint8_t reserved; 2860 uint8_t hard_address[3]; 2861 } ga_nxt; 2862 2863 struct { 2864 /* Assume the largest number of targets for the union */ 2865 struct ct_sns_gid_pt_data 2866 entries[MAX_FIBRE_DEVICES_MAX]; 2867 } gid_pt; 2868 2869 struct { 2870 uint8_t port_name[8]; 2871 } gpn_id; 2872 2873 struct { 2874 uint8_t node_name[8]; 2875 } gnn_id; 2876 2877 struct { 2878 uint8_t fc4_types[32]; 2879 } gft_id; 2880 2881 struct { 2882 uint32_t entry_count; 2883 uint8_t port_name[8]; 2884 struct ct_fdmi_hba_attributes attrs; 2885 } ghat; 2886 2887 struct { 2888 uint8_t port_name[8]; 2889 } gfpn_id; 2890 2891 struct { 2892 uint16_t speeds; 2893 uint16_t speed; 2894 } gpsc; 2895 2896 #define GFF_FCP_SCSI_OFFSET 7 2897 #define GFF_NVME_OFFSET 23 /* type = 28h */ 2898 struct { 2899 uint8_t fc4_features[128]; 2900 } gff_id; 2901 struct { 2902 uint8_t reserved; 2903 uint8_t port_id[3]; 2904 } gid_pn; 2905 } rsp; 2906 }; 2907 2908 struct ct_sns_pkt { 2909 union { 2910 struct ct_sns_req req; 2911 struct ct_sns_rsp rsp; 2912 } p; 2913 }; 2914 2915 /* 2916 * SNS command structures -- for 2200 compatibility. 2917 */ 2918 #define RFT_ID_SNS_SCMD_LEN 22 2919 #define RFT_ID_SNS_CMD_SIZE 60 2920 #define RFT_ID_SNS_DATA_SIZE 16 2921 2922 #define RNN_ID_SNS_SCMD_LEN 10 2923 #define RNN_ID_SNS_CMD_SIZE 36 2924 #define RNN_ID_SNS_DATA_SIZE 16 2925 2926 #define GA_NXT_SNS_SCMD_LEN 6 2927 #define GA_NXT_SNS_CMD_SIZE 28 2928 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 2929 2930 #define GID_PT_SNS_SCMD_LEN 6 2931 #define GID_PT_SNS_CMD_SIZE 28 2932 /* 2933 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 2934 * adapters. 2935 */ 2936 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 2937 2938 #define GPN_ID_SNS_SCMD_LEN 6 2939 #define GPN_ID_SNS_CMD_SIZE 28 2940 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 2941 2942 #define GNN_ID_SNS_SCMD_LEN 6 2943 #define GNN_ID_SNS_CMD_SIZE 28 2944 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 2945 2946 struct sns_cmd_pkt { 2947 union { 2948 struct { 2949 uint16_t buffer_length; 2950 uint16_t reserved_1; 2951 uint32_t buffer_address[2]; 2952 uint16_t subcommand_length; 2953 uint16_t reserved_2; 2954 uint16_t subcommand; 2955 uint16_t size; 2956 uint32_t reserved_3; 2957 uint8_t param[36]; 2958 } cmd; 2959 2960 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 2961 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 2962 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 2963 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 2964 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 2965 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 2966 } p; 2967 }; 2968 2969 struct fw_blob { 2970 char *name; 2971 uint32_t segs[4]; 2972 const struct firmware *fw; 2973 }; 2974 2975 /* Return data from MBC_GET_ID_LIST call. */ 2976 struct gid_list_info { 2977 uint8_t al_pa; 2978 uint8_t area; 2979 uint8_t domain; 2980 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2981 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2982 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 2983 }; 2984 2985 /* NPIV */ 2986 typedef struct vport_info { 2987 uint8_t port_name[WWN_SIZE]; 2988 uint8_t node_name[WWN_SIZE]; 2989 int vp_id; 2990 uint16_t loop_id; 2991 unsigned long host_no; 2992 uint8_t port_id[3]; 2993 int loop_state; 2994 } vport_info_t; 2995 2996 typedef struct vport_params { 2997 uint8_t port_name[WWN_SIZE]; 2998 uint8_t node_name[WWN_SIZE]; 2999 uint32_t options; 3000 #define VP_OPTS_RETRY_ENABLE BIT_0 3001 #define VP_OPTS_VP_DISABLE BIT_1 3002 } vport_params_t; 3003 3004 /* NPIV - return codes of VP create and modify */ 3005 #define VP_RET_CODE_OK 0 3006 #define VP_RET_CODE_FATAL 1 3007 #define VP_RET_CODE_WRONG_ID 2 3008 #define VP_RET_CODE_WWPN 3 3009 #define VP_RET_CODE_RESOURCES 4 3010 #define VP_RET_CODE_NO_MEM 5 3011 #define VP_RET_CODE_NOT_FOUND 6 3012 3013 struct qla_hw_data; 3014 struct rsp_que; 3015 /* 3016 * ISP operations 3017 */ 3018 struct isp_operations { 3019 3020 int (*pci_config) (struct scsi_qla_host *); 3021 void (*reset_chip) (struct scsi_qla_host *); 3022 int (*chip_diag) (struct scsi_qla_host *); 3023 void (*config_rings) (struct scsi_qla_host *); 3024 void (*reset_adapter) (struct scsi_qla_host *); 3025 int (*nvram_config) (struct scsi_qla_host *); 3026 void (*update_fw_options) (struct scsi_qla_host *); 3027 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3028 3029 char * (*pci_info_str) (struct scsi_qla_host *, char *); 3030 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3031 3032 irq_handler_t intr_handler; 3033 void (*enable_intrs) (struct qla_hw_data *); 3034 void (*disable_intrs) (struct qla_hw_data *); 3035 3036 int (*abort_command) (srb_t *); 3037 int (*target_reset) (struct fc_port *, uint64_t, int); 3038 int (*lun_reset) (struct fc_port *, uint64_t, int); 3039 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3040 uint8_t, uint8_t, uint16_t *, uint8_t); 3041 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3042 uint8_t, uint8_t); 3043 3044 uint16_t (*calc_req_entries) (uint16_t); 3045 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3046 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3047 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3048 uint32_t); 3049 3050 uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *, 3051 uint32_t, uint32_t); 3052 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 3053 uint32_t); 3054 3055 void (*fw_dump) (struct scsi_qla_host *, int); 3056 3057 int (*beacon_on) (struct scsi_qla_host *); 3058 int (*beacon_off) (struct scsi_qla_host *); 3059 void (*beacon_blink) (struct scsi_qla_host *); 3060 3061 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 3062 uint32_t, uint32_t); 3063 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 3064 uint32_t); 3065 3066 int (*get_flash_version) (struct scsi_qla_host *, void *); 3067 int (*start_scsi) (srb_t *); 3068 int (*start_scsi_mq) (srb_t *); 3069 int (*abort_isp) (struct scsi_qla_host *); 3070 int (*iospace_config)(struct qla_hw_data*); 3071 int (*initialize_adapter)(struct scsi_qla_host *); 3072 }; 3073 3074 /* MSI-X Support *************************************************************/ 3075 3076 #define QLA_MSIX_CHIP_REV_24XX 3 3077 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3078 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3079 3080 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3081 #define QLA_MSIX_RSP_Q 0x01 3082 #define QLA_ATIO_VECTOR 0x02 3083 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3084 3085 #define QLA_MIDX_DEFAULT 0 3086 #define QLA_MIDX_RSP_Q 1 3087 #define QLA_PCI_MSIX_CONTROL 0xa2 3088 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3089 3090 struct scsi_qla_host; 3091 3092 3093 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3094 3095 struct qla_msix_entry { 3096 int have_irq; 3097 int in_use; 3098 uint32_t vector; 3099 uint16_t entry; 3100 char name[30]; 3101 void *handle; 3102 int cpuid; 3103 }; 3104 3105 #define WATCH_INTERVAL 1 /* number of seconds */ 3106 3107 /* Work events. */ 3108 enum qla_work_type { 3109 QLA_EVT_AEN, 3110 QLA_EVT_IDC_ACK, 3111 QLA_EVT_ASYNC_LOGIN, 3112 QLA_EVT_ASYNC_LOGOUT, 3113 QLA_EVT_ASYNC_LOGOUT_DONE, 3114 QLA_EVT_ASYNC_ADISC, 3115 QLA_EVT_ASYNC_ADISC_DONE, 3116 QLA_EVT_UEVENT, 3117 QLA_EVT_AENFX, 3118 QLA_EVT_GIDPN, 3119 QLA_EVT_GPNID, 3120 QLA_EVT_GPNID_DONE, 3121 QLA_EVT_NEW_SESS, 3122 QLA_EVT_GPDB, 3123 QLA_EVT_PRLI, 3124 QLA_EVT_GPSC, 3125 QLA_EVT_UPD_FCPORT, 3126 QLA_EVT_GNL, 3127 QLA_EVT_NACK, 3128 }; 3129 3130 3131 struct qla_work_evt { 3132 struct list_head list; 3133 enum qla_work_type type; 3134 u32 flags; 3135 #define QLA_EVT_FLAG_FREE 0x1 3136 3137 union { 3138 struct { 3139 enum fc_host_event_code code; 3140 u32 data; 3141 } aen; 3142 struct { 3143 #define QLA_IDC_ACK_REGS 7 3144 uint16_t mb[QLA_IDC_ACK_REGS]; 3145 } idc_ack; 3146 struct { 3147 struct fc_port *fcport; 3148 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3149 u16 data[2]; 3150 } logio; 3151 struct { 3152 u32 code; 3153 #define QLA_UEVENT_CODE_FW_DUMP 0 3154 } uevent; 3155 struct { 3156 uint32_t evtcode; 3157 uint32_t mbx[8]; 3158 uint32_t count; 3159 } aenfx; 3160 struct { 3161 srb_t *sp; 3162 } iosb; 3163 struct { 3164 port_id_t id; 3165 } gpnid; 3166 struct { 3167 port_id_t id; 3168 u8 port_name[8]; 3169 void *pla; 3170 } new_sess; 3171 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */ 3172 fc_port_t *fcport; 3173 u8 opt; 3174 } fcport; 3175 struct { 3176 fc_port_t *fcport; 3177 u8 iocb[IOCB_SIZE]; 3178 int type; 3179 } nack; 3180 } u; 3181 }; 3182 3183 struct qla_chip_state_84xx { 3184 struct list_head list; 3185 struct kref kref; 3186 3187 void *bus; 3188 spinlock_t access_lock; 3189 struct mutex fw_update_mutex; 3190 uint32_t fw_update; 3191 uint32_t op_fw_version; 3192 uint32_t op_fw_size; 3193 uint32_t op_fw_seq_size; 3194 uint32_t diag_fw_version; 3195 uint32_t gold_fw_version; 3196 }; 3197 3198 struct qla_dif_statistics { 3199 uint64_t dif_input_bytes; 3200 uint64_t dif_output_bytes; 3201 uint64_t dif_input_requests; 3202 uint64_t dif_output_requests; 3203 uint32_t dif_guard_err; 3204 uint32_t dif_ref_tag_err; 3205 uint32_t dif_app_tag_err; 3206 }; 3207 3208 struct qla_statistics { 3209 uint32_t total_isp_aborts; 3210 uint64_t input_bytes; 3211 uint64_t output_bytes; 3212 uint64_t input_requests; 3213 uint64_t output_requests; 3214 uint32_t control_requests; 3215 3216 uint64_t jiffies_at_last_reset; 3217 uint32_t stat_max_pend_cmds; 3218 uint32_t stat_max_qfull_cmds_alloc; 3219 uint32_t stat_max_qfull_cmds_dropped; 3220 3221 struct qla_dif_statistics qla_dif_stats; 3222 }; 3223 3224 struct bidi_statistics { 3225 unsigned long long io_count; 3226 unsigned long long transfer_bytes; 3227 }; 3228 3229 struct qla_tc_param { 3230 struct scsi_qla_host *vha; 3231 uint32_t blk_sz; 3232 uint32_t bufflen; 3233 struct scatterlist *sg; 3234 struct scatterlist *prot_sg; 3235 struct crc_context *ctx; 3236 uint8_t *ctx_dsd_alloced; 3237 }; 3238 3239 /* Multi queue support */ 3240 #define MBC_INITIALIZE_MULTIQ 0x1f 3241 #define QLA_QUE_PAGE 0X1000 3242 #define QLA_MQ_SIZE 32 3243 #define QLA_MAX_QUEUES 256 3244 #define ISP_QUE_REG(ha, id) \ 3245 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \ 3246 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3247 ((void __iomem *)ha->iobase)) 3248 #define QLA_REQ_QUE_ID(tag) \ 3249 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3250 #define QLA_DEFAULT_QUE_QOS 5 3251 #define QLA_PRECONFIG_VPORTS 32 3252 #define QLA_MAX_VPORTS_QLA24XX 128 3253 #define QLA_MAX_VPORTS_QLA25XX 256 3254 3255 struct qla_tgt_counters { 3256 uint64_t qla_core_sbt_cmd; 3257 uint64_t core_qla_que_buf; 3258 uint64_t qla_core_ret_ctio; 3259 uint64_t core_qla_snd_status; 3260 uint64_t qla_core_ret_sta_ctio; 3261 uint64_t core_qla_free_cmd; 3262 uint64_t num_q_full_sent; 3263 uint64_t num_alloc_iocb_failed; 3264 uint64_t num_term_xchg_sent; 3265 }; 3266 3267 struct qla_qpair; 3268 3269 /* Response queue data structure */ 3270 struct rsp_que { 3271 dma_addr_t dma; 3272 response_t *ring; 3273 response_t *ring_ptr; 3274 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 3275 uint32_t __iomem *rsp_q_out; 3276 uint16_t ring_index; 3277 uint16_t out_ptr; 3278 uint16_t *in_ptr; /* queue shadow in index */ 3279 uint16_t length; 3280 uint16_t options; 3281 uint16_t rid; 3282 uint16_t id; 3283 uint16_t vp_idx; 3284 struct qla_hw_data *hw; 3285 struct qla_msix_entry *msix; 3286 struct req_que *req; 3287 srb_t *status_srb; /* status continuation entry */ 3288 struct qla_qpair *qpair; 3289 3290 dma_addr_t dma_fx00; 3291 response_t *ring_fx00; 3292 uint16_t length_fx00; 3293 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3294 }; 3295 3296 /* Request queue data structure */ 3297 struct req_que { 3298 dma_addr_t dma; 3299 request_t *ring; 3300 request_t *ring_ptr; 3301 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 3302 uint32_t __iomem *req_q_out; 3303 uint16_t ring_index; 3304 uint16_t in_ptr; 3305 uint16_t *out_ptr; /* queue shadow out index */ 3306 uint16_t cnt; 3307 uint16_t length; 3308 uint16_t options; 3309 uint16_t rid; 3310 uint16_t id; 3311 uint16_t qos; 3312 uint16_t vp_idx; 3313 struct rsp_que *rsp; 3314 srb_t **outstanding_cmds; 3315 uint32_t current_outstanding_cmd; 3316 uint16_t num_outstanding_cmds; 3317 int max_q_depth; 3318 3319 dma_addr_t dma_fx00; 3320 request_t *ring_fx00; 3321 uint16_t length_fx00; 3322 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3323 }; 3324 3325 /*Queue pair data structure */ 3326 struct qla_qpair { 3327 spinlock_t qp_lock; 3328 atomic_t ref_count; 3329 uint32_t lun_cnt; 3330 /* 3331 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3332 * legacy code. For other Qpair(s), it will point at qp_lock. 3333 */ 3334 spinlock_t *qp_lock_ptr; 3335 struct scsi_qla_host *vha; 3336 u32 chip_reset; 3337 3338 /* distill these fields down to 'online=0/1' 3339 * ha->flags.eeh_busy 3340 * ha->flags.pci_channel_io_perm_failure 3341 * base_vha->loop_state 3342 */ 3343 uint32_t online:1; 3344 /* move vha->flags.difdix_supported here */ 3345 uint32_t difdix_supported:1; 3346 uint32_t delete_in_progress:1; 3347 uint32_t fw_started:1; 3348 uint32_t enable_class_2:1; 3349 uint32_t enable_explicit_conf:1; 3350 uint32_t use_shadow_reg:1; 3351 3352 uint16_t id; /* qp number used with FW */ 3353 uint16_t vp_idx; /* vport ID */ 3354 mempool_t *srb_mempool; 3355 3356 struct pci_dev *pdev; 3357 void (*reqq_start_iocbs)(struct qla_qpair *); 3358 3359 /* to do: New driver: move queues to here instead of pointers */ 3360 struct req_que *req; 3361 struct rsp_que *rsp; 3362 struct atio_que *atio; 3363 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3364 struct qla_hw_data *hw; 3365 struct work_struct q_work; 3366 struct list_head qp_list_elem; /* vha->qp_list */ 3367 struct list_head hints_list; 3368 struct list_head nvme_done_list; 3369 uint16_t cpuid; 3370 struct qla_tgt_counters tgt_counters; 3371 }; 3372 3373 /* Place holder for FW buffer parameters */ 3374 struct qlfc_fw { 3375 void *fw_buf; 3376 dma_addr_t fw_dma; 3377 uint32_t len; 3378 }; 3379 3380 struct scsi_qlt_host { 3381 void *target_lport_ptr; 3382 struct mutex tgt_mutex; 3383 struct mutex tgt_host_action_mutex; 3384 struct qla_tgt *qla_tgt; 3385 }; 3386 3387 struct qlt_hw_data { 3388 /* Protected by hw lock */ 3389 uint32_t node_name_set:1; 3390 3391 dma_addr_t atio_dma; /* Physical address. */ 3392 struct atio *atio_ring; /* Base virtual address */ 3393 struct atio *atio_ring_ptr; /* Current address. */ 3394 uint16_t atio_ring_index; /* Current index. */ 3395 uint16_t atio_q_length; 3396 uint32_t __iomem *atio_q_in; 3397 uint32_t __iomem *atio_q_out; 3398 3399 struct qla_tgt_func_tmpl *tgt_ops; 3400 struct qla_tgt_vp_map *tgt_vp_map; 3401 3402 int saved_set; 3403 uint16_t saved_exchange_count; 3404 uint32_t saved_firmware_options_1; 3405 uint32_t saved_firmware_options_2; 3406 uint32_t saved_firmware_options_3; 3407 uint8_t saved_firmware_options[2]; 3408 uint8_t saved_add_firmware_options[2]; 3409 3410 uint8_t tgt_node_name[WWN_SIZE]; 3411 3412 struct dentry *dfs_tgt_sess; 3413 struct dentry *dfs_tgt_port_database; 3414 struct dentry *dfs_naqp; 3415 3416 struct list_head q_full_list; 3417 uint32_t num_pend_cmds; 3418 uint32_t num_qfull_cmds_alloc; 3419 uint32_t num_qfull_cmds_dropped; 3420 spinlock_t q_full_lock; 3421 uint32_t leak_exchg_thresh_hold; 3422 spinlock_t sess_lock; 3423 int num_act_qpairs; 3424 #define DEFAULT_NAQP 2 3425 spinlock_t atio_lock ____cacheline_aligned; 3426 struct btree_head32 host_map; 3427 }; 3428 3429 #define MAX_QFULL_CMDS_ALLOC 8192 3430 #define Q_FULL_THRESH_HOLD_PERCENT 90 3431 #define Q_FULL_THRESH_HOLD(ha) \ 3432 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3433 3434 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3435 3436 #define QLA_EARLY_LINKUP(_ha) \ 3437 ((_ha->flags.n2n_ae || _ha->flags.lip_ae) && \ 3438 _ha->flags.fw_started && !_ha->flags.fw_init_done) 3439 3440 /* 3441 * Qlogic host adapter specific data structure. 3442 */ 3443 struct qla_hw_data { 3444 struct pci_dev *pdev; 3445 /* SRB cache. */ 3446 #define SRB_MIN_REQ 128 3447 mempool_t *srb_mempool; 3448 3449 volatile struct { 3450 uint32_t mbox_int :1; 3451 uint32_t mbox_busy :1; 3452 uint32_t disable_risc_code_load :1; 3453 uint32_t enable_64bit_addressing :1; 3454 uint32_t enable_lip_reset :1; 3455 uint32_t enable_target_reset :1; 3456 uint32_t enable_lip_full_login :1; 3457 uint32_t enable_led_scheme :1; 3458 3459 uint32_t msi_enabled :1; 3460 uint32_t msix_enabled :1; 3461 uint32_t disable_serdes :1; 3462 uint32_t gpsc_supported :1; 3463 uint32_t npiv_supported :1; 3464 uint32_t pci_channel_io_perm_failure :1; 3465 uint32_t fce_enabled :1; 3466 uint32_t fac_supported :1; 3467 3468 uint32_t chip_reset_done :1; 3469 uint32_t running_gold_fw :1; 3470 uint32_t eeh_busy :1; 3471 uint32_t disable_msix_handshake :1; 3472 uint32_t fcp_prio_enabled :1; 3473 uint32_t isp82xx_fw_hung:1; 3474 uint32_t nic_core_hung:1; 3475 3476 uint32_t quiesce_owner:1; 3477 uint32_t nic_core_reset_hdlr_active:1; 3478 uint32_t nic_core_reset_owner:1; 3479 uint32_t isp82xx_no_md_cap:1; 3480 uint32_t host_shutting_down:1; 3481 uint32_t idc_compl_status:1; 3482 uint32_t mr_reset_hdlr_active:1; 3483 uint32_t mr_intr_valid:1; 3484 3485 uint32_t dport_enabled:1; 3486 uint32_t fawwpn_enabled:1; 3487 uint32_t exlogins_enabled:1; 3488 uint32_t exchoffld_enabled:1; 3489 3490 uint32_t lip_ae:1; 3491 uint32_t n2n_ae:1; 3492 uint32_t fw_started:1; 3493 uint32_t fw_init_done:1; 3494 3495 uint32_t detected_lr_sfp:1; 3496 uint32_t using_lr_setting:1; 3497 } flags; 3498 3499 uint16_t long_range_distance; /* 32G & above */ 3500 #define LR_DISTANCE_5K 1 3501 #define LR_DISTANCE_10K 0 3502 3503 /* This spinlock is used to protect "io transactions", you must 3504 * acquire it before doing any IO to the card, eg with RD_REG*() and 3505 * WRT_REG*() for the duration of your entire commandtransaction. 3506 * 3507 * This spinlock is of lower priority than the io request lock. 3508 */ 3509 3510 spinlock_t hardware_lock ____cacheline_aligned; 3511 int bars; 3512 int mem_only; 3513 device_reg_t *iobase; /* Base I/O address */ 3514 resource_size_t pio_address; 3515 3516 #define MIN_IOBASE_LEN 0x100 3517 dma_addr_t bar0_hdl; 3518 3519 void __iomem *cregbase; 3520 dma_addr_t bar2_hdl; 3521 #define BAR0_LEN_FX00 (1024 * 1024) 3522 #define BAR2_LEN_FX00 (128 * 1024) 3523 3524 uint32_t rqstq_intr_code; 3525 uint32_t mbx_intr_code; 3526 uint32_t req_que_len; 3527 uint32_t rsp_que_len; 3528 uint32_t req_que_off; 3529 uint32_t rsp_que_off; 3530 3531 /* Multi queue data structs */ 3532 device_reg_t *mqiobase; 3533 device_reg_t *msixbase; 3534 uint16_t msix_count; 3535 uint8_t mqenable; 3536 struct req_que **req_q_map; 3537 struct rsp_que **rsp_q_map; 3538 struct qla_qpair **queue_pair_map; 3539 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3540 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3541 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 3542 / sizeof(unsigned long)]; 3543 uint8_t max_req_queues; 3544 uint8_t max_rsp_queues; 3545 uint8_t max_qpairs; 3546 uint8_t num_qpairs; 3547 struct qla_qpair *base_qpair; 3548 struct qla_npiv_entry *npiv_info; 3549 uint16_t nvram_npiv_size; 3550 3551 uint16_t switch_cap; 3552 #define FLOGI_SEQ_DEL BIT_8 3553 #define FLOGI_MID_SUPPORT BIT_10 3554 #define FLOGI_VSAN_SUPPORT BIT_12 3555 #define FLOGI_SP_SUPPORT BIT_13 3556 3557 uint8_t port_no; /* Physical port of adapter */ 3558 uint8_t exch_starvation; 3559 3560 /* Timeout timers. */ 3561 uint8_t loop_down_abort_time; /* port down timer */ 3562 atomic_t loop_down_timer; /* loop down timer */ 3563 uint8_t link_down_timeout; /* link down timeout */ 3564 uint16_t max_loop_id; 3565 uint16_t max_fibre_devices; /* Maximum number of targets */ 3566 3567 uint16_t fb_rev; 3568 uint16_t min_external_loopid; /* First external loop Id */ 3569 3570 #define PORT_SPEED_UNKNOWN 0xFFFF 3571 #define PORT_SPEED_1GB 0x00 3572 #define PORT_SPEED_2GB 0x01 3573 #define PORT_SPEED_4GB 0x03 3574 #define PORT_SPEED_8GB 0x04 3575 #define PORT_SPEED_16GB 0x05 3576 #define PORT_SPEED_32GB 0x06 3577 #define PORT_SPEED_10GB 0x13 3578 uint16_t link_data_rate; /* F/W operating speed */ 3579 3580 uint8_t current_topology; 3581 uint8_t prev_topology; 3582 #define ISP_CFG_NL 1 3583 #define ISP_CFG_N 2 3584 #define ISP_CFG_FL 4 3585 #define ISP_CFG_F 8 3586 3587 uint8_t operating_mode; /* F/W operating mode */ 3588 #define LOOP 0 3589 #define P2P 1 3590 #define LOOP_P2P 2 3591 #define P2P_LOOP 3 3592 uint8_t interrupts_on; 3593 uint32_t isp_abort_cnt; 3594 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 3595 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 3596 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 3597 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 3598 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 3599 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 3600 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 3601 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 3602 3603 uint32_t isp_type; 3604 #define DT_ISP2100 BIT_0 3605 #define DT_ISP2200 BIT_1 3606 #define DT_ISP2300 BIT_2 3607 #define DT_ISP2312 BIT_3 3608 #define DT_ISP2322 BIT_4 3609 #define DT_ISP6312 BIT_5 3610 #define DT_ISP6322 BIT_6 3611 #define DT_ISP2422 BIT_7 3612 #define DT_ISP2432 BIT_8 3613 #define DT_ISP5422 BIT_9 3614 #define DT_ISP5432 BIT_10 3615 #define DT_ISP2532 BIT_11 3616 #define DT_ISP8432 BIT_12 3617 #define DT_ISP8001 BIT_13 3618 #define DT_ISP8021 BIT_14 3619 #define DT_ISP2031 BIT_15 3620 #define DT_ISP8031 BIT_16 3621 #define DT_ISPFX00 BIT_17 3622 #define DT_ISP8044 BIT_18 3623 #define DT_ISP2071 BIT_19 3624 #define DT_ISP2271 BIT_20 3625 #define DT_ISP2261 BIT_21 3626 #define DT_ISP_LAST (DT_ISP2261 << 1) 3627 3628 uint32_t device_type; 3629 #define DT_T10_PI BIT_25 3630 #define DT_IIDMA BIT_26 3631 #define DT_FWI2 BIT_27 3632 #define DT_ZIO_SUPPORTED BIT_28 3633 #define DT_OEM_001 BIT_29 3634 #define DT_ISP2200A BIT_30 3635 #define DT_EXTENDED_IDS BIT_31 3636 3637 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 3638 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 3639 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 3640 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 3641 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 3642 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 3643 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 3644 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 3645 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 3646 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 3647 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 3648 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 3649 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 3650 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 3651 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 3652 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 3653 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 3654 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 3655 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 3656 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 3657 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 3658 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 3659 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 3660 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 3661 3662 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 3663 IS_QLA6312(ha) || IS_QLA6322(ha)) 3664 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 3665 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 3666 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 3667 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 3668 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 3669 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 3670 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 3671 IS_QLA84XX(ha)) 3672 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 3673 IS_QLA8031(ha) || IS_QLA8044(ha)) 3674 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 3675 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 3676 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 3677 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 3678 IS_QLA8044(ha) || IS_QLA27XX(ha)) 3679 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3680 IS_QLA27XX(ha)) 3681 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 3682 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3683 IS_QLA27XX(ha)) 3684 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3685 IS_QLA27XX(ha)) 3686 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 3687 3688 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 3689 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 3690 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 3691 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 3692 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 3693 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 3694 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 3695 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 3696 IS_QLA27XX(ha)) 3697 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) 3698 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 3699 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3700 ((ha)->fw_attributes_ext[0] & BIT_0)) 3701 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3702 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3703 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3704 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3705 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3706 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3707 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3708 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3709 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha)) 3710 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3711 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3712 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 3713 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3714 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 3715 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3716 3717 /* HBA serial number */ 3718 uint8_t serial0; 3719 uint8_t serial1; 3720 uint8_t serial2; 3721 3722 /* NVRAM configuration data */ 3723 #define MAX_NVRAM_SIZE 4096 3724 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 3725 uint16_t nvram_size; 3726 uint16_t nvram_base; 3727 void *nvram; 3728 uint16_t vpd_size; 3729 uint16_t vpd_base; 3730 void *vpd; 3731 3732 uint16_t loop_reset_delay; 3733 uint8_t retry_count; 3734 uint8_t login_timeout; 3735 uint16_t r_a_tov; 3736 int port_down_retry_count; 3737 uint8_t mbx_count; 3738 uint8_t aen_mbx_count; 3739 3740 uint32_t login_retry_count; 3741 /* SNS command interfaces. */ 3742 ms_iocb_entry_t *ms_iocb; 3743 dma_addr_t ms_iocb_dma; 3744 struct ct_sns_pkt *ct_sns; 3745 dma_addr_t ct_sns_dma; 3746 /* SNS command interfaces for 2200. */ 3747 struct sns_cmd_pkt *sns_cmd; 3748 dma_addr_t sns_cmd_dma; 3749 3750 #define SFP_DEV_SIZE 512 3751 #define SFP_BLOCK_SIZE 64 3752 void *sfp_data; 3753 dma_addr_t sfp_data_dma; 3754 3755 #define XGMAC_DATA_SIZE 4096 3756 void *xgmac_data; 3757 dma_addr_t xgmac_data_dma; 3758 3759 #define DCBX_TLV_DATA_SIZE 4096 3760 void *dcbx_tlv; 3761 dma_addr_t dcbx_tlv_dma; 3762 3763 struct task_struct *dpc_thread; 3764 uint8_t dpc_active; /* DPC routine is active */ 3765 3766 dma_addr_t gid_list_dma; 3767 struct gid_list_info *gid_list; 3768 int gid_list_info_size; 3769 3770 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3771 #define DMA_POOL_SIZE 256 3772 struct dma_pool *s_dma_pool; 3773 3774 dma_addr_t init_cb_dma; 3775 init_cb_t *init_cb; 3776 int init_cb_size; 3777 dma_addr_t ex_init_cb_dma; 3778 struct ex_init_cb_81xx *ex_init_cb; 3779 3780 void *async_pd; 3781 dma_addr_t async_pd_dma; 3782 3783 #define ENABLE_EXTENDED_LOGIN BIT_7 3784 3785 /* Extended Logins */ 3786 void *exlogin_buf; 3787 dma_addr_t exlogin_buf_dma; 3788 int exlogin_size; 3789 3790 #define ENABLE_EXCHANGE_OFFLD BIT_2 3791 3792 /* Exchange Offload */ 3793 void *exchoffld_buf; 3794 dma_addr_t exchoffld_buf_dma; 3795 int exchoffld_size; 3796 int exchoffld_count; 3797 3798 void *swl; 3799 3800 /* These are used by mailbox operations. */ 3801 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3802 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 3803 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 3804 3805 mbx_cmd_t *mcp; 3806 struct mbx_cmd_32 *mcp32; 3807 3808 unsigned long mbx_cmd_flags; 3809 #define MBX_INTERRUPT 1 3810 #define MBX_INTR_WAIT 2 3811 #define MBX_UPDATE_FLASH_ACTIVE 3 3812 3813 struct mutex vport_lock; /* Virtual port synchronization */ 3814 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 3815 struct mutex mq_lock; /* multi-queue synchronization */ 3816 struct completion mbx_cmd_comp; /* Serialize mbx access */ 3817 struct completion mbx_intr_comp; /* Used for completion notification */ 3818 struct completion dcbx_comp; /* For set port config notification */ 3819 struct completion lb_portup_comp; /* Used to wait for link up during 3820 * loopback */ 3821 #define DCBX_COMP_TIMEOUT 20 3822 #define LB_PORTUP_COMP_TIMEOUT 10 3823 3824 int notify_dcbx_comp; 3825 int notify_lb_portup_comp; 3826 struct mutex selflogin_lock; 3827 3828 /* Basic firmware related information. */ 3829 uint16_t fw_major_version; 3830 uint16_t fw_minor_version; 3831 uint16_t fw_subminor_version; 3832 uint16_t fw_attributes; 3833 uint16_t fw_attributes_h; 3834 uint16_t fw_attributes_ext[2]; 3835 uint32_t fw_memory_size; 3836 uint32_t fw_transfer_size; 3837 uint32_t fw_srisc_address; 3838 #define RISC_START_ADDRESS_2100 0x1000 3839 #define RISC_START_ADDRESS_2300 0x800 3840 #define RISC_START_ADDRESS_2400 0x100000 3841 3842 uint16_t orig_fw_tgt_xcb_count; 3843 uint16_t cur_fw_tgt_xcb_count; 3844 uint16_t orig_fw_xcb_count; 3845 uint16_t cur_fw_xcb_count; 3846 uint16_t orig_fw_iocb_count; 3847 uint16_t cur_fw_iocb_count; 3848 uint16_t fw_max_fcf_count; 3849 3850 uint32_t fw_shared_ram_start; 3851 uint32_t fw_shared_ram_end; 3852 uint32_t fw_ddr_ram_start; 3853 uint32_t fw_ddr_ram_end; 3854 3855 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 3856 uint8_t fw_seriallink_options[4]; 3857 uint16_t fw_seriallink_options24[4]; 3858 3859 uint8_t mpi_version[3]; 3860 uint32_t mpi_capabilities; 3861 uint8_t phy_version[3]; 3862 uint8_t pep_version[3]; 3863 3864 /* Firmware dump template */ 3865 void *fw_dump_template; 3866 uint32_t fw_dump_template_len; 3867 /* Firmware dump information. */ 3868 struct qla2xxx_fw_dump *fw_dump; 3869 uint32_t fw_dump_len; 3870 int fw_dumped; 3871 unsigned long fw_dump_cap_flags; 3872 #define RISC_PAUSE_CMPL 0 3873 #define DMA_SHUTDOWN_CMPL 1 3874 #define ISP_RESET_CMPL 2 3875 #define RISC_RDY_AFT_RESET 3 3876 #define RISC_SRAM_DUMP_CMPL 4 3877 #define RISC_EXT_MEM_DUMP_CMPL 5 3878 #define ISP_MBX_RDY 6 3879 #define ISP_SOFT_RESET_CMPL 7 3880 int fw_dump_reading; 3881 int prev_minidump_failed; 3882 dma_addr_t eft_dma; 3883 void *eft; 3884 /* Current size of mctp dump is 0x086064 bytes */ 3885 #define MCTP_DUMP_SIZE 0x086064 3886 dma_addr_t mctp_dump_dma; 3887 void *mctp_dump; 3888 int mctp_dumped; 3889 int mctp_dump_reading; 3890 uint32_t chain_offset; 3891 struct dentry *dfs_dir; 3892 struct dentry *dfs_fce; 3893 struct dentry *dfs_tgt_counters; 3894 struct dentry *dfs_fw_resource_cnt; 3895 3896 dma_addr_t fce_dma; 3897 void *fce; 3898 uint32_t fce_bufs; 3899 uint16_t fce_mb[8]; 3900 uint64_t fce_wr, fce_rd; 3901 struct mutex fce_mutex; 3902 3903 uint32_t pci_attr; 3904 uint16_t chip_revision; 3905 3906 uint16_t product_id[4]; 3907 3908 uint8_t model_number[16+1]; 3909 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 3910 char model_desc[80]; 3911 uint8_t adapter_id[16+1]; 3912 3913 /* Option ROM information. */ 3914 char *optrom_buffer; 3915 uint32_t optrom_size; 3916 int optrom_state; 3917 #define QLA_SWAITING 0 3918 #define QLA_SREADING 1 3919 #define QLA_SWRITING 2 3920 uint32_t optrom_region_start; 3921 uint32_t optrom_region_size; 3922 struct mutex optrom_mutex; 3923 3924 /* PCI expansion ROM image information. */ 3925 #define ROM_CODE_TYPE_BIOS 0 3926 #define ROM_CODE_TYPE_FCODE 1 3927 #define ROM_CODE_TYPE_EFI 3 3928 uint8_t bios_revision[2]; 3929 uint8_t efi_revision[2]; 3930 uint8_t fcode_revision[16]; 3931 uint32_t fw_revision[4]; 3932 3933 uint32_t gold_fw_version[4]; 3934 3935 /* Offsets for flash/nvram access (set to ~0 if not used). */ 3936 uint32_t flash_conf_off; 3937 uint32_t flash_data_off; 3938 uint32_t nvram_conf_off; 3939 uint32_t nvram_data_off; 3940 3941 uint32_t fdt_wrt_disable; 3942 uint32_t fdt_wrt_enable; 3943 uint32_t fdt_erase_cmd; 3944 uint32_t fdt_block_size; 3945 uint32_t fdt_unprotect_sec_cmd; 3946 uint32_t fdt_protect_sec_cmd; 3947 uint32_t fdt_wrt_sts_reg_cmd; 3948 3949 uint32_t flt_region_flt; 3950 uint32_t flt_region_fdt; 3951 uint32_t flt_region_boot; 3952 uint32_t flt_region_boot_sec; 3953 uint32_t flt_region_fw; 3954 uint32_t flt_region_fw_sec; 3955 uint32_t flt_region_vpd_nvram; 3956 uint32_t flt_region_vpd; 3957 uint32_t flt_region_vpd_sec; 3958 uint32_t flt_region_nvram; 3959 uint32_t flt_region_npiv_conf; 3960 uint32_t flt_region_gold_fw; 3961 uint32_t flt_region_fcp_prio; 3962 uint32_t flt_region_bootload; 3963 uint32_t flt_region_img_status_pri; 3964 uint32_t flt_region_img_status_sec; 3965 uint8_t active_image; 3966 3967 /* Needed for BEACON */ 3968 uint16_t beacon_blink_led; 3969 uint8_t beacon_color_state; 3970 #define QLA_LED_GRN_ON 0x01 3971 #define QLA_LED_YLW_ON 0x02 3972 #define QLA_LED_ABR_ON 0x04 3973 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 3974 /* ISP2322: red, green, amber. */ 3975 uint16_t zio_mode; 3976 uint16_t zio_timer; 3977 3978 struct qla_msix_entry *msix_entries; 3979 3980 struct list_head vp_list; /* list of VP */ 3981 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 3982 sizeof(unsigned long)]; 3983 uint16_t num_vhosts; /* number of vports created */ 3984 uint16_t num_vsans; /* number of vsan created */ 3985 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 3986 int cur_vport_count; 3987 3988 struct qla_chip_state_84xx *cs84xx; 3989 struct isp_operations *isp_ops; 3990 struct workqueue_struct *wq; 3991 struct qlfc_fw fw_buf; 3992 3993 /* FCP_CMND priority support */ 3994 struct qla_fcp_prio_cfg *fcp_prio_cfg; 3995 3996 struct dma_pool *dl_dma_pool; 3997 #define DSD_LIST_DMA_POOL_SIZE 512 3998 3999 struct dma_pool *fcp_cmnd_dma_pool; 4000 mempool_t *ctx_mempool; 4001 #define FCP_CMND_DMA_POOL_SIZE 512 4002 4003 void __iomem *nx_pcibase; /* Base I/O address */ 4004 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4005 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4006 4007 uint32_t crb_win; 4008 uint32_t curr_window; 4009 uint32_t ddr_mn_window; 4010 unsigned long mn_win_crb; 4011 unsigned long ms_win_crb; 4012 int qdr_sn_window; 4013 uint32_t fcoe_dev_init_timeout; 4014 uint32_t fcoe_reset_timeout; 4015 rwlock_t hw_lock; 4016 uint16_t portnum; /* port number */ 4017 int link_width; 4018 struct fw_blob *hablob; 4019 struct qla82xx_legacy_intr_set nx_legacy_intr; 4020 4021 uint16_t gbl_dsd_inuse; 4022 uint16_t gbl_dsd_avail; 4023 struct list_head gbl_dsd_list; 4024 #define NUM_DSD_CHAIN 4096 4025 4026 uint8_t fw_type; 4027 __le32 file_prd_off; /* File firmware product offset */ 4028 4029 uint32_t md_template_size; 4030 void *md_tmplt_hdr; 4031 dma_addr_t md_tmplt_hdr_dma; 4032 void *md_dump; 4033 uint32_t md_dump_size; 4034 4035 void *loop_id_map; 4036 4037 /* QLA83XX IDC specific fields */ 4038 uint32_t idc_audit_ts; 4039 uint32_t idc_extend_tmo; 4040 4041 /* DPC low-priority workqueue */ 4042 struct workqueue_struct *dpc_lp_wq; 4043 struct work_struct idc_aen; 4044 /* DPC high-priority workqueue */ 4045 struct workqueue_struct *dpc_hp_wq; 4046 struct work_struct nic_core_reset; 4047 struct work_struct idc_state_handler; 4048 struct work_struct nic_core_unrecoverable; 4049 struct work_struct board_disable; 4050 4051 struct mr_data_fx00 mr; 4052 4053 struct qlt_hw_data tgt; 4054 int allow_cna_fw_dump; 4055 uint32_t fw_ability_mask; 4056 uint16_t min_link_speed; 4057 uint16_t max_speed_sup; 4058 4059 atomic_t nvme_active_aen_cnt; 4060 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4061 }; 4062 4063 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4064 #define FW_ABILITY_MAX_SPEED_16G 0x0 4065 #define FW_ABILITY_MAX_SPEED_32G 0x1 4066 #define FW_ABILITY_MAX_SPEED(ha) \ 4067 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4068 4069 /* 4070 * Qlogic scsi host structure 4071 */ 4072 typedef struct scsi_qla_host { 4073 struct list_head list; 4074 struct list_head vp_fcports; /* list of fcports */ 4075 struct list_head work_list; 4076 spinlock_t work_lock; 4077 struct work_struct iocb_work; 4078 4079 /* Commonly used flags and state information. */ 4080 struct Scsi_Host *host; 4081 unsigned long host_no; 4082 uint8_t host_str[16]; 4083 4084 volatile struct { 4085 uint32_t init_done :1; 4086 uint32_t online :1; 4087 uint32_t reset_active :1; 4088 4089 uint32_t management_server_logged_in :1; 4090 uint32_t process_response_queue :1; 4091 uint32_t difdix_supported:1; 4092 uint32_t delete_progress:1; 4093 4094 uint32_t fw_tgt_reported:1; 4095 uint32_t bbcr_enable:1; 4096 uint32_t qpairs_available:1; 4097 uint32_t qpairs_req_created:1; 4098 uint32_t qpairs_rsp_created:1; 4099 uint32_t nvme_enabled:1; 4100 } flags; 4101 4102 atomic_t loop_state; 4103 #define LOOP_TIMEOUT 1 4104 #define LOOP_DOWN 2 4105 #define LOOP_UP 3 4106 #define LOOP_UPDATE 4 4107 #define LOOP_READY 5 4108 #define LOOP_DEAD 6 4109 4110 unsigned long dpc_flags; 4111 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4112 #define RESET_ACTIVE 1 4113 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4114 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4115 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4116 #define LOOP_RESYNC_ACTIVE 5 4117 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4118 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4119 #define RELOGIN_NEEDED 8 4120 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4121 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4122 #define BEACON_BLINK_NEEDED 11 4123 #define REGISTER_FDMI_NEEDED 12 4124 #define FCPORT_UPDATE_NEEDED 13 4125 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4126 #define UNLOADING 15 4127 #define NPIV_CONFIG_NEEDED 16 4128 #define ISP_UNRECOVERABLE 17 4129 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4130 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4131 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4132 #define FREE_BIT 21 4133 #define PORT_UPDATE_NEEDED 22 4134 #define FX00_RESET_RECOVERY 23 4135 #define FX00_TARGET_SCAN 24 4136 #define FX00_CRITEMP_RECOVERY 25 4137 #define FX00_HOST_INFO_RESEND 26 4138 #define QPAIR_ONLINE_CHECK_NEEDED 27 4139 #define SET_ZIO_THRESHOLD_NEEDED 28 4140 #define DETECT_SFP_CHANGE 29 4141 #define N2N_LOGIN_NEEDED 30 4142 4143 unsigned long pci_flags; 4144 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4145 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4146 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4147 4148 uint32_t device_flags; 4149 #define SWITCH_FOUND BIT_0 4150 #define DFLG_NO_CABLE BIT_1 4151 #define DFLG_DEV_FAILED BIT_5 4152 4153 /* ISP configuration data. */ 4154 uint16_t loop_id; /* Host adapter loop id */ 4155 uint16_t self_login_loop_id; /* host adapter loop id 4156 * get it on self login 4157 */ 4158 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4159 * no need of allocating it for 4160 * each command 4161 */ 4162 4163 port_id_t d_id; /* Host adapter port id */ 4164 uint8_t marker_needed; 4165 uint16_t mgmt_svr_loop_id; 4166 4167 4168 4169 /* Timeout timers. */ 4170 uint8_t loop_down_abort_time; /* port down timer */ 4171 atomic_t loop_down_timer; /* loop down timer */ 4172 uint8_t link_down_timeout; /* link down timeout */ 4173 4174 uint32_t timer_active; 4175 struct timer_list timer; 4176 4177 uint8_t node_name[WWN_SIZE]; 4178 uint8_t port_name[WWN_SIZE]; 4179 uint8_t fabric_node_name[WWN_SIZE]; 4180 4181 struct nvme_fc_local_port *nvme_local_port; 4182 struct completion nvme_del_done; 4183 struct list_head nvme_rport_list; 4184 atomic_t nvme_active_aen_cnt; 4185 uint16_t nvme_last_rptd_aen; 4186 4187 uint16_t fcoe_vlan_id; 4188 uint16_t fcoe_fcf_idx; 4189 uint8_t fcoe_vn_port_mac[6]; 4190 4191 /* list of commands waiting on workqueue */ 4192 struct list_head qla_cmd_list; 4193 struct list_head qla_sess_op_cmd_list; 4194 struct list_head unknown_atio_list; 4195 spinlock_t cmd_list_lock; 4196 struct delayed_work unknown_atio_work; 4197 4198 /* Counter to detect races between ELS and RSCN events */ 4199 atomic_t generation_tick; 4200 /* Time when global fcport update has been scheduled */ 4201 int total_fcport_update_gen; 4202 /* List of pending LOGOs, protected by tgt_mutex */ 4203 struct list_head logo_list; 4204 /* List of pending PLOGI acks, protected by hw lock */ 4205 struct list_head plogi_ack_list; 4206 4207 struct list_head qp_list; 4208 4209 uint32_t vp_abort_cnt; 4210 4211 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4212 uint16_t vp_idx; /* vport ID */ 4213 struct qla_qpair *qpair; /* base qpair */ 4214 4215 unsigned long vp_flags; 4216 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4217 #define VP_CREATE_NEEDED 1 4218 #define VP_BIND_NEEDED 2 4219 #define VP_DELETE_NEEDED 3 4220 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4221 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4222 atomic_t vp_state; 4223 #define VP_OFFLINE 0 4224 #define VP_ACTIVE 1 4225 #define VP_FAILED 2 4226 // #define VP_DISABLE 3 4227 uint16_t vp_err_state; 4228 uint16_t vp_prev_err_state; 4229 #define VP_ERR_UNKWN 0 4230 #define VP_ERR_PORTDWN 1 4231 #define VP_ERR_FAB_UNSUPPORTED 2 4232 #define VP_ERR_FAB_NORESOURCES 3 4233 #define VP_ERR_FAB_LOGOUT 4 4234 #define VP_ERR_ADAP_NORESOURCES 5 4235 struct qla_hw_data *hw; 4236 struct scsi_qlt_host vha_tgt; 4237 struct req_que *req; 4238 int fw_heartbeat_counter; 4239 int seconds_since_last_heartbeat; 4240 struct fc_host_statistics fc_host_stat; 4241 struct qla_statistics qla_stats; 4242 struct bidi_statistics bidi_stats; 4243 atomic_t vref_count; 4244 struct qla8044_reset_template reset_tmplt; 4245 uint16_t bbcr; 4246 struct name_list_extended gnl; 4247 /* Count of active session/fcport */ 4248 int fcport_count; 4249 wait_queue_head_t fcport_waitQ; 4250 wait_queue_head_t vref_waitq; 4251 uint8_t min_link_speed_feat; 4252 uint8_t n2n_node_name[WWN_SIZE]; 4253 uint8_t n2n_port_name[WWN_SIZE]; 4254 uint16_t n2n_id; 4255 } scsi_qla_host_t; 4256 4257 struct qla27xx_image_status { 4258 uint8_t image_status_mask; 4259 uint16_t generation_number; 4260 uint8_t reserved[3]; 4261 uint8_t ver_minor; 4262 uint8_t ver_major; 4263 uint32_t checksum; 4264 uint32_t signature; 4265 } __packed; 4266 4267 #define SET_VP_IDX 1 4268 #define SET_AL_PA 2 4269 #define RESET_VP_IDX 3 4270 #define RESET_AL_PA 4 4271 struct qla_tgt_vp_map { 4272 uint8_t idx; 4273 scsi_qla_host_t *vha; 4274 }; 4275 4276 struct qla2_sgx { 4277 dma_addr_t dma_addr; /* OUT */ 4278 uint32_t dma_len; /* OUT */ 4279 4280 uint32_t tot_bytes; /* IN */ 4281 struct scatterlist *cur_sg; /* IN */ 4282 4283 /* for book keeping, bzero on initial invocation */ 4284 uint32_t bytes_consumed; 4285 uint32_t num_bytes; 4286 uint32_t tot_partial; 4287 4288 /* for debugging */ 4289 uint32_t num_sg; 4290 srb_t *sp; 4291 }; 4292 4293 #define QLA_FW_STARTED(_ha) { \ 4294 int i; \ 4295 _ha->flags.fw_started = 1; \ 4296 _ha->base_qpair->fw_started = 1; \ 4297 for (i = 0; i < _ha->max_qpairs; i++) { \ 4298 if (_ha->queue_pair_map[i]) \ 4299 _ha->queue_pair_map[i]->fw_started = 1; \ 4300 } \ 4301 } 4302 4303 #define QLA_FW_STOPPED(_ha) { \ 4304 int i; \ 4305 _ha->flags.fw_started = 0; \ 4306 _ha->base_qpair->fw_started = 0; \ 4307 for (i = 0; i < _ha->max_qpairs; i++) { \ 4308 if (_ha->queue_pair_map[i]) \ 4309 _ha->queue_pair_map[i]->fw_started = 0; \ 4310 } \ 4311 } 4312 4313 /* 4314 * Macros to help code, maintain, etc. 4315 */ 4316 #define LOOP_TRANSITION(ha) \ 4317 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4318 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 4319 atomic_read(&ha->loop_state) == LOOP_DOWN) 4320 4321 #define STATE_TRANSITION(ha) \ 4322 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4323 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 4324 4325 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 4326 atomic_inc(&__vha->vref_count); \ 4327 mb(); \ 4328 if (__vha->flags.delete_progress) { \ 4329 atomic_dec(&__vha->vref_count); \ 4330 wake_up(&__vha->vref_waitq); \ 4331 __bail = 1; \ 4332 } else { \ 4333 __bail = 0; \ 4334 } \ 4335 } while (0) 4336 4337 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 4338 atomic_dec(&__vha->vref_count); \ 4339 wake_up(&__vha->vref_waitq); \ 4340 } while (0) \ 4341 4342 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 4343 atomic_inc(&__qpair->ref_count); \ 4344 mb(); \ 4345 if (__qpair->delete_in_progress) { \ 4346 atomic_dec(&__qpair->ref_count); \ 4347 __bail = 1; \ 4348 } else { \ 4349 __bail = 0; \ 4350 } \ 4351 } while (0) 4352 4353 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 4354 atomic_dec(&__qpair->ref_count); \ 4355 4356 4357 #define QLA_ENA_CONF(_ha) {\ 4358 int i;\ 4359 _ha->base_qpair->enable_explicit_conf = 1; \ 4360 for (i = 0; i < _ha->max_qpairs; i++) { \ 4361 if (_ha->queue_pair_map[i]) \ 4362 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 4363 } \ 4364 } 4365 4366 #define QLA_DIS_CONF(_ha) {\ 4367 int i;\ 4368 _ha->base_qpair->enable_explicit_conf = 0; \ 4369 for (i = 0; i < _ha->max_qpairs; i++) { \ 4370 if (_ha->queue_pair_map[i]) \ 4371 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 4372 } \ 4373 } 4374 4375 /* 4376 * qla2x00 local function return status codes 4377 */ 4378 #define MBS_MASK 0x3fff 4379 4380 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 4381 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 4382 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 4383 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 4384 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 4385 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 4386 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 4387 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 4388 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 4389 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 4390 4391 #define QLA_FUNCTION_TIMEOUT 0x100 4392 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 4393 #define QLA_FUNCTION_FAILED 0x102 4394 #define QLA_MEMORY_ALLOC_FAILED 0x103 4395 #define QLA_LOCK_TIMEOUT 0x104 4396 #define QLA_ABORTED 0x105 4397 #define QLA_SUSPENDED 0x106 4398 #define QLA_BUSY 0x107 4399 #define QLA_ALREADY_REGISTERED 0x109 4400 4401 #define NVRAM_DELAY() udelay(10) 4402 4403 /* 4404 * Flash support definitions 4405 */ 4406 #define OPTROM_SIZE_2300 0x20000 4407 #define OPTROM_SIZE_2322 0x100000 4408 #define OPTROM_SIZE_24XX 0x100000 4409 #define OPTROM_SIZE_25XX 0x200000 4410 #define OPTROM_SIZE_81XX 0x400000 4411 #define OPTROM_SIZE_82XX 0x800000 4412 #define OPTROM_SIZE_83XX 0x1000000 4413 4414 #define OPTROM_BURST_SIZE 0x1000 4415 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 4416 4417 #define QLA_DSDS_PER_IOCB 37 4418 4419 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 4420 4421 #define QLA_SG_ALL 1024 4422 4423 enum nexus_wait_type { 4424 WAIT_HOST = 0, 4425 WAIT_TARGET, 4426 WAIT_LUN, 4427 }; 4428 4429 /* Refer to SNIA SFF 8247 */ 4430 struct sff_8247_a0 { 4431 u8 txid; /* transceiver id */ 4432 u8 ext_txid; 4433 u8 connector; 4434 /* compliance code */ 4435 u8 eth_infi_cc3; /* ethernet, inifiband */ 4436 u8 sonet_cc4[2]; 4437 u8 eth_cc6; 4438 /* link length */ 4439 #define FC_LL_VL BIT_7 /* very long */ 4440 #define FC_LL_S BIT_6 /* Short */ 4441 #define FC_LL_I BIT_5 /* Intermidiate*/ 4442 #define FC_LL_L BIT_4 /* Long */ 4443 #define FC_LL_M BIT_3 /* Medium */ 4444 #define FC_LL_SA BIT_2 /* ShortWave laser */ 4445 #define FC_LL_LC BIT_1 /* LongWave laser */ 4446 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 4447 u8 fc_ll_cc7; 4448 /* FC technology */ 4449 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 4450 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 4451 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 4452 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 4453 #define FC_TEC_ACT BIT_3 /* Active cable */ 4454 #define FC_TEC_PAS BIT_2 /* Passive cable */ 4455 u8 fc_tec_cc8; 4456 /* Transmission Media */ 4457 #define FC_MED_TW BIT_7 /* Twin Ax */ 4458 #define FC_MED_TP BIT_6 /* Twited Pair */ 4459 #define FC_MED_MI BIT_5 /* Min Coax */ 4460 #define FC_MED_TV BIT_4 /* Video Coax */ 4461 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 4462 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 4463 #define FC_MED_SM BIT_0 /* Single Mode */ 4464 u8 fc_med_cc9; 4465 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 4466 #define FC_SP_12 BIT_7 4467 #define FC_SP_8 BIT_6 4468 #define FC_SP_16 BIT_5 4469 #define FC_SP_4 BIT_4 4470 #define FC_SP_32 BIT_3 4471 #define FC_SP_2 BIT_2 4472 #define FC_SP_1 BIT_0 4473 u8 fc_sp_cc10; 4474 u8 encode; 4475 u8 bitrate; 4476 u8 rate_id; 4477 u8 length_km; /* offset 14/eh */ 4478 u8 length_100m; 4479 u8 length_50um_10m; 4480 u8 length_62um_10m; 4481 u8 length_om4_10m; 4482 u8 length_om3_10m; 4483 #define SFF_VEN_NAME_LEN 16 4484 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 4485 u8 tx_compat; 4486 u8 vendor_oui[3]; 4487 #define SFF_PART_NAME_LEN 16 4488 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 4489 u8 vendor_rev[4]; 4490 u8 wavelength[2]; 4491 u8 resv; 4492 u8 cc_base; 4493 u8 options[2]; /* offset 64 */ 4494 u8 br_max; 4495 u8 br_min; 4496 u8 vendor_sn[16]; 4497 u8 date_code[8]; 4498 u8 diag; 4499 u8 enh_options; 4500 u8 sff_revision; 4501 u8 cc_ext; 4502 u8 vendor_specific[32]; 4503 u8 resv2[128]; 4504 }; 4505 4506 #define AUTO_DETECT_SFP_SUPPORT(_vha)\ 4507 (ql2xautodetectsfp && !_vha->vp_idx && \ 4508 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\ 4509 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw))) 4510 4511 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 4512 (IS_QLA27XX(_ha) || IS_QLA83XX(_ha))) 4513 4514 #include "qla_target.h" 4515 #include "qla_gbl.h" 4516 #include "qla_dbg.h" 4517 #include "qla_inline.h" 4518 #endif 4519