1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 #include <scsi/scsi_bsg_fc.h> 35 36 #include "qla_bsg.h" 37 #include "qla_nx.h" 38 #include "qla_nx2.h" 39 #define QLA2XXX_DRIVER_NAME "qla2xxx" 40 #define QLA2XXX_APIDEV "ql2xapidev" 41 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 42 43 /* 44 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 45 * but that's fine as we don't look at the last 24 ones for 46 * ISP2100 HBAs. 47 */ 48 #define MAILBOX_REGISTER_COUNT_2100 8 49 #define MAILBOX_REGISTER_COUNT_2200 24 50 #define MAILBOX_REGISTER_COUNT 32 51 52 #define QLA2200A_RISC_ROM_VER 4 53 #define FPM_2300 6 54 #define FPM_2310 7 55 56 #include "qla_settings.h" 57 58 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 59 60 /* 61 * Data bit definitions 62 */ 63 #define BIT_0 0x1 64 #define BIT_1 0x2 65 #define BIT_2 0x4 66 #define BIT_3 0x8 67 #define BIT_4 0x10 68 #define BIT_5 0x20 69 #define BIT_6 0x40 70 #define BIT_7 0x80 71 #define BIT_8 0x100 72 #define BIT_9 0x200 73 #define BIT_10 0x400 74 #define BIT_11 0x800 75 #define BIT_12 0x1000 76 #define BIT_13 0x2000 77 #define BIT_14 0x4000 78 #define BIT_15 0x8000 79 #define BIT_16 0x10000 80 #define BIT_17 0x20000 81 #define BIT_18 0x40000 82 #define BIT_19 0x80000 83 #define BIT_20 0x100000 84 #define BIT_21 0x200000 85 #define BIT_22 0x400000 86 #define BIT_23 0x800000 87 #define BIT_24 0x1000000 88 #define BIT_25 0x2000000 89 #define BIT_26 0x4000000 90 #define BIT_27 0x8000000 91 #define BIT_28 0x10000000 92 #define BIT_29 0x20000000 93 #define BIT_30 0x40000000 94 #define BIT_31 0x80000000 95 96 #define LSB(x) ((uint8_t)(x)) 97 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 98 99 #define LSW(x) ((uint16_t)(x)) 100 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 101 102 #define LSD(x) ((uint32_t)((uint64_t)(x))) 103 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 104 105 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 106 107 /* 108 * I/O register 109 */ 110 111 #define RD_REG_BYTE(addr) readb(addr) 112 #define RD_REG_WORD(addr) readw(addr) 113 #define RD_REG_DWORD(addr) readl(addr) 114 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 115 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 116 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 117 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 118 #define WRT_REG_WORD(addr, data) writew(data,addr) 119 #define WRT_REG_DWORD(addr, data) writel(data,addr) 120 121 /* 122 * ISP83XX specific remote register addresses 123 */ 124 #define QLA83XX_LED_PORT0 0x00201320 125 #define QLA83XX_LED_PORT1 0x00201328 126 #define QLA83XX_IDC_DEV_STATE 0x22102384 127 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 128 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 129 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 130 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 131 #define QLA83XX_IDC_CONTROL 0x22102390 132 #define QLA83XX_IDC_AUDIT 0x22102394 133 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 134 #define QLA83XX_DRIVER_LOCKID 0x22102104 135 #define QLA83XX_DRIVER_LOCK 0x8111c028 136 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 137 #define QLA83XX_FLASH_LOCKID 0x22102100 138 #define QLA83XX_FLASH_LOCK 0x8111c010 139 #define QLA83XX_FLASH_UNLOCK 0x8111c014 140 #define QLA83XX_DEV_PARTINFO1 0x221023e0 141 #define QLA83XX_DEV_PARTINFO2 0x221023e4 142 #define QLA83XX_FW_HEARTBEAT 0x221020b0 143 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 144 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 145 146 /* 83XX: Macros defining 8200 AEN Reason codes */ 147 #define IDC_DEVICE_STATE_CHANGE BIT_0 148 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 149 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 150 #define IDC_HEARTBEAT_FAILURE BIT_3 151 152 /* 83XX: Macros defining 8200 AEN Error-levels */ 153 #define ERR_LEVEL_NON_FATAL 0x1 154 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 155 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 156 157 /* 83XX: Macros for IDC Version */ 158 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 159 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 160 161 /* 83XX: Macros for scheduling dpc tasks */ 162 #define QLA83XX_NIC_CORE_RESET 0x1 163 #define QLA83XX_IDC_STATE_HANDLER 0x2 164 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 165 166 /* 83XX: Macros for defining IDC-Control bits */ 167 #define QLA83XX_IDC_RESET_DISABLED BIT_0 168 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 169 170 /* 83XX: Macros for different timeouts */ 171 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 172 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 173 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 174 175 /* 83XX: Macros for defining class in DEV-Partition Info register */ 176 #define QLA83XX_CLASS_TYPE_NONE 0x0 177 #define QLA83XX_CLASS_TYPE_NIC 0x1 178 #define QLA83XX_CLASS_TYPE_FCOE 0x2 179 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 180 181 /* 83XX: Macros for IDC Lock-Recovery stages */ 182 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 183 * lock-recovery 184 */ 185 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 186 187 /* 83XX: Macros for IDC Audit type */ 188 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 189 * dev-state change to NEED-RESET 190 * or NEED-QUIESCENT 191 */ 192 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 193 * reset-recovery completion is 194 * second 195 */ 196 /* ISP2031: Values for laser on/off */ 197 #define PORT_0_2031 0x00201340 198 #define PORT_1_2031 0x00201350 199 #define LASER_ON_2031 0x01800100 200 #define LASER_OFF_2031 0x01800180 201 202 /* 203 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 204 * 133Mhz slot. 205 */ 206 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 207 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 208 209 /* 210 * Fibre Channel device definitions. 211 */ 212 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 213 #define MAX_FIBRE_DEVICES_2100 512 214 #define MAX_FIBRE_DEVICES_2400 2048 215 #define MAX_FIBRE_DEVICES_LOOP 128 216 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 217 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 218 #define MAX_FIBRE_LUNS 0xFFFF 219 #define MAX_HOST_COUNT 16 220 221 /* 222 * Host adapter default definitions. 223 */ 224 #define MAX_BUSES 1 /* We only have one bus today */ 225 #define MIN_LUNS 8 226 #define MAX_LUNS MAX_FIBRE_LUNS 227 #define MAX_CMDS_PER_LUN 255 228 229 /* 230 * Fibre Channel device definitions. 231 */ 232 #define SNS_LAST_LOOP_ID_2100 0xfe 233 #define SNS_LAST_LOOP_ID_2300 0x7ff 234 235 #define LAST_LOCAL_LOOP_ID 0x7d 236 #define SNS_FL_PORT 0x7e 237 #define FABRIC_CONTROLLER 0x7f 238 #define SIMPLE_NAME_SERVER 0x80 239 #define SNS_FIRST_LOOP_ID 0x81 240 #define MANAGEMENT_SERVER 0xfe 241 #define BROADCAST 0xff 242 243 /* 244 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 245 * valid range of an N-PORT id is 0 through 0x7ef. 246 */ 247 #define NPH_LAST_HANDLE 0x7ef 248 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ 249 #define NPH_SNS 0x7fc /* FFFFFC */ 250 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 251 #define NPH_F_PORT 0x7fe /* FFFFFE */ 252 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 253 254 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 255 #include "qla_fw.h" 256 257 struct name_list_extended { 258 struct get_name_list_extended *l; 259 dma_addr_t ldma; 260 struct list_head fcports; /* protect by sess_list */ 261 u32 size; 262 u8 sent; 263 }; 264 /* 265 * Timeout timer counts in seconds 266 */ 267 #define PORT_RETRY_TIME 1 268 #define LOOP_DOWN_TIMEOUT 60 269 #define LOOP_DOWN_TIME 255 /* 240 */ 270 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 271 272 #define DEFAULT_OUTSTANDING_COMMANDS 4096 273 #define MIN_OUTSTANDING_COMMANDS 128 274 275 /* ISP request and response entry counts (37-65535) */ 276 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 277 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 278 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 279 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 280 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 281 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 282 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 283 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 284 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 285 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 286 #define EXTENDED_EXCH_ENTRY_CNT 32768 /* Entries for offload case */ 287 288 struct req_que; 289 struct qla_tgt_sess; 290 291 /* 292 * SCSI Request Block 293 */ 294 struct srb_cmd { 295 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 296 uint32_t request_sense_length; 297 uint32_t fw_sense_length; 298 uint8_t *request_sense_ptr; 299 void *ctx; 300 }; 301 302 /* 303 * SRB flag definitions 304 */ 305 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 306 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 307 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 308 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 309 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 310 311 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 312 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 313 314 struct els_logo_payload { 315 uint8_t opcode; 316 uint8_t rsvd[3]; 317 uint8_t s_id[3]; 318 uint8_t rsvd1[1]; 319 uint8_t wwpn[WWN_SIZE]; 320 }; 321 322 struct ct_arg { 323 void *iocb; 324 u16 nport_handle; 325 dma_addr_t req_dma; 326 dma_addr_t rsp_dma; 327 u32 req_size; 328 u32 rsp_size; 329 void *req; 330 void *rsp; 331 }; 332 333 /* 334 * SRB extensions. 335 */ 336 struct srb_iocb { 337 union { 338 struct { 339 uint16_t flags; 340 #define SRB_LOGIN_RETRIED BIT_0 341 #define SRB_LOGIN_COND_PLOGI BIT_1 342 #define SRB_LOGIN_SKIP_PRLI BIT_2 343 uint16_t data[2]; 344 u32 iop[2]; 345 } logio; 346 struct { 347 #define ELS_DCMD_TIMEOUT 20 348 #define ELS_DCMD_LOGO 0x5 349 uint32_t flags; 350 uint32_t els_cmd; 351 struct completion comp; 352 struct els_logo_payload *els_logo_pyld; 353 dma_addr_t els_logo_pyld_dma; 354 } els_logo; 355 struct { 356 /* 357 * Values for flags field below are as 358 * defined in tsk_mgmt_entry struct 359 * for control_flags field in qla_fw.h. 360 */ 361 uint64_t lun; 362 uint32_t flags; 363 uint32_t data; 364 struct completion comp; 365 __le16 comp_status; 366 } tmf; 367 struct { 368 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 369 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 370 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 371 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 372 #define FXDISC_TIMEOUT 20 373 uint8_t flags; 374 uint32_t req_len; 375 uint32_t rsp_len; 376 void *req_addr; 377 void *rsp_addr; 378 dma_addr_t req_dma_handle; 379 dma_addr_t rsp_dma_handle; 380 __le32 adapter_id; 381 __le32 adapter_id_hi; 382 __le16 req_func_type; 383 __le32 req_data; 384 __le32 req_data_extra; 385 __le32 result; 386 __le32 seq_number; 387 __le16 fw_flags; 388 struct completion fxiocb_comp; 389 __le32 reserved_0; 390 uint8_t reserved_1; 391 } fxiocb; 392 struct { 393 uint32_t cmd_hndl; 394 __le16 comp_status; 395 struct completion comp; 396 } abt; 397 struct ct_arg ctarg; 398 struct { 399 __le16 in_mb[28]; /* fr fw */ 400 __le16 out_mb[28]; /* to fw */ 401 void *out, *in; 402 dma_addr_t out_dma, in_dma; 403 } mbx; 404 struct { 405 struct imm_ntfy_from_isp *ntfy; 406 } nack; 407 } u; 408 409 struct timer_list timer; 410 void (*timeout)(void *); 411 }; 412 413 /* Values for srb_ctx type */ 414 #define SRB_LOGIN_CMD 1 415 #define SRB_LOGOUT_CMD 2 416 #define SRB_ELS_CMD_RPT 3 417 #define SRB_ELS_CMD_HST 4 418 #define SRB_CT_CMD 5 419 #define SRB_ADISC_CMD 6 420 #define SRB_TM_CMD 7 421 #define SRB_SCSI_CMD 8 422 #define SRB_BIDI_CMD 9 423 #define SRB_FXIOCB_DCMD 10 424 #define SRB_FXIOCB_BCMD 11 425 #define SRB_ABT_CMD 12 426 #define SRB_ELS_DCMD 13 427 #define SRB_MB_IOCB 14 428 #define SRB_CT_PTHRU_CMD 15 429 #define SRB_NACK_PLOGI 16 430 #define SRB_NACK_PRLI 17 431 #define SRB_NACK_LOGO 18 432 433 typedef struct srb { 434 atomic_t ref_count; 435 struct fc_port *fcport; 436 struct scsi_qla_host *vha; 437 uint32_t handle; 438 uint16_t flags; 439 uint16_t type; 440 char *name; 441 int iocbs; 442 struct qla_qpair *qpair; 443 u32 gen1; /* scratch */ 444 u32 gen2; /* scratch */ 445 union { 446 struct srb_iocb iocb_cmd; 447 struct bsg_job *bsg_job; 448 struct srb_cmd scmd; 449 } u; 450 void (*done)(void *, int); 451 void (*free)(void *); 452 } srb_t; 453 454 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 455 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 456 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 457 458 #define GET_CMD_SENSE_LEN(sp) \ 459 (sp->u.scmd.request_sense_length) 460 #define SET_CMD_SENSE_LEN(sp, len) \ 461 (sp->u.scmd.request_sense_length = len) 462 #define GET_CMD_SENSE_PTR(sp) \ 463 (sp->u.scmd.request_sense_ptr) 464 #define SET_CMD_SENSE_PTR(sp, ptr) \ 465 (sp->u.scmd.request_sense_ptr = ptr) 466 #define GET_FW_SENSE_LEN(sp) \ 467 (sp->u.scmd.fw_sense_length) 468 #define SET_FW_SENSE_LEN(sp, len) \ 469 (sp->u.scmd.fw_sense_length = len) 470 471 struct msg_echo_lb { 472 dma_addr_t send_dma; 473 dma_addr_t rcv_dma; 474 uint16_t req_sg_cnt; 475 uint16_t rsp_sg_cnt; 476 uint16_t options; 477 uint32_t transfer_size; 478 uint32_t iteration_count; 479 }; 480 481 /* 482 * ISP I/O Register Set structure definitions. 483 */ 484 struct device_reg_2xxx { 485 uint16_t flash_address; /* Flash BIOS address */ 486 uint16_t flash_data; /* Flash BIOS data */ 487 uint16_t unused_1[1]; /* Gap */ 488 uint16_t ctrl_status; /* Control/Status */ 489 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 490 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 491 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 492 493 uint16_t ictrl; /* Interrupt control */ 494 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 495 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 496 497 uint16_t istatus; /* Interrupt status */ 498 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 499 500 uint16_t semaphore; /* Semaphore */ 501 uint16_t nvram; /* NVRAM register. */ 502 #define NVR_DESELECT 0 503 #define NVR_BUSY BIT_15 504 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 505 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 506 #define NVR_DATA_IN BIT_3 507 #define NVR_DATA_OUT BIT_2 508 #define NVR_SELECT BIT_1 509 #define NVR_CLOCK BIT_0 510 511 #define NVR_WAIT_CNT 20000 512 513 union { 514 struct { 515 uint16_t mailbox0; 516 uint16_t mailbox1; 517 uint16_t mailbox2; 518 uint16_t mailbox3; 519 uint16_t mailbox4; 520 uint16_t mailbox5; 521 uint16_t mailbox6; 522 uint16_t mailbox7; 523 uint16_t unused_2[59]; /* Gap */ 524 } __attribute__((packed)) isp2100; 525 struct { 526 /* Request Queue */ 527 uint16_t req_q_in; /* In-Pointer */ 528 uint16_t req_q_out; /* Out-Pointer */ 529 /* Response Queue */ 530 uint16_t rsp_q_in; /* In-Pointer */ 531 uint16_t rsp_q_out; /* Out-Pointer */ 532 533 /* RISC to Host Status */ 534 uint32_t host_status; 535 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 536 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 537 538 /* Host to Host Semaphore */ 539 uint16_t host_semaphore; 540 uint16_t unused_3[17]; /* Gap */ 541 uint16_t mailbox0; 542 uint16_t mailbox1; 543 uint16_t mailbox2; 544 uint16_t mailbox3; 545 uint16_t mailbox4; 546 uint16_t mailbox5; 547 uint16_t mailbox6; 548 uint16_t mailbox7; 549 uint16_t mailbox8; 550 uint16_t mailbox9; 551 uint16_t mailbox10; 552 uint16_t mailbox11; 553 uint16_t mailbox12; 554 uint16_t mailbox13; 555 uint16_t mailbox14; 556 uint16_t mailbox15; 557 uint16_t mailbox16; 558 uint16_t mailbox17; 559 uint16_t mailbox18; 560 uint16_t mailbox19; 561 uint16_t mailbox20; 562 uint16_t mailbox21; 563 uint16_t mailbox22; 564 uint16_t mailbox23; 565 uint16_t mailbox24; 566 uint16_t mailbox25; 567 uint16_t mailbox26; 568 uint16_t mailbox27; 569 uint16_t mailbox28; 570 uint16_t mailbox29; 571 uint16_t mailbox30; 572 uint16_t mailbox31; 573 uint16_t fb_cmd; 574 uint16_t unused_4[10]; /* Gap */ 575 } __attribute__((packed)) isp2300; 576 } u; 577 578 uint16_t fpm_diag_config; 579 uint16_t unused_5[0x4]; /* Gap */ 580 uint16_t risc_hw; 581 uint16_t unused_5_1; /* Gap */ 582 uint16_t pcr; /* Processor Control Register. */ 583 uint16_t unused_6[0x5]; /* Gap */ 584 uint16_t mctr; /* Memory Configuration and Timing. */ 585 uint16_t unused_7[0x3]; /* Gap */ 586 uint16_t fb_cmd_2100; /* Unused on 23XX */ 587 uint16_t unused_8[0x3]; /* Gap */ 588 uint16_t hccr; /* Host command & control register. */ 589 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 590 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 591 /* HCCR commands */ 592 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 593 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 594 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 595 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 596 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 597 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 598 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 599 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 600 601 uint16_t unused_9[5]; /* Gap */ 602 uint16_t gpiod; /* GPIO Data register. */ 603 uint16_t gpioe; /* GPIO Enable register. */ 604 #define GPIO_LED_MASK 0x00C0 605 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 606 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 607 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 608 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 609 #define GPIO_LED_ALL_OFF 0x0000 610 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 611 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 612 613 union { 614 struct { 615 uint16_t unused_10[8]; /* Gap */ 616 uint16_t mailbox8; 617 uint16_t mailbox9; 618 uint16_t mailbox10; 619 uint16_t mailbox11; 620 uint16_t mailbox12; 621 uint16_t mailbox13; 622 uint16_t mailbox14; 623 uint16_t mailbox15; 624 uint16_t mailbox16; 625 uint16_t mailbox17; 626 uint16_t mailbox18; 627 uint16_t mailbox19; 628 uint16_t mailbox20; 629 uint16_t mailbox21; 630 uint16_t mailbox22; 631 uint16_t mailbox23; /* Also probe reg. */ 632 } __attribute__((packed)) isp2200; 633 } u_end; 634 }; 635 636 struct device_reg_25xxmq { 637 uint32_t req_q_in; 638 uint32_t req_q_out; 639 uint32_t rsp_q_in; 640 uint32_t rsp_q_out; 641 uint32_t atio_q_in; 642 uint32_t atio_q_out; 643 }; 644 645 646 struct device_reg_fx00 { 647 uint32_t mailbox0; /* 00 */ 648 uint32_t mailbox1; /* 04 */ 649 uint32_t mailbox2; /* 08 */ 650 uint32_t mailbox3; /* 0C */ 651 uint32_t mailbox4; /* 10 */ 652 uint32_t mailbox5; /* 14 */ 653 uint32_t mailbox6; /* 18 */ 654 uint32_t mailbox7; /* 1C */ 655 uint32_t mailbox8; /* 20 */ 656 uint32_t mailbox9; /* 24 */ 657 uint32_t mailbox10; /* 28 */ 658 uint32_t mailbox11; 659 uint32_t mailbox12; 660 uint32_t mailbox13; 661 uint32_t mailbox14; 662 uint32_t mailbox15; 663 uint32_t mailbox16; 664 uint32_t mailbox17; 665 uint32_t mailbox18; 666 uint32_t mailbox19; 667 uint32_t mailbox20; 668 uint32_t mailbox21; 669 uint32_t mailbox22; 670 uint32_t mailbox23; 671 uint32_t mailbox24; 672 uint32_t mailbox25; 673 uint32_t mailbox26; 674 uint32_t mailbox27; 675 uint32_t mailbox28; 676 uint32_t mailbox29; 677 uint32_t mailbox30; 678 uint32_t mailbox31; 679 uint32_t aenmailbox0; 680 uint32_t aenmailbox1; 681 uint32_t aenmailbox2; 682 uint32_t aenmailbox3; 683 uint32_t aenmailbox4; 684 uint32_t aenmailbox5; 685 uint32_t aenmailbox6; 686 uint32_t aenmailbox7; 687 /* Request Queue. */ 688 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 689 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 690 /* Response Queue. */ 691 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 692 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 693 /* Init values shadowed on FW Up Event */ 694 uint32_t initval0; /* B0 */ 695 uint32_t initval1; /* B4 */ 696 uint32_t initval2; /* B8 */ 697 uint32_t initval3; /* BC */ 698 uint32_t initval4; /* C0 */ 699 uint32_t initval5; /* C4 */ 700 uint32_t initval6; /* C8 */ 701 uint32_t initval7; /* CC */ 702 uint32_t fwheartbeat; /* D0 */ 703 uint32_t pseudoaen; /* D4 */ 704 }; 705 706 707 708 typedef union { 709 struct device_reg_2xxx isp; 710 struct device_reg_24xx isp24; 711 struct device_reg_25xxmq isp25mq; 712 struct device_reg_82xx isp82; 713 struct device_reg_fx00 ispfx00; 714 } __iomem device_reg_t; 715 716 #define ISP_REQ_Q_IN(ha, reg) \ 717 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 718 &(reg)->u.isp2100.mailbox4 : \ 719 &(reg)->u.isp2300.req_q_in) 720 #define ISP_REQ_Q_OUT(ha, reg) \ 721 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 722 &(reg)->u.isp2100.mailbox4 : \ 723 &(reg)->u.isp2300.req_q_out) 724 #define ISP_RSP_Q_IN(ha, reg) \ 725 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 726 &(reg)->u.isp2100.mailbox5 : \ 727 &(reg)->u.isp2300.rsp_q_in) 728 #define ISP_RSP_Q_OUT(ha, reg) \ 729 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 730 &(reg)->u.isp2100.mailbox5 : \ 731 &(reg)->u.isp2300.rsp_q_out) 732 733 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 734 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 735 736 #define MAILBOX_REG(ha, reg, num) \ 737 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 738 (num < 8 ? \ 739 &(reg)->u.isp2100.mailbox0 + (num) : \ 740 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 741 &(reg)->u.isp2300.mailbox0 + (num)) 742 #define RD_MAILBOX_REG(ha, reg, num) \ 743 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 744 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 745 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 746 747 #define FB_CMD_REG(ha, reg) \ 748 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 749 &(reg)->fb_cmd_2100 : \ 750 &(reg)->u.isp2300.fb_cmd) 751 #define RD_FB_CMD_REG(ha, reg) \ 752 RD_REG_WORD(FB_CMD_REG(ha, reg)) 753 #define WRT_FB_CMD_REG(ha, reg, data) \ 754 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 755 756 typedef struct { 757 uint32_t out_mb; /* outbound from driver */ 758 uint32_t in_mb; /* Incoming from RISC */ 759 uint16_t mb[MAILBOX_REGISTER_COUNT]; 760 long buf_size; 761 void *bufp; 762 uint32_t tov; 763 uint8_t flags; 764 #define MBX_DMA_IN BIT_0 765 #define MBX_DMA_OUT BIT_1 766 #define IOCTL_CMD BIT_2 767 } mbx_cmd_t; 768 769 struct mbx_cmd_32 { 770 uint32_t out_mb; /* outbound from driver */ 771 uint32_t in_mb; /* Incoming from RISC */ 772 uint32_t mb[MAILBOX_REGISTER_COUNT]; 773 long buf_size; 774 void *bufp; 775 uint32_t tov; 776 uint8_t flags; 777 #define MBX_DMA_IN BIT_0 778 #define MBX_DMA_OUT BIT_1 779 #define IOCTL_CMD BIT_2 780 }; 781 782 783 #define MBX_TOV_SECONDS 30 784 785 /* 786 * ISP product identification definitions in mailboxes after reset. 787 */ 788 #define PROD_ID_1 0x4953 789 #define PROD_ID_2 0x0000 790 #define PROD_ID_2a 0x5020 791 #define PROD_ID_3 0x2020 792 793 /* 794 * ISP mailbox Self-Test status codes 795 */ 796 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 797 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 798 #define MBS_BUSY 4 /* Busy. */ 799 800 /* 801 * ISP mailbox command complete status codes 802 */ 803 #define MBS_COMMAND_COMPLETE 0x4000 804 #define MBS_INVALID_COMMAND 0x4001 805 #define MBS_HOST_INTERFACE_ERROR 0x4002 806 #define MBS_TEST_FAILED 0x4003 807 #define MBS_COMMAND_ERROR 0x4005 808 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 809 #define MBS_PORT_ID_USED 0x4007 810 #define MBS_LOOP_ID_USED 0x4008 811 #define MBS_ALL_IDS_IN_USE 0x4009 812 #define MBS_NOT_LOGGED_IN 0x400A 813 #define MBS_LINK_DOWN_ERROR 0x400B 814 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 815 816 /* 817 * ISP mailbox asynchronous event status codes 818 */ 819 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 820 #define MBA_RESET 0x8001 /* Reset Detected. */ 821 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 822 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 823 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 824 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 825 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 826 /* occurred. */ 827 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 828 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 829 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 830 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 831 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 832 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 833 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 834 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 835 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 836 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 837 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 838 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 839 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 840 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 841 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 842 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 843 /* used. */ 844 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 845 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 846 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 847 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 848 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 849 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 850 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 851 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 852 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 853 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 854 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 855 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 856 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 857 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 858 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 859 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 860 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 861 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 862 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 863 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 864 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 865 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 866 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 867 Notification */ 868 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 869 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 870 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 871 /* 83XX FCoE specific */ 872 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 873 874 /* Interrupt type codes */ 875 #define INTR_ROM_MB_SUCCESS 0x1 876 #define INTR_ROM_MB_FAILED 0x2 877 #define INTR_MB_SUCCESS 0x10 878 #define INTR_MB_FAILED 0x11 879 #define INTR_ASYNC_EVENT 0x12 880 #define INTR_RSP_QUE_UPDATE 0x13 881 #define INTR_RSP_QUE_UPDATE_83XX 0x14 882 #define INTR_ATIO_QUE_UPDATE 0x1C 883 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 884 885 /* ISP mailbox loopback echo diagnostic error code */ 886 #define MBS_LB_RESET 0x17 887 /* 888 * Firmware options 1, 2, 3. 889 */ 890 #define FO1_AE_ON_LIPF8 BIT_0 891 #define FO1_AE_ALL_LIP_RESET BIT_1 892 #define FO1_CTIO_RETRY BIT_3 893 #define FO1_DISABLE_LIP_F7_SW BIT_4 894 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 895 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 896 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 897 #define FO1_SET_EMPHASIS_SWING BIT_8 898 #define FO1_AE_AUTO_BYPASS BIT_9 899 #define FO1_ENABLE_PURE_IOCB BIT_10 900 #define FO1_AE_PLOGI_RJT BIT_11 901 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 902 #define FO1_AE_QUEUE_FULL BIT_13 903 904 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 905 #define FO2_REV_LOOPBACK BIT_1 906 907 #define FO3_ENABLE_EMERG_IOCB BIT_0 908 #define FO3_AE_RND_ERROR BIT_1 909 910 /* 24XX additional firmware options */ 911 #define ADD_FO_COUNT 3 912 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 913 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 914 915 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 916 917 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 918 919 /* 920 * ISP mailbox commands 921 */ 922 #define MBC_LOAD_RAM 1 /* Load RAM. */ 923 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 924 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 925 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 926 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 927 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 928 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 929 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 930 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 931 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 932 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 933 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 934 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 935 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 936 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 937 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 938 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 939 #define MBC_RESET 0x18 /* Reset. */ 940 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 941 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 942 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 943 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 944 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 945 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 946 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 947 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 948 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 949 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 950 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 951 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 952 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 953 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 954 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 955 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 956 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 957 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 958 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 959 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 960 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 961 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 962 #define MBC_DATA_RATE 0x5d /* Data Rate */ 963 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 964 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 965 /* Initialization Procedure */ 966 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 967 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 968 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 969 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 970 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 971 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 972 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 973 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 974 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 975 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 976 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 977 /* commandd. */ 978 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 979 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 980 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 981 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 982 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 983 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 984 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 985 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 986 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 987 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 988 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 989 990 /* 991 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 992 * should be defined with MBC_MR_* 993 */ 994 #define MBC_MR_DRV_SHUTDOWN 0x6A 995 996 /* 997 * ISP24xx mailbox commands 998 */ 999 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1000 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1001 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1002 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1003 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1004 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1005 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1006 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1007 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1008 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1009 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1010 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1011 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1012 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1013 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1014 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1015 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1016 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1017 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1018 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1019 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1020 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1021 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1022 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1023 1024 /* 1025 * ISP81xx mailbox commands 1026 */ 1027 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1028 1029 /* 1030 * ISP8044 mailbox commands 1031 */ 1032 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1033 #define HCS_WRITE_SERDES 0x3 1034 #define HCS_READ_SERDES 0x4 1035 1036 /* Firmware return data sizes */ 1037 #define FCAL_MAP_SIZE 128 1038 1039 /* Mailbox bit definitions for out_mb and in_mb */ 1040 #define MBX_31 BIT_31 1041 #define MBX_30 BIT_30 1042 #define MBX_29 BIT_29 1043 #define MBX_28 BIT_28 1044 #define MBX_27 BIT_27 1045 #define MBX_26 BIT_26 1046 #define MBX_25 BIT_25 1047 #define MBX_24 BIT_24 1048 #define MBX_23 BIT_23 1049 #define MBX_22 BIT_22 1050 #define MBX_21 BIT_21 1051 #define MBX_20 BIT_20 1052 #define MBX_19 BIT_19 1053 #define MBX_18 BIT_18 1054 #define MBX_17 BIT_17 1055 #define MBX_16 BIT_16 1056 #define MBX_15 BIT_15 1057 #define MBX_14 BIT_14 1058 #define MBX_13 BIT_13 1059 #define MBX_12 BIT_12 1060 #define MBX_11 BIT_11 1061 #define MBX_10 BIT_10 1062 #define MBX_9 BIT_9 1063 #define MBX_8 BIT_8 1064 #define MBX_7 BIT_7 1065 #define MBX_6 BIT_6 1066 #define MBX_5 BIT_5 1067 #define MBX_4 BIT_4 1068 #define MBX_3 BIT_3 1069 #define MBX_2 BIT_2 1070 #define MBX_1 BIT_1 1071 #define MBX_0 BIT_0 1072 1073 #define RNID_TYPE_SET_VERSION 0x9 1074 #define RNID_TYPE_ASIC_TEMP 0xC 1075 1076 /* 1077 * Firmware state codes from get firmware state mailbox command 1078 */ 1079 #define FSTATE_CONFIG_WAIT 0 1080 #define FSTATE_WAIT_AL_PA 1 1081 #define FSTATE_WAIT_LOGIN 2 1082 #define FSTATE_READY 3 1083 #define FSTATE_LOSS_OF_SYNC 4 1084 #define FSTATE_ERROR 5 1085 #define FSTATE_REINIT 6 1086 #define FSTATE_NON_PART 7 1087 1088 #define FSTATE_CONFIG_CORRECT 0 1089 #define FSTATE_P2P_RCV_LIP 1 1090 #define FSTATE_P2P_CHOOSE_LOOP 2 1091 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1092 #define FSTATE_FATAL_ERROR 4 1093 #define FSTATE_LOOP_BACK_CONN 5 1094 1095 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1096 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1097 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1098 #define QLA27XX_PRIMARY_IMAGE 1 1099 #define QLA27XX_SECONDARY_IMAGE 2 1100 1101 /* 1102 * Port Database structure definition 1103 * Little endian except where noted. 1104 */ 1105 #define PORT_DATABASE_SIZE 128 /* bytes */ 1106 typedef struct { 1107 uint8_t options; 1108 uint8_t control; 1109 uint8_t master_state; 1110 uint8_t slave_state; 1111 uint8_t reserved[2]; 1112 uint8_t hard_address; 1113 uint8_t reserved_1; 1114 uint8_t port_id[4]; 1115 uint8_t node_name[WWN_SIZE]; 1116 uint8_t port_name[WWN_SIZE]; 1117 uint16_t execution_throttle; 1118 uint16_t execution_count; 1119 uint8_t reset_count; 1120 uint8_t reserved_2; 1121 uint16_t resource_allocation; 1122 uint16_t current_allocation; 1123 uint16_t queue_head; 1124 uint16_t queue_tail; 1125 uint16_t transmit_execution_list_next; 1126 uint16_t transmit_execution_list_previous; 1127 uint16_t common_features; 1128 uint16_t total_concurrent_sequences; 1129 uint16_t RO_by_information_category; 1130 uint8_t recipient; 1131 uint8_t initiator; 1132 uint16_t receive_data_size; 1133 uint16_t concurrent_sequences; 1134 uint16_t open_sequences_per_exchange; 1135 uint16_t lun_abort_flags; 1136 uint16_t lun_stop_flags; 1137 uint16_t stop_queue_head; 1138 uint16_t stop_queue_tail; 1139 uint16_t port_retry_timer; 1140 uint16_t next_sequence_id; 1141 uint16_t frame_count; 1142 uint16_t PRLI_payload_length; 1143 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1144 /* Bits 15-0 of word 0 */ 1145 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1146 /* Bits 15-0 of word 3 */ 1147 uint16_t loop_id; 1148 uint16_t extended_lun_info_list_pointer; 1149 uint16_t extended_lun_stop_list_pointer; 1150 } port_database_t; 1151 1152 /* 1153 * Port database slave/master states 1154 */ 1155 #define PD_STATE_DISCOVERY 0 1156 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1157 #define PD_STATE_PORT_LOGIN 2 1158 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1159 #define PD_STATE_PROCESS_LOGIN 4 1160 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1161 #define PD_STATE_PORT_LOGGED_IN 6 1162 #define PD_STATE_PORT_UNAVAILABLE 7 1163 #define PD_STATE_PROCESS_LOGOUT 8 1164 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1165 #define PD_STATE_PORT_LOGOUT 10 1166 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1167 1168 1169 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1170 #define QLA_ZIO_DISABLED 0 1171 #define QLA_ZIO_DEFAULT_TIMER 2 1172 1173 /* 1174 * ISP Initialization Control Block. 1175 * Little endian except where noted. 1176 */ 1177 #define ICB_VERSION 1 1178 typedef struct { 1179 uint8_t version; 1180 uint8_t reserved_1; 1181 1182 /* 1183 * LSB BIT 0 = Enable Hard Loop Id 1184 * LSB BIT 1 = Enable Fairness 1185 * LSB BIT 2 = Enable Full-Duplex 1186 * LSB BIT 3 = Enable Fast Posting 1187 * LSB BIT 4 = Enable Target Mode 1188 * LSB BIT 5 = Disable Initiator Mode 1189 * LSB BIT 6 = Enable ADISC 1190 * LSB BIT 7 = Enable Target Inquiry Data 1191 * 1192 * MSB BIT 0 = Enable PDBC Notify 1193 * MSB BIT 1 = Non Participating LIP 1194 * MSB BIT 2 = Descending Loop ID Search 1195 * MSB BIT 3 = Acquire Loop ID in LIPA 1196 * MSB BIT 4 = Stop PortQ on Full Status 1197 * MSB BIT 5 = Full Login after LIP 1198 * MSB BIT 6 = Node Name Option 1199 * MSB BIT 7 = Ext IFWCB enable bit 1200 */ 1201 uint8_t firmware_options[2]; 1202 1203 uint16_t frame_payload_size; 1204 uint16_t max_iocb_allocation; 1205 uint16_t execution_throttle; 1206 uint8_t retry_count; 1207 uint8_t retry_delay; /* unused */ 1208 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1209 uint16_t hard_address; 1210 uint8_t inquiry_data; 1211 uint8_t login_timeout; 1212 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1213 1214 uint16_t request_q_outpointer; 1215 uint16_t response_q_inpointer; 1216 uint16_t request_q_length; 1217 uint16_t response_q_length; 1218 uint32_t request_q_address[2]; 1219 uint32_t response_q_address[2]; 1220 1221 uint16_t lun_enables; 1222 uint8_t command_resource_count; 1223 uint8_t immediate_notify_resource_count; 1224 uint16_t timeout; 1225 uint8_t reserved_2[2]; 1226 1227 /* 1228 * LSB BIT 0 = Timer Operation mode bit 0 1229 * LSB BIT 1 = Timer Operation mode bit 1 1230 * LSB BIT 2 = Timer Operation mode bit 2 1231 * LSB BIT 3 = Timer Operation mode bit 3 1232 * LSB BIT 4 = Init Config Mode bit 0 1233 * LSB BIT 5 = Init Config Mode bit 1 1234 * LSB BIT 6 = Init Config Mode bit 2 1235 * LSB BIT 7 = Enable Non part on LIHA failure 1236 * 1237 * MSB BIT 0 = Enable class 2 1238 * MSB BIT 1 = Enable ACK0 1239 * MSB BIT 2 = 1240 * MSB BIT 3 = 1241 * MSB BIT 4 = FC Tape Enable 1242 * MSB BIT 5 = Enable FC Confirm 1243 * MSB BIT 6 = Enable command queuing in target mode 1244 * MSB BIT 7 = No Logo On Link Down 1245 */ 1246 uint8_t add_firmware_options[2]; 1247 1248 uint8_t response_accumulation_timer; 1249 uint8_t interrupt_delay_timer; 1250 1251 /* 1252 * LSB BIT 0 = Enable Read xfr_rdy 1253 * LSB BIT 1 = Soft ID only 1254 * LSB BIT 2 = 1255 * LSB BIT 3 = 1256 * LSB BIT 4 = FCP RSP Payload [0] 1257 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1258 * LSB BIT 6 = Enable Out-of-Order frame handling 1259 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1260 * 1261 * MSB BIT 0 = Sbus enable - 2300 1262 * MSB BIT 1 = 1263 * MSB BIT 2 = 1264 * MSB BIT 3 = 1265 * MSB BIT 4 = LED mode 1266 * MSB BIT 5 = enable 50 ohm termination 1267 * MSB BIT 6 = Data Rate (2300 only) 1268 * MSB BIT 7 = Data Rate (2300 only) 1269 */ 1270 uint8_t special_options[2]; 1271 1272 uint8_t reserved_3[26]; 1273 } init_cb_t; 1274 1275 /* 1276 * Get Link Status mailbox command return buffer. 1277 */ 1278 #define GLSO_SEND_RPS BIT_0 1279 #define GLSO_USE_DID BIT_3 1280 1281 struct link_statistics { 1282 uint32_t link_fail_cnt; 1283 uint32_t loss_sync_cnt; 1284 uint32_t loss_sig_cnt; 1285 uint32_t prim_seq_err_cnt; 1286 uint32_t inval_xmit_word_cnt; 1287 uint32_t inval_crc_cnt; 1288 uint32_t lip_cnt; 1289 uint32_t link_up_cnt; 1290 uint32_t link_down_loop_init_tmo; 1291 uint32_t link_down_los; 1292 uint32_t link_down_loss_rcv_clk; 1293 uint32_t reserved0[5]; 1294 uint32_t port_cfg_chg; 1295 uint32_t reserved1[11]; 1296 uint32_t rsp_q_full; 1297 uint32_t atio_q_full; 1298 uint32_t drop_ae; 1299 uint32_t els_proto_err; 1300 uint32_t reserved2; 1301 uint32_t tx_frames; 1302 uint32_t rx_frames; 1303 uint32_t discarded_frames; 1304 uint32_t dropped_frames; 1305 uint32_t reserved3; 1306 uint32_t nos_rcvd; 1307 uint32_t reserved4[4]; 1308 uint32_t tx_prjt; 1309 uint32_t rcv_exfail; 1310 uint32_t rcv_abts; 1311 uint32_t seq_frm_miss; 1312 uint32_t corr_err; 1313 uint32_t mb_rqst; 1314 uint32_t nport_full; 1315 uint32_t eofa; 1316 uint32_t reserved5; 1317 uint32_t fpm_recv_word_cnt_lo; 1318 uint32_t fpm_recv_word_cnt_hi; 1319 uint32_t fpm_disc_word_cnt_lo; 1320 uint32_t fpm_disc_word_cnt_hi; 1321 uint32_t fpm_xmit_word_cnt_lo; 1322 uint32_t fpm_xmit_word_cnt_hi; 1323 uint32_t reserved6[70]; 1324 }; 1325 1326 /* 1327 * NVRAM Command values. 1328 */ 1329 #define NV_START_BIT BIT_2 1330 #define NV_WRITE_OP (BIT_26+BIT_24) 1331 #define NV_READ_OP (BIT_26+BIT_25) 1332 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1333 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1334 #define NV_DELAY_COUNT 10 1335 1336 /* 1337 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1338 */ 1339 typedef struct { 1340 /* 1341 * NVRAM header 1342 */ 1343 uint8_t id[4]; 1344 uint8_t nvram_version; 1345 uint8_t reserved_0; 1346 1347 /* 1348 * NVRAM RISC parameter block 1349 */ 1350 uint8_t parameter_block_version; 1351 uint8_t reserved_1; 1352 1353 /* 1354 * LSB BIT 0 = Enable Hard Loop Id 1355 * LSB BIT 1 = Enable Fairness 1356 * LSB BIT 2 = Enable Full-Duplex 1357 * LSB BIT 3 = Enable Fast Posting 1358 * LSB BIT 4 = Enable Target Mode 1359 * LSB BIT 5 = Disable Initiator Mode 1360 * LSB BIT 6 = Enable ADISC 1361 * LSB BIT 7 = Enable Target Inquiry Data 1362 * 1363 * MSB BIT 0 = Enable PDBC Notify 1364 * MSB BIT 1 = Non Participating LIP 1365 * MSB BIT 2 = Descending Loop ID Search 1366 * MSB BIT 3 = Acquire Loop ID in LIPA 1367 * MSB BIT 4 = Stop PortQ on Full Status 1368 * MSB BIT 5 = Full Login after LIP 1369 * MSB BIT 6 = Node Name Option 1370 * MSB BIT 7 = Ext IFWCB enable bit 1371 */ 1372 uint8_t firmware_options[2]; 1373 1374 uint16_t frame_payload_size; 1375 uint16_t max_iocb_allocation; 1376 uint16_t execution_throttle; 1377 uint8_t retry_count; 1378 uint8_t retry_delay; /* unused */ 1379 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1380 uint16_t hard_address; 1381 uint8_t inquiry_data; 1382 uint8_t login_timeout; 1383 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1384 1385 /* 1386 * LSB BIT 0 = Timer Operation mode bit 0 1387 * LSB BIT 1 = Timer Operation mode bit 1 1388 * LSB BIT 2 = Timer Operation mode bit 2 1389 * LSB BIT 3 = Timer Operation mode bit 3 1390 * LSB BIT 4 = Init Config Mode bit 0 1391 * LSB BIT 5 = Init Config Mode bit 1 1392 * LSB BIT 6 = Init Config Mode bit 2 1393 * LSB BIT 7 = Enable Non part on LIHA failure 1394 * 1395 * MSB BIT 0 = Enable class 2 1396 * MSB BIT 1 = Enable ACK0 1397 * MSB BIT 2 = 1398 * MSB BIT 3 = 1399 * MSB BIT 4 = FC Tape Enable 1400 * MSB BIT 5 = Enable FC Confirm 1401 * MSB BIT 6 = Enable command queuing in target mode 1402 * MSB BIT 7 = No Logo On Link Down 1403 */ 1404 uint8_t add_firmware_options[2]; 1405 1406 uint8_t response_accumulation_timer; 1407 uint8_t interrupt_delay_timer; 1408 1409 /* 1410 * LSB BIT 0 = Enable Read xfr_rdy 1411 * LSB BIT 1 = Soft ID only 1412 * LSB BIT 2 = 1413 * LSB BIT 3 = 1414 * LSB BIT 4 = FCP RSP Payload [0] 1415 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1416 * LSB BIT 6 = Enable Out-of-Order frame handling 1417 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1418 * 1419 * MSB BIT 0 = Sbus enable - 2300 1420 * MSB BIT 1 = 1421 * MSB BIT 2 = 1422 * MSB BIT 3 = 1423 * MSB BIT 4 = LED mode 1424 * MSB BIT 5 = enable 50 ohm termination 1425 * MSB BIT 6 = Data Rate (2300 only) 1426 * MSB BIT 7 = Data Rate (2300 only) 1427 */ 1428 uint8_t special_options[2]; 1429 1430 /* Reserved for expanded RISC parameter block */ 1431 uint8_t reserved_2[22]; 1432 1433 /* 1434 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1435 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1436 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1437 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1438 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1439 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1440 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1441 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1442 * 1443 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1444 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1445 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1446 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1447 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1448 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1449 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1450 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1451 * 1452 * LSB BIT 0 = Output Swing 1G bit 0 1453 * LSB BIT 1 = Output Swing 1G bit 1 1454 * LSB BIT 2 = Output Swing 1G bit 2 1455 * LSB BIT 3 = Output Emphasis 1G bit 0 1456 * LSB BIT 4 = Output Emphasis 1G bit 1 1457 * LSB BIT 5 = Output Swing 2G bit 0 1458 * LSB BIT 6 = Output Swing 2G bit 1 1459 * LSB BIT 7 = Output Swing 2G bit 2 1460 * 1461 * MSB BIT 0 = Output Emphasis 2G bit 0 1462 * MSB BIT 1 = Output Emphasis 2G bit 1 1463 * MSB BIT 2 = Output Enable 1464 * MSB BIT 3 = 1465 * MSB BIT 4 = 1466 * MSB BIT 5 = 1467 * MSB BIT 6 = 1468 * MSB BIT 7 = 1469 */ 1470 uint8_t seriallink_options[4]; 1471 1472 /* 1473 * NVRAM host parameter block 1474 * 1475 * LSB BIT 0 = Enable spinup delay 1476 * LSB BIT 1 = Disable BIOS 1477 * LSB BIT 2 = Enable Memory Map BIOS 1478 * LSB BIT 3 = Enable Selectable Boot 1479 * LSB BIT 4 = Disable RISC code load 1480 * LSB BIT 5 = Set cache line size 1 1481 * LSB BIT 6 = PCI Parity Disable 1482 * LSB BIT 7 = Enable extended logging 1483 * 1484 * MSB BIT 0 = Enable 64bit addressing 1485 * MSB BIT 1 = Enable lip reset 1486 * MSB BIT 2 = Enable lip full login 1487 * MSB BIT 3 = Enable target reset 1488 * MSB BIT 4 = Enable database storage 1489 * MSB BIT 5 = Enable cache flush read 1490 * MSB BIT 6 = Enable database load 1491 * MSB BIT 7 = Enable alternate WWN 1492 */ 1493 uint8_t host_p[2]; 1494 1495 uint8_t boot_node_name[WWN_SIZE]; 1496 uint8_t boot_lun_number; 1497 uint8_t reset_delay; 1498 uint8_t port_down_retry_count; 1499 uint8_t boot_id_number; 1500 uint16_t max_luns_per_target; 1501 uint8_t fcode_boot_port_name[WWN_SIZE]; 1502 uint8_t alternate_port_name[WWN_SIZE]; 1503 uint8_t alternate_node_name[WWN_SIZE]; 1504 1505 /* 1506 * BIT 0 = Selective Login 1507 * BIT 1 = Alt-Boot Enable 1508 * BIT 2 = 1509 * BIT 3 = Boot Order List 1510 * BIT 4 = 1511 * BIT 5 = Selective LUN 1512 * BIT 6 = 1513 * BIT 7 = unused 1514 */ 1515 uint8_t efi_parameters; 1516 1517 uint8_t link_down_timeout; 1518 1519 uint8_t adapter_id[16]; 1520 1521 uint8_t alt1_boot_node_name[WWN_SIZE]; 1522 uint16_t alt1_boot_lun_number; 1523 uint8_t alt2_boot_node_name[WWN_SIZE]; 1524 uint16_t alt2_boot_lun_number; 1525 uint8_t alt3_boot_node_name[WWN_SIZE]; 1526 uint16_t alt3_boot_lun_number; 1527 uint8_t alt4_boot_node_name[WWN_SIZE]; 1528 uint16_t alt4_boot_lun_number; 1529 uint8_t alt5_boot_node_name[WWN_SIZE]; 1530 uint16_t alt5_boot_lun_number; 1531 uint8_t alt6_boot_node_name[WWN_SIZE]; 1532 uint16_t alt6_boot_lun_number; 1533 uint8_t alt7_boot_node_name[WWN_SIZE]; 1534 uint16_t alt7_boot_lun_number; 1535 1536 uint8_t reserved_3[2]; 1537 1538 /* Offset 200-215 : Model Number */ 1539 uint8_t model_number[16]; 1540 1541 /* OEM related items */ 1542 uint8_t oem_specific[16]; 1543 1544 /* 1545 * NVRAM Adapter Features offset 232-239 1546 * 1547 * LSB BIT 0 = External GBIC 1548 * LSB BIT 1 = Risc RAM parity 1549 * LSB BIT 2 = Buffer Plus Module 1550 * LSB BIT 3 = Multi Chip Adapter 1551 * LSB BIT 4 = Internal connector 1552 * LSB BIT 5 = 1553 * LSB BIT 6 = 1554 * LSB BIT 7 = 1555 * 1556 * MSB BIT 0 = 1557 * MSB BIT 1 = 1558 * MSB BIT 2 = 1559 * MSB BIT 3 = 1560 * MSB BIT 4 = 1561 * MSB BIT 5 = 1562 * MSB BIT 6 = 1563 * MSB BIT 7 = 1564 */ 1565 uint8_t adapter_features[2]; 1566 1567 uint8_t reserved_4[16]; 1568 1569 /* Subsystem vendor ID for ISP2200 */ 1570 uint16_t subsystem_vendor_id_2200; 1571 1572 /* Subsystem device ID for ISP2200 */ 1573 uint16_t subsystem_device_id_2200; 1574 1575 uint8_t reserved_5; 1576 uint8_t checksum; 1577 } nvram_t; 1578 1579 /* 1580 * ISP queue - response queue entry definition. 1581 */ 1582 typedef struct { 1583 uint8_t entry_type; /* Entry type. */ 1584 uint8_t entry_count; /* Entry count. */ 1585 uint8_t sys_define; /* System defined. */ 1586 uint8_t entry_status; /* Entry Status. */ 1587 uint32_t handle; /* System defined handle */ 1588 uint8_t data[52]; 1589 uint32_t signature; 1590 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1591 } response_t; 1592 1593 /* 1594 * ISP queue - ATIO queue entry definition. 1595 */ 1596 struct atio { 1597 uint8_t entry_type; /* Entry type. */ 1598 uint8_t entry_count; /* Entry count. */ 1599 __le16 attr_n_length; 1600 uint8_t data[56]; 1601 uint32_t signature; 1602 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1603 }; 1604 1605 typedef union { 1606 uint16_t extended; 1607 struct { 1608 uint8_t reserved; 1609 uint8_t standard; 1610 } id; 1611 } target_id_t; 1612 1613 #define SET_TARGET_ID(ha, to, from) \ 1614 do { \ 1615 if (HAS_EXTENDED_IDS(ha)) \ 1616 to.extended = cpu_to_le16(from); \ 1617 else \ 1618 to.id.standard = (uint8_t)from; \ 1619 } while (0) 1620 1621 /* 1622 * ISP queue - command entry structure definition. 1623 */ 1624 #define COMMAND_TYPE 0x11 /* Command entry */ 1625 typedef struct { 1626 uint8_t entry_type; /* Entry type. */ 1627 uint8_t entry_count; /* Entry count. */ 1628 uint8_t sys_define; /* System defined. */ 1629 uint8_t entry_status; /* Entry Status. */ 1630 uint32_t handle; /* System handle. */ 1631 target_id_t target; /* SCSI ID */ 1632 uint16_t lun; /* SCSI LUN */ 1633 uint16_t control_flags; /* Control flags. */ 1634 #define CF_WRITE BIT_6 1635 #define CF_READ BIT_5 1636 #define CF_SIMPLE_TAG BIT_3 1637 #define CF_ORDERED_TAG BIT_2 1638 #define CF_HEAD_TAG BIT_1 1639 uint16_t reserved_1; 1640 uint16_t timeout; /* Command timeout. */ 1641 uint16_t dseg_count; /* Data segment count. */ 1642 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1643 uint32_t byte_count; /* Total byte count. */ 1644 uint32_t dseg_0_address; /* Data segment 0 address. */ 1645 uint32_t dseg_0_length; /* Data segment 0 length. */ 1646 uint32_t dseg_1_address; /* Data segment 1 address. */ 1647 uint32_t dseg_1_length; /* Data segment 1 length. */ 1648 uint32_t dseg_2_address; /* Data segment 2 address. */ 1649 uint32_t dseg_2_length; /* Data segment 2 length. */ 1650 } cmd_entry_t; 1651 1652 /* 1653 * ISP queue - 64-Bit addressing, command entry structure definition. 1654 */ 1655 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1656 typedef struct { 1657 uint8_t entry_type; /* Entry type. */ 1658 uint8_t entry_count; /* Entry count. */ 1659 uint8_t sys_define; /* System defined. */ 1660 uint8_t entry_status; /* Entry Status. */ 1661 uint32_t handle; /* System handle. */ 1662 target_id_t target; /* SCSI ID */ 1663 uint16_t lun; /* SCSI LUN */ 1664 uint16_t control_flags; /* Control flags. */ 1665 uint16_t reserved_1; 1666 uint16_t timeout; /* Command timeout. */ 1667 uint16_t dseg_count; /* Data segment count. */ 1668 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1669 uint32_t byte_count; /* Total byte count. */ 1670 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1671 uint32_t dseg_0_length; /* Data segment 0 length. */ 1672 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1673 uint32_t dseg_1_length; /* Data segment 1 length. */ 1674 } cmd_a64_entry_t, request_t; 1675 1676 /* 1677 * ISP queue - continuation entry structure definition. 1678 */ 1679 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1680 typedef struct { 1681 uint8_t entry_type; /* Entry type. */ 1682 uint8_t entry_count; /* Entry count. */ 1683 uint8_t sys_define; /* System defined. */ 1684 uint8_t entry_status; /* Entry Status. */ 1685 uint32_t reserved; 1686 uint32_t dseg_0_address; /* Data segment 0 address. */ 1687 uint32_t dseg_0_length; /* Data segment 0 length. */ 1688 uint32_t dseg_1_address; /* Data segment 1 address. */ 1689 uint32_t dseg_1_length; /* Data segment 1 length. */ 1690 uint32_t dseg_2_address; /* Data segment 2 address. */ 1691 uint32_t dseg_2_length; /* Data segment 2 length. */ 1692 uint32_t dseg_3_address; /* Data segment 3 address. */ 1693 uint32_t dseg_3_length; /* Data segment 3 length. */ 1694 uint32_t dseg_4_address; /* Data segment 4 address. */ 1695 uint32_t dseg_4_length; /* Data segment 4 length. */ 1696 uint32_t dseg_5_address; /* Data segment 5 address. */ 1697 uint32_t dseg_5_length; /* Data segment 5 length. */ 1698 uint32_t dseg_6_address; /* Data segment 6 address. */ 1699 uint32_t dseg_6_length; /* Data segment 6 length. */ 1700 } cont_entry_t; 1701 1702 /* 1703 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1704 */ 1705 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1706 typedef struct { 1707 uint8_t entry_type; /* Entry type. */ 1708 uint8_t entry_count; /* Entry count. */ 1709 uint8_t sys_define; /* System defined. */ 1710 uint8_t entry_status; /* Entry Status. */ 1711 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1712 uint32_t dseg_0_length; /* Data segment 0 length. */ 1713 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1714 uint32_t dseg_1_length; /* Data segment 1 length. */ 1715 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1716 uint32_t dseg_2_length; /* Data segment 2 length. */ 1717 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1718 uint32_t dseg_3_length; /* Data segment 3 length. */ 1719 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1720 uint32_t dseg_4_length; /* Data segment 4 length. */ 1721 } cont_a64_entry_t; 1722 1723 #define PO_MODE_DIF_INSERT 0 1724 #define PO_MODE_DIF_REMOVE 1 1725 #define PO_MODE_DIF_PASS 2 1726 #define PO_MODE_DIF_REPLACE 3 1727 #define PO_MODE_DIF_TCP_CKSUM 6 1728 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1729 #define PO_DISABLE_GUARD_CHECK BIT_4 1730 #define PO_DISABLE_INCR_REF_TAG BIT_5 1731 #define PO_DIS_HEADER_MODE BIT_7 1732 #define PO_ENABLE_DIF_BUNDLING BIT_8 1733 #define PO_DIS_FRAME_MODE BIT_9 1734 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1735 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1736 1737 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1738 #define PO_DIS_REF_TAG_REPL BIT_13 1739 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1740 #define PO_DIS_REF_TAG_VALD BIT_15 1741 1742 /* 1743 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1744 */ 1745 struct crc_context { 1746 uint32_t handle; /* System handle. */ 1747 __le32 ref_tag; 1748 __le16 app_tag; 1749 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1750 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1751 __le16 guard_seed; /* Initial Guard Seed */ 1752 __le16 prot_opts; /* Requested Data Protection Mode */ 1753 __le16 blk_size; /* Data size in bytes */ 1754 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1755 * only) */ 1756 __le32 byte_count; /* Total byte count/ total data 1757 * transfer count */ 1758 union { 1759 struct { 1760 uint32_t reserved_1; 1761 uint16_t reserved_2; 1762 uint16_t reserved_3; 1763 uint32_t reserved_4; 1764 uint32_t data_address[2]; 1765 uint32_t data_length; 1766 uint32_t reserved_5[2]; 1767 uint32_t reserved_6; 1768 } nobundling; 1769 struct { 1770 __le32 dif_byte_count; /* Total DIF byte 1771 * count */ 1772 uint16_t reserved_1; 1773 __le16 dseg_count; /* Data segment count */ 1774 uint32_t reserved_2; 1775 uint32_t data_address[2]; 1776 uint32_t data_length; 1777 uint32_t dif_address[2]; 1778 uint32_t dif_length; /* Data segment 0 1779 * length */ 1780 } bundling; 1781 } u; 1782 1783 struct fcp_cmnd fcp_cmnd; 1784 dma_addr_t crc_ctx_dma; 1785 /* List of DMA context transfers */ 1786 struct list_head dsd_list; 1787 1788 /* This structure should not exceed 512 bytes */ 1789 }; 1790 1791 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1792 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1793 1794 /* 1795 * ISP queue - status entry structure definition. 1796 */ 1797 #define STATUS_TYPE 0x03 /* Status entry. */ 1798 typedef struct { 1799 uint8_t entry_type; /* Entry type. */ 1800 uint8_t entry_count; /* Entry count. */ 1801 uint8_t sys_define; /* System defined. */ 1802 uint8_t entry_status; /* Entry Status. */ 1803 uint32_t handle; /* System handle. */ 1804 uint16_t scsi_status; /* SCSI status. */ 1805 uint16_t comp_status; /* Completion status. */ 1806 uint16_t state_flags; /* State flags. */ 1807 uint16_t status_flags; /* Status flags. */ 1808 uint16_t rsp_info_len; /* Response Info Length. */ 1809 uint16_t req_sense_length; /* Request sense data length. */ 1810 uint32_t residual_length; /* Residual transfer length. */ 1811 uint8_t rsp_info[8]; /* FCP response information. */ 1812 uint8_t req_sense_data[32]; /* Request sense data. */ 1813 } sts_entry_t; 1814 1815 /* 1816 * Status entry entry status 1817 */ 1818 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1819 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1820 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1821 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1822 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1823 #define RF_BUSY BIT_1 /* Busy */ 1824 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1825 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1826 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1827 RF_INV_E_TYPE) 1828 1829 /* 1830 * Status entry SCSI status bit definitions. 1831 */ 1832 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1833 #define SS_RESIDUAL_UNDER BIT_11 1834 #define SS_RESIDUAL_OVER BIT_10 1835 #define SS_SENSE_LEN_VALID BIT_9 1836 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1837 #define SS_SCSI_STATUS_BYTE 0xff 1838 1839 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1840 #define SS_BUSY_CONDITION BIT_3 1841 #define SS_CONDITION_MET BIT_2 1842 #define SS_CHECK_CONDITION BIT_1 1843 1844 /* 1845 * Status entry completion status 1846 */ 1847 #define CS_COMPLETE 0x0 /* No errors */ 1848 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1849 #define CS_DMA 0x2 /* A DMA direction error. */ 1850 #define CS_TRANSPORT 0x3 /* Transport error. */ 1851 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1852 #define CS_ABORTED 0x5 /* System aborted command. */ 1853 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1854 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1855 #define CS_DIF_ERROR 0xC /* DIF error detected */ 1856 1857 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1858 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1859 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1860 /* (selection timeout) */ 1861 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1862 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1863 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1864 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1865 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 1866 failure */ 1867 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1868 #define CS_UNKNOWN 0x81 /* Driver defined */ 1869 #define CS_RETRY 0x82 /* Driver defined */ 1870 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1871 1872 #define CS_BIDIR_RD_OVERRUN 0x700 1873 #define CS_BIDIR_RD_WR_OVERRUN 0x707 1874 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 1875 #define CS_BIDIR_RD_UNDERRUN 0x1500 1876 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 1877 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 1878 #define CS_BIDIR_DMA 0x200 1879 /* 1880 * Status entry status flags 1881 */ 1882 #define SF_ABTS_TERMINATED BIT_10 1883 #define SF_LOGOUT_SENT BIT_13 1884 1885 /* 1886 * ISP queue - status continuation entry structure definition. 1887 */ 1888 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1889 typedef struct { 1890 uint8_t entry_type; /* Entry type. */ 1891 uint8_t entry_count; /* Entry count. */ 1892 uint8_t sys_define; /* System defined. */ 1893 uint8_t entry_status; /* Entry Status. */ 1894 uint8_t data[60]; /* data */ 1895 } sts_cont_entry_t; 1896 1897 /* 1898 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1899 * structure definition. 1900 */ 1901 #define STATUS_TYPE_21 0x21 /* Status entry. */ 1902 typedef struct { 1903 uint8_t entry_type; /* Entry type. */ 1904 uint8_t entry_count; /* Entry count. */ 1905 uint8_t handle_count; /* Handle count. */ 1906 uint8_t entry_status; /* Entry Status. */ 1907 uint32_t handle[15]; /* System handles. */ 1908 } sts21_entry_t; 1909 1910 /* 1911 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1912 * structure definition. 1913 */ 1914 #define STATUS_TYPE_22 0x22 /* Status entry. */ 1915 typedef struct { 1916 uint8_t entry_type; /* Entry type. */ 1917 uint8_t entry_count; /* Entry count. */ 1918 uint8_t handle_count; /* Handle count. */ 1919 uint8_t entry_status; /* Entry Status. */ 1920 uint16_t handle[30]; /* System handles. */ 1921 } sts22_entry_t; 1922 1923 /* 1924 * ISP queue - marker entry structure definition. 1925 */ 1926 #define MARKER_TYPE 0x04 /* Marker entry. */ 1927 typedef struct { 1928 uint8_t entry_type; /* Entry type. */ 1929 uint8_t entry_count; /* Entry count. */ 1930 uint8_t handle_count; /* Handle count. */ 1931 uint8_t entry_status; /* Entry Status. */ 1932 uint32_t sys_define_2; /* System defined. */ 1933 target_id_t target; /* SCSI ID */ 1934 uint8_t modifier; /* Modifier (7-0). */ 1935 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1936 #define MK_SYNC_ID 1 /* Synchronize ID */ 1937 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1938 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 1939 /* clear port changed, */ 1940 /* use sequence number. */ 1941 uint8_t reserved_1; 1942 uint16_t sequence_number; /* Sequence number of event */ 1943 uint16_t lun; /* SCSI LUN */ 1944 uint8_t reserved_2[48]; 1945 } mrk_entry_t; 1946 1947 /* 1948 * ISP queue - Management Server entry structure definition. 1949 */ 1950 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 1951 typedef struct { 1952 uint8_t entry_type; /* Entry type. */ 1953 uint8_t entry_count; /* Entry count. */ 1954 uint8_t handle_count; /* Handle count. */ 1955 uint8_t entry_status; /* Entry Status. */ 1956 uint32_t handle1; /* System handle. */ 1957 target_id_t loop_id; 1958 uint16_t status; 1959 uint16_t control_flags; /* Control flags. */ 1960 uint16_t reserved2; 1961 uint16_t timeout; 1962 uint16_t cmd_dsd_count; 1963 uint16_t total_dsd_count; 1964 uint8_t type; 1965 uint8_t r_ctl; 1966 uint16_t rx_id; 1967 uint16_t reserved3; 1968 uint32_t handle2; 1969 uint32_t rsp_bytecount; 1970 uint32_t req_bytecount; 1971 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 1972 uint32_t dseg_req_length; /* Data segment 0 length. */ 1973 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 1974 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 1975 } ms_iocb_entry_t; 1976 1977 1978 /* 1979 * ISP queue - Mailbox Command entry structure definition. 1980 */ 1981 #define MBX_IOCB_TYPE 0x39 1982 struct mbx_entry { 1983 uint8_t entry_type; 1984 uint8_t entry_count; 1985 uint8_t sys_define1; 1986 /* Use sys_define1 for source type */ 1987 #define SOURCE_SCSI 0x00 1988 #define SOURCE_IP 0x01 1989 #define SOURCE_VI 0x02 1990 #define SOURCE_SCTP 0x03 1991 #define SOURCE_MP 0x04 1992 #define SOURCE_MPIOCTL 0x05 1993 #define SOURCE_ASYNC_IOCB 0x07 1994 1995 uint8_t entry_status; 1996 1997 uint32_t handle; 1998 target_id_t loop_id; 1999 2000 uint16_t status; 2001 uint16_t state_flags; 2002 uint16_t status_flags; 2003 2004 uint32_t sys_define2[2]; 2005 2006 uint16_t mb0; 2007 uint16_t mb1; 2008 uint16_t mb2; 2009 uint16_t mb3; 2010 uint16_t mb6; 2011 uint16_t mb7; 2012 uint16_t mb9; 2013 uint16_t mb10; 2014 uint32_t reserved_2[2]; 2015 uint8_t node_name[WWN_SIZE]; 2016 uint8_t port_name[WWN_SIZE]; 2017 }; 2018 2019 #ifndef IMMED_NOTIFY_TYPE 2020 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2021 /* 2022 * ISP queue - immediate notify entry structure definition. 2023 * This is sent by the ISP to the Target driver. 2024 * This IOCB would have report of events sent by the 2025 * initiator, that needs to be handled by the target 2026 * driver immediately. 2027 */ 2028 struct imm_ntfy_from_isp { 2029 uint8_t entry_type; /* Entry type. */ 2030 uint8_t entry_count; /* Entry count. */ 2031 uint8_t sys_define; /* System defined. */ 2032 uint8_t entry_status; /* Entry Status. */ 2033 union { 2034 struct { 2035 uint32_t sys_define_2; /* System defined. */ 2036 target_id_t target; 2037 uint16_t lun; 2038 uint8_t target_id; 2039 uint8_t reserved_1; 2040 uint16_t status_modifier; 2041 uint16_t status; 2042 uint16_t task_flags; 2043 uint16_t seq_id; 2044 uint16_t srr_rx_id; 2045 uint32_t srr_rel_offs; 2046 uint16_t srr_ui; 2047 #define SRR_IU_DATA_IN 0x1 2048 #define SRR_IU_DATA_OUT 0x5 2049 #define SRR_IU_STATUS 0x7 2050 uint16_t srr_ox_id; 2051 uint8_t reserved_2[28]; 2052 } isp2x; 2053 struct { 2054 uint32_t reserved; 2055 uint16_t nport_handle; 2056 uint16_t reserved_2; 2057 uint16_t flags; 2058 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2059 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2060 uint16_t srr_rx_id; 2061 uint16_t status; 2062 uint8_t status_subcode; 2063 uint8_t fw_handle; 2064 uint32_t exchange_address; 2065 uint32_t srr_rel_offs; 2066 uint16_t srr_ui; 2067 uint16_t srr_ox_id; 2068 union { 2069 struct { 2070 uint8_t node_name[8]; 2071 } plogi; /* PLOGI/ADISC/PDISC */ 2072 struct { 2073 /* PRLI word 3 bit 0-15 */ 2074 uint16_t wd3_lo; 2075 uint8_t resv0[6]; 2076 } prli; 2077 struct { 2078 uint8_t port_id[3]; 2079 uint8_t resv1; 2080 uint16_t nport_handle; 2081 uint16_t resv2; 2082 } req_els; 2083 } u; 2084 uint8_t port_name[8]; 2085 uint8_t resv3[3]; 2086 uint8_t vp_index; 2087 uint32_t reserved_5; 2088 uint8_t port_id[3]; 2089 uint8_t reserved_6; 2090 } isp24; 2091 } u; 2092 uint16_t reserved_7; 2093 uint16_t ox_id; 2094 } __packed; 2095 #endif 2096 2097 /* 2098 * ISP request and response queue entry sizes 2099 */ 2100 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2101 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2102 2103 2104 /* 2105 * 24 bit port ID type definition. 2106 */ 2107 typedef union { 2108 uint32_t b24 : 24; 2109 2110 struct { 2111 #ifdef __BIG_ENDIAN 2112 uint8_t domain; 2113 uint8_t area; 2114 uint8_t al_pa; 2115 #elif defined(__LITTLE_ENDIAN) 2116 uint8_t al_pa; 2117 uint8_t area; 2118 uint8_t domain; 2119 #else 2120 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 2121 #endif 2122 uint8_t rsvd_1; 2123 } b; 2124 } port_id_t; 2125 #define INVALID_PORT_ID 0xFFFFFF 2126 2127 /* 2128 * Switch info gathering structure. 2129 */ 2130 typedef struct { 2131 port_id_t d_id; 2132 uint8_t node_name[WWN_SIZE]; 2133 uint8_t port_name[WWN_SIZE]; 2134 uint8_t fabric_port_name[WWN_SIZE]; 2135 uint16_t fp_speed; 2136 uint8_t fc4_type; 2137 } sw_info_t; 2138 2139 /* FCP-4 types */ 2140 #define FC4_TYPE_FCP_SCSI 0x08 2141 #define FC4_TYPE_OTHER 0x0 2142 #define FC4_TYPE_UNKNOWN 0xff 2143 2144 /* mailbox command 4G & above */ 2145 struct mbx_24xx_entry { 2146 uint8_t entry_type; 2147 uint8_t entry_count; 2148 uint8_t sys_define1; 2149 uint8_t entry_status; 2150 uint32_t handle; 2151 uint16_t mb[28]; 2152 }; 2153 2154 #define IOCB_SIZE 64 2155 2156 /* 2157 * Fibre channel port type. 2158 */ 2159 typedef enum { 2160 FCT_UNKNOWN, 2161 FCT_RSCN, 2162 FCT_SWITCH, 2163 FCT_BROADCAST, 2164 FCT_INITIATOR, 2165 FCT_TARGET 2166 } fc_port_type_t; 2167 2168 enum qla_sess_deletion { 2169 QLA_SESS_DELETION_NONE = 0, 2170 QLA_SESS_DELETION_IN_PROGRESS, 2171 QLA_SESS_DELETED, 2172 }; 2173 2174 enum qlt_plogi_link_t { 2175 QLT_PLOGI_LINK_SAME_WWN, 2176 QLT_PLOGI_LINK_CONFLICT, 2177 QLT_PLOGI_LINK_MAX 2178 }; 2179 2180 struct qlt_plogi_ack_t { 2181 struct list_head list; 2182 struct imm_ntfy_from_isp iocb; 2183 port_id_t id; 2184 int ref_count; 2185 void *fcport; 2186 }; 2187 2188 struct ct_sns_desc { 2189 struct ct_sns_pkt *ct_sns; 2190 dma_addr_t ct_sns_dma; 2191 }; 2192 2193 enum discovery_state { 2194 DSC_DELETED, 2195 DSC_GID_PN, 2196 DSC_GNL, 2197 DSC_LOGIN_PEND, 2198 DSC_LOGIN_FAILED, 2199 DSC_GPDB, 2200 DSC_GPSC, 2201 DSC_UPD_FCPORT, 2202 DSC_LOGIN_COMPLETE, 2203 DSC_DELETE_PEND, 2204 }; 2205 2206 enum login_state { /* FW control Target side */ 2207 DSC_LS_LLIOCB_SENT = 2, 2208 DSC_LS_PLOGI_PEND, 2209 DSC_LS_PLOGI_COMP, 2210 DSC_LS_PRLI_PEND, 2211 DSC_LS_PRLI_COMP, 2212 DSC_LS_PORT_UNAVAIL, 2213 DSC_LS_PRLO_PEND = 9, 2214 DSC_LS_LOGO_PEND, 2215 }; 2216 2217 enum fcport_mgt_event { 2218 FCME_RELOGIN = 1, 2219 FCME_RSCN, 2220 FCME_GIDPN_DONE, 2221 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */ 2222 FCME_GNL_DONE, 2223 FCME_GPSC_DONE, 2224 FCME_GPDB_DONE, 2225 FCME_GPNID_DONE, 2226 FCME_DELETE_DONE, 2227 }; 2228 2229 enum rscn_addr_format { 2230 RSCN_PORT_ADDR, 2231 RSCN_AREA_ADDR, 2232 RSCN_DOM_ADDR, 2233 RSCN_FAB_ADDR, 2234 }; 2235 2236 /* 2237 * Fibre channel port structure. 2238 */ 2239 typedef struct fc_port { 2240 struct list_head list; 2241 struct scsi_qla_host *vha; 2242 2243 uint8_t node_name[WWN_SIZE]; 2244 uint8_t port_name[WWN_SIZE]; 2245 port_id_t d_id; 2246 uint16_t loop_id; 2247 uint16_t old_loop_id; 2248 2249 unsigned int conf_compl_supported:1; 2250 unsigned int deleted:2; 2251 unsigned int local:1; 2252 unsigned int logout_on_delete:1; 2253 unsigned int logo_ack_needed:1; 2254 unsigned int keep_nport_handle:1; 2255 unsigned int send_els_logo:1; 2256 unsigned int login_pause:1; 2257 unsigned int login_succ:1; 2258 2259 struct fc_port *conflict; 2260 unsigned char logout_completed; 2261 int generation; 2262 2263 struct se_session *se_sess; 2264 struct kref sess_kref; 2265 struct qla_tgt *tgt; 2266 unsigned long expires; 2267 struct list_head del_list_entry; 2268 struct work_struct free_work; 2269 2270 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2271 2272 uint16_t tgt_id; 2273 uint16_t old_tgt_id; 2274 2275 uint8_t fcp_prio; 2276 2277 uint8_t fabric_port_name[WWN_SIZE]; 2278 uint16_t fp_speed; 2279 2280 fc_port_type_t port_type; 2281 2282 atomic_t state; 2283 uint32_t flags; 2284 2285 int login_retry; 2286 2287 struct fc_rport *rport, *drport; 2288 u32 supported_classes; 2289 2290 uint8_t fc4_type; 2291 uint8_t scan_state; 2292 2293 unsigned long last_queue_full; 2294 unsigned long last_ramp_up; 2295 2296 uint16_t port_id; 2297 2298 unsigned long retry_delay_timestamp; 2299 struct qla_tgt_sess *tgt_session; 2300 struct ct_sns_desc ct_desc; 2301 enum discovery_state disc_state; 2302 enum login_state fw_login_state; 2303 u32 login_gen, last_login_gen; 2304 u32 rscn_gen, last_rscn_gen; 2305 u32 chip_reset; 2306 struct list_head gnl_entry; 2307 struct work_struct del_work; 2308 u8 iocb[IOCB_SIZE]; 2309 } fc_port_t; 2310 2311 #define QLA_FCPORT_SCAN 1 2312 #define QLA_FCPORT_FOUND 2 2313 2314 struct event_arg { 2315 enum fcport_mgt_event event; 2316 fc_port_t *fcport; 2317 srb_t *sp; 2318 port_id_t id; 2319 u16 data[2], rc; 2320 u8 port_name[WWN_SIZE]; 2321 u32 iop[2]; 2322 }; 2323 2324 #include "qla_mr.h" 2325 2326 /* 2327 * Fibre channel port/lun states. 2328 */ 2329 #define FCS_UNCONFIGURED 1 2330 #define FCS_DEVICE_DEAD 2 2331 #define FCS_DEVICE_LOST 3 2332 #define FCS_ONLINE 4 2333 2334 static const char * const port_state_str[] = { 2335 "Unknown", 2336 "UNCONFIGURED", 2337 "DEAD", 2338 "LOST", 2339 "ONLINE" 2340 }; 2341 2342 /* 2343 * FC port flags. 2344 */ 2345 #define FCF_FABRIC_DEVICE BIT_0 2346 #define FCF_LOGIN_NEEDED BIT_1 2347 #define FCF_FCP2_DEVICE BIT_2 2348 #define FCF_ASYNC_SENT BIT_3 2349 #define FCF_CONF_COMP_SUPPORTED BIT_4 2350 2351 /* No loop ID flag. */ 2352 #define FC_NO_LOOP_ID 0x1000 2353 2354 /* 2355 * FC-CT interface 2356 * 2357 * NOTE: All structures are big-endian in form. 2358 */ 2359 2360 #define CT_REJECT_RESPONSE 0x8001 2361 #define CT_ACCEPT_RESPONSE 0x8002 2362 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2363 #define CT_REASON_CANNOT_PERFORM 0x09 2364 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2365 #define CT_EXPL_ALREADY_REGISTERED 0x10 2366 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2367 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2368 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2369 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2370 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2371 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2372 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2373 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2374 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2375 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2376 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2377 2378 #define NS_N_PORT_TYPE 0x01 2379 #define NS_NL_PORT_TYPE 0x02 2380 #define NS_NX_PORT_TYPE 0x7F 2381 2382 #define GA_NXT_CMD 0x100 2383 #define GA_NXT_REQ_SIZE (16 + 4) 2384 #define GA_NXT_RSP_SIZE (16 + 620) 2385 2386 #define GID_PT_CMD 0x1A1 2387 #define GID_PT_REQ_SIZE (16 + 4) 2388 2389 #define GPN_ID_CMD 0x112 2390 #define GPN_ID_REQ_SIZE (16 + 4) 2391 #define GPN_ID_RSP_SIZE (16 + 8) 2392 2393 #define GNN_ID_CMD 0x113 2394 #define GNN_ID_REQ_SIZE (16 + 4) 2395 #define GNN_ID_RSP_SIZE (16 + 8) 2396 2397 #define GFT_ID_CMD 0x117 2398 #define GFT_ID_REQ_SIZE (16 + 4) 2399 #define GFT_ID_RSP_SIZE (16 + 32) 2400 2401 #define GID_PN_CMD 0x121 2402 #define GID_PN_REQ_SIZE (16 + 8) 2403 #define GID_PN_RSP_SIZE (16 + 4) 2404 2405 #define RFT_ID_CMD 0x217 2406 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2407 #define RFT_ID_RSP_SIZE 16 2408 2409 #define RFF_ID_CMD 0x21F 2410 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2411 #define RFF_ID_RSP_SIZE 16 2412 2413 #define RNN_ID_CMD 0x213 2414 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2415 #define RNN_ID_RSP_SIZE 16 2416 2417 #define RSNN_NN_CMD 0x239 2418 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2419 #define RSNN_NN_RSP_SIZE 16 2420 2421 #define GFPN_ID_CMD 0x11C 2422 #define GFPN_ID_REQ_SIZE (16 + 4) 2423 #define GFPN_ID_RSP_SIZE (16 + 8) 2424 2425 #define GPSC_CMD 0x127 2426 #define GPSC_REQ_SIZE (16 + 8) 2427 #define GPSC_RSP_SIZE (16 + 2 + 2) 2428 2429 #define GFF_ID_CMD 0x011F 2430 #define GFF_ID_REQ_SIZE (16 + 4) 2431 #define GFF_ID_RSP_SIZE (16 + 128) 2432 2433 /* 2434 * HBA attribute types. 2435 */ 2436 #define FDMI_HBA_ATTR_COUNT 9 2437 #define FDMIV2_HBA_ATTR_COUNT 17 2438 #define FDMI_HBA_NODE_NAME 0x1 2439 #define FDMI_HBA_MANUFACTURER 0x2 2440 #define FDMI_HBA_SERIAL_NUMBER 0x3 2441 #define FDMI_HBA_MODEL 0x4 2442 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2443 #define FDMI_HBA_HARDWARE_VERSION 0x6 2444 #define FDMI_HBA_DRIVER_VERSION 0x7 2445 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2446 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2447 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2448 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2449 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2450 #define FDMI_HBA_VENDOR_ID 0xd 2451 #define FDMI_HBA_NUM_PORTS 0xe 2452 #define FDMI_HBA_FABRIC_NAME 0xf 2453 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2454 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0 2455 2456 struct ct_fdmi_hba_attr { 2457 uint16_t type; 2458 uint16_t len; 2459 union { 2460 uint8_t node_name[WWN_SIZE]; 2461 uint8_t manufacturer[64]; 2462 uint8_t serial_num[32]; 2463 uint8_t model[16+1]; 2464 uint8_t model_desc[80]; 2465 uint8_t hw_version[32]; 2466 uint8_t driver_version[32]; 2467 uint8_t orom_version[16]; 2468 uint8_t fw_version[32]; 2469 uint8_t os_version[128]; 2470 uint32_t max_ct_len; 2471 } a; 2472 }; 2473 2474 struct ct_fdmi_hba_attributes { 2475 uint32_t count; 2476 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2477 }; 2478 2479 struct ct_fdmiv2_hba_attr { 2480 uint16_t type; 2481 uint16_t len; 2482 union { 2483 uint8_t node_name[WWN_SIZE]; 2484 uint8_t manufacturer[64]; 2485 uint8_t serial_num[32]; 2486 uint8_t model[16+1]; 2487 uint8_t model_desc[80]; 2488 uint8_t hw_version[16]; 2489 uint8_t driver_version[32]; 2490 uint8_t orom_version[16]; 2491 uint8_t fw_version[32]; 2492 uint8_t os_version[128]; 2493 uint32_t max_ct_len; 2494 uint8_t sym_name[256]; 2495 uint32_t vendor_id; 2496 uint32_t num_ports; 2497 uint8_t fabric_name[WWN_SIZE]; 2498 uint8_t bios_name[32]; 2499 uint8_t vendor_identifier[8]; 2500 } a; 2501 }; 2502 2503 struct ct_fdmiv2_hba_attributes { 2504 uint32_t count; 2505 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT]; 2506 }; 2507 2508 /* 2509 * Port attribute types. 2510 */ 2511 #define FDMI_PORT_ATTR_COUNT 6 2512 #define FDMIV2_PORT_ATTR_COUNT 16 2513 #define FDMI_PORT_FC4_TYPES 0x1 2514 #define FDMI_PORT_SUPPORT_SPEED 0x2 2515 #define FDMI_PORT_CURRENT_SPEED 0x3 2516 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2517 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2518 #define FDMI_PORT_HOST_NAME 0x6 2519 #define FDMI_PORT_NODE_NAME 0x7 2520 #define FDMI_PORT_NAME 0x8 2521 #define FDMI_PORT_SYM_NAME 0x9 2522 #define FDMI_PORT_TYPE 0xa 2523 #define FDMI_PORT_SUPP_COS 0xb 2524 #define FDMI_PORT_FABRIC_NAME 0xc 2525 #define FDMI_PORT_FC4_TYPE 0xd 2526 #define FDMI_PORT_STATE 0x101 2527 #define FDMI_PORT_COUNT 0x102 2528 #define FDMI_PORT_ID 0x103 2529 2530 #define FDMI_PORT_SPEED_1GB 0x1 2531 #define FDMI_PORT_SPEED_2GB 0x2 2532 #define FDMI_PORT_SPEED_10GB 0x4 2533 #define FDMI_PORT_SPEED_4GB 0x8 2534 #define FDMI_PORT_SPEED_8GB 0x10 2535 #define FDMI_PORT_SPEED_16GB 0x20 2536 #define FDMI_PORT_SPEED_32GB 0x40 2537 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2538 2539 #define FC_CLASS_2 0x04 2540 #define FC_CLASS_3 0x08 2541 #define FC_CLASS_2_3 0x0C 2542 2543 struct ct_fdmiv2_port_attr { 2544 uint16_t type; 2545 uint16_t len; 2546 union { 2547 uint8_t fc4_types[32]; 2548 uint32_t sup_speed; 2549 uint32_t cur_speed; 2550 uint32_t max_frame_size; 2551 uint8_t os_dev_name[32]; 2552 uint8_t host_name[256]; 2553 uint8_t node_name[WWN_SIZE]; 2554 uint8_t port_name[WWN_SIZE]; 2555 uint8_t port_sym_name[128]; 2556 uint32_t port_type; 2557 uint32_t port_supported_cos; 2558 uint8_t fabric_name[WWN_SIZE]; 2559 uint8_t port_fc4_type[32]; 2560 uint32_t port_state; 2561 uint32_t num_ports; 2562 uint32_t port_id; 2563 } a; 2564 }; 2565 2566 /* 2567 * Port Attribute Block. 2568 */ 2569 struct ct_fdmiv2_port_attributes { 2570 uint32_t count; 2571 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT]; 2572 }; 2573 2574 struct ct_fdmi_port_attr { 2575 uint16_t type; 2576 uint16_t len; 2577 union { 2578 uint8_t fc4_types[32]; 2579 uint32_t sup_speed; 2580 uint32_t cur_speed; 2581 uint32_t max_frame_size; 2582 uint8_t os_dev_name[32]; 2583 uint8_t host_name[256]; 2584 } a; 2585 }; 2586 2587 struct ct_fdmi_port_attributes { 2588 uint32_t count; 2589 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2590 }; 2591 2592 /* FDMI definitions. */ 2593 #define GRHL_CMD 0x100 2594 #define GHAT_CMD 0x101 2595 #define GRPL_CMD 0x102 2596 #define GPAT_CMD 0x110 2597 2598 #define RHBA_CMD 0x200 2599 #define RHBA_RSP_SIZE 16 2600 2601 #define RHAT_CMD 0x201 2602 #define RPRT_CMD 0x210 2603 2604 #define RPA_CMD 0x211 2605 #define RPA_RSP_SIZE 16 2606 2607 #define DHBA_CMD 0x300 2608 #define DHBA_REQ_SIZE (16 + 8) 2609 #define DHBA_RSP_SIZE 16 2610 2611 #define DHAT_CMD 0x301 2612 #define DPRT_CMD 0x310 2613 #define DPA_CMD 0x311 2614 2615 /* CT command header -- request/response common fields */ 2616 struct ct_cmd_hdr { 2617 uint8_t revision; 2618 uint8_t in_id[3]; 2619 uint8_t gs_type; 2620 uint8_t gs_subtype; 2621 uint8_t options; 2622 uint8_t reserved; 2623 }; 2624 2625 /* CT command request */ 2626 struct ct_sns_req { 2627 struct ct_cmd_hdr header; 2628 uint16_t command; 2629 uint16_t max_rsp_size; 2630 uint8_t fragment_id; 2631 uint8_t reserved[3]; 2632 2633 union { 2634 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2635 struct { 2636 uint8_t reserved; 2637 uint8_t port_id[3]; 2638 } port_id; 2639 2640 struct { 2641 uint8_t port_type; 2642 uint8_t domain; 2643 uint8_t area; 2644 uint8_t reserved; 2645 } gid_pt; 2646 2647 struct { 2648 uint8_t reserved; 2649 uint8_t port_id[3]; 2650 uint8_t fc4_types[32]; 2651 } rft_id; 2652 2653 struct { 2654 uint8_t reserved; 2655 uint8_t port_id[3]; 2656 uint16_t reserved2; 2657 uint8_t fc4_feature; 2658 uint8_t fc4_type; 2659 } rff_id; 2660 2661 struct { 2662 uint8_t reserved; 2663 uint8_t port_id[3]; 2664 uint8_t node_name[8]; 2665 } rnn_id; 2666 2667 struct { 2668 uint8_t node_name[8]; 2669 uint8_t name_len; 2670 uint8_t sym_node_name[255]; 2671 } rsnn_nn; 2672 2673 struct { 2674 uint8_t hba_identifier[8]; 2675 } ghat; 2676 2677 struct { 2678 uint8_t hba_identifier[8]; 2679 uint32_t entry_count; 2680 uint8_t port_name[8]; 2681 struct ct_fdmi_hba_attributes attrs; 2682 } rhba; 2683 2684 struct { 2685 uint8_t hba_identifier[8]; 2686 uint32_t entry_count; 2687 uint8_t port_name[8]; 2688 struct ct_fdmiv2_hba_attributes attrs; 2689 } rhba2; 2690 2691 struct { 2692 uint8_t hba_identifier[8]; 2693 struct ct_fdmi_hba_attributes attrs; 2694 } rhat; 2695 2696 struct { 2697 uint8_t port_name[8]; 2698 struct ct_fdmi_port_attributes attrs; 2699 } rpa; 2700 2701 struct { 2702 uint8_t port_name[8]; 2703 struct ct_fdmiv2_port_attributes attrs; 2704 } rpa2; 2705 2706 struct { 2707 uint8_t port_name[8]; 2708 } dhba; 2709 2710 struct { 2711 uint8_t port_name[8]; 2712 } dhat; 2713 2714 struct { 2715 uint8_t port_name[8]; 2716 } dprt; 2717 2718 struct { 2719 uint8_t port_name[8]; 2720 } dpa; 2721 2722 struct { 2723 uint8_t port_name[8]; 2724 } gpsc; 2725 2726 struct { 2727 uint8_t reserved; 2728 uint8_t port_name[3]; 2729 } gff_id; 2730 2731 struct { 2732 uint8_t port_name[8]; 2733 } gid_pn; 2734 } req; 2735 }; 2736 2737 /* CT command response header */ 2738 struct ct_rsp_hdr { 2739 struct ct_cmd_hdr header; 2740 uint16_t response; 2741 uint16_t residual; 2742 uint8_t fragment_id; 2743 uint8_t reason_code; 2744 uint8_t explanation_code; 2745 uint8_t vendor_unique; 2746 }; 2747 2748 struct ct_sns_gid_pt_data { 2749 uint8_t control_byte; 2750 uint8_t port_id[3]; 2751 }; 2752 2753 struct ct_sns_rsp { 2754 struct ct_rsp_hdr header; 2755 2756 union { 2757 struct { 2758 uint8_t port_type; 2759 uint8_t port_id[3]; 2760 uint8_t port_name[8]; 2761 uint8_t sym_port_name_len; 2762 uint8_t sym_port_name[255]; 2763 uint8_t node_name[8]; 2764 uint8_t sym_node_name_len; 2765 uint8_t sym_node_name[255]; 2766 uint8_t init_proc_assoc[8]; 2767 uint8_t node_ip_addr[16]; 2768 uint8_t class_of_service[4]; 2769 uint8_t fc4_types[32]; 2770 uint8_t ip_address[16]; 2771 uint8_t fabric_port_name[8]; 2772 uint8_t reserved; 2773 uint8_t hard_address[3]; 2774 } ga_nxt; 2775 2776 struct { 2777 /* Assume the largest number of targets for the union */ 2778 struct ct_sns_gid_pt_data 2779 entries[MAX_FIBRE_DEVICES_MAX]; 2780 } gid_pt; 2781 2782 struct { 2783 uint8_t port_name[8]; 2784 } gpn_id; 2785 2786 struct { 2787 uint8_t node_name[8]; 2788 } gnn_id; 2789 2790 struct { 2791 uint8_t fc4_types[32]; 2792 } gft_id; 2793 2794 struct { 2795 uint32_t entry_count; 2796 uint8_t port_name[8]; 2797 struct ct_fdmi_hba_attributes attrs; 2798 } ghat; 2799 2800 struct { 2801 uint8_t port_name[8]; 2802 } gfpn_id; 2803 2804 struct { 2805 uint16_t speeds; 2806 uint16_t speed; 2807 } gpsc; 2808 2809 #define GFF_FCP_SCSI_OFFSET 7 2810 struct { 2811 uint8_t fc4_features[128]; 2812 } gff_id; 2813 struct { 2814 uint8_t reserved; 2815 uint8_t port_id[3]; 2816 } gid_pn; 2817 } rsp; 2818 }; 2819 2820 struct ct_sns_pkt { 2821 union { 2822 struct ct_sns_req req; 2823 struct ct_sns_rsp rsp; 2824 } p; 2825 }; 2826 2827 /* 2828 * SNS command structures -- for 2200 compatibility. 2829 */ 2830 #define RFT_ID_SNS_SCMD_LEN 22 2831 #define RFT_ID_SNS_CMD_SIZE 60 2832 #define RFT_ID_SNS_DATA_SIZE 16 2833 2834 #define RNN_ID_SNS_SCMD_LEN 10 2835 #define RNN_ID_SNS_CMD_SIZE 36 2836 #define RNN_ID_SNS_DATA_SIZE 16 2837 2838 #define GA_NXT_SNS_SCMD_LEN 6 2839 #define GA_NXT_SNS_CMD_SIZE 28 2840 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 2841 2842 #define GID_PT_SNS_SCMD_LEN 6 2843 #define GID_PT_SNS_CMD_SIZE 28 2844 /* 2845 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 2846 * adapters. 2847 */ 2848 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 2849 2850 #define GPN_ID_SNS_SCMD_LEN 6 2851 #define GPN_ID_SNS_CMD_SIZE 28 2852 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 2853 2854 #define GNN_ID_SNS_SCMD_LEN 6 2855 #define GNN_ID_SNS_CMD_SIZE 28 2856 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 2857 2858 struct sns_cmd_pkt { 2859 union { 2860 struct { 2861 uint16_t buffer_length; 2862 uint16_t reserved_1; 2863 uint32_t buffer_address[2]; 2864 uint16_t subcommand_length; 2865 uint16_t reserved_2; 2866 uint16_t subcommand; 2867 uint16_t size; 2868 uint32_t reserved_3; 2869 uint8_t param[36]; 2870 } cmd; 2871 2872 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 2873 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 2874 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 2875 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 2876 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 2877 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 2878 } p; 2879 }; 2880 2881 struct fw_blob { 2882 char *name; 2883 uint32_t segs[4]; 2884 const struct firmware *fw; 2885 }; 2886 2887 /* Return data from MBC_GET_ID_LIST call. */ 2888 struct gid_list_info { 2889 uint8_t al_pa; 2890 uint8_t area; 2891 uint8_t domain; 2892 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2893 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2894 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 2895 }; 2896 2897 /* NPIV */ 2898 typedef struct vport_info { 2899 uint8_t port_name[WWN_SIZE]; 2900 uint8_t node_name[WWN_SIZE]; 2901 int vp_id; 2902 uint16_t loop_id; 2903 unsigned long host_no; 2904 uint8_t port_id[3]; 2905 int loop_state; 2906 } vport_info_t; 2907 2908 typedef struct vport_params { 2909 uint8_t port_name[WWN_SIZE]; 2910 uint8_t node_name[WWN_SIZE]; 2911 uint32_t options; 2912 #define VP_OPTS_RETRY_ENABLE BIT_0 2913 #define VP_OPTS_VP_DISABLE BIT_1 2914 } vport_params_t; 2915 2916 /* NPIV - return codes of VP create and modify */ 2917 #define VP_RET_CODE_OK 0 2918 #define VP_RET_CODE_FATAL 1 2919 #define VP_RET_CODE_WRONG_ID 2 2920 #define VP_RET_CODE_WWPN 3 2921 #define VP_RET_CODE_RESOURCES 4 2922 #define VP_RET_CODE_NO_MEM 5 2923 #define VP_RET_CODE_NOT_FOUND 6 2924 2925 struct qla_hw_data; 2926 struct rsp_que; 2927 /* 2928 * ISP operations 2929 */ 2930 struct isp_operations { 2931 2932 int (*pci_config) (struct scsi_qla_host *); 2933 void (*reset_chip) (struct scsi_qla_host *); 2934 int (*chip_diag) (struct scsi_qla_host *); 2935 void (*config_rings) (struct scsi_qla_host *); 2936 void (*reset_adapter) (struct scsi_qla_host *); 2937 int (*nvram_config) (struct scsi_qla_host *); 2938 void (*update_fw_options) (struct scsi_qla_host *); 2939 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 2940 2941 char * (*pci_info_str) (struct scsi_qla_host *, char *); 2942 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 2943 2944 irq_handler_t intr_handler; 2945 void (*enable_intrs) (struct qla_hw_data *); 2946 void (*disable_intrs) (struct qla_hw_data *); 2947 2948 int (*abort_command) (srb_t *); 2949 int (*target_reset) (struct fc_port *, uint64_t, int); 2950 int (*lun_reset) (struct fc_port *, uint64_t, int); 2951 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 2952 uint8_t, uint8_t, uint16_t *, uint8_t); 2953 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 2954 uint8_t, uint8_t); 2955 2956 uint16_t (*calc_req_entries) (uint16_t); 2957 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 2958 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 2959 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 2960 uint32_t); 2961 2962 uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *, 2963 uint32_t, uint32_t); 2964 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 2965 uint32_t); 2966 2967 void (*fw_dump) (struct scsi_qla_host *, int); 2968 2969 int (*beacon_on) (struct scsi_qla_host *); 2970 int (*beacon_off) (struct scsi_qla_host *); 2971 void (*beacon_blink) (struct scsi_qla_host *); 2972 2973 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 2974 uint32_t, uint32_t); 2975 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 2976 uint32_t); 2977 2978 int (*get_flash_version) (struct scsi_qla_host *, void *); 2979 int (*start_scsi) (srb_t *); 2980 int (*start_scsi_mq) (srb_t *); 2981 int (*abort_isp) (struct scsi_qla_host *); 2982 int (*iospace_config)(struct qla_hw_data*); 2983 int (*initialize_adapter)(struct scsi_qla_host *); 2984 }; 2985 2986 /* MSI-X Support *************************************************************/ 2987 2988 #define QLA_MSIX_CHIP_REV_24XX 3 2989 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 2990 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 2991 2992 #define QLA_BASE_VECTORS 2 /* default + RSP */ 2993 #define QLA_MSIX_RSP_Q 0x01 2994 #define QLA_ATIO_VECTOR 0x02 2995 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 2996 2997 #define QLA_MIDX_DEFAULT 0 2998 #define QLA_MIDX_RSP_Q 1 2999 #define QLA_PCI_MSIX_CONTROL 0xa2 3000 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3001 3002 struct scsi_qla_host; 3003 3004 3005 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3006 3007 struct qla_msix_entry { 3008 int have_irq; 3009 int in_use; 3010 uint32_t vector; 3011 uint16_t entry; 3012 char name[30]; 3013 void *handle; 3014 int cpuid; 3015 }; 3016 3017 #define WATCH_INTERVAL 1 /* number of seconds */ 3018 3019 /* Work events. */ 3020 enum qla_work_type { 3021 QLA_EVT_AEN, 3022 QLA_EVT_IDC_ACK, 3023 QLA_EVT_ASYNC_LOGIN, 3024 QLA_EVT_ASYNC_LOGOUT, 3025 QLA_EVT_ASYNC_LOGOUT_DONE, 3026 QLA_EVT_ASYNC_ADISC, 3027 QLA_EVT_ASYNC_ADISC_DONE, 3028 QLA_EVT_UEVENT, 3029 QLA_EVT_AENFX, 3030 QLA_EVT_GIDPN, 3031 QLA_EVT_GPNID, 3032 QLA_EVT_GPNID_DONE, 3033 QLA_EVT_NEW_SESS, 3034 QLA_EVT_GPDB, 3035 QLA_EVT_GPSC, 3036 QLA_EVT_UPD_FCPORT, 3037 QLA_EVT_GNL, 3038 QLA_EVT_NACK, 3039 }; 3040 3041 3042 struct qla_work_evt { 3043 struct list_head list; 3044 enum qla_work_type type; 3045 u32 flags; 3046 #define QLA_EVT_FLAG_FREE 0x1 3047 3048 union { 3049 struct { 3050 enum fc_host_event_code code; 3051 u32 data; 3052 } aen; 3053 struct { 3054 #define QLA_IDC_ACK_REGS 7 3055 uint16_t mb[QLA_IDC_ACK_REGS]; 3056 } idc_ack; 3057 struct { 3058 struct fc_port *fcport; 3059 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3060 u16 data[2]; 3061 } logio; 3062 struct { 3063 u32 code; 3064 #define QLA_UEVENT_CODE_FW_DUMP 0 3065 } uevent; 3066 struct { 3067 uint32_t evtcode; 3068 uint32_t mbx[8]; 3069 uint32_t count; 3070 } aenfx; 3071 struct { 3072 srb_t *sp; 3073 } iosb; 3074 struct { 3075 port_id_t id; 3076 } gpnid; 3077 struct { 3078 port_id_t id; 3079 u8 port_name[8]; 3080 void *pla; 3081 } new_sess; 3082 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */ 3083 fc_port_t *fcport; 3084 u8 opt; 3085 } fcport; 3086 struct { 3087 fc_port_t *fcport; 3088 u8 iocb[IOCB_SIZE]; 3089 int type; 3090 } nack; 3091 } u; 3092 }; 3093 3094 struct qla_chip_state_84xx { 3095 struct list_head list; 3096 struct kref kref; 3097 3098 void *bus; 3099 spinlock_t access_lock; 3100 struct mutex fw_update_mutex; 3101 uint32_t fw_update; 3102 uint32_t op_fw_version; 3103 uint32_t op_fw_size; 3104 uint32_t op_fw_seq_size; 3105 uint32_t diag_fw_version; 3106 uint32_t gold_fw_version; 3107 }; 3108 3109 struct qla_statistics { 3110 uint32_t total_isp_aborts; 3111 uint64_t input_bytes; 3112 uint64_t output_bytes; 3113 uint64_t input_requests; 3114 uint64_t output_requests; 3115 uint32_t control_requests; 3116 3117 uint64_t jiffies_at_last_reset; 3118 uint32_t stat_max_pend_cmds; 3119 uint32_t stat_max_qfull_cmds_alloc; 3120 uint32_t stat_max_qfull_cmds_dropped; 3121 }; 3122 3123 struct bidi_statistics { 3124 unsigned long long io_count; 3125 unsigned long long transfer_bytes; 3126 }; 3127 3128 /* Multi queue support */ 3129 #define MBC_INITIALIZE_MULTIQ 0x1f 3130 #define QLA_QUE_PAGE 0X1000 3131 #define QLA_MQ_SIZE 32 3132 #define QLA_MAX_QUEUES 256 3133 #define ISP_QUE_REG(ha, id) \ 3134 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \ 3135 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3136 ((void __iomem *)ha->iobase)) 3137 #define QLA_REQ_QUE_ID(tag) \ 3138 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3139 #define QLA_DEFAULT_QUE_QOS 5 3140 #define QLA_PRECONFIG_VPORTS 32 3141 #define QLA_MAX_VPORTS_QLA24XX 128 3142 #define QLA_MAX_VPORTS_QLA25XX 256 3143 /* Response queue data structure */ 3144 struct rsp_que { 3145 dma_addr_t dma; 3146 response_t *ring; 3147 response_t *ring_ptr; 3148 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 3149 uint32_t __iomem *rsp_q_out; 3150 uint16_t ring_index; 3151 uint16_t out_ptr; 3152 uint16_t *in_ptr; /* queue shadow in index */ 3153 uint16_t length; 3154 uint16_t options; 3155 uint16_t rid; 3156 uint16_t id; 3157 uint16_t vp_idx; 3158 struct qla_hw_data *hw; 3159 struct qla_msix_entry *msix; 3160 struct req_que *req; 3161 srb_t *status_srb; /* status continuation entry */ 3162 3163 dma_addr_t dma_fx00; 3164 response_t *ring_fx00; 3165 uint16_t length_fx00; 3166 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3167 }; 3168 3169 /* Request queue data structure */ 3170 struct req_que { 3171 dma_addr_t dma; 3172 request_t *ring; 3173 request_t *ring_ptr; 3174 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 3175 uint32_t __iomem *req_q_out; 3176 uint16_t ring_index; 3177 uint16_t in_ptr; 3178 uint16_t *out_ptr; /* queue shadow out index */ 3179 uint16_t cnt; 3180 uint16_t length; 3181 uint16_t options; 3182 uint16_t rid; 3183 uint16_t id; 3184 uint16_t qos; 3185 uint16_t vp_idx; 3186 struct rsp_que *rsp; 3187 srb_t **outstanding_cmds; 3188 uint32_t current_outstanding_cmd; 3189 uint16_t num_outstanding_cmds; 3190 int max_q_depth; 3191 3192 dma_addr_t dma_fx00; 3193 request_t *ring_fx00; 3194 uint16_t length_fx00; 3195 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3196 }; 3197 3198 /*Queue pair data structure */ 3199 struct qla_qpair { 3200 spinlock_t qp_lock; 3201 atomic_t ref_count; 3202 /* distill these fields down to 'online=0/1' 3203 * ha->flags.eeh_busy 3204 * ha->flags.pci_channel_io_perm_failure 3205 * base_vha->loop_state 3206 */ 3207 uint32_t online:1; 3208 /* move vha->flags.difdix_supported here */ 3209 uint32_t difdix_supported:1; 3210 uint32_t delete_in_progress:1; 3211 3212 uint16_t id; /* qp number used with FW */ 3213 uint16_t num_active_cmd; /* cmds down at firmware */ 3214 cpumask_t cpu_mask; /* CPU mask for cpu affinity operation */ 3215 uint16_t vp_idx; /* vport ID */ 3216 3217 mempool_t *srb_mempool; 3218 3219 /* to do: New driver: move queues to here instead of pointers */ 3220 struct req_que *req; 3221 struct rsp_que *rsp; 3222 struct atio_que *atio; 3223 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3224 struct qla_hw_data *hw; 3225 struct work_struct q_work; 3226 struct list_head qp_list_elem; /* vha->qp_list */ 3227 struct scsi_qla_host *vha; 3228 }; 3229 3230 /* Place holder for FW buffer parameters */ 3231 struct qlfc_fw { 3232 void *fw_buf; 3233 dma_addr_t fw_dma; 3234 uint32_t len; 3235 }; 3236 3237 struct scsi_qlt_host { 3238 void *target_lport_ptr; 3239 struct mutex tgt_mutex; 3240 struct mutex tgt_host_action_mutex; 3241 struct qla_tgt *qla_tgt; 3242 }; 3243 3244 struct qlt_hw_data { 3245 /* Protected by hw lock */ 3246 uint32_t enable_class_2:1; 3247 uint32_t enable_explicit_conf:1; 3248 uint32_t node_name_set:1; 3249 3250 dma_addr_t atio_dma; /* Physical address. */ 3251 struct atio *atio_ring; /* Base virtual address */ 3252 struct atio *atio_ring_ptr; /* Current address. */ 3253 uint16_t atio_ring_index; /* Current index. */ 3254 uint16_t atio_q_length; 3255 uint32_t __iomem *atio_q_in; 3256 uint32_t __iomem *atio_q_out; 3257 3258 struct qla_tgt_func_tmpl *tgt_ops; 3259 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS]; 3260 uint16_t current_handle; 3261 3262 struct qla_tgt_vp_map *tgt_vp_map; 3263 3264 int saved_set; 3265 uint16_t saved_exchange_count; 3266 uint32_t saved_firmware_options_1; 3267 uint32_t saved_firmware_options_2; 3268 uint32_t saved_firmware_options_3; 3269 uint8_t saved_firmware_options[2]; 3270 uint8_t saved_add_firmware_options[2]; 3271 3272 uint8_t tgt_node_name[WWN_SIZE]; 3273 3274 struct dentry *dfs_tgt_sess; 3275 struct list_head q_full_list; 3276 uint32_t num_pend_cmds; 3277 uint32_t num_qfull_cmds_alloc; 3278 uint32_t num_qfull_cmds_dropped; 3279 spinlock_t q_full_lock; 3280 uint32_t leak_exchg_thresh_hold; 3281 spinlock_t sess_lock; 3282 int rspq_vector_cpuid; 3283 spinlock_t atio_lock ____cacheline_aligned; 3284 }; 3285 3286 #define MAX_QFULL_CMDS_ALLOC 8192 3287 #define Q_FULL_THRESH_HOLD_PERCENT 90 3288 #define Q_FULL_THRESH_HOLD(ha) \ 3289 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3290 3291 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3292 3293 /* 3294 * Qlogic host adapter specific data structure. 3295 */ 3296 struct qla_hw_data { 3297 struct pci_dev *pdev; 3298 /* SRB cache. */ 3299 #define SRB_MIN_REQ 128 3300 mempool_t *srb_mempool; 3301 3302 volatile struct { 3303 uint32_t mbox_int :1; 3304 uint32_t mbox_busy :1; 3305 uint32_t disable_risc_code_load :1; 3306 uint32_t enable_64bit_addressing :1; 3307 uint32_t enable_lip_reset :1; 3308 uint32_t enable_target_reset :1; 3309 uint32_t enable_lip_full_login :1; 3310 uint32_t enable_led_scheme :1; 3311 3312 uint32_t msi_enabled :1; 3313 uint32_t msix_enabled :1; 3314 uint32_t disable_serdes :1; 3315 uint32_t gpsc_supported :1; 3316 uint32_t npiv_supported :1; 3317 uint32_t pci_channel_io_perm_failure :1; 3318 uint32_t fce_enabled :1; 3319 uint32_t fac_supported :1; 3320 3321 uint32_t chip_reset_done :1; 3322 uint32_t running_gold_fw :1; 3323 uint32_t eeh_busy :1; 3324 uint32_t disable_msix_handshake :1; 3325 uint32_t fcp_prio_enabled :1; 3326 uint32_t isp82xx_fw_hung:1; 3327 uint32_t nic_core_hung:1; 3328 3329 uint32_t quiesce_owner:1; 3330 uint32_t nic_core_reset_hdlr_active:1; 3331 uint32_t nic_core_reset_owner:1; 3332 uint32_t isp82xx_no_md_cap:1; 3333 uint32_t host_shutting_down:1; 3334 uint32_t idc_compl_status:1; 3335 uint32_t mr_reset_hdlr_active:1; 3336 uint32_t mr_intr_valid:1; 3337 3338 uint32_t dport_enabled:1; 3339 uint32_t fawwpn_enabled:1; 3340 uint32_t exlogins_enabled:1; 3341 uint32_t exchoffld_enabled:1; 3342 /* 35 bits */ 3343 } flags; 3344 3345 /* This spinlock is used to protect "io transactions", you must 3346 * acquire it before doing any IO to the card, eg with RD_REG*() and 3347 * WRT_REG*() for the duration of your entire commandtransaction. 3348 * 3349 * This spinlock is of lower priority than the io request lock. 3350 */ 3351 3352 spinlock_t hardware_lock ____cacheline_aligned; 3353 int bars; 3354 int mem_only; 3355 device_reg_t *iobase; /* Base I/O address */ 3356 resource_size_t pio_address; 3357 3358 #define MIN_IOBASE_LEN 0x100 3359 dma_addr_t bar0_hdl; 3360 3361 void __iomem *cregbase; 3362 dma_addr_t bar2_hdl; 3363 #define BAR0_LEN_FX00 (1024 * 1024) 3364 #define BAR2_LEN_FX00 (128 * 1024) 3365 3366 uint32_t rqstq_intr_code; 3367 uint32_t mbx_intr_code; 3368 uint32_t req_que_len; 3369 uint32_t rsp_que_len; 3370 uint32_t req_que_off; 3371 uint32_t rsp_que_off; 3372 3373 /* Multi queue data structs */ 3374 device_reg_t *mqiobase; 3375 device_reg_t *msixbase; 3376 uint16_t msix_count; 3377 uint8_t mqenable; 3378 struct req_que **req_q_map; 3379 struct rsp_que **rsp_q_map; 3380 struct qla_qpair **queue_pair_map; 3381 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3382 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3383 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 3384 / sizeof(unsigned long)]; 3385 uint8_t max_req_queues; 3386 uint8_t max_rsp_queues; 3387 uint8_t max_qpairs; 3388 struct qla_qpair *base_qpair; 3389 struct qla_npiv_entry *npiv_info; 3390 uint16_t nvram_npiv_size; 3391 3392 uint16_t switch_cap; 3393 #define FLOGI_SEQ_DEL BIT_8 3394 #define FLOGI_MID_SUPPORT BIT_10 3395 #define FLOGI_VSAN_SUPPORT BIT_12 3396 #define FLOGI_SP_SUPPORT BIT_13 3397 3398 uint8_t port_no; /* Physical port of adapter */ 3399 uint8_t exch_starvation; 3400 3401 /* Timeout timers. */ 3402 uint8_t loop_down_abort_time; /* port down timer */ 3403 atomic_t loop_down_timer; /* loop down timer */ 3404 uint8_t link_down_timeout; /* link down timeout */ 3405 uint16_t max_loop_id; 3406 uint16_t max_fibre_devices; /* Maximum number of targets */ 3407 3408 uint16_t fb_rev; 3409 uint16_t min_external_loopid; /* First external loop Id */ 3410 3411 #define PORT_SPEED_UNKNOWN 0xFFFF 3412 #define PORT_SPEED_1GB 0x00 3413 #define PORT_SPEED_2GB 0x01 3414 #define PORT_SPEED_4GB 0x03 3415 #define PORT_SPEED_8GB 0x04 3416 #define PORT_SPEED_16GB 0x05 3417 #define PORT_SPEED_32GB 0x06 3418 #define PORT_SPEED_10GB 0x13 3419 uint16_t link_data_rate; /* F/W operating speed */ 3420 3421 uint8_t current_topology; 3422 uint8_t prev_topology; 3423 #define ISP_CFG_NL 1 3424 #define ISP_CFG_N 2 3425 #define ISP_CFG_FL 4 3426 #define ISP_CFG_F 8 3427 3428 uint8_t operating_mode; /* F/W operating mode */ 3429 #define LOOP 0 3430 #define P2P 1 3431 #define LOOP_P2P 2 3432 #define P2P_LOOP 3 3433 uint8_t interrupts_on; 3434 uint32_t isp_abort_cnt; 3435 3436 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 3437 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 3438 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 3439 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 3440 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 3441 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 3442 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 3443 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 3444 3445 uint32_t isp_type; 3446 #define DT_ISP2100 BIT_0 3447 #define DT_ISP2200 BIT_1 3448 #define DT_ISP2300 BIT_2 3449 #define DT_ISP2312 BIT_3 3450 #define DT_ISP2322 BIT_4 3451 #define DT_ISP6312 BIT_5 3452 #define DT_ISP6322 BIT_6 3453 #define DT_ISP2422 BIT_7 3454 #define DT_ISP2432 BIT_8 3455 #define DT_ISP5422 BIT_9 3456 #define DT_ISP5432 BIT_10 3457 #define DT_ISP2532 BIT_11 3458 #define DT_ISP8432 BIT_12 3459 #define DT_ISP8001 BIT_13 3460 #define DT_ISP8021 BIT_14 3461 #define DT_ISP2031 BIT_15 3462 #define DT_ISP8031 BIT_16 3463 #define DT_ISPFX00 BIT_17 3464 #define DT_ISP8044 BIT_18 3465 #define DT_ISP2071 BIT_19 3466 #define DT_ISP2271 BIT_20 3467 #define DT_ISP2261 BIT_21 3468 #define DT_ISP_LAST (DT_ISP2261 << 1) 3469 3470 uint32_t device_type; 3471 #define DT_T10_PI BIT_25 3472 #define DT_IIDMA BIT_26 3473 #define DT_FWI2 BIT_27 3474 #define DT_ZIO_SUPPORTED BIT_28 3475 #define DT_OEM_001 BIT_29 3476 #define DT_ISP2200A BIT_30 3477 #define DT_EXTENDED_IDS BIT_31 3478 3479 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 3480 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 3481 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 3482 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 3483 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 3484 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 3485 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 3486 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 3487 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 3488 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 3489 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 3490 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 3491 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 3492 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 3493 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 3494 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 3495 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 3496 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 3497 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 3498 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 3499 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 3500 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 3501 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 3502 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 3503 3504 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 3505 IS_QLA6312(ha) || IS_QLA6322(ha)) 3506 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 3507 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 3508 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 3509 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 3510 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 3511 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 3512 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 3513 IS_QLA84XX(ha)) 3514 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 3515 IS_QLA8031(ha) || IS_QLA8044(ha)) 3516 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 3517 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 3518 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 3519 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 3520 IS_QLA8044(ha) || IS_QLA27XX(ha)) 3521 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3522 IS_QLA27XX(ha)) 3523 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 3524 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3525 IS_QLA27XX(ha)) 3526 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3527 IS_QLA27XX(ha)) 3528 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 3529 3530 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 3531 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 3532 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 3533 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 3534 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 3535 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 3536 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 3537 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 3538 IS_QLA27XX(ha)) 3539 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) 3540 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 3541 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3542 ((ha)->fw_attributes_ext[0] & BIT_0)) 3543 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3544 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3545 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3546 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3547 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3548 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3549 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3550 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3551 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha)) 3552 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3553 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3554 3555 /* HBA serial number */ 3556 uint8_t serial0; 3557 uint8_t serial1; 3558 uint8_t serial2; 3559 3560 /* NVRAM configuration data */ 3561 #define MAX_NVRAM_SIZE 4096 3562 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 3563 uint16_t nvram_size; 3564 uint16_t nvram_base; 3565 void *nvram; 3566 uint16_t vpd_size; 3567 uint16_t vpd_base; 3568 void *vpd; 3569 3570 uint16_t loop_reset_delay; 3571 uint8_t retry_count; 3572 uint8_t login_timeout; 3573 uint16_t r_a_tov; 3574 int port_down_retry_count; 3575 uint8_t mbx_count; 3576 uint8_t aen_mbx_count; 3577 3578 uint32_t login_retry_count; 3579 /* SNS command interfaces. */ 3580 ms_iocb_entry_t *ms_iocb; 3581 dma_addr_t ms_iocb_dma; 3582 struct ct_sns_pkt *ct_sns; 3583 dma_addr_t ct_sns_dma; 3584 /* SNS command interfaces for 2200. */ 3585 struct sns_cmd_pkt *sns_cmd; 3586 dma_addr_t sns_cmd_dma; 3587 3588 #define SFP_DEV_SIZE 256 3589 #define SFP_BLOCK_SIZE 64 3590 void *sfp_data; 3591 dma_addr_t sfp_data_dma; 3592 3593 #define XGMAC_DATA_SIZE 4096 3594 void *xgmac_data; 3595 dma_addr_t xgmac_data_dma; 3596 3597 #define DCBX_TLV_DATA_SIZE 4096 3598 void *dcbx_tlv; 3599 dma_addr_t dcbx_tlv_dma; 3600 3601 struct task_struct *dpc_thread; 3602 uint8_t dpc_active; /* DPC routine is active */ 3603 3604 dma_addr_t gid_list_dma; 3605 struct gid_list_info *gid_list; 3606 int gid_list_info_size; 3607 3608 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3609 #define DMA_POOL_SIZE 256 3610 struct dma_pool *s_dma_pool; 3611 3612 dma_addr_t init_cb_dma; 3613 init_cb_t *init_cb; 3614 int init_cb_size; 3615 dma_addr_t ex_init_cb_dma; 3616 struct ex_init_cb_81xx *ex_init_cb; 3617 3618 void *async_pd; 3619 dma_addr_t async_pd_dma; 3620 3621 #define ENABLE_EXTENDED_LOGIN BIT_7 3622 3623 /* Extended Logins */ 3624 void *exlogin_buf; 3625 dma_addr_t exlogin_buf_dma; 3626 int exlogin_size; 3627 3628 #define ENABLE_EXCHANGE_OFFLD BIT_2 3629 3630 /* Exchange Offload */ 3631 void *exchoffld_buf; 3632 dma_addr_t exchoffld_buf_dma; 3633 int exchoffld_size; 3634 int exchoffld_count; 3635 3636 void *swl; 3637 3638 /* These are used by mailbox operations. */ 3639 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3640 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 3641 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 3642 3643 mbx_cmd_t *mcp; 3644 struct mbx_cmd_32 *mcp32; 3645 3646 unsigned long mbx_cmd_flags; 3647 #define MBX_INTERRUPT 1 3648 #define MBX_INTR_WAIT 2 3649 #define MBX_UPDATE_FLASH_ACTIVE 3 3650 3651 struct mutex vport_lock; /* Virtual port synchronization */ 3652 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 3653 struct mutex mq_lock; /* multi-queue synchronization */ 3654 struct completion mbx_cmd_comp; /* Serialize mbx access */ 3655 struct completion mbx_intr_comp; /* Used for completion notification */ 3656 struct completion dcbx_comp; /* For set port config notification */ 3657 struct completion lb_portup_comp; /* Used to wait for link up during 3658 * loopback */ 3659 #define DCBX_COMP_TIMEOUT 20 3660 #define LB_PORTUP_COMP_TIMEOUT 10 3661 3662 int notify_dcbx_comp; 3663 int notify_lb_portup_comp; 3664 struct mutex selflogin_lock; 3665 3666 /* Basic firmware related information. */ 3667 uint16_t fw_major_version; 3668 uint16_t fw_minor_version; 3669 uint16_t fw_subminor_version; 3670 uint16_t fw_attributes; 3671 uint16_t fw_attributes_h; 3672 uint16_t fw_attributes_ext[2]; 3673 uint32_t fw_memory_size; 3674 uint32_t fw_transfer_size; 3675 uint32_t fw_srisc_address; 3676 #define RISC_START_ADDRESS_2100 0x1000 3677 #define RISC_START_ADDRESS_2300 0x800 3678 #define RISC_START_ADDRESS_2400 0x100000 3679 3680 uint16_t orig_fw_tgt_xcb_count; 3681 uint16_t cur_fw_tgt_xcb_count; 3682 uint16_t orig_fw_xcb_count; 3683 uint16_t cur_fw_xcb_count; 3684 uint16_t orig_fw_iocb_count; 3685 uint16_t cur_fw_iocb_count; 3686 uint16_t fw_max_fcf_count; 3687 3688 uint32_t fw_shared_ram_start; 3689 uint32_t fw_shared_ram_end; 3690 uint32_t fw_ddr_ram_start; 3691 uint32_t fw_ddr_ram_end; 3692 3693 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 3694 uint8_t fw_seriallink_options[4]; 3695 uint16_t fw_seriallink_options24[4]; 3696 3697 uint8_t mpi_version[3]; 3698 uint32_t mpi_capabilities; 3699 uint8_t phy_version[3]; 3700 uint8_t pep_version[3]; 3701 3702 /* Firmware dump template */ 3703 void *fw_dump_template; 3704 uint32_t fw_dump_template_len; 3705 /* Firmware dump information. */ 3706 struct qla2xxx_fw_dump *fw_dump; 3707 uint32_t fw_dump_len; 3708 int fw_dumped; 3709 unsigned long fw_dump_cap_flags; 3710 #define RISC_PAUSE_CMPL 0 3711 #define DMA_SHUTDOWN_CMPL 1 3712 #define ISP_RESET_CMPL 2 3713 #define RISC_RDY_AFT_RESET 3 3714 #define RISC_SRAM_DUMP_CMPL 4 3715 #define RISC_EXT_MEM_DUMP_CMPL 5 3716 #define ISP_MBX_RDY 6 3717 #define ISP_SOFT_RESET_CMPL 7 3718 int fw_dump_reading; 3719 int prev_minidump_failed; 3720 dma_addr_t eft_dma; 3721 void *eft; 3722 /* Current size of mctp dump is 0x086064 bytes */ 3723 #define MCTP_DUMP_SIZE 0x086064 3724 dma_addr_t mctp_dump_dma; 3725 void *mctp_dump; 3726 int mctp_dumped; 3727 int mctp_dump_reading; 3728 uint32_t chain_offset; 3729 struct dentry *dfs_dir; 3730 struct dentry *dfs_fce; 3731 struct dentry *dfs_tgt_counters; 3732 struct dentry *dfs_fw_resource_cnt; 3733 3734 dma_addr_t fce_dma; 3735 void *fce; 3736 uint32_t fce_bufs; 3737 uint16_t fce_mb[8]; 3738 uint64_t fce_wr, fce_rd; 3739 struct mutex fce_mutex; 3740 3741 uint32_t pci_attr; 3742 uint16_t chip_revision; 3743 3744 uint16_t product_id[4]; 3745 3746 uint8_t model_number[16+1]; 3747 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 3748 char model_desc[80]; 3749 uint8_t adapter_id[16+1]; 3750 3751 /* Option ROM information. */ 3752 char *optrom_buffer; 3753 uint32_t optrom_size; 3754 int optrom_state; 3755 #define QLA_SWAITING 0 3756 #define QLA_SREADING 1 3757 #define QLA_SWRITING 2 3758 uint32_t optrom_region_start; 3759 uint32_t optrom_region_size; 3760 struct mutex optrom_mutex; 3761 3762 /* PCI expansion ROM image information. */ 3763 #define ROM_CODE_TYPE_BIOS 0 3764 #define ROM_CODE_TYPE_FCODE 1 3765 #define ROM_CODE_TYPE_EFI 3 3766 uint8_t bios_revision[2]; 3767 uint8_t efi_revision[2]; 3768 uint8_t fcode_revision[16]; 3769 uint32_t fw_revision[4]; 3770 3771 uint32_t gold_fw_version[4]; 3772 3773 /* Offsets for flash/nvram access (set to ~0 if not used). */ 3774 uint32_t flash_conf_off; 3775 uint32_t flash_data_off; 3776 uint32_t nvram_conf_off; 3777 uint32_t nvram_data_off; 3778 3779 uint32_t fdt_wrt_disable; 3780 uint32_t fdt_wrt_enable; 3781 uint32_t fdt_erase_cmd; 3782 uint32_t fdt_block_size; 3783 uint32_t fdt_unprotect_sec_cmd; 3784 uint32_t fdt_protect_sec_cmd; 3785 uint32_t fdt_wrt_sts_reg_cmd; 3786 3787 uint32_t flt_region_flt; 3788 uint32_t flt_region_fdt; 3789 uint32_t flt_region_boot; 3790 uint32_t flt_region_boot_sec; 3791 uint32_t flt_region_fw; 3792 uint32_t flt_region_fw_sec; 3793 uint32_t flt_region_vpd_nvram; 3794 uint32_t flt_region_vpd; 3795 uint32_t flt_region_vpd_sec; 3796 uint32_t flt_region_nvram; 3797 uint32_t flt_region_npiv_conf; 3798 uint32_t flt_region_gold_fw; 3799 uint32_t flt_region_fcp_prio; 3800 uint32_t flt_region_bootload; 3801 uint32_t flt_region_img_status_pri; 3802 uint32_t flt_region_img_status_sec; 3803 uint8_t active_image; 3804 3805 /* Needed for BEACON */ 3806 uint16_t beacon_blink_led; 3807 uint8_t beacon_color_state; 3808 #define QLA_LED_GRN_ON 0x01 3809 #define QLA_LED_YLW_ON 0x02 3810 #define QLA_LED_ABR_ON 0x04 3811 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 3812 /* ISP2322: red, green, amber. */ 3813 uint16_t zio_mode; 3814 uint16_t zio_timer; 3815 3816 struct qla_msix_entry *msix_entries; 3817 3818 struct list_head vp_list; /* list of VP */ 3819 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 3820 sizeof(unsigned long)]; 3821 uint16_t num_vhosts; /* number of vports created */ 3822 uint16_t num_vsans; /* number of vsan created */ 3823 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 3824 int cur_vport_count; 3825 3826 struct qla_chip_state_84xx *cs84xx; 3827 struct isp_operations *isp_ops; 3828 struct workqueue_struct *wq; 3829 struct qlfc_fw fw_buf; 3830 3831 /* FCP_CMND priority support */ 3832 struct qla_fcp_prio_cfg *fcp_prio_cfg; 3833 3834 struct dma_pool *dl_dma_pool; 3835 #define DSD_LIST_DMA_POOL_SIZE 512 3836 3837 struct dma_pool *fcp_cmnd_dma_pool; 3838 mempool_t *ctx_mempool; 3839 #define FCP_CMND_DMA_POOL_SIZE 512 3840 3841 void __iomem *nx_pcibase; /* Base I/O address */ 3842 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 3843 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 3844 3845 uint32_t crb_win; 3846 uint32_t curr_window; 3847 uint32_t ddr_mn_window; 3848 unsigned long mn_win_crb; 3849 unsigned long ms_win_crb; 3850 int qdr_sn_window; 3851 uint32_t fcoe_dev_init_timeout; 3852 uint32_t fcoe_reset_timeout; 3853 rwlock_t hw_lock; 3854 uint16_t portnum; /* port number */ 3855 int link_width; 3856 struct fw_blob *hablob; 3857 struct qla82xx_legacy_intr_set nx_legacy_intr; 3858 3859 uint16_t gbl_dsd_inuse; 3860 uint16_t gbl_dsd_avail; 3861 struct list_head gbl_dsd_list; 3862 #define NUM_DSD_CHAIN 4096 3863 3864 uint8_t fw_type; 3865 __le32 file_prd_off; /* File firmware product offset */ 3866 3867 uint32_t md_template_size; 3868 void *md_tmplt_hdr; 3869 dma_addr_t md_tmplt_hdr_dma; 3870 void *md_dump; 3871 uint32_t md_dump_size; 3872 3873 void *loop_id_map; 3874 3875 /* QLA83XX IDC specific fields */ 3876 uint32_t idc_audit_ts; 3877 uint32_t idc_extend_tmo; 3878 3879 /* DPC low-priority workqueue */ 3880 struct workqueue_struct *dpc_lp_wq; 3881 struct work_struct idc_aen; 3882 /* DPC high-priority workqueue */ 3883 struct workqueue_struct *dpc_hp_wq; 3884 struct work_struct nic_core_reset; 3885 struct work_struct idc_state_handler; 3886 struct work_struct nic_core_unrecoverable; 3887 struct work_struct board_disable; 3888 3889 struct mr_data_fx00 mr; 3890 uint32_t chip_reset; 3891 3892 struct qlt_hw_data tgt; 3893 int allow_cna_fw_dump; 3894 }; 3895 3896 struct qla_tgt_counters { 3897 uint64_t qla_core_sbt_cmd; 3898 uint64_t core_qla_que_buf; 3899 uint64_t qla_core_ret_ctio; 3900 uint64_t core_qla_snd_status; 3901 uint64_t qla_core_ret_sta_ctio; 3902 uint64_t core_qla_free_cmd; 3903 uint64_t num_q_full_sent; 3904 uint64_t num_alloc_iocb_failed; 3905 uint64_t num_term_xchg_sent; 3906 }; 3907 3908 /* 3909 * Qlogic scsi host structure 3910 */ 3911 typedef struct scsi_qla_host { 3912 struct list_head list; 3913 struct list_head vp_fcports; /* list of fcports */ 3914 struct list_head work_list; 3915 spinlock_t work_lock; 3916 3917 /* Commonly used flags and state information. */ 3918 struct Scsi_Host *host; 3919 unsigned long host_no; 3920 uint8_t host_str[16]; 3921 3922 volatile struct { 3923 uint32_t init_done :1; 3924 uint32_t online :1; 3925 uint32_t reset_active :1; 3926 3927 uint32_t management_server_logged_in :1; 3928 uint32_t process_response_queue :1; 3929 uint32_t difdix_supported:1; 3930 uint32_t delete_progress:1; 3931 3932 uint32_t fw_tgt_reported:1; 3933 uint32_t bbcr_enable:1; 3934 uint32_t qpairs_available:1; 3935 } flags; 3936 3937 atomic_t loop_state; 3938 #define LOOP_TIMEOUT 1 3939 #define LOOP_DOWN 2 3940 #define LOOP_UP 3 3941 #define LOOP_UPDATE 4 3942 #define LOOP_READY 5 3943 #define LOOP_DEAD 6 3944 3945 unsigned long dpc_flags; 3946 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 3947 #define RESET_ACTIVE 1 3948 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 3949 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 3950 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 3951 #define LOOP_RESYNC_ACTIVE 5 3952 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 3953 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 3954 #define RELOGIN_NEEDED 8 3955 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 3956 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 3957 #define BEACON_BLINK_NEEDED 11 3958 #define REGISTER_FDMI_NEEDED 12 3959 #define FCPORT_UPDATE_NEEDED 13 3960 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 3961 #define UNLOADING 15 3962 #define NPIV_CONFIG_NEEDED 16 3963 #define ISP_UNRECOVERABLE 17 3964 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 3965 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 3966 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 3967 #define FREE_BIT 21 3968 #define PORT_UPDATE_NEEDED 22 3969 #define FX00_RESET_RECOVERY 23 3970 #define FX00_TARGET_SCAN 24 3971 #define FX00_CRITEMP_RECOVERY 25 3972 #define FX00_HOST_INFO_RESEND 26 3973 #define QPAIR_ONLINE_CHECK_NEEDED 27 3974 3975 unsigned long pci_flags; 3976 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 3977 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 3978 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 3979 #define PCI_ERR 30 3980 3981 uint32_t device_flags; 3982 #define SWITCH_FOUND BIT_0 3983 #define DFLG_NO_CABLE BIT_1 3984 #define DFLG_DEV_FAILED BIT_5 3985 3986 /* ISP configuration data. */ 3987 uint16_t loop_id; /* Host adapter loop id */ 3988 uint16_t self_login_loop_id; /* host adapter loop id 3989 * get it on self login 3990 */ 3991 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 3992 * no need of allocating it for 3993 * each command 3994 */ 3995 3996 port_id_t d_id; /* Host adapter port id */ 3997 uint8_t marker_needed; 3998 uint16_t mgmt_svr_loop_id; 3999 4000 4001 4002 /* Timeout timers. */ 4003 uint8_t loop_down_abort_time; /* port down timer */ 4004 atomic_t loop_down_timer; /* loop down timer */ 4005 uint8_t link_down_timeout; /* link down timeout */ 4006 4007 uint32_t timer_active; 4008 struct timer_list timer; 4009 4010 uint8_t node_name[WWN_SIZE]; 4011 uint8_t port_name[WWN_SIZE]; 4012 uint8_t fabric_node_name[WWN_SIZE]; 4013 4014 uint16_t fcoe_vlan_id; 4015 uint16_t fcoe_fcf_idx; 4016 uint8_t fcoe_vn_port_mac[6]; 4017 4018 /* list of commands waiting on workqueue */ 4019 struct list_head qla_cmd_list; 4020 struct list_head qla_sess_op_cmd_list; 4021 struct list_head unknown_atio_list; 4022 spinlock_t cmd_list_lock; 4023 struct delayed_work unknown_atio_work; 4024 4025 /* Counter to detect races between ELS and RSCN events */ 4026 atomic_t generation_tick; 4027 /* Time when global fcport update has been scheduled */ 4028 int total_fcport_update_gen; 4029 /* List of pending LOGOs, protected by tgt_mutex */ 4030 struct list_head logo_list; 4031 /* List of pending PLOGI acks, protected by hw lock */ 4032 struct list_head plogi_ack_list; 4033 4034 struct list_head qp_list; 4035 4036 uint32_t vp_abort_cnt; 4037 4038 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4039 uint16_t vp_idx; /* vport ID */ 4040 struct qla_qpair *qpair; /* base qpair */ 4041 4042 unsigned long vp_flags; 4043 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4044 #define VP_CREATE_NEEDED 1 4045 #define VP_BIND_NEEDED 2 4046 #define VP_DELETE_NEEDED 3 4047 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4048 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4049 atomic_t vp_state; 4050 #define VP_OFFLINE 0 4051 #define VP_ACTIVE 1 4052 #define VP_FAILED 2 4053 // #define VP_DISABLE 3 4054 uint16_t vp_err_state; 4055 uint16_t vp_prev_err_state; 4056 #define VP_ERR_UNKWN 0 4057 #define VP_ERR_PORTDWN 1 4058 #define VP_ERR_FAB_UNSUPPORTED 2 4059 #define VP_ERR_FAB_NORESOURCES 3 4060 #define VP_ERR_FAB_LOGOUT 4 4061 #define VP_ERR_ADAP_NORESOURCES 5 4062 struct qla_hw_data *hw; 4063 struct scsi_qlt_host vha_tgt; 4064 struct req_que *req; 4065 int fw_heartbeat_counter; 4066 int seconds_since_last_heartbeat; 4067 struct fc_host_statistics fc_host_stat; 4068 struct qla_statistics qla_stats; 4069 struct bidi_statistics bidi_stats; 4070 4071 atomic_t vref_count; 4072 struct qla8044_reset_template reset_tmplt; 4073 struct qla_tgt_counters tgt_counters; 4074 uint16_t bbcr; 4075 struct name_list_extended gnl; 4076 /* Count of active session/fcport */ 4077 int fcport_count; 4078 wait_queue_head_t fcport_waitQ; 4079 } scsi_qla_host_t; 4080 4081 struct qla27xx_image_status { 4082 uint8_t image_status_mask; 4083 uint16_t generation_number; 4084 uint8_t reserved[3]; 4085 uint8_t ver_minor; 4086 uint8_t ver_major; 4087 uint32_t checksum; 4088 uint32_t signature; 4089 } __packed; 4090 4091 #define SET_VP_IDX 1 4092 #define SET_AL_PA 2 4093 #define RESET_VP_IDX 3 4094 #define RESET_AL_PA 4 4095 struct qla_tgt_vp_map { 4096 uint8_t idx; 4097 scsi_qla_host_t *vha; 4098 }; 4099 4100 struct qla2_sgx { 4101 dma_addr_t dma_addr; /* OUT */ 4102 uint32_t dma_len; /* OUT */ 4103 4104 uint32_t tot_bytes; /* IN */ 4105 struct scatterlist *cur_sg; /* IN */ 4106 4107 /* for book keeping, bzero on initial invocation */ 4108 uint32_t bytes_consumed; 4109 uint32_t num_bytes; 4110 uint32_t tot_partial; 4111 4112 /* for debugging */ 4113 uint32_t num_sg; 4114 srb_t *sp; 4115 }; 4116 4117 /* 4118 * Macros to help code, maintain, etc. 4119 */ 4120 #define LOOP_TRANSITION(ha) \ 4121 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4122 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 4123 atomic_read(&ha->loop_state) == LOOP_DOWN) 4124 4125 #define STATE_TRANSITION(ha) \ 4126 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 4127 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 4128 4129 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 4130 atomic_inc(&__vha->vref_count); \ 4131 mb(); \ 4132 if (__vha->flags.delete_progress) { \ 4133 atomic_dec(&__vha->vref_count); \ 4134 __bail = 1; \ 4135 } else { \ 4136 __bail = 0; \ 4137 } \ 4138 } while (0) 4139 4140 #define QLA_VHA_MARK_NOT_BUSY(__vha) \ 4141 atomic_dec(&__vha->vref_count); \ 4142 4143 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 4144 atomic_inc(&__qpair->ref_count); \ 4145 mb(); \ 4146 if (__qpair->delete_in_progress) { \ 4147 atomic_dec(&__qpair->ref_count); \ 4148 __bail = 1; \ 4149 } else { \ 4150 __bail = 0; \ 4151 } \ 4152 } while (0) 4153 4154 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 4155 atomic_dec(&__qpair->ref_count); \ 4156 4157 /* 4158 * qla2x00 local function return status codes 4159 */ 4160 #define MBS_MASK 0x3fff 4161 4162 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 4163 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 4164 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 4165 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 4166 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 4167 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 4168 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 4169 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 4170 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 4171 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 4172 4173 #define QLA_FUNCTION_TIMEOUT 0x100 4174 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 4175 #define QLA_FUNCTION_FAILED 0x102 4176 #define QLA_MEMORY_ALLOC_FAILED 0x103 4177 #define QLA_LOCK_TIMEOUT 0x104 4178 #define QLA_ABORTED 0x105 4179 #define QLA_SUSPENDED 0x106 4180 #define QLA_BUSY 0x107 4181 #define QLA_ALREADY_REGISTERED 0x109 4182 4183 #define NVRAM_DELAY() udelay(10) 4184 4185 /* 4186 * Flash support definitions 4187 */ 4188 #define OPTROM_SIZE_2300 0x20000 4189 #define OPTROM_SIZE_2322 0x100000 4190 #define OPTROM_SIZE_24XX 0x100000 4191 #define OPTROM_SIZE_25XX 0x200000 4192 #define OPTROM_SIZE_81XX 0x400000 4193 #define OPTROM_SIZE_82XX 0x800000 4194 #define OPTROM_SIZE_83XX 0x1000000 4195 4196 #define OPTROM_BURST_SIZE 0x1000 4197 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 4198 4199 #define QLA_DSDS_PER_IOCB 37 4200 4201 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 4202 4203 #define QLA_SG_ALL 1024 4204 4205 enum nexus_wait_type { 4206 WAIT_HOST = 0, 4207 WAIT_TARGET, 4208 WAIT_LUN, 4209 }; 4210 4211 #include "qla_gbl.h" 4212 #include "qla_dbg.h" 4213 #include "qla_inline.h" 4214 #endif 4215