1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #ifndef __QLA_DEF_H 7 #define __QLA_DEF_H 8 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/types.h> 12 #include <linux/module.h> 13 #include <linux/list.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/sched.h> 17 #include <linux/slab.h> 18 #include <linux/dmapool.h> 19 #include <linux/mempool.h> 20 #include <linux/spinlock.h> 21 #include <linux/completion.h> 22 #include <linux/interrupt.h> 23 #include <linux/workqueue.h> 24 #include <linux/firmware.h> 25 #include <linux/aer.h> 26 #include <linux/mutex.h> 27 #include <linux/btree.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 #include <scsi/scsi_bsg_fc.h> 35 36 #include <uapi/scsi/fc/fc_els.h> 37 38 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 39 typedef struct { 40 uint8_t domain; 41 uint8_t area; 42 uint8_t al_pa; 43 } be_id_t; 44 45 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 46 typedef struct { 47 uint8_t al_pa; 48 uint8_t area; 49 uint8_t domain; 50 } le_id_t; 51 52 /* 53 * 24 bit port ID type definition. 54 */ 55 typedef union { 56 uint32_t b24 : 24; 57 struct { 58 #ifdef __BIG_ENDIAN 59 uint8_t domain; 60 uint8_t area; 61 uint8_t al_pa; 62 #elif defined(__LITTLE_ENDIAN) 63 uint8_t al_pa; 64 uint8_t area; 65 uint8_t domain; 66 #else 67 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 68 #endif 69 uint8_t rsvd_1; 70 } b; 71 } port_id_t; 72 #define INVALID_PORT_ID 0xFFFFFF 73 74 #include "qla_bsg.h" 75 #include "qla_dsd.h" 76 #include "qla_nx.h" 77 #include "qla_nx2.h" 78 #include "qla_nvme.h" 79 #define QLA2XXX_DRIVER_NAME "qla2xxx" 80 #define QLA2XXX_APIDEV "ql2xapidev" 81 #define QLA2XXX_MANUFACTURER "Marvell Semiconductor, Inc." 82 83 /* 84 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 85 * but that's fine as we don't look at the last 24 ones for 86 * ISP2100 HBAs. 87 */ 88 #define MAILBOX_REGISTER_COUNT_2100 8 89 #define MAILBOX_REGISTER_COUNT_2200 24 90 #define MAILBOX_REGISTER_COUNT 32 91 92 #define QLA2200A_RISC_ROM_VER 4 93 #define FPM_2300 6 94 #define FPM_2310 7 95 96 #include "qla_settings.h" 97 98 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 99 100 /* 101 * Data bit definitions 102 */ 103 #define BIT_0 0x1 104 #define BIT_1 0x2 105 #define BIT_2 0x4 106 #define BIT_3 0x8 107 #define BIT_4 0x10 108 #define BIT_5 0x20 109 #define BIT_6 0x40 110 #define BIT_7 0x80 111 #define BIT_8 0x100 112 #define BIT_9 0x200 113 #define BIT_10 0x400 114 #define BIT_11 0x800 115 #define BIT_12 0x1000 116 #define BIT_13 0x2000 117 #define BIT_14 0x4000 118 #define BIT_15 0x8000 119 #define BIT_16 0x10000 120 #define BIT_17 0x20000 121 #define BIT_18 0x40000 122 #define BIT_19 0x80000 123 #define BIT_20 0x100000 124 #define BIT_21 0x200000 125 #define BIT_22 0x400000 126 #define BIT_23 0x800000 127 #define BIT_24 0x1000000 128 #define BIT_25 0x2000000 129 #define BIT_26 0x4000000 130 #define BIT_27 0x8000000 131 #define BIT_28 0x10000000 132 #define BIT_29 0x20000000 133 #define BIT_30 0x40000000 134 #define BIT_31 0x80000000 135 136 #define LSB(x) ((uint8_t)(x)) 137 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 138 139 #define LSW(x) ((uint16_t)(x)) 140 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 141 142 #define LSD(x) ((uint32_t)((uint64_t)(x))) 143 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 144 145 static inline uint32_t make_handle(uint16_t x, uint16_t y) 146 { 147 return ((uint32_t)x << 16) | y; 148 } 149 150 /* 151 * I/O register 152 */ 153 154 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr) 155 { 156 return readb(addr); 157 } 158 159 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr) 160 { 161 return readw(addr); 162 } 163 164 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr) 165 { 166 return readl(addr); 167 } 168 169 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr) 170 { 171 return readb_relaxed(addr); 172 } 173 174 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr) 175 { 176 return readw_relaxed(addr); 177 } 178 179 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr) 180 { 181 return readl_relaxed(addr); 182 } 183 184 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data) 185 { 186 return writeb(data, addr); 187 } 188 189 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data) 190 { 191 return writew(data, addr); 192 } 193 194 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data) 195 { 196 return writel(data, addr); 197 } 198 199 /* 200 * ISP83XX specific remote register addresses 201 */ 202 #define QLA83XX_LED_PORT0 0x00201320 203 #define QLA83XX_LED_PORT1 0x00201328 204 #define QLA83XX_IDC_DEV_STATE 0x22102384 205 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 206 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 207 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 208 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 209 #define QLA83XX_IDC_CONTROL 0x22102390 210 #define QLA83XX_IDC_AUDIT 0x22102394 211 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 212 #define QLA83XX_DRIVER_LOCKID 0x22102104 213 #define QLA83XX_DRIVER_LOCK 0x8111c028 214 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 215 #define QLA83XX_FLASH_LOCKID 0x22102100 216 #define QLA83XX_FLASH_LOCK 0x8111c010 217 #define QLA83XX_FLASH_UNLOCK 0x8111c014 218 #define QLA83XX_DEV_PARTINFO1 0x221023e0 219 #define QLA83XX_DEV_PARTINFO2 0x221023e4 220 #define QLA83XX_FW_HEARTBEAT 0x221020b0 221 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 222 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 223 224 /* 83XX: Macros defining 8200 AEN Reason codes */ 225 #define IDC_DEVICE_STATE_CHANGE BIT_0 226 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 227 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 228 #define IDC_HEARTBEAT_FAILURE BIT_3 229 230 /* 83XX: Macros defining 8200 AEN Error-levels */ 231 #define ERR_LEVEL_NON_FATAL 0x1 232 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 233 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 234 235 /* 83XX: Macros for IDC Version */ 236 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 237 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 238 239 /* 83XX: Macros for scheduling dpc tasks */ 240 #define QLA83XX_NIC_CORE_RESET 0x1 241 #define QLA83XX_IDC_STATE_HANDLER 0x2 242 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 243 244 /* 83XX: Macros for defining IDC-Control bits */ 245 #define QLA83XX_IDC_RESET_DISABLED BIT_0 246 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 247 248 /* 83XX: Macros for different timeouts */ 249 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 250 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 251 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 252 253 /* 83XX: Macros for defining class in DEV-Partition Info register */ 254 #define QLA83XX_CLASS_TYPE_NONE 0x0 255 #define QLA83XX_CLASS_TYPE_NIC 0x1 256 #define QLA83XX_CLASS_TYPE_FCOE 0x2 257 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 258 259 /* 83XX: Macros for IDC Lock-Recovery stages */ 260 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 261 * lock-recovery 262 */ 263 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 264 265 /* 83XX: Macros for IDC Audit type */ 266 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 267 * dev-state change to NEED-RESET 268 * or NEED-QUIESCENT 269 */ 270 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 271 * reset-recovery completion is 272 * second 273 */ 274 /* ISP2031: Values for laser on/off */ 275 #define PORT_0_2031 0x00201340 276 #define PORT_1_2031 0x00201350 277 #define LASER_ON_2031 0x01800100 278 #define LASER_OFF_2031 0x01800180 279 280 /* 281 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 282 * 133Mhz slot. 283 */ 284 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 285 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr)) 286 287 /* 288 * Fibre Channel device definitions. 289 */ 290 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 291 #define MAX_FIBRE_DEVICES_2100 512 292 #define MAX_FIBRE_DEVICES_2400 2048 293 #define MAX_FIBRE_DEVICES_LOOP 128 294 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 295 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 296 #define MAX_FIBRE_LUNS 0xFFFF 297 #define MAX_HOST_COUNT 16 298 299 /* 300 * Host adapter default definitions. 301 */ 302 #define MAX_BUSES 1 /* We only have one bus today */ 303 #define MIN_LUNS 8 304 #define MAX_LUNS MAX_FIBRE_LUNS 305 #define MAX_CMDS_PER_LUN 255 306 307 /* 308 * Fibre Channel device definitions. 309 */ 310 #define SNS_LAST_LOOP_ID_2100 0xfe 311 #define SNS_LAST_LOOP_ID_2300 0x7ff 312 313 #define LAST_LOCAL_LOOP_ID 0x7d 314 #define SNS_FL_PORT 0x7e 315 #define FABRIC_CONTROLLER 0x7f 316 #define SIMPLE_NAME_SERVER 0x80 317 #define SNS_FIRST_LOOP_ID 0x81 318 #define MANAGEMENT_SERVER 0xfe 319 #define BROADCAST 0xff 320 321 /* 322 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 323 * valid range of an N-PORT id is 0 through 0x7ef. 324 */ 325 #define NPH_LAST_HANDLE 0x7ee 326 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ 327 #define NPH_SNS 0x7fc /* FFFFFC */ 328 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 329 #define NPH_F_PORT 0x7fe /* FFFFFE */ 330 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 331 332 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 333 334 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 335 #include "qla_fw.h" 336 337 struct name_list_extended { 338 struct get_name_list_extended *l; 339 dma_addr_t ldma; 340 struct list_head fcports; 341 u32 size; 342 u8 sent; 343 }; 344 345 struct els_reject { 346 struct fc_els_ls_rjt *c; 347 dma_addr_t cdma; 348 u16 size; 349 }; 350 351 /* 352 * Timeout timer counts in seconds 353 */ 354 #define PORT_RETRY_TIME 1 355 #define LOOP_DOWN_TIMEOUT 60 356 #define LOOP_DOWN_TIME 255 /* 240 */ 357 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 358 359 #define DEFAULT_OUTSTANDING_COMMANDS 4096 360 #define MIN_OUTSTANDING_COMMANDS 128 361 362 /* ISP request and response entry counts (37-65535) */ 363 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 364 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 365 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 366 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 367 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 368 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 369 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 370 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 371 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 372 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 373 #define FW_DEF_EXCHANGES_CNT 2048 374 #define FW_MAX_EXCHANGES_CNT (32 * 1024) 375 #define REDUCE_EXCHANGES_CNT (8 * 1024) 376 377 #define SET_DID_STATUS(stat_var, status) (stat_var = status << 16) 378 379 struct req_que; 380 struct qla_tgt_sess; 381 382 /* 383 * SCSI Request Block 384 */ 385 struct srb_cmd { 386 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 387 uint32_t request_sense_length; 388 uint32_t fw_sense_length; 389 uint8_t *request_sense_ptr; 390 struct ct6_dsd *ct6_ctx; 391 struct crc_context *crc_ctx; 392 }; 393 394 /* 395 * SRB flag definitions 396 */ 397 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 398 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 399 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 400 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 401 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 402 #define SRB_WAKEUP_ON_COMP BIT_6 403 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */ 404 #define SRB_EDIF_CLEANUP_DELETE BIT_9 405 406 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 407 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 408 #define ISP_REG16_DISCONNECT 0xFFFF 409 410 static inline le_id_t be_id_to_le(be_id_t id) 411 { 412 le_id_t res; 413 414 res.domain = id.domain; 415 res.area = id.area; 416 res.al_pa = id.al_pa; 417 418 return res; 419 } 420 421 static inline be_id_t le_id_to_be(le_id_t id) 422 { 423 be_id_t res; 424 425 res.domain = id.domain; 426 res.area = id.area; 427 res.al_pa = id.al_pa; 428 429 return res; 430 } 431 432 static inline port_id_t be_to_port_id(be_id_t id) 433 { 434 port_id_t res; 435 436 res.b.domain = id.domain; 437 res.b.area = id.area; 438 res.b.al_pa = id.al_pa; 439 res.b.rsvd_1 = 0; 440 441 return res; 442 } 443 444 static inline be_id_t port_id_to_be_id(port_id_t port_id) 445 { 446 be_id_t res; 447 448 res.domain = port_id.b.domain; 449 res.area = port_id.b.area; 450 res.al_pa = port_id.b.al_pa; 451 452 return res; 453 } 454 455 struct els_logo_payload { 456 uint8_t opcode; 457 uint8_t rsvd[3]; 458 uint8_t s_id[3]; 459 uint8_t rsvd1[1]; 460 uint8_t wwpn[WWN_SIZE]; 461 }; 462 463 struct els_plogi_payload { 464 uint8_t opcode; 465 uint8_t rsvd[3]; 466 __be32 data[112 / 4]; 467 }; 468 469 struct ct_arg { 470 void *iocb; 471 u16 nport_handle; 472 dma_addr_t req_dma; 473 dma_addr_t rsp_dma; 474 u32 req_size; 475 u32 rsp_size; 476 u32 req_allocated_size; 477 u32 rsp_allocated_size; 478 void *req; 479 void *rsp; 480 port_id_t id; 481 }; 482 483 /* 484 * SRB extensions. 485 */ 486 struct srb_iocb { 487 union { 488 struct { 489 uint16_t flags; 490 #define SRB_LOGIN_RETRIED BIT_0 491 #define SRB_LOGIN_COND_PLOGI BIT_1 492 #define SRB_LOGIN_SKIP_PRLI BIT_2 493 #define SRB_LOGIN_NVME_PRLI BIT_3 494 #define SRB_LOGIN_PRLI_ONLY BIT_4 495 #define SRB_LOGIN_FCSP BIT_5 496 uint16_t data[2]; 497 u32 iop[2]; 498 } logio; 499 struct { 500 #define ELS_DCMD_TIMEOUT 20 501 #define ELS_DCMD_LOGO 0x5 502 uint32_t flags; 503 uint32_t els_cmd; 504 struct completion comp; 505 struct els_logo_payload *els_logo_pyld; 506 dma_addr_t els_logo_pyld_dma; 507 } els_logo; 508 struct els_plogi { 509 #define ELS_DCMD_PLOGI 0x3 510 uint32_t flags; 511 uint32_t els_cmd; 512 struct completion comp; 513 struct els_plogi_payload *els_plogi_pyld; 514 struct els_plogi_payload *els_resp_pyld; 515 u32 tx_size; 516 u32 rx_size; 517 dma_addr_t els_plogi_pyld_dma; 518 dma_addr_t els_resp_pyld_dma; 519 __le32 fw_status[3]; 520 __le16 comp_status; 521 __le16 len; 522 } els_plogi; 523 struct { 524 /* 525 * Values for flags field below are as 526 * defined in tsk_mgmt_entry struct 527 * for control_flags field in qla_fw.h. 528 */ 529 uint64_t lun; 530 uint32_t flags; 531 uint32_t data; 532 struct completion comp; 533 __le16 comp_status; 534 } tmf; 535 struct { 536 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 537 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 538 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 539 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 540 #define FXDISC_TIMEOUT 20 541 uint8_t flags; 542 uint32_t req_len; 543 uint32_t rsp_len; 544 void *req_addr; 545 void *rsp_addr; 546 dma_addr_t req_dma_handle; 547 dma_addr_t rsp_dma_handle; 548 __le32 adapter_id; 549 __le32 adapter_id_hi; 550 __le16 req_func_type; 551 __le32 req_data; 552 __le32 req_data_extra; 553 __le32 result; 554 __le32 seq_number; 555 __le16 fw_flags; 556 struct completion fxiocb_comp; 557 __le32 reserved_0; 558 uint8_t reserved_1; 559 } fxiocb; 560 struct { 561 uint32_t cmd_hndl; 562 __le16 comp_status; 563 __le16 req_que_no; 564 struct completion comp; 565 } abt; 566 struct ct_arg ctarg; 567 #define MAX_IOCB_MB_REG 28 568 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 569 struct { 570 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 571 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 572 void *out, *in; 573 dma_addr_t out_dma, in_dma; 574 struct completion comp; 575 int rc; 576 } mbx; 577 struct { 578 struct imm_ntfy_from_isp *ntfy; 579 } nack; 580 struct { 581 __le16 comp_status; 582 __le16 rsp_pyld_len; 583 uint8_t aen_op; 584 void *desc; 585 586 /* These are only used with ls4 requests */ 587 int cmd_len; 588 int rsp_len; 589 dma_addr_t cmd_dma; 590 dma_addr_t rsp_dma; 591 enum nvmefc_fcp_datadir dir; 592 uint32_t dl; 593 uint32_t timeout_sec; 594 struct list_head entry; 595 } nvme; 596 struct { 597 u16 cmd; 598 u16 vp_index; 599 } ctrlvp; 600 struct { 601 struct edif_sa_ctl *sa_ctl; 602 struct qla_sa_update_frame sa_frame; 603 } sa_update; 604 } u; 605 606 struct timer_list timer; 607 void (*timeout)(void *); 608 }; 609 610 /* Values for srb_ctx type */ 611 #define SRB_LOGIN_CMD 1 612 #define SRB_LOGOUT_CMD 2 613 #define SRB_ELS_CMD_RPT 3 614 #define SRB_ELS_CMD_HST 4 615 #define SRB_CT_CMD 5 616 #define SRB_ADISC_CMD 6 617 #define SRB_TM_CMD 7 618 #define SRB_SCSI_CMD 8 619 #define SRB_BIDI_CMD 9 620 #define SRB_FXIOCB_DCMD 10 621 #define SRB_FXIOCB_BCMD 11 622 #define SRB_ABT_CMD 12 623 #define SRB_ELS_DCMD 13 624 #define SRB_MB_IOCB 14 625 #define SRB_CT_PTHRU_CMD 15 626 #define SRB_NACK_PLOGI 16 627 #define SRB_NACK_PRLI 17 628 #define SRB_NACK_LOGO 18 629 #define SRB_NVME_CMD 19 630 #define SRB_NVME_LS 20 631 #define SRB_PRLI_CMD 21 632 #define SRB_CTRL_VP 22 633 #define SRB_PRLO_CMD 23 634 #define SRB_SA_UPDATE 25 635 #define SRB_ELS_CMD_HST_NOLOGIN 26 636 #define SRB_SA_REPLACE 27 637 638 struct qla_els_pt_arg { 639 u8 els_opcode; 640 u8 vp_idx; 641 __le16 nport_handle; 642 u16 control_flags, ox_id; 643 __le32 rx_xchg_address; 644 port_id_t did, sid; 645 u32 tx_len, tx_byte_count, rx_len, rx_byte_count; 646 dma_addr_t tx_addr, rx_addr; 647 648 }; 649 650 enum { 651 TYPE_SRB, 652 TYPE_TGT_CMD, 653 TYPE_TGT_TMCMD, /* task management */ 654 }; 655 656 struct iocb_resource { 657 u8 res_type; 658 u8 pad; 659 u16 iocb_cnt; 660 }; 661 662 struct bsg_cmd { 663 struct bsg_job *bsg_job; 664 union { 665 struct qla_els_pt_arg els_arg; 666 } u; 667 }; 668 669 typedef struct srb { 670 /* 671 * Do not move cmd_type field, it needs to 672 * line up with qla_tgt_cmd->cmd_type 673 */ 674 uint8_t cmd_type; 675 uint8_t pad[3]; 676 struct iocb_resource iores; 677 struct kref cmd_kref; /* need to migrate ref_count over to this */ 678 void *priv; 679 wait_queue_head_t nvme_ls_waitq; 680 struct fc_port *fcport; 681 struct scsi_qla_host *vha; 682 unsigned int start_timer:1; 683 684 uint32_t handle; 685 uint16_t flags; 686 uint16_t type; 687 const char *name; 688 int iocbs; 689 struct qla_qpair *qpair; 690 struct srb *cmd_sp; 691 struct list_head elem; 692 u32 gen1; /* scratch */ 693 u32 gen2; /* scratch */ 694 int rc; 695 int retry_count; 696 struct completion *comp; 697 union { 698 struct srb_iocb iocb_cmd; 699 struct bsg_job *bsg_job; 700 struct srb_cmd scmd; 701 struct bsg_cmd bsg_cmd; 702 } u; 703 struct { 704 bool remapped; 705 struct { 706 dma_addr_t dma; 707 void *buf; 708 uint len; 709 } req; 710 struct { 711 dma_addr_t dma; 712 void *buf; 713 uint len; 714 } rsp; 715 } remap; 716 /* 717 * Report completion status @res and call sp_put(@sp). @res is 718 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a 719 * QLA_* status value. 720 */ 721 void (*done)(struct srb *sp, int res); 722 /* Stop the timer and free @sp. Only used by the FCP code. */ 723 void (*free)(struct srb *sp); 724 /* 725 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe 726 * code. 727 */ 728 void (*put_fn)(struct kref *kref); 729 730 /* 731 * Report completion for asynchronous commands. 732 */ 733 void (*async_done)(struct srb *sp, int res); 734 } srb_t; 735 736 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 737 738 #define GET_CMD_SENSE_LEN(sp) \ 739 (sp->u.scmd.request_sense_length) 740 #define SET_CMD_SENSE_LEN(sp, len) \ 741 (sp->u.scmd.request_sense_length = len) 742 #define GET_CMD_SENSE_PTR(sp) \ 743 (sp->u.scmd.request_sense_ptr) 744 #define SET_CMD_SENSE_PTR(sp, ptr) \ 745 (sp->u.scmd.request_sense_ptr = ptr) 746 #define GET_FW_SENSE_LEN(sp) \ 747 (sp->u.scmd.fw_sense_length) 748 #define SET_FW_SENSE_LEN(sp, len) \ 749 (sp->u.scmd.fw_sense_length = len) 750 751 struct msg_echo_lb { 752 dma_addr_t send_dma; 753 dma_addr_t rcv_dma; 754 uint16_t req_sg_cnt; 755 uint16_t rsp_sg_cnt; 756 uint16_t options; 757 uint32_t transfer_size; 758 uint32_t iteration_count; 759 }; 760 761 /* 762 * ISP I/O Register Set structure definitions. 763 */ 764 struct device_reg_2xxx { 765 __le16 flash_address; /* Flash BIOS address */ 766 __le16 flash_data; /* Flash BIOS data */ 767 __le16 unused_1[1]; /* Gap */ 768 __le16 ctrl_status; /* Control/Status */ 769 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 770 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 771 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 772 773 __le16 ictrl; /* Interrupt control */ 774 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 775 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 776 777 __le16 istatus; /* Interrupt status */ 778 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 779 780 __le16 semaphore; /* Semaphore */ 781 __le16 nvram; /* NVRAM register. */ 782 #define NVR_DESELECT 0 783 #define NVR_BUSY BIT_15 784 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 785 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 786 #define NVR_DATA_IN BIT_3 787 #define NVR_DATA_OUT BIT_2 788 #define NVR_SELECT BIT_1 789 #define NVR_CLOCK BIT_0 790 791 #define NVR_WAIT_CNT 20000 792 793 union { 794 struct { 795 __le16 mailbox0; 796 __le16 mailbox1; 797 __le16 mailbox2; 798 __le16 mailbox3; 799 __le16 mailbox4; 800 __le16 mailbox5; 801 __le16 mailbox6; 802 __le16 mailbox7; 803 __le16 unused_2[59]; /* Gap */ 804 } __attribute__((packed)) isp2100; 805 struct { 806 /* Request Queue */ 807 __le16 req_q_in; /* In-Pointer */ 808 __le16 req_q_out; /* Out-Pointer */ 809 /* Response Queue */ 810 __le16 rsp_q_in; /* In-Pointer */ 811 __le16 rsp_q_out; /* Out-Pointer */ 812 813 /* RISC to Host Status */ 814 __le32 host_status; 815 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 816 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 817 818 /* Host to Host Semaphore */ 819 __le16 host_semaphore; 820 __le16 unused_3[17]; /* Gap */ 821 __le16 mailbox0; 822 __le16 mailbox1; 823 __le16 mailbox2; 824 __le16 mailbox3; 825 __le16 mailbox4; 826 __le16 mailbox5; 827 __le16 mailbox6; 828 __le16 mailbox7; 829 __le16 mailbox8; 830 __le16 mailbox9; 831 __le16 mailbox10; 832 __le16 mailbox11; 833 __le16 mailbox12; 834 __le16 mailbox13; 835 __le16 mailbox14; 836 __le16 mailbox15; 837 __le16 mailbox16; 838 __le16 mailbox17; 839 __le16 mailbox18; 840 __le16 mailbox19; 841 __le16 mailbox20; 842 __le16 mailbox21; 843 __le16 mailbox22; 844 __le16 mailbox23; 845 __le16 mailbox24; 846 __le16 mailbox25; 847 __le16 mailbox26; 848 __le16 mailbox27; 849 __le16 mailbox28; 850 __le16 mailbox29; 851 __le16 mailbox30; 852 __le16 mailbox31; 853 __le16 fb_cmd; 854 __le16 unused_4[10]; /* Gap */ 855 } __attribute__((packed)) isp2300; 856 } u; 857 858 __le16 fpm_diag_config; 859 __le16 unused_5[0x4]; /* Gap */ 860 __le16 risc_hw; 861 __le16 unused_5_1; /* Gap */ 862 __le16 pcr; /* Processor Control Register. */ 863 __le16 unused_6[0x5]; /* Gap */ 864 __le16 mctr; /* Memory Configuration and Timing. */ 865 __le16 unused_7[0x3]; /* Gap */ 866 __le16 fb_cmd_2100; /* Unused on 23XX */ 867 __le16 unused_8[0x3]; /* Gap */ 868 __le16 hccr; /* Host command & control register. */ 869 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 870 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 871 /* HCCR commands */ 872 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 873 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 874 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 875 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 876 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 877 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 878 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 879 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 880 881 __le16 unused_9[5]; /* Gap */ 882 __le16 gpiod; /* GPIO Data register. */ 883 __le16 gpioe; /* GPIO Enable register. */ 884 #define GPIO_LED_MASK 0x00C0 885 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 886 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 887 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 888 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 889 #define GPIO_LED_ALL_OFF 0x0000 890 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 891 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 892 893 union { 894 struct { 895 __le16 unused_10[8]; /* Gap */ 896 __le16 mailbox8; 897 __le16 mailbox9; 898 __le16 mailbox10; 899 __le16 mailbox11; 900 __le16 mailbox12; 901 __le16 mailbox13; 902 __le16 mailbox14; 903 __le16 mailbox15; 904 __le16 mailbox16; 905 __le16 mailbox17; 906 __le16 mailbox18; 907 __le16 mailbox19; 908 __le16 mailbox20; 909 __le16 mailbox21; 910 __le16 mailbox22; 911 __le16 mailbox23; /* Also probe reg. */ 912 } __attribute__((packed)) isp2200; 913 } u_end; 914 }; 915 916 struct device_reg_25xxmq { 917 __le32 req_q_in; 918 __le32 req_q_out; 919 __le32 rsp_q_in; 920 __le32 rsp_q_out; 921 __le32 atio_q_in; 922 __le32 atio_q_out; 923 }; 924 925 926 struct device_reg_fx00 { 927 __le32 mailbox0; /* 00 */ 928 __le32 mailbox1; /* 04 */ 929 __le32 mailbox2; /* 08 */ 930 __le32 mailbox3; /* 0C */ 931 __le32 mailbox4; /* 10 */ 932 __le32 mailbox5; /* 14 */ 933 __le32 mailbox6; /* 18 */ 934 __le32 mailbox7; /* 1C */ 935 __le32 mailbox8; /* 20 */ 936 __le32 mailbox9; /* 24 */ 937 __le32 mailbox10; /* 28 */ 938 __le32 mailbox11; 939 __le32 mailbox12; 940 __le32 mailbox13; 941 __le32 mailbox14; 942 __le32 mailbox15; 943 __le32 mailbox16; 944 __le32 mailbox17; 945 __le32 mailbox18; 946 __le32 mailbox19; 947 __le32 mailbox20; 948 __le32 mailbox21; 949 __le32 mailbox22; 950 __le32 mailbox23; 951 __le32 mailbox24; 952 __le32 mailbox25; 953 __le32 mailbox26; 954 __le32 mailbox27; 955 __le32 mailbox28; 956 __le32 mailbox29; 957 __le32 mailbox30; 958 __le32 mailbox31; 959 __le32 aenmailbox0; 960 __le32 aenmailbox1; 961 __le32 aenmailbox2; 962 __le32 aenmailbox3; 963 __le32 aenmailbox4; 964 __le32 aenmailbox5; 965 __le32 aenmailbox6; 966 __le32 aenmailbox7; 967 /* Request Queue. */ 968 __le32 req_q_in; /* A0 - Request Queue In-Pointer */ 969 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */ 970 /* Response Queue. */ 971 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */ 972 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */ 973 /* Init values shadowed on FW Up Event */ 974 __le32 initval0; /* B0 */ 975 __le32 initval1; /* B4 */ 976 __le32 initval2; /* B8 */ 977 __le32 initval3; /* BC */ 978 __le32 initval4; /* C0 */ 979 __le32 initval5; /* C4 */ 980 __le32 initval6; /* C8 */ 981 __le32 initval7; /* CC */ 982 __le32 fwheartbeat; /* D0 */ 983 __le32 pseudoaen; /* D4 */ 984 }; 985 986 987 988 typedef union { 989 struct device_reg_2xxx isp; 990 struct device_reg_24xx isp24; 991 struct device_reg_25xxmq isp25mq; 992 struct device_reg_82xx isp82; 993 struct device_reg_fx00 ispfx00; 994 } __iomem device_reg_t; 995 996 #define ISP_REQ_Q_IN(ha, reg) \ 997 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 998 &(reg)->u.isp2100.mailbox4 : \ 999 &(reg)->u.isp2300.req_q_in) 1000 #define ISP_REQ_Q_OUT(ha, reg) \ 1001 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1002 &(reg)->u.isp2100.mailbox4 : \ 1003 &(reg)->u.isp2300.req_q_out) 1004 #define ISP_RSP_Q_IN(ha, reg) \ 1005 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1006 &(reg)->u.isp2100.mailbox5 : \ 1007 &(reg)->u.isp2300.rsp_q_in) 1008 #define ISP_RSP_Q_OUT(ha, reg) \ 1009 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1010 &(reg)->u.isp2100.mailbox5 : \ 1011 &(reg)->u.isp2300.rsp_q_out) 1012 1013 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 1014 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 1015 1016 #define MAILBOX_REG(ha, reg, num) \ 1017 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1018 (num < 8 ? \ 1019 &(reg)->u.isp2100.mailbox0 + (num) : \ 1020 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 1021 &(reg)->u.isp2300.mailbox0 + (num)) 1022 #define RD_MAILBOX_REG(ha, reg, num) \ 1023 rd_reg_word(MAILBOX_REG(ha, reg, num)) 1024 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 1025 wrt_reg_word(MAILBOX_REG(ha, reg, num), data) 1026 1027 #define FB_CMD_REG(ha, reg) \ 1028 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1029 &(reg)->fb_cmd_2100 : \ 1030 &(reg)->u.isp2300.fb_cmd) 1031 #define RD_FB_CMD_REG(ha, reg) \ 1032 rd_reg_word(FB_CMD_REG(ha, reg)) 1033 #define WRT_FB_CMD_REG(ha, reg, data) \ 1034 wrt_reg_word(FB_CMD_REG(ha, reg), data) 1035 1036 typedef struct { 1037 uint32_t out_mb; /* outbound from driver */ 1038 uint32_t in_mb; /* Incoming from RISC */ 1039 uint16_t mb[MAILBOX_REGISTER_COUNT]; 1040 long buf_size; 1041 void *bufp; 1042 uint32_t tov; 1043 uint8_t flags; 1044 #define MBX_DMA_IN BIT_0 1045 #define MBX_DMA_OUT BIT_1 1046 #define IOCTL_CMD BIT_2 1047 } mbx_cmd_t; 1048 1049 struct mbx_cmd_32 { 1050 uint32_t out_mb; /* outbound from driver */ 1051 uint32_t in_mb; /* Incoming from RISC */ 1052 uint32_t mb[MAILBOX_REGISTER_COUNT]; 1053 long buf_size; 1054 void *bufp; 1055 uint32_t tov; 1056 uint8_t flags; 1057 #define MBX_DMA_IN BIT_0 1058 #define MBX_DMA_OUT BIT_1 1059 #define IOCTL_CMD BIT_2 1060 }; 1061 1062 1063 #define MBX_TOV_SECONDS 30 1064 1065 /* 1066 * ISP product identification definitions in mailboxes after reset. 1067 */ 1068 #define PROD_ID_1 0x4953 1069 #define PROD_ID_2 0x0000 1070 #define PROD_ID_2a 0x5020 1071 #define PROD_ID_3 0x2020 1072 1073 /* 1074 * ISP mailbox Self-Test status codes 1075 */ 1076 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 1077 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 1078 #define MBS_BUSY 4 /* Busy. */ 1079 1080 /* 1081 * ISP mailbox command complete status codes 1082 */ 1083 #define MBS_COMMAND_COMPLETE 0x4000 1084 #define MBS_INVALID_COMMAND 0x4001 1085 #define MBS_HOST_INTERFACE_ERROR 0x4002 1086 #define MBS_TEST_FAILED 0x4003 1087 #define MBS_COMMAND_ERROR 0x4005 1088 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 1089 #define MBS_PORT_ID_USED 0x4007 1090 #define MBS_LOOP_ID_USED 0x4008 1091 #define MBS_ALL_IDS_IN_USE 0x4009 1092 #define MBS_NOT_LOGGED_IN 0x400A 1093 #define MBS_LINK_DOWN_ERROR 0x400B 1094 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 1095 1096 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs) 1097 { 1098 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR; 1099 } 1100 1101 /* 1102 * ISP mailbox asynchronous event status codes 1103 */ 1104 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 1105 #define MBA_RESET 0x8001 /* Reset Detected. */ 1106 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 1107 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 1108 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 1109 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 1110 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 1111 /* occurred. */ 1112 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 1113 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 1114 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 1115 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 1116 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 1117 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 1118 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 1119 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 1120 #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */ 1121 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 1122 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 1123 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 1124 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 1125 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 1126 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 1127 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 1128 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 1129 /* used. */ 1130 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 1131 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 1132 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 1133 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 1134 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 1135 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 1136 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 1137 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 1138 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 1139 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 1140 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 1141 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 1142 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 1143 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 1144 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 1145 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 1146 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 1147 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 1148 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 1149 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 1150 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 1151 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 1152 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */ 1153 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 1154 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 1155 Notification */ 1156 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 1157 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 1158 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 1159 /* 83XX FCoE specific */ 1160 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 1161 1162 /* Interrupt type codes */ 1163 #define INTR_ROM_MB_SUCCESS 0x1 1164 #define INTR_ROM_MB_FAILED 0x2 1165 #define INTR_MB_SUCCESS 0x10 1166 #define INTR_MB_FAILED 0x11 1167 #define INTR_ASYNC_EVENT 0x12 1168 #define INTR_RSP_QUE_UPDATE 0x13 1169 #define INTR_RSP_QUE_UPDATE_83XX 0x14 1170 #define INTR_ATIO_QUE_UPDATE 0x1C 1171 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 1172 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 1173 1174 /* ISP mailbox loopback echo diagnostic error code */ 1175 #define MBS_LB_RESET 0x17 1176 1177 /* AEN mailbox Port Diagnostics test */ 1178 #define AEN_START_DIAG_TEST 0x0 /* start the diagnostics */ 1179 #define AEN_DONE_DIAG_TEST_WITH_NOERR 0x1 /* Done with no errors */ 1180 #define AEN_DONE_DIAG_TEST_WITH_ERR 0x2 /* Done with error.*/ 1181 1182 /* 1183 * Firmware options 1, 2, 3. 1184 */ 1185 #define FO1_AE_ON_LIPF8 BIT_0 1186 #define FO1_AE_ALL_LIP_RESET BIT_1 1187 #define FO1_CTIO_RETRY BIT_3 1188 #define FO1_DISABLE_LIP_F7_SW BIT_4 1189 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 1190 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 1191 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 1192 #define FO1_SET_EMPHASIS_SWING BIT_8 1193 #define FO1_AE_AUTO_BYPASS BIT_9 1194 #define FO1_ENABLE_PURE_IOCB BIT_10 1195 #define FO1_AE_PLOGI_RJT BIT_11 1196 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 1197 #define FO1_AE_QUEUE_FULL BIT_13 1198 1199 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 1200 #define FO2_REV_LOOPBACK BIT_1 1201 1202 #define FO3_ENABLE_EMERG_IOCB BIT_0 1203 #define FO3_AE_RND_ERROR BIT_1 1204 1205 /* 24XX additional firmware options */ 1206 #define ADD_FO_COUNT 3 1207 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 1208 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 1209 1210 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 1211 1212 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 1213 1214 /* 1215 * ISP mailbox commands 1216 */ 1217 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1218 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1219 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 1220 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 1221 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1222 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 1223 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 1224 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 1225 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */ 1226 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 1227 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 1228 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 1229 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 1230 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 1231 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 1232 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 1233 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 1234 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1235 #define MBC_RESET 0x18 /* Reset. */ 1236 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1237 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1238 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1239 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1240 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1241 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1242 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1243 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1244 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */ 1245 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1246 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1247 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1248 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1249 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1250 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1251 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1252 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1253 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1254 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1255 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1256 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1257 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1258 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1259 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1260 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1261 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1262 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1263 /* Initialization Procedure */ 1264 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1265 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1266 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1267 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1268 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1269 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1270 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1271 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1272 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1273 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1274 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1275 /* commandd. */ 1276 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1277 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1278 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1279 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1280 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1281 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1282 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1283 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1284 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1285 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1286 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1287 1288 /* 1289 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1290 * should be defined with MBC_MR_* 1291 */ 1292 #define MBC_MR_DRV_SHUTDOWN 0x6A 1293 1294 /* 1295 * ISP24xx mailbox commands 1296 */ 1297 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1298 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1299 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1300 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1301 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1302 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1303 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1304 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1305 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1306 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1307 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1308 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1309 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1310 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1311 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1312 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1313 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1314 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1315 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1316 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1317 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1318 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1319 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1320 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1321 1322 /* 1323 * ISP81xx mailbox commands 1324 */ 1325 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1326 1327 /* 1328 * ISP8044 mailbox commands 1329 */ 1330 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1331 #define HCS_WRITE_SERDES 0x3 1332 #define HCS_READ_SERDES 0x4 1333 1334 /* Firmware return data sizes */ 1335 #define FCAL_MAP_SIZE 128 1336 1337 /* Mailbox bit definitions for out_mb and in_mb */ 1338 #define MBX_31 BIT_31 1339 #define MBX_30 BIT_30 1340 #define MBX_29 BIT_29 1341 #define MBX_28 BIT_28 1342 #define MBX_27 BIT_27 1343 #define MBX_26 BIT_26 1344 #define MBX_25 BIT_25 1345 #define MBX_24 BIT_24 1346 #define MBX_23 BIT_23 1347 #define MBX_22 BIT_22 1348 #define MBX_21 BIT_21 1349 #define MBX_20 BIT_20 1350 #define MBX_19 BIT_19 1351 #define MBX_18 BIT_18 1352 #define MBX_17 BIT_17 1353 #define MBX_16 BIT_16 1354 #define MBX_15 BIT_15 1355 #define MBX_14 BIT_14 1356 #define MBX_13 BIT_13 1357 #define MBX_12 BIT_12 1358 #define MBX_11 BIT_11 1359 #define MBX_10 BIT_10 1360 #define MBX_9 BIT_9 1361 #define MBX_8 BIT_8 1362 #define MBX_7 BIT_7 1363 #define MBX_6 BIT_6 1364 #define MBX_5 BIT_5 1365 #define MBX_4 BIT_4 1366 #define MBX_3 BIT_3 1367 #define MBX_2 BIT_2 1368 #define MBX_1 BIT_1 1369 #define MBX_0 BIT_0 1370 1371 #define RNID_TYPE_ELS_CMD 0x5 1372 #define RNID_TYPE_PORT_LOGIN 0x7 1373 #define RNID_BUFFER_CREDITS 0x8 1374 #define RNID_TYPE_SET_VERSION 0x9 1375 #define RNID_TYPE_ASIC_TEMP 0xC 1376 1377 #define ELS_CMD_MAP_SIZE 32 1378 1379 /* 1380 * Firmware state codes from get firmware state mailbox command 1381 */ 1382 #define FSTATE_CONFIG_WAIT 0 1383 #define FSTATE_WAIT_AL_PA 1 1384 #define FSTATE_WAIT_LOGIN 2 1385 #define FSTATE_READY 3 1386 #define FSTATE_LOSS_OF_SYNC 4 1387 #define FSTATE_ERROR 5 1388 #define FSTATE_REINIT 6 1389 #define FSTATE_NON_PART 7 1390 1391 #define FSTATE_CONFIG_CORRECT 0 1392 #define FSTATE_P2P_RCV_LIP 1 1393 #define FSTATE_P2P_CHOOSE_LOOP 2 1394 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1395 #define FSTATE_FATAL_ERROR 4 1396 #define FSTATE_LOOP_BACK_CONN 5 1397 1398 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1399 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1400 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1401 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1402 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1403 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED 1404 #define QLA27XX_DEFAULT_IMAGE 0 1405 #define QLA27XX_PRIMARY_IMAGE 1 1406 #define QLA27XX_SECONDARY_IMAGE 2 1407 1408 /* 1409 * Port Database structure definition 1410 * Little endian except where noted. 1411 */ 1412 #define PORT_DATABASE_SIZE 128 /* bytes */ 1413 typedef struct { 1414 uint8_t options; 1415 uint8_t control; 1416 uint8_t master_state; 1417 uint8_t slave_state; 1418 uint8_t reserved[2]; 1419 uint8_t hard_address; 1420 uint8_t reserved_1; 1421 uint8_t port_id[4]; 1422 uint8_t node_name[WWN_SIZE]; 1423 uint8_t port_name[WWN_SIZE]; 1424 __le16 execution_throttle; 1425 uint16_t execution_count; 1426 uint8_t reset_count; 1427 uint8_t reserved_2; 1428 uint16_t resource_allocation; 1429 uint16_t current_allocation; 1430 uint16_t queue_head; 1431 uint16_t queue_tail; 1432 uint16_t transmit_execution_list_next; 1433 uint16_t transmit_execution_list_previous; 1434 uint16_t common_features; 1435 uint16_t total_concurrent_sequences; 1436 uint16_t RO_by_information_category; 1437 uint8_t recipient; 1438 uint8_t initiator; 1439 uint16_t receive_data_size; 1440 uint16_t concurrent_sequences; 1441 uint16_t open_sequences_per_exchange; 1442 uint16_t lun_abort_flags; 1443 uint16_t lun_stop_flags; 1444 uint16_t stop_queue_head; 1445 uint16_t stop_queue_tail; 1446 uint16_t port_retry_timer; 1447 uint16_t next_sequence_id; 1448 uint16_t frame_count; 1449 uint16_t PRLI_payload_length; 1450 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1451 /* Bits 15-0 of word 0 */ 1452 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1453 /* Bits 15-0 of word 3 */ 1454 uint16_t loop_id; 1455 uint16_t extended_lun_info_list_pointer; 1456 uint16_t extended_lun_stop_list_pointer; 1457 } port_database_t; 1458 1459 /* 1460 * Port database slave/master states 1461 */ 1462 #define PD_STATE_DISCOVERY 0 1463 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1464 #define PD_STATE_PORT_LOGIN 2 1465 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1466 #define PD_STATE_PROCESS_LOGIN 4 1467 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1468 #define PD_STATE_PORT_LOGGED_IN 6 1469 #define PD_STATE_PORT_UNAVAILABLE 7 1470 #define PD_STATE_PROCESS_LOGOUT 8 1471 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1472 #define PD_STATE_PORT_LOGOUT 10 1473 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1474 1475 1476 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1477 #define QLA_ZIO_DISABLED 0 1478 #define QLA_ZIO_DEFAULT_TIMER 2 1479 1480 /* 1481 * ISP Initialization Control Block. 1482 * Little endian except where noted. 1483 */ 1484 #define ICB_VERSION 1 1485 typedef struct { 1486 uint8_t version; 1487 uint8_t reserved_1; 1488 1489 /* 1490 * LSB BIT 0 = Enable Hard Loop Id 1491 * LSB BIT 1 = Enable Fairness 1492 * LSB BIT 2 = Enable Full-Duplex 1493 * LSB BIT 3 = Enable Fast Posting 1494 * LSB BIT 4 = Enable Target Mode 1495 * LSB BIT 5 = Disable Initiator Mode 1496 * LSB BIT 6 = Enable ADISC 1497 * LSB BIT 7 = Enable Target Inquiry Data 1498 * 1499 * MSB BIT 0 = Enable PDBC Notify 1500 * MSB BIT 1 = Non Participating LIP 1501 * MSB BIT 2 = Descending Loop ID Search 1502 * MSB BIT 3 = Acquire Loop ID in LIPA 1503 * MSB BIT 4 = Stop PortQ on Full Status 1504 * MSB BIT 5 = Full Login after LIP 1505 * MSB BIT 6 = Node Name Option 1506 * MSB BIT 7 = Ext IFWCB enable bit 1507 */ 1508 uint8_t firmware_options[2]; 1509 1510 __le16 frame_payload_size; 1511 __le16 max_iocb_allocation; 1512 __le16 execution_throttle; 1513 uint8_t retry_count; 1514 uint8_t retry_delay; /* unused */ 1515 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1516 uint16_t hard_address; 1517 uint8_t inquiry_data; 1518 uint8_t login_timeout; 1519 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1520 1521 __le16 request_q_outpointer; 1522 __le16 response_q_inpointer; 1523 __le16 request_q_length; 1524 __le16 response_q_length; 1525 __le64 request_q_address __packed; 1526 __le64 response_q_address __packed; 1527 1528 __le16 lun_enables; 1529 uint8_t command_resource_count; 1530 uint8_t immediate_notify_resource_count; 1531 __le16 timeout; 1532 uint8_t reserved_2[2]; 1533 1534 /* 1535 * LSB BIT 0 = Timer Operation mode bit 0 1536 * LSB BIT 1 = Timer Operation mode bit 1 1537 * LSB BIT 2 = Timer Operation mode bit 2 1538 * LSB BIT 3 = Timer Operation mode bit 3 1539 * LSB BIT 4 = Init Config Mode bit 0 1540 * LSB BIT 5 = Init Config Mode bit 1 1541 * LSB BIT 6 = Init Config Mode bit 2 1542 * LSB BIT 7 = Enable Non part on LIHA failure 1543 * 1544 * MSB BIT 0 = Enable class 2 1545 * MSB BIT 1 = Enable ACK0 1546 * MSB BIT 2 = 1547 * MSB BIT 3 = 1548 * MSB BIT 4 = FC Tape Enable 1549 * MSB BIT 5 = Enable FC Confirm 1550 * MSB BIT 6 = Enable command queuing in target mode 1551 * MSB BIT 7 = No Logo On Link Down 1552 */ 1553 uint8_t add_firmware_options[2]; 1554 1555 uint8_t response_accumulation_timer; 1556 uint8_t interrupt_delay_timer; 1557 1558 /* 1559 * LSB BIT 0 = Enable Read xfr_rdy 1560 * LSB BIT 1 = Soft ID only 1561 * LSB BIT 2 = 1562 * LSB BIT 3 = 1563 * LSB BIT 4 = FCP RSP Payload [0] 1564 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1565 * LSB BIT 6 = Enable Out-of-Order frame handling 1566 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1567 * 1568 * MSB BIT 0 = Sbus enable - 2300 1569 * MSB BIT 1 = 1570 * MSB BIT 2 = 1571 * MSB BIT 3 = 1572 * MSB BIT 4 = LED mode 1573 * MSB BIT 5 = enable 50 ohm termination 1574 * MSB BIT 6 = Data Rate (2300 only) 1575 * MSB BIT 7 = Data Rate (2300 only) 1576 */ 1577 uint8_t special_options[2]; 1578 1579 uint8_t reserved_3[26]; 1580 } init_cb_t; 1581 1582 /* Special Features Control Block */ 1583 struct init_sf_cb { 1584 uint8_t format; 1585 uint8_t reserved0; 1586 /* 1587 * BIT 15-14 = Reserved 1588 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled) 1589 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled) 1590 * BIT 11-0 = Reserved 1591 */ 1592 __le16 flags; 1593 uint8_t reserved1[32]; 1594 uint16_t discard_OHRB_timeout_value; 1595 uint16_t remote_write_opt_queue_num; 1596 uint8_t reserved2[40]; 1597 uint8_t scm_related_parameter[16]; 1598 uint8_t reserved3[32]; 1599 }; 1600 1601 /* 1602 * Get Link Status mailbox command return buffer. 1603 */ 1604 #define GLSO_SEND_RPS BIT_0 1605 #define GLSO_USE_DID BIT_3 1606 1607 struct link_statistics { 1608 __le32 link_fail_cnt; 1609 __le32 loss_sync_cnt; 1610 __le32 loss_sig_cnt; 1611 __le32 prim_seq_err_cnt; 1612 __le32 inval_xmit_word_cnt; 1613 __le32 inval_crc_cnt; 1614 __le32 lip_cnt; 1615 __le32 link_up_cnt; 1616 __le32 link_down_loop_init_tmo; 1617 __le32 link_down_los; 1618 __le32 link_down_loss_rcv_clk; 1619 uint32_t reserved0[5]; 1620 __le32 port_cfg_chg; 1621 uint32_t reserved1[11]; 1622 __le32 rsp_q_full; 1623 __le32 atio_q_full; 1624 __le32 drop_ae; 1625 __le32 els_proto_err; 1626 __le32 reserved2; 1627 __le32 tx_frames; 1628 __le32 rx_frames; 1629 __le32 discarded_frames; 1630 __le32 dropped_frames; 1631 uint32_t reserved3; 1632 __le32 nos_rcvd; 1633 uint32_t reserved4[4]; 1634 __le32 tx_prjt; 1635 __le32 rcv_exfail; 1636 __le32 rcv_abts; 1637 __le32 seq_frm_miss; 1638 __le32 corr_err; 1639 __le32 mb_rqst; 1640 __le32 nport_full; 1641 __le32 eofa; 1642 uint32_t reserved5; 1643 __le64 fpm_recv_word_cnt; 1644 __le64 fpm_disc_word_cnt; 1645 __le64 fpm_xmit_word_cnt; 1646 uint32_t reserved6[70]; 1647 }; 1648 1649 /* 1650 * NVRAM Command values. 1651 */ 1652 #define NV_START_BIT BIT_2 1653 #define NV_WRITE_OP (BIT_26+BIT_24) 1654 #define NV_READ_OP (BIT_26+BIT_25) 1655 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1656 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1657 #define NV_DELAY_COUNT 10 1658 1659 /* 1660 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1661 */ 1662 typedef struct { 1663 /* 1664 * NVRAM header 1665 */ 1666 uint8_t id[4]; 1667 uint8_t nvram_version; 1668 uint8_t reserved_0; 1669 1670 /* 1671 * NVRAM RISC parameter block 1672 */ 1673 uint8_t parameter_block_version; 1674 uint8_t reserved_1; 1675 1676 /* 1677 * LSB BIT 0 = Enable Hard Loop Id 1678 * LSB BIT 1 = Enable Fairness 1679 * LSB BIT 2 = Enable Full-Duplex 1680 * LSB BIT 3 = Enable Fast Posting 1681 * LSB BIT 4 = Enable Target Mode 1682 * LSB BIT 5 = Disable Initiator Mode 1683 * LSB BIT 6 = Enable ADISC 1684 * LSB BIT 7 = Enable Target Inquiry Data 1685 * 1686 * MSB BIT 0 = Enable PDBC Notify 1687 * MSB BIT 1 = Non Participating LIP 1688 * MSB BIT 2 = Descending Loop ID Search 1689 * MSB BIT 3 = Acquire Loop ID in LIPA 1690 * MSB BIT 4 = Stop PortQ on Full Status 1691 * MSB BIT 5 = Full Login after LIP 1692 * MSB BIT 6 = Node Name Option 1693 * MSB BIT 7 = Ext IFWCB enable bit 1694 */ 1695 uint8_t firmware_options[2]; 1696 1697 __le16 frame_payload_size; 1698 __le16 max_iocb_allocation; 1699 __le16 execution_throttle; 1700 uint8_t retry_count; 1701 uint8_t retry_delay; /* unused */ 1702 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1703 uint16_t hard_address; 1704 uint8_t inquiry_data; 1705 uint8_t login_timeout; 1706 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1707 1708 /* 1709 * LSB BIT 0 = Timer Operation mode bit 0 1710 * LSB BIT 1 = Timer Operation mode bit 1 1711 * LSB BIT 2 = Timer Operation mode bit 2 1712 * LSB BIT 3 = Timer Operation mode bit 3 1713 * LSB BIT 4 = Init Config Mode bit 0 1714 * LSB BIT 5 = Init Config Mode bit 1 1715 * LSB BIT 6 = Init Config Mode bit 2 1716 * LSB BIT 7 = Enable Non part on LIHA failure 1717 * 1718 * MSB BIT 0 = Enable class 2 1719 * MSB BIT 1 = Enable ACK0 1720 * MSB BIT 2 = 1721 * MSB BIT 3 = 1722 * MSB BIT 4 = FC Tape Enable 1723 * MSB BIT 5 = Enable FC Confirm 1724 * MSB BIT 6 = Enable command queuing in target mode 1725 * MSB BIT 7 = No Logo On Link Down 1726 */ 1727 uint8_t add_firmware_options[2]; 1728 1729 uint8_t response_accumulation_timer; 1730 uint8_t interrupt_delay_timer; 1731 1732 /* 1733 * LSB BIT 0 = Enable Read xfr_rdy 1734 * LSB BIT 1 = Soft ID only 1735 * LSB BIT 2 = 1736 * LSB BIT 3 = 1737 * LSB BIT 4 = FCP RSP Payload [0] 1738 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1739 * LSB BIT 6 = Enable Out-of-Order frame handling 1740 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1741 * 1742 * MSB BIT 0 = Sbus enable - 2300 1743 * MSB BIT 1 = 1744 * MSB BIT 2 = 1745 * MSB BIT 3 = 1746 * MSB BIT 4 = LED mode 1747 * MSB BIT 5 = enable 50 ohm termination 1748 * MSB BIT 6 = Data Rate (2300 only) 1749 * MSB BIT 7 = Data Rate (2300 only) 1750 */ 1751 uint8_t special_options[2]; 1752 1753 /* Reserved for expanded RISC parameter block */ 1754 uint8_t reserved_2[22]; 1755 1756 /* 1757 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1758 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1759 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1760 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1761 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1762 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1763 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1764 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1765 * 1766 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1767 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1768 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1769 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1770 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1771 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1772 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1773 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1774 * 1775 * LSB BIT 0 = Output Swing 1G bit 0 1776 * LSB BIT 1 = Output Swing 1G bit 1 1777 * LSB BIT 2 = Output Swing 1G bit 2 1778 * LSB BIT 3 = Output Emphasis 1G bit 0 1779 * LSB BIT 4 = Output Emphasis 1G bit 1 1780 * LSB BIT 5 = Output Swing 2G bit 0 1781 * LSB BIT 6 = Output Swing 2G bit 1 1782 * LSB BIT 7 = Output Swing 2G bit 2 1783 * 1784 * MSB BIT 0 = Output Emphasis 2G bit 0 1785 * MSB BIT 1 = Output Emphasis 2G bit 1 1786 * MSB BIT 2 = Output Enable 1787 * MSB BIT 3 = 1788 * MSB BIT 4 = 1789 * MSB BIT 5 = 1790 * MSB BIT 6 = 1791 * MSB BIT 7 = 1792 */ 1793 uint8_t seriallink_options[4]; 1794 1795 /* 1796 * NVRAM host parameter block 1797 * 1798 * LSB BIT 0 = Enable spinup delay 1799 * LSB BIT 1 = Disable BIOS 1800 * LSB BIT 2 = Enable Memory Map BIOS 1801 * LSB BIT 3 = Enable Selectable Boot 1802 * LSB BIT 4 = Disable RISC code load 1803 * LSB BIT 5 = Set cache line size 1 1804 * LSB BIT 6 = PCI Parity Disable 1805 * LSB BIT 7 = Enable extended logging 1806 * 1807 * MSB BIT 0 = Enable 64bit addressing 1808 * MSB BIT 1 = Enable lip reset 1809 * MSB BIT 2 = Enable lip full login 1810 * MSB BIT 3 = Enable target reset 1811 * MSB BIT 4 = Enable database storage 1812 * MSB BIT 5 = Enable cache flush read 1813 * MSB BIT 6 = Enable database load 1814 * MSB BIT 7 = Enable alternate WWN 1815 */ 1816 uint8_t host_p[2]; 1817 1818 uint8_t boot_node_name[WWN_SIZE]; 1819 uint8_t boot_lun_number; 1820 uint8_t reset_delay; 1821 uint8_t port_down_retry_count; 1822 uint8_t boot_id_number; 1823 __le16 max_luns_per_target; 1824 uint8_t fcode_boot_port_name[WWN_SIZE]; 1825 uint8_t alternate_port_name[WWN_SIZE]; 1826 uint8_t alternate_node_name[WWN_SIZE]; 1827 1828 /* 1829 * BIT 0 = Selective Login 1830 * BIT 1 = Alt-Boot Enable 1831 * BIT 2 = 1832 * BIT 3 = Boot Order List 1833 * BIT 4 = 1834 * BIT 5 = Selective LUN 1835 * BIT 6 = 1836 * BIT 7 = unused 1837 */ 1838 uint8_t efi_parameters; 1839 1840 uint8_t link_down_timeout; 1841 1842 uint8_t adapter_id[16]; 1843 1844 uint8_t alt1_boot_node_name[WWN_SIZE]; 1845 uint16_t alt1_boot_lun_number; 1846 uint8_t alt2_boot_node_name[WWN_SIZE]; 1847 uint16_t alt2_boot_lun_number; 1848 uint8_t alt3_boot_node_name[WWN_SIZE]; 1849 uint16_t alt3_boot_lun_number; 1850 uint8_t alt4_boot_node_name[WWN_SIZE]; 1851 uint16_t alt4_boot_lun_number; 1852 uint8_t alt5_boot_node_name[WWN_SIZE]; 1853 uint16_t alt5_boot_lun_number; 1854 uint8_t alt6_boot_node_name[WWN_SIZE]; 1855 uint16_t alt6_boot_lun_number; 1856 uint8_t alt7_boot_node_name[WWN_SIZE]; 1857 uint16_t alt7_boot_lun_number; 1858 1859 uint8_t reserved_3[2]; 1860 1861 /* Offset 200-215 : Model Number */ 1862 uint8_t model_number[16]; 1863 1864 /* OEM related items */ 1865 uint8_t oem_specific[16]; 1866 1867 /* 1868 * NVRAM Adapter Features offset 232-239 1869 * 1870 * LSB BIT 0 = External GBIC 1871 * LSB BIT 1 = Risc RAM parity 1872 * LSB BIT 2 = Buffer Plus Module 1873 * LSB BIT 3 = Multi Chip Adapter 1874 * LSB BIT 4 = Internal connector 1875 * LSB BIT 5 = 1876 * LSB BIT 6 = 1877 * LSB BIT 7 = 1878 * 1879 * MSB BIT 0 = 1880 * MSB BIT 1 = 1881 * MSB BIT 2 = 1882 * MSB BIT 3 = 1883 * MSB BIT 4 = 1884 * MSB BIT 5 = 1885 * MSB BIT 6 = 1886 * MSB BIT 7 = 1887 */ 1888 uint8_t adapter_features[2]; 1889 1890 uint8_t reserved_4[16]; 1891 1892 /* Subsystem vendor ID for ISP2200 */ 1893 uint16_t subsystem_vendor_id_2200; 1894 1895 /* Subsystem device ID for ISP2200 */ 1896 uint16_t subsystem_device_id_2200; 1897 1898 uint8_t reserved_5; 1899 uint8_t checksum; 1900 } nvram_t; 1901 1902 /* 1903 * ISP queue - response queue entry definition. 1904 */ 1905 typedef struct { 1906 uint8_t entry_type; /* Entry type. */ 1907 uint8_t entry_count; /* Entry count. */ 1908 uint8_t sys_define; /* System defined. */ 1909 uint8_t entry_status; /* Entry Status. */ 1910 uint32_t handle; /* System defined handle */ 1911 uint8_t data[52]; 1912 uint32_t signature; 1913 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1914 } response_t; 1915 1916 /* 1917 * ISP queue - ATIO queue entry definition. 1918 */ 1919 struct atio { 1920 uint8_t entry_type; /* Entry type. */ 1921 uint8_t entry_count; /* Entry count. */ 1922 __le16 attr_n_length; 1923 uint8_t data[56]; 1924 uint32_t signature; 1925 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1926 }; 1927 1928 typedef union { 1929 __le16 extended; 1930 struct { 1931 uint8_t reserved; 1932 uint8_t standard; 1933 } id; 1934 } target_id_t; 1935 1936 #define SET_TARGET_ID(ha, to, from) \ 1937 do { \ 1938 if (HAS_EXTENDED_IDS(ha)) \ 1939 to.extended = cpu_to_le16(from); \ 1940 else \ 1941 to.id.standard = (uint8_t)from; \ 1942 } while (0) 1943 1944 /* 1945 * ISP queue - command entry structure definition. 1946 */ 1947 #define COMMAND_TYPE 0x11 /* Command entry */ 1948 typedef struct { 1949 uint8_t entry_type; /* Entry type. */ 1950 uint8_t entry_count; /* Entry count. */ 1951 uint8_t sys_define; /* System defined. */ 1952 uint8_t entry_status; /* Entry Status. */ 1953 uint32_t handle; /* System handle. */ 1954 target_id_t target; /* SCSI ID */ 1955 __le16 lun; /* SCSI LUN */ 1956 __le16 control_flags; /* Control flags. */ 1957 #define CF_WRITE BIT_6 1958 #define CF_READ BIT_5 1959 #define CF_SIMPLE_TAG BIT_3 1960 #define CF_ORDERED_TAG BIT_2 1961 #define CF_HEAD_TAG BIT_1 1962 uint16_t reserved_1; 1963 __le16 timeout; /* Command timeout. */ 1964 __le16 dseg_count; /* Data segment count. */ 1965 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1966 __le32 byte_count; /* Total byte count. */ 1967 union { 1968 struct dsd32 dsd32[3]; 1969 struct dsd64 dsd64[2]; 1970 }; 1971 } cmd_entry_t; 1972 1973 /* 1974 * ISP queue - 64-Bit addressing, command entry structure definition. 1975 */ 1976 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1977 typedef struct { 1978 uint8_t entry_type; /* Entry type. */ 1979 uint8_t entry_count; /* Entry count. */ 1980 uint8_t sys_define; /* System defined. */ 1981 uint8_t entry_status; /* Entry Status. */ 1982 uint32_t handle; /* System handle. */ 1983 target_id_t target; /* SCSI ID */ 1984 __le16 lun; /* SCSI LUN */ 1985 __le16 control_flags; /* Control flags. */ 1986 uint16_t reserved_1; 1987 __le16 timeout; /* Command timeout. */ 1988 __le16 dseg_count; /* Data segment count. */ 1989 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1990 uint32_t byte_count; /* Total byte count. */ 1991 struct dsd64 dsd[2]; 1992 } cmd_a64_entry_t, request_t; 1993 1994 /* 1995 * ISP queue - continuation entry structure definition. 1996 */ 1997 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1998 typedef struct { 1999 uint8_t entry_type; /* Entry type. */ 2000 uint8_t entry_count; /* Entry count. */ 2001 uint8_t sys_define; /* System defined. */ 2002 uint8_t entry_status; /* Entry Status. */ 2003 uint32_t reserved; 2004 struct dsd32 dsd[7]; 2005 } cont_entry_t; 2006 2007 /* 2008 * ISP queue - 64-Bit addressing, continuation entry structure definition. 2009 */ 2010 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 2011 typedef struct { 2012 uint8_t entry_type; /* Entry type. */ 2013 uint8_t entry_count; /* Entry count. */ 2014 uint8_t sys_define; /* System defined. */ 2015 uint8_t entry_status; /* Entry Status. */ 2016 struct dsd64 dsd[5]; 2017 } cont_a64_entry_t; 2018 2019 #define PO_MODE_DIF_INSERT 0 2020 #define PO_MODE_DIF_REMOVE 1 2021 #define PO_MODE_DIF_PASS 2 2022 #define PO_MODE_DIF_REPLACE 3 2023 #define PO_MODE_DIF_TCP_CKSUM 6 2024 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 2025 #define PO_DISABLE_GUARD_CHECK BIT_4 2026 #define PO_DISABLE_INCR_REF_TAG BIT_5 2027 #define PO_DIS_HEADER_MODE BIT_7 2028 #define PO_ENABLE_DIF_BUNDLING BIT_8 2029 #define PO_DIS_FRAME_MODE BIT_9 2030 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 2031 #define PO_DIS_VALD_APP_REF_ESC BIT_11 2032 2033 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 2034 #define PO_DIS_REF_TAG_REPL BIT_13 2035 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 2036 #define PO_DIS_REF_TAG_VALD BIT_15 2037 2038 /* 2039 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 2040 */ 2041 struct crc_context { 2042 uint32_t handle; /* System handle. */ 2043 __le32 ref_tag; 2044 __le16 app_tag; 2045 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 2046 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 2047 __le16 guard_seed; /* Initial Guard Seed */ 2048 __le16 prot_opts; /* Requested Data Protection Mode */ 2049 __le16 blk_size; /* Data size in bytes */ 2050 __le16 runt_blk_guard; /* Guard value for runt block (tape 2051 * only) */ 2052 __le32 byte_count; /* Total byte count/ total data 2053 * transfer count */ 2054 union { 2055 struct { 2056 uint32_t reserved_1; 2057 uint16_t reserved_2; 2058 uint16_t reserved_3; 2059 uint32_t reserved_4; 2060 struct dsd64 data_dsd[1]; 2061 uint32_t reserved_5[2]; 2062 uint32_t reserved_6; 2063 } nobundling; 2064 struct { 2065 __le32 dif_byte_count; /* Total DIF byte 2066 * count */ 2067 uint16_t reserved_1; 2068 __le16 dseg_count; /* Data segment count */ 2069 uint32_t reserved_2; 2070 struct dsd64 data_dsd[1]; 2071 struct dsd64 dif_dsd; 2072 } bundling; 2073 } u; 2074 2075 struct fcp_cmnd fcp_cmnd; 2076 dma_addr_t crc_ctx_dma; 2077 /* List of DMA context transfers */ 2078 struct list_head dsd_list; 2079 2080 /* List of DIF Bundling context DMA address */ 2081 struct list_head ldif_dsd_list; 2082 u8 no_ldif_dsd; 2083 2084 struct list_head ldif_dma_hndl_list; 2085 u32 dif_bundl_len; 2086 u8 no_dif_bundl; 2087 /* This structure should not exceed 512 bytes */ 2088 }; 2089 2090 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 2091 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 2092 2093 /* 2094 * ISP queue - status entry structure definition. 2095 */ 2096 #define STATUS_TYPE 0x03 /* Status entry. */ 2097 typedef struct { 2098 uint8_t entry_type; /* Entry type. */ 2099 uint8_t entry_count; /* Entry count. */ 2100 uint8_t sys_define; /* System defined. */ 2101 uint8_t entry_status; /* Entry Status. */ 2102 uint32_t handle; /* System handle. */ 2103 __le16 scsi_status; /* SCSI status. */ 2104 __le16 comp_status; /* Completion status. */ 2105 __le16 state_flags; /* State flags. */ 2106 __le16 status_flags; /* Status flags. */ 2107 __le16 rsp_info_len; /* Response Info Length. */ 2108 __le16 req_sense_length; /* Request sense data length. */ 2109 __le32 residual_length; /* Residual transfer length. */ 2110 uint8_t rsp_info[8]; /* FCP response information. */ 2111 uint8_t req_sense_data[32]; /* Request sense data. */ 2112 } sts_entry_t; 2113 2114 /* 2115 * Status entry entry status 2116 */ 2117 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 2118 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 2119 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 2120 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 2121 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 2122 #define RF_BUSY BIT_1 /* Busy */ 2123 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 2124 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 2125 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 2126 RF_INV_E_TYPE) 2127 2128 /* 2129 * Status entry SCSI status bit definitions. 2130 */ 2131 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 2132 #define SS_RESIDUAL_UNDER BIT_11 2133 #define SS_RESIDUAL_OVER BIT_10 2134 #define SS_SENSE_LEN_VALID BIT_9 2135 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 2136 #define SS_SCSI_STATUS_BYTE 0xff 2137 2138 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 2139 #define SS_BUSY_CONDITION BIT_3 2140 #define SS_CONDITION_MET BIT_2 2141 #define SS_CHECK_CONDITION BIT_1 2142 2143 /* 2144 * Status entry completion status 2145 */ 2146 #define CS_COMPLETE 0x0 /* No errors */ 2147 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 2148 #define CS_DMA 0x2 /* A DMA direction error. */ 2149 #define CS_TRANSPORT 0x3 /* Transport error. */ 2150 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 2151 #define CS_ABORTED 0x5 /* System aborted command. */ 2152 #define CS_TIMEOUT 0x6 /* Timeout error. */ 2153 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 2154 #define CS_DIF_ERROR 0xC /* DIF error detected */ 2155 2156 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 2157 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 2158 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 2159 /* (selection timeout) */ 2160 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 2161 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 2162 #define CS_PORT_BUSY 0x2B /* Port Busy */ 2163 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 2164 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 2165 failure */ 2166 #define CS_REJECT_RECEIVED 0x4E /* Reject received */ 2167 #define CS_EDIF_AUTH_ERROR 0x63 /* decrypt error */ 2168 #define CS_EDIF_PAD_LEN_ERROR 0x65 /* pad > frame size, not 4byte align */ 2169 #define CS_EDIF_INV_REQ 0x66 /* invalid request */ 2170 #define CS_EDIF_SPI_ERROR 0x67 /* rx frame unable to locate sa */ 2171 #define CS_EDIF_HDR_ERROR 0x69 /* data frame != expected len */ 2172 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 2173 #define CS_UNKNOWN 0x81 /* Driver defined */ 2174 #define CS_RETRY 0x82 /* Driver defined */ 2175 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 2176 2177 #define CS_BIDIR_RD_OVERRUN 0x700 2178 #define CS_BIDIR_RD_WR_OVERRUN 0x707 2179 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 2180 #define CS_BIDIR_RD_UNDERRUN 0x1500 2181 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 2182 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 2183 #define CS_BIDIR_DMA 0x200 2184 /* 2185 * Status entry status flags 2186 */ 2187 #define SF_ABTS_TERMINATED BIT_10 2188 #define SF_LOGOUT_SENT BIT_13 2189 2190 /* 2191 * ISP queue - status continuation entry structure definition. 2192 */ 2193 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 2194 typedef struct { 2195 uint8_t entry_type; /* Entry type. */ 2196 uint8_t entry_count; /* Entry count. */ 2197 uint8_t sys_define; /* System defined. */ 2198 uint8_t entry_status; /* Entry Status. */ 2199 uint8_t data[60]; /* data */ 2200 } sts_cont_entry_t; 2201 2202 /* 2203 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 2204 * structure definition. 2205 */ 2206 #define STATUS_TYPE_21 0x21 /* Status entry. */ 2207 typedef struct { 2208 uint8_t entry_type; /* Entry type. */ 2209 uint8_t entry_count; /* Entry count. */ 2210 uint8_t handle_count; /* Handle count. */ 2211 uint8_t entry_status; /* Entry Status. */ 2212 uint32_t handle[15]; /* System handles. */ 2213 } sts21_entry_t; 2214 2215 /* 2216 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 2217 * structure definition. 2218 */ 2219 #define STATUS_TYPE_22 0x22 /* Status entry. */ 2220 typedef struct { 2221 uint8_t entry_type; /* Entry type. */ 2222 uint8_t entry_count; /* Entry count. */ 2223 uint8_t handle_count; /* Handle count. */ 2224 uint8_t entry_status; /* Entry Status. */ 2225 uint16_t handle[30]; /* System handles. */ 2226 } sts22_entry_t; 2227 2228 /* 2229 * ISP queue - marker entry structure definition. 2230 */ 2231 #define MARKER_TYPE 0x04 /* Marker entry. */ 2232 typedef struct { 2233 uint8_t entry_type; /* Entry type. */ 2234 uint8_t entry_count; /* Entry count. */ 2235 uint8_t handle_count; /* Handle count. */ 2236 uint8_t entry_status; /* Entry Status. */ 2237 uint32_t sys_define_2; /* System defined. */ 2238 target_id_t target; /* SCSI ID */ 2239 uint8_t modifier; /* Modifier (7-0). */ 2240 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 2241 #define MK_SYNC_ID 1 /* Synchronize ID */ 2242 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2243 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2244 /* clear port changed, */ 2245 /* use sequence number. */ 2246 uint8_t reserved_1; 2247 __le16 sequence_number; /* Sequence number of event */ 2248 __le16 lun; /* SCSI LUN */ 2249 uint8_t reserved_2[48]; 2250 } mrk_entry_t; 2251 2252 /* 2253 * ISP queue - Management Server entry structure definition. 2254 */ 2255 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2256 typedef struct { 2257 uint8_t entry_type; /* Entry type. */ 2258 uint8_t entry_count; /* Entry count. */ 2259 uint8_t handle_count; /* Handle count. */ 2260 uint8_t entry_status; /* Entry Status. */ 2261 uint32_t handle1; /* System handle. */ 2262 target_id_t loop_id; 2263 __le16 status; 2264 __le16 control_flags; /* Control flags. */ 2265 uint16_t reserved2; 2266 __le16 timeout; 2267 __le16 cmd_dsd_count; 2268 __le16 total_dsd_count; 2269 uint8_t type; 2270 uint8_t r_ctl; 2271 __le16 rx_id; 2272 uint16_t reserved3; 2273 uint32_t handle2; 2274 __le32 rsp_bytecount; 2275 __le32 req_bytecount; 2276 struct dsd64 req_dsd; 2277 struct dsd64 rsp_dsd; 2278 } ms_iocb_entry_t; 2279 2280 #define SCM_EDC_ACC_RECEIVED BIT_6 2281 #define SCM_RDF_ACC_RECEIVED BIT_7 2282 2283 /* 2284 * ISP queue - Mailbox Command entry structure definition. 2285 */ 2286 #define MBX_IOCB_TYPE 0x39 2287 struct mbx_entry { 2288 uint8_t entry_type; 2289 uint8_t entry_count; 2290 uint8_t sys_define1; 2291 /* Use sys_define1 for source type */ 2292 #define SOURCE_SCSI 0x00 2293 #define SOURCE_IP 0x01 2294 #define SOURCE_VI 0x02 2295 #define SOURCE_SCTP 0x03 2296 #define SOURCE_MP 0x04 2297 #define SOURCE_MPIOCTL 0x05 2298 #define SOURCE_ASYNC_IOCB 0x07 2299 2300 uint8_t entry_status; 2301 2302 uint32_t handle; 2303 target_id_t loop_id; 2304 2305 __le16 status; 2306 __le16 state_flags; 2307 __le16 status_flags; 2308 2309 uint32_t sys_define2[2]; 2310 2311 __le16 mb0; 2312 __le16 mb1; 2313 __le16 mb2; 2314 __le16 mb3; 2315 __le16 mb6; 2316 __le16 mb7; 2317 __le16 mb9; 2318 __le16 mb10; 2319 uint32_t reserved_2[2]; 2320 uint8_t node_name[WWN_SIZE]; 2321 uint8_t port_name[WWN_SIZE]; 2322 }; 2323 2324 #ifndef IMMED_NOTIFY_TYPE 2325 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2326 /* 2327 * ISP queue - immediate notify entry structure definition. 2328 * This is sent by the ISP to the Target driver. 2329 * This IOCB would have report of events sent by the 2330 * initiator, that needs to be handled by the target 2331 * driver immediately. 2332 */ 2333 struct imm_ntfy_from_isp { 2334 uint8_t entry_type; /* Entry type. */ 2335 uint8_t entry_count; /* Entry count. */ 2336 uint8_t sys_define; /* System defined. */ 2337 uint8_t entry_status; /* Entry Status. */ 2338 union { 2339 struct { 2340 __le32 sys_define_2; /* System defined. */ 2341 target_id_t target; 2342 __le16 lun; 2343 uint8_t target_id; 2344 uint8_t reserved_1; 2345 __le16 status_modifier; 2346 __le16 status; 2347 __le16 task_flags; 2348 __le16 seq_id; 2349 __le16 srr_rx_id; 2350 __le32 srr_rel_offs; 2351 __le16 srr_ui; 2352 #define SRR_IU_DATA_IN 0x1 2353 #define SRR_IU_DATA_OUT 0x5 2354 #define SRR_IU_STATUS 0x7 2355 __le16 srr_ox_id; 2356 uint8_t reserved_2[28]; 2357 } isp2x; 2358 struct { 2359 uint32_t reserved; 2360 __le16 nport_handle; 2361 uint16_t reserved_2; 2362 __le16 flags; 2363 #define NOTIFY24XX_FLAGS_FCSP BIT_5 2364 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2365 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2366 __le16 srr_rx_id; 2367 __le16 status; 2368 uint8_t status_subcode; 2369 uint8_t fw_handle; 2370 __le32 exchange_address; 2371 __le32 srr_rel_offs; 2372 __le16 srr_ui; 2373 __le16 srr_ox_id; 2374 union { 2375 struct { 2376 uint8_t node_name[8]; 2377 } plogi; /* PLOGI/ADISC/PDISC */ 2378 struct { 2379 /* PRLI word 3 bit 0-15 */ 2380 __le16 wd3_lo; 2381 uint8_t resv0[6]; 2382 } prli; 2383 struct { 2384 uint8_t port_id[3]; 2385 uint8_t resv1; 2386 __le16 nport_handle; 2387 uint16_t resv2; 2388 } req_els; 2389 } u; 2390 uint8_t port_name[8]; 2391 uint8_t resv3[3]; 2392 uint8_t vp_index; 2393 uint32_t reserved_5; 2394 uint8_t port_id[3]; 2395 uint8_t reserved_6; 2396 } isp24; 2397 } u; 2398 uint16_t reserved_7; 2399 __le16 ox_id; 2400 } __packed; 2401 #endif 2402 2403 /* 2404 * ISP request and response queue entry sizes 2405 */ 2406 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2407 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2408 2409 2410 2411 /* 2412 * Switch info gathering structure. 2413 */ 2414 typedef struct { 2415 port_id_t d_id; 2416 uint8_t node_name[WWN_SIZE]; 2417 uint8_t port_name[WWN_SIZE]; 2418 uint8_t fabric_port_name[WWN_SIZE]; 2419 uint16_t fp_speed; 2420 uint8_t fc4_type; 2421 uint8_t fc4_features; 2422 } sw_info_t; 2423 2424 /* FCP-4 types */ 2425 #define FC4_TYPE_FCP_SCSI 0x08 2426 #define FC4_TYPE_NVME 0x28 2427 #define FC4_TYPE_OTHER 0x0 2428 #define FC4_TYPE_UNKNOWN 0xff 2429 2430 /* mailbox command 4G & above */ 2431 struct mbx_24xx_entry { 2432 uint8_t entry_type; 2433 uint8_t entry_count; 2434 uint8_t sys_define1; 2435 uint8_t entry_status; 2436 uint32_t handle; 2437 uint16_t mb[28]; 2438 }; 2439 2440 #define IOCB_SIZE 64 2441 2442 /* 2443 * Fibre channel port type. 2444 */ 2445 typedef enum { 2446 FCT_UNKNOWN, 2447 FCT_BROADCAST = 0x01, 2448 FCT_INITIATOR = 0x02, 2449 FCT_TARGET = 0x04, 2450 FCT_NVME_INITIATOR = 0x10, 2451 FCT_NVME_TARGET = 0x20, 2452 FCT_NVME_DISCOVERY = 0x40, 2453 FCT_NVME = 0xf0, 2454 } fc_port_type_t; 2455 2456 enum qla_sess_deletion { 2457 QLA_SESS_DELETION_NONE = 0, 2458 QLA_SESS_DELETION_IN_PROGRESS, 2459 QLA_SESS_DELETED, 2460 }; 2461 2462 enum qlt_plogi_link_t { 2463 QLT_PLOGI_LINK_SAME_WWN, 2464 QLT_PLOGI_LINK_CONFLICT, 2465 QLT_PLOGI_LINK_MAX 2466 }; 2467 2468 struct qlt_plogi_ack_t { 2469 struct list_head list; 2470 struct imm_ntfy_from_isp iocb; 2471 port_id_t id; 2472 int ref_count; 2473 void *fcport; 2474 }; 2475 2476 struct ct_sns_desc { 2477 struct ct_sns_pkt *ct_sns; 2478 dma_addr_t ct_sns_dma; 2479 }; 2480 2481 enum discovery_state { 2482 DSC_DELETED, 2483 DSC_GNN_ID, 2484 DSC_GNL, 2485 DSC_LOGIN_PEND, 2486 DSC_LOGIN_FAILED, 2487 DSC_GPDB, 2488 DSC_UPD_FCPORT, 2489 DSC_LOGIN_COMPLETE, 2490 DSC_ADISC, 2491 DSC_DELETE_PEND, 2492 DSC_LOGIN_AUTH_PEND, 2493 }; 2494 2495 enum login_state { /* FW control Target side */ 2496 DSC_LS_LLIOCB_SENT = 2, 2497 DSC_LS_PLOGI_PEND, 2498 DSC_LS_PLOGI_COMP, 2499 DSC_LS_PRLI_PEND, 2500 DSC_LS_PRLI_COMP, 2501 DSC_LS_PORT_UNAVAIL, 2502 DSC_LS_PRLO_PEND = 9, 2503 DSC_LS_LOGO_PEND, 2504 }; 2505 2506 enum rscn_addr_format { 2507 RSCN_PORT_ADDR, 2508 RSCN_AREA_ADDR, 2509 RSCN_DOM_ADDR, 2510 RSCN_FAB_ADDR, 2511 }; 2512 2513 /* 2514 * Fibre channel port structure. 2515 */ 2516 typedef struct fc_port { 2517 struct list_head list; 2518 struct scsi_qla_host *vha; 2519 2520 unsigned int conf_compl_supported:1; 2521 unsigned int deleted:2; 2522 unsigned int free_pending:1; 2523 unsigned int local:1; 2524 unsigned int logout_on_delete:1; 2525 unsigned int logo_ack_needed:1; 2526 unsigned int keep_nport_handle:1; 2527 unsigned int send_els_logo:1; 2528 unsigned int login_pause:1; 2529 unsigned int login_succ:1; 2530 unsigned int query:1; 2531 unsigned int id_changed:1; 2532 unsigned int scan_needed:1; 2533 unsigned int n2n_flag:1; 2534 unsigned int explicit_logout:1; 2535 unsigned int prli_pend_timer:1; 2536 unsigned int do_prli_nvme:1; 2537 2538 uint8_t nvme_flag; 2539 2540 uint8_t node_name[WWN_SIZE]; 2541 uint8_t port_name[WWN_SIZE]; 2542 port_id_t d_id; 2543 uint16_t loop_id; 2544 uint16_t old_loop_id; 2545 2546 struct completion nvme_del_done; 2547 uint32_t nvme_prli_service_param; 2548 #define NVME_PRLI_SP_PI_CTRL BIT_9 2549 #define NVME_PRLI_SP_SLER BIT_8 2550 #define NVME_PRLI_SP_CONF BIT_7 2551 #define NVME_PRLI_SP_INITIATOR BIT_5 2552 #define NVME_PRLI_SP_TARGET BIT_4 2553 #define NVME_PRLI_SP_DISCOVERY BIT_3 2554 #define NVME_PRLI_SP_FIRST_BURST BIT_0 2555 2556 uint32_t nvme_first_burst_size; 2557 #define NVME_FLAG_REGISTERED 4 2558 #define NVME_FLAG_DELETING 2 2559 #define NVME_FLAG_RESETTING 1 2560 2561 struct fc_port *conflict; 2562 unsigned char logout_completed; 2563 int generation; 2564 2565 struct se_session *se_sess; 2566 struct list_head sess_cmd_list; 2567 spinlock_t sess_cmd_lock; 2568 struct kref sess_kref; 2569 struct qla_tgt *tgt; 2570 unsigned long expires; 2571 struct list_head del_list_entry; 2572 struct work_struct free_work; 2573 struct work_struct reg_work; 2574 uint64_t jiffies_at_registration; 2575 unsigned long prli_expired; 2576 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2577 2578 uint16_t tgt_id; 2579 uint16_t old_tgt_id; 2580 uint16_t sec_since_registration; 2581 2582 uint8_t fcp_prio; 2583 2584 uint8_t fabric_port_name[WWN_SIZE]; 2585 uint16_t fp_speed; 2586 2587 fc_port_type_t port_type; 2588 2589 atomic_t state; 2590 uint32_t flags; 2591 2592 int login_retry; 2593 2594 struct fc_rport *rport, *drport; 2595 u32 supported_classes; 2596 2597 uint8_t fc4_type; 2598 uint8_t fc4_features; 2599 uint8_t scan_state; 2600 2601 unsigned long last_queue_full; 2602 unsigned long last_ramp_up; 2603 2604 uint16_t port_id; 2605 2606 struct nvme_fc_remote_port *nvme_remote_port; 2607 2608 unsigned long retry_delay_timestamp; 2609 struct qla_tgt_sess *tgt_session; 2610 struct ct_sns_desc ct_desc; 2611 enum discovery_state disc_state; 2612 atomic_t shadow_disc_state; 2613 enum discovery_state next_disc_state; 2614 enum login_state fw_login_state; 2615 unsigned long dm_login_expire; 2616 unsigned long plogi_nack_done_deadline; 2617 2618 u32 login_gen, last_login_gen; 2619 u32 rscn_gen, last_rscn_gen; 2620 u32 chip_reset; 2621 struct list_head gnl_entry; 2622 struct work_struct del_work; 2623 u8 iocb[IOCB_SIZE]; 2624 u8 current_login_state; 2625 u8 last_login_state; 2626 u16 n2n_link_reset_cnt; 2627 u16 n2n_chip_reset; 2628 2629 struct dentry *dfs_rport_dir; 2630 2631 u64 tgt_short_link_down_cnt; 2632 u64 tgt_link_down_time; 2633 u64 dev_loss_tmo; 2634 /* 2635 * EDIF parameters for encryption. 2636 */ 2637 struct { 2638 uint32_t enable:1; /* device is edif enabled/req'd */ 2639 uint32_t app_stop:2; 2640 uint32_t aes_gmac:1; 2641 uint32_t app_sess_online:1; 2642 uint32_t tx_sa_set:1; 2643 uint32_t rx_sa_set:1; 2644 uint32_t tx_sa_pending:1; 2645 uint32_t rx_sa_pending:1; 2646 uint32_t tx_rekey_cnt; 2647 uint32_t rx_rekey_cnt; 2648 uint64_t tx_bytes; 2649 uint64_t rx_bytes; 2650 uint8_t sess_down_acked; 2651 uint8_t auth_state; 2652 uint16_t authok:1; 2653 uint16_t rekey_cnt; 2654 struct list_head edif_indx_list; 2655 spinlock_t indx_list_lock; 2656 2657 struct list_head tx_sa_list; 2658 struct list_head rx_sa_list; 2659 spinlock_t sa_list_lock; 2660 } edif; 2661 } fc_port_t; 2662 2663 enum { 2664 FC4_PRIORITY_NVME = 1, 2665 FC4_PRIORITY_FCP = 2, 2666 }; 2667 2668 #define QLA_FCPORT_SCAN 1 2669 #define QLA_FCPORT_FOUND 2 2670 2671 struct event_arg { 2672 fc_port_t *fcport; 2673 srb_t *sp; 2674 port_id_t id; 2675 u16 data[2], rc; 2676 u8 port_name[WWN_SIZE]; 2677 u32 iop[2]; 2678 }; 2679 2680 #include "qla_mr.h" 2681 2682 /* 2683 * Fibre channel port/lun states. 2684 */ 2685 enum { 2686 FCS_UNKNOWN, 2687 FCS_UNCONFIGURED, 2688 FCS_DEVICE_DEAD, 2689 FCS_DEVICE_LOST, 2690 FCS_ONLINE, 2691 }; 2692 2693 extern const char *const port_state_str[5]; 2694 2695 static const char *const port_dstate_str[] = { 2696 [DSC_DELETED] = "DELETED", 2697 [DSC_GNN_ID] = "GNN_ID", 2698 [DSC_GNL] = "GNL", 2699 [DSC_LOGIN_PEND] = "LOGIN_PEND", 2700 [DSC_LOGIN_FAILED] = "LOGIN_FAILED", 2701 [DSC_GPDB] = "GPDB", 2702 [DSC_UPD_FCPORT] = "UPD_FCPORT", 2703 [DSC_LOGIN_COMPLETE] = "LOGIN_COMPLETE", 2704 [DSC_ADISC] = "ADISC", 2705 [DSC_DELETE_PEND] = "DELETE_PEND", 2706 [DSC_LOGIN_AUTH_PEND] = "LOGIN_AUTH_PEND", 2707 }; 2708 2709 /* 2710 * FC port flags. 2711 */ 2712 #define FCF_FABRIC_DEVICE BIT_0 2713 #define FCF_LOGIN_NEEDED BIT_1 2714 #define FCF_FCP2_DEVICE BIT_2 2715 #define FCF_ASYNC_SENT BIT_3 2716 #define FCF_CONF_COMP_SUPPORTED BIT_4 2717 #define FCF_ASYNC_ACTIVE BIT_5 2718 #define FCF_FCSP_DEVICE BIT_6 2719 #define FCF_EDIF_DELETE BIT_7 2720 2721 /* No loop ID flag. */ 2722 #define FC_NO_LOOP_ID 0x1000 2723 2724 /* 2725 * FC-CT interface 2726 * 2727 * NOTE: All structures are big-endian in form. 2728 */ 2729 2730 #define CT_REJECT_RESPONSE 0x8001 2731 #define CT_ACCEPT_RESPONSE 0x8002 2732 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2733 #define CT_REASON_CANNOT_PERFORM 0x09 2734 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2735 #define CT_EXPL_ALREADY_REGISTERED 0x10 2736 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2737 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2738 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2739 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2740 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2741 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2742 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2743 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2744 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2745 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2746 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2747 2748 #define NS_N_PORT_TYPE 0x01 2749 #define NS_NL_PORT_TYPE 0x02 2750 #define NS_NX_PORT_TYPE 0x7F 2751 2752 #define GA_NXT_CMD 0x100 2753 #define GA_NXT_REQ_SIZE (16 + 4) 2754 #define GA_NXT_RSP_SIZE (16 + 620) 2755 2756 #define GPN_FT_CMD 0x172 2757 #define GPN_FT_REQ_SIZE (16 + 4) 2758 #define GNN_FT_CMD 0x173 2759 #define GNN_FT_REQ_SIZE (16 + 4) 2760 2761 #define GID_PT_CMD 0x1A1 2762 #define GID_PT_REQ_SIZE (16 + 4) 2763 2764 #define GPN_ID_CMD 0x112 2765 #define GPN_ID_REQ_SIZE (16 + 4) 2766 #define GPN_ID_RSP_SIZE (16 + 8) 2767 2768 #define GNN_ID_CMD 0x113 2769 #define GNN_ID_REQ_SIZE (16 + 4) 2770 #define GNN_ID_RSP_SIZE (16 + 8) 2771 2772 #define GFT_ID_CMD 0x117 2773 #define GFT_ID_REQ_SIZE (16 + 4) 2774 #define GFT_ID_RSP_SIZE (16 + 32) 2775 2776 #define GID_PN_CMD 0x121 2777 #define GID_PN_REQ_SIZE (16 + 8) 2778 #define GID_PN_RSP_SIZE (16 + 4) 2779 2780 #define RFT_ID_CMD 0x217 2781 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2782 #define RFT_ID_RSP_SIZE 16 2783 2784 #define RFF_ID_CMD 0x21F 2785 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2786 #define RFF_ID_RSP_SIZE 16 2787 2788 #define RNN_ID_CMD 0x213 2789 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2790 #define RNN_ID_RSP_SIZE 16 2791 2792 #define RSNN_NN_CMD 0x239 2793 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2794 #define RSNN_NN_RSP_SIZE 16 2795 2796 #define GFPN_ID_CMD 0x11C 2797 #define GFPN_ID_REQ_SIZE (16 + 4) 2798 #define GFPN_ID_RSP_SIZE (16 + 8) 2799 2800 #define GPSC_CMD 0x127 2801 #define GPSC_REQ_SIZE (16 + 8) 2802 #define GPSC_RSP_SIZE (16 + 2 + 2) 2803 2804 #define GFF_ID_CMD 0x011F 2805 #define GFF_ID_REQ_SIZE (16 + 4) 2806 #define GFF_ID_RSP_SIZE (16 + 128) 2807 2808 /* 2809 * FDMI HBA attribute types. 2810 */ 2811 #define FDMI1_HBA_ATTR_COUNT 10 2812 #define FDMI2_HBA_ATTR_COUNT 17 2813 2814 #define FDMI_HBA_NODE_NAME 0x1 2815 #define FDMI_HBA_MANUFACTURER 0x2 2816 #define FDMI_HBA_SERIAL_NUMBER 0x3 2817 #define FDMI_HBA_MODEL 0x4 2818 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2819 #define FDMI_HBA_HARDWARE_VERSION 0x6 2820 #define FDMI_HBA_DRIVER_VERSION 0x7 2821 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2822 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2823 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2824 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2825 2826 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2827 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd 2828 #define FDMI_HBA_NUM_PORTS 0xe 2829 #define FDMI_HBA_FABRIC_NAME 0xf 2830 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2831 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0 2832 2833 struct ct_fdmi_hba_attr { 2834 __be16 type; 2835 __be16 len; 2836 union { 2837 uint8_t node_name[WWN_SIZE]; 2838 uint8_t manufacturer[64]; 2839 uint8_t serial_num[32]; 2840 uint8_t model[16+1]; 2841 uint8_t model_desc[80]; 2842 uint8_t hw_version[32]; 2843 uint8_t driver_version[32]; 2844 uint8_t orom_version[16]; 2845 uint8_t fw_version[32]; 2846 uint8_t os_version[128]; 2847 __be32 max_ct_len; 2848 2849 uint8_t sym_name[256]; 2850 __be32 vendor_specific_info; 2851 __be32 num_ports; 2852 uint8_t fabric_name[WWN_SIZE]; 2853 uint8_t bios_name[32]; 2854 uint8_t vendor_identifier[8]; 2855 } a; 2856 }; 2857 2858 struct ct_fdmi1_hba_attributes { 2859 __be32 count; 2860 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT]; 2861 }; 2862 2863 struct ct_fdmi2_hba_attributes { 2864 __be32 count; 2865 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT]; 2866 }; 2867 2868 /* 2869 * FDMI Port attribute types. 2870 */ 2871 #define FDMI1_PORT_ATTR_COUNT 6 2872 #define FDMI2_PORT_ATTR_COUNT 16 2873 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23 2874 2875 #define FDMI_PORT_FC4_TYPES 0x1 2876 #define FDMI_PORT_SUPPORT_SPEED 0x2 2877 #define FDMI_PORT_CURRENT_SPEED 0x3 2878 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2879 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2880 #define FDMI_PORT_HOST_NAME 0x6 2881 2882 #define FDMI_PORT_NODE_NAME 0x7 2883 #define FDMI_PORT_NAME 0x8 2884 #define FDMI_PORT_SYM_NAME 0x9 2885 #define FDMI_PORT_TYPE 0xa 2886 #define FDMI_PORT_SUPP_COS 0xb 2887 #define FDMI_PORT_FABRIC_NAME 0xc 2888 #define FDMI_PORT_FC4_TYPE 0xd 2889 #define FDMI_PORT_STATE 0x101 2890 #define FDMI_PORT_COUNT 0x102 2891 #define FDMI_PORT_IDENTIFIER 0x103 2892 2893 #define FDMI_SMARTSAN_SERVICE 0xF100 2894 #define FDMI_SMARTSAN_GUID 0xF101 2895 #define FDMI_SMARTSAN_VERSION 0xF102 2896 #define FDMI_SMARTSAN_PROD_NAME 0xF103 2897 #define FDMI_SMARTSAN_PORT_INFO 0xF104 2898 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105 2899 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106 2900 2901 #define FDMI_PORT_SPEED_1GB 0x1 2902 #define FDMI_PORT_SPEED_2GB 0x2 2903 #define FDMI_PORT_SPEED_10GB 0x4 2904 #define FDMI_PORT_SPEED_4GB 0x8 2905 #define FDMI_PORT_SPEED_8GB 0x10 2906 #define FDMI_PORT_SPEED_16GB 0x20 2907 #define FDMI_PORT_SPEED_32GB 0x40 2908 #define FDMI_PORT_SPEED_20GB 0x80 2909 #define FDMI_PORT_SPEED_40GB 0x100 2910 #define FDMI_PORT_SPEED_128GB 0x200 2911 #define FDMI_PORT_SPEED_64GB 0x400 2912 #define FDMI_PORT_SPEED_256GB 0x800 2913 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2914 2915 #define FC_CLASS_2 0x04 2916 #define FC_CLASS_3 0x08 2917 #define FC_CLASS_2_3 0x0C 2918 2919 struct ct_fdmi_port_attr { 2920 __be16 type; 2921 __be16 len; 2922 union { 2923 uint8_t fc4_types[32]; 2924 __be32 sup_speed; 2925 __be32 cur_speed; 2926 __be32 max_frame_size; 2927 uint8_t os_dev_name[32]; 2928 uint8_t host_name[256]; 2929 2930 uint8_t node_name[WWN_SIZE]; 2931 uint8_t port_name[WWN_SIZE]; 2932 uint8_t port_sym_name[128]; 2933 __be32 port_type; 2934 __be32 port_supported_cos; 2935 uint8_t fabric_name[WWN_SIZE]; 2936 uint8_t port_fc4_type[32]; 2937 __be32 port_state; 2938 __be32 num_ports; 2939 __be32 port_id; 2940 2941 uint8_t smartsan_service[24]; 2942 uint8_t smartsan_guid[16]; 2943 uint8_t smartsan_version[24]; 2944 uint8_t smartsan_prod_name[16]; 2945 __be32 smartsan_port_info; 2946 __be32 smartsan_qos_support; 2947 __be32 smartsan_security_support; 2948 } a; 2949 }; 2950 2951 struct ct_fdmi1_port_attributes { 2952 __be32 count; 2953 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT]; 2954 }; 2955 2956 struct ct_fdmi2_port_attributes { 2957 __be32 count; 2958 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT]; 2959 }; 2960 2961 #define FDMI_ATTR_TYPELEN(obj) \ 2962 (sizeof((obj)->type) + sizeof((obj)->len)) 2963 2964 #define FDMI_ATTR_ALIGNMENT(len) \ 2965 (4 - ((len) & 3)) 2966 2967 /* FDMI register call options */ 2968 #define CALLOPT_FDMI1 0 2969 #define CALLOPT_FDMI2 1 2970 #define CALLOPT_FDMI2_SMARTSAN 2 2971 2972 /* FDMI definitions. */ 2973 #define GRHL_CMD 0x100 2974 #define GHAT_CMD 0x101 2975 #define GRPL_CMD 0x102 2976 #define GPAT_CMD 0x110 2977 2978 #define RHBA_CMD 0x200 2979 #define RHBA_RSP_SIZE 16 2980 2981 #define RHAT_CMD 0x201 2982 2983 #define RPRT_CMD 0x210 2984 #define RPRT_RSP_SIZE 24 2985 2986 #define RPA_CMD 0x211 2987 #define RPA_RSP_SIZE 16 2988 #define SMARTSAN_RPA_RSP_SIZE 24 2989 2990 #define DHBA_CMD 0x300 2991 #define DHBA_REQ_SIZE (16 + 8) 2992 #define DHBA_RSP_SIZE 16 2993 2994 #define DHAT_CMD 0x301 2995 #define DPRT_CMD 0x310 2996 #define DPA_CMD 0x311 2997 2998 /* CT command header -- request/response common fields */ 2999 struct ct_cmd_hdr { 3000 uint8_t revision; 3001 uint8_t in_id[3]; 3002 uint8_t gs_type; 3003 uint8_t gs_subtype; 3004 uint8_t options; 3005 uint8_t reserved; 3006 }; 3007 3008 /* CT command request */ 3009 struct ct_sns_req { 3010 struct ct_cmd_hdr header; 3011 __be16 command; 3012 __be16 max_rsp_size; 3013 uint8_t fragment_id; 3014 uint8_t reserved[3]; 3015 3016 union { 3017 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 3018 struct { 3019 uint8_t reserved; 3020 be_id_t port_id; 3021 } port_id; 3022 3023 struct { 3024 uint8_t reserved; 3025 uint8_t domain; 3026 uint8_t area; 3027 uint8_t port_type; 3028 } gpn_ft; 3029 3030 struct { 3031 uint8_t port_type; 3032 uint8_t domain; 3033 uint8_t area; 3034 uint8_t reserved; 3035 } gid_pt; 3036 3037 struct { 3038 uint8_t reserved; 3039 be_id_t port_id; 3040 uint8_t fc4_types[32]; 3041 } rft_id; 3042 3043 struct { 3044 uint8_t reserved; 3045 be_id_t port_id; 3046 uint16_t reserved2; 3047 uint8_t fc4_feature; 3048 uint8_t fc4_type; 3049 } rff_id; 3050 3051 struct { 3052 uint8_t reserved; 3053 be_id_t port_id; 3054 uint8_t node_name[8]; 3055 } rnn_id; 3056 3057 struct { 3058 uint8_t node_name[8]; 3059 uint8_t name_len; 3060 uint8_t sym_node_name[255]; 3061 } rsnn_nn; 3062 3063 struct { 3064 uint8_t hba_identifier[8]; 3065 } ghat; 3066 3067 struct { 3068 uint8_t hba_identifier[8]; 3069 __be32 entry_count; 3070 uint8_t port_name[8]; 3071 struct ct_fdmi2_hba_attributes attrs; 3072 } rhba; 3073 3074 struct { 3075 uint8_t hba_identifier[8]; 3076 struct ct_fdmi1_hba_attributes attrs; 3077 } rhat; 3078 3079 struct { 3080 uint8_t port_name[8]; 3081 struct ct_fdmi2_port_attributes attrs; 3082 } rpa; 3083 3084 struct { 3085 uint8_t hba_identifier[8]; 3086 uint8_t port_name[8]; 3087 struct ct_fdmi2_port_attributes attrs; 3088 } rprt; 3089 3090 struct { 3091 uint8_t port_name[8]; 3092 } dhba; 3093 3094 struct { 3095 uint8_t port_name[8]; 3096 } dhat; 3097 3098 struct { 3099 uint8_t port_name[8]; 3100 } dprt; 3101 3102 struct { 3103 uint8_t port_name[8]; 3104 } dpa; 3105 3106 struct { 3107 uint8_t port_name[8]; 3108 } gpsc; 3109 3110 struct { 3111 uint8_t reserved; 3112 uint8_t port_id[3]; 3113 } gff_id; 3114 3115 struct { 3116 uint8_t port_name[8]; 3117 } gid_pn; 3118 } req; 3119 }; 3120 3121 /* CT command response header */ 3122 struct ct_rsp_hdr { 3123 struct ct_cmd_hdr header; 3124 __be16 response; 3125 uint16_t residual; 3126 uint8_t fragment_id; 3127 uint8_t reason_code; 3128 uint8_t explanation_code; 3129 uint8_t vendor_unique; 3130 }; 3131 3132 struct ct_sns_gid_pt_data { 3133 uint8_t control_byte; 3134 be_id_t port_id; 3135 }; 3136 3137 /* It's the same for both GPN_FT and GNN_FT */ 3138 struct ct_sns_gpnft_rsp { 3139 struct { 3140 struct ct_cmd_hdr header; 3141 uint16_t response; 3142 uint16_t residual; 3143 uint8_t fragment_id; 3144 uint8_t reason_code; 3145 uint8_t explanation_code; 3146 uint8_t vendor_unique; 3147 }; 3148 /* Assume the largest number of targets for the union */ 3149 struct ct_sns_gpn_ft_data { 3150 u8 control_byte; 3151 u8 port_id[3]; 3152 u32 reserved; 3153 u8 port_name[8]; 3154 } entries[1]; 3155 }; 3156 3157 /* CT command response */ 3158 struct ct_sns_rsp { 3159 struct ct_rsp_hdr header; 3160 3161 union { 3162 struct { 3163 uint8_t port_type; 3164 be_id_t port_id; 3165 uint8_t port_name[8]; 3166 uint8_t sym_port_name_len; 3167 uint8_t sym_port_name[255]; 3168 uint8_t node_name[8]; 3169 uint8_t sym_node_name_len; 3170 uint8_t sym_node_name[255]; 3171 uint8_t init_proc_assoc[8]; 3172 uint8_t node_ip_addr[16]; 3173 uint8_t class_of_service[4]; 3174 uint8_t fc4_types[32]; 3175 uint8_t ip_address[16]; 3176 uint8_t fabric_port_name[8]; 3177 uint8_t reserved; 3178 uint8_t hard_address[3]; 3179 } ga_nxt; 3180 3181 struct { 3182 /* Assume the largest number of targets for the union */ 3183 struct ct_sns_gid_pt_data 3184 entries[MAX_FIBRE_DEVICES_MAX]; 3185 } gid_pt; 3186 3187 struct { 3188 uint8_t port_name[8]; 3189 } gpn_id; 3190 3191 struct { 3192 uint8_t node_name[8]; 3193 } gnn_id; 3194 3195 struct { 3196 uint8_t fc4_types[32]; 3197 } gft_id; 3198 3199 struct { 3200 uint32_t entry_count; 3201 uint8_t port_name[8]; 3202 struct ct_fdmi1_hba_attributes attrs; 3203 } ghat; 3204 3205 struct { 3206 uint8_t port_name[8]; 3207 } gfpn_id; 3208 3209 struct { 3210 __be16 speeds; 3211 __be16 speed; 3212 } gpsc; 3213 3214 #define GFF_FCP_SCSI_OFFSET 7 3215 #define GFF_NVME_OFFSET 23 /* type = 28h */ 3216 struct { 3217 uint8_t fc4_features[128]; 3218 #define FC4_FF_TARGET BIT_0 3219 #define FC4_FF_INITIATOR BIT_1 3220 } gff_id; 3221 struct { 3222 uint8_t reserved; 3223 uint8_t port_id[3]; 3224 } gid_pn; 3225 } rsp; 3226 }; 3227 3228 struct ct_sns_pkt { 3229 union { 3230 struct ct_sns_req req; 3231 struct ct_sns_rsp rsp; 3232 } p; 3233 }; 3234 3235 struct ct_sns_gpnft_pkt { 3236 union { 3237 struct ct_sns_req req; 3238 struct ct_sns_gpnft_rsp rsp; 3239 } p; 3240 }; 3241 3242 enum scan_flags_t { 3243 SF_SCANNING = BIT_0, 3244 SF_QUEUED = BIT_1, 3245 }; 3246 3247 enum fc4type_t { 3248 FS_FC4TYPE_FCP = BIT_0, 3249 FS_FC4TYPE_NVME = BIT_1, 3250 FS_FCP_IS_N2N = BIT_7, 3251 }; 3252 3253 struct fab_scan_rp { 3254 port_id_t id; 3255 enum fc4type_t fc4type; 3256 u8 port_name[8]; 3257 u8 node_name[8]; 3258 }; 3259 3260 struct fab_scan { 3261 struct fab_scan_rp *l; 3262 u32 size; 3263 u16 scan_retry; 3264 #define MAX_SCAN_RETRIES 5 3265 enum scan_flags_t scan_flags; 3266 struct delayed_work scan_work; 3267 }; 3268 3269 /* 3270 * SNS command structures -- for 2200 compatibility. 3271 */ 3272 #define RFT_ID_SNS_SCMD_LEN 22 3273 #define RFT_ID_SNS_CMD_SIZE 60 3274 #define RFT_ID_SNS_DATA_SIZE 16 3275 3276 #define RNN_ID_SNS_SCMD_LEN 10 3277 #define RNN_ID_SNS_CMD_SIZE 36 3278 #define RNN_ID_SNS_DATA_SIZE 16 3279 3280 #define GA_NXT_SNS_SCMD_LEN 6 3281 #define GA_NXT_SNS_CMD_SIZE 28 3282 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 3283 3284 #define GID_PT_SNS_SCMD_LEN 6 3285 #define GID_PT_SNS_CMD_SIZE 28 3286 /* 3287 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 3288 * adapters. 3289 */ 3290 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 3291 3292 #define GPN_ID_SNS_SCMD_LEN 6 3293 #define GPN_ID_SNS_CMD_SIZE 28 3294 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 3295 3296 #define GNN_ID_SNS_SCMD_LEN 6 3297 #define GNN_ID_SNS_CMD_SIZE 28 3298 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 3299 3300 struct sns_cmd_pkt { 3301 union { 3302 struct { 3303 __le16 buffer_length; 3304 __le16 reserved_1; 3305 __le64 buffer_address __packed; 3306 __le16 subcommand_length; 3307 __le16 reserved_2; 3308 __le16 subcommand; 3309 __le16 size; 3310 uint32_t reserved_3; 3311 uint8_t param[36]; 3312 } cmd; 3313 3314 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 3315 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 3316 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 3317 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 3318 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 3319 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 3320 } p; 3321 }; 3322 3323 struct fw_blob { 3324 char *name; 3325 uint32_t segs[4]; 3326 const struct firmware *fw; 3327 }; 3328 3329 /* Return data from MBC_GET_ID_LIST call. */ 3330 struct gid_list_info { 3331 uint8_t al_pa; 3332 uint8_t area; 3333 uint8_t domain; 3334 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 3335 __le16 loop_id; /* ISP23XX -- 6 bytes. */ 3336 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 3337 }; 3338 3339 /* NPIV */ 3340 typedef struct vport_info { 3341 uint8_t port_name[WWN_SIZE]; 3342 uint8_t node_name[WWN_SIZE]; 3343 int vp_id; 3344 uint16_t loop_id; 3345 unsigned long host_no; 3346 uint8_t port_id[3]; 3347 int loop_state; 3348 } vport_info_t; 3349 3350 typedef struct vport_params { 3351 uint8_t port_name[WWN_SIZE]; 3352 uint8_t node_name[WWN_SIZE]; 3353 uint32_t options; 3354 #define VP_OPTS_RETRY_ENABLE BIT_0 3355 #define VP_OPTS_VP_DISABLE BIT_1 3356 } vport_params_t; 3357 3358 /* NPIV - return codes of VP create and modify */ 3359 #define VP_RET_CODE_OK 0 3360 #define VP_RET_CODE_FATAL 1 3361 #define VP_RET_CODE_WRONG_ID 2 3362 #define VP_RET_CODE_WWPN 3 3363 #define VP_RET_CODE_RESOURCES 4 3364 #define VP_RET_CODE_NO_MEM 5 3365 #define VP_RET_CODE_NOT_FOUND 6 3366 3367 struct qla_hw_data; 3368 struct rsp_que; 3369 /* 3370 * ISP operations 3371 */ 3372 struct isp_operations { 3373 3374 int (*pci_config) (struct scsi_qla_host *); 3375 int (*reset_chip)(struct scsi_qla_host *); 3376 int (*chip_diag) (struct scsi_qla_host *); 3377 void (*config_rings) (struct scsi_qla_host *); 3378 int (*reset_adapter)(struct scsi_qla_host *); 3379 int (*nvram_config) (struct scsi_qla_host *); 3380 void (*update_fw_options) (struct scsi_qla_host *); 3381 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3382 3383 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t); 3384 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3385 3386 irq_handler_t intr_handler; 3387 void (*enable_intrs) (struct qla_hw_data *); 3388 void (*disable_intrs) (struct qla_hw_data *); 3389 3390 int (*abort_command) (srb_t *); 3391 int (*target_reset) (struct fc_port *, uint64_t, int); 3392 int (*lun_reset) (struct fc_port *, uint64_t, int); 3393 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3394 uint8_t, uint8_t, uint16_t *, uint8_t); 3395 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3396 uint8_t, uint8_t); 3397 3398 uint16_t (*calc_req_entries) (uint16_t); 3399 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3400 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3401 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3402 uint32_t); 3403 3404 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *, 3405 uint32_t, uint32_t); 3406 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t, 3407 uint32_t); 3408 3409 void (*fw_dump)(struct scsi_qla_host *vha); 3410 void (*mpi_fw_dump)(struct scsi_qla_host *, int); 3411 3412 /* Context: task, might sleep */ 3413 int (*beacon_on) (struct scsi_qla_host *); 3414 int (*beacon_off) (struct scsi_qla_host *); 3415 3416 void (*beacon_blink) (struct scsi_qla_host *); 3417 3418 void *(*read_optrom)(struct scsi_qla_host *, void *, 3419 uint32_t, uint32_t); 3420 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t, 3421 uint32_t); 3422 3423 int (*get_flash_version) (struct scsi_qla_host *, void *); 3424 int (*start_scsi) (srb_t *); 3425 int (*start_scsi_mq) (srb_t *); 3426 3427 /* Context: task, might sleep */ 3428 int (*abort_isp) (struct scsi_qla_host *); 3429 3430 int (*iospace_config)(struct qla_hw_data *); 3431 int (*initialize_adapter)(struct scsi_qla_host *); 3432 }; 3433 3434 /* MSI-X Support *************************************************************/ 3435 3436 #define QLA_MSIX_CHIP_REV_24XX 3 3437 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3438 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3439 3440 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3441 #define QLA_MSIX_RSP_Q 0x01 3442 #define QLA_ATIO_VECTOR 0x02 3443 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3444 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04 3445 3446 #define QLA_MIDX_DEFAULT 0 3447 #define QLA_MIDX_RSP_Q 1 3448 #define QLA_PCI_MSIX_CONTROL 0xa2 3449 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3450 3451 struct scsi_qla_host; 3452 3453 3454 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3455 3456 struct qla_msix_entry { 3457 int have_irq; 3458 int in_use; 3459 uint32_t vector; 3460 uint16_t entry; 3461 char name[30]; 3462 void *handle; 3463 int cpuid; 3464 }; 3465 3466 #define WATCH_INTERVAL 1 /* number of seconds */ 3467 3468 /* Work events. */ 3469 enum qla_work_type { 3470 QLA_EVT_AEN, 3471 QLA_EVT_IDC_ACK, 3472 QLA_EVT_ASYNC_LOGIN, 3473 QLA_EVT_ASYNC_LOGOUT, 3474 QLA_EVT_ASYNC_ADISC, 3475 QLA_EVT_UEVENT, 3476 QLA_EVT_AENFX, 3477 QLA_EVT_GPNID, 3478 QLA_EVT_UNMAP, 3479 QLA_EVT_NEW_SESS, 3480 QLA_EVT_GPDB, 3481 QLA_EVT_PRLI, 3482 QLA_EVT_GPSC, 3483 QLA_EVT_GNL, 3484 QLA_EVT_NACK, 3485 QLA_EVT_RELOGIN, 3486 QLA_EVT_ASYNC_PRLO, 3487 QLA_EVT_ASYNC_PRLO_DONE, 3488 QLA_EVT_GPNFT, 3489 QLA_EVT_GPNFT_DONE, 3490 QLA_EVT_GNNFT_DONE, 3491 QLA_EVT_GNNID, 3492 QLA_EVT_GFPNID, 3493 QLA_EVT_SP_RETRY, 3494 QLA_EVT_IIDMA, 3495 QLA_EVT_ELS_PLOGI, 3496 QLA_EVT_SA_REPLACE, 3497 }; 3498 3499 3500 struct qla_work_evt { 3501 struct list_head list; 3502 enum qla_work_type type; 3503 u32 flags; 3504 #define QLA_EVT_FLAG_FREE 0x1 3505 3506 union { 3507 struct { 3508 enum fc_host_event_code code; 3509 u32 data; 3510 } aen; 3511 struct { 3512 #define QLA_IDC_ACK_REGS 7 3513 uint16_t mb[QLA_IDC_ACK_REGS]; 3514 } idc_ack; 3515 struct { 3516 struct fc_port *fcport; 3517 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3518 u16 data[2]; 3519 } logio; 3520 struct { 3521 u32 code; 3522 #define QLA_UEVENT_CODE_FW_DUMP 0 3523 } uevent; 3524 struct { 3525 uint32_t evtcode; 3526 uint32_t mbx[8]; 3527 uint32_t count; 3528 } aenfx; 3529 struct { 3530 srb_t *sp; 3531 } iosb; 3532 struct { 3533 port_id_t id; 3534 } gpnid; 3535 struct { 3536 port_id_t id; 3537 u8 port_name[8]; 3538 u8 node_name[8]; 3539 void *pla; 3540 u8 fc4_type; 3541 } new_sess; 3542 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */ 3543 fc_port_t *fcport; 3544 u8 opt; 3545 } fcport; 3546 struct { 3547 fc_port_t *fcport; 3548 u8 iocb[IOCB_SIZE]; 3549 int type; 3550 } nack; 3551 struct { 3552 u8 fc4_type; 3553 srb_t *sp; 3554 } gpnft; 3555 struct { 3556 struct edif_sa_ctl *sa_ctl; 3557 fc_port_t *fcport; 3558 uint16_t nport_handle; 3559 } sa_update; 3560 } u; 3561 }; 3562 3563 struct qla_chip_state_84xx { 3564 struct list_head list; 3565 struct kref kref; 3566 3567 void *bus; 3568 spinlock_t access_lock; 3569 struct mutex fw_update_mutex; 3570 uint32_t fw_update; 3571 uint32_t op_fw_version; 3572 uint32_t op_fw_size; 3573 uint32_t op_fw_seq_size; 3574 uint32_t diag_fw_version; 3575 uint32_t gold_fw_version; 3576 }; 3577 3578 struct qla_dif_statistics { 3579 uint64_t dif_input_bytes; 3580 uint64_t dif_output_bytes; 3581 uint64_t dif_input_requests; 3582 uint64_t dif_output_requests; 3583 uint32_t dif_guard_err; 3584 uint32_t dif_ref_tag_err; 3585 uint32_t dif_app_tag_err; 3586 }; 3587 3588 struct qla_statistics { 3589 uint32_t total_isp_aborts; 3590 uint64_t input_bytes; 3591 uint64_t output_bytes; 3592 uint64_t input_requests; 3593 uint64_t output_requests; 3594 uint32_t control_requests; 3595 3596 uint64_t jiffies_at_last_reset; 3597 uint32_t stat_max_pend_cmds; 3598 uint32_t stat_max_qfull_cmds_alloc; 3599 uint32_t stat_max_qfull_cmds_dropped; 3600 3601 struct qla_dif_statistics qla_dif_stats; 3602 }; 3603 3604 struct bidi_statistics { 3605 unsigned long long io_count; 3606 unsigned long long transfer_bytes; 3607 }; 3608 3609 struct qla_tc_param { 3610 struct scsi_qla_host *vha; 3611 uint32_t blk_sz; 3612 uint32_t bufflen; 3613 struct scatterlist *sg; 3614 struct scatterlist *prot_sg; 3615 struct crc_context *ctx; 3616 uint8_t *ctx_dsd_alloced; 3617 }; 3618 3619 /* Multi queue support */ 3620 #define MBC_INITIALIZE_MULTIQ 0x1f 3621 #define QLA_QUE_PAGE 0X1000 3622 #define QLA_MQ_SIZE 32 3623 #define QLA_MAX_QUEUES 256 3624 #define ISP_QUE_REG(ha, id) \ 3625 ((ha->mqenable || IS_QLA83XX(ha) || \ 3626 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \ 3627 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3628 ((void __iomem *)ha->iobase)) 3629 #define QLA_REQ_QUE_ID(tag) \ 3630 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3631 #define QLA_DEFAULT_QUE_QOS 5 3632 #define QLA_PRECONFIG_VPORTS 32 3633 #define QLA_MAX_VPORTS_QLA24XX 128 3634 #define QLA_MAX_VPORTS_QLA25XX 256 3635 3636 struct qla_tgt_counters { 3637 uint64_t qla_core_sbt_cmd; 3638 uint64_t core_qla_que_buf; 3639 uint64_t qla_core_ret_ctio; 3640 uint64_t core_qla_snd_status; 3641 uint64_t qla_core_ret_sta_ctio; 3642 uint64_t core_qla_free_cmd; 3643 uint64_t num_q_full_sent; 3644 uint64_t num_alloc_iocb_failed; 3645 uint64_t num_term_xchg_sent; 3646 }; 3647 3648 struct qla_counters { 3649 uint64_t input_bytes; 3650 uint64_t input_requests; 3651 uint64_t output_bytes; 3652 uint64_t output_requests; 3653 3654 }; 3655 3656 struct qla_qpair; 3657 3658 /* Response queue data structure */ 3659 struct rsp_que { 3660 dma_addr_t dma; 3661 response_t *ring; 3662 response_t *ring_ptr; 3663 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */ 3664 __le32 __iomem *rsp_q_out; 3665 uint16_t ring_index; 3666 uint16_t out_ptr; 3667 uint16_t *in_ptr; /* queue shadow in index */ 3668 uint16_t length; 3669 uint16_t options; 3670 uint16_t rid; 3671 uint16_t id; 3672 uint16_t vp_idx; 3673 struct qla_hw_data *hw; 3674 struct qla_msix_entry *msix; 3675 struct req_que *req; 3676 srb_t *status_srb; /* status continuation entry */ 3677 struct qla_qpair *qpair; 3678 3679 dma_addr_t dma_fx00; 3680 response_t *ring_fx00; 3681 uint16_t length_fx00; 3682 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3683 }; 3684 3685 /* Request queue data structure */ 3686 struct req_que { 3687 dma_addr_t dma; 3688 request_t *ring; 3689 request_t *ring_ptr; 3690 __le32 __iomem *req_q_in; /* FWI2-capable only. */ 3691 __le32 __iomem *req_q_out; 3692 uint16_t ring_index; 3693 uint16_t in_ptr; 3694 uint16_t *out_ptr; /* queue shadow out index */ 3695 uint16_t cnt; 3696 uint16_t length; 3697 uint16_t options; 3698 uint16_t rid; 3699 uint16_t id; 3700 uint16_t qos; 3701 uint16_t vp_idx; 3702 struct rsp_que *rsp; 3703 srb_t **outstanding_cmds; 3704 uint32_t current_outstanding_cmd; 3705 uint16_t num_outstanding_cmds; 3706 int max_q_depth; 3707 3708 dma_addr_t dma_fx00; 3709 request_t *ring_fx00; 3710 uint16_t length_fx00; 3711 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3712 }; 3713 3714 struct qla_fw_resources { 3715 u16 iocbs_total; 3716 u16 iocbs_limit; 3717 u16 iocbs_qp_limit; 3718 u16 iocbs_used; 3719 }; 3720 3721 #define QLA_IOCB_PCT_LIMIT 95 3722 3723 /*Queue pair data structure */ 3724 struct qla_qpair { 3725 spinlock_t qp_lock; 3726 atomic_t ref_count; 3727 uint32_t lun_cnt; 3728 /* 3729 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3730 * legacy code. For other Qpair(s), it will point at qp_lock. 3731 */ 3732 spinlock_t *qp_lock_ptr; 3733 struct scsi_qla_host *vha; 3734 u32 chip_reset; 3735 3736 /* distill these fields down to 'online=0/1' 3737 * ha->flags.eeh_busy 3738 * ha->flags.pci_channel_io_perm_failure 3739 * base_vha->loop_state 3740 */ 3741 uint32_t online:1; 3742 /* move vha->flags.difdix_supported here */ 3743 uint32_t difdix_supported:1; 3744 uint32_t delete_in_progress:1; 3745 uint32_t fw_started:1; 3746 uint32_t enable_class_2:1; 3747 uint32_t enable_explicit_conf:1; 3748 uint32_t use_shadow_reg:1; 3749 uint32_t rcv_intr:1; 3750 3751 uint16_t id; /* qp number used with FW */ 3752 uint16_t vp_idx; /* vport ID */ 3753 mempool_t *srb_mempool; 3754 3755 struct pci_dev *pdev; 3756 void (*reqq_start_iocbs)(struct qla_qpair *); 3757 3758 /* to do: New driver: move queues to here instead of pointers */ 3759 struct req_que *req; 3760 struct rsp_que *rsp; 3761 struct atio_que *atio; 3762 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3763 struct qla_hw_data *hw; 3764 struct work_struct q_work; 3765 struct qla_counters counters; 3766 3767 struct list_head qp_list_elem; /* vha->qp_list */ 3768 struct list_head hints_list; 3769 3770 uint16_t retry_term_cnt; 3771 __le32 retry_term_exchg_addr; 3772 uint64_t retry_term_jiff; 3773 struct qla_tgt_counters tgt_counters; 3774 uint16_t cpuid; 3775 struct qla_fw_resources fwres ____cacheline_aligned; 3776 u32 cmd_cnt; 3777 u32 cmd_completion_cnt; 3778 u32 prev_completion_cnt; 3779 }; 3780 3781 /* Place holder for FW buffer parameters */ 3782 struct qlfc_fw { 3783 void *fw_buf; 3784 dma_addr_t fw_dma; 3785 uint32_t len; 3786 }; 3787 3788 struct rdp_req_payload { 3789 uint32_t els_request; 3790 uint32_t desc_list_len; 3791 3792 /* NPIV descriptor */ 3793 struct { 3794 uint32_t desc_tag; 3795 uint32_t desc_len; 3796 uint8_t reserved; 3797 uint8_t nport_id[3]; 3798 } npiv_desc; 3799 }; 3800 3801 struct rdp_rsp_payload { 3802 struct { 3803 __be32 cmd; 3804 __be32 len; 3805 } hdr; 3806 3807 /* LS Request Info descriptor */ 3808 struct { 3809 __be32 desc_tag; 3810 __be32 desc_len; 3811 __be32 req_payload_word_0; 3812 } ls_req_info_desc; 3813 3814 /* LS Request Info descriptor */ 3815 struct { 3816 __be32 desc_tag; 3817 __be32 desc_len; 3818 __be32 req_payload_word_0; 3819 } ls_req_info_desc2; 3820 3821 /* SFP diagnostic param descriptor */ 3822 struct { 3823 __be32 desc_tag; 3824 __be32 desc_len; 3825 __be16 temperature; 3826 __be16 vcc; 3827 __be16 tx_bias; 3828 __be16 tx_power; 3829 __be16 rx_power; 3830 __be16 sfp_flags; 3831 } sfp_diag_desc; 3832 3833 /* Port Speed Descriptor */ 3834 struct { 3835 __be32 desc_tag; 3836 __be32 desc_len; 3837 __be16 speed_capab; 3838 __be16 operating_speed; 3839 } port_speed_desc; 3840 3841 /* Link Error Status Descriptor */ 3842 struct { 3843 __be32 desc_tag; 3844 __be32 desc_len; 3845 __be32 link_fail_cnt; 3846 __be32 loss_sync_cnt; 3847 __be32 loss_sig_cnt; 3848 __be32 prim_seq_err_cnt; 3849 __be32 inval_xmit_word_cnt; 3850 __be32 inval_crc_cnt; 3851 uint8_t pn_port_phy_type; 3852 uint8_t reserved[3]; 3853 } ls_err_desc; 3854 3855 /* Port name description with diag param */ 3856 struct { 3857 __be32 desc_tag; 3858 __be32 desc_len; 3859 uint8_t WWNN[WWN_SIZE]; 3860 uint8_t WWPN[WWN_SIZE]; 3861 } port_name_diag_desc; 3862 3863 /* Port Name desc for Direct attached Fx_Port or Nx_Port */ 3864 struct { 3865 __be32 desc_tag; 3866 __be32 desc_len; 3867 uint8_t WWNN[WWN_SIZE]; 3868 uint8_t WWPN[WWN_SIZE]; 3869 } port_name_direct_desc; 3870 3871 /* Buffer Credit descriptor */ 3872 struct { 3873 __be32 desc_tag; 3874 __be32 desc_len; 3875 __be32 fcport_b2b; 3876 __be32 attached_fcport_b2b; 3877 __be32 fcport_rtt; 3878 } buffer_credit_desc; 3879 3880 /* Optical Element Data Descriptor */ 3881 struct { 3882 __be32 desc_tag; 3883 __be32 desc_len; 3884 __be16 high_alarm; 3885 __be16 low_alarm; 3886 __be16 high_warn; 3887 __be16 low_warn; 3888 __be32 element_flags; 3889 } optical_elmt_desc[5]; 3890 3891 /* Optical Product Data Descriptor */ 3892 struct { 3893 __be32 desc_tag; 3894 __be32 desc_len; 3895 uint8_t vendor_name[16]; 3896 uint8_t part_number[16]; 3897 uint8_t serial_number[16]; 3898 uint8_t revision[4]; 3899 uint8_t date[8]; 3900 } optical_prod_desc; 3901 }; 3902 3903 #define RDP_DESC_LEN(obj) \ 3904 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len)) 3905 3906 #define RDP_PORT_SPEED_1GB BIT_15 3907 #define RDP_PORT_SPEED_2GB BIT_14 3908 #define RDP_PORT_SPEED_4GB BIT_13 3909 #define RDP_PORT_SPEED_10GB BIT_12 3910 #define RDP_PORT_SPEED_8GB BIT_11 3911 #define RDP_PORT_SPEED_16GB BIT_10 3912 #define RDP_PORT_SPEED_32GB BIT_9 3913 #define RDP_PORT_SPEED_64GB BIT_8 3914 #define RDP_PORT_SPEED_UNKNOWN BIT_0 3915 3916 struct scsi_qlt_host { 3917 void *target_lport_ptr; 3918 struct mutex tgt_mutex; 3919 struct mutex tgt_host_action_mutex; 3920 struct qla_tgt *qla_tgt; 3921 }; 3922 3923 struct qlt_hw_data { 3924 /* Protected by hw lock */ 3925 uint32_t node_name_set:1; 3926 3927 dma_addr_t atio_dma; /* Physical address. */ 3928 struct atio *atio_ring; /* Base virtual address */ 3929 struct atio *atio_ring_ptr; /* Current address. */ 3930 uint16_t atio_ring_index; /* Current index. */ 3931 uint16_t atio_q_length; 3932 __le32 __iomem *atio_q_in; 3933 __le32 __iomem *atio_q_out; 3934 3935 const struct qla_tgt_func_tmpl *tgt_ops; 3936 struct qla_tgt_vp_map *tgt_vp_map; 3937 3938 int saved_set; 3939 __le16 saved_exchange_count; 3940 __le32 saved_firmware_options_1; 3941 __le32 saved_firmware_options_2; 3942 __le32 saved_firmware_options_3; 3943 uint8_t saved_firmware_options[2]; 3944 uint8_t saved_add_firmware_options[2]; 3945 3946 uint8_t tgt_node_name[WWN_SIZE]; 3947 3948 struct dentry *dfs_tgt_sess; 3949 struct dentry *dfs_tgt_port_database; 3950 struct dentry *dfs_naqp; 3951 3952 struct list_head q_full_list; 3953 uint32_t num_pend_cmds; 3954 uint32_t num_qfull_cmds_alloc; 3955 uint32_t num_qfull_cmds_dropped; 3956 spinlock_t q_full_lock; 3957 uint32_t leak_exchg_thresh_hold; 3958 spinlock_t sess_lock; 3959 int num_act_qpairs; 3960 #define DEFAULT_NAQP 2 3961 spinlock_t atio_lock ____cacheline_aligned; 3962 }; 3963 3964 #define MAX_QFULL_CMDS_ALLOC 8192 3965 #define Q_FULL_THRESH_HOLD_PERCENT 90 3966 #define Q_FULL_THRESH_HOLD(ha) \ 3967 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 3968 3969 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 3970 3971 struct qla_hw_data_stat { 3972 u32 num_fw_dump; 3973 u32 num_mpi_reset; 3974 }; 3975 3976 /* refer to pcie_do_recovery reference */ 3977 typedef enum { 3978 QLA_PCI_RESUME, 3979 QLA_PCI_ERR_DETECTED, 3980 QLA_PCI_MMIO_ENABLED, 3981 QLA_PCI_SLOT_RESET, 3982 } pci_error_state_t; 3983 /* 3984 * Qlogic host adapter specific data structure. 3985 */ 3986 struct qla_hw_data { 3987 struct pci_dev *pdev; 3988 /* SRB cache. */ 3989 #define SRB_MIN_REQ 128 3990 mempool_t *srb_mempool; 3991 u8 port_name[WWN_SIZE]; 3992 3993 volatile struct { 3994 uint32_t mbox_int :1; 3995 uint32_t mbox_busy :1; 3996 uint32_t disable_risc_code_load :1; 3997 uint32_t enable_64bit_addressing :1; 3998 uint32_t enable_lip_reset :1; 3999 uint32_t enable_target_reset :1; 4000 uint32_t enable_lip_full_login :1; 4001 uint32_t enable_led_scheme :1; 4002 4003 uint32_t msi_enabled :1; 4004 uint32_t msix_enabled :1; 4005 uint32_t disable_serdes :1; 4006 uint32_t gpsc_supported :1; 4007 uint32_t npiv_supported :1; 4008 uint32_t pci_channel_io_perm_failure :1; 4009 uint32_t fce_enabled :1; 4010 uint32_t fac_supported :1; 4011 4012 uint32_t chip_reset_done :1; 4013 uint32_t running_gold_fw :1; 4014 uint32_t eeh_busy :1; 4015 uint32_t disable_msix_handshake :1; 4016 uint32_t fcp_prio_enabled :1; 4017 uint32_t isp82xx_fw_hung:1; 4018 uint32_t nic_core_hung:1; 4019 4020 uint32_t quiesce_owner:1; 4021 uint32_t nic_core_reset_hdlr_active:1; 4022 uint32_t nic_core_reset_owner:1; 4023 uint32_t isp82xx_no_md_cap:1; 4024 uint32_t host_shutting_down:1; 4025 uint32_t idc_compl_status:1; 4026 uint32_t mr_reset_hdlr_active:1; 4027 uint32_t mr_intr_valid:1; 4028 4029 uint32_t dport_enabled:1; 4030 uint32_t fawwpn_enabled:1; 4031 uint32_t exlogins_enabled:1; 4032 uint32_t exchoffld_enabled:1; 4033 4034 uint32_t lip_ae:1; 4035 uint32_t n2n_ae:1; 4036 uint32_t fw_started:1; 4037 uint32_t fw_init_done:1; 4038 4039 uint32_t lr_detected:1; 4040 4041 uint32_t rida_fmt2:1; 4042 uint32_t purge_mbox:1; 4043 uint32_t n2n_bigger:1; 4044 uint32_t secure_adapter:1; 4045 uint32_t secure_fw:1; 4046 /* Supported by Adapter */ 4047 uint32_t scm_supported_a:1; 4048 /* Supported by Firmware */ 4049 uint32_t scm_supported_f:1; 4050 /* Enabled in Driver */ 4051 uint32_t scm_enabled:1; 4052 uint32_t edif_hw:1; 4053 uint32_t edif_enabled:1; 4054 uint32_t n2n_fw_acc_sec:1; 4055 uint32_t plogi_template_valid:1; 4056 uint32_t port_isolated:1; 4057 uint32_t eeh_flush:2; 4058 #define EEH_FLUSH_RDY 1 4059 #define EEH_FLUSH_DONE 2 4060 } flags; 4061 4062 uint16_t max_exchg; 4063 uint16_t lr_distance; /* 32G & above */ 4064 #define LR_DISTANCE_5K 1 4065 #define LR_DISTANCE_10K 0 4066 4067 /* This spinlock is used to protect "io transactions", you must 4068 * acquire it before doing any IO to the card, eg with RD_REG*() and 4069 * WRT_REG*() for the duration of your entire commandtransaction. 4070 * 4071 * This spinlock is of lower priority than the io request lock. 4072 */ 4073 4074 spinlock_t hardware_lock ____cacheline_aligned; 4075 int bars; 4076 int mem_only; 4077 device_reg_t *iobase; /* Base I/O address */ 4078 resource_size_t pio_address; 4079 4080 #define MIN_IOBASE_LEN 0x100 4081 dma_addr_t bar0_hdl; 4082 4083 void __iomem *cregbase; 4084 dma_addr_t bar2_hdl; 4085 #define BAR0_LEN_FX00 (1024 * 1024) 4086 #define BAR2_LEN_FX00 (128 * 1024) 4087 4088 uint32_t rqstq_intr_code; 4089 uint32_t mbx_intr_code; 4090 uint32_t req_que_len; 4091 uint32_t rsp_que_len; 4092 uint32_t req_que_off; 4093 uint32_t rsp_que_off; 4094 unsigned long eeh_jif; 4095 4096 /* Multi queue data structs */ 4097 device_reg_t *mqiobase; 4098 device_reg_t *msixbase; 4099 uint16_t msix_count; 4100 uint8_t mqenable; 4101 struct req_que **req_q_map; 4102 struct rsp_que **rsp_q_map; 4103 struct qla_qpair **queue_pair_map; 4104 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4105 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4106 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 4107 / sizeof(unsigned long)]; 4108 uint8_t max_req_queues; 4109 uint8_t max_rsp_queues; 4110 uint8_t max_qpairs; 4111 uint8_t num_qpairs; 4112 struct qla_qpair *base_qpair; 4113 struct qla_npiv_entry *npiv_info; 4114 uint16_t nvram_npiv_size; 4115 4116 uint16_t switch_cap; 4117 #define FLOGI_SEQ_DEL BIT_8 4118 #define FLOGI_MID_SUPPORT BIT_10 4119 #define FLOGI_VSAN_SUPPORT BIT_12 4120 #define FLOGI_SP_SUPPORT BIT_13 4121 4122 uint8_t port_no; /* Physical port of adapter */ 4123 uint8_t exch_starvation; 4124 4125 /* Timeout timers. */ 4126 uint8_t loop_down_abort_time; /* port down timer */ 4127 atomic_t loop_down_timer; /* loop down timer */ 4128 uint8_t link_down_timeout; /* link down timeout */ 4129 uint16_t max_loop_id; 4130 uint16_t max_fibre_devices; /* Maximum number of targets */ 4131 4132 uint16_t fb_rev; 4133 uint16_t min_external_loopid; /* First external loop Id */ 4134 4135 #define PORT_SPEED_UNKNOWN 0xFFFF 4136 #define PORT_SPEED_1GB 0x00 4137 #define PORT_SPEED_2GB 0x01 4138 #define PORT_SPEED_AUTO 0x02 4139 #define PORT_SPEED_4GB 0x03 4140 #define PORT_SPEED_8GB 0x04 4141 #define PORT_SPEED_16GB 0x05 4142 #define PORT_SPEED_32GB 0x06 4143 #define PORT_SPEED_64GB 0x07 4144 #define PORT_SPEED_10GB 0x13 4145 uint16_t link_data_rate; /* F/W operating speed */ 4146 uint16_t set_data_rate; /* Set by user */ 4147 4148 uint8_t current_topology; 4149 uint8_t prev_topology; 4150 #define ISP_CFG_NL 1 4151 #define ISP_CFG_N 2 4152 #define ISP_CFG_FL 4 4153 #define ISP_CFG_F 8 4154 4155 uint8_t operating_mode; /* F/W operating mode */ 4156 #define LOOP 0 4157 #define P2P 1 4158 #define LOOP_P2P 2 4159 #define P2P_LOOP 3 4160 uint8_t interrupts_on; 4161 uint32_t isp_abort_cnt; 4162 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 4163 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 4164 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 4165 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 4166 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 4167 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 4168 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 4169 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 4170 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061 4171 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081 4172 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089 4173 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281 4174 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289 4175 4176 uint32_t isp_type; 4177 #define DT_ISP2100 BIT_0 4178 #define DT_ISP2200 BIT_1 4179 #define DT_ISP2300 BIT_2 4180 #define DT_ISP2312 BIT_3 4181 #define DT_ISP2322 BIT_4 4182 #define DT_ISP6312 BIT_5 4183 #define DT_ISP6322 BIT_6 4184 #define DT_ISP2422 BIT_7 4185 #define DT_ISP2432 BIT_8 4186 #define DT_ISP5422 BIT_9 4187 #define DT_ISP5432 BIT_10 4188 #define DT_ISP2532 BIT_11 4189 #define DT_ISP8432 BIT_12 4190 #define DT_ISP8001 BIT_13 4191 #define DT_ISP8021 BIT_14 4192 #define DT_ISP2031 BIT_15 4193 #define DT_ISP8031 BIT_16 4194 #define DT_ISPFX00 BIT_17 4195 #define DT_ISP8044 BIT_18 4196 #define DT_ISP2071 BIT_19 4197 #define DT_ISP2271 BIT_20 4198 #define DT_ISP2261 BIT_21 4199 #define DT_ISP2061 BIT_22 4200 #define DT_ISP2081 BIT_23 4201 #define DT_ISP2089 BIT_24 4202 #define DT_ISP2281 BIT_25 4203 #define DT_ISP2289 BIT_26 4204 #define DT_ISP_LAST (DT_ISP2289 << 1) 4205 4206 uint32_t device_type; 4207 #define DT_T10_PI BIT_25 4208 #define DT_IIDMA BIT_26 4209 #define DT_FWI2 BIT_27 4210 #define DT_ZIO_SUPPORTED BIT_28 4211 #define DT_OEM_001 BIT_29 4212 #define DT_ISP2200A BIT_30 4213 #define DT_EXTENDED_IDS BIT_31 4214 4215 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 4216 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 4217 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 4218 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 4219 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 4220 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 4221 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 4222 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 4223 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 4224 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 4225 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 4226 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 4227 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 4228 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 4229 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 4230 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 4231 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 4232 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 4233 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 4234 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 4235 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 4236 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 4237 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 4238 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 4239 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081) 4240 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281) 4241 4242 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 4243 IS_QLA6312(ha) || IS_QLA6322(ha)) 4244 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 4245 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 4246 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 4247 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 4248 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 4249 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 4250 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha)) 4251 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 4252 IS_QLA84XX(ha)) 4253 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 4254 IS_QLA8031(ha) || IS_QLA8044(ha)) 4255 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 4256 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 4257 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 4258 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 4259 IS_QLA8044(ha) || IS_QLA27XX(ha) || \ 4260 IS_QLA28XX(ha)) 4261 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4262 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4263 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 4264 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4265 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4266 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4267 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4268 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 4269 4270 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 4271 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 4272 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 4273 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 4274 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 4275 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 4276 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 4277 #define IS_MQUE_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4278 IS_QLA28XX(ha)) 4279 #define IS_BIDI_CAPABLE(ha) \ 4280 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4281 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 4282 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 4283 ((ha)->fw_attributes_ext[0] & BIT_0)) 4284 #define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14) 4285 #define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS) 4286 #define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD) 4287 #define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp)) 4288 #define QLA_LS_ABTS_WAIT_ENABLED(_sp) \ 4289 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4290 #define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \ 4291 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4292 #define QLA_ABTS_WAIT_ENABLED(_sp) \ 4293 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4294 4295 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4296 IS_QLA28XX(ha)) 4297 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4298 IS_QLA28XX(ha)) 4299 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 4300 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4301 IS_QLA28XX(ha)) 4302 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 4303 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 4304 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4305 IS_QLA28XX(ha)) 4306 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 4307 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4308 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4309 IS_QLA28XX(ha)) 4310 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4311 IS_QLA28XX(ha)) 4312 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 4313 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4314 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 4315 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4316 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4317 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ 4318 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4319 4320 #define IS_ZIO_THRESHOLD_CAPABLE(ha) \ 4321 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\ 4322 (ha->zio_mode == QLA_ZIO_MODE_6)) 4323 4324 /* HBA serial number */ 4325 uint8_t serial0; 4326 uint8_t serial1; 4327 uint8_t serial2; 4328 4329 /* NVRAM configuration data */ 4330 #define MAX_NVRAM_SIZE 4096 4331 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2) 4332 uint16_t nvram_size; 4333 uint16_t nvram_base; 4334 void *nvram; 4335 uint16_t vpd_size; 4336 uint16_t vpd_base; 4337 void *vpd; 4338 4339 uint16_t loop_reset_delay; 4340 uint8_t retry_count; 4341 uint8_t login_timeout; 4342 uint16_t r_a_tov; 4343 int port_down_retry_count; 4344 uint8_t mbx_count; 4345 uint8_t aen_mbx_count; 4346 atomic_t num_pend_mbx_stage1; 4347 atomic_t num_pend_mbx_stage2; 4348 atomic_t num_pend_mbx_stage3; 4349 uint16_t frame_payload_size; 4350 4351 uint32_t login_retry_count; 4352 /* SNS command interfaces. */ 4353 ms_iocb_entry_t *ms_iocb; 4354 dma_addr_t ms_iocb_dma; 4355 struct ct_sns_pkt *ct_sns; 4356 dma_addr_t ct_sns_dma; 4357 /* SNS command interfaces for 2200. */ 4358 struct sns_cmd_pkt *sns_cmd; 4359 dma_addr_t sns_cmd_dma; 4360 4361 #define SFP_DEV_SIZE 512 4362 #define SFP_BLOCK_SIZE 64 4363 #define SFP_RTDI_LEN SFP_BLOCK_SIZE 4364 4365 void *sfp_data; 4366 dma_addr_t sfp_data_dma; 4367 4368 struct qla_flt_header *flt; 4369 dma_addr_t flt_dma; 4370 4371 #define XGMAC_DATA_SIZE 4096 4372 void *xgmac_data; 4373 dma_addr_t xgmac_data_dma; 4374 4375 #define DCBX_TLV_DATA_SIZE 4096 4376 void *dcbx_tlv; 4377 dma_addr_t dcbx_tlv_dma; 4378 4379 struct task_struct *dpc_thread; 4380 uint8_t dpc_active; /* DPC routine is active */ 4381 4382 dma_addr_t gid_list_dma; 4383 struct gid_list_info *gid_list; 4384 int gid_list_info_size; 4385 4386 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 4387 #define DMA_POOL_SIZE 256 4388 struct dma_pool *s_dma_pool; 4389 4390 dma_addr_t init_cb_dma; 4391 init_cb_t *init_cb; 4392 int init_cb_size; 4393 dma_addr_t ex_init_cb_dma; 4394 struct ex_init_cb_81xx *ex_init_cb; 4395 dma_addr_t sf_init_cb_dma; 4396 struct init_sf_cb *sf_init_cb; 4397 4398 void *scm_fpin_els_buff; 4399 uint64_t scm_fpin_els_buff_size; 4400 bool scm_fpin_valid; 4401 bool scm_fpin_payload_size; 4402 4403 void *async_pd; 4404 dma_addr_t async_pd_dma; 4405 4406 #define ENABLE_EXTENDED_LOGIN BIT_7 4407 4408 /* Extended Logins */ 4409 void *exlogin_buf; 4410 dma_addr_t exlogin_buf_dma; 4411 uint32_t exlogin_size; 4412 4413 #define ENABLE_EXCHANGE_OFFLD BIT_2 4414 4415 /* Exchange Offload */ 4416 void *exchoffld_buf; 4417 dma_addr_t exchoffld_buf_dma; 4418 int exchoffld_size; 4419 int exchoffld_count; 4420 4421 /* n2n */ 4422 struct fc_els_flogi plogi_els_payld; 4423 #define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4) 4424 4425 void *swl; 4426 4427 /* These are used by mailbox operations. */ 4428 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 4429 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 4430 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 4431 4432 mbx_cmd_t *mcp; 4433 struct mbx_cmd_32 *mcp32; 4434 4435 unsigned long mbx_cmd_flags; 4436 #define MBX_INTERRUPT 1 4437 #define MBX_INTR_WAIT 2 4438 #define MBX_UPDATE_FLASH_ACTIVE 3 4439 4440 struct mutex vport_lock; /* Virtual port synchronization */ 4441 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 4442 struct mutex mq_lock; /* multi-queue synchronization */ 4443 struct completion mbx_cmd_comp; /* Serialize mbx access */ 4444 struct completion mbx_intr_comp; /* Used for completion notification */ 4445 struct completion dcbx_comp; /* For set port config notification */ 4446 struct completion lb_portup_comp; /* Used to wait for link up during 4447 * loopback */ 4448 #define DCBX_COMP_TIMEOUT 20 4449 #define LB_PORTUP_COMP_TIMEOUT 10 4450 4451 int notify_dcbx_comp; 4452 int notify_lb_portup_comp; 4453 struct mutex selflogin_lock; 4454 4455 /* Basic firmware related information. */ 4456 uint16_t fw_major_version; 4457 uint16_t fw_minor_version; 4458 uint16_t fw_subminor_version; 4459 uint16_t fw_attributes; 4460 uint16_t fw_attributes_h; 4461 #define FW_ATTR_H_NVME_FBURST BIT_1 4462 #define FW_ATTR_H_NVME BIT_10 4463 #define FW_ATTR_H_NVME_UPDATED BIT_14 4464 4465 /* About firmware SCM support */ 4466 #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12 4467 /* Brocade fabric attached */ 4468 #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000 4469 /* Cisco fabric attached */ 4470 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000 4471 #define FW_ATTR_EXT0_NVME2 BIT_13 4472 #define FW_ATTR_EXT0_EDIF BIT_5 4473 uint16_t fw_attributes_ext[2]; 4474 uint32_t fw_memory_size; 4475 uint32_t fw_transfer_size; 4476 uint32_t fw_srisc_address; 4477 #define RISC_START_ADDRESS_2100 0x1000 4478 #define RISC_START_ADDRESS_2300 0x800 4479 #define RISC_START_ADDRESS_2400 0x100000 4480 4481 uint16_t orig_fw_tgt_xcb_count; 4482 uint16_t cur_fw_tgt_xcb_count; 4483 uint16_t orig_fw_xcb_count; 4484 uint16_t cur_fw_xcb_count; 4485 uint16_t orig_fw_iocb_count; 4486 uint16_t cur_fw_iocb_count; 4487 uint16_t fw_max_fcf_count; 4488 4489 uint32_t fw_shared_ram_start; 4490 uint32_t fw_shared_ram_end; 4491 uint32_t fw_ddr_ram_start; 4492 uint32_t fw_ddr_ram_end; 4493 4494 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 4495 uint8_t fw_seriallink_options[4]; 4496 __le16 fw_seriallink_options24[4]; 4497 4498 uint8_t serdes_version[3]; 4499 uint8_t mpi_version[3]; 4500 uint32_t mpi_capabilities; 4501 uint8_t phy_version[3]; 4502 uint8_t pep_version[3]; 4503 4504 /* Firmware dump template */ 4505 struct fwdt { 4506 void *template; 4507 ulong length; 4508 ulong dump_size; 4509 } fwdt[2]; 4510 struct qla2xxx_fw_dump *fw_dump; 4511 uint32_t fw_dump_len; 4512 u32 fw_dump_alloc_len; 4513 bool fw_dumped; 4514 unsigned long fw_dump_cap_flags; 4515 #define RISC_PAUSE_CMPL 0 4516 #define DMA_SHUTDOWN_CMPL 1 4517 #define ISP_RESET_CMPL 2 4518 #define RISC_RDY_AFT_RESET 3 4519 #define RISC_SRAM_DUMP_CMPL 4 4520 #define RISC_EXT_MEM_DUMP_CMPL 5 4521 #define ISP_MBX_RDY 6 4522 #define ISP_SOFT_RESET_CMPL 7 4523 int fw_dump_reading; 4524 void *mpi_fw_dump; 4525 u32 mpi_fw_dump_len; 4526 unsigned int mpi_fw_dump_reading:1; 4527 unsigned int mpi_fw_dumped:1; 4528 int prev_minidump_failed; 4529 dma_addr_t eft_dma; 4530 void *eft; 4531 /* Current size of mctp dump is 0x086064 bytes */ 4532 #define MCTP_DUMP_SIZE 0x086064 4533 dma_addr_t mctp_dump_dma; 4534 void *mctp_dump; 4535 int mctp_dumped; 4536 int mctp_dump_reading; 4537 uint32_t chain_offset; 4538 struct dentry *dfs_dir; 4539 struct dentry *dfs_fce; 4540 struct dentry *dfs_tgt_counters; 4541 struct dentry *dfs_fw_resource_cnt; 4542 4543 dma_addr_t fce_dma; 4544 void *fce; 4545 uint32_t fce_bufs; 4546 uint16_t fce_mb[8]; 4547 uint64_t fce_wr, fce_rd; 4548 struct mutex fce_mutex; 4549 4550 uint32_t pci_attr; 4551 uint16_t chip_revision; 4552 4553 uint16_t product_id[4]; 4554 4555 uint8_t model_number[16+1]; 4556 char model_desc[80]; 4557 uint8_t adapter_id[16+1]; 4558 4559 /* Option ROM information. */ 4560 char *optrom_buffer; 4561 uint32_t optrom_size; 4562 int optrom_state; 4563 #define QLA_SWAITING 0 4564 #define QLA_SREADING 1 4565 #define QLA_SWRITING 2 4566 uint32_t optrom_region_start; 4567 uint32_t optrom_region_size; 4568 struct mutex optrom_mutex; 4569 4570 /* PCI expansion ROM image information. */ 4571 #define ROM_CODE_TYPE_BIOS 0 4572 #define ROM_CODE_TYPE_FCODE 1 4573 #define ROM_CODE_TYPE_EFI 3 4574 uint8_t bios_revision[2]; 4575 uint8_t efi_revision[2]; 4576 uint8_t fcode_revision[16]; 4577 uint32_t fw_revision[4]; 4578 4579 uint32_t gold_fw_version[4]; 4580 4581 /* Offsets for flash/nvram access (set to ~0 if not used). */ 4582 uint32_t flash_conf_off; 4583 uint32_t flash_data_off; 4584 uint32_t nvram_conf_off; 4585 uint32_t nvram_data_off; 4586 4587 uint32_t fdt_wrt_disable; 4588 uint32_t fdt_wrt_enable; 4589 uint32_t fdt_erase_cmd; 4590 uint32_t fdt_block_size; 4591 uint32_t fdt_unprotect_sec_cmd; 4592 uint32_t fdt_protect_sec_cmd; 4593 uint32_t fdt_wrt_sts_reg_cmd; 4594 4595 struct { 4596 uint32_t flt_region_flt; 4597 uint32_t flt_region_fdt; 4598 uint32_t flt_region_boot; 4599 uint32_t flt_region_boot_sec; 4600 uint32_t flt_region_fw; 4601 uint32_t flt_region_fw_sec; 4602 uint32_t flt_region_vpd_nvram; 4603 uint32_t flt_region_vpd_nvram_sec; 4604 uint32_t flt_region_vpd; 4605 uint32_t flt_region_vpd_sec; 4606 uint32_t flt_region_nvram; 4607 uint32_t flt_region_nvram_sec; 4608 uint32_t flt_region_npiv_conf; 4609 uint32_t flt_region_gold_fw; 4610 uint32_t flt_region_fcp_prio; 4611 uint32_t flt_region_bootload; 4612 uint32_t flt_region_img_status_pri; 4613 uint32_t flt_region_img_status_sec; 4614 uint32_t flt_region_aux_img_status_pri; 4615 uint32_t flt_region_aux_img_status_sec; 4616 }; 4617 uint8_t active_image; 4618 4619 /* Needed for BEACON */ 4620 uint16_t beacon_blink_led; 4621 uint8_t beacon_color_state; 4622 #define QLA_LED_GRN_ON 0x01 4623 #define QLA_LED_YLW_ON 0x02 4624 #define QLA_LED_ABR_ON 0x04 4625 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 4626 /* ISP2322: red, green, amber. */ 4627 uint16_t zio_mode; 4628 uint16_t zio_timer; 4629 4630 struct qla_msix_entry *msix_entries; 4631 4632 struct list_head vp_list; /* list of VP */ 4633 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 4634 sizeof(unsigned long)]; 4635 uint16_t num_vhosts; /* number of vports created */ 4636 uint16_t num_vsans; /* number of vsan created */ 4637 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 4638 int cur_vport_count; 4639 4640 struct qla_chip_state_84xx *cs84xx; 4641 struct isp_operations *isp_ops; 4642 struct workqueue_struct *wq; 4643 struct work_struct heartbeat_work; 4644 struct qlfc_fw fw_buf; 4645 unsigned long last_heartbeat_run_jiffies; 4646 4647 /* FCP_CMND priority support */ 4648 struct qla_fcp_prio_cfg *fcp_prio_cfg; 4649 4650 struct dma_pool *dl_dma_pool; 4651 #define DSD_LIST_DMA_POOL_SIZE 512 4652 4653 struct dma_pool *fcp_cmnd_dma_pool; 4654 mempool_t *ctx_mempool; 4655 #define FCP_CMND_DMA_POOL_SIZE 512 4656 4657 void __iomem *nx_pcibase; /* Base I/O address */ 4658 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4659 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4660 4661 uint32_t crb_win; 4662 uint32_t curr_window; 4663 uint32_t ddr_mn_window; 4664 unsigned long mn_win_crb; 4665 unsigned long ms_win_crb; 4666 int qdr_sn_window; 4667 uint32_t fcoe_dev_init_timeout; 4668 uint32_t fcoe_reset_timeout; 4669 rwlock_t hw_lock; 4670 uint16_t portnum; /* port number */ 4671 int link_width; 4672 struct fw_blob *hablob; 4673 struct qla82xx_legacy_intr_set nx_legacy_intr; 4674 4675 uint16_t gbl_dsd_inuse; 4676 uint16_t gbl_dsd_avail; 4677 struct list_head gbl_dsd_list; 4678 #define NUM_DSD_CHAIN 4096 4679 4680 uint8_t fw_type; 4681 uint32_t file_prd_off; /* File firmware product offset */ 4682 4683 uint32_t md_template_size; 4684 void *md_tmplt_hdr; 4685 dma_addr_t md_tmplt_hdr_dma; 4686 void *md_dump; 4687 uint32_t md_dump_size; 4688 4689 void *loop_id_map; 4690 4691 /* QLA83XX IDC specific fields */ 4692 uint32_t idc_audit_ts; 4693 uint32_t idc_extend_tmo; 4694 4695 /* DPC low-priority workqueue */ 4696 struct workqueue_struct *dpc_lp_wq; 4697 struct work_struct idc_aen; 4698 /* DPC high-priority workqueue */ 4699 struct workqueue_struct *dpc_hp_wq; 4700 struct work_struct nic_core_reset; 4701 struct work_struct idc_state_handler; 4702 struct work_struct nic_core_unrecoverable; 4703 struct work_struct board_disable; 4704 4705 struct mr_data_fx00 mr; 4706 uint32_t chip_reset; 4707 4708 struct qlt_hw_data tgt; 4709 int allow_cna_fw_dump; 4710 uint32_t fw_ability_mask; 4711 uint16_t min_supported_speed; 4712 uint16_t max_supported_speed; 4713 4714 /* DMA pool for the DIF bundling buffers */ 4715 struct dma_pool *dif_bundl_pool; 4716 #define DIF_BUNDLING_DMA_POOL_SIZE 1024 4717 struct { 4718 struct { 4719 struct list_head head; 4720 uint count; 4721 } good; 4722 struct { 4723 struct list_head head; 4724 uint count; 4725 } unusable; 4726 } pool; 4727 4728 unsigned long long dif_bundle_crossed_pages; 4729 unsigned long long dif_bundle_reads; 4730 unsigned long long dif_bundle_writes; 4731 unsigned long long dif_bundle_kallocs; 4732 unsigned long long dif_bundle_dma_allocs; 4733 4734 atomic_t nvme_active_aen_cnt; 4735 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4736 4737 uint8_t fc4_type_priority; 4738 4739 atomic_t zio_threshold; 4740 uint16_t last_zio_threshold; 4741 4742 #define DEFAULT_ZIO_THRESHOLD 5 4743 4744 struct qla_hw_data_stat stat; 4745 pci_error_state_t pci_error_state; 4746 struct dma_pool *purex_dma_pool; 4747 struct btree_head32 host_map; 4748 4749 #define EDIF_NUM_SA_INDEX 512 4750 #define EDIF_TX_SA_INDEX_BASE EDIF_NUM_SA_INDEX 4751 void *edif_rx_sa_id_map; 4752 void *edif_tx_sa_id_map; 4753 spinlock_t sadb_fp_lock; 4754 4755 struct list_head sadb_tx_index_list; 4756 struct list_head sadb_rx_index_list; 4757 spinlock_t sadb_lock; /* protects list */ 4758 struct els_reject elsrej; 4759 u8 edif_post_stop_cnt_down; 4760 }; 4761 4762 #define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES)) 4763 4764 struct active_regions { 4765 uint8_t global; 4766 struct { 4767 uint8_t board_config; 4768 uint8_t vpd_nvram; 4769 uint8_t npiv_config_0_1; 4770 uint8_t npiv_config_2_3; 4771 } aux; 4772 }; 4773 4774 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4775 #define FW_ABILITY_MAX_SPEED_16G 0x0 4776 #define FW_ABILITY_MAX_SPEED_32G 0x1 4777 #define FW_ABILITY_MAX_SPEED(ha) \ 4778 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4779 4780 #define QLA_GET_DATA_RATE 0 4781 #define QLA_SET_DATA_RATE_NOLR 1 4782 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */ 4783 4784 #define QLA_DEFAULT_PAYLOAD_SIZE 64 4785 /* 4786 * This item might be allocated with a size > sizeof(struct purex_item). 4787 * The "size" variable gives the size of the payload (which 4788 * is variable) starting at "iocb". 4789 */ 4790 struct purex_item { 4791 struct list_head list; 4792 struct scsi_qla_host *vha; 4793 void (*process_item)(struct scsi_qla_host *vha, 4794 struct purex_item *pkt); 4795 atomic_t in_use; 4796 uint16_t size; 4797 struct { 4798 uint8_t iocb[64]; 4799 } iocb; 4800 }; 4801 4802 #include "qla_edif.h" 4803 4804 #define SCM_FLAG_RDF_REJECT 0x00 4805 #define SCM_FLAG_RDF_COMPLETED 0x01 4806 4807 #define QLA_CON_PRIMITIVE_RECEIVED 0x1 4808 #define QLA_CONGESTION_ARB_WARNING 0x1 4809 #define QLA_CONGESTION_ARB_ALARM 0X2 4810 4811 /* 4812 * Qlogic scsi host structure 4813 */ 4814 typedef struct scsi_qla_host { 4815 struct list_head list; 4816 struct list_head vp_fcports; /* list of fcports */ 4817 struct list_head work_list; 4818 spinlock_t work_lock; 4819 struct work_struct iocb_work; 4820 4821 /* Commonly used flags and state information. */ 4822 struct Scsi_Host *host; 4823 unsigned long host_no; 4824 uint8_t host_str[16]; 4825 4826 volatile struct { 4827 uint32_t init_done :1; 4828 uint32_t online :1; 4829 uint32_t reset_active :1; 4830 4831 uint32_t management_server_logged_in :1; 4832 uint32_t process_response_queue :1; 4833 uint32_t difdix_supported:1; 4834 uint32_t delete_progress:1; 4835 4836 uint32_t fw_tgt_reported:1; 4837 uint32_t bbcr_enable:1; 4838 uint32_t qpairs_available:1; 4839 uint32_t qpairs_req_created:1; 4840 uint32_t qpairs_rsp_created:1; 4841 uint32_t nvme_enabled:1; 4842 uint32_t nvme_first_burst:1; 4843 uint32_t nvme2_enabled:1; 4844 } flags; 4845 4846 atomic_t loop_state; 4847 #define LOOP_TIMEOUT 1 4848 #define LOOP_DOWN 2 4849 #define LOOP_UP 3 4850 #define LOOP_UPDATE 4 4851 #define LOOP_READY 5 4852 #define LOOP_DEAD 6 4853 4854 unsigned long relogin_jif; 4855 unsigned long dpc_flags; 4856 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4857 #define RESET_ACTIVE 1 4858 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4859 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4860 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4861 #define LOOP_RESYNC_ACTIVE 5 4862 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4863 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4864 #define RELOGIN_NEEDED 8 4865 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4866 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4867 #define BEACON_BLINK_NEEDED 11 4868 #define REGISTER_FDMI_NEEDED 12 4869 #define FCPORT_UPDATE_NEEDED 13 4870 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4871 #define UNLOADING 15 4872 #define NPIV_CONFIG_NEEDED 16 4873 #define ISP_UNRECOVERABLE 17 4874 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4875 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4876 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4877 #define N2N_LINK_RESET 21 4878 #define PORT_UPDATE_NEEDED 22 4879 #define FX00_RESET_RECOVERY 23 4880 #define FX00_TARGET_SCAN 24 4881 #define FX00_CRITEMP_RECOVERY 25 4882 #define FX00_HOST_INFO_RESEND 26 4883 #define QPAIR_ONLINE_CHECK_NEEDED 27 4884 #define DO_EEH_RECOVERY 28 4885 #define DETECT_SFP_CHANGE 29 4886 #define N2N_LOGIN_NEEDED 30 4887 #define IOCB_WORK_ACTIVE 31 4888 #define SET_ZIO_THRESHOLD_NEEDED 32 4889 #define ISP_ABORT_TO_ROM 33 4890 #define VPORT_DELETE 34 4891 4892 #define PROCESS_PUREX_IOCB 63 4893 4894 unsigned long pci_flags; 4895 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4896 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4897 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4898 4899 uint32_t device_flags; 4900 #define SWITCH_FOUND BIT_0 4901 #define DFLG_NO_CABLE BIT_1 4902 #define DFLG_DEV_FAILED BIT_5 4903 4904 /* ISP configuration data. */ 4905 uint16_t loop_id; /* Host adapter loop id */ 4906 uint16_t self_login_loop_id; /* host adapter loop id 4907 * get it on self login 4908 */ 4909 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4910 * no need of allocating it for 4911 * each command 4912 */ 4913 4914 port_id_t d_id; /* Host adapter port id */ 4915 uint8_t marker_needed; 4916 uint16_t mgmt_svr_loop_id; 4917 4918 4919 4920 /* Timeout timers. */ 4921 uint8_t loop_down_abort_time; /* port down timer */ 4922 atomic_t loop_down_timer; /* loop down timer */ 4923 uint8_t link_down_timeout; /* link down timeout */ 4924 4925 uint32_t timer_active; 4926 struct timer_list timer; 4927 4928 uint8_t node_name[WWN_SIZE]; 4929 uint8_t port_name[WWN_SIZE]; 4930 uint8_t fabric_node_name[WWN_SIZE]; 4931 uint8_t fabric_port_name[WWN_SIZE]; 4932 4933 struct nvme_fc_local_port *nvme_local_port; 4934 struct completion nvme_del_done; 4935 4936 uint16_t fcoe_vlan_id; 4937 uint16_t fcoe_fcf_idx; 4938 uint8_t fcoe_vn_port_mac[6]; 4939 4940 /* list of commands waiting on workqueue */ 4941 struct list_head qla_cmd_list; 4942 struct list_head unknown_atio_list; 4943 spinlock_t cmd_list_lock; 4944 struct delayed_work unknown_atio_work; 4945 4946 /* Counter to detect races between ELS and RSCN events */ 4947 atomic_t generation_tick; 4948 /* Time when global fcport update has been scheduled */ 4949 int total_fcport_update_gen; 4950 /* List of pending LOGOs, protected by tgt_mutex */ 4951 struct list_head logo_list; 4952 /* List of pending PLOGI acks, protected by hw lock */ 4953 struct list_head plogi_ack_list; 4954 4955 struct list_head qp_list; 4956 4957 uint32_t vp_abort_cnt; 4958 4959 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 4960 uint16_t vp_idx; /* vport ID */ 4961 struct qla_qpair *qpair; /* base qpair */ 4962 4963 unsigned long vp_flags; 4964 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 4965 #define VP_CREATE_NEEDED 1 4966 #define VP_BIND_NEEDED 2 4967 #define VP_DELETE_NEEDED 3 4968 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 4969 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 4970 atomic_t vp_state; 4971 #define VP_OFFLINE 0 4972 #define VP_ACTIVE 1 4973 #define VP_FAILED 2 4974 // #define VP_DISABLE 3 4975 uint16_t vp_err_state; 4976 uint16_t vp_prev_err_state; 4977 #define VP_ERR_UNKWN 0 4978 #define VP_ERR_PORTDWN 1 4979 #define VP_ERR_FAB_UNSUPPORTED 2 4980 #define VP_ERR_FAB_NORESOURCES 3 4981 #define VP_ERR_FAB_LOGOUT 4 4982 #define VP_ERR_ADAP_NORESOURCES 5 4983 struct qla_hw_data *hw; 4984 struct scsi_qlt_host vha_tgt; 4985 struct req_que *req; 4986 int fw_heartbeat_counter; 4987 int seconds_since_last_heartbeat; 4988 struct fc_host_statistics fc_host_stat; 4989 struct qla_statistics qla_stats; 4990 struct bidi_statistics bidi_stats; 4991 atomic_t vref_count; 4992 struct qla8044_reset_template reset_tmplt; 4993 uint16_t bbcr; 4994 4995 uint16_t u_ql2xexchoffld; 4996 uint16_t u_ql2xiniexchg; 4997 uint16_t qlini_mode; 4998 uint16_t ql2xexchoffld; 4999 uint16_t ql2xiniexchg; 5000 5001 struct dentry *dfs_rport_root; 5002 5003 struct purex_list { 5004 struct list_head head; 5005 spinlock_t lock; 5006 } purex_list; 5007 struct purex_item default_item; 5008 5009 struct name_list_extended gnl; 5010 /* Count of active session/fcport */ 5011 int fcport_count; 5012 wait_queue_head_t fcport_waitQ; 5013 wait_queue_head_t vref_waitq; 5014 uint8_t min_supported_speed; 5015 uint8_t n2n_node_name[WWN_SIZE]; 5016 uint8_t n2n_port_name[WWN_SIZE]; 5017 uint16_t n2n_id; 5018 __le16 dport_data[4]; 5019 struct list_head gpnid_list; 5020 struct fab_scan scan; 5021 uint8_t scm_fabric_connection_flags; 5022 5023 unsigned int irq_offset; 5024 5025 u64 hw_err_cnt; 5026 u64 interface_err_cnt; 5027 u64 cmd_timeout_cnt; 5028 u64 reset_cmd_err_cnt; 5029 u64 link_down_time; 5030 u64 short_link_down_cnt; 5031 struct edif_dbell e_dbell; 5032 struct pur_core pur_cinfo; 5033 5034 #define DPORT_DIAG_IN_PROGRESS BIT_0 5035 #define DPORT_DIAG_CHIP_RESET_IN_PROGRESS BIT_1 5036 uint16_t dport_status; 5037 } scsi_qla_host_t; 5038 5039 struct qla27xx_image_status { 5040 uint8_t image_status_mask; 5041 __le16 generation; 5042 uint8_t ver_major; 5043 uint8_t ver_minor; 5044 uint8_t bitmap; /* 28xx only */ 5045 uint8_t reserved[2]; 5046 __le32 checksum; 5047 __le32 signature; 5048 } __packed; 5049 5050 /* 28xx aux image status bimap values */ 5051 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0 5052 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1 5053 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2 5054 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3 5055 5056 #define SET_VP_IDX 1 5057 #define SET_AL_PA 2 5058 #define RESET_VP_IDX 3 5059 #define RESET_AL_PA 4 5060 struct qla_tgt_vp_map { 5061 uint8_t idx; 5062 scsi_qla_host_t *vha; 5063 }; 5064 5065 struct qla2_sgx { 5066 dma_addr_t dma_addr; /* OUT */ 5067 uint32_t dma_len; /* OUT */ 5068 5069 uint32_t tot_bytes; /* IN */ 5070 struct scatterlist *cur_sg; /* IN */ 5071 5072 /* for book keeping, bzero on initial invocation */ 5073 uint32_t bytes_consumed; 5074 uint32_t num_bytes; 5075 uint32_t tot_partial; 5076 5077 /* for debugging */ 5078 uint32_t num_sg; 5079 srb_t *sp; 5080 }; 5081 5082 #define QLA_FW_STARTED(_ha) { \ 5083 int i; \ 5084 _ha->flags.fw_started = 1; \ 5085 _ha->base_qpair->fw_started = 1; \ 5086 for (i = 0; i < _ha->max_qpairs; i++) { \ 5087 if (_ha->queue_pair_map[i]) \ 5088 _ha->queue_pair_map[i]->fw_started = 1; \ 5089 } \ 5090 } 5091 5092 #define QLA_FW_STOPPED(_ha) { \ 5093 int i; \ 5094 _ha->flags.fw_started = 0; \ 5095 _ha->base_qpair->fw_started = 0; \ 5096 for (i = 0; i < _ha->max_qpairs; i++) { \ 5097 if (_ha->queue_pair_map[i]) \ 5098 _ha->queue_pair_map[i]->fw_started = 0; \ 5099 } \ 5100 } 5101 5102 5103 #define SFUB_CHECKSUM_SIZE 4 5104 5105 struct secure_flash_update_block { 5106 uint32_t block_info; 5107 uint32_t signature_lo; 5108 uint32_t signature_hi; 5109 uint32_t signature_upper[0x3e]; 5110 }; 5111 5112 struct secure_flash_update_block_pk { 5113 uint32_t block_info; 5114 uint32_t signature_lo; 5115 uint32_t signature_hi; 5116 uint32_t signature_upper[0x3e]; 5117 uint32_t public_key[0x41]; 5118 }; 5119 5120 /* 5121 * Macros to help code, maintain, etc. 5122 */ 5123 #define LOOP_TRANSITION(ha) \ 5124 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5125 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 5126 atomic_read(&ha->loop_state) == LOOP_DOWN) 5127 5128 #define STATE_TRANSITION(ha) \ 5129 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5130 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 5131 5132 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 5133 atomic_inc(&__vha->vref_count); \ 5134 mb(); \ 5135 if (__vha->flags.delete_progress) { \ 5136 atomic_dec(&__vha->vref_count); \ 5137 wake_up(&__vha->vref_waitq); \ 5138 __bail = 1; \ 5139 } else { \ 5140 __bail = 0; \ 5141 } \ 5142 } while (0) 5143 5144 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 5145 atomic_dec(&__vha->vref_count); \ 5146 wake_up(&__vha->vref_waitq); \ 5147 } while (0) \ 5148 5149 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 5150 atomic_inc(&__qpair->ref_count); \ 5151 mb(); \ 5152 if (__qpair->delete_in_progress) { \ 5153 atomic_dec(&__qpair->ref_count); \ 5154 __bail = 1; \ 5155 } else { \ 5156 __bail = 0; \ 5157 } \ 5158 } while (0) 5159 5160 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 5161 atomic_dec(&__qpair->ref_count) 5162 5163 #define QLA_ENA_CONF(_ha) {\ 5164 int i;\ 5165 _ha->base_qpair->enable_explicit_conf = 1; \ 5166 for (i = 0; i < _ha->max_qpairs; i++) { \ 5167 if (_ha->queue_pair_map[i]) \ 5168 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 5169 } \ 5170 } 5171 5172 #define QLA_DIS_CONF(_ha) {\ 5173 int i;\ 5174 _ha->base_qpair->enable_explicit_conf = 0; \ 5175 for (i = 0; i < _ha->max_qpairs; i++) { \ 5176 if (_ha->queue_pair_map[i]) \ 5177 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 5178 } \ 5179 } 5180 5181 /* 5182 * qla2x00 local function return status codes 5183 */ 5184 #define MBS_MASK 0x3fff 5185 5186 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 5187 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 5188 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 5189 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 5190 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 5191 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 5192 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 5193 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 5194 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 5195 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 5196 5197 #define QLA_FUNCTION_TIMEOUT 0x100 5198 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 5199 #define QLA_FUNCTION_FAILED 0x102 5200 #define QLA_MEMORY_ALLOC_FAILED 0x103 5201 #define QLA_LOCK_TIMEOUT 0x104 5202 #define QLA_ABORTED 0x105 5203 #define QLA_SUSPENDED 0x106 5204 #define QLA_BUSY 0x107 5205 #define QLA_ALREADY_REGISTERED 0x109 5206 #define QLA_OS_TIMER_EXPIRED 0x10a 5207 #define QLA_ERR_NO_QPAIR 0x10b 5208 #define QLA_ERR_NOT_FOUND 0x10c 5209 #define QLA_ERR_FROM_FW 0x10d 5210 5211 #define NVRAM_DELAY() udelay(10) 5212 5213 /* 5214 * Flash support definitions 5215 */ 5216 #define OPTROM_SIZE_2300 0x20000 5217 #define OPTROM_SIZE_2322 0x100000 5218 #define OPTROM_SIZE_24XX 0x100000 5219 #define OPTROM_SIZE_25XX 0x200000 5220 #define OPTROM_SIZE_81XX 0x400000 5221 #define OPTROM_SIZE_82XX 0x800000 5222 #define OPTROM_SIZE_83XX 0x1000000 5223 #define OPTROM_SIZE_28XX 0x2000000 5224 5225 #define OPTROM_BURST_SIZE 0x1000 5226 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 5227 5228 #define QLA_DSDS_PER_IOCB 37 5229 5230 #define QLA_SG_ALL 1024 5231 5232 enum nexus_wait_type { 5233 WAIT_HOST = 0, 5234 WAIT_TARGET, 5235 WAIT_LUN, 5236 }; 5237 5238 #define INVALID_EDIF_SA_INDEX 0xffff 5239 #define RX_DELETE_NO_EDIF_SA_INDEX 0xfffe 5240 5241 #define QLA_SKIP_HANDLE QLA_TGT_SKIP_HANDLE 5242 5243 /* edif hash element */ 5244 struct edif_list_entry { 5245 uint16_t handle; /* nport_handle */ 5246 uint32_t update_sa_index; 5247 uint32_t delete_sa_index; 5248 uint32_t count; /* counter for filtering sa_index */ 5249 #define EDIF_ENTRY_FLAGS_CLEANUP 0x01 /* this index is being cleaned up */ 5250 uint32_t flags; /* used by sadb cleanup code */ 5251 fc_port_t *fcport; /* needed by rx delay timer function */ 5252 struct timer_list timer; /* rx delay timer */ 5253 struct list_head next; 5254 }; 5255 5256 #define EDIF_TX_INDX_BASE 512 5257 #define EDIF_RX_INDX_BASE 0 5258 #define EDIF_RX_DELETE_FILTER_COUNT 3 /* delay queuing rx delete until this many */ 5259 5260 /* entry in the sa_index free pool */ 5261 5262 struct sa_index_pair { 5263 uint16_t sa_index; 5264 uint32_t spi; 5265 }; 5266 5267 /* edif sa_index data structure */ 5268 struct edif_sa_index_entry { 5269 struct sa_index_pair sa_pair[2]; 5270 fc_port_t *fcport; 5271 uint16_t handle; 5272 struct list_head next; 5273 }; 5274 5275 /* Refer to SNIA SFF 8247 */ 5276 struct sff_8247_a0 { 5277 u8 txid; /* transceiver id */ 5278 u8 ext_txid; 5279 u8 connector; 5280 /* compliance code */ 5281 u8 eth_infi_cc3; /* ethernet, inifiband */ 5282 u8 sonet_cc4[2]; 5283 u8 eth_cc6; 5284 /* link length */ 5285 #define FC_LL_VL BIT_7 /* very long */ 5286 #define FC_LL_S BIT_6 /* Short */ 5287 #define FC_LL_I BIT_5 /* Intermidiate*/ 5288 #define FC_LL_L BIT_4 /* Long */ 5289 #define FC_LL_M BIT_3 /* Medium */ 5290 #define FC_LL_SA BIT_2 /* ShortWave laser */ 5291 #define FC_LL_LC BIT_1 /* LongWave laser */ 5292 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 5293 u8 fc_ll_cc7; 5294 /* FC technology */ 5295 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 5296 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 5297 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 5298 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 5299 #define FC_TEC_ACT BIT_3 /* Active cable */ 5300 #define FC_TEC_PAS BIT_2 /* Passive cable */ 5301 u8 fc_tec_cc8; 5302 /* Transmission Media */ 5303 #define FC_MED_TW BIT_7 /* Twin Ax */ 5304 #define FC_MED_TP BIT_6 /* Twited Pair */ 5305 #define FC_MED_MI BIT_5 /* Min Coax */ 5306 #define FC_MED_TV BIT_4 /* Video Coax */ 5307 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 5308 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 5309 #define FC_MED_SM BIT_0 /* Single Mode */ 5310 u8 fc_med_cc9; 5311 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 5312 #define FC_SP_12 BIT_7 5313 #define FC_SP_8 BIT_6 5314 #define FC_SP_16 BIT_5 5315 #define FC_SP_4 BIT_4 5316 #define FC_SP_32 BIT_3 5317 #define FC_SP_2 BIT_2 5318 #define FC_SP_1 BIT_0 5319 u8 fc_sp_cc10; 5320 u8 encode; 5321 u8 bitrate; 5322 u8 rate_id; 5323 u8 length_km; /* offset 14/eh */ 5324 u8 length_100m; 5325 u8 length_50um_10m; 5326 u8 length_62um_10m; 5327 u8 length_om4_10m; 5328 u8 length_om3_10m; 5329 #define SFF_VEN_NAME_LEN 16 5330 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 5331 u8 tx_compat; 5332 u8 vendor_oui[3]; 5333 #define SFF_PART_NAME_LEN 16 5334 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 5335 u8 vendor_rev[4]; 5336 u8 wavelength[2]; 5337 u8 resv; 5338 u8 cc_base; 5339 u8 options[2]; /* offset 64 */ 5340 u8 br_max; 5341 u8 br_min; 5342 u8 vendor_sn[16]; 5343 u8 date_code[8]; 5344 u8 diag; 5345 u8 enh_options; 5346 u8 sff_revision; 5347 u8 cc_ext; 5348 u8 vendor_specific[32]; 5349 u8 resv2[128]; 5350 }; 5351 5352 /* BPM -- Buffer Plus Management support. */ 5353 #define IS_BPM_CAPABLE(ha) \ 5354 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 5355 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5356 #define IS_BPM_RANGE_CAPABLE(ha) \ 5357 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5358 #define IS_BPM_ENABLED(vha) \ 5359 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw)) 5360 5361 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016 5362 5363 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 5364 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha))) 5365 5366 #define SAVE_TOPO(_ha) { \ 5367 if (_ha->current_topology) \ 5368 _ha->prev_topology = _ha->current_topology; \ 5369 } 5370 5371 #define N2N_TOPO(ha) \ 5372 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ 5373 ha->current_topology == ISP_CFG_N || \ 5374 !ha->current_topology) 5375 5376 #define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */ 5377 5378 #define NVME_TYPE(fcport) \ 5379 (fcport->fc4_type & FS_FC4TYPE_NVME) \ 5380 5381 #define FCP_TYPE(fcport) \ 5382 (fcport->fc4_type & FS_FC4TYPE_FCP) \ 5383 5384 #define NVME_ONLY_TARGET(fcport) \ 5385 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \ 5386 5387 #define NVME_FCP_TARGET(fcport) \ 5388 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \ 5389 5390 #define NVME_PRIORITY(ha, fcport) \ 5391 (NVME_FCP_TARGET(fcport) && \ 5392 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) 5393 5394 #define NVME_TARGET(ha, fcport) \ 5395 (fcport->do_prli_nvme || \ 5396 NVME_ONLY_TARGET(fcport)) \ 5397 5398 #define PRLI_PHASE(_cls) \ 5399 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP)) 5400 5401 enum ql_vnd_host_stat_action { 5402 QLA_STOP = 0, 5403 QLA_START, 5404 QLA_CLEAR, 5405 }; 5406 5407 struct ql_vnd_mng_host_stats_param { 5408 u32 stat_type; 5409 enum ql_vnd_host_stat_action action; 5410 } __packed; 5411 5412 struct ql_vnd_mng_host_stats_resp { 5413 u32 status; 5414 } __packed; 5415 5416 struct ql_vnd_stats_param { 5417 u32 stat_type; 5418 } __packed; 5419 5420 struct ql_vnd_tgt_stats_param { 5421 s32 tgt_id; 5422 u32 stat_type; 5423 } __packed; 5424 5425 enum ql_vnd_host_port_action { 5426 QLA_ENABLE = 0, 5427 QLA_DISABLE, 5428 }; 5429 5430 struct ql_vnd_mng_host_port_param { 5431 enum ql_vnd_host_port_action action; 5432 } __packed; 5433 5434 struct ql_vnd_mng_host_port_resp { 5435 u32 status; 5436 } __packed; 5437 5438 struct ql_vnd_stat_entry { 5439 u32 stat_type; /* Failure type */ 5440 u32 tgt_num; /* Target Num */ 5441 u64 cnt; /* Counter value */ 5442 } __packed; 5443 5444 struct ql_vnd_stats { 5445 u64 entry_count; /* Num of entries */ 5446 u64 rservd; 5447 struct ql_vnd_stat_entry entry[]; /* Place holder of entries */ 5448 } __packed; 5449 5450 struct ql_vnd_host_stats_resp { 5451 u32 status; 5452 struct ql_vnd_stats stats; 5453 } __packed; 5454 5455 struct ql_vnd_tgt_stats_resp { 5456 u32 status; 5457 struct ql_vnd_stats stats; 5458 } __packed; 5459 5460 #include "qla_target.h" 5461 #include "qla_gbl.h" 5462 #include "qla_dbg.h" 5463 #include "qla_inline.h" 5464 5465 #define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND || \ 5466 _fcport->disc_state == DSC_DELETED) 5467 5468 #define DBG_FCPORT_PRFMT(_fp, _fmt, _args...) \ 5469 "%s: %8phC: " _fmt " (state=%d disc_state=%d scan_state=%d loopid=0x%x deleted=%d flags=0x%x)\n", \ 5470 __func__, _fp->port_name, ##_args, atomic_read(&_fp->state), \ 5471 _fp->disc_state, _fp->scan_state, _fp->loop_id, _fp->deleted, \ 5472 _fp->flags 5473 5474 #endif 5475