1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #ifndef __QLA_DEF_H 7 #define __QLA_DEF_H 8 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/types.h> 12 #include <linux/module.h> 13 #include <linux/list.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/sched.h> 17 #include <linux/slab.h> 18 #include <linux/dmapool.h> 19 #include <linux/mempool.h> 20 #include <linux/spinlock.h> 21 #include <linux/completion.h> 22 #include <linux/interrupt.h> 23 #include <linux/workqueue.h> 24 #include <linux/firmware.h> 25 #include <linux/mutex.h> 26 #include <linux/btree.h> 27 28 #include <scsi/scsi.h> 29 #include <scsi/scsi_host.h> 30 #include <scsi/scsi_device.h> 31 #include <scsi/scsi_cmnd.h> 32 #include <scsi/scsi_transport_fc.h> 33 #include <scsi/scsi_bsg_fc.h> 34 35 #include <uapi/scsi/fc/fc_els.h> 36 37 #define QLA_DFS_DEFINE_DENTRY(_debugfs_file_name) \ 38 struct dentry *dfs_##_debugfs_file_name 39 #define QLA_DFS_ROOT_DEFINE_DENTRY(_debugfs_file_name) \ 40 struct dentry *qla_dfs_##_debugfs_file_name 41 42 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 43 typedef struct { 44 uint8_t domain; 45 uint8_t area; 46 uint8_t al_pa; 47 } be_id_t; 48 49 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */ 50 typedef struct { 51 uint8_t al_pa; 52 uint8_t area; 53 uint8_t domain; 54 } le_id_t; 55 56 /* 57 * 24 bit port ID type definition. 58 */ 59 typedef union { 60 uint32_t b24 : 24; 61 struct { 62 #ifdef __BIG_ENDIAN 63 uint8_t domain; 64 uint8_t area; 65 uint8_t al_pa; 66 #elif defined(__LITTLE_ENDIAN) 67 uint8_t al_pa; 68 uint8_t area; 69 uint8_t domain; 70 #else 71 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 72 #endif 73 uint8_t rsvd_1; 74 } b; 75 } port_id_t; 76 #define INVALID_PORT_ID 0xFFFFFF 77 78 #include "qla_bsg.h" 79 #include "qla_dsd.h" 80 #include "qla_nx.h" 81 #include "qla_nx2.h" 82 #include "qla_nvme.h" 83 #define QLA2XXX_DRIVER_NAME "qla2xxx" 84 #define QLA2XXX_APIDEV "ql2xapidev" 85 #define QLA2XXX_MANUFACTURER "Marvell Semiconductor, Inc." 86 87 /* 88 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 89 * but that's fine as we don't look at the last 24 ones for 90 * ISP2100 HBAs. 91 */ 92 #define MAILBOX_REGISTER_COUNT_2100 8 93 #define MAILBOX_REGISTER_COUNT_2200 24 94 #define MAILBOX_REGISTER_COUNT 32 95 96 #define QLA2200A_RISC_ROM_VER 4 97 #define FPM_2300 6 98 #define FPM_2310 7 99 100 #include "qla_settings.h" 101 102 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR) 103 104 /* 105 * Data bit definitions 106 */ 107 #define BIT_0 0x1 108 #define BIT_1 0x2 109 #define BIT_2 0x4 110 #define BIT_3 0x8 111 #define BIT_4 0x10 112 #define BIT_5 0x20 113 #define BIT_6 0x40 114 #define BIT_7 0x80 115 #define BIT_8 0x100 116 #define BIT_9 0x200 117 #define BIT_10 0x400 118 #define BIT_11 0x800 119 #define BIT_12 0x1000 120 #define BIT_13 0x2000 121 #define BIT_14 0x4000 122 #define BIT_15 0x8000 123 #define BIT_16 0x10000 124 #define BIT_17 0x20000 125 #define BIT_18 0x40000 126 #define BIT_19 0x80000 127 #define BIT_20 0x100000 128 #define BIT_21 0x200000 129 #define BIT_22 0x400000 130 #define BIT_23 0x800000 131 #define BIT_24 0x1000000 132 #define BIT_25 0x2000000 133 #define BIT_26 0x4000000 134 #define BIT_27 0x8000000 135 #define BIT_28 0x10000000 136 #define BIT_29 0x20000000 137 #define BIT_30 0x40000000 138 #define BIT_31 0x80000000 139 140 #define LSB(x) ((uint8_t)(x)) 141 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 142 143 #define LSW(x) ((uint16_t)(x)) 144 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 145 146 #define LSD(x) ((uint32_t)((uint64_t)(x))) 147 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 148 149 static inline uint32_t make_handle(uint16_t x, uint16_t y) 150 { 151 return ((uint32_t)x << 16) | y; 152 } 153 154 /* 155 * I/O register 156 */ 157 158 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr) 159 { 160 return readb(addr); 161 } 162 163 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr) 164 { 165 return readw(addr); 166 } 167 168 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr) 169 { 170 return readl(addr); 171 } 172 173 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr) 174 { 175 return readb_relaxed(addr); 176 } 177 178 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr) 179 { 180 return readw_relaxed(addr); 181 } 182 183 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr) 184 { 185 return readl_relaxed(addr); 186 } 187 188 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data) 189 { 190 return writeb(data, addr); 191 } 192 193 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data) 194 { 195 return writew(data, addr); 196 } 197 198 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data) 199 { 200 return writel(data, addr); 201 } 202 203 /* 204 * ISP83XX specific remote register addresses 205 */ 206 #define QLA83XX_LED_PORT0 0x00201320 207 #define QLA83XX_LED_PORT1 0x00201328 208 #define QLA83XX_IDC_DEV_STATE 0x22102384 209 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 210 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 211 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 212 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 213 #define QLA83XX_IDC_CONTROL 0x22102390 214 #define QLA83XX_IDC_AUDIT 0x22102394 215 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 216 #define QLA83XX_DRIVER_LOCKID 0x22102104 217 #define QLA83XX_DRIVER_LOCK 0x8111c028 218 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 219 #define QLA83XX_FLASH_LOCKID 0x22102100 220 #define QLA83XX_FLASH_LOCK 0x8111c010 221 #define QLA83XX_FLASH_UNLOCK 0x8111c014 222 #define QLA83XX_DEV_PARTINFO1 0x221023e0 223 #define QLA83XX_DEV_PARTINFO2 0x221023e4 224 #define QLA83XX_FW_HEARTBEAT 0x221020b0 225 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 226 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 227 228 /* 83XX: Macros defining 8200 AEN Reason codes */ 229 #define IDC_DEVICE_STATE_CHANGE BIT_0 230 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 231 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 232 #define IDC_HEARTBEAT_FAILURE BIT_3 233 234 /* 83XX: Macros defining 8200 AEN Error-levels */ 235 #define ERR_LEVEL_NON_FATAL 0x1 236 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 237 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 238 239 /* 83XX: Macros for IDC Version */ 240 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 241 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 242 243 /* 83XX: Macros for scheduling dpc tasks */ 244 #define QLA83XX_NIC_CORE_RESET 0x1 245 #define QLA83XX_IDC_STATE_HANDLER 0x2 246 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 247 248 /* 83XX: Macros for defining IDC-Control bits */ 249 #define QLA83XX_IDC_RESET_DISABLED BIT_0 250 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 251 252 /* 83XX: Macros for different timeouts */ 253 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 254 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 255 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 256 257 /* 83XX: Macros for defining class in DEV-Partition Info register */ 258 #define QLA83XX_CLASS_TYPE_NONE 0x0 259 #define QLA83XX_CLASS_TYPE_NIC 0x1 260 #define QLA83XX_CLASS_TYPE_FCOE 0x2 261 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 262 263 /* 83XX: Macros for IDC Lock-Recovery stages */ 264 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 265 * lock-recovery 266 */ 267 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 268 269 /* 83XX: Macros for IDC Audit type */ 270 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 271 * dev-state change to NEED-RESET 272 * or NEED-QUIESCENT 273 */ 274 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 275 * reset-recovery completion is 276 * second 277 */ 278 /* ISP2031: Values for laser on/off */ 279 #define PORT_0_2031 0x00201340 280 #define PORT_1_2031 0x00201350 281 #define LASER_ON_2031 0x01800100 282 #define LASER_OFF_2031 0x01800180 283 284 /* 285 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 286 * 133Mhz slot. 287 */ 288 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 289 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr)) 290 291 /* 292 * Fibre Channel device definitions. 293 */ 294 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 295 #define MAX_FIBRE_DEVICES_2100 512 296 #define MAX_FIBRE_DEVICES_2400 2048 297 #define MAX_FIBRE_DEVICES_LOOP 128 298 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 299 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 300 #define MAX_FIBRE_LUNS 0xFFFF 301 #define MAX_HOST_COUNT 16 302 303 /* 304 * Host adapter default definitions. 305 */ 306 #define MAX_BUSES 1 /* We only have one bus today */ 307 #define MIN_LUNS 8 308 #define MAX_LUNS MAX_FIBRE_LUNS 309 #define MAX_CMDS_PER_LUN 255 310 311 /* 312 * Fibre Channel device definitions. 313 */ 314 #define SNS_LAST_LOOP_ID_2100 0xfe 315 #define SNS_LAST_LOOP_ID_2300 0x7ff 316 317 #define LAST_LOCAL_LOOP_ID 0x7d 318 #define SNS_FL_PORT 0x7e 319 #define FABRIC_CONTROLLER 0x7f 320 #define SIMPLE_NAME_SERVER 0x80 321 #define SNS_FIRST_LOOP_ID 0x81 322 #define MANAGEMENT_SERVER 0xfe 323 #define BROADCAST 0xff 324 325 /* 326 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 327 * valid range of an N-PORT id is 0 through 0x7ef. 328 */ 329 #define NPH_LAST_HANDLE 0x7ee 330 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */ 331 #define NPH_SNS 0x7fc /* FFFFFC */ 332 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 333 #define NPH_F_PORT 0x7fe /* FFFFFE */ 334 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 335 336 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER) 337 338 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 339 #include "qla_fw.h" 340 341 struct name_list_extended { 342 struct get_name_list_extended *l; 343 dma_addr_t ldma; 344 struct list_head fcports; 345 u32 size; 346 u8 sent; 347 }; 348 349 struct els_reject { 350 struct fc_els_ls_rjt *c; 351 dma_addr_t cdma; 352 u16 size; 353 }; 354 355 /* 356 * Timeout timer counts in seconds 357 */ 358 #define PORT_RETRY_TIME 1 359 #define LOOP_DOWN_TIMEOUT 60 360 #define LOOP_DOWN_TIME 255 /* 240 */ 361 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 362 363 #define DEFAULT_OUTSTANDING_COMMANDS 4096 364 #define MIN_OUTSTANDING_COMMANDS 128 365 366 /* ISP request and response entry counts (37-65535) */ 367 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 368 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 369 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 370 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 371 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 372 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 373 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 374 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 375 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 376 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 377 #define FW_DEF_EXCHANGES_CNT 2048 378 #define FW_MAX_EXCHANGES_CNT (32 * 1024) 379 #define REDUCE_EXCHANGES_CNT (8 * 1024) 380 381 #define SET_DID_STATUS(stat_var, status) (stat_var = status << 16) 382 383 struct req_que; 384 struct qla_tgt_sess; 385 386 struct qla_buf_dsc { 387 u16 tag; 388 #define TAG_FREED 0xffff 389 void *buf; 390 dma_addr_t buf_dma; 391 }; 392 393 /* 394 * SCSI Request Block 395 */ 396 struct srb_cmd { 397 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 398 uint32_t request_sense_length; 399 uint32_t fw_sense_length; 400 uint8_t *request_sense_ptr; 401 struct crc_context *crc_ctx; 402 struct ct6_dsd ct6_ctx; 403 struct qla_buf_dsc buf_dsc; 404 }; 405 406 /* 407 * SRB flag definitions 408 */ 409 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 410 #define SRB_GOT_BUF BIT_1 411 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 412 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 413 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 414 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 415 #define SRB_WAKEUP_ON_COMP BIT_6 416 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */ 417 #define SRB_EDIF_CLEANUP_DELETE BIT_9 418 419 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 420 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 421 #define ISP_REG16_DISCONNECT 0xFFFF 422 423 static inline le_id_t be_id_to_le(be_id_t id) 424 { 425 le_id_t res; 426 427 res.domain = id.domain; 428 res.area = id.area; 429 res.al_pa = id.al_pa; 430 431 return res; 432 } 433 434 static inline be_id_t le_id_to_be(le_id_t id) 435 { 436 be_id_t res; 437 438 res.domain = id.domain; 439 res.area = id.area; 440 res.al_pa = id.al_pa; 441 442 return res; 443 } 444 445 static inline port_id_t be_to_port_id(be_id_t id) 446 { 447 port_id_t res; 448 449 res.b.domain = id.domain; 450 res.b.area = id.area; 451 res.b.al_pa = id.al_pa; 452 res.b.rsvd_1 = 0; 453 454 return res; 455 } 456 457 static inline be_id_t port_id_to_be_id(port_id_t port_id) 458 { 459 be_id_t res; 460 461 res.domain = port_id.b.domain; 462 res.area = port_id.b.area; 463 res.al_pa = port_id.b.al_pa; 464 465 return res; 466 } 467 468 struct tmf_arg { 469 struct qla_qpair *qpair; 470 struct fc_port *fcport; 471 struct scsi_qla_host *vha; 472 u64 lun; 473 u32 flags; 474 uint8_t modifier; 475 }; 476 477 struct els_logo_payload { 478 uint8_t opcode; 479 uint8_t rsvd[3]; 480 uint8_t s_id[3]; 481 uint8_t rsvd1[1]; 482 uint8_t wwpn[WWN_SIZE]; 483 }; 484 485 struct els_plogi_payload { 486 uint8_t opcode; 487 uint8_t rsvd[3]; 488 __be32 data[112 / 4]; 489 }; 490 491 struct ct_arg { 492 void *iocb; 493 u16 nport_handle; 494 dma_addr_t req_dma; 495 dma_addr_t rsp_dma; 496 u32 req_size; 497 u32 rsp_size; 498 u32 req_allocated_size; 499 u32 rsp_allocated_size; 500 void *req; 501 void *rsp; 502 port_id_t id; 503 }; 504 505 /* 506 * SRB extensions. 507 */ 508 struct srb_iocb { 509 union { 510 struct { 511 uint16_t flags; 512 #define SRB_LOGIN_RETRIED BIT_0 513 #define SRB_LOGIN_COND_PLOGI BIT_1 514 #define SRB_LOGIN_SKIP_PRLI BIT_2 515 #define SRB_LOGIN_NVME_PRLI BIT_3 516 #define SRB_LOGIN_PRLI_ONLY BIT_4 517 #define SRB_LOGIN_FCSP BIT_5 518 uint16_t data[2]; 519 u32 iop[2]; 520 } logio; 521 struct { 522 #define ELS_DCMD_TIMEOUT 20 523 #define ELS_DCMD_LOGO 0x5 524 uint32_t flags; 525 uint32_t els_cmd; 526 struct completion comp; 527 struct els_logo_payload *els_logo_pyld; 528 dma_addr_t els_logo_pyld_dma; 529 } els_logo; 530 struct els_plogi { 531 #define ELS_DCMD_PLOGI 0x3 532 uint32_t flags; 533 uint32_t els_cmd; 534 struct completion comp; 535 struct els_plogi_payload *els_plogi_pyld; 536 struct els_plogi_payload *els_resp_pyld; 537 u32 tx_size; 538 u32 rx_size; 539 dma_addr_t els_plogi_pyld_dma; 540 dma_addr_t els_resp_pyld_dma; 541 __le32 fw_status[3]; 542 __le16 comp_status; 543 __le16 len; 544 } els_plogi; 545 struct { 546 /* 547 * Values for flags field below are as 548 * defined in tsk_mgmt_entry struct 549 * for control_flags field in qla_fw.h. 550 */ 551 uint64_t lun; 552 uint32_t flags; 553 uint32_t data; 554 struct completion comp; 555 __le16 comp_status; 556 557 uint8_t modifier; 558 uint8_t vp_index; 559 uint16_t loop_id; 560 } tmf; 561 struct { 562 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 563 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 564 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 565 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 566 #define FXDISC_TIMEOUT 20 567 uint8_t flags; 568 uint32_t req_len; 569 uint32_t rsp_len; 570 void *req_addr; 571 void *rsp_addr; 572 dma_addr_t req_dma_handle; 573 dma_addr_t rsp_dma_handle; 574 __le32 adapter_id; 575 __le32 adapter_id_hi; 576 __le16 req_func_type; 577 __le32 req_data; 578 __le32 req_data_extra; 579 __le32 result; 580 __le32 seq_number; 581 __le16 fw_flags; 582 struct completion fxiocb_comp; 583 __le32 reserved_0; 584 uint8_t reserved_1; 585 } fxiocb; 586 struct { 587 uint32_t cmd_hndl; 588 __le16 comp_status; 589 __le16 req_que_no; 590 struct completion comp; 591 } abt; 592 struct ct_arg ctarg; 593 #define MAX_IOCB_MB_REG 28 594 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t)) 595 struct { 596 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */ 597 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */ 598 void *out, *in; 599 dma_addr_t out_dma, in_dma; 600 struct completion comp; 601 int rc; 602 } mbx; 603 struct { 604 struct imm_ntfy_from_isp *ntfy; 605 } nack; 606 struct { 607 __le16 comp_status; 608 __le16 rsp_pyld_len; 609 uint8_t aen_op; 610 void *desc; 611 612 /* These are only used with ls4 requests */ 613 int cmd_len; 614 int rsp_len; 615 dma_addr_t cmd_dma; 616 dma_addr_t rsp_dma; 617 enum nvmefc_fcp_datadir dir; 618 uint32_t dl; 619 uint32_t timeout_sec; 620 struct list_head entry; 621 } nvme; 622 struct { 623 u16 cmd; 624 u16 vp_index; 625 } ctrlvp; 626 struct { 627 struct edif_sa_ctl *sa_ctl; 628 struct qla_sa_update_frame sa_frame; 629 } sa_update; 630 } u; 631 632 struct timer_list timer; 633 void (*timeout)(void *); 634 }; 635 636 /* Values for srb_ctx type */ 637 #define SRB_LOGIN_CMD 1 638 #define SRB_LOGOUT_CMD 2 639 #define SRB_ELS_CMD_RPT 3 640 #define SRB_ELS_CMD_HST 4 641 #define SRB_CT_CMD 5 642 #define SRB_ADISC_CMD 6 643 #define SRB_TM_CMD 7 644 #define SRB_SCSI_CMD 8 645 #define SRB_BIDI_CMD 9 646 #define SRB_FXIOCB_DCMD 10 647 #define SRB_FXIOCB_BCMD 11 648 #define SRB_ABT_CMD 12 649 #define SRB_ELS_DCMD 13 650 #define SRB_MB_IOCB 14 651 #define SRB_CT_PTHRU_CMD 15 652 #define SRB_NACK_PLOGI 16 653 #define SRB_NACK_PRLI 17 654 #define SRB_NACK_LOGO 18 655 #define SRB_NVME_CMD 19 656 #define SRB_NVME_LS 20 657 #define SRB_PRLI_CMD 21 658 #define SRB_CTRL_VP 22 659 #define SRB_PRLO_CMD 23 660 #define SRB_SA_UPDATE 25 661 #define SRB_ELS_CMD_HST_NOLOGIN 26 662 #define SRB_SA_REPLACE 27 663 #define SRB_MARKER 28 664 665 struct qla_els_pt_arg { 666 u8 els_opcode; 667 u8 vp_idx; 668 __le16 nport_handle; 669 u16 control_flags, ox_id; 670 __le32 rx_xchg_address; 671 port_id_t did, sid; 672 u32 tx_len, tx_byte_count, rx_len, rx_byte_count; 673 dma_addr_t tx_addr, rx_addr; 674 675 }; 676 677 enum { 678 TYPE_SRB, 679 TYPE_TGT_CMD, 680 TYPE_TGT_TMCMD, /* task management */ 681 }; 682 683 struct iocb_resource { 684 u8 res_type; 685 u8 exch_cnt; 686 u16 iocb_cnt; 687 }; 688 689 struct bsg_cmd { 690 struct bsg_job *bsg_job; 691 union { 692 struct qla_els_pt_arg els_arg; 693 } u; 694 }; 695 696 typedef struct srb { 697 /* 698 * Do not move cmd_type field, it needs to 699 * line up with qla_tgt_cmd->cmd_type 700 */ 701 uint8_t cmd_type; 702 uint8_t pad[3]; 703 struct iocb_resource iores; 704 struct kref cmd_kref; /* need to migrate ref_count over to this */ 705 void *priv; 706 wait_queue_head_t nvme_ls_waitq; 707 struct fc_port *fcport; 708 struct scsi_qla_host *vha; 709 unsigned int start_timer:1; 710 711 uint32_t handle; 712 uint16_t flags; 713 uint16_t type; 714 const char *name; 715 int iocbs; 716 struct qla_qpair *qpair; 717 struct srb *cmd_sp; 718 struct list_head elem; 719 u32 gen1; /* scratch */ 720 u32 gen2; /* scratch */ 721 int rc; 722 int retry_count; 723 struct completion *comp; 724 union { 725 struct srb_iocb iocb_cmd; 726 struct bsg_job *bsg_job; 727 struct srb_cmd scmd; 728 struct bsg_cmd bsg_cmd; 729 } u; 730 struct { 731 bool remapped; 732 struct { 733 dma_addr_t dma; 734 void *buf; 735 uint len; 736 } req; 737 struct { 738 dma_addr_t dma; 739 void *buf; 740 uint len; 741 } rsp; 742 } remap; 743 /* 744 * Report completion status @res and call sp_put(@sp). @res is 745 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a 746 * QLA_* status value. 747 */ 748 void (*done)(struct srb *sp, int res); 749 /* Stop the timer and free @sp. Only used by the FCP code. */ 750 void (*free)(struct srb *sp); 751 /* 752 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe 753 * code. 754 */ 755 void (*put_fn)(struct kref *kref); 756 757 /* 758 * Report completion for asynchronous commands. 759 */ 760 void (*async_done)(struct srb *sp, int res); 761 } srb_t; 762 763 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 764 765 #define GET_CMD_SENSE_LEN(sp) \ 766 (sp->u.scmd.request_sense_length) 767 #define SET_CMD_SENSE_LEN(sp, len) \ 768 (sp->u.scmd.request_sense_length = len) 769 #define GET_CMD_SENSE_PTR(sp) \ 770 (sp->u.scmd.request_sense_ptr) 771 #define SET_CMD_SENSE_PTR(sp, ptr) \ 772 (sp->u.scmd.request_sense_ptr = ptr) 773 #define GET_FW_SENSE_LEN(sp) \ 774 (sp->u.scmd.fw_sense_length) 775 #define SET_FW_SENSE_LEN(sp, len) \ 776 (sp->u.scmd.fw_sense_length = len) 777 778 struct msg_echo_lb { 779 dma_addr_t send_dma; 780 dma_addr_t rcv_dma; 781 uint16_t req_sg_cnt; 782 uint16_t rsp_sg_cnt; 783 uint16_t options; 784 uint32_t transfer_size; 785 uint32_t iteration_count; 786 }; 787 788 /* 789 * ISP I/O Register Set structure definitions. 790 */ 791 struct device_reg_2xxx { 792 __le16 flash_address; /* Flash BIOS address */ 793 __le16 flash_data; /* Flash BIOS data */ 794 __le16 unused_1[1]; /* Gap */ 795 __le16 ctrl_status; /* Control/Status */ 796 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 797 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 798 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 799 800 __le16 ictrl; /* Interrupt control */ 801 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 802 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 803 804 __le16 istatus; /* Interrupt status */ 805 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 806 807 __le16 semaphore; /* Semaphore */ 808 __le16 nvram; /* NVRAM register. */ 809 #define NVR_DESELECT 0 810 #define NVR_BUSY BIT_15 811 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 812 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 813 #define NVR_DATA_IN BIT_3 814 #define NVR_DATA_OUT BIT_2 815 #define NVR_SELECT BIT_1 816 #define NVR_CLOCK BIT_0 817 818 #define NVR_WAIT_CNT 20000 819 820 union { 821 struct { 822 __le16 mailbox0; 823 __le16 mailbox1; 824 __le16 mailbox2; 825 __le16 mailbox3; 826 __le16 mailbox4; 827 __le16 mailbox5; 828 __le16 mailbox6; 829 __le16 mailbox7; 830 __le16 unused_2[59]; /* Gap */ 831 } __attribute__((packed)) isp2100; 832 struct { 833 /* Request Queue */ 834 __le16 req_q_in; /* In-Pointer */ 835 __le16 req_q_out; /* Out-Pointer */ 836 /* Response Queue */ 837 __le16 rsp_q_in; /* In-Pointer */ 838 __le16 rsp_q_out; /* Out-Pointer */ 839 840 /* RISC to Host Status */ 841 __le32 host_status; 842 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 843 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 844 845 /* Host to Host Semaphore */ 846 __le16 host_semaphore; 847 __le16 unused_3[17]; /* Gap */ 848 __le16 mailbox0; 849 __le16 mailbox1; 850 __le16 mailbox2; 851 __le16 mailbox3; 852 __le16 mailbox4; 853 __le16 mailbox5; 854 __le16 mailbox6; 855 __le16 mailbox7; 856 __le16 mailbox8; 857 __le16 mailbox9; 858 __le16 mailbox10; 859 __le16 mailbox11; 860 __le16 mailbox12; 861 __le16 mailbox13; 862 __le16 mailbox14; 863 __le16 mailbox15; 864 __le16 mailbox16; 865 __le16 mailbox17; 866 __le16 mailbox18; 867 __le16 mailbox19; 868 __le16 mailbox20; 869 __le16 mailbox21; 870 __le16 mailbox22; 871 __le16 mailbox23; 872 __le16 mailbox24; 873 __le16 mailbox25; 874 __le16 mailbox26; 875 __le16 mailbox27; 876 __le16 mailbox28; 877 __le16 mailbox29; 878 __le16 mailbox30; 879 __le16 mailbox31; 880 __le16 fb_cmd; 881 __le16 unused_4[10]; /* Gap */ 882 } __attribute__((packed)) isp2300; 883 } u; 884 885 __le16 fpm_diag_config; 886 __le16 unused_5[0x4]; /* Gap */ 887 __le16 risc_hw; 888 __le16 unused_5_1; /* Gap */ 889 __le16 pcr; /* Processor Control Register. */ 890 __le16 unused_6[0x5]; /* Gap */ 891 __le16 mctr; /* Memory Configuration and Timing. */ 892 __le16 unused_7[0x3]; /* Gap */ 893 __le16 fb_cmd_2100; /* Unused on 23XX */ 894 __le16 unused_8[0x3]; /* Gap */ 895 __le16 hccr; /* Host command & control register. */ 896 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 897 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 898 /* HCCR commands */ 899 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 900 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 901 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 902 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 903 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 904 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 905 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 906 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 907 908 __le16 unused_9[5]; /* Gap */ 909 __le16 gpiod; /* GPIO Data register. */ 910 __le16 gpioe; /* GPIO Enable register. */ 911 #define GPIO_LED_MASK 0x00C0 912 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 913 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 914 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 915 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 916 #define GPIO_LED_ALL_OFF 0x0000 917 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 918 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 919 920 union { 921 struct { 922 __le16 unused_10[8]; /* Gap */ 923 __le16 mailbox8; 924 __le16 mailbox9; 925 __le16 mailbox10; 926 __le16 mailbox11; 927 __le16 mailbox12; 928 __le16 mailbox13; 929 __le16 mailbox14; 930 __le16 mailbox15; 931 __le16 mailbox16; 932 __le16 mailbox17; 933 __le16 mailbox18; 934 __le16 mailbox19; 935 __le16 mailbox20; 936 __le16 mailbox21; 937 __le16 mailbox22; 938 __le16 mailbox23; /* Also probe reg. */ 939 } __attribute__((packed)) isp2200; 940 } u_end; 941 }; 942 943 struct device_reg_25xxmq { 944 __le32 req_q_in; 945 __le32 req_q_out; 946 __le32 rsp_q_in; 947 __le32 rsp_q_out; 948 __le32 atio_q_in; 949 __le32 atio_q_out; 950 }; 951 952 953 struct device_reg_fx00 { 954 __le32 mailbox0; /* 00 */ 955 __le32 mailbox1; /* 04 */ 956 __le32 mailbox2; /* 08 */ 957 __le32 mailbox3; /* 0C */ 958 __le32 mailbox4; /* 10 */ 959 __le32 mailbox5; /* 14 */ 960 __le32 mailbox6; /* 18 */ 961 __le32 mailbox7; /* 1C */ 962 __le32 mailbox8; /* 20 */ 963 __le32 mailbox9; /* 24 */ 964 __le32 mailbox10; /* 28 */ 965 __le32 mailbox11; 966 __le32 mailbox12; 967 __le32 mailbox13; 968 __le32 mailbox14; 969 __le32 mailbox15; 970 __le32 mailbox16; 971 __le32 mailbox17; 972 __le32 mailbox18; 973 __le32 mailbox19; 974 __le32 mailbox20; 975 __le32 mailbox21; 976 __le32 mailbox22; 977 __le32 mailbox23; 978 __le32 mailbox24; 979 __le32 mailbox25; 980 __le32 mailbox26; 981 __le32 mailbox27; 982 __le32 mailbox28; 983 __le32 mailbox29; 984 __le32 mailbox30; 985 __le32 mailbox31; 986 __le32 aenmailbox0; 987 __le32 aenmailbox1; 988 __le32 aenmailbox2; 989 __le32 aenmailbox3; 990 __le32 aenmailbox4; 991 __le32 aenmailbox5; 992 __le32 aenmailbox6; 993 __le32 aenmailbox7; 994 /* Request Queue. */ 995 __le32 req_q_in; /* A0 - Request Queue In-Pointer */ 996 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */ 997 /* Response Queue. */ 998 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */ 999 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */ 1000 /* Init values shadowed on FW Up Event */ 1001 __le32 initval0; /* B0 */ 1002 __le32 initval1; /* B4 */ 1003 __le32 initval2; /* B8 */ 1004 __le32 initval3; /* BC */ 1005 __le32 initval4; /* C0 */ 1006 __le32 initval5; /* C4 */ 1007 __le32 initval6; /* C8 */ 1008 __le32 initval7; /* CC */ 1009 __le32 fwheartbeat; /* D0 */ 1010 __le32 pseudoaen; /* D4 */ 1011 }; 1012 1013 1014 1015 typedef union { 1016 struct device_reg_2xxx isp; 1017 struct device_reg_24xx isp24; 1018 struct device_reg_25xxmq isp25mq; 1019 struct device_reg_82xx isp82; 1020 struct device_reg_fx00 ispfx00; 1021 } __iomem device_reg_t; 1022 1023 #define ISP_REQ_Q_IN(ha, reg) \ 1024 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1025 &(reg)->u.isp2100.mailbox4 : \ 1026 &(reg)->u.isp2300.req_q_in) 1027 #define ISP_REQ_Q_OUT(ha, reg) \ 1028 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1029 &(reg)->u.isp2100.mailbox4 : \ 1030 &(reg)->u.isp2300.req_q_out) 1031 #define ISP_RSP_Q_IN(ha, reg) \ 1032 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1033 &(reg)->u.isp2100.mailbox5 : \ 1034 &(reg)->u.isp2300.rsp_q_in) 1035 #define ISP_RSP_Q_OUT(ha, reg) \ 1036 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1037 &(reg)->u.isp2100.mailbox5 : \ 1038 &(reg)->u.isp2300.rsp_q_out) 1039 1040 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 1041 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 1042 1043 #define MAILBOX_REG(ha, reg, num) \ 1044 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1045 (num < 8 ? \ 1046 &(reg)->u.isp2100.mailbox0 + (num) : \ 1047 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 1048 &(reg)->u.isp2300.mailbox0 + (num)) 1049 #define RD_MAILBOX_REG(ha, reg, num) \ 1050 rd_reg_word(MAILBOX_REG(ha, reg, num)) 1051 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 1052 wrt_reg_word(MAILBOX_REG(ha, reg, num), data) 1053 1054 #define FB_CMD_REG(ha, reg) \ 1055 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 1056 &(reg)->fb_cmd_2100 : \ 1057 &(reg)->u.isp2300.fb_cmd) 1058 #define RD_FB_CMD_REG(ha, reg) \ 1059 rd_reg_word(FB_CMD_REG(ha, reg)) 1060 #define WRT_FB_CMD_REG(ha, reg, data) \ 1061 wrt_reg_word(FB_CMD_REG(ha, reg), data) 1062 1063 typedef struct { 1064 uint32_t out_mb; /* outbound from driver */ 1065 uint32_t in_mb; /* Incoming from RISC */ 1066 uint16_t mb[MAILBOX_REGISTER_COUNT]; 1067 long buf_size; 1068 void *bufp; 1069 uint32_t tov; 1070 uint8_t flags; 1071 #define MBX_DMA_IN BIT_0 1072 #define MBX_DMA_OUT BIT_1 1073 #define IOCTL_CMD BIT_2 1074 } mbx_cmd_t; 1075 1076 struct mbx_cmd_32 { 1077 uint32_t out_mb; /* outbound from driver */ 1078 uint32_t in_mb; /* Incoming from RISC */ 1079 uint32_t mb[MAILBOX_REGISTER_COUNT]; 1080 long buf_size; 1081 void *bufp; 1082 uint32_t tov; 1083 uint8_t flags; 1084 #define MBX_DMA_IN BIT_0 1085 #define MBX_DMA_OUT BIT_1 1086 #define IOCTL_CMD BIT_2 1087 }; 1088 1089 1090 #define MBX_TOV_SECONDS 30 1091 1092 /* 1093 * ISP product identification definitions in mailboxes after reset. 1094 */ 1095 #define PROD_ID_1 0x4953 1096 #define PROD_ID_2 0x0000 1097 #define PROD_ID_2a 0x5020 1098 #define PROD_ID_3 0x2020 1099 1100 /* 1101 * ISP mailbox Self-Test status codes 1102 */ 1103 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 1104 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 1105 #define MBS_BUSY 4 /* Busy. */ 1106 1107 /* 1108 * ISP mailbox command complete status codes 1109 */ 1110 #define MBS_COMMAND_COMPLETE 0x4000 1111 #define MBS_INVALID_COMMAND 0x4001 1112 #define MBS_HOST_INTERFACE_ERROR 0x4002 1113 #define MBS_TEST_FAILED 0x4003 1114 #define MBS_COMMAND_ERROR 0x4005 1115 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 1116 #define MBS_PORT_ID_USED 0x4007 1117 #define MBS_LOOP_ID_USED 0x4008 1118 #define MBS_ALL_IDS_IN_USE 0x4009 1119 #define MBS_NOT_LOGGED_IN 0x400A 1120 #define MBS_LINK_DOWN_ERROR 0x400B 1121 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 1122 1123 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs) 1124 { 1125 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR; 1126 } 1127 1128 /* 1129 * ISP mailbox asynchronous event status codes 1130 */ 1131 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 1132 #define MBA_RESET 0x8001 /* Reset Detected. */ 1133 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 1134 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 1135 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 1136 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 1137 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 1138 /* occurred. */ 1139 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 1140 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 1141 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 1142 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 1143 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 1144 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 1145 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 1146 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 1147 #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */ 1148 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 1149 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 1150 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 1151 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 1152 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 1153 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 1154 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 1155 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 1156 /* used. */ 1157 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 1158 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 1159 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 1160 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 1161 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 1162 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 1163 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 1164 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 1165 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 1166 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 1167 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 1168 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 1169 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 1170 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 1171 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 1172 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 1173 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 1174 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 1175 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 1176 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 1177 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 1178 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */ 1179 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */ 1180 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 1181 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 1182 Notification */ 1183 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 1184 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 1185 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 1186 /* 83XX FCoE specific */ 1187 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 1188 1189 /* Interrupt type codes */ 1190 #define INTR_ROM_MB_SUCCESS 0x1 1191 #define INTR_ROM_MB_FAILED 0x2 1192 #define INTR_MB_SUCCESS 0x10 1193 #define INTR_MB_FAILED 0x11 1194 #define INTR_ASYNC_EVENT 0x12 1195 #define INTR_RSP_QUE_UPDATE 0x13 1196 #define INTR_RSP_QUE_UPDATE_83XX 0x14 1197 #define INTR_ATIO_QUE_UPDATE 0x1C 1198 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 1199 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E 1200 1201 /* ISP mailbox loopback echo diagnostic error code */ 1202 #define MBS_LB_RESET 0x17 1203 1204 /* AEN mailbox Port Diagnostics test */ 1205 #define AEN_START_DIAG_TEST 0x0 /* start the diagnostics */ 1206 #define AEN_DONE_DIAG_TEST_WITH_NOERR 0x1 /* Done with no errors */ 1207 #define AEN_DONE_DIAG_TEST_WITH_ERR 0x2 /* Done with error.*/ 1208 1209 /* 1210 * Firmware options 1, 2, 3. 1211 */ 1212 #define FO1_AE_ON_LIPF8 BIT_0 1213 #define FO1_AE_ALL_LIP_RESET BIT_1 1214 #define FO1_CTIO_RETRY BIT_3 1215 #define FO1_DISABLE_LIP_F7_SW BIT_4 1216 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 1217 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 1218 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 1219 #define FO1_SET_EMPHASIS_SWING BIT_8 1220 #define FO1_AE_AUTO_BYPASS BIT_9 1221 #define FO1_ENABLE_PURE_IOCB BIT_10 1222 #define FO1_AE_PLOGI_RJT BIT_11 1223 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 1224 #define FO1_AE_QUEUE_FULL BIT_13 1225 1226 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 1227 #define FO2_REV_LOOPBACK BIT_1 1228 1229 #define FO3_ENABLE_EMERG_IOCB BIT_0 1230 #define FO3_AE_RND_ERROR BIT_1 1231 1232 /* 24XX additional firmware options */ 1233 #define ADD_FO_COUNT 3 1234 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 1235 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 1236 1237 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 1238 1239 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 1240 1241 /* 1242 * ISP mailbox commands 1243 */ 1244 #define MBC_LOAD_RAM 1 /* Load RAM. */ 1245 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 1246 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 1247 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 1248 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 1249 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 1250 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 1251 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 1252 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */ 1253 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 1254 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 1255 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 1256 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 1257 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 1258 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 1259 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 1260 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 1261 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 1262 #define MBC_RESET 0x18 /* Reset. */ 1263 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 1264 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */ 1265 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 1266 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 1267 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 1268 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 1269 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 1270 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 1271 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */ 1272 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 1273 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 1274 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 1275 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 1276 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 1277 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 1278 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 1279 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 1280 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 1281 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 1282 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 1283 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 1284 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 1285 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 1286 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 1287 #define MBC_DATA_RATE 0x5d /* Data Rate */ 1288 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 1289 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 1290 /* Initialization Procedure */ 1291 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 1292 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 1293 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 1294 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 1295 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 1296 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 1297 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 1298 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 1299 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 1300 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 1301 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 1302 /* commandd. */ 1303 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 1304 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 1305 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 1306 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 1307 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 1308 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 1309 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 1310 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 1311 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 1312 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 1313 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 1314 1315 /* 1316 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 1317 * should be defined with MBC_MR_* 1318 */ 1319 #define MBC_MR_DRV_SHUTDOWN 0x6A 1320 1321 /* 1322 * ISP24xx mailbox commands 1323 */ 1324 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 1325 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 1326 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 1327 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 1328 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 1329 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 1330 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 1331 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 1332 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 1333 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 1334 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 1335 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 1336 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 1337 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 1338 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 1339 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 1340 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 1341 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 1342 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 1343 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 1344 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 1345 #define MBC_PORT_RESET 0x120 /* Port Reset */ 1346 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 1347 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 1348 1349 /* 1350 * ISP81xx mailbox commands 1351 */ 1352 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 1353 1354 /* 1355 * ISP8044 mailbox commands 1356 */ 1357 #define MBC_SET_GET_ETH_SERDES_REG 0x150 1358 #define HCS_WRITE_SERDES 0x3 1359 #define HCS_READ_SERDES 0x4 1360 1361 /* Firmware return data sizes */ 1362 #define FCAL_MAP_SIZE 128 1363 1364 /* Mailbox bit definitions for out_mb and in_mb */ 1365 #define MBX_31 BIT_31 1366 #define MBX_30 BIT_30 1367 #define MBX_29 BIT_29 1368 #define MBX_28 BIT_28 1369 #define MBX_27 BIT_27 1370 #define MBX_26 BIT_26 1371 #define MBX_25 BIT_25 1372 #define MBX_24 BIT_24 1373 #define MBX_23 BIT_23 1374 #define MBX_22 BIT_22 1375 #define MBX_21 BIT_21 1376 #define MBX_20 BIT_20 1377 #define MBX_19 BIT_19 1378 #define MBX_18 BIT_18 1379 #define MBX_17 BIT_17 1380 #define MBX_16 BIT_16 1381 #define MBX_15 BIT_15 1382 #define MBX_14 BIT_14 1383 #define MBX_13 BIT_13 1384 #define MBX_12 BIT_12 1385 #define MBX_11 BIT_11 1386 #define MBX_10 BIT_10 1387 #define MBX_9 BIT_9 1388 #define MBX_8 BIT_8 1389 #define MBX_7 BIT_7 1390 #define MBX_6 BIT_6 1391 #define MBX_5 BIT_5 1392 #define MBX_4 BIT_4 1393 #define MBX_3 BIT_3 1394 #define MBX_2 BIT_2 1395 #define MBX_1 BIT_1 1396 #define MBX_0 BIT_0 1397 1398 #define RNID_TYPE_ELS_CMD 0x5 1399 #define RNID_TYPE_PORT_LOGIN 0x7 1400 #define RNID_BUFFER_CREDITS 0x8 1401 #define RNID_TYPE_SET_VERSION 0x9 1402 #define RNID_TYPE_ASIC_TEMP 0xC 1403 1404 #define ELS_CMD_MAP_SIZE 32 1405 1406 /* 1407 * Firmware state codes from get firmware state mailbox command 1408 */ 1409 #define FSTATE_CONFIG_WAIT 0 1410 #define FSTATE_WAIT_AL_PA 1 1411 #define FSTATE_WAIT_LOGIN 2 1412 #define FSTATE_READY 3 1413 #define FSTATE_LOSS_OF_SYNC 4 1414 #define FSTATE_ERROR 5 1415 #define FSTATE_REINIT 6 1416 #define FSTATE_NON_PART 7 1417 1418 #define FSTATE_CONFIG_CORRECT 0 1419 #define FSTATE_P2P_RCV_LIP 1 1420 #define FSTATE_P2P_CHOOSE_LOOP 2 1421 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1422 #define FSTATE_FATAL_ERROR 4 1423 #define FSTATE_LOOP_BACK_CONN 5 1424 1425 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1426 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1427 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1428 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1429 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF 1430 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED 1431 #define QLA27XX_DEFAULT_IMAGE 0 1432 #define QLA27XX_PRIMARY_IMAGE 1 1433 #define QLA27XX_SECONDARY_IMAGE 2 1434 1435 /* 1436 * Port Database structure definition 1437 * Little endian except where noted. 1438 */ 1439 #define PORT_DATABASE_SIZE 128 /* bytes */ 1440 typedef struct { 1441 uint8_t options; 1442 uint8_t control; 1443 uint8_t master_state; 1444 uint8_t slave_state; 1445 uint8_t reserved[2]; 1446 uint8_t hard_address; 1447 uint8_t reserved_1; 1448 uint8_t port_id[4]; 1449 uint8_t node_name[WWN_SIZE]; 1450 uint8_t port_name[WWN_SIZE]; 1451 __le16 execution_throttle; 1452 uint16_t execution_count; 1453 uint8_t reset_count; 1454 uint8_t reserved_2; 1455 uint16_t resource_allocation; 1456 uint16_t current_allocation; 1457 uint16_t queue_head; 1458 uint16_t queue_tail; 1459 uint16_t transmit_execution_list_next; 1460 uint16_t transmit_execution_list_previous; 1461 uint16_t common_features; 1462 uint16_t total_concurrent_sequences; 1463 uint16_t RO_by_information_category; 1464 uint8_t recipient; 1465 uint8_t initiator; 1466 uint16_t receive_data_size; 1467 uint16_t concurrent_sequences; 1468 uint16_t open_sequences_per_exchange; 1469 uint16_t lun_abort_flags; 1470 uint16_t lun_stop_flags; 1471 uint16_t stop_queue_head; 1472 uint16_t stop_queue_tail; 1473 uint16_t port_retry_timer; 1474 uint16_t next_sequence_id; 1475 uint16_t frame_count; 1476 uint16_t PRLI_payload_length; 1477 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1478 /* Bits 15-0 of word 0 */ 1479 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1480 /* Bits 15-0 of word 3 */ 1481 uint16_t loop_id; 1482 uint16_t extended_lun_info_list_pointer; 1483 uint16_t extended_lun_stop_list_pointer; 1484 } port_database_t; 1485 1486 /* 1487 * Port database slave/master states 1488 */ 1489 #define PD_STATE_DISCOVERY 0 1490 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1491 #define PD_STATE_PORT_LOGIN 2 1492 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1493 #define PD_STATE_PROCESS_LOGIN 4 1494 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1495 #define PD_STATE_PORT_LOGGED_IN 6 1496 #define PD_STATE_PORT_UNAVAILABLE 7 1497 #define PD_STATE_PROCESS_LOGOUT 8 1498 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1499 #define PD_STATE_PORT_LOGOUT 10 1500 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1501 1502 1503 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1504 #define QLA_ZIO_DISABLED 0 1505 #define QLA_ZIO_DEFAULT_TIMER 2 1506 1507 /* 1508 * ISP Initialization Control Block. 1509 * Little endian except where noted. 1510 */ 1511 #define ICB_VERSION 1 1512 typedef struct { 1513 uint8_t version; 1514 uint8_t reserved_1; 1515 1516 /* 1517 * LSB BIT 0 = Enable Hard Loop Id 1518 * LSB BIT 1 = Enable Fairness 1519 * LSB BIT 2 = Enable Full-Duplex 1520 * LSB BIT 3 = Enable Fast Posting 1521 * LSB BIT 4 = Enable Target Mode 1522 * LSB BIT 5 = Disable Initiator Mode 1523 * LSB BIT 6 = Enable ADISC 1524 * LSB BIT 7 = Enable Target Inquiry Data 1525 * 1526 * MSB BIT 0 = Enable PDBC Notify 1527 * MSB BIT 1 = Non Participating LIP 1528 * MSB BIT 2 = Descending Loop ID Search 1529 * MSB BIT 3 = Acquire Loop ID in LIPA 1530 * MSB BIT 4 = Stop PortQ on Full Status 1531 * MSB BIT 5 = Full Login after LIP 1532 * MSB BIT 6 = Node Name Option 1533 * MSB BIT 7 = Ext IFWCB enable bit 1534 */ 1535 uint8_t firmware_options[2]; 1536 1537 __le16 frame_payload_size; 1538 __le16 max_iocb_allocation; 1539 __le16 execution_throttle; 1540 uint8_t retry_count; 1541 uint8_t retry_delay; /* unused */ 1542 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1543 uint16_t hard_address; 1544 uint8_t inquiry_data; 1545 uint8_t login_timeout; 1546 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1547 1548 __le16 request_q_outpointer; 1549 __le16 response_q_inpointer; 1550 __le16 request_q_length; 1551 __le16 response_q_length; 1552 __le64 request_q_address __packed; 1553 __le64 response_q_address __packed; 1554 1555 __le16 lun_enables; 1556 uint8_t command_resource_count; 1557 uint8_t immediate_notify_resource_count; 1558 __le16 timeout; 1559 uint8_t reserved_2[2]; 1560 1561 /* 1562 * LSB BIT 0 = Timer Operation mode bit 0 1563 * LSB BIT 1 = Timer Operation mode bit 1 1564 * LSB BIT 2 = Timer Operation mode bit 2 1565 * LSB BIT 3 = Timer Operation mode bit 3 1566 * LSB BIT 4 = Init Config Mode bit 0 1567 * LSB BIT 5 = Init Config Mode bit 1 1568 * LSB BIT 6 = Init Config Mode bit 2 1569 * LSB BIT 7 = Enable Non part on LIHA failure 1570 * 1571 * MSB BIT 0 = Enable class 2 1572 * MSB BIT 1 = Enable ACK0 1573 * MSB BIT 2 = 1574 * MSB BIT 3 = 1575 * MSB BIT 4 = FC Tape Enable 1576 * MSB BIT 5 = Enable FC Confirm 1577 * MSB BIT 6 = Enable command queuing in target mode 1578 * MSB BIT 7 = No Logo On Link Down 1579 */ 1580 uint8_t add_firmware_options[2]; 1581 1582 uint8_t response_accumulation_timer; 1583 uint8_t interrupt_delay_timer; 1584 1585 /* 1586 * LSB BIT 0 = Enable Read xfr_rdy 1587 * LSB BIT 1 = Soft ID only 1588 * LSB BIT 2 = 1589 * LSB BIT 3 = 1590 * LSB BIT 4 = FCP RSP Payload [0] 1591 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1592 * LSB BIT 6 = Enable Out-of-Order frame handling 1593 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1594 * 1595 * MSB BIT 0 = Sbus enable - 2300 1596 * MSB BIT 1 = 1597 * MSB BIT 2 = 1598 * MSB BIT 3 = 1599 * MSB BIT 4 = LED mode 1600 * MSB BIT 5 = enable 50 ohm termination 1601 * MSB BIT 6 = Data Rate (2300 only) 1602 * MSB BIT 7 = Data Rate (2300 only) 1603 */ 1604 uint8_t special_options[2]; 1605 1606 uint8_t reserved_3[26]; 1607 } init_cb_t; 1608 1609 /* Special Features Control Block */ 1610 struct init_sf_cb { 1611 uint8_t format; 1612 uint8_t reserved0; 1613 /* 1614 * BIT 15-14 = Reserved 1615 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled) 1616 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled) 1617 * BIT 11-0 = Reserved 1618 */ 1619 __le16 flags; 1620 uint8_t reserved1[32]; 1621 uint16_t discard_OHRB_timeout_value; 1622 uint16_t remote_write_opt_queue_num; 1623 uint8_t reserved2[40]; 1624 uint8_t scm_related_parameter[16]; 1625 uint8_t reserved3[32]; 1626 }; 1627 1628 /* 1629 * Get Link Status mailbox command return buffer. 1630 */ 1631 #define GLSO_SEND_RPS BIT_0 1632 #define GLSO_USE_DID BIT_3 1633 1634 struct link_statistics { 1635 __le32 link_fail_cnt; 1636 __le32 loss_sync_cnt; 1637 __le32 loss_sig_cnt; 1638 __le32 prim_seq_err_cnt; 1639 __le32 inval_xmit_word_cnt; 1640 __le32 inval_crc_cnt; 1641 __le32 lip_cnt; 1642 __le32 link_up_cnt; 1643 __le32 link_down_loop_init_tmo; 1644 __le32 link_down_los; 1645 __le32 link_down_loss_rcv_clk; 1646 uint32_t reserved0[5]; 1647 __le32 port_cfg_chg; 1648 uint32_t reserved1[11]; 1649 __le32 rsp_q_full; 1650 __le32 atio_q_full; 1651 __le32 drop_ae; 1652 __le32 els_proto_err; 1653 __le32 reserved2; 1654 __le32 tx_frames; 1655 __le32 rx_frames; 1656 __le32 discarded_frames; 1657 __le32 dropped_frames; 1658 uint32_t reserved3; 1659 __le32 nos_rcvd; 1660 uint32_t reserved4[4]; 1661 __le32 tx_prjt; 1662 __le32 rcv_exfail; 1663 __le32 rcv_abts; 1664 __le32 seq_frm_miss; 1665 __le32 corr_err; 1666 __le32 mb_rqst; 1667 __le32 nport_full; 1668 __le32 eofa; 1669 uint32_t reserved5; 1670 __le64 fpm_recv_word_cnt; 1671 __le64 fpm_disc_word_cnt; 1672 __le64 fpm_xmit_word_cnt; 1673 uint32_t reserved6[70]; 1674 }; 1675 1676 /* 1677 * NVRAM Command values. 1678 */ 1679 #define NV_START_BIT BIT_2 1680 #define NV_WRITE_OP (BIT_26+BIT_24) 1681 #define NV_READ_OP (BIT_26+BIT_25) 1682 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1683 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1684 #define NV_DELAY_COUNT 10 1685 1686 /* 1687 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1688 */ 1689 typedef struct { 1690 /* 1691 * NVRAM header 1692 */ 1693 uint8_t id[4]; 1694 uint8_t nvram_version; 1695 uint8_t reserved_0; 1696 1697 /* 1698 * NVRAM RISC parameter block 1699 */ 1700 uint8_t parameter_block_version; 1701 uint8_t reserved_1; 1702 1703 /* 1704 * LSB BIT 0 = Enable Hard Loop Id 1705 * LSB BIT 1 = Enable Fairness 1706 * LSB BIT 2 = Enable Full-Duplex 1707 * LSB BIT 3 = Enable Fast Posting 1708 * LSB BIT 4 = Enable Target Mode 1709 * LSB BIT 5 = Disable Initiator Mode 1710 * LSB BIT 6 = Enable ADISC 1711 * LSB BIT 7 = Enable Target Inquiry Data 1712 * 1713 * MSB BIT 0 = Enable PDBC Notify 1714 * MSB BIT 1 = Non Participating LIP 1715 * MSB BIT 2 = Descending Loop ID Search 1716 * MSB BIT 3 = Acquire Loop ID in LIPA 1717 * MSB BIT 4 = Stop PortQ on Full Status 1718 * MSB BIT 5 = Full Login after LIP 1719 * MSB BIT 6 = Node Name Option 1720 * MSB BIT 7 = Ext IFWCB enable bit 1721 */ 1722 uint8_t firmware_options[2]; 1723 1724 __le16 frame_payload_size; 1725 __le16 max_iocb_allocation; 1726 __le16 execution_throttle; 1727 uint8_t retry_count; 1728 uint8_t retry_delay; /* unused */ 1729 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1730 uint16_t hard_address; 1731 uint8_t inquiry_data; 1732 uint8_t login_timeout; 1733 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1734 1735 /* 1736 * LSB BIT 0 = Timer Operation mode bit 0 1737 * LSB BIT 1 = Timer Operation mode bit 1 1738 * LSB BIT 2 = Timer Operation mode bit 2 1739 * LSB BIT 3 = Timer Operation mode bit 3 1740 * LSB BIT 4 = Init Config Mode bit 0 1741 * LSB BIT 5 = Init Config Mode bit 1 1742 * LSB BIT 6 = Init Config Mode bit 2 1743 * LSB BIT 7 = Enable Non part on LIHA failure 1744 * 1745 * MSB BIT 0 = Enable class 2 1746 * MSB BIT 1 = Enable ACK0 1747 * MSB BIT 2 = 1748 * MSB BIT 3 = 1749 * MSB BIT 4 = FC Tape Enable 1750 * MSB BIT 5 = Enable FC Confirm 1751 * MSB BIT 6 = Enable command queuing in target mode 1752 * MSB BIT 7 = No Logo On Link Down 1753 */ 1754 uint8_t add_firmware_options[2]; 1755 1756 uint8_t response_accumulation_timer; 1757 uint8_t interrupt_delay_timer; 1758 1759 /* 1760 * LSB BIT 0 = Enable Read xfr_rdy 1761 * LSB BIT 1 = Soft ID only 1762 * LSB BIT 2 = 1763 * LSB BIT 3 = 1764 * LSB BIT 4 = FCP RSP Payload [0] 1765 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1766 * LSB BIT 6 = Enable Out-of-Order frame handling 1767 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1768 * 1769 * MSB BIT 0 = Sbus enable - 2300 1770 * MSB BIT 1 = 1771 * MSB BIT 2 = 1772 * MSB BIT 3 = 1773 * MSB BIT 4 = LED mode 1774 * MSB BIT 5 = enable 50 ohm termination 1775 * MSB BIT 6 = Data Rate (2300 only) 1776 * MSB BIT 7 = Data Rate (2300 only) 1777 */ 1778 uint8_t special_options[2]; 1779 1780 /* Reserved for expanded RISC parameter block */ 1781 uint8_t reserved_2[22]; 1782 1783 /* 1784 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1785 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1786 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1787 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1788 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1789 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1790 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1791 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1792 * 1793 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1794 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1795 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1796 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1797 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1798 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1799 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1800 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1801 * 1802 * LSB BIT 0 = Output Swing 1G bit 0 1803 * LSB BIT 1 = Output Swing 1G bit 1 1804 * LSB BIT 2 = Output Swing 1G bit 2 1805 * LSB BIT 3 = Output Emphasis 1G bit 0 1806 * LSB BIT 4 = Output Emphasis 1G bit 1 1807 * LSB BIT 5 = Output Swing 2G bit 0 1808 * LSB BIT 6 = Output Swing 2G bit 1 1809 * LSB BIT 7 = Output Swing 2G bit 2 1810 * 1811 * MSB BIT 0 = Output Emphasis 2G bit 0 1812 * MSB BIT 1 = Output Emphasis 2G bit 1 1813 * MSB BIT 2 = Output Enable 1814 * MSB BIT 3 = 1815 * MSB BIT 4 = 1816 * MSB BIT 5 = 1817 * MSB BIT 6 = 1818 * MSB BIT 7 = 1819 */ 1820 uint8_t seriallink_options[4]; 1821 1822 /* 1823 * NVRAM host parameter block 1824 * 1825 * LSB BIT 0 = Enable spinup delay 1826 * LSB BIT 1 = Disable BIOS 1827 * LSB BIT 2 = Enable Memory Map BIOS 1828 * LSB BIT 3 = Enable Selectable Boot 1829 * LSB BIT 4 = Disable RISC code load 1830 * LSB BIT 5 = Set cache line size 1 1831 * LSB BIT 6 = PCI Parity Disable 1832 * LSB BIT 7 = Enable extended logging 1833 * 1834 * MSB BIT 0 = Enable 64bit addressing 1835 * MSB BIT 1 = Enable lip reset 1836 * MSB BIT 2 = Enable lip full login 1837 * MSB BIT 3 = Enable target reset 1838 * MSB BIT 4 = Enable database storage 1839 * MSB BIT 5 = Enable cache flush read 1840 * MSB BIT 6 = Enable database load 1841 * MSB BIT 7 = Enable alternate WWN 1842 */ 1843 uint8_t host_p[2]; 1844 1845 uint8_t boot_node_name[WWN_SIZE]; 1846 uint8_t boot_lun_number; 1847 uint8_t reset_delay; 1848 uint8_t port_down_retry_count; 1849 uint8_t boot_id_number; 1850 __le16 max_luns_per_target; 1851 uint8_t fcode_boot_port_name[WWN_SIZE]; 1852 uint8_t alternate_port_name[WWN_SIZE]; 1853 uint8_t alternate_node_name[WWN_SIZE]; 1854 1855 /* 1856 * BIT 0 = Selective Login 1857 * BIT 1 = Alt-Boot Enable 1858 * BIT 2 = 1859 * BIT 3 = Boot Order List 1860 * BIT 4 = 1861 * BIT 5 = Selective LUN 1862 * BIT 6 = 1863 * BIT 7 = unused 1864 */ 1865 uint8_t efi_parameters; 1866 1867 uint8_t link_down_timeout; 1868 1869 uint8_t adapter_id[16]; 1870 1871 uint8_t alt1_boot_node_name[WWN_SIZE]; 1872 uint16_t alt1_boot_lun_number; 1873 uint8_t alt2_boot_node_name[WWN_SIZE]; 1874 uint16_t alt2_boot_lun_number; 1875 uint8_t alt3_boot_node_name[WWN_SIZE]; 1876 uint16_t alt3_boot_lun_number; 1877 uint8_t alt4_boot_node_name[WWN_SIZE]; 1878 uint16_t alt4_boot_lun_number; 1879 uint8_t alt5_boot_node_name[WWN_SIZE]; 1880 uint16_t alt5_boot_lun_number; 1881 uint8_t alt6_boot_node_name[WWN_SIZE]; 1882 uint16_t alt6_boot_lun_number; 1883 uint8_t alt7_boot_node_name[WWN_SIZE]; 1884 uint16_t alt7_boot_lun_number; 1885 1886 uint8_t reserved_3[2]; 1887 1888 /* Offset 200-215 : Model Number */ 1889 uint8_t model_number[16]; 1890 1891 /* OEM related items */ 1892 uint8_t oem_specific[16]; 1893 1894 /* 1895 * NVRAM Adapter Features offset 232-239 1896 * 1897 * LSB BIT 0 = External GBIC 1898 * LSB BIT 1 = Risc RAM parity 1899 * LSB BIT 2 = Buffer Plus Module 1900 * LSB BIT 3 = Multi Chip Adapter 1901 * LSB BIT 4 = Internal connector 1902 * LSB BIT 5 = 1903 * LSB BIT 6 = 1904 * LSB BIT 7 = 1905 * 1906 * MSB BIT 0 = 1907 * MSB BIT 1 = 1908 * MSB BIT 2 = 1909 * MSB BIT 3 = 1910 * MSB BIT 4 = 1911 * MSB BIT 5 = 1912 * MSB BIT 6 = 1913 * MSB BIT 7 = 1914 */ 1915 uint8_t adapter_features[2]; 1916 1917 uint8_t reserved_4[16]; 1918 1919 /* Subsystem vendor ID for ISP2200 */ 1920 uint16_t subsystem_vendor_id_2200; 1921 1922 /* Subsystem device ID for ISP2200 */ 1923 uint16_t subsystem_device_id_2200; 1924 1925 uint8_t reserved_5; 1926 uint8_t checksum; 1927 } nvram_t; 1928 1929 /* 1930 * ISP queue - response queue entry definition. 1931 */ 1932 typedef struct { 1933 uint8_t entry_type; /* Entry type. */ 1934 uint8_t entry_count; /* Entry count. */ 1935 uint8_t sys_define; /* System defined. */ 1936 uint8_t entry_status; /* Entry Status. */ 1937 uint32_t handle; /* System defined handle */ 1938 uint8_t data[52]; 1939 uint32_t signature; 1940 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1941 } response_t; 1942 1943 /* 1944 * ISP queue - ATIO queue entry definition. 1945 */ 1946 struct atio { 1947 uint8_t entry_type; /* Entry type. */ 1948 uint8_t entry_count; /* Entry count. */ 1949 __le16 attr_n_length; 1950 uint8_t data[56]; 1951 uint32_t signature; 1952 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1953 }; 1954 1955 typedef union { 1956 __le16 extended; 1957 struct { 1958 uint8_t reserved; 1959 uint8_t standard; 1960 } id; 1961 } target_id_t; 1962 1963 #define SET_TARGET_ID(ha, to, from) \ 1964 do { \ 1965 if (HAS_EXTENDED_IDS(ha)) \ 1966 to.extended = cpu_to_le16(from); \ 1967 else \ 1968 to.id.standard = (uint8_t)from; \ 1969 } while (0) 1970 1971 /* 1972 * ISP queue - command entry structure definition. 1973 */ 1974 #define COMMAND_TYPE 0x11 /* Command entry */ 1975 typedef struct { 1976 uint8_t entry_type; /* Entry type. */ 1977 uint8_t entry_count; /* Entry count. */ 1978 uint8_t sys_define; /* System defined. */ 1979 uint8_t entry_status; /* Entry Status. */ 1980 uint32_t handle; /* System handle. */ 1981 target_id_t target; /* SCSI ID */ 1982 __le16 lun; /* SCSI LUN */ 1983 __le16 control_flags; /* Control flags. */ 1984 #define CF_WRITE BIT_6 1985 #define CF_READ BIT_5 1986 #define CF_SIMPLE_TAG BIT_3 1987 #define CF_ORDERED_TAG BIT_2 1988 #define CF_HEAD_TAG BIT_1 1989 uint16_t reserved_1; 1990 __le16 timeout; /* Command timeout. */ 1991 __le16 dseg_count; /* Data segment count. */ 1992 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1993 __le32 byte_count; /* Total byte count. */ 1994 union { 1995 struct dsd32 dsd32[3]; 1996 struct dsd64 dsd64[2]; 1997 }; 1998 } cmd_entry_t; 1999 2000 /* 2001 * ISP queue - 64-Bit addressing, command entry structure definition. 2002 */ 2003 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 2004 typedef struct { 2005 uint8_t entry_type; /* Entry type. */ 2006 uint8_t entry_count; /* Entry count. */ 2007 uint8_t sys_define; /* System defined. */ 2008 uint8_t entry_status; /* Entry Status. */ 2009 uint32_t handle; /* System handle. */ 2010 target_id_t target; /* SCSI ID */ 2011 __le16 lun; /* SCSI LUN */ 2012 __le16 control_flags; /* Control flags. */ 2013 uint16_t reserved_1; 2014 __le16 timeout; /* Command timeout. */ 2015 __le16 dseg_count; /* Data segment count. */ 2016 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 2017 uint32_t byte_count; /* Total byte count. */ 2018 struct dsd64 dsd[2]; 2019 } cmd_a64_entry_t, request_t; 2020 2021 /* 2022 * ISP queue - continuation entry structure definition. 2023 */ 2024 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 2025 typedef struct { 2026 uint8_t entry_type; /* Entry type. */ 2027 uint8_t entry_count; /* Entry count. */ 2028 uint8_t sys_define; /* System defined. */ 2029 uint8_t entry_status; /* Entry Status. */ 2030 uint32_t reserved; 2031 struct dsd32 dsd[7]; 2032 } cont_entry_t; 2033 2034 /* 2035 * ISP queue - 64-Bit addressing, continuation entry structure definition. 2036 */ 2037 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 2038 typedef struct { 2039 uint8_t entry_type; /* Entry type. */ 2040 uint8_t entry_count; /* Entry count. */ 2041 uint8_t sys_define; /* System defined. */ 2042 uint8_t entry_status; /* Entry Status. */ 2043 struct dsd64 dsd[5]; 2044 } cont_a64_entry_t; 2045 2046 #define PO_MODE_DIF_INSERT 0 2047 #define PO_MODE_DIF_REMOVE 1 2048 #define PO_MODE_DIF_PASS 2 2049 #define PO_MODE_DIF_REPLACE 3 2050 #define PO_MODE_DIF_TCP_CKSUM 6 2051 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 2052 #define PO_DISABLE_GUARD_CHECK BIT_4 2053 #define PO_DISABLE_INCR_REF_TAG BIT_5 2054 #define PO_DIS_HEADER_MODE BIT_7 2055 #define PO_ENABLE_DIF_BUNDLING BIT_8 2056 #define PO_DIS_FRAME_MODE BIT_9 2057 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 2058 #define PO_DIS_VALD_APP_REF_ESC BIT_11 2059 2060 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 2061 #define PO_DIS_REF_TAG_REPL BIT_13 2062 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 2063 #define PO_DIS_REF_TAG_VALD BIT_15 2064 2065 /* 2066 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 2067 */ 2068 struct crc_context { 2069 uint32_t handle; /* System handle. */ 2070 __le32 ref_tag; 2071 __le16 app_tag; 2072 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 2073 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 2074 __le16 guard_seed; /* Initial Guard Seed */ 2075 __le16 prot_opts; /* Requested Data Protection Mode */ 2076 __le16 blk_size; /* Data size in bytes */ 2077 __le16 runt_blk_guard; /* Guard value for runt block (tape 2078 * only) */ 2079 __le32 byte_count; /* Total byte count/ total data 2080 * transfer count */ 2081 union { 2082 struct { 2083 uint32_t reserved_1; 2084 uint16_t reserved_2; 2085 uint16_t reserved_3; 2086 uint32_t reserved_4; 2087 struct dsd64 data_dsd[1]; 2088 uint32_t reserved_5[2]; 2089 uint32_t reserved_6; 2090 } nobundling; 2091 struct { 2092 __le32 dif_byte_count; /* Total DIF byte 2093 * count */ 2094 uint16_t reserved_1; 2095 __le16 dseg_count; /* Data segment count */ 2096 uint32_t reserved_2; 2097 struct dsd64 data_dsd[1]; 2098 struct dsd64 dif_dsd; 2099 } bundling; 2100 } u; 2101 2102 struct fcp_cmnd fcp_cmnd; 2103 dma_addr_t crc_ctx_dma; 2104 /* List of DMA context transfers */ 2105 struct list_head dsd_list; 2106 2107 /* List of DIF Bundling context DMA address */ 2108 struct list_head ldif_dsd_list; 2109 u8 no_ldif_dsd; 2110 2111 struct list_head ldif_dma_hndl_list; 2112 u32 dif_bundl_len; 2113 u8 no_dif_bundl; 2114 /* This structure should not exceed 512 bytes */ 2115 }; 2116 2117 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 2118 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 2119 2120 /* 2121 * ISP queue - status entry structure definition. 2122 */ 2123 #define STATUS_TYPE 0x03 /* Status entry. */ 2124 typedef struct { 2125 uint8_t entry_type; /* Entry type. */ 2126 uint8_t entry_count; /* Entry count. */ 2127 uint8_t sys_define; /* System defined. */ 2128 uint8_t entry_status; /* Entry Status. */ 2129 uint32_t handle; /* System handle. */ 2130 __le16 scsi_status; /* SCSI status. */ 2131 __le16 comp_status; /* Completion status. */ 2132 __le16 state_flags; /* State flags. */ 2133 __le16 status_flags; /* Status flags. */ 2134 __le16 rsp_info_len; /* Response Info Length. */ 2135 __le16 req_sense_length; /* Request sense data length. */ 2136 __le32 residual_length; /* Residual transfer length. */ 2137 uint8_t rsp_info[8]; /* FCP response information. */ 2138 uint8_t req_sense_data[32]; /* Request sense data. */ 2139 } sts_entry_t; 2140 2141 /* 2142 * Status entry entry status 2143 */ 2144 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 2145 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 2146 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 2147 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 2148 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 2149 #define RF_BUSY BIT_1 /* Busy */ 2150 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 2151 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 2152 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 2153 RF_INV_E_TYPE) 2154 2155 /* 2156 * Status entry SCSI status bit definitions. 2157 */ 2158 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 2159 #define SS_RESIDUAL_UNDER BIT_11 2160 #define SS_RESIDUAL_OVER BIT_10 2161 #define SS_SENSE_LEN_VALID BIT_9 2162 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 2163 #define SS_SCSI_STATUS_BYTE 0xff 2164 2165 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 2166 #define SS_BUSY_CONDITION BIT_3 2167 #define SS_CONDITION_MET BIT_2 2168 #define SS_CHECK_CONDITION BIT_1 2169 2170 /* 2171 * Status entry completion status 2172 */ 2173 #define CS_COMPLETE 0x0 /* No errors */ 2174 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 2175 #define CS_DMA 0x2 /* A DMA direction error. */ 2176 #define CS_TRANSPORT 0x3 /* Transport error. */ 2177 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 2178 #define CS_ABORTED 0x5 /* System aborted command. */ 2179 #define CS_TIMEOUT 0x6 /* Timeout error. */ 2180 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 2181 #define CS_DIF_ERROR 0xC /* DIF error detected */ 2182 2183 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 2184 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 2185 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 2186 /* (selection timeout) */ 2187 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 2188 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 2189 #define CS_PORT_BUSY 0x2B /* Port Busy */ 2190 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 2191 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 2192 failure */ 2193 #define CS_REJECT_RECEIVED 0x4E /* Reject received */ 2194 #define CS_EDIF_AUTH_ERROR 0x63 /* decrypt error */ 2195 #define CS_EDIF_PAD_LEN_ERROR 0x65 /* pad > frame size, not 4byte align */ 2196 #define CS_EDIF_INV_REQ 0x66 /* invalid request */ 2197 #define CS_EDIF_SPI_ERROR 0x67 /* rx frame unable to locate sa */ 2198 #define CS_EDIF_HDR_ERROR 0x69 /* data frame != expected len */ 2199 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 2200 #define CS_UNKNOWN 0x81 /* Driver defined */ 2201 #define CS_RETRY 0x82 /* Driver defined */ 2202 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 2203 2204 #define CS_BIDIR_RD_OVERRUN 0x700 2205 #define CS_BIDIR_RD_WR_OVERRUN 0x707 2206 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 2207 #define CS_BIDIR_RD_UNDERRUN 0x1500 2208 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 2209 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 2210 #define CS_BIDIR_DMA 0x200 2211 /* 2212 * Status entry status flags 2213 */ 2214 #define SF_ABTS_TERMINATED BIT_10 2215 #define SF_LOGOUT_SENT BIT_13 2216 2217 /* 2218 * ISP queue - status continuation entry structure definition. 2219 */ 2220 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 2221 typedef struct { 2222 uint8_t entry_type; /* Entry type. */ 2223 uint8_t entry_count; /* Entry count. */ 2224 uint8_t sys_define; /* System defined. */ 2225 uint8_t entry_status; /* Entry Status. */ 2226 uint8_t data[60]; /* data */ 2227 } sts_cont_entry_t; 2228 2229 /* 2230 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 2231 * structure definition. 2232 */ 2233 #define STATUS_TYPE_21 0x21 /* Status entry. */ 2234 typedef struct { 2235 uint8_t entry_type; /* Entry type. */ 2236 uint8_t entry_count; /* Entry count. */ 2237 uint8_t handle_count; /* Handle count. */ 2238 uint8_t entry_status; /* Entry Status. */ 2239 uint32_t handle[15]; /* System handles. */ 2240 } sts21_entry_t; 2241 2242 /* 2243 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 2244 * structure definition. 2245 */ 2246 #define STATUS_TYPE_22 0x22 /* Status entry. */ 2247 typedef struct { 2248 uint8_t entry_type; /* Entry type. */ 2249 uint8_t entry_count; /* Entry count. */ 2250 uint8_t handle_count; /* Handle count. */ 2251 uint8_t entry_status; /* Entry Status. */ 2252 uint16_t handle[30]; /* System handles. */ 2253 } sts22_entry_t; 2254 2255 /* 2256 * ISP queue - marker entry structure definition. 2257 */ 2258 #define MARKER_TYPE 0x04 /* Marker entry. */ 2259 typedef struct { 2260 uint8_t entry_type; /* Entry type. */ 2261 uint8_t entry_count; /* Entry count. */ 2262 uint8_t handle_count; /* Handle count. */ 2263 uint8_t entry_status; /* Entry Status. */ 2264 uint32_t sys_define_2; /* System defined. */ 2265 target_id_t target; /* SCSI ID */ 2266 uint8_t modifier; /* Modifier (7-0). */ 2267 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 2268 #define MK_SYNC_ID 1 /* Synchronize ID */ 2269 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 2270 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 2271 /* clear port changed, */ 2272 /* use sequence number. */ 2273 uint8_t reserved_1; 2274 __le16 sequence_number; /* Sequence number of event */ 2275 __le16 lun; /* SCSI LUN */ 2276 uint8_t reserved_2[48]; 2277 } mrk_entry_t; 2278 2279 /* 2280 * ISP queue - Management Server entry structure definition. 2281 */ 2282 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 2283 typedef struct { 2284 uint8_t entry_type; /* Entry type. */ 2285 uint8_t entry_count; /* Entry count. */ 2286 uint8_t handle_count; /* Handle count. */ 2287 uint8_t entry_status; /* Entry Status. */ 2288 uint32_t handle1; /* System handle. */ 2289 target_id_t loop_id; 2290 __le16 status; 2291 __le16 control_flags; /* Control flags. */ 2292 uint16_t reserved2; 2293 __le16 timeout; 2294 __le16 cmd_dsd_count; 2295 __le16 total_dsd_count; 2296 uint8_t type; 2297 uint8_t r_ctl; 2298 __le16 rx_id; 2299 uint16_t reserved3; 2300 uint32_t handle2; 2301 __le32 rsp_bytecount; 2302 __le32 req_bytecount; 2303 struct dsd64 req_dsd; 2304 struct dsd64 rsp_dsd; 2305 } ms_iocb_entry_t; 2306 2307 #define SCM_EDC_ACC_RECEIVED BIT_6 2308 #define SCM_RDF_ACC_RECEIVED BIT_7 2309 2310 /* 2311 * ISP queue - Mailbox Command entry structure definition. 2312 */ 2313 #define MBX_IOCB_TYPE 0x39 2314 struct mbx_entry { 2315 uint8_t entry_type; 2316 uint8_t entry_count; 2317 uint8_t sys_define1; 2318 /* Use sys_define1 for source type */ 2319 #define SOURCE_SCSI 0x00 2320 #define SOURCE_IP 0x01 2321 #define SOURCE_VI 0x02 2322 #define SOURCE_SCTP 0x03 2323 #define SOURCE_MP 0x04 2324 #define SOURCE_MPIOCTL 0x05 2325 #define SOURCE_ASYNC_IOCB 0x07 2326 2327 uint8_t entry_status; 2328 2329 uint32_t handle; 2330 target_id_t loop_id; 2331 2332 __le16 status; 2333 __le16 state_flags; 2334 __le16 status_flags; 2335 2336 uint32_t sys_define2[2]; 2337 2338 __le16 mb0; 2339 __le16 mb1; 2340 __le16 mb2; 2341 __le16 mb3; 2342 __le16 mb6; 2343 __le16 mb7; 2344 __le16 mb9; 2345 __le16 mb10; 2346 uint32_t reserved_2[2]; 2347 uint8_t node_name[WWN_SIZE]; 2348 uint8_t port_name[WWN_SIZE]; 2349 }; 2350 2351 #ifndef IMMED_NOTIFY_TYPE 2352 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */ 2353 /* 2354 * ISP queue - immediate notify entry structure definition. 2355 * This is sent by the ISP to the Target driver. 2356 * This IOCB would have report of events sent by the 2357 * initiator, that needs to be handled by the target 2358 * driver immediately. 2359 */ 2360 struct imm_ntfy_from_isp { 2361 uint8_t entry_type; /* Entry type. */ 2362 uint8_t entry_count; /* Entry count. */ 2363 uint8_t sys_define; /* System defined. */ 2364 uint8_t entry_status; /* Entry Status. */ 2365 union { 2366 struct { 2367 __le32 sys_define_2; /* System defined. */ 2368 target_id_t target; 2369 __le16 lun; 2370 uint8_t target_id; 2371 uint8_t reserved_1; 2372 __le16 status_modifier; 2373 __le16 status; 2374 __le16 task_flags; 2375 __le16 seq_id; 2376 __le16 srr_rx_id; 2377 __le32 srr_rel_offs; 2378 __le16 srr_ui; 2379 #define SRR_IU_DATA_IN 0x1 2380 #define SRR_IU_DATA_OUT 0x5 2381 #define SRR_IU_STATUS 0x7 2382 __le16 srr_ox_id; 2383 uint8_t reserved_2[28]; 2384 } isp2x; 2385 struct { 2386 uint32_t reserved; 2387 __le16 nport_handle; 2388 uint16_t reserved_2; 2389 __le16 flags; 2390 #define NOTIFY24XX_FLAGS_FCSP BIT_5 2391 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1 2392 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0 2393 __le16 srr_rx_id; 2394 __le16 status; 2395 uint8_t status_subcode; 2396 uint8_t fw_handle; 2397 __le32 exchange_address; 2398 __le32 srr_rel_offs; 2399 __le16 srr_ui; 2400 __le16 srr_ox_id; 2401 union { 2402 struct { 2403 uint8_t node_name[8]; 2404 } plogi; /* PLOGI/ADISC/PDISC */ 2405 struct { 2406 /* PRLI word 3 bit 0-15 */ 2407 __le16 wd3_lo; 2408 uint8_t resv0[6]; 2409 } prli; 2410 struct { 2411 uint8_t port_id[3]; 2412 uint8_t resv1; 2413 __le16 nport_handle; 2414 uint16_t resv2; 2415 } req_els; 2416 } u; 2417 uint8_t port_name[8]; 2418 uint8_t resv3[3]; 2419 uint8_t vp_index; 2420 uint32_t reserved_5; 2421 uint8_t port_id[3]; 2422 uint8_t reserved_6; 2423 } isp24; 2424 } u; 2425 uint16_t reserved_7; 2426 __le16 ox_id; 2427 } __packed; 2428 #endif 2429 2430 /* 2431 * ISP request and response queue entry sizes 2432 */ 2433 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 2434 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 2435 2436 2437 2438 /* 2439 * Switch info gathering structure. 2440 */ 2441 typedef struct { 2442 port_id_t d_id; 2443 uint8_t node_name[WWN_SIZE]; 2444 uint8_t port_name[WWN_SIZE]; 2445 uint8_t fabric_port_name[WWN_SIZE]; 2446 uint16_t fp_speed; 2447 uint8_t fc4_type; 2448 uint8_t fc4_features; 2449 } sw_info_t; 2450 2451 /* FCP-4 types */ 2452 #define FC4_TYPE_FCP_SCSI 0x08 2453 #define FC4_TYPE_NVME 0x28 2454 #define FC4_TYPE_OTHER 0x0 2455 #define FC4_TYPE_UNKNOWN 0xff 2456 2457 /* mailbox command 4G & above */ 2458 struct mbx_24xx_entry { 2459 uint8_t entry_type; 2460 uint8_t entry_count; 2461 uint8_t sys_define1; 2462 uint8_t entry_status; 2463 uint32_t handle; 2464 uint16_t mb[28]; 2465 }; 2466 2467 #define IOCB_SIZE 64 2468 2469 /* 2470 * Fibre channel port type. 2471 */ 2472 typedef enum { 2473 FCT_UNKNOWN, 2474 FCT_BROADCAST = 0x01, 2475 FCT_INITIATOR = 0x02, 2476 FCT_TARGET = 0x04, 2477 FCT_NVME_INITIATOR = 0x10, 2478 FCT_NVME_TARGET = 0x20, 2479 FCT_NVME_DISCOVERY = 0x40, 2480 FCT_NVME = 0xf0, 2481 } fc_port_type_t; 2482 2483 enum qla_sess_deletion { 2484 QLA_SESS_DELETION_NONE = 0, 2485 QLA_SESS_DELETION_IN_PROGRESS, 2486 QLA_SESS_DELETED, 2487 }; 2488 2489 enum qlt_plogi_link_t { 2490 QLT_PLOGI_LINK_SAME_WWN, 2491 QLT_PLOGI_LINK_CONFLICT, 2492 QLT_PLOGI_LINK_MAX 2493 }; 2494 2495 struct qlt_plogi_ack_t { 2496 struct list_head list; 2497 struct imm_ntfy_from_isp iocb; 2498 port_id_t id; 2499 int ref_count; 2500 void *fcport; 2501 }; 2502 2503 struct ct_sns_desc { 2504 struct ct_sns_pkt *ct_sns; 2505 dma_addr_t ct_sns_dma; 2506 }; 2507 2508 enum discovery_state { 2509 DSC_DELETED, 2510 DSC_GNL, 2511 DSC_LOGIN_PEND, 2512 DSC_LOGIN_FAILED, 2513 DSC_GPDB, 2514 DSC_UPD_FCPORT, 2515 DSC_LOGIN_COMPLETE, 2516 DSC_ADISC, 2517 DSC_DELETE_PEND, 2518 DSC_LOGIN_AUTH_PEND, 2519 }; 2520 2521 enum login_state { /* FW control Target side */ 2522 DSC_LS_LLIOCB_SENT = 2, 2523 DSC_LS_PLOGI_PEND, 2524 DSC_LS_PLOGI_COMP, 2525 DSC_LS_PRLI_PEND, 2526 DSC_LS_PRLI_COMP, 2527 DSC_LS_PORT_UNAVAIL, 2528 DSC_LS_PRLO_PEND = 9, 2529 DSC_LS_LOGO_PEND, 2530 }; 2531 2532 enum rscn_addr_format { 2533 RSCN_PORT_ADDR, 2534 RSCN_AREA_ADDR, 2535 RSCN_DOM_ADDR, 2536 RSCN_FAB_ADDR, 2537 }; 2538 2539 /* 2540 * Fibre channel port structure. 2541 */ 2542 typedef struct fc_port { 2543 struct list_head list; 2544 struct scsi_qla_host *vha; 2545 struct list_head tmf_pending; 2546 2547 unsigned int conf_compl_supported:1; 2548 unsigned int deleted:2; 2549 unsigned int free_pending:1; 2550 unsigned int local:1; 2551 unsigned int logout_on_delete:1; 2552 unsigned int logo_ack_needed:1; 2553 unsigned int keep_nport_handle:1; 2554 unsigned int send_els_logo:1; 2555 unsigned int login_pause:1; 2556 unsigned int login_succ:1; 2557 unsigned int query:1; 2558 unsigned int id_changed:1; 2559 unsigned int scan_needed:1; 2560 unsigned int n2n_flag:1; 2561 unsigned int explicit_logout:1; 2562 unsigned int prli_pend_timer:1; 2563 unsigned int do_prli_nvme:1; 2564 2565 uint8_t nvme_flag; 2566 uint8_t active_tmf; 2567 #define MAX_ACTIVE_TMF 8 2568 2569 uint8_t node_name[WWN_SIZE]; 2570 uint8_t port_name[WWN_SIZE]; 2571 port_id_t d_id; 2572 uint16_t loop_id; 2573 uint16_t old_loop_id; 2574 2575 struct completion nvme_del_done; 2576 uint32_t nvme_prli_service_param; 2577 #define NVME_PRLI_SP_PI_CTRL BIT_9 2578 #define NVME_PRLI_SP_SLER BIT_8 2579 #define NVME_PRLI_SP_CONF BIT_7 2580 #define NVME_PRLI_SP_INITIATOR BIT_5 2581 #define NVME_PRLI_SP_TARGET BIT_4 2582 #define NVME_PRLI_SP_DISCOVERY BIT_3 2583 #define NVME_PRLI_SP_FIRST_BURST BIT_0 2584 2585 uint32_t nvme_first_burst_size; 2586 #define NVME_FLAG_REGISTERED 4 2587 #define NVME_FLAG_DELETING 2 2588 #define NVME_FLAG_RESETTING 1 2589 2590 struct fc_port *conflict; 2591 unsigned char logout_completed; 2592 int generation; 2593 2594 struct se_session *se_sess; 2595 struct list_head sess_cmd_list; 2596 spinlock_t sess_cmd_lock; 2597 struct kref sess_kref; 2598 struct qla_tgt *tgt; 2599 unsigned long expires; 2600 struct list_head del_list_entry; 2601 struct work_struct free_work; 2602 struct work_struct reg_work; 2603 uint64_t jiffies_at_registration; 2604 unsigned long prli_expired; 2605 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX]; 2606 2607 uint16_t tgt_id; 2608 uint16_t old_tgt_id; 2609 uint16_t sec_since_registration; 2610 2611 uint8_t fcp_prio; 2612 2613 uint8_t fabric_port_name[WWN_SIZE]; 2614 uint16_t fp_speed; 2615 2616 fc_port_type_t port_type; 2617 2618 atomic_t state; 2619 uint32_t flags; 2620 2621 int login_retry; 2622 2623 struct fc_rport *rport; 2624 u32 supported_classes; 2625 2626 uint8_t fc4_type; 2627 uint8_t fc4_features; 2628 uint8_t scan_state; 2629 2630 unsigned long last_queue_full; 2631 unsigned long last_ramp_up; 2632 2633 uint16_t port_id; 2634 2635 struct nvme_fc_remote_port *nvme_remote_port; 2636 2637 unsigned long retry_delay_timestamp; 2638 struct qla_tgt_sess *tgt_session; 2639 struct ct_sns_desc ct_desc; 2640 enum discovery_state disc_state; 2641 atomic_t shadow_disc_state; 2642 enum discovery_state next_disc_state; 2643 enum login_state fw_login_state; 2644 unsigned long dm_login_expire; 2645 unsigned long plogi_nack_done_deadline; 2646 2647 u32 login_gen, last_login_gen; 2648 u32 rscn_gen, last_rscn_gen; 2649 u32 chip_reset; 2650 struct list_head gnl_entry; 2651 struct work_struct del_work; 2652 u8 iocb[IOCB_SIZE]; 2653 u8 current_login_state; 2654 u8 last_login_state; 2655 u16 n2n_link_reset_cnt; 2656 u16 n2n_chip_reset; 2657 2658 struct dentry *dfs_rport_dir; 2659 2660 u64 tgt_short_link_down_cnt; 2661 u64 tgt_link_down_time; 2662 u64 dev_loss_tmo; 2663 /* 2664 * EDIF parameters for encryption. 2665 */ 2666 struct { 2667 uint32_t enable:1; /* device is edif enabled/req'd */ 2668 uint32_t app_stop:2; 2669 uint32_t aes_gmac:1; 2670 uint32_t app_sess_online:1; 2671 uint32_t tx_sa_set:1; 2672 uint32_t rx_sa_set:1; 2673 uint32_t tx_sa_pending:1; 2674 uint32_t rx_sa_pending:1; 2675 uint32_t tx_rekey_cnt; 2676 uint32_t rx_rekey_cnt; 2677 uint64_t tx_bytes; 2678 uint64_t rx_bytes; 2679 uint8_t sess_down_acked; 2680 uint8_t auth_state; 2681 uint16_t authok:1; 2682 uint16_t rekey_cnt; 2683 struct list_head edif_indx_list; 2684 spinlock_t indx_list_lock; 2685 2686 struct list_head tx_sa_list; 2687 struct list_head rx_sa_list; 2688 spinlock_t sa_list_lock; 2689 } edif; 2690 } fc_port_t; 2691 2692 enum { 2693 FC4_PRIORITY_NVME = 1, 2694 FC4_PRIORITY_FCP = 2, 2695 }; 2696 2697 #define QLA_FCPORT_SCAN 1 2698 #define QLA_FCPORT_FOUND 2 2699 2700 struct event_arg { 2701 fc_port_t *fcport; 2702 srb_t *sp; 2703 port_id_t id; 2704 u16 data[2], rc; 2705 u8 port_name[WWN_SIZE]; 2706 u32 iop[2]; 2707 }; 2708 2709 #include "qla_mr.h" 2710 2711 /* 2712 * Fibre channel port/lun states. 2713 */ 2714 enum { 2715 FCS_UNKNOWN, 2716 FCS_UNCONFIGURED, 2717 FCS_DEVICE_DEAD, 2718 FCS_DEVICE_LOST, 2719 FCS_ONLINE, 2720 }; 2721 2722 extern const char *const port_state_str[5]; 2723 2724 static const char *const port_dstate_str[] = { 2725 [DSC_DELETED] = "DELETED", 2726 [DSC_GNL] = "GNL", 2727 [DSC_LOGIN_PEND] = "LOGIN_PEND", 2728 [DSC_LOGIN_FAILED] = "LOGIN_FAILED", 2729 [DSC_GPDB] = "GPDB", 2730 [DSC_UPD_FCPORT] = "UPD_FCPORT", 2731 [DSC_LOGIN_COMPLETE] = "LOGIN_COMPLETE", 2732 [DSC_ADISC] = "ADISC", 2733 [DSC_DELETE_PEND] = "DELETE_PEND", 2734 [DSC_LOGIN_AUTH_PEND] = "LOGIN_AUTH_PEND", 2735 }; 2736 2737 /* 2738 * FC port flags. 2739 */ 2740 #define FCF_FABRIC_DEVICE BIT_0 2741 #define FCF_LOGIN_NEEDED BIT_1 2742 #define FCF_FCP2_DEVICE BIT_2 2743 #define FCF_ASYNC_SENT BIT_3 2744 #define FCF_CONF_COMP_SUPPORTED BIT_4 2745 #define FCF_ASYNC_ACTIVE BIT_5 2746 #define FCF_FCSP_DEVICE BIT_6 2747 #define FCF_EDIF_DELETE BIT_7 2748 2749 /* No loop ID flag. */ 2750 #define FC_NO_LOOP_ID 0x1000 2751 2752 /* 2753 * FC-CT interface 2754 * 2755 * NOTE: All structures are big-endian in form. 2756 */ 2757 2758 #define CT_REJECT_RESPONSE 0x8001 2759 #define CT_ACCEPT_RESPONSE 0x8002 2760 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2761 #define CT_REASON_CANNOT_PERFORM 0x09 2762 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2763 #define CT_EXPL_ALREADY_REGISTERED 0x10 2764 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2765 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2766 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2767 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2768 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2769 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2770 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2771 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2772 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2773 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2774 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2775 2776 #define NS_N_PORT_TYPE 0x01 2777 #define NS_NL_PORT_TYPE 0x02 2778 #define NS_NX_PORT_TYPE 0x7F 2779 2780 #define GA_NXT_CMD 0x100 2781 #define GA_NXT_REQ_SIZE (16 + 4) 2782 #define GA_NXT_RSP_SIZE (16 + 620) 2783 2784 #define GPN_FT_CMD 0x172 2785 #define GPN_FT_REQ_SIZE (16 + 4) 2786 #define GNN_FT_CMD 0x173 2787 #define GNN_FT_REQ_SIZE (16 + 4) 2788 2789 #define GID_PT_CMD 0x1A1 2790 #define GID_PT_REQ_SIZE (16 + 4) 2791 2792 #define GPN_ID_CMD 0x112 2793 #define GPN_ID_REQ_SIZE (16 + 4) 2794 #define GPN_ID_RSP_SIZE (16 + 8) 2795 2796 #define GNN_ID_CMD 0x113 2797 #define GNN_ID_REQ_SIZE (16 + 4) 2798 #define GNN_ID_RSP_SIZE (16 + 8) 2799 2800 #define GFT_ID_CMD 0x117 2801 #define GFT_ID_REQ_SIZE (16 + 4) 2802 #define GFT_ID_RSP_SIZE (16 + 32) 2803 2804 #define GID_PN_CMD 0x121 2805 #define GID_PN_REQ_SIZE (16 + 8) 2806 #define GID_PN_RSP_SIZE (16 + 4) 2807 2808 #define RFT_ID_CMD 0x217 2809 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2810 #define RFT_ID_RSP_SIZE 16 2811 2812 #define RFF_ID_CMD 0x21F 2813 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2814 #define RFF_ID_RSP_SIZE 16 2815 2816 #define RNN_ID_CMD 0x213 2817 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2818 #define RNN_ID_RSP_SIZE 16 2819 2820 #define RSNN_NN_CMD 0x239 2821 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2822 #define RSNN_NN_RSP_SIZE 16 2823 2824 #define GFPN_ID_CMD 0x11C 2825 #define GFPN_ID_REQ_SIZE (16 + 4) 2826 #define GFPN_ID_RSP_SIZE (16 + 8) 2827 2828 #define GPSC_CMD 0x127 2829 #define GPSC_REQ_SIZE (16 + 8) 2830 #define GPSC_RSP_SIZE (16 + 2 + 2) 2831 2832 #define GFF_ID_CMD 0x011F 2833 #define GFF_ID_REQ_SIZE (16 + 4) 2834 #define GFF_ID_RSP_SIZE (16 + 128) 2835 2836 /* 2837 * FDMI HBA attribute types. 2838 */ 2839 #define FDMI1_HBA_ATTR_COUNT 10 2840 #define FDMI2_HBA_ATTR_COUNT 17 2841 2842 #define FDMI_HBA_NODE_NAME 0x1 2843 #define FDMI_HBA_MANUFACTURER 0x2 2844 #define FDMI_HBA_SERIAL_NUMBER 0x3 2845 #define FDMI_HBA_MODEL 0x4 2846 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2847 #define FDMI_HBA_HARDWARE_VERSION 0x6 2848 #define FDMI_HBA_DRIVER_VERSION 0x7 2849 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2850 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2851 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2852 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2853 2854 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2855 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd 2856 #define FDMI_HBA_NUM_PORTS 0xe 2857 #define FDMI_HBA_FABRIC_NAME 0xf 2858 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2859 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0 2860 2861 struct ct_fdmi_hba_attr { 2862 __be16 type; 2863 __be16 len; 2864 union { 2865 uint8_t node_name[WWN_SIZE]; 2866 uint8_t manufacturer[64]; 2867 uint8_t serial_num[32]; 2868 uint8_t model[16+1]; 2869 uint8_t model_desc[80]; 2870 uint8_t hw_version[32]; 2871 uint8_t driver_version[32]; 2872 uint8_t orom_version[16]; 2873 uint8_t fw_version[32]; 2874 uint8_t os_version[128]; 2875 __be32 max_ct_len; 2876 2877 uint8_t sym_name[256]; 2878 __be32 vendor_specific_info; 2879 __be32 num_ports; 2880 uint8_t fabric_name[WWN_SIZE]; 2881 uint8_t bios_name[32]; 2882 uint8_t vendor_identifier[8]; 2883 } a; 2884 }; 2885 2886 struct ct_fdmi1_hba_attributes { 2887 __be32 count; 2888 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT]; 2889 }; 2890 2891 struct ct_fdmi2_hba_attributes { 2892 __be32 count; 2893 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT]; 2894 }; 2895 2896 /* 2897 * FDMI Port attribute types. 2898 */ 2899 #define FDMI1_PORT_ATTR_COUNT 6 2900 #define FDMI2_PORT_ATTR_COUNT 16 2901 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23 2902 2903 #define FDMI_PORT_FC4_TYPES 0x1 2904 #define FDMI_PORT_SUPPORT_SPEED 0x2 2905 #define FDMI_PORT_CURRENT_SPEED 0x3 2906 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2907 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2908 #define FDMI_PORT_HOST_NAME 0x6 2909 2910 #define FDMI_PORT_NODE_NAME 0x7 2911 #define FDMI_PORT_NAME 0x8 2912 #define FDMI_PORT_SYM_NAME 0x9 2913 #define FDMI_PORT_TYPE 0xa 2914 #define FDMI_PORT_SUPP_COS 0xb 2915 #define FDMI_PORT_FABRIC_NAME 0xc 2916 #define FDMI_PORT_FC4_TYPE 0xd 2917 #define FDMI_PORT_STATE 0x101 2918 #define FDMI_PORT_COUNT 0x102 2919 #define FDMI_PORT_IDENTIFIER 0x103 2920 2921 #define FDMI_SMARTSAN_SERVICE 0xF100 2922 #define FDMI_SMARTSAN_GUID 0xF101 2923 #define FDMI_SMARTSAN_VERSION 0xF102 2924 #define FDMI_SMARTSAN_PROD_NAME 0xF103 2925 #define FDMI_SMARTSAN_PORT_INFO 0xF104 2926 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105 2927 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106 2928 2929 #define FDMI_PORT_SPEED_1GB 0x1 2930 #define FDMI_PORT_SPEED_2GB 0x2 2931 #define FDMI_PORT_SPEED_10GB 0x4 2932 #define FDMI_PORT_SPEED_4GB 0x8 2933 #define FDMI_PORT_SPEED_8GB 0x10 2934 #define FDMI_PORT_SPEED_16GB 0x20 2935 #define FDMI_PORT_SPEED_32GB 0x40 2936 #define FDMI_PORT_SPEED_20GB 0x80 2937 #define FDMI_PORT_SPEED_40GB 0x100 2938 #define FDMI_PORT_SPEED_128GB 0x200 2939 #define FDMI_PORT_SPEED_64GB 0x400 2940 #define FDMI_PORT_SPEED_256GB 0x800 2941 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2942 2943 #define FC_CLASS_2 0x04 2944 #define FC_CLASS_3 0x08 2945 #define FC_CLASS_2_3 0x0C 2946 2947 struct ct_fdmi_port_attr { 2948 __be16 type; 2949 __be16 len; 2950 union { 2951 uint8_t fc4_types[32]; 2952 __be32 sup_speed; 2953 __be32 cur_speed; 2954 __be32 max_frame_size; 2955 uint8_t os_dev_name[32]; 2956 uint8_t host_name[256]; 2957 2958 uint8_t node_name[WWN_SIZE]; 2959 uint8_t port_name[WWN_SIZE]; 2960 uint8_t port_sym_name[128]; 2961 __be32 port_type; 2962 __be32 port_supported_cos; 2963 uint8_t fabric_name[WWN_SIZE]; 2964 uint8_t port_fc4_type[32]; 2965 __be32 port_state; 2966 __be32 num_ports; 2967 __be32 port_id; 2968 2969 uint8_t smartsan_service[24]; 2970 uint8_t smartsan_guid[16]; 2971 uint8_t smartsan_version[24]; 2972 uint8_t smartsan_prod_name[16]; 2973 __be32 smartsan_port_info; 2974 __be32 smartsan_qos_support; 2975 __be32 smartsan_security_support; 2976 } a; 2977 }; 2978 2979 struct ct_fdmi1_port_attributes { 2980 __be32 count; 2981 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT]; 2982 }; 2983 2984 struct ct_fdmi2_port_attributes { 2985 __be32 count; 2986 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT]; 2987 }; 2988 2989 #define FDMI_ATTR_TYPELEN(obj) \ 2990 (sizeof((obj)->type) + sizeof((obj)->len)) 2991 2992 #define FDMI_ATTR_ALIGNMENT(len) \ 2993 (4 - ((len) & 3)) 2994 2995 /* FDMI register call options */ 2996 #define CALLOPT_FDMI1 0 2997 #define CALLOPT_FDMI2 1 2998 #define CALLOPT_FDMI2_SMARTSAN 2 2999 3000 /* FDMI definitions. */ 3001 #define GRHL_CMD 0x100 3002 #define GHAT_CMD 0x101 3003 #define GRPL_CMD 0x102 3004 #define GPAT_CMD 0x110 3005 3006 #define RHBA_CMD 0x200 3007 #define RHBA_RSP_SIZE 16 3008 3009 #define RHAT_CMD 0x201 3010 3011 #define RPRT_CMD 0x210 3012 #define RPRT_RSP_SIZE 24 3013 3014 #define RPA_CMD 0x211 3015 #define RPA_RSP_SIZE 16 3016 #define SMARTSAN_RPA_RSP_SIZE 24 3017 3018 #define DHBA_CMD 0x300 3019 #define DHBA_REQ_SIZE (16 + 8) 3020 #define DHBA_RSP_SIZE 16 3021 3022 #define DHAT_CMD 0x301 3023 #define DPRT_CMD 0x310 3024 #define DPA_CMD 0x311 3025 3026 /* CT command header -- request/response common fields */ 3027 struct ct_cmd_hdr { 3028 uint8_t revision; 3029 uint8_t in_id[3]; 3030 uint8_t gs_type; 3031 uint8_t gs_subtype; 3032 uint8_t options; 3033 uint8_t reserved; 3034 }; 3035 3036 /* CT command request */ 3037 struct ct_sns_req { 3038 struct ct_cmd_hdr header; 3039 __be16 command; 3040 __be16 max_rsp_size; 3041 uint8_t fragment_id; 3042 uint8_t reserved[3]; 3043 3044 union { 3045 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 3046 struct { 3047 uint8_t reserved; 3048 be_id_t port_id; 3049 } port_id; 3050 3051 struct { 3052 uint8_t reserved; 3053 uint8_t domain; 3054 uint8_t area; 3055 uint8_t port_type; 3056 } gpn_ft; 3057 3058 struct { 3059 uint8_t port_type; 3060 uint8_t domain; 3061 uint8_t area; 3062 uint8_t reserved; 3063 } gid_pt; 3064 3065 struct { 3066 uint8_t reserved; 3067 be_id_t port_id; 3068 uint8_t fc4_types[32]; 3069 } rft_id; 3070 3071 struct { 3072 uint8_t reserved; 3073 be_id_t port_id; 3074 uint16_t reserved2; 3075 uint8_t fc4_feature; 3076 uint8_t fc4_type; 3077 } rff_id; 3078 3079 struct { 3080 uint8_t reserved; 3081 be_id_t port_id; 3082 uint8_t node_name[8]; 3083 } rnn_id; 3084 3085 struct { 3086 uint8_t node_name[8]; 3087 uint8_t name_len; 3088 uint8_t sym_node_name[255]; 3089 } rsnn_nn; 3090 3091 struct { 3092 uint8_t hba_identifier[8]; 3093 } ghat; 3094 3095 struct { 3096 uint8_t hba_identifier[8]; 3097 __be32 entry_count; 3098 uint8_t port_name[8]; 3099 struct ct_fdmi2_hba_attributes attrs; 3100 } rhba; 3101 3102 struct { 3103 uint8_t hba_identifier[8]; 3104 struct ct_fdmi1_hba_attributes attrs; 3105 } rhat; 3106 3107 struct { 3108 uint8_t port_name[8]; 3109 struct ct_fdmi2_port_attributes attrs; 3110 } rpa; 3111 3112 struct { 3113 uint8_t hba_identifier[8]; 3114 uint8_t port_name[8]; 3115 struct ct_fdmi2_port_attributes attrs; 3116 } rprt; 3117 3118 struct { 3119 uint8_t port_name[8]; 3120 } dhba; 3121 3122 struct { 3123 uint8_t port_name[8]; 3124 } dhat; 3125 3126 struct { 3127 uint8_t port_name[8]; 3128 } dprt; 3129 3130 struct { 3131 uint8_t port_name[8]; 3132 } dpa; 3133 3134 struct { 3135 uint8_t port_name[8]; 3136 } gpsc; 3137 3138 struct { 3139 uint8_t reserved; 3140 uint8_t port_id[3]; 3141 } gff_id; 3142 3143 struct { 3144 uint8_t port_name[8]; 3145 } gid_pn; 3146 } req; 3147 }; 3148 3149 /* CT command response header */ 3150 struct ct_rsp_hdr { 3151 struct ct_cmd_hdr header; 3152 __be16 response; 3153 uint16_t residual; 3154 uint8_t fragment_id; 3155 uint8_t reason_code; 3156 uint8_t explanation_code; 3157 uint8_t vendor_unique; 3158 }; 3159 3160 struct ct_sns_gid_pt_data { 3161 uint8_t control_byte; 3162 be_id_t port_id; 3163 }; 3164 3165 /* It's the same for both GPN_FT and GNN_FT */ 3166 struct ct_sns_gpnft_rsp { 3167 struct { 3168 struct ct_cmd_hdr header; 3169 uint16_t response; 3170 uint16_t residual; 3171 uint8_t fragment_id; 3172 uint8_t reason_code; 3173 uint8_t explanation_code; 3174 uint8_t vendor_unique; 3175 }; 3176 /* Assume the largest number of targets for the union */ 3177 struct ct_sns_gpn_ft_data { 3178 u8 control_byte; 3179 u8 port_id[3]; 3180 u32 reserved; 3181 u8 port_name[8]; 3182 } entries[1]; 3183 }; 3184 3185 /* CT command response */ 3186 struct ct_sns_rsp { 3187 struct ct_rsp_hdr header; 3188 3189 union { 3190 struct { 3191 uint8_t port_type; 3192 be_id_t port_id; 3193 uint8_t port_name[8]; 3194 uint8_t sym_port_name_len; 3195 uint8_t sym_port_name[255]; 3196 uint8_t node_name[8]; 3197 uint8_t sym_node_name_len; 3198 uint8_t sym_node_name[255]; 3199 uint8_t init_proc_assoc[8]; 3200 uint8_t node_ip_addr[16]; 3201 uint8_t class_of_service[4]; 3202 uint8_t fc4_types[32]; 3203 uint8_t ip_address[16]; 3204 uint8_t fabric_port_name[8]; 3205 uint8_t reserved; 3206 uint8_t hard_address[3]; 3207 } ga_nxt; 3208 3209 struct { 3210 /* Assume the largest number of targets for the union */ 3211 struct ct_sns_gid_pt_data 3212 entries[MAX_FIBRE_DEVICES_MAX]; 3213 } gid_pt; 3214 3215 struct { 3216 uint8_t port_name[8]; 3217 } gpn_id; 3218 3219 struct { 3220 uint8_t node_name[8]; 3221 } gnn_id; 3222 3223 struct { 3224 uint8_t fc4_types[32]; 3225 } gft_id; 3226 3227 struct { 3228 uint32_t entry_count; 3229 uint8_t port_name[8]; 3230 struct ct_fdmi1_hba_attributes attrs; 3231 } ghat; 3232 3233 struct { 3234 uint8_t port_name[8]; 3235 } gfpn_id; 3236 3237 struct { 3238 __be16 speeds; 3239 __be16 speed; 3240 } gpsc; 3241 3242 #define GFF_FCP_SCSI_OFFSET 7 3243 #define GFF_NVME_OFFSET 23 /* type = 28h */ 3244 struct { 3245 uint8_t fc4_features[128]; 3246 #define FC4_FF_TARGET BIT_0 3247 #define FC4_FF_INITIATOR BIT_1 3248 } gff_id; 3249 struct { 3250 uint8_t reserved; 3251 uint8_t port_id[3]; 3252 } gid_pn; 3253 } rsp; 3254 }; 3255 3256 struct ct_sns_pkt { 3257 union { 3258 struct ct_sns_req req; 3259 struct ct_sns_rsp rsp; 3260 } p; 3261 }; 3262 3263 struct ct_sns_gpnft_pkt { 3264 union { 3265 struct ct_sns_req req; 3266 struct ct_sns_gpnft_rsp rsp; 3267 } p; 3268 }; 3269 3270 enum scan_flags_t { 3271 SF_SCANNING = BIT_0, 3272 SF_QUEUED = BIT_1, 3273 }; 3274 3275 enum fc4type_t { 3276 FS_FC4TYPE_FCP = BIT_0, 3277 FS_FC4TYPE_NVME = BIT_1, 3278 FS_FCP_IS_N2N = BIT_7, 3279 }; 3280 3281 struct fab_scan_rp { 3282 port_id_t id; 3283 enum fc4type_t fc4type; 3284 u8 port_name[8]; 3285 u8 node_name[8]; 3286 }; 3287 3288 struct fab_scan { 3289 struct fab_scan_rp *l; 3290 u32 size; 3291 u16 scan_retry; 3292 #define MAX_SCAN_RETRIES 5 3293 enum scan_flags_t scan_flags; 3294 struct delayed_work scan_work; 3295 }; 3296 3297 /* 3298 * SNS command structures -- for 2200 compatibility. 3299 */ 3300 #define RFT_ID_SNS_SCMD_LEN 22 3301 #define RFT_ID_SNS_CMD_SIZE 60 3302 #define RFT_ID_SNS_DATA_SIZE 16 3303 3304 #define RNN_ID_SNS_SCMD_LEN 10 3305 #define RNN_ID_SNS_CMD_SIZE 36 3306 #define RNN_ID_SNS_DATA_SIZE 16 3307 3308 #define GA_NXT_SNS_SCMD_LEN 6 3309 #define GA_NXT_SNS_CMD_SIZE 28 3310 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 3311 3312 #define GID_PT_SNS_SCMD_LEN 6 3313 #define GID_PT_SNS_CMD_SIZE 28 3314 /* 3315 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 3316 * adapters. 3317 */ 3318 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 3319 3320 #define GPN_ID_SNS_SCMD_LEN 6 3321 #define GPN_ID_SNS_CMD_SIZE 28 3322 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 3323 3324 #define GNN_ID_SNS_SCMD_LEN 6 3325 #define GNN_ID_SNS_CMD_SIZE 28 3326 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 3327 3328 struct sns_cmd_pkt { 3329 union { 3330 struct { 3331 __le16 buffer_length; 3332 __le16 reserved_1; 3333 __le64 buffer_address __packed; 3334 __le16 subcommand_length; 3335 __le16 reserved_2; 3336 __le16 subcommand; 3337 __le16 size; 3338 uint32_t reserved_3; 3339 uint8_t param[36]; 3340 } cmd; 3341 3342 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 3343 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 3344 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 3345 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 3346 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 3347 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 3348 } p; 3349 }; 3350 3351 struct fw_blob { 3352 char *name; 3353 uint32_t segs[4]; 3354 const struct firmware *fw; 3355 }; 3356 3357 /* Return data from MBC_GET_ID_LIST call. */ 3358 struct gid_list_info { 3359 uint8_t al_pa; 3360 uint8_t area; 3361 uint8_t domain; 3362 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 3363 __le16 loop_id; /* ISP23XX -- 6 bytes. */ 3364 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 3365 }; 3366 3367 /* NPIV */ 3368 typedef struct vport_info { 3369 uint8_t port_name[WWN_SIZE]; 3370 uint8_t node_name[WWN_SIZE]; 3371 int vp_id; 3372 uint16_t loop_id; 3373 unsigned long host_no; 3374 uint8_t port_id[3]; 3375 int loop_state; 3376 } vport_info_t; 3377 3378 typedef struct vport_params { 3379 uint8_t port_name[WWN_SIZE]; 3380 uint8_t node_name[WWN_SIZE]; 3381 uint32_t options; 3382 #define VP_OPTS_RETRY_ENABLE BIT_0 3383 #define VP_OPTS_VP_DISABLE BIT_1 3384 } vport_params_t; 3385 3386 /* NPIV - return codes of VP create and modify */ 3387 #define VP_RET_CODE_OK 0 3388 #define VP_RET_CODE_FATAL 1 3389 #define VP_RET_CODE_WRONG_ID 2 3390 #define VP_RET_CODE_WWPN 3 3391 #define VP_RET_CODE_RESOURCES 4 3392 #define VP_RET_CODE_NO_MEM 5 3393 #define VP_RET_CODE_NOT_FOUND 6 3394 3395 struct qla_hw_data; 3396 struct rsp_que; 3397 /* 3398 * ISP operations 3399 */ 3400 struct isp_operations { 3401 3402 int (*pci_config) (struct scsi_qla_host *); 3403 int (*reset_chip)(struct scsi_qla_host *); 3404 int (*chip_diag) (struct scsi_qla_host *); 3405 void (*config_rings) (struct scsi_qla_host *); 3406 int (*reset_adapter)(struct scsi_qla_host *); 3407 int (*nvram_config) (struct scsi_qla_host *); 3408 void (*update_fw_options) (struct scsi_qla_host *); 3409 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 3410 3411 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t); 3412 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 3413 3414 irq_handler_t intr_handler; 3415 void (*enable_intrs) (struct qla_hw_data *); 3416 void (*disable_intrs) (struct qla_hw_data *); 3417 3418 int (*abort_command) (srb_t *); 3419 int (*target_reset) (struct fc_port *, uint64_t, int); 3420 int (*lun_reset) (struct fc_port *, uint64_t, int); 3421 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 3422 uint8_t, uint8_t, uint16_t *, uint8_t); 3423 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 3424 uint8_t, uint8_t); 3425 3426 uint16_t (*calc_req_entries) (uint16_t); 3427 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 3428 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *); 3429 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 3430 uint32_t); 3431 3432 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *, 3433 uint32_t, uint32_t); 3434 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t, 3435 uint32_t); 3436 3437 void (*fw_dump)(struct scsi_qla_host *vha); 3438 void (*mpi_fw_dump)(struct scsi_qla_host *, int); 3439 3440 /* Context: task, might sleep */ 3441 int (*beacon_on) (struct scsi_qla_host *); 3442 int (*beacon_off) (struct scsi_qla_host *); 3443 3444 void (*beacon_blink) (struct scsi_qla_host *); 3445 3446 void *(*read_optrom)(struct scsi_qla_host *, void *, 3447 uint32_t, uint32_t); 3448 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t, 3449 uint32_t); 3450 3451 int (*get_flash_version) (struct scsi_qla_host *, void *); 3452 int (*start_scsi) (srb_t *); 3453 int (*start_scsi_mq) (srb_t *); 3454 3455 /* Context: task, might sleep */ 3456 int (*abort_isp) (struct scsi_qla_host *); 3457 3458 int (*iospace_config)(struct qla_hw_data *); 3459 int (*initialize_adapter)(struct scsi_qla_host *); 3460 }; 3461 3462 /* MSI-X Support *************************************************************/ 3463 3464 #define QLA_MSIX_CHIP_REV_24XX 3 3465 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 3466 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 3467 3468 #define QLA_BASE_VECTORS 2 /* default + RSP */ 3469 #define QLA_MSIX_RSP_Q 0x01 3470 #define QLA_ATIO_VECTOR 0x02 3471 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03 3472 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04 3473 3474 #define QLA_MIDX_DEFAULT 0 3475 #define QLA_MIDX_RSP_Q 1 3476 #define QLA_PCI_MSIX_CONTROL 0xa2 3477 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 3478 3479 struct scsi_qla_host; 3480 3481 3482 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 3483 3484 struct qla_msix_entry { 3485 int have_irq; 3486 int in_use; 3487 uint32_t vector; 3488 uint32_t vector_base0; 3489 uint16_t entry; 3490 char name[30]; 3491 void *handle; 3492 int cpuid; 3493 }; 3494 3495 #define WATCH_INTERVAL 1 /* number of seconds */ 3496 3497 /* Work events. */ 3498 enum qla_work_type { 3499 QLA_EVT_AEN, 3500 QLA_EVT_IDC_ACK, 3501 QLA_EVT_ASYNC_LOGIN, 3502 QLA_EVT_ASYNC_LOGOUT, 3503 QLA_EVT_ASYNC_ADISC, 3504 QLA_EVT_UEVENT, 3505 QLA_EVT_AENFX, 3506 QLA_EVT_UNMAP, 3507 QLA_EVT_NEW_SESS, 3508 QLA_EVT_GPDB, 3509 QLA_EVT_PRLI, 3510 QLA_EVT_GPSC, 3511 QLA_EVT_GNL, 3512 QLA_EVT_NACK, 3513 QLA_EVT_RELOGIN, 3514 QLA_EVT_ASYNC_PRLO, 3515 QLA_EVT_ASYNC_PRLO_DONE, 3516 QLA_EVT_GPNFT, 3517 QLA_EVT_GPNFT_DONE, 3518 QLA_EVT_GNNFT_DONE, 3519 QLA_EVT_GFPNID, 3520 QLA_EVT_SP_RETRY, 3521 QLA_EVT_IIDMA, 3522 QLA_EVT_ELS_PLOGI, 3523 QLA_EVT_SA_REPLACE, 3524 }; 3525 3526 3527 struct qla_work_evt { 3528 struct list_head list; 3529 enum qla_work_type type; 3530 u32 flags; 3531 #define QLA_EVT_FLAG_FREE 0x1 3532 3533 union { 3534 struct { 3535 enum fc_host_event_code code; 3536 u32 data; 3537 } aen; 3538 struct { 3539 #define QLA_IDC_ACK_REGS 7 3540 uint16_t mb[QLA_IDC_ACK_REGS]; 3541 } idc_ack; 3542 struct { 3543 struct fc_port *fcport; 3544 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 3545 u16 data[2]; 3546 } logio; 3547 struct { 3548 u32 code; 3549 #define QLA_UEVENT_CODE_FW_DUMP 0 3550 } uevent; 3551 struct { 3552 uint32_t evtcode; 3553 uint32_t mbx[8]; 3554 uint32_t count; 3555 } aenfx; 3556 struct { 3557 srb_t *sp; 3558 } iosb; 3559 struct { 3560 port_id_t id; 3561 u8 port_name[8]; 3562 u8 node_name[8]; 3563 void *pla; 3564 u8 fc4_type; 3565 } new_sess; 3566 struct { /*Get PDB, Get Speed, update fcport, gnl */ 3567 fc_port_t *fcport; 3568 u8 opt; 3569 } fcport; 3570 struct { 3571 fc_port_t *fcport; 3572 u8 iocb[IOCB_SIZE]; 3573 int type; 3574 } nack; 3575 struct { 3576 u8 fc4_type; 3577 srb_t *sp; 3578 } gpnft; 3579 struct { 3580 struct edif_sa_ctl *sa_ctl; 3581 fc_port_t *fcport; 3582 uint16_t nport_handle; 3583 } sa_update; 3584 } u; 3585 }; 3586 3587 struct qla_chip_state_84xx { 3588 struct list_head list; 3589 struct kref kref; 3590 3591 void *bus; 3592 spinlock_t access_lock; 3593 struct mutex fw_update_mutex; 3594 uint32_t fw_update; 3595 uint32_t op_fw_version; 3596 uint32_t op_fw_size; 3597 uint32_t op_fw_seq_size; 3598 uint32_t diag_fw_version; 3599 uint32_t gold_fw_version; 3600 }; 3601 3602 struct qla_dif_statistics { 3603 uint64_t dif_input_bytes; 3604 uint64_t dif_output_bytes; 3605 uint64_t dif_input_requests; 3606 uint64_t dif_output_requests; 3607 uint32_t dif_guard_err; 3608 uint32_t dif_ref_tag_err; 3609 uint32_t dif_app_tag_err; 3610 }; 3611 3612 struct qla_statistics { 3613 uint32_t total_isp_aborts; 3614 uint64_t input_bytes; 3615 uint64_t output_bytes; 3616 uint64_t input_requests; 3617 uint64_t output_requests; 3618 uint32_t control_requests; 3619 3620 uint64_t jiffies_at_last_reset; 3621 uint32_t stat_max_pend_cmds; 3622 uint32_t stat_max_qfull_cmds_alloc; 3623 uint32_t stat_max_qfull_cmds_dropped; 3624 3625 struct qla_dif_statistics qla_dif_stats; 3626 }; 3627 3628 struct bidi_statistics { 3629 unsigned long long io_count; 3630 unsigned long long transfer_bytes; 3631 }; 3632 3633 struct qla_tc_param { 3634 struct scsi_qla_host *vha; 3635 uint32_t blk_sz; 3636 uint32_t bufflen; 3637 struct scatterlist *sg; 3638 struct scatterlist *prot_sg; 3639 struct crc_context *ctx; 3640 uint8_t *ctx_dsd_alloced; 3641 }; 3642 3643 /* Multi queue support */ 3644 #define MBC_INITIALIZE_MULTIQ 0x1f 3645 #define QLA_QUE_PAGE 0X1000 3646 #define QLA_MQ_SIZE 32 3647 #define QLA_MAX_QUEUES 256 3648 #define ISP_QUE_REG(ha, id) \ 3649 ((ha->mqenable || IS_QLA83XX(ha) || \ 3650 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \ 3651 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 3652 ((void __iomem *)ha->iobase)) 3653 #define QLA_REQ_QUE_ID(tag) \ 3654 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 3655 #define QLA_DEFAULT_QUE_QOS 5 3656 #define QLA_PRECONFIG_VPORTS 32 3657 #define QLA_MAX_VPORTS_QLA24XX 128 3658 #define QLA_MAX_VPORTS_QLA25XX 256 3659 3660 struct qla_tgt_counters { 3661 uint64_t qla_core_sbt_cmd; 3662 uint64_t core_qla_que_buf; 3663 uint64_t qla_core_ret_ctio; 3664 uint64_t core_qla_snd_status; 3665 uint64_t qla_core_ret_sta_ctio; 3666 uint64_t core_qla_free_cmd; 3667 uint64_t num_q_full_sent; 3668 uint64_t num_alloc_iocb_failed; 3669 uint64_t num_term_xchg_sent; 3670 }; 3671 3672 struct qla_counters { 3673 uint64_t input_bytes; 3674 uint64_t input_requests; 3675 uint64_t output_bytes; 3676 uint64_t output_requests; 3677 3678 }; 3679 3680 struct qla_qpair; 3681 3682 /* Response queue data structure */ 3683 struct rsp_que { 3684 dma_addr_t dma; 3685 response_t *ring; 3686 response_t *ring_ptr; 3687 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */ 3688 __le32 __iomem *rsp_q_out; 3689 uint16_t ring_index; 3690 uint16_t out_ptr; 3691 uint16_t *in_ptr; /* queue shadow in index */ 3692 uint16_t length; 3693 uint16_t options; 3694 uint16_t rid; 3695 uint16_t id; 3696 uint16_t vp_idx; 3697 struct qla_hw_data *hw; 3698 struct qla_msix_entry *msix; 3699 struct req_que *req; 3700 srb_t *status_srb; /* status continuation entry */ 3701 struct qla_qpair *qpair; 3702 3703 dma_addr_t dma_fx00; 3704 response_t *ring_fx00; 3705 uint16_t length_fx00; 3706 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 3707 }; 3708 3709 /* Request queue data structure */ 3710 struct req_que { 3711 dma_addr_t dma; 3712 request_t *ring; 3713 request_t *ring_ptr; 3714 __le32 __iomem *req_q_in; /* FWI2-capable only. */ 3715 __le32 __iomem *req_q_out; 3716 uint16_t ring_index; 3717 uint16_t in_ptr; 3718 uint16_t *out_ptr; /* queue shadow out index */ 3719 uint16_t cnt; 3720 uint16_t length; 3721 uint16_t options; 3722 uint16_t rid; 3723 uint16_t id; 3724 uint16_t qos; 3725 uint16_t vp_idx; 3726 struct rsp_que *rsp; 3727 srb_t **outstanding_cmds; 3728 uint32_t current_outstanding_cmd; 3729 uint16_t num_outstanding_cmds; 3730 int max_q_depth; 3731 3732 dma_addr_t dma_fx00; 3733 request_t *ring_fx00; 3734 uint16_t length_fx00; 3735 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 3736 }; 3737 3738 struct qla_fw_resources { 3739 u16 iocbs_total; 3740 u16 iocbs_limit; 3741 u16 iocbs_qp_limit; 3742 u16 iocbs_used; 3743 u16 exch_total; 3744 u16 exch_limit; 3745 u16 exch_used; 3746 u16 pad; 3747 }; 3748 3749 #define QLA_IOCB_PCT_LIMIT 95 3750 3751 struct qla_buf_pool { 3752 u16 num_bufs; 3753 u16 num_active; 3754 u16 max_used; 3755 u16 num_alloc; 3756 u16 prev_max; 3757 u16 pad; 3758 uint32_t take_snapshot:1; 3759 unsigned long *buf_map; 3760 void **buf_array; 3761 dma_addr_t *dma_array; 3762 }; 3763 3764 /*Queue pair data structure */ 3765 struct qla_qpair { 3766 spinlock_t qp_lock; 3767 atomic_t ref_count; 3768 uint32_t lun_cnt; 3769 /* 3770 * For qpair 0, qp_lock_ptr will point at hardware_lock due to 3771 * legacy code. For other Qpair(s), it will point at qp_lock. 3772 */ 3773 spinlock_t *qp_lock_ptr; 3774 struct scsi_qla_host *vha; 3775 u32 chip_reset; 3776 3777 /* distill these fields down to 'online=0/1' 3778 * ha->flags.eeh_busy 3779 * ha->flags.pci_channel_io_perm_failure 3780 * base_vha->loop_state 3781 */ 3782 uint32_t online:1; 3783 /* move vha->flags.difdix_supported here */ 3784 uint32_t difdix_supported:1; 3785 uint32_t delete_in_progress:1; 3786 uint32_t fw_started:1; 3787 uint32_t enable_class_2:1; 3788 uint32_t enable_explicit_conf:1; 3789 uint32_t use_shadow_reg:1; 3790 uint32_t rcv_intr:1; 3791 3792 uint16_t id; /* qp number used with FW */ 3793 uint16_t vp_idx; /* vport ID */ 3794 mempool_t *srb_mempool; 3795 3796 struct pci_dev *pdev; 3797 void (*reqq_start_iocbs)(struct qla_qpair *); 3798 3799 /* to do: New driver: move queues to here instead of pointers */ 3800 struct req_que *req; 3801 struct rsp_que *rsp; 3802 struct atio_que *atio; 3803 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */ 3804 struct qla_hw_data *hw; 3805 struct work_struct q_work; 3806 struct qla_counters counters; 3807 3808 struct list_head qp_list_elem; /* vha->qp_list */ 3809 struct list_head hints_list; 3810 3811 uint16_t retry_term_cnt; 3812 __le32 retry_term_exchg_addr; 3813 uint64_t retry_term_jiff; 3814 struct qla_tgt_counters tgt_counters; 3815 uint16_t cpuid; 3816 struct qla_fw_resources fwres ____cacheline_aligned; 3817 struct qla_buf_pool buf_pool; 3818 u32 cmd_cnt; 3819 u32 cmd_completion_cnt; 3820 u32 prev_completion_cnt; 3821 }; 3822 3823 /* Place holder for FW buffer parameters */ 3824 struct qlfc_fw { 3825 void *fw_buf; 3826 dma_addr_t fw_dma; 3827 uint32_t len; 3828 }; 3829 3830 struct rdp_req_payload { 3831 uint32_t els_request; 3832 uint32_t desc_list_len; 3833 3834 /* NPIV descriptor */ 3835 struct { 3836 uint32_t desc_tag; 3837 uint32_t desc_len; 3838 uint8_t reserved; 3839 uint8_t nport_id[3]; 3840 } npiv_desc; 3841 }; 3842 3843 struct rdp_rsp_payload { 3844 struct { 3845 __be32 cmd; 3846 __be32 len; 3847 } hdr; 3848 3849 /* LS Request Info descriptor */ 3850 struct { 3851 __be32 desc_tag; 3852 __be32 desc_len; 3853 __be32 req_payload_word_0; 3854 } ls_req_info_desc; 3855 3856 /* LS Request Info descriptor */ 3857 struct { 3858 __be32 desc_tag; 3859 __be32 desc_len; 3860 __be32 req_payload_word_0; 3861 } ls_req_info_desc2; 3862 3863 /* SFP diagnostic param descriptor */ 3864 struct { 3865 __be32 desc_tag; 3866 __be32 desc_len; 3867 __be16 temperature; 3868 __be16 vcc; 3869 __be16 tx_bias; 3870 __be16 tx_power; 3871 __be16 rx_power; 3872 __be16 sfp_flags; 3873 } sfp_diag_desc; 3874 3875 /* Port Speed Descriptor */ 3876 struct { 3877 __be32 desc_tag; 3878 __be32 desc_len; 3879 __be16 speed_capab; 3880 __be16 operating_speed; 3881 } port_speed_desc; 3882 3883 /* Link Error Status Descriptor */ 3884 struct { 3885 __be32 desc_tag; 3886 __be32 desc_len; 3887 __be32 link_fail_cnt; 3888 __be32 loss_sync_cnt; 3889 __be32 loss_sig_cnt; 3890 __be32 prim_seq_err_cnt; 3891 __be32 inval_xmit_word_cnt; 3892 __be32 inval_crc_cnt; 3893 uint8_t pn_port_phy_type; 3894 uint8_t reserved[3]; 3895 } ls_err_desc; 3896 3897 /* Port name description with diag param */ 3898 struct { 3899 __be32 desc_tag; 3900 __be32 desc_len; 3901 uint8_t WWNN[WWN_SIZE]; 3902 uint8_t WWPN[WWN_SIZE]; 3903 } port_name_diag_desc; 3904 3905 /* Port Name desc for Direct attached Fx_Port or Nx_Port */ 3906 struct { 3907 __be32 desc_tag; 3908 __be32 desc_len; 3909 uint8_t WWNN[WWN_SIZE]; 3910 uint8_t WWPN[WWN_SIZE]; 3911 } port_name_direct_desc; 3912 3913 /* Buffer Credit descriptor */ 3914 struct { 3915 __be32 desc_tag; 3916 __be32 desc_len; 3917 __be32 fcport_b2b; 3918 __be32 attached_fcport_b2b; 3919 __be32 fcport_rtt; 3920 } buffer_credit_desc; 3921 3922 /* Optical Element Data Descriptor */ 3923 struct { 3924 __be32 desc_tag; 3925 __be32 desc_len; 3926 __be16 high_alarm; 3927 __be16 low_alarm; 3928 __be16 high_warn; 3929 __be16 low_warn; 3930 __be32 element_flags; 3931 } optical_elmt_desc[5]; 3932 3933 /* Optical Product Data Descriptor */ 3934 struct { 3935 __be32 desc_tag; 3936 __be32 desc_len; 3937 uint8_t vendor_name[16]; 3938 uint8_t part_number[16]; 3939 uint8_t serial_number[16]; 3940 uint8_t revision[4]; 3941 uint8_t date[8]; 3942 } optical_prod_desc; 3943 }; 3944 3945 #define RDP_DESC_LEN(obj) \ 3946 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len)) 3947 3948 #define RDP_PORT_SPEED_1GB BIT_15 3949 #define RDP_PORT_SPEED_2GB BIT_14 3950 #define RDP_PORT_SPEED_4GB BIT_13 3951 #define RDP_PORT_SPEED_10GB BIT_12 3952 #define RDP_PORT_SPEED_8GB BIT_11 3953 #define RDP_PORT_SPEED_16GB BIT_10 3954 #define RDP_PORT_SPEED_32GB BIT_9 3955 #define RDP_PORT_SPEED_64GB BIT_8 3956 #define RDP_PORT_SPEED_UNKNOWN BIT_0 3957 3958 struct scsi_qlt_host { 3959 void *target_lport_ptr; 3960 struct mutex tgt_mutex; 3961 struct mutex tgt_host_action_mutex; 3962 struct qla_tgt *qla_tgt; 3963 }; 3964 3965 struct qlt_hw_data { 3966 /* Protected by hw lock */ 3967 uint32_t node_name_set:1; 3968 3969 dma_addr_t atio_dma; /* Physical address. */ 3970 struct atio *atio_ring; /* Base virtual address */ 3971 struct atio *atio_ring_ptr; /* Current address. */ 3972 uint16_t atio_ring_index; /* Current index. */ 3973 uint16_t atio_q_length; 3974 __le32 __iomem *atio_q_in; 3975 __le32 __iomem *atio_q_out; 3976 3977 const struct qla_tgt_func_tmpl *tgt_ops; 3978 3979 int saved_set; 3980 __le16 saved_exchange_count; 3981 __le32 saved_firmware_options_1; 3982 __le32 saved_firmware_options_2; 3983 __le32 saved_firmware_options_3; 3984 uint8_t saved_firmware_options[2]; 3985 uint8_t saved_add_firmware_options[2]; 3986 3987 uint8_t tgt_node_name[WWN_SIZE]; 3988 3989 struct dentry *dfs_tgt_sess; 3990 struct dentry *dfs_tgt_port_database; 3991 struct dentry *dfs_naqp; 3992 3993 struct list_head q_full_list; 3994 uint32_t num_pend_cmds; 3995 uint32_t num_qfull_cmds_alloc; 3996 uint32_t num_qfull_cmds_dropped; 3997 spinlock_t q_full_lock; 3998 uint32_t leak_exchg_thresh_hold; 3999 spinlock_t sess_lock; 4000 int num_act_qpairs; 4001 #define DEFAULT_NAQP 2 4002 spinlock_t atio_lock ____cacheline_aligned; 4003 }; 4004 4005 #define MAX_QFULL_CMDS_ALLOC 8192 4006 #define Q_FULL_THRESH_HOLD_PERCENT 90 4007 #define Q_FULL_THRESH_HOLD(ha) \ 4008 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 4009 4010 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 4011 4012 struct qla_hw_data_stat { 4013 u32 num_fw_dump; 4014 u32 num_mpi_reset; 4015 }; 4016 4017 /* refer to pcie_do_recovery reference */ 4018 typedef enum { 4019 QLA_PCI_RESUME, 4020 QLA_PCI_ERR_DETECTED, 4021 QLA_PCI_MMIO_ENABLED, 4022 QLA_PCI_SLOT_RESET, 4023 } pci_error_state_t; 4024 /* 4025 * Qlogic host adapter specific data structure. 4026 */ 4027 struct qla_hw_data { 4028 struct pci_dev *pdev; 4029 /* SRB cache. */ 4030 #define SRB_MIN_REQ 128 4031 mempool_t *srb_mempool; 4032 u8 port_name[WWN_SIZE]; 4033 4034 volatile struct { 4035 uint32_t mbox_int :1; 4036 uint32_t mbox_busy :1; 4037 uint32_t disable_risc_code_load :1; 4038 uint32_t enable_64bit_addressing :1; 4039 uint32_t enable_lip_reset :1; 4040 uint32_t enable_target_reset :1; 4041 uint32_t enable_lip_full_login :1; 4042 uint32_t enable_led_scheme :1; 4043 4044 uint32_t msi_enabled :1; 4045 uint32_t msix_enabled :1; 4046 uint32_t disable_serdes :1; 4047 uint32_t gpsc_supported :1; 4048 uint32_t npiv_supported :1; 4049 uint32_t pci_channel_io_perm_failure :1; 4050 uint32_t fce_enabled :1; 4051 uint32_t fac_supported :1; 4052 4053 uint32_t chip_reset_done :1; 4054 uint32_t running_gold_fw :1; 4055 uint32_t eeh_busy :1; 4056 uint32_t disable_msix_handshake :1; 4057 uint32_t fcp_prio_enabled :1; 4058 uint32_t isp82xx_fw_hung:1; 4059 uint32_t nic_core_hung:1; 4060 4061 uint32_t quiesce_owner:1; 4062 uint32_t nic_core_reset_hdlr_active:1; 4063 uint32_t nic_core_reset_owner:1; 4064 uint32_t isp82xx_no_md_cap:1; 4065 uint32_t host_shutting_down:1; 4066 uint32_t idc_compl_status:1; 4067 uint32_t mr_reset_hdlr_active:1; 4068 uint32_t mr_intr_valid:1; 4069 4070 uint32_t dport_enabled:1; 4071 uint32_t fawwpn_enabled:1; 4072 uint32_t exlogins_enabled:1; 4073 uint32_t exchoffld_enabled:1; 4074 4075 uint32_t lip_ae:1; 4076 uint32_t n2n_ae:1; 4077 uint32_t fw_started:1; 4078 uint32_t fw_init_done:1; 4079 4080 uint32_t lr_detected:1; 4081 4082 uint32_t rida_fmt2:1; 4083 uint32_t purge_mbox:1; 4084 uint32_t n2n_bigger:1; 4085 uint32_t secure_adapter:1; 4086 uint32_t secure_fw:1; 4087 /* Supported by Adapter */ 4088 uint32_t scm_supported_a:1; 4089 /* Supported by Firmware */ 4090 uint32_t scm_supported_f:1; 4091 /* Enabled in Driver */ 4092 uint32_t scm_enabled:1; 4093 uint32_t edif_hw:1; 4094 uint32_t edif_enabled:1; 4095 uint32_t n2n_fw_acc_sec:1; 4096 uint32_t plogi_template_valid:1; 4097 uint32_t port_isolated:1; 4098 uint32_t eeh_flush:2; 4099 #define EEH_FLUSH_RDY 1 4100 #define EEH_FLUSH_DONE 2 4101 } flags; 4102 4103 uint16_t max_exchg; 4104 uint16_t lr_distance; /* 32G & above */ 4105 #define LR_DISTANCE_5K 1 4106 #define LR_DISTANCE_10K 0 4107 4108 /* This spinlock is used to protect "io transactions", you must 4109 * acquire it before doing any IO to the card, eg with RD_REG*() and 4110 * WRT_REG*() for the duration of your entire commandtransaction. 4111 * 4112 * This spinlock is of lower priority than the io request lock. 4113 */ 4114 4115 spinlock_t hardware_lock ____cacheline_aligned; 4116 int bars; 4117 int mem_only; 4118 device_reg_t *iobase; /* Base I/O address */ 4119 resource_size_t pio_address; 4120 4121 #define MIN_IOBASE_LEN 0x100 4122 dma_addr_t bar0_hdl; 4123 4124 void __iomem *cregbase; 4125 dma_addr_t bar2_hdl; 4126 #define BAR0_LEN_FX00 (1024 * 1024) 4127 #define BAR2_LEN_FX00 (128 * 1024) 4128 4129 uint32_t rqstq_intr_code; 4130 uint32_t mbx_intr_code; 4131 uint32_t req_que_len; 4132 uint32_t rsp_que_len; 4133 uint32_t req_que_off; 4134 uint32_t rsp_que_off; 4135 unsigned long eeh_jif; 4136 4137 /* Multi queue data structs */ 4138 device_reg_t *mqiobase; 4139 device_reg_t *msixbase; 4140 uint16_t msix_count; 4141 uint8_t mqenable; 4142 struct req_que **req_q_map; 4143 struct rsp_que **rsp_q_map; 4144 struct qla_qpair **queue_pair_map; 4145 struct qla_qpair **qp_cpu_map; 4146 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4147 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 4148 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8) 4149 / sizeof(unsigned long)]; 4150 uint8_t max_req_queues; 4151 uint8_t max_rsp_queues; 4152 uint8_t max_qpairs; 4153 uint8_t num_qpairs; 4154 struct qla_qpair *base_qpair; 4155 struct qla_npiv_entry *npiv_info; 4156 uint16_t nvram_npiv_size; 4157 4158 uint16_t switch_cap; 4159 #define FLOGI_SEQ_DEL BIT_8 4160 #define FLOGI_MID_SUPPORT BIT_10 4161 #define FLOGI_VSAN_SUPPORT BIT_12 4162 #define FLOGI_SP_SUPPORT BIT_13 4163 4164 uint8_t port_no; /* Physical port of adapter */ 4165 uint8_t exch_starvation; 4166 4167 /* Timeout timers. */ 4168 uint8_t loop_down_abort_time; /* port down timer */ 4169 atomic_t loop_down_timer; /* loop down timer */ 4170 uint8_t link_down_timeout; /* link down timeout */ 4171 uint16_t max_loop_id; 4172 uint16_t max_fibre_devices; /* Maximum number of targets */ 4173 4174 uint16_t fb_rev; 4175 uint16_t min_external_loopid; /* First external loop Id */ 4176 4177 #define PORT_SPEED_UNKNOWN 0xFFFF 4178 #define PORT_SPEED_1GB 0x00 4179 #define PORT_SPEED_2GB 0x01 4180 #define PORT_SPEED_AUTO 0x02 4181 #define PORT_SPEED_4GB 0x03 4182 #define PORT_SPEED_8GB 0x04 4183 #define PORT_SPEED_16GB 0x05 4184 #define PORT_SPEED_32GB 0x06 4185 #define PORT_SPEED_64GB 0x07 4186 #define PORT_SPEED_10GB 0x13 4187 uint16_t link_data_rate; /* F/W operating speed */ 4188 uint16_t set_data_rate; /* Set by user */ 4189 4190 uint8_t current_topology; 4191 uint8_t prev_topology; 4192 #define ISP_CFG_NL 1 4193 #define ISP_CFG_N 2 4194 #define ISP_CFG_FL 4 4195 #define ISP_CFG_F 8 4196 4197 uint8_t operating_mode; /* F/W operating mode */ 4198 #define LOOP 0 4199 #define P2P 1 4200 #define LOOP_P2P 2 4201 #define P2P_LOOP 3 4202 uint8_t interrupts_on; 4203 uint32_t isp_abort_cnt; 4204 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 4205 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 4206 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 4207 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 4208 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 4209 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 4210 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 4211 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 4212 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061 4213 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081 4214 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089 4215 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281 4216 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289 4217 4218 uint32_t isp_type; 4219 #define DT_ISP2100 BIT_0 4220 #define DT_ISP2200 BIT_1 4221 #define DT_ISP2300 BIT_2 4222 #define DT_ISP2312 BIT_3 4223 #define DT_ISP2322 BIT_4 4224 #define DT_ISP6312 BIT_5 4225 #define DT_ISP6322 BIT_6 4226 #define DT_ISP2422 BIT_7 4227 #define DT_ISP2432 BIT_8 4228 #define DT_ISP5422 BIT_9 4229 #define DT_ISP5432 BIT_10 4230 #define DT_ISP2532 BIT_11 4231 #define DT_ISP8432 BIT_12 4232 #define DT_ISP8001 BIT_13 4233 #define DT_ISP8021 BIT_14 4234 #define DT_ISP2031 BIT_15 4235 #define DT_ISP8031 BIT_16 4236 #define DT_ISPFX00 BIT_17 4237 #define DT_ISP8044 BIT_18 4238 #define DT_ISP2071 BIT_19 4239 #define DT_ISP2271 BIT_20 4240 #define DT_ISP2261 BIT_21 4241 #define DT_ISP2061 BIT_22 4242 #define DT_ISP2081 BIT_23 4243 #define DT_ISP2089 BIT_24 4244 #define DT_ISP2281 BIT_25 4245 #define DT_ISP2289 BIT_26 4246 #define DT_ISP_LAST (DT_ISP2289 << 1) 4247 4248 uint32_t device_type; 4249 #define DT_T10_PI BIT_25 4250 #define DT_IIDMA BIT_26 4251 #define DT_FWI2 BIT_27 4252 #define DT_ZIO_SUPPORTED BIT_28 4253 #define DT_OEM_001 BIT_29 4254 #define DT_ISP2200A BIT_30 4255 #define DT_EXTENDED_IDS BIT_31 4256 4257 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 4258 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 4259 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 4260 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 4261 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 4262 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 4263 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 4264 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 4265 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 4266 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 4267 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 4268 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 4269 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 4270 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 4271 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 4272 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 4273 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 4274 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 4275 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 4276 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 4277 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 4278 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 4279 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 4280 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 4281 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081) 4282 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281) 4283 4284 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 4285 IS_QLA6312(ha) || IS_QLA6322(ha)) 4286 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 4287 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 4288 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 4289 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 4290 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 4291 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 4292 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha)) 4293 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 4294 IS_QLA84XX(ha)) 4295 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 4296 IS_QLA8031(ha) || IS_QLA8044(ha)) 4297 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 4298 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 4299 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 4300 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 4301 IS_QLA8044(ha) || IS_QLA27XX(ha) || \ 4302 IS_QLA28XX(ha)) 4303 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4304 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4305 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 4306 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4307 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4308 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4309 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4310 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 4311 4312 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 4313 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 4314 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 4315 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 4316 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 4317 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 4318 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 4319 #define IS_MQUE_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4320 IS_QLA28XX(ha)) 4321 #define IS_BIDI_CAPABLE(ha) \ 4322 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4323 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 4324 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 4325 ((ha)->fw_attributes_ext[0] & BIT_0)) 4326 #define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14) 4327 #define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS) 4328 #define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD) 4329 #define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp)) 4330 #define QLA_LS_ABTS_WAIT_ENABLED(_sp) \ 4331 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4332 #define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \ 4333 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4334 #define QLA_ABTS_WAIT_ENABLED(_sp) \ 4335 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw)) 4336 4337 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4338 IS_QLA28XX(ha)) 4339 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4340 IS_QLA28XX(ha)) 4341 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 4342 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4343 IS_QLA28XX(ha)) 4344 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 4345 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 4346 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4347 IS_QLA28XX(ha)) 4348 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 4349 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4350 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4351 IS_QLA28XX(ha)) 4352 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \ 4353 IS_QLA28XX(ha)) 4354 #define IS_EXCHG_OFFLD_CAPABLE(ha) \ 4355 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4356 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \ 4357 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 4358 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4359 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\ 4360 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4361 4362 #define IS_ZIO_THRESHOLD_CAPABLE(ha) \ 4363 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\ 4364 (ha->zio_mode == QLA_ZIO_MODE_6)) 4365 4366 /* HBA serial number */ 4367 uint8_t serial0; 4368 uint8_t serial1; 4369 uint8_t serial2; 4370 4371 /* NVRAM configuration data */ 4372 #define MAX_NVRAM_SIZE 4096 4373 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2) 4374 uint16_t nvram_size; 4375 uint16_t nvram_base; 4376 void *nvram; 4377 uint16_t vpd_size; 4378 uint16_t vpd_base; 4379 void *vpd; 4380 4381 uint16_t loop_reset_delay; 4382 uint8_t retry_count; 4383 uint8_t login_timeout; 4384 uint16_t r_a_tov; 4385 int port_down_retry_count; 4386 uint8_t mbx_count; 4387 uint8_t aen_mbx_count; 4388 atomic_t num_pend_mbx_stage1; 4389 atomic_t num_pend_mbx_stage2; 4390 atomic_t num_pend_mbx_stage3; 4391 uint16_t frame_payload_size; 4392 4393 uint32_t login_retry_count; 4394 /* SNS command interfaces. */ 4395 ms_iocb_entry_t *ms_iocb; 4396 dma_addr_t ms_iocb_dma; 4397 struct ct_sns_pkt *ct_sns; 4398 dma_addr_t ct_sns_dma; 4399 /* SNS command interfaces for 2200. */ 4400 struct sns_cmd_pkt *sns_cmd; 4401 dma_addr_t sns_cmd_dma; 4402 4403 #define SFP_DEV_SIZE 512 4404 #define SFP_BLOCK_SIZE 64 4405 #define SFP_RTDI_LEN SFP_BLOCK_SIZE 4406 4407 void *sfp_data; 4408 dma_addr_t sfp_data_dma; 4409 4410 struct qla_flt_header *flt; 4411 dma_addr_t flt_dma; 4412 4413 #define XGMAC_DATA_SIZE 4096 4414 void *xgmac_data; 4415 dma_addr_t xgmac_data_dma; 4416 4417 #define DCBX_TLV_DATA_SIZE 4096 4418 void *dcbx_tlv; 4419 dma_addr_t dcbx_tlv_dma; 4420 4421 struct task_struct *dpc_thread; 4422 uint8_t dpc_active; /* DPC routine is active */ 4423 4424 dma_addr_t gid_list_dma; 4425 struct gid_list_info *gid_list; 4426 int gid_list_info_size; 4427 4428 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 4429 #define DMA_POOL_SIZE 256 4430 struct dma_pool *s_dma_pool; 4431 4432 dma_addr_t init_cb_dma; 4433 init_cb_t *init_cb; 4434 int init_cb_size; 4435 dma_addr_t ex_init_cb_dma; 4436 struct ex_init_cb_81xx *ex_init_cb; 4437 dma_addr_t sf_init_cb_dma; 4438 struct init_sf_cb *sf_init_cb; 4439 4440 void *scm_fpin_els_buff; 4441 uint64_t scm_fpin_els_buff_size; 4442 bool scm_fpin_valid; 4443 bool scm_fpin_payload_size; 4444 4445 void *async_pd; 4446 dma_addr_t async_pd_dma; 4447 4448 #define ENABLE_EXTENDED_LOGIN BIT_7 4449 4450 /* Extended Logins */ 4451 void *exlogin_buf; 4452 dma_addr_t exlogin_buf_dma; 4453 uint32_t exlogin_size; 4454 4455 #define ENABLE_EXCHANGE_OFFLD BIT_2 4456 4457 /* Exchange Offload */ 4458 void *exchoffld_buf; 4459 dma_addr_t exchoffld_buf_dma; 4460 int exchoffld_size; 4461 int exchoffld_count; 4462 4463 /* n2n */ 4464 struct fc_els_flogi plogi_els_payld; 4465 #define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4) 4466 4467 void *swl; 4468 4469 /* These are used by mailbox operations. */ 4470 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 4471 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 4472 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 4473 4474 mbx_cmd_t *mcp; 4475 struct mbx_cmd_32 *mcp32; 4476 4477 unsigned long mbx_cmd_flags; 4478 #define MBX_INTERRUPT 1 4479 #define MBX_INTR_WAIT 2 4480 #define MBX_UPDATE_FLASH_ACTIVE 3 4481 4482 struct mutex vport_lock; /* Virtual port synchronization */ 4483 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 4484 struct mutex mq_lock; /* multi-queue synchronization */ 4485 struct completion mbx_cmd_comp; /* Serialize mbx access */ 4486 struct completion mbx_intr_comp; /* Used for completion notification */ 4487 struct completion dcbx_comp; /* For set port config notification */ 4488 struct completion lb_portup_comp; /* Used to wait for link up during 4489 * loopback */ 4490 #define DCBX_COMP_TIMEOUT 20 4491 #define LB_PORTUP_COMP_TIMEOUT 10 4492 4493 int notify_dcbx_comp; 4494 int notify_lb_portup_comp; 4495 struct mutex selflogin_lock; 4496 4497 /* Basic firmware related information. */ 4498 uint16_t fw_major_version; 4499 uint16_t fw_minor_version; 4500 uint16_t fw_subminor_version; 4501 uint16_t fw_attributes; 4502 uint16_t fw_attributes_h; 4503 #define FW_ATTR_H_NVME_FBURST BIT_1 4504 #define FW_ATTR_H_NVME BIT_10 4505 #define FW_ATTR_H_NVME_UPDATED BIT_14 4506 4507 /* About firmware SCM support */ 4508 #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12 4509 /* Brocade fabric attached */ 4510 #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000 4511 /* Cisco fabric attached */ 4512 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000 4513 #define FW_ATTR_EXT0_NVME2 BIT_13 4514 #define FW_ATTR_EXT0_EDIF BIT_5 4515 uint16_t fw_attributes_ext[2]; 4516 uint32_t fw_memory_size; 4517 uint32_t fw_transfer_size; 4518 uint32_t fw_srisc_address; 4519 #define RISC_START_ADDRESS_2100 0x1000 4520 #define RISC_START_ADDRESS_2300 0x800 4521 #define RISC_START_ADDRESS_2400 0x100000 4522 4523 uint16_t orig_fw_tgt_xcb_count; 4524 uint16_t cur_fw_tgt_xcb_count; 4525 uint16_t orig_fw_xcb_count; 4526 uint16_t cur_fw_xcb_count; 4527 uint16_t orig_fw_iocb_count; 4528 uint16_t cur_fw_iocb_count; 4529 uint16_t fw_max_fcf_count; 4530 4531 uint32_t fw_shared_ram_start; 4532 uint32_t fw_shared_ram_end; 4533 uint32_t fw_ddr_ram_start; 4534 uint32_t fw_ddr_ram_end; 4535 4536 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 4537 uint8_t fw_seriallink_options[4]; 4538 __le16 fw_seriallink_options24[4]; 4539 4540 uint8_t serdes_version[3]; 4541 uint8_t mpi_version[3]; 4542 uint32_t mpi_capabilities; 4543 uint8_t phy_version[3]; 4544 uint8_t pep_version[3]; 4545 4546 /* Firmware dump template */ 4547 struct fwdt { 4548 void *template; 4549 ulong length; 4550 ulong dump_size; 4551 } fwdt[2]; 4552 struct qla2xxx_fw_dump *fw_dump; 4553 uint32_t fw_dump_len; 4554 u32 fw_dump_alloc_len; 4555 bool fw_dumped; 4556 unsigned long fw_dump_cap_flags; 4557 #define RISC_PAUSE_CMPL 0 4558 #define DMA_SHUTDOWN_CMPL 1 4559 #define ISP_RESET_CMPL 2 4560 #define RISC_RDY_AFT_RESET 3 4561 #define RISC_SRAM_DUMP_CMPL 4 4562 #define RISC_EXT_MEM_DUMP_CMPL 5 4563 #define ISP_MBX_RDY 6 4564 #define ISP_SOFT_RESET_CMPL 7 4565 int fw_dump_reading; 4566 void *mpi_fw_dump; 4567 u32 mpi_fw_dump_len; 4568 unsigned int mpi_fw_dump_reading:1; 4569 unsigned int mpi_fw_dumped:1; 4570 int prev_minidump_failed; 4571 dma_addr_t eft_dma; 4572 void *eft; 4573 /* Current size of mctp dump is 0x086064 bytes */ 4574 #define MCTP_DUMP_SIZE 0x086064 4575 dma_addr_t mctp_dump_dma; 4576 void *mctp_dump; 4577 int mctp_dumped; 4578 int mctp_dump_reading; 4579 uint32_t chain_offset; 4580 struct dentry *dfs_dir; 4581 struct dentry *dfs_fce; 4582 struct dentry *dfs_tgt_counters; 4583 struct dentry *dfs_fw_resource_cnt; 4584 4585 dma_addr_t fce_dma; 4586 void *fce; 4587 uint32_t fce_bufs; 4588 uint16_t fce_mb[8]; 4589 uint64_t fce_wr, fce_rd; 4590 struct mutex fce_mutex; 4591 4592 uint32_t pci_attr; 4593 uint16_t chip_revision; 4594 4595 uint16_t product_id[4]; 4596 4597 uint8_t model_number[16+1]; 4598 char model_desc[80]; 4599 uint8_t adapter_id[16+1]; 4600 4601 /* Option ROM information. */ 4602 char *optrom_buffer; 4603 uint32_t optrom_size; 4604 int optrom_state; 4605 #define QLA_SWAITING 0 4606 #define QLA_SREADING 1 4607 #define QLA_SWRITING 2 4608 uint32_t optrom_region_start; 4609 uint32_t optrom_region_size; 4610 struct mutex optrom_mutex; 4611 4612 /* PCI expansion ROM image information. */ 4613 #define ROM_CODE_TYPE_BIOS 0 4614 #define ROM_CODE_TYPE_FCODE 1 4615 #define ROM_CODE_TYPE_EFI 3 4616 uint8_t bios_revision[2]; 4617 uint8_t efi_revision[2]; 4618 uint8_t fcode_revision[16]; 4619 uint32_t fw_revision[4]; 4620 4621 uint32_t gold_fw_version[4]; 4622 4623 /* Offsets for flash/nvram access (set to ~0 if not used). */ 4624 uint32_t flash_conf_off; 4625 uint32_t flash_data_off; 4626 uint32_t nvram_conf_off; 4627 uint32_t nvram_data_off; 4628 4629 uint32_t fdt_wrt_disable; 4630 uint32_t fdt_wrt_enable; 4631 uint32_t fdt_erase_cmd; 4632 uint32_t fdt_block_size; 4633 uint32_t fdt_unprotect_sec_cmd; 4634 uint32_t fdt_protect_sec_cmd; 4635 uint32_t fdt_wrt_sts_reg_cmd; 4636 4637 struct { 4638 uint32_t flt_region_flt; 4639 uint32_t flt_region_fdt; 4640 uint32_t flt_region_boot; 4641 uint32_t flt_region_boot_sec; 4642 uint32_t flt_region_fw; 4643 uint32_t flt_region_fw_sec; 4644 uint32_t flt_region_vpd_nvram; 4645 uint32_t flt_region_vpd_nvram_sec; 4646 uint32_t flt_region_vpd; 4647 uint32_t flt_region_vpd_sec; 4648 uint32_t flt_region_nvram; 4649 uint32_t flt_region_nvram_sec; 4650 uint32_t flt_region_npiv_conf; 4651 uint32_t flt_region_gold_fw; 4652 uint32_t flt_region_fcp_prio; 4653 uint32_t flt_region_bootload; 4654 uint32_t flt_region_img_status_pri; 4655 uint32_t flt_region_img_status_sec; 4656 uint32_t flt_region_aux_img_status_pri; 4657 uint32_t flt_region_aux_img_status_sec; 4658 }; 4659 uint8_t active_image; 4660 4661 /* Needed for BEACON */ 4662 uint16_t beacon_blink_led; 4663 uint8_t beacon_color_state; 4664 #define QLA_LED_GRN_ON 0x01 4665 #define QLA_LED_YLW_ON 0x02 4666 #define QLA_LED_ABR_ON 0x04 4667 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 4668 /* ISP2322: red, green, amber. */ 4669 uint16_t zio_mode; 4670 uint16_t zio_timer; 4671 4672 struct qla_msix_entry *msix_entries; 4673 4674 struct list_head vp_list; /* list of VP */ 4675 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 4676 sizeof(unsigned long)]; 4677 uint16_t num_vhosts; /* number of vports created */ 4678 uint16_t num_vsans; /* number of vsan created */ 4679 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 4680 int cur_vport_count; 4681 4682 struct qla_chip_state_84xx *cs84xx; 4683 struct isp_operations *isp_ops; 4684 struct workqueue_struct *wq; 4685 struct work_struct heartbeat_work; 4686 struct qlfc_fw fw_buf; 4687 unsigned long last_heartbeat_run_jiffies; 4688 4689 /* FCP_CMND priority support */ 4690 struct qla_fcp_prio_cfg *fcp_prio_cfg; 4691 4692 struct dma_pool *dl_dma_pool; 4693 #define DSD_LIST_DMA_POOL_SIZE 512 4694 4695 struct dma_pool *fcp_cmnd_dma_pool; 4696 mempool_t *ctx_mempool; 4697 #define FCP_CMND_DMA_POOL_SIZE 512 4698 4699 void __iomem *nx_pcibase; /* Base I/O address */ 4700 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 4701 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 4702 4703 uint32_t crb_win; 4704 uint32_t curr_window; 4705 uint32_t ddr_mn_window; 4706 unsigned long mn_win_crb; 4707 unsigned long ms_win_crb; 4708 int qdr_sn_window; 4709 uint32_t fcoe_dev_init_timeout; 4710 uint32_t fcoe_reset_timeout; 4711 rwlock_t hw_lock; 4712 uint16_t portnum; /* port number */ 4713 int link_width; 4714 struct fw_blob *hablob; 4715 struct qla82xx_legacy_intr_set nx_legacy_intr; 4716 4717 uint16_t gbl_dsd_inuse; 4718 uint16_t gbl_dsd_avail; 4719 struct list_head gbl_dsd_list; 4720 #define NUM_DSD_CHAIN 4096 4721 4722 uint8_t fw_type; 4723 uint32_t file_prd_off; /* File firmware product offset */ 4724 4725 uint32_t md_template_size; 4726 void *md_tmplt_hdr; 4727 dma_addr_t md_tmplt_hdr_dma; 4728 void *md_dump; 4729 uint32_t md_dump_size; 4730 4731 void *loop_id_map; 4732 4733 /* QLA83XX IDC specific fields */ 4734 uint32_t idc_audit_ts; 4735 uint32_t idc_extend_tmo; 4736 4737 /* DPC low-priority workqueue */ 4738 struct workqueue_struct *dpc_lp_wq; 4739 struct work_struct idc_aen; 4740 /* DPC high-priority workqueue */ 4741 struct workqueue_struct *dpc_hp_wq; 4742 struct work_struct nic_core_reset; 4743 struct work_struct idc_state_handler; 4744 struct work_struct nic_core_unrecoverable; 4745 struct work_struct board_disable; 4746 4747 struct mr_data_fx00 mr; 4748 uint32_t chip_reset; 4749 4750 struct qlt_hw_data tgt; 4751 int allow_cna_fw_dump; 4752 uint32_t fw_ability_mask; 4753 uint16_t min_supported_speed; 4754 uint16_t max_supported_speed; 4755 4756 /* DMA pool for the DIF bundling buffers */ 4757 struct dma_pool *dif_bundl_pool; 4758 #define DIF_BUNDLING_DMA_POOL_SIZE 1024 4759 struct { 4760 struct { 4761 struct list_head head; 4762 uint count; 4763 } good; 4764 struct { 4765 struct list_head head; 4766 uint count; 4767 } unusable; 4768 } pool; 4769 4770 unsigned long long dif_bundle_crossed_pages; 4771 unsigned long long dif_bundle_reads; 4772 unsigned long long dif_bundle_writes; 4773 unsigned long long dif_bundle_kallocs; 4774 unsigned long long dif_bundle_dma_allocs; 4775 4776 atomic_t nvme_active_aen_cnt; 4777 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */ 4778 4779 uint8_t fc4_type_priority; 4780 4781 atomic_t zio_threshold; 4782 uint16_t last_zio_threshold; 4783 4784 #define DEFAULT_ZIO_THRESHOLD 5 4785 4786 struct qla_hw_data_stat stat; 4787 pci_error_state_t pci_error_state; 4788 struct dma_pool *purex_dma_pool; 4789 struct btree_head32 host_map; 4790 4791 #define EDIF_NUM_SA_INDEX 512 4792 #define EDIF_TX_SA_INDEX_BASE EDIF_NUM_SA_INDEX 4793 void *edif_rx_sa_id_map; 4794 void *edif_tx_sa_id_map; 4795 spinlock_t sadb_fp_lock; 4796 4797 struct list_head sadb_tx_index_list; 4798 struct list_head sadb_rx_index_list; 4799 spinlock_t sadb_lock; /* protects list */ 4800 struct els_reject elsrej; 4801 u8 edif_post_stop_cnt_down; 4802 struct qla_vp_map *vp_map; 4803 }; 4804 4805 #define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES)) 4806 4807 struct active_regions { 4808 uint8_t global; 4809 struct { 4810 uint8_t board_config; 4811 uint8_t vpd_nvram; 4812 uint8_t npiv_config_0_1; 4813 uint8_t npiv_config_2_3; 4814 uint8_t nvme_params; 4815 } aux; 4816 }; 4817 4818 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL 4819 #define FW_ABILITY_MAX_SPEED_16G 0x0 4820 #define FW_ABILITY_MAX_SPEED_32G 0x1 4821 #define FW_ABILITY_MAX_SPEED(ha) \ 4822 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK) 4823 4824 #define QLA_GET_DATA_RATE 0 4825 #define QLA_SET_DATA_RATE_NOLR 1 4826 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */ 4827 4828 #define QLA_DEFAULT_PAYLOAD_SIZE 64 4829 /* 4830 * This item might be allocated with a size > sizeof(struct purex_item). 4831 * The "size" variable gives the size of the payload (which 4832 * is variable) starting at "iocb". 4833 */ 4834 struct purex_item { 4835 struct list_head list; 4836 struct scsi_qla_host *vha; 4837 void (*process_item)(struct scsi_qla_host *vha, 4838 struct purex_item *pkt); 4839 atomic_t in_use; 4840 uint16_t size; 4841 struct { 4842 uint8_t iocb[64]; 4843 } iocb; 4844 }; 4845 4846 #include "qla_edif.h" 4847 4848 #define SCM_FLAG_RDF_REJECT 0x00 4849 #define SCM_FLAG_RDF_COMPLETED 0x01 4850 4851 #define QLA_CON_PRIMITIVE_RECEIVED 0x1 4852 #define QLA_CONGESTION_ARB_WARNING 0x1 4853 #define QLA_CONGESTION_ARB_ALARM 0X2 4854 4855 /* 4856 * Qlogic scsi host structure 4857 */ 4858 typedef struct scsi_qla_host { 4859 struct list_head list; 4860 struct list_head vp_fcports; /* list of fcports */ 4861 struct list_head work_list; 4862 spinlock_t work_lock; 4863 struct work_struct iocb_work; 4864 4865 /* Commonly used flags and state information. */ 4866 struct Scsi_Host *host; 4867 unsigned long host_no; 4868 uint8_t host_str[16]; 4869 4870 volatile struct { 4871 uint32_t init_done :1; 4872 uint32_t online :1; 4873 uint32_t reset_active :1; 4874 4875 uint32_t management_server_logged_in :1; 4876 uint32_t process_response_queue :1; 4877 uint32_t difdix_supported:1; 4878 uint32_t delete_progress:1; 4879 4880 uint32_t fw_tgt_reported:1; 4881 uint32_t bbcr_enable:1; 4882 uint32_t qpairs_available:1; 4883 uint32_t qpairs_req_created:1; 4884 uint32_t qpairs_rsp_created:1; 4885 uint32_t nvme_enabled:1; 4886 uint32_t nvme_first_burst:1; 4887 uint32_t nvme2_enabled:1; 4888 } flags; 4889 4890 atomic_t loop_state; 4891 #define LOOP_TIMEOUT 1 4892 #define LOOP_DOWN 2 4893 #define LOOP_UP 3 4894 #define LOOP_UPDATE 4 4895 #define LOOP_READY 5 4896 #define LOOP_DEAD 6 4897 4898 unsigned long buf_expired; 4899 unsigned long relogin_jif; 4900 unsigned long dpc_flags; 4901 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 4902 #define RESET_ACTIVE 1 4903 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 4904 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 4905 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 4906 #define LOOP_RESYNC_ACTIVE 5 4907 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 4908 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 4909 #define RELOGIN_NEEDED 8 4910 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 4911 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 4912 #define BEACON_BLINK_NEEDED 11 4913 #define REGISTER_FDMI_NEEDED 12 4914 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 4915 #define UNLOADING 15 4916 #define NPIV_CONFIG_NEEDED 16 4917 #define ISP_UNRECOVERABLE 17 4918 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 4919 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 4920 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 4921 #define N2N_LINK_RESET 21 4922 #define PORT_UPDATE_NEEDED 22 4923 #define FX00_RESET_RECOVERY 23 4924 #define FX00_TARGET_SCAN 24 4925 #define FX00_CRITEMP_RECOVERY 25 4926 #define FX00_HOST_INFO_RESEND 26 4927 #define QPAIR_ONLINE_CHECK_NEEDED 27 4928 #define DO_EEH_RECOVERY 28 4929 #define DETECT_SFP_CHANGE 29 4930 #define N2N_LOGIN_NEEDED 30 4931 #define IOCB_WORK_ACTIVE 31 4932 #define SET_ZIO_THRESHOLD_NEEDED 32 4933 #define ISP_ABORT_TO_ROM 33 4934 #define VPORT_DELETE 34 4935 4936 #define PROCESS_PUREX_IOCB 63 4937 4938 unsigned long pci_flags; 4939 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 4940 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 4941 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 4942 4943 uint32_t device_flags; 4944 #define SWITCH_FOUND BIT_0 4945 #define DFLG_NO_CABLE BIT_1 4946 #define DFLG_DEV_FAILED BIT_5 4947 4948 /* ISP configuration data. */ 4949 uint16_t loop_id; /* Host adapter loop id */ 4950 uint16_t self_login_loop_id; /* host adapter loop id 4951 * get it on self login 4952 */ 4953 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 4954 * no need of allocating it for 4955 * each command 4956 */ 4957 4958 port_id_t d_id; /* Host adapter port id */ 4959 uint8_t marker_needed; 4960 uint16_t mgmt_svr_loop_id; 4961 4962 4963 4964 /* Timeout timers. */ 4965 uint8_t loop_down_abort_time; /* port down timer */ 4966 atomic_t loop_down_timer; /* loop down timer */ 4967 uint8_t link_down_timeout; /* link down timeout */ 4968 4969 uint32_t timer_active; 4970 struct timer_list timer; 4971 4972 uint8_t node_name[WWN_SIZE]; 4973 uint8_t port_name[WWN_SIZE]; 4974 uint8_t fabric_node_name[WWN_SIZE]; 4975 uint8_t fabric_port_name[WWN_SIZE]; 4976 4977 struct nvme_fc_local_port *nvme_local_port; 4978 struct completion nvme_del_done; 4979 4980 uint16_t fcoe_vlan_id; 4981 uint16_t fcoe_fcf_idx; 4982 uint8_t fcoe_vn_port_mac[6]; 4983 4984 /* list of commands waiting on workqueue */ 4985 struct list_head qla_cmd_list; 4986 struct list_head unknown_atio_list; 4987 spinlock_t cmd_list_lock; 4988 struct delayed_work unknown_atio_work; 4989 4990 /* Counter to detect races between ELS and RSCN events */ 4991 atomic_t generation_tick; 4992 /* Time when global fcport update has been scheduled */ 4993 int total_fcport_update_gen; 4994 /* List of pending LOGOs, protected by tgt_mutex */ 4995 struct list_head logo_list; 4996 /* List of pending PLOGI acks, protected by hw lock */ 4997 struct list_head plogi_ack_list; 4998 4999 struct list_head qp_list; 5000 5001 uint32_t vp_abort_cnt; 5002 5003 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 5004 uint16_t vp_idx; /* vport ID */ 5005 struct qla_qpair *qpair; /* base qpair */ 5006 5007 unsigned long vp_flags; 5008 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 5009 #define VP_CREATE_NEEDED 1 5010 #define VP_BIND_NEEDED 2 5011 #define VP_DELETE_NEEDED 3 5012 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 5013 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 5014 atomic_t vp_state; 5015 #define VP_OFFLINE 0 5016 #define VP_ACTIVE 1 5017 #define VP_FAILED 2 5018 // #define VP_DISABLE 3 5019 uint16_t vp_err_state; 5020 uint16_t vp_prev_err_state; 5021 #define VP_ERR_UNKWN 0 5022 #define VP_ERR_PORTDWN 1 5023 #define VP_ERR_FAB_UNSUPPORTED 2 5024 #define VP_ERR_FAB_NORESOURCES 3 5025 #define VP_ERR_FAB_LOGOUT 4 5026 #define VP_ERR_ADAP_NORESOURCES 5 5027 struct qla_hw_data *hw; 5028 struct scsi_qlt_host vha_tgt; 5029 struct req_que *req; 5030 int fw_heartbeat_counter; 5031 int seconds_since_last_heartbeat; 5032 struct fc_host_statistics fc_host_stat; 5033 struct qla_statistics qla_stats; 5034 struct bidi_statistics bidi_stats; 5035 atomic_t vref_count; 5036 struct qla8044_reset_template reset_tmplt; 5037 uint16_t bbcr; 5038 5039 uint16_t u_ql2xexchoffld; 5040 uint16_t u_ql2xiniexchg; 5041 uint16_t qlini_mode; 5042 uint16_t ql2xexchoffld; 5043 uint16_t ql2xiniexchg; 5044 5045 struct dentry *dfs_rport_root; 5046 5047 struct purex_list { 5048 struct list_head head; 5049 spinlock_t lock; 5050 } purex_list; 5051 struct purex_item default_item; 5052 5053 struct name_list_extended gnl; 5054 /* Count of active session/fcport */ 5055 int fcport_count; 5056 wait_queue_head_t fcport_waitQ; 5057 wait_queue_head_t vref_waitq; 5058 uint8_t min_supported_speed; 5059 uint8_t n2n_node_name[WWN_SIZE]; 5060 uint8_t n2n_port_name[WWN_SIZE]; 5061 uint16_t n2n_id; 5062 __le16 dport_data[4]; 5063 struct fab_scan scan; 5064 uint8_t scm_fabric_connection_flags; 5065 5066 unsigned int irq_offset; 5067 5068 u64 hw_err_cnt; 5069 u64 interface_err_cnt; 5070 u64 cmd_timeout_cnt; 5071 u64 reset_cmd_err_cnt; 5072 u64 link_down_time; 5073 u64 short_link_down_cnt; 5074 struct edif_dbell e_dbell; 5075 struct pur_core pur_cinfo; 5076 5077 #define DPORT_DIAG_IN_PROGRESS BIT_0 5078 #define DPORT_DIAG_CHIP_RESET_IN_PROGRESS BIT_1 5079 uint16_t dport_status; 5080 } scsi_qla_host_t; 5081 5082 struct qla27xx_image_status { 5083 uint8_t image_status_mask; 5084 __le16 generation; 5085 uint8_t ver_major; 5086 uint8_t ver_minor; 5087 uint8_t bitmap; /* 28xx only */ 5088 uint8_t reserved[2]; 5089 __le32 checksum; 5090 __le32 signature; 5091 } __packed; 5092 5093 /* 28xx aux image status bimap values */ 5094 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0 5095 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1 5096 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2 5097 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3 5098 #define QLA28XX_AUX_IMG_NVME_PARAMS BIT_4 5099 5100 #define SET_VP_IDX 1 5101 #define SET_AL_PA 2 5102 #define RESET_VP_IDX 3 5103 #define RESET_AL_PA 4 5104 struct qla_vp_map { 5105 uint8_t idx; 5106 scsi_qla_host_t *vha; 5107 }; 5108 5109 struct qla2_sgx { 5110 dma_addr_t dma_addr; /* OUT */ 5111 uint32_t dma_len; /* OUT */ 5112 5113 uint32_t tot_bytes; /* IN */ 5114 struct scatterlist *cur_sg; /* IN */ 5115 5116 /* for book keeping, bzero on initial invocation */ 5117 uint32_t bytes_consumed; 5118 uint32_t num_bytes; 5119 uint32_t tot_partial; 5120 5121 /* for debugging */ 5122 uint32_t num_sg; 5123 srb_t *sp; 5124 }; 5125 5126 #define QLA_FW_STARTED(_ha) { \ 5127 int i; \ 5128 _ha->flags.fw_started = 1; \ 5129 _ha->base_qpair->fw_started = 1; \ 5130 for (i = 0; i < _ha->max_qpairs; i++) { \ 5131 if (_ha->queue_pair_map[i]) \ 5132 _ha->queue_pair_map[i]->fw_started = 1; \ 5133 } \ 5134 } 5135 5136 #define QLA_FW_STOPPED(_ha) { \ 5137 int i; \ 5138 _ha->flags.fw_started = 0; \ 5139 _ha->base_qpair->fw_started = 0; \ 5140 for (i = 0; i < _ha->max_qpairs; i++) { \ 5141 if (_ha->queue_pair_map[i]) \ 5142 _ha->queue_pair_map[i]->fw_started = 0; \ 5143 } \ 5144 } 5145 5146 5147 #define SFUB_CHECKSUM_SIZE 4 5148 5149 struct secure_flash_update_block { 5150 uint32_t block_info; 5151 uint32_t signature_lo; 5152 uint32_t signature_hi; 5153 uint32_t signature_upper[0x3e]; 5154 }; 5155 5156 struct secure_flash_update_block_pk { 5157 uint32_t block_info; 5158 uint32_t signature_lo; 5159 uint32_t signature_hi; 5160 uint32_t signature_upper[0x3e]; 5161 uint32_t public_key[0x41]; 5162 }; 5163 5164 /* 5165 * Macros to help code, maintain, etc. 5166 */ 5167 #define LOOP_TRANSITION(ha) \ 5168 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5169 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 5170 atomic_read(&ha->loop_state) == LOOP_DOWN) 5171 5172 #define STATE_TRANSITION(ha) \ 5173 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 5174 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 5175 5176 static inline bool qla_vha_mark_busy(scsi_qla_host_t *vha) 5177 { 5178 atomic_inc(&vha->vref_count); 5179 mb(); 5180 if (vha->flags.delete_progress) { 5181 atomic_dec(&vha->vref_count); 5182 wake_up(&vha->vref_waitq); 5183 return true; 5184 } 5185 return false; 5186 } 5187 5188 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 5189 atomic_dec(&__vha->vref_count); \ 5190 wake_up(&__vha->vref_waitq); \ 5191 } while (0) \ 5192 5193 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \ 5194 atomic_inc(&__qpair->ref_count); \ 5195 mb(); \ 5196 if (__qpair->delete_in_progress) { \ 5197 atomic_dec(&__qpair->ref_count); \ 5198 __bail = 1; \ 5199 } else { \ 5200 __bail = 0; \ 5201 } \ 5202 } while (0) 5203 5204 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \ 5205 atomic_dec(&__qpair->ref_count) 5206 5207 #define QLA_ENA_CONF(_ha) {\ 5208 int i;\ 5209 _ha->base_qpair->enable_explicit_conf = 1; \ 5210 for (i = 0; i < _ha->max_qpairs; i++) { \ 5211 if (_ha->queue_pair_map[i]) \ 5212 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \ 5213 } \ 5214 } 5215 5216 #define QLA_DIS_CONF(_ha) {\ 5217 int i;\ 5218 _ha->base_qpair->enable_explicit_conf = 0; \ 5219 for (i = 0; i < _ha->max_qpairs; i++) { \ 5220 if (_ha->queue_pair_map[i]) \ 5221 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \ 5222 } \ 5223 } 5224 5225 /* 5226 * qla2x00 local function return status codes 5227 */ 5228 #define MBS_MASK 0x3fff 5229 5230 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 5231 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 5232 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 5233 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 5234 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 5235 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 5236 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 5237 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 5238 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 5239 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 5240 5241 #define QLA_FUNCTION_TIMEOUT 0x100 5242 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 5243 #define QLA_FUNCTION_FAILED 0x102 5244 #define QLA_MEMORY_ALLOC_FAILED 0x103 5245 #define QLA_LOCK_TIMEOUT 0x104 5246 #define QLA_ABORTED 0x105 5247 #define QLA_SUSPENDED 0x106 5248 #define QLA_BUSY 0x107 5249 #define QLA_ALREADY_REGISTERED 0x109 5250 #define QLA_OS_TIMER_EXPIRED 0x10a 5251 #define QLA_ERR_NO_QPAIR 0x10b 5252 #define QLA_ERR_NOT_FOUND 0x10c 5253 #define QLA_ERR_FROM_FW 0x10d 5254 5255 #define NVRAM_DELAY() udelay(10) 5256 5257 /* 5258 * Flash support definitions 5259 */ 5260 #define OPTROM_SIZE_2300 0x20000 5261 #define OPTROM_SIZE_2322 0x100000 5262 #define OPTROM_SIZE_24XX 0x100000 5263 #define OPTROM_SIZE_25XX 0x200000 5264 #define OPTROM_SIZE_81XX 0x400000 5265 #define OPTROM_SIZE_82XX 0x800000 5266 #define OPTROM_SIZE_83XX 0x1000000 5267 #define OPTROM_SIZE_28XX 0x2000000 5268 5269 #define OPTROM_BURST_SIZE 0x1000 5270 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 5271 5272 #define QLA_DSDS_PER_IOCB 37 5273 5274 #define QLA_SG_ALL 1024 5275 5276 enum nexus_wait_type { 5277 WAIT_HOST = 0, 5278 WAIT_TARGET, 5279 WAIT_LUN, 5280 }; 5281 5282 #define INVALID_EDIF_SA_INDEX 0xffff 5283 #define RX_DELETE_NO_EDIF_SA_INDEX 0xfffe 5284 5285 #define QLA_SKIP_HANDLE QLA_TGT_SKIP_HANDLE 5286 5287 /* edif hash element */ 5288 struct edif_list_entry { 5289 uint16_t handle; /* nport_handle */ 5290 uint32_t update_sa_index; 5291 uint32_t delete_sa_index; 5292 uint32_t count; /* counter for filtering sa_index */ 5293 #define EDIF_ENTRY_FLAGS_CLEANUP 0x01 /* this index is being cleaned up */ 5294 uint32_t flags; /* used by sadb cleanup code */ 5295 fc_port_t *fcport; /* needed by rx delay timer function */ 5296 struct timer_list timer; /* rx delay timer */ 5297 struct list_head next; 5298 }; 5299 5300 #define EDIF_TX_INDX_BASE 512 5301 #define EDIF_RX_INDX_BASE 0 5302 #define EDIF_RX_DELETE_FILTER_COUNT 3 /* delay queuing rx delete until this many */ 5303 5304 /* entry in the sa_index free pool */ 5305 5306 struct sa_index_pair { 5307 uint16_t sa_index; 5308 uint32_t spi; 5309 }; 5310 5311 /* edif sa_index data structure */ 5312 struct edif_sa_index_entry { 5313 struct sa_index_pair sa_pair[2]; 5314 fc_port_t *fcport; 5315 uint16_t handle; 5316 struct list_head next; 5317 }; 5318 5319 /* Refer to SNIA SFF 8247 */ 5320 struct sff_8247_a0 { 5321 u8 txid; /* transceiver id */ 5322 u8 ext_txid; 5323 u8 connector; 5324 /* compliance code */ 5325 u8 eth_infi_cc3; /* ethernet, inifiband */ 5326 u8 sonet_cc4[2]; 5327 u8 eth_cc6; 5328 /* link length */ 5329 #define FC_LL_VL BIT_7 /* very long */ 5330 #define FC_LL_S BIT_6 /* Short */ 5331 #define FC_LL_I BIT_5 /* Intermidiate*/ 5332 #define FC_LL_L BIT_4 /* Long */ 5333 #define FC_LL_M BIT_3 /* Medium */ 5334 #define FC_LL_SA BIT_2 /* ShortWave laser */ 5335 #define FC_LL_LC BIT_1 /* LongWave laser */ 5336 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */ 5337 u8 fc_ll_cc7; 5338 /* FC technology */ 5339 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */ 5340 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */ 5341 #define FC_TEC_SL BIT_5 /* short wave with OFC */ 5342 #define FC_TEC_LL BIT_4 /* Longwave Laser */ 5343 #define FC_TEC_ACT BIT_3 /* Active cable */ 5344 #define FC_TEC_PAS BIT_2 /* Passive cable */ 5345 u8 fc_tec_cc8; 5346 /* Transmission Media */ 5347 #define FC_MED_TW BIT_7 /* Twin Ax */ 5348 #define FC_MED_TP BIT_6 /* Twited Pair */ 5349 #define FC_MED_MI BIT_5 /* Min Coax */ 5350 #define FC_MED_TV BIT_4 /* Video Coax */ 5351 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */ 5352 #define FC_MED_M5 BIT_2 /* Multimode, 50um */ 5353 #define FC_MED_SM BIT_0 /* Single Mode */ 5354 u8 fc_med_cc9; 5355 /* speed FC_SP_12: 12*100M = 1200 MB/s */ 5356 #define FC_SP_12 BIT_7 5357 #define FC_SP_8 BIT_6 5358 #define FC_SP_16 BIT_5 5359 #define FC_SP_4 BIT_4 5360 #define FC_SP_32 BIT_3 5361 #define FC_SP_2 BIT_2 5362 #define FC_SP_1 BIT_0 5363 u8 fc_sp_cc10; 5364 u8 encode; 5365 u8 bitrate; 5366 u8 rate_id; 5367 u8 length_km; /* offset 14/eh */ 5368 u8 length_100m; 5369 u8 length_50um_10m; 5370 u8 length_62um_10m; 5371 u8 length_om4_10m; 5372 u8 length_om3_10m; 5373 #define SFF_VEN_NAME_LEN 16 5374 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */ 5375 u8 tx_compat; 5376 u8 vendor_oui[3]; 5377 #define SFF_PART_NAME_LEN 16 5378 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */ 5379 u8 vendor_rev[4]; 5380 u8 wavelength[2]; 5381 u8 resv; 5382 u8 cc_base; 5383 u8 options[2]; /* offset 64 */ 5384 u8 br_max; 5385 u8 br_min; 5386 u8 vendor_sn[16]; 5387 u8 date_code[8]; 5388 u8 diag; 5389 u8 enh_options; 5390 u8 sff_revision; 5391 u8 cc_ext; 5392 u8 vendor_specific[32]; 5393 u8 resv2[128]; 5394 }; 5395 5396 /* BPM -- Buffer Plus Management support. */ 5397 #define IS_BPM_CAPABLE(ha) \ 5398 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 5399 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5400 #define IS_BPM_RANGE_CAPABLE(ha) \ 5401 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 5402 #define IS_BPM_ENABLED(vha) \ 5403 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw)) 5404 5405 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016 5406 5407 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \ 5408 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha))) 5409 5410 #define SAVE_TOPO(_ha) { \ 5411 if (_ha->current_topology) \ 5412 _ha->prev_topology = _ha->current_topology; \ 5413 } 5414 5415 #define N2N_TOPO(ha) \ 5416 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \ 5417 ha->current_topology == ISP_CFG_N || \ 5418 !ha->current_topology) 5419 5420 #define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */ 5421 5422 #define NVME_TYPE(fcport) \ 5423 (fcport->fc4_type & FS_FC4TYPE_NVME) \ 5424 5425 #define FCP_TYPE(fcport) \ 5426 (fcport->fc4_type & FS_FC4TYPE_FCP) \ 5427 5428 #define NVME_ONLY_TARGET(fcport) \ 5429 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \ 5430 5431 #define NVME_FCP_TARGET(fcport) \ 5432 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \ 5433 5434 #define NVME_PRIORITY(ha, fcport) \ 5435 (NVME_FCP_TARGET(fcport) && \ 5436 (ha->fc4_type_priority == FC4_PRIORITY_NVME)) 5437 5438 #define NVME_TARGET(ha, fcport) \ 5439 (fcport->do_prli_nvme || \ 5440 NVME_ONLY_TARGET(fcport)) \ 5441 5442 #define PRLI_PHASE(_cls) \ 5443 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP)) 5444 5445 enum ql_vnd_host_stat_action { 5446 QLA_STOP = 0, 5447 QLA_START, 5448 QLA_CLEAR, 5449 }; 5450 5451 struct ql_vnd_mng_host_stats_param { 5452 u32 stat_type; 5453 enum ql_vnd_host_stat_action action; 5454 } __packed; 5455 5456 struct ql_vnd_mng_host_stats_resp { 5457 u32 status; 5458 } __packed; 5459 5460 struct ql_vnd_stats_param { 5461 u32 stat_type; 5462 } __packed; 5463 5464 struct ql_vnd_tgt_stats_param { 5465 s32 tgt_id; 5466 u32 stat_type; 5467 } __packed; 5468 5469 enum ql_vnd_host_port_action { 5470 QLA_ENABLE = 0, 5471 QLA_DISABLE, 5472 }; 5473 5474 struct ql_vnd_mng_host_port_param { 5475 enum ql_vnd_host_port_action action; 5476 } __packed; 5477 5478 struct ql_vnd_mng_host_port_resp { 5479 u32 status; 5480 } __packed; 5481 5482 struct ql_vnd_stat_entry { 5483 u32 stat_type; /* Failure type */ 5484 u32 tgt_num; /* Target Num */ 5485 u64 cnt; /* Counter value */ 5486 } __packed; 5487 5488 struct ql_vnd_stats { 5489 u64 entry_count; /* Num of entries */ 5490 u64 rservd; 5491 struct ql_vnd_stat_entry entry[]; /* Place holder of entries */ 5492 } __packed; 5493 5494 struct ql_vnd_host_stats_resp { 5495 u32 status; 5496 struct ql_vnd_stats stats; 5497 } __packed; 5498 5499 struct ql_vnd_tgt_stats_resp { 5500 u32 status; 5501 struct ql_vnd_stats stats; 5502 } __packed; 5503 5504 #include "qla_target.h" 5505 #include "qla_gbl.h" 5506 #include "qla_dbg.h" 5507 #include "qla_inline.h" 5508 5509 #define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND || \ 5510 _fcport->disc_state == DSC_DELETED) 5511 5512 #define DBG_FCPORT_PRFMT(_fp, _fmt, _args...) \ 5513 "%s: %8phC: " _fmt " (state=%d disc_state=%d scan_state=%d loopid=0x%x deleted=%d flags=0x%x)\n", \ 5514 __func__, _fp->port_name, ##_args, atomic_read(&_fp->state), \ 5515 _fp->disc_state, _fp->scan_state, _fp->loop_id, _fp->deleted, \ 5516 _fp->flags 5517 5518 #define TMF_NOT_READY(_fcport) \ 5519 (!_fcport || IS_SESSION_DELETED(_fcport) || atomic_read(&_fcport->state) != FCS_ONLINE || \ 5520 !_fcport->vha->hw->flags.fw_started) 5521 5522 #endif 5523