1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2008 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8 #include "qla_def.h" 9 10 /* 11 * Driver debug definitions. 12 */ 13 /* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM1 */ 14 /* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM1 */ 15 /* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM1 */ 16 /* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM1 */ 17 /* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM1 */ 18 /* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM1 */ 19 /* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM1 */ 20 /* #define QL_DEBUG_LEVEL_8 */ /* Output ring saturation msgs to COM1 */ 21 /* #define QL_DEBUG_LEVEL_9 */ /* Output IOCTL trace msgs */ 22 /* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */ 23 /* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */ 24 /* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */ 25 /* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */ 26 /* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */ 27 /* #define QL_DEBUG_LEVEL_15 */ /* Output NPIV trace msgs */ 28 /* #define QL_DEBUG_LEVEL_16 */ /* Output ISP84XX trace msgs */ 29 /* #define QL_DEBUG_LEVEL_17 */ /* Output EEH trace messages */ 30 31 /* 32 * Macros use for debugging the driver. 33 */ 34 35 #define DEBUG(x) do { if (ql2xextended_error_logging) { x; } } while (0) 36 37 #if defined(QL_DEBUG_LEVEL_1) 38 #define DEBUG1(x) do {x;} while (0) 39 #else 40 #define DEBUG1(x) do {} while (0) 41 #endif 42 43 #define DEBUG2(x) do { if (ql2xextended_error_logging) { x; } } while (0) 44 #define DEBUG2_3(x) do { if (ql2xextended_error_logging) { x; } } while (0) 45 #define DEBUG2_3_11(x) do { if (ql2xextended_error_logging) { x; } } while (0) 46 #define DEBUG2_9_10(x) do { if (ql2xextended_error_logging) { x; } } while (0) 47 #define DEBUG2_11(x) do { if (ql2xextended_error_logging) { x; } } while (0) 48 #define DEBUG2_13(x) do { if (ql2xextended_error_logging) { x; } } while (0) 49 #define DEBUG2_16(x) do { if (ql2xextended_error_logging) { x; } } while (0) 50 #define DEBUG2_17(x) do { if (ql2xextended_error_logging) { x; } } while (0) 51 52 #if defined(QL_DEBUG_LEVEL_3) 53 #define DEBUG3(x) do {x;} while (0) 54 #define DEBUG3_11(x) do {x;} while (0) 55 #else 56 #define DEBUG3(x) do {} while (0) 57 #endif 58 59 #if defined(QL_DEBUG_LEVEL_4) 60 #define DEBUG4(x) do {x;} while (0) 61 #else 62 #define DEBUG4(x) do {} while (0) 63 #endif 64 65 #if defined(QL_DEBUG_LEVEL_5) 66 #define DEBUG5(x) do {x;} while (0) 67 #else 68 #define DEBUG5(x) do {} while (0) 69 #endif 70 71 #if defined(QL_DEBUG_LEVEL_7) 72 #define DEBUG7(x) do {x;} while (0) 73 #else 74 #define DEBUG7(x) do {} while (0) 75 #endif 76 77 #if defined(QL_DEBUG_LEVEL_9) 78 #define DEBUG9(x) do {x;} while (0) 79 #define DEBUG9_10(x) do {x;} while (0) 80 #else 81 #define DEBUG9(x) do {} while (0) 82 #endif 83 84 #if defined(QL_DEBUG_LEVEL_10) 85 #define DEBUG10(x) do {x;} while (0) 86 #define DEBUG9_10(x) do {x;} while (0) 87 #else 88 #define DEBUG10(x) do {} while (0) 89 #if !defined(DEBUG9_10) 90 #define DEBUG9_10(x) do {} while (0) 91 #endif 92 #endif 93 94 #if defined(QL_DEBUG_LEVEL_11) 95 #define DEBUG11(x) do{x;} while(0) 96 #if !defined(DEBUG3_11) 97 #define DEBUG3_11(x) do{x;} while(0) 98 #endif 99 #else 100 #define DEBUG11(x) do{} while(0) 101 #if !defined(QL_DEBUG_LEVEL_3) 102 #define DEBUG3_11(x) do{} while(0) 103 #endif 104 #endif 105 106 #if defined(QL_DEBUG_LEVEL_12) 107 #define DEBUG12(x) do {x;} while (0) 108 #else 109 #define DEBUG12(x) do {} while (0) 110 #endif 111 112 #if defined(QL_DEBUG_LEVEL_13) 113 #define DEBUG13(x) do {x;} while (0) 114 #else 115 #define DEBUG13(x) do {} while (0) 116 #endif 117 118 #if defined(QL_DEBUG_LEVEL_14) 119 #define DEBUG14(x) do {x;} while (0) 120 #else 121 #define DEBUG14(x) do {} while (0) 122 #endif 123 124 #if defined(QL_DEBUG_LEVEL_15) 125 #define DEBUG15(x) do {x;} while (0) 126 #else 127 #define DEBUG15(x) do {} while (0) 128 #endif 129 130 #if defined(QL_DEBUG_LEVEL_16) 131 #define DEBUG16(x) do {x;} while (0) 132 #else 133 #define DEBUG16(x) do {} while (0) 134 #endif 135 136 #if defined(QL_DEBUG_LEVEL_17) 137 #define DEBUG17(x) do {x;} while (0) 138 #else 139 #define DEBUG17(x) do {} while (0) 140 #endif 141 142 /* 143 * Firmware Dump structure definition 144 */ 145 146 struct qla2300_fw_dump { 147 uint16_t hccr; 148 uint16_t pbiu_reg[8]; 149 uint16_t risc_host_reg[8]; 150 uint16_t mailbox_reg[32]; 151 uint16_t resp_dma_reg[32]; 152 uint16_t dma_reg[48]; 153 uint16_t risc_hdw_reg[16]; 154 uint16_t risc_gp0_reg[16]; 155 uint16_t risc_gp1_reg[16]; 156 uint16_t risc_gp2_reg[16]; 157 uint16_t risc_gp3_reg[16]; 158 uint16_t risc_gp4_reg[16]; 159 uint16_t risc_gp5_reg[16]; 160 uint16_t risc_gp6_reg[16]; 161 uint16_t risc_gp7_reg[16]; 162 uint16_t frame_buf_hdw_reg[64]; 163 uint16_t fpm_b0_reg[64]; 164 uint16_t fpm_b1_reg[64]; 165 uint16_t risc_ram[0xf800]; 166 uint16_t stack_ram[0x1000]; 167 uint16_t data_ram[1]; 168 }; 169 170 struct qla2100_fw_dump { 171 uint16_t hccr; 172 uint16_t pbiu_reg[8]; 173 uint16_t mailbox_reg[32]; 174 uint16_t dma_reg[48]; 175 uint16_t risc_hdw_reg[16]; 176 uint16_t risc_gp0_reg[16]; 177 uint16_t risc_gp1_reg[16]; 178 uint16_t risc_gp2_reg[16]; 179 uint16_t risc_gp3_reg[16]; 180 uint16_t risc_gp4_reg[16]; 181 uint16_t risc_gp5_reg[16]; 182 uint16_t risc_gp6_reg[16]; 183 uint16_t risc_gp7_reg[16]; 184 uint16_t frame_buf_hdw_reg[16]; 185 uint16_t fpm_b0_reg[64]; 186 uint16_t fpm_b1_reg[64]; 187 uint16_t risc_ram[0xf000]; 188 }; 189 190 struct qla24xx_fw_dump { 191 uint32_t host_status; 192 uint32_t host_reg[32]; 193 uint32_t shadow_reg[7]; 194 uint16_t mailbox_reg[32]; 195 uint32_t xseq_gp_reg[128]; 196 uint32_t xseq_0_reg[16]; 197 uint32_t xseq_1_reg[16]; 198 uint32_t rseq_gp_reg[128]; 199 uint32_t rseq_0_reg[16]; 200 uint32_t rseq_1_reg[16]; 201 uint32_t rseq_2_reg[16]; 202 uint32_t cmd_dma_reg[16]; 203 uint32_t req0_dma_reg[15]; 204 uint32_t resp0_dma_reg[15]; 205 uint32_t req1_dma_reg[15]; 206 uint32_t xmt0_dma_reg[32]; 207 uint32_t xmt1_dma_reg[32]; 208 uint32_t xmt2_dma_reg[32]; 209 uint32_t xmt3_dma_reg[32]; 210 uint32_t xmt4_dma_reg[32]; 211 uint32_t xmt_data_dma_reg[16]; 212 uint32_t rcvt0_data_dma_reg[32]; 213 uint32_t rcvt1_data_dma_reg[32]; 214 uint32_t risc_gp_reg[128]; 215 uint32_t lmc_reg[112]; 216 uint32_t fpm_hdw_reg[192]; 217 uint32_t fb_hdw_reg[176]; 218 uint32_t code_ram[0x2000]; 219 uint32_t ext_mem[1]; 220 }; 221 222 struct qla25xx_fw_dump { 223 uint32_t host_status; 224 uint32_t host_risc_reg[32]; 225 uint32_t pcie_regs[4]; 226 uint32_t host_reg[32]; 227 uint32_t shadow_reg[11]; 228 uint32_t risc_io_reg; 229 uint16_t mailbox_reg[32]; 230 uint32_t xseq_gp_reg[128]; 231 uint32_t xseq_0_reg[48]; 232 uint32_t xseq_1_reg[16]; 233 uint32_t rseq_gp_reg[128]; 234 uint32_t rseq_0_reg[32]; 235 uint32_t rseq_1_reg[16]; 236 uint32_t rseq_2_reg[16]; 237 uint32_t aseq_gp_reg[128]; 238 uint32_t aseq_0_reg[32]; 239 uint32_t aseq_1_reg[16]; 240 uint32_t aseq_2_reg[16]; 241 uint32_t cmd_dma_reg[16]; 242 uint32_t req0_dma_reg[15]; 243 uint32_t resp0_dma_reg[15]; 244 uint32_t req1_dma_reg[15]; 245 uint32_t xmt0_dma_reg[32]; 246 uint32_t xmt1_dma_reg[32]; 247 uint32_t xmt2_dma_reg[32]; 248 uint32_t xmt3_dma_reg[32]; 249 uint32_t xmt4_dma_reg[32]; 250 uint32_t xmt_data_dma_reg[16]; 251 uint32_t rcvt0_data_dma_reg[32]; 252 uint32_t rcvt1_data_dma_reg[32]; 253 uint32_t risc_gp_reg[128]; 254 uint32_t lmc_reg[128]; 255 uint32_t fpm_hdw_reg[192]; 256 uint32_t fb_hdw_reg[192]; 257 uint32_t code_ram[0x2000]; 258 uint32_t ext_mem[1]; 259 }; 260 261 struct qla81xx_fw_dump { 262 uint32_t host_status; 263 uint32_t host_risc_reg[32]; 264 uint32_t pcie_regs[4]; 265 uint32_t host_reg[32]; 266 uint32_t shadow_reg[11]; 267 uint32_t risc_io_reg; 268 uint16_t mailbox_reg[32]; 269 uint32_t xseq_gp_reg[128]; 270 uint32_t xseq_0_reg[48]; 271 uint32_t xseq_1_reg[16]; 272 uint32_t rseq_gp_reg[128]; 273 uint32_t rseq_0_reg[32]; 274 uint32_t rseq_1_reg[16]; 275 uint32_t rseq_2_reg[16]; 276 uint32_t aseq_gp_reg[128]; 277 uint32_t aseq_0_reg[32]; 278 uint32_t aseq_1_reg[16]; 279 uint32_t aseq_2_reg[16]; 280 uint32_t cmd_dma_reg[16]; 281 uint32_t req0_dma_reg[15]; 282 uint32_t resp0_dma_reg[15]; 283 uint32_t req1_dma_reg[15]; 284 uint32_t xmt0_dma_reg[32]; 285 uint32_t xmt1_dma_reg[32]; 286 uint32_t xmt2_dma_reg[32]; 287 uint32_t xmt3_dma_reg[32]; 288 uint32_t xmt4_dma_reg[32]; 289 uint32_t xmt_data_dma_reg[16]; 290 uint32_t rcvt0_data_dma_reg[32]; 291 uint32_t rcvt1_data_dma_reg[32]; 292 uint32_t risc_gp_reg[128]; 293 uint32_t lmc_reg[128]; 294 uint32_t fpm_hdw_reg[224]; 295 uint32_t fb_hdw_reg[208]; 296 uint32_t code_ram[0x2000]; 297 uint32_t ext_mem[1]; 298 }; 299 300 #define EFT_NUM_BUFFERS 4 301 #define EFT_BYTES_PER_BUFFER 0x4000 302 #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) 303 304 #define FCE_NUM_BUFFERS 64 305 #define FCE_BYTES_PER_BUFFER 0x400 306 #define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS)) 307 #define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b)) 308 309 struct qla2xxx_fce_chain { 310 uint32_t type; 311 uint32_t chain_size; 312 313 uint32_t size; 314 uint32_t addr_l; 315 uint32_t addr_h; 316 uint32_t eregs[8]; 317 }; 318 319 struct qla2xxx_mq_chain { 320 uint32_t type; 321 uint32_t chain_size; 322 323 uint32_t count; 324 uint32_t qregs[4 * QLA_MQ_SIZE]; 325 }; 326 327 #define DUMP_CHAIN_VARIANT 0x80000000 328 #define DUMP_CHAIN_FCE 0x7FFFFAF0 329 #define DUMP_CHAIN_MQ 0x7FFFFAF1 330 #define DUMP_CHAIN_LAST 0x80000000 331 332 struct qla2xxx_fw_dump { 333 uint8_t signature[4]; 334 uint32_t version; 335 336 uint32_t fw_major_version; 337 uint32_t fw_minor_version; 338 uint32_t fw_subminor_version; 339 uint32_t fw_attributes; 340 341 uint32_t vendor; 342 uint32_t device; 343 uint32_t subsystem_vendor; 344 uint32_t subsystem_device; 345 346 uint32_t fixed_size; 347 uint32_t mem_size; 348 uint32_t req_q_size; 349 uint32_t rsp_q_size; 350 351 uint32_t eft_size; 352 uint32_t eft_addr_l; 353 uint32_t eft_addr_h; 354 355 uint32_t header_size; 356 357 union { 358 struct qla2100_fw_dump isp21; 359 struct qla2300_fw_dump isp23; 360 struct qla24xx_fw_dump isp24; 361 struct qla25xx_fw_dump isp25; 362 struct qla81xx_fw_dump isp81; 363 } isp; 364 }; 365