1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2011 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8 #include "qla_def.h" 9 10 /* 11 * Firmware Dump structure definition 12 */ 13 14 struct qla2300_fw_dump { 15 uint16_t hccr; 16 uint16_t pbiu_reg[8]; 17 uint16_t risc_host_reg[8]; 18 uint16_t mailbox_reg[32]; 19 uint16_t resp_dma_reg[32]; 20 uint16_t dma_reg[48]; 21 uint16_t risc_hdw_reg[16]; 22 uint16_t risc_gp0_reg[16]; 23 uint16_t risc_gp1_reg[16]; 24 uint16_t risc_gp2_reg[16]; 25 uint16_t risc_gp3_reg[16]; 26 uint16_t risc_gp4_reg[16]; 27 uint16_t risc_gp5_reg[16]; 28 uint16_t risc_gp6_reg[16]; 29 uint16_t risc_gp7_reg[16]; 30 uint16_t frame_buf_hdw_reg[64]; 31 uint16_t fpm_b0_reg[64]; 32 uint16_t fpm_b1_reg[64]; 33 uint16_t risc_ram[0xf800]; 34 uint16_t stack_ram[0x1000]; 35 uint16_t data_ram[1]; 36 }; 37 38 struct qla2100_fw_dump { 39 uint16_t hccr; 40 uint16_t pbiu_reg[8]; 41 uint16_t mailbox_reg[32]; 42 uint16_t dma_reg[48]; 43 uint16_t risc_hdw_reg[16]; 44 uint16_t risc_gp0_reg[16]; 45 uint16_t risc_gp1_reg[16]; 46 uint16_t risc_gp2_reg[16]; 47 uint16_t risc_gp3_reg[16]; 48 uint16_t risc_gp4_reg[16]; 49 uint16_t risc_gp5_reg[16]; 50 uint16_t risc_gp6_reg[16]; 51 uint16_t risc_gp7_reg[16]; 52 uint16_t frame_buf_hdw_reg[16]; 53 uint16_t fpm_b0_reg[64]; 54 uint16_t fpm_b1_reg[64]; 55 uint16_t risc_ram[0xf000]; 56 }; 57 58 struct qla24xx_fw_dump { 59 uint32_t host_status; 60 uint32_t host_reg[32]; 61 uint32_t shadow_reg[7]; 62 uint16_t mailbox_reg[32]; 63 uint32_t xseq_gp_reg[128]; 64 uint32_t xseq_0_reg[16]; 65 uint32_t xseq_1_reg[16]; 66 uint32_t rseq_gp_reg[128]; 67 uint32_t rseq_0_reg[16]; 68 uint32_t rseq_1_reg[16]; 69 uint32_t rseq_2_reg[16]; 70 uint32_t cmd_dma_reg[16]; 71 uint32_t req0_dma_reg[15]; 72 uint32_t resp0_dma_reg[15]; 73 uint32_t req1_dma_reg[15]; 74 uint32_t xmt0_dma_reg[32]; 75 uint32_t xmt1_dma_reg[32]; 76 uint32_t xmt2_dma_reg[32]; 77 uint32_t xmt3_dma_reg[32]; 78 uint32_t xmt4_dma_reg[32]; 79 uint32_t xmt_data_dma_reg[16]; 80 uint32_t rcvt0_data_dma_reg[32]; 81 uint32_t rcvt1_data_dma_reg[32]; 82 uint32_t risc_gp_reg[128]; 83 uint32_t lmc_reg[112]; 84 uint32_t fpm_hdw_reg[192]; 85 uint32_t fb_hdw_reg[176]; 86 uint32_t code_ram[0x2000]; 87 uint32_t ext_mem[1]; 88 }; 89 90 struct qla25xx_fw_dump { 91 uint32_t host_status; 92 uint32_t host_risc_reg[32]; 93 uint32_t pcie_regs[4]; 94 uint32_t host_reg[32]; 95 uint32_t shadow_reg[11]; 96 uint32_t risc_io_reg; 97 uint16_t mailbox_reg[32]; 98 uint32_t xseq_gp_reg[128]; 99 uint32_t xseq_0_reg[48]; 100 uint32_t xseq_1_reg[16]; 101 uint32_t rseq_gp_reg[128]; 102 uint32_t rseq_0_reg[32]; 103 uint32_t rseq_1_reg[16]; 104 uint32_t rseq_2_reg[16]; 105 uint32_t aseq_gp_reg[128]; 106 uint32_t aseq_0_reg[32]; 107 uint32_t aseq_1_reg[16]; 108 uint32_t aseq_2_reg[16]; 109 uint32_t cmd_dma_reg[16]; 110 uint32_t req0_dma_reg[15]; 111 uint32_t resp0_dma_reg[15]; 112 uint32_t req1_dma_reg[15]; 113 uint32_t xmt0_dma_reg[32]; 114 uint32_t xmt1_dma_reg[32]; 115 uint32_t xmt2_dma_reg[32]; 116 uint32_t xmt3_dma_reg[32]; 117 uint32_t xmt4_dma_reg[32]; 118 uint32_t xmt_data_dma_reg[16]; 119 uint32_t rcvt0_data_dma_reg[32]; 120 uint32_t rcvt1_data_dma_reg[32]; 121 uint32_t risc_gp_reg[128]; 122 uint32_t lmc_reg[128]; 123 uint32_t fpm_hdw_reg[192]; 124 uint32_t fb_hdw_reg[192]; 125 uint32_t code_ram[0x2000]; 126 uint32_t ext_mem[1]; 127 }; 128 129 struct qla81xx_fw_dump { 130 uint32_t host_status; 131 uint32_t host_risc_reg[32]; 132 uint32_t pcie_regs[4]; 133 uint32_t host_reg[32]; 134 uint32_t shadow_reg[11]; 135 uint32_t risc_io_reg; 136 uint16_t mailbox_reg[32]; 137 uint32_t xseq_gp_reg[128]; 138 uint32_t xseq_0_reg[48]; 139 uint32_t xseq_1_reg[16]; 140 uint32_t rseq_gp_reg[128]; 141 uint32_t rseq_0_reg[32]; 142 uint32_t rseq_1_reg[16]; 143 uint32_t rseq_2_reg[16]; 144 uint32_t aseq_gp_reg[128]; 145 uint32_t aseq_0_reg[32]; 146 uint32_t aseq_1_reg[16]; 147 uint32_t aseq_2_reg[16]; 148 uint32_t cmd_dma_reg[16]; 149 uint32_t req0_dma_reg[15]; 150 uint32_t resp0_dma_reg[15]; 151 uint32_t req1_dma_reg[15]; 152 uint32_t xmt0_dma_reg[32]; 153 uint32_t xmt1_dma_reg[32]; 154 uint32_t xmt2_dma_reg[32]; 155 uint32_t xmt3_dma_reg[32]; 156 uint32_t xmt4_dma_reg[32]; 157 uint32_t xmt_data_dma_reg[16]; 158 uint32_t rcvt0_data_dma_reg[32]; 159 uint32_t rcvt1_data_dma_reg[32]; 160 uint32_t risc_gp_reg[128]; 161 uint32_t lmc_reg[128]; 162 uint32_t fpm_hdw_reg[224]; 163 uint32_t fb_hdw_reg[208]; 164 uint32_t code_ram[0x2000]; 165 uint32_t ext_mem[1]; 166 }; 167 168 #define EFT_NUM_BUFFERS 4 169 #define EFT_BYTES_PER_BUFFER 0x4000 170 #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) 171 172 #define FCE_NUM_BUFFERS 64 173 #define FCE_BYTES_PER_BUFFER 0x400 174 #define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS)) 175 #define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b)) 176 177 struct qla2xxx_fce_chain { 178 uint32_t type; 179 uint32_t chain_size; 180 181 uint32_t size; 182 uint32_t addr_l; 183 uint32_t addr_h; 184 uint32_t eregs[8]; 185 }; 186 187 struct qla2xxx_mq_chain { 188 uint32_t type; 189 uint32_t chain_size; 190 191 uint32_t count; 192 uint32_t qregs[4 * QLA_MQ_SIZE]; 193 }; 194 195 #define DUMP_CHAIN_VARIANT 0x80000000 196 #define DUMP_CHAIN_FCE 0x7FFFFAF0 197 #define DUMP_CHAIN_MQ 0x7FFFFAF1 198 #define DUMP_CHAIN_LAST 0x80000000 199 200 struct qla2xxx_fw_dump { 201 uint8_t signature[4]; 202 uint32_t version; 203 204 uint32_t fw_major_version; 205 uint32_t fw_minor_version; 206 uint32_t fw_subminor_version; 207 uint32_t fw_attributes; 208 209 uint32_t vendor; 210 uint32_t device; 211 uint32_t subsystem_vendor; 212 uint32_t subsystem_device; 213 214 uint32_t fixed_size; 215 uint32_t mem_size; 216 uint32_t req_q_size; 217 uint32_t rsp_q_size; 218 219 uint32_t eft_size; 220 uint32_t eft_addr_l; 221 uint32_t eft_addr_h; 222 223 uint32_t header_size; 224 225 union { 226 struct qla2100_fw_dump isp21; 227 struct qla2300_fw_dump isp23; 228 struct qla24xx_fw_dump isp24; 229 struct qla25xx_fw_dump isp25; 230 struct qla81xx_fw_dump isp81; 231 } isp; 232 }; 233 234 #define QL_MSGHDR "qla2xxx" 235 236 #define ql_log_fatal 0 /* display fatal errors */ 237 #define ql_log_warn 1 /* display critical errors */ 238 #define ql_log_info 2 /* display all recovered errors */ 239 #define ql_log_all 3 /* This value is only used by ql_errlev. 240 * No messages will use this value. 241 * This should be always highest value 242 * as compared to other log levels. 243 */ 244 245 extern int ql_errlev; 246 247 void 248 ql_dbg(uint32_t, scsi_qla_host_t *vha, int32_t, char *, ...); 249 void 250 ql_dbg_pci(uint32_t, struct pci_dev *pdev, int32_t, char *, ...); 251 252 void 253 ql_log(uint32_t, scsi_qla_host_t *vha, int32_t, char *, ...); 254 void 255 ql_log_pci(uint32_t, struct pci_dev *pdev, int32_t, char *, ...); 256 257 /* Debug Levels */ 258 /* The 0x40000000 is the max value any debug level can have 259 * as ql2xextended_error_logging is of type signed int 260 */ 261 #define ql_dbg_init 0x40000000 /* Init Debug */ 262 #define ql_dbg_mbx 0x20000000 /* MBX Debug */ 263 #define ql_dbg_disc 0x10000000 /* Device Discovery Debug */ 264 #define ql_dbg_io 0x08000000 /* IO Tracing Debug */ 265 #define ql_dbg_dpc 0x04000000 /* DPC Thead Debug */ 266 #define ql_dbg_async 0x02000000 /* Async events Debug */ 267 #define ql_dbg_timer 0x01000000 /* Timer Debug */ 268 #define ql_dbg_user 0x00800000 /* User Space Interations Debug */ 269 #define ql_dbg_taskm 0x00400000 /* Task Management Debug */ 270 #define ql_dbg_aer 0x00200000 /* AER/EEH Debug */ 271 #define ql_dbg_multiq 0x00100000 /* MultiQ Debug */ 272 #define ql_dbg_p3p 0x00080000 /* P3P specific Debug */ 273 #define ql_dbg_vport 0x00040000 /* Virtual Port Debug */ 274 #define ql_dbg_buffer 0x00020000 /* For dumping the buffer/regs */ 275 #define ql_dbg_misc 0x00010000 /* For dumping everything that is not 276 * not covered by upper categories 277 */ 278 279 #define QL_DBG_BUF_LEN 512 280