1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8 #include "qla_def.h" 9 10 /* 11 * Firmware Dump structure definition 12 */ 13 14 struct qla2300_fw_dump { 15 __be16 hccr; 16 __be16 pbiu_reg[8]; 17 __be16 risc_host_reg[8]; 18 __be16 mailbox_reg[32]; 19 __be16 resp_dma_reg[32]; 20 __be16 dma_reg[48]; 21 __be16 risc_hdw_reg[16]; 22 __be16 risc_gp0_reg[16]; 23 __be16 risc_gp1_reg[16]; 24 __be16 risc_gp2_reg[16]; 25 __be16 risc_gp3_reg[16]; 26 __be16 risc_gp4_reg[16]; 27 __be16 risc_gp5_reg[16]; 28 __be16 risc_gp6_reg[16]; 29 __be16 risc_gp7_reg[16]; 30 __be16 frame_buf_hdw_reg[64]; 31 __be16 fpm_b0_reg[64]; 32 __be16 fpm_b1_reg[64]; 33 __be16 risc_ram[0xf800]; 34 __be16 stack_ram[0x1000]; 35 __be16 data_ram[1]; 36 }; 37 38 struct qla2100_fw_dump { 39 __be16 hccr; 40 __be16 pbiu_reg[8]; 41 __be16 mailbox_reg[32]; 42 __be16 dma_reg[48]; 43 __be16 risc_hdw_reg[16]; 44 __be16 risc_gp0_reg[16]; 45 __be16 risc_gp1_reg[16]; 46 __be16 risc_gp2_reg[16]; 47 __be16 risc_gp3_reg[16]; 48 __be16 risc_gp4_reg[16]; 49 __be16 risc_gp5_reg[16]; 50 __be16 risc_gp6_reg[16]; 51 __be16 risc_gp7_reg[16]; 52 __be16 frame_buf_hdw_reg[16]; 53 __be16 fpm_b0_reg[64]; 54 __be16 fpm_b1_reg[64]; 55 __be16 risc_ram[0xf000]; 56 u8 queue_dump[]; 57 }; 58 59 struct qla24xx_fw_dump { 60 __be32 host_status; 61 __be32 host_reg[32]; 62 __be32 shadow_reg[7]; 63 __be16 mailbox_reg[32]; 64 __be32 xseq_gp_reg[128]; 65 __be32 xseq_0_reg[16]; 66 __be32 xseq_1_reg[16]; 67 __be32 rseq_gp_reg[128]; 68 __be32 rseq_0_reg[16]; 69 __be32 rseq_1_reg[16]; 70 __be32 rseq_2_reg[16]; 71 __be32 cmd_dma_reg[16]; 72 __be32 req0_dma_reg[15]; 73 __be32 resp0_dma_reg[15]; 74 __be32 req1_dma_reg[15]; 75 __be32 xmt0_dma_reg[32]; 76 __be32 xmt1_dma_reg[32]; 77 __be32 xmt2_dma_reg[32]; 78 __be32 xmt3_dma_reg[32]; 79 __be32 xmt4_dma_reg[32]; 80 __be32 xmt_data_dma_reg[16]; 81 __be32 rcvt0_data_dma_reg[32]; 82 __be32 rcvt1_data_dma_reg[32]; 83 __be32 risc_gp_reg[128]; 84 __be32 lmc_reg[112]; 85 __be32 fpm_hdw_reg[192]; 86 __be32 fb_hdw_reg[176]; 87 __be32 code_ram[0x2000]; 88 __be32 ext_mem[1]; 89 }; 90 91 struct qla25xx_fw_dump { 92 __be32 host_status; 93 __be32 host_risc_reg[32]; 94 __be32 pcie_regs[4]; 95 __be32 host_reg[32]; 96 __be32 shadow_reg[11]; 97 __be32 risc_io_reg; 98 __be16 mailbox_reg[32]; 99 __be32 xseq_gp_reg[128]; 100 __be32 xseq_0_reg[48]; 101 __be32 xseq_1_reg[16]; 102 __be32 rseq_gp_reg[128]; 103 __be32 rseq_0_reg[32]; 104 __be32 rseq_1_reg[16]; 105 __be32 rseq_2_reg[16]; 106 __be32 aseq_gp_reg[128]; 107 __be32 aseq_0_reg[32]; 108 __be32 aseq_1_reg[16]; 109 __be32 aseq_2_reg[16]; 110 __be32 cmd_dma_reg[16]; 111 __be32 req0_dma_reg[15]; 112 __be32 resp0_dma_reg[15]; 113 __be32 req1_dma_reg[15]; 114 __be32 xmt0_dma_reg[32]; 115 __be32 xmt1_dma_reg[32]; 116 __be32 xmt2_dma_reg[32]; 117 __be32 xmt3_dma_reg[32]; 118 __be32 xmt4_dma_reg[32]; 119 __be32 xmt_data_dma_reg[16]; 120 __be32 rcvt0_data_dma_reg[32]; 121 __be32 rcvt1_data_dma_reg[32]; 122 __be32 risc_gp_reg[128]; 123 __be32 lmc_reg[128]; 124 __be32 fpm_hdw_reg[192]; 125 __be32 fb_hdw_reg[192]; 126 __be32 code_ram[0x2000]; 127 __be32 ext_mem[1]; 128 }; 129 130 struct qla81xx_fw_dump { 131 __be32 host_status; 132 __be32 host_risc_reg[32]; 133 __be32 pcie_regs[4]; 134 __be32 host_reg[32]; 135 __be32 shadow_reg[11]; 136 __be32 risc_io_reg; 137 __be16 mailbox_reg[32]; 138 __be32 xseq_gp_reg[128]; 139 __be32 xseq_0_reg[48]; 140 __be32 xseq_1_reg[16]; 141 __be32 rseq_gp_reg[128]; 142 __be32 rseq_0_reg[32]; 143 __be32 rseq_1_reg[16]; 144 __be32 rseq_2_reg[16]; 145 __be32 aseq_gp_reg[128]; 146 __be32 aseq_0_reg[32]; 147 __be32 aseq_1_reg[16]; 148 __be32 aseq_2_reg[16]; 149 __be32 cmd_dma_reg[16]; 150 __be32 req0_dma_reg[15]; 151 __be32 resp0_dma_reg[15]; 152 __be32 req1_dma_reg[15]; 153 __be32 xmt0_dma_reg[32]; 154 __be32 xmt1_dma_reg[32]; 155 __be32 xmt2_dma_reg[32]; 156 __be32 xmt3_dma_reg[32]; 157 __be32 xmt4_dma_reg[32]; 158 __be32 xmt_data_dma_reg[16]; 159 __be32 rcvt0_data_dma_reg[32]; 160 __be32 rcvt1_data_dma_reg[32]; 161 __be32 risc_gp_reg[128]; 162 __be32 lmc_reg[128]; 163 __be32 fpm_hdw_reg[224]; 164 __be32 fb_hdw_reg[208]; 165 __be32 code_ram[0x2000]; 166 __be32 ext_mem[1]; 167 }; 168 169 struct qla83xx_fw_dump { 170 __be32 host_status; 171 __be32 host_risc_reg[48]; 172 __be32 pcie_regs[4]; 173 __be32 host_reg[32]; 174 __be32 shadow_reg[11]; 175 __be32 risc_io_reg; 176 __be16 mailbox_reg[32]; 177 __be32 xseq_gp_reg[256]; 178 __be32 xseq_0_reg[48]; 179 __be32 xseq_1_reg[16]; 180 __be32 xseq_2_reg[16]; 181 __be32 rseq_gp_reg[256]; 182 __be32 rseq_0_reg[32]; 183 __be32 rseq_1_reg[16]; 184 __be32 rseq_2_reg[16]; 185 __be32 rseq_3_reg[16]; 186 __be32 aseq_gp_reg[256]; 187 __be32 aseq_0_reg[32]; 188 __be32 aseq_1_reg[16]; 189 __be32 aseq_2_reg[16]; 190 __be32 aseq_3_reg[16]; 191 __be32 cmd_dma_reg[64]; 192 __be32 req0_dma_reg[15]; 193 __be32 resp0_dma_reg[15]; 194 __be32 req1_dma_reg[15]; 195 __be32 xmt0_dma_reg[32]; 196 __be32 xmt1_dma_reg[32]; 197 __be32 xmt2_dma_reg[32]; 198 __be32 xmt3_dma_reg[32]; 199 __be32 xmt4_dma_reg[32]; 200 __be32 xmt_data_dma_reg[16]; 201 __be32 rcvt0_data_dma_reg[32]; 202 __be32 rcvt1_data_dma_reg[32]; 203 __be32 risc_gp_reg[128]; 204 __be32 lmc_reg[128]; 205 __be32 fpm_hdw_reg[256]; 206 __be32 rq0_array_reg[256]; 207 __be32 rq1_array_reg[256]; 208 __be32 rp0_array_reg[256]; 209 __be32 rp1_array_reg[256]; 210 __be32 queue_control_reg[16]; 211 __be32 fb_hdw_reg[432]; 212 __be32 at0_array_reg[128]; 213 __be32 code_ram[0x2400]; 214 __be32 ext_mem[1]; 215 }; 216 217 #define EFT_NUM_BUFFERS 4 218 #define EFT_BYTES_PER_BUFFER 0x4000 219 #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) 220 221 #define FCE_NUM_BUFFERS 64 222 #define FCE_BYTES_PER_BUFFER 0x400 223 #define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS)) 224 #define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b)) 225 226 struct qla2xxx_fce_chain { 227 __be32 type; 228 __be32 chain_size; 229 230 __be32 size; 231 __be32 addr_l; 232 __be32 addr_h; 233 __be32 eregs[8]; 234 }; 235 236 /* used by exchange off load and extended login offload */ 237 struct qla2xxx_offld_chain { 238 __be32 type; 239 __be32 chain_size; 240 241 __be32 size; 242 __be32 reserved; 243 __be64 addr; 244 }; 245 246 struct qla2xxx_mq_chain { 247 __be32 type; 248 __be32 chain_size; 249 250 __be32 count; 251 __be32 qregs[4 * QLA_MQ_SIZE]; 252 }; 253 254 struct qla2xxx_mqueue_header { 255 __be32 queue; 256 #define TYPE_REQUEST_QUEUE 0x1 257 #define TYPE_RESPONSE_QUEUE 0x2 258 #define TYPE_ATIO_QUEUE 0x3 259 __be32 number; 260 __be32 size; 261 }; 262 263 struct qla2xxx_mqueue_chain { 264 __be32 type; 265 __be32 chain_size; 266 }; 267 268 #define DUMP_CHAIN_VARIANT 0x80000000 269 #define DUMP_CHAIN_FCE 0x7FFFFAF0 270 #define DUMP_CHAIN_MQ 0x7FFFFAF1 271 #define DUMP_CHAIN_QUEUE 0x7FFFFAF2 272 #define DUMP_CHAIN_EXLOGIN 0x7FFFFAF3 273 #define DUMP_CHAIN_EXCHG 0x7FFFFAF4 274 #define DUMP_CHAIN_LAST 0x80000000 275 276 struct qla2xxx_fw_dump { 277 uint8_t signature[4]; 278 __be32 version; 279 280 __be32 fw_major_version; 281 __be32 fw_minor_version; 282 __be32 fw_subminor_version; 283 __be32 fw_attributes; 284 285 __be32 vendor; 286 __be32 device; 287 __be32 subsystem_vendor; 288 __be32 subsystem_device; 289 290 __be32 fixed_size; 291 __be32 mem_size; 292 __be32 req_q_size; 293 __be32 rsp_q_size; 294 295 __be32 eft_size; 296 __be32 eft_addr_l; 297 __be32 eft_addr_h; 298 299 __be32 header_size; 300 301 union { 302 struct qla2100_fw_dump isp21; 303 struct qla2300_fw_dump isp23; 304 struct qla24xx_fw_dump isp24; 305 struct qla25xx_fw_dump isp25; 306 struct qla81xx_fw_dump isp81; 307 struct qla83xx_fw_dump isp83; 308 } isp; 309 }; 310 311 #define QL_MSGHDR "qla2xxx" 312 #define QL_DBG_DEFAULT1_MASK 0x1e400000 313 314 #define ql_log_fatal 0 /* display fatal errors */ 315 #define ql_log_warn 1 /* display critical errors */ 316 #define ql_log_info 2 /* display all recovered errors */ 317 #define ql_log_all 3 /* This value is only used by ql_errlev. 318 * No messages will use this value. 319 * This should be always highest value 320 * as compared to other log levels. 321 */ 322 323 extern uint ql_errlev; 324 325 void __attribute__((format (printf, 4, 5))) 326 ql_dbg(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...); 327 void __attribute__((format (printf, 4, 5))) 328 ql_dbg_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...); 329 void __attribute__((format (printf, 4, 5))) 330 ql_dbg_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...); 331 332 333 void __attribute__((format (printf, 4, 5))) 334 ql_log(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...); 335 void __attribute__((format (printf, 4, 5))) 336 ql_log_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...); 337 338 void __attribute__((format (printf, 4, 5))) 339 ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...); 340 341 /* Debug Levels */ 342 /* The 0x40000000 is the max value any debug level can have 343 * as ql2xextended_error_logging is of type signed int 344 */ 345 #define ql_dbg_init 0x40000000 /* Init Debug */ 346 #define ql_dbg_mbx 0x20000000 /* MBX Debug */ 347 #define ql_dbg_disc 0x10000000 /* Device Discovery Debug */ 348 #define ql_dbg_io 0x08000000 /* IO Tracing Debug */ 349 #define ql_dbg_dpc 0x04000000 /* DPC Thead Debug */ 350 #define ql_dbg_async 0x02000000 /* Async events Debug */ 351 #define ql_dbg_timer 0x01000000 /* Timer Debug */ 352 #define ql_dbg_user 0x00800000 /* User Space Interations Debug */ 353 #define ql_dbg_taskm 0x00400000 /* Task Management Debug */ 354 #define ql_dbg_aer 0x00200000 /* AER/EEH Debug */ 355 #define ql_dbg_multiq 0x00100000 /* MultiQ Debug */ 356 #define ql_dbg_p3p 0x00080000 /* P3P specific Debug */ 357 #define ql_dbg_vport 0x00040000 /* Virtual Port Debug */ 358 #define ql_dbg_buffer 0x00020000 /* For dumping the buffer/regs */ 359 #define ql_dbg_misc 0x00010000 /* For dumping everything that is not 360 * not covered by upper categories 361 */ 362 #define ql_dbg_verbose 0x00008000 /* More verbosity for each level 363 * This is to be used with other levels where 364 * more verbosity is required. It might not 365 * be applicable to all the levels. 366 */ 367 #define ql_dbg_tgt 0x00004000 /* Target mode */ 368 #define ql_dbg_tgt_mgt 0x00002000 /* Target mode management */ 369 #define ql_dbg_tgt_tmr 0x00001000 /* Target mode task management */ 370 #define ql_dbg_tgt_dif 0x00000800 /* Target mode dif */ 371 372 extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *, 373 uint32_t, void **); 374 extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, __be32 *, 375 uint32_t, void **); 376 extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *, 377 struct qla_hw_data *); 378 extern int qla24xx_soft_reset(struct qla_hw_data *); 379 380 static inline int 381 ql_mask_match(uint level) 382 { 383 if (ql2xextended_error_logging == 1) 384 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 385 386 return (level & ql2xextended_error_logging) == level; 387 } 388