1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8 #include "qla_def.h" 9 10 /* 11 * Firmware Dump structure definition 12 */ 13 14 struct qla2300_fw_dump { 15 uint16_t hccr; 16 uint16_t pbiu_reg[8]; 17 uint16_t risc_host_reg[8]; 18 uint16_t mailbox_reg[32]; 19 uint16_t resp_dma_reg[32]; 20 uint16_t dma_reg[48]; 21 uint16_t risc_hdw_reg[16]; 22 uint16_t risc_gp0_reg[16]; 23 uint16_t risc_gp1_reg[16]; 24 uint16_t risc_gp2_reg[16]; 25 uint16_t risc_gp3_reg[16]; 26 uint16_t risc_gp4_reg[16]; 27 uint16_t risc_gp5_reg[16]; 28 uint16_t risc_gp6_reg[16]; 29 uint16_t risc_gp7_reg[16]; 30 uint16_t frame_buf_hdw_reg[64]; 31 uint16_t fpm_b0_reg[64]; 32 uint16_t fpm_b1_reg[64]; 33 uint16_t risc_ram[0xf800]; 34 uint16_t stack_ram[0x1000]; 35 uint16_t data_ram[1]; 36 }; 37 38 struct qla2100_fw_dump { 39 uint16_t hccr; 40 uint16_t pbiu_reg[8]; 41 uint16_t mailbox_reg[32]; 42 uint16_t dma_reg[48]; 43 uint16_t risc_hdw_reg[16]; 44 uint16_t risc_gp0_reg[16]; 45 uint16_t risc_gp1_reg[16]; 46 uint16_t risc_gp2_reg[16]; 47 uint16_t risc_gp3_reg[16]; 48 uint16_t risc_gp4_reg[16]; 49 uint16_t risc_gp5_reg[16]; 50 uint16_t risc_gp6_reg[16]; 51 uint16_t risc_gp7_reg[16]; 52 uint16_t frame_buf_hdw_reg[16]; 53 uint16_t fpm_b0_reg[64]; 54 uint16_t fpm_b1_reg[64]; 55 uint16_t risc_ram[0xf000]; 56 }; 57 58 struct qla24xx_fw_dump { 59 uint32_t host_status; 60 uint32_t host_reg[32]; 61 uint32_t shadow_reg[7]; 62 uint16_t mailbox_reg[32]; 63 uint32_t xseq_gp_reg[128]; 64 uint32_t xseq_0_reg[16]; 65 uint32_t xseq_1_reg[16]; 66 uint32_t rseq_gp_reg[128]; 67 uint32_t rseq_0_reg[16]; 68 uint32_t rseq_1_reg[16]; 69 uint32_t rseq_2_reg[16]; 70 uint32_t cmd_dma_reg[16]; 71 uint32_t req0_dma_reg[15]; 72 uint32_t resp0_dma_reg[15]; 73 uint32_t req1_dma_reg[15]; 74 uint32_t xmt0_dma_reg[32]; 75 uint32_t xmt1_dma_reg[32]; 76 uint32_t xmt2_dma_reg[32]; 77 uint32_t xmt3_dma_reg[32]; 78 uint32_t xmt4_dma_reg[32]; 79 uint32_t xmt_data_dma_reg[16]; 80 uint32_t rcvt0_data_dma_reg[32]; 81 uint32_t rcvt1_data_dma_reg[32]; 82 uint32_t risc_gp_reg[128]; 83 uint32_t lmc_reg[112]; 84 uint32_t fpm_hdw_reg[192]; 85 uint32_t fb_hdw_reg[176]; 86 uint32_t code_ram[0x2000]; 87 uint32_t ext_mem[1]; 88 }; 89 90 struct qla25xx_fw_dump { 91 uint32_t host_status; 92 uint32_t host_risc_reg[32]; 93 uint32_t pcie_regs[4]; 94 uint32_t host_reg[32]; 95 uint32_t shadow_reg[11]; 96 uint32_t risc_io_reg; 97 uint16_t mailbox_reg[32]; 98 uint32_t xseq_gp_reg[128]; 99 uint32_t xseq_0_reg[48]; 100 uint32_t xseq_1_reg[16]; 101 uint32_t rseq_gp_reg[128]; 102 uint32_t rseq_0_reg[32]; 103 uint32_t rseq_1_reg[16]; 104 uint32_t rseq_2_reg[16]; 105 uint32_t aseq_gp_reg[128]; 106 uint32_t aseq_0_reg[32]; 107 uint32_t aseq_1_reg[16]; 108 uint32_t aseq_2_reg[16]; 109 uint32_t cmd_dma_reg[16]; 110 uint32_t req0_dma_reg[15]; 111 uint32_t resp0_dma_reg[15]; 112 uint32_t req1_dma_reg[15]; 113 uint32_t xmt0_dma_reg[32]; 114 uint32_t xmt1_dma_reg[32]; 115 uint32_t xmt2_dma_reg[32]; 116 uint32_t xmt3_dma_reg[32]; 117 uint32_t xmt4_dma_reg[32]; 118 uint32_t xmt_data_dma_reg[16]; 119 uint32_t rcvt0_data_dma_reg[32]; 120 uint32_t rcvt1_data_dma_reg[32]; 121 uint32_t risc_gp_reg[128]; 122 uint32_t lmc_reg[128]; 123 uint32_t fpm_hdw_reg[192]; 124 uint32_t fb_hdw_reg[192]; 125 uint32_t code_ram[0x2000]; 126 uint32_t ext_mem[1]; 127 }; 128 129 struct qla81xx_fw_dump { 130 uint32_t host_status; 131 uint32_t host_risc_reg[32]; 132 uint32_t pcie_regs[4]; 133 uint32_t host_reg[32]; 134 uint32_t shadow_reg[11]; 135 uint32_t risc_io_reg; 136 uint16_t mailbox_reg[32]; 137 uint32_t xseq_gp_reg[128]; 138 uint32_t xseq_0_reg[48]; 139 uint32_t xseq_1_reg[16]; 140 uint32_t rseq_gp_reg[128]; 141 uint32_t rseq_0_reg[32]; 142 uint32_t rseq_1_reg[16]; 143 uint32_t rseq_2_reg[16]; 144 uint32_t aseq_gp_reg[128]; 145 uint32_t aseq_0_reg[32]; 146 uint32_t aseq_1_reg[16]; 147 uint32_t aseq_2_reg[16]; 148 uint32_t cmd_dma_reg[16]; 149 uint32_t req0_dma_reg[15]; 150 uint32_t resp0_dma_reg[15]; 151 uint32_t req1_dma_reg[15]; 152 uint32_t xmt0_dma_reg[32]; 153 uint32_t xmt1_dma_reg[32]; 154 uint32_t xmt2_dma_reg[32]; 155 uint32_t xmt3_dma_reg[32]; 156 uint32_t xmt4_dma_reg[32]; 157 uint32_t xmt_data_dma_reg[16]; 158 uint32_t rcvt0_data_dma_reg[32]; 159 uint32_t rcvt1_data_dma_reg[32]; 160 uint32_t risc_gp_reg[128]; 161 uint32_t lmc_reg[128]; 162 uint32_t fpm_hdw_reg[224]; 163 uint32_t fb_hdw_reg[208]; 164 uint32_t code_ram[0x2000]; 165 uint32_t ext_mem[1]; 166 }; 167 168 struct qla83xx_fw_dump { 169 uint32_t host_status; 170 uint32_t host_risc_reg[48]; 171 uint32_t pcie_regs[4]; 172 uint32_t host_reg[32]; 173 uint32_t shadow_reg[11]; 174 uint32_t risc_io_reg; 175 uint16_t mailbox_reg[32]; 176 uint32_t xseq_gp_reg[256]; 177 uint32_t xseq_0_reg[48]; 178 uint32_t xseq_1_reg[16]; 179 uint32_t xseq_2_reg[16]; 180 uint32_t rseq_gp_reg[256]; 181 uint32_t rseq_0_reg[32]; 182 uint32_t rseq_1_reg[16]; 183 uint32_t rseq_2_reg[16]; 184 uint32_t rseq_3_reg[16]; 185 uint32_t aseq_gp_reg[256]; 186 uint32_t aseq_0_reg[32]; 187 uint32_t aseq_1_reg[16]; 188 uint32_t aseq_2_reg[16]; 189 uint32_t aseq_3_reg[16]; 190 uint32_t cmd_dma_reg[64]; 191 uint32_t req0_dma_reg[15]; 192 uint32_t resp0_dma_reg[15]; 193 uint32_t req1_dma_reg[15]; 194 uint32_t xmt0_dma_reg[32]; 195 uint32_t xmt1_dma_reg[32]; 196 uint32_t xmt2_dma_reg[32]; 197 uint32_t xmt3_dma_reg[32]; 198 uint32_t xmt4_dma_reg[32]; 199 uint32_t xmt_data_dma_reg[16]; 200 uint32_t rcvt0_data_dma_reg[32]; 201 uint32_t rcvt1_data_dma_reg[32]; 202 uint32_t risc_gp_reg[128]; 203 uint32_t lmc_reg[128]; 204 uint32_t fpm_hdw_reg[256]; 205 uint32_t rq0_array_reg[256]; 206 uint32_t rq1_array_reg[256]; 207 uint32_t rp0_array_reg[256]; 208 uint32_t rp1_array_reg[256]; 209 uint32_t queue_control_reg[16]; 210 uint32_t fb_hdw_reg[432]; 211 uint32_t at0_array_reg[128]; 212 uint32_t code_ram[0x2400]; 213 uint32_t ext_mem[1]; 214 }; 215 216 #define EFT_NUM_BUFFERS 4 217 #define EFT_BYTES_PER_BUFFER 0x4000 218 #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) 219 220 #define FCE_NUM_BUFFERS 64 221 #define FCE_BYTES_PER_BUFFER 0x400 222 #define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS)) 223 #define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b)) 224 225 struct qla2xxx_fce_chain { 226 uint32_t type; 227 uint32_t chain_size; 228 229 uint32_t size; 230 uint32_t addr_l; 231 uint32_t addr_h; 232 uint32_t eregs[8]; 233 }; 234 235 /* used by exchange off load and extended login offload */ 236 struct qla2xxx_offld_chain { 237 uint32_t type; 238 uint32_t chain_size; 239 240 uint32_t size; 241 u64 addr; 242 }; 243 244 struct qla2xxx_mq_chain { 245 uint32_t type; 246 uint32_t chain_size; 247 248 uint32_t count; 249 uint32_t qregs[4 * QLA_MQ_SIZE]; 250 }; 251 252 struct qla2xxx_mqueue_header { 253 uint32_t queue; 254 #define TYPE_REQUEST_QUEUE 0x1 255 #define TYPE_RESPONSE_QUEUE 0x2 256 #define TYPE_ATIO_QUEUE 0x3 257 uint32_t number; 258 uint32_t size; 259 }; 260 261 struct qla2xxx_mqueue_chain { 262 uint32_t type; 263 uint32_t chain_size; 264 }; 265 266 #define DUMP_CHAIN_VARIANT 0x80000000 267 #define DUMP_CHAIN_FCE 0x7FFFFAF0 268 #define DUMP_CHAIN_MQ 0x7FFFFAF1 269 #define DUMP_CHAIN_QUEUE 0x7FFFFAF2 270 #define DUMP_CHAIN_EXLOGIN 0x7FFFFAF3 271 #define DUMP_CHAIN_EXCHG 0x7FFFFAF4 272 #define DUMP_CHAIN_LAST 0x80000000 273 274 struct qla2xxx_fw_dump { 275 uint8_t signature[4]; 276 uint32_t version; 277 278 uint32_t fw_major_version; 279 uint32_t fw_minor_version; 280 uint32_t fw_subminor_version; 281 uint32_t fw_attributes; 282 283 uint32_t vendor; 284 uint32_t device; 285 uint32_t subsystem_vendor; 286 uint32_t subsystem_device; 287 288 uint32_t fixed_size; 289 uint32_t mem_size; 290 uint32_t req_q_size; 291 uint32_t rsp_q_size; 292 293 uint32_t eft_size; 294 uint32_t eft_addr_l; 295 uint32_t eft_addr_h; 296 297 uint32_t header_size; 298 299 union { 300 struct qla2100_fw_dump isp21; 301 struct qla2300_fw_dump isp23; 302 struct qla24xx_fw_dump isp24; 303 struct qla25xx_fw_dump isp25; 304 struct qla81xx_fw_dump isp81; 305 struct qla83xx_fw_dump isp83; 306 } isp; 307 }; 308 309 #define QL_MSGHDR "qla2xxx" 310 #define QL_DBG_DEFAULT1_MASK 0x1e400000 311 312 #define ql_log_fatal 0 /* display fatal errors */ 313 #define ql_log_warn 1 /* display critical errors */ 314 #define ql_log_info 2 /* display all recovered errors */ 315 #define ql_log_all 3 /* This value is only used by ql_errlev. 316 * No messages will use this value. 317 * This should be always highest value 318 * as compared to other log levels. 319 */ 320 321 extern uint ql_errlev; 322 323 void __attribute__((format (printf, 4, 5))) 324 ql_dbg(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...); 325 void __attribute__((format (printf, 4, 5))) 326 ql_dbg_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...); 327 void __attribute__((format (printf, 4, 5))) 328 ql_dbg_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...); 329 330 331 void __attribute__((format (printf, 4, 5))) 332 ql_log(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...); 333 void __attribute__((format (printf, 4, 5))) 334 ql_log_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...); 335 336 void __attribute__((format (printf, 4, 5))) 337 ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...); 338 339 /* Debug Levels */ 340 /* The 0x40000000 is the max value any debug level can have 341 * as ql2xextended_error_logging is of type signed int 342 */ 343 #define ql_dbg_init 0x40000000 /* Init Debug */ 344 #define ql_dbg_mbx 0x20000000 /* MBX Debug */ 345 #define ql_dbg_disc 0x10000000 /* Device Discovery Debug */ 346 #define ql_dbg_io 0x08000000 /* IO Tracing Debug */ 347 #define ql_dbg_dpc 0x04000000 /* DPC Thead Debug */ 348 #define ql_dbg_async 0x02000000 /* Async events Debug */ 349 #define ql_dbg_timer 0x01000000 /* Timer Debug */ 350 #define ql_dbg_user 0x00800000 /* User Space Interations Debug */ 351 #define ql_dbg_taskm 0x00400000 /* Task Management Debug */ 352 #define ql_dbg_aer 0x00200000 /* AER/EEH Debug */ 353 #define ql_dbg_multiq 0x00100000 /* MultiQ Debug */ 354 #define ql_dbg_p3p 0x00080000 /* P3P specific Debug */ 355 #define ql_dbg_vport 0x00040000 /* Virtual Port Debug */ 356 #define ql_dbg_buffer 0x00020000 /* For dumping the buffer/regs */ 357 #define ql_dbg_misc 0x00010000 /* For dumping everything that is not 358 * not covered by upper categories 359 */ 360 #define ql_dbg_verbose 0x00008000 /* More verbosity for each level 361 * This is to be used with other levels where 362 * more verbosity is required. It might not 363 * be applicable to all the levels. 364 */ 365 #define ql_dbg_tgt 0x00004000 /* Target mode */ 366 #define ql_dbg_tgt_mgt 0x00002000 /* Target mode management */ 367 #define ql_dbg_tgt_tmr 0x00001000 /* Target mode task management */ 368 #define ql_dbg_tgt_dif 0x00000800 /* Target mode dif */ 369 370 extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *, 371 uint32_t, void **); 372 extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *, 373 uint32_t, void **); 374 extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *, 375 struct qla_hw_data *); 376 extern int qla24xx_soft_reset(struct qla_hw_data *); 377