1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2008 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/delay.h> 10 11 static inline void 12 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) 13 { 14 fw_dump->fw_major_version = htonl(ha->fw_major_version); 15 fw_dump->fw_minor_version = htonl(ha->fw_minor_version); 16 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); 17 fw_dump->fw_attributes = htonl(ha->fw_attributes); 18 19 fw_dump->vendor = htonl(ha->pdev->vendor); 20 fw_dump->device = htonl(ha->pdev->device); 21 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); 22 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); 23 } 24 25 static inline void * 26 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) 27 { 28 struct req_que *req = ha->req_q_map[0]; 29 struct rsp_que *rsp = ha->rsp_q_map[0]; 30 /* Request queue. */ 31 memcpy(ptr, req->ring, req->length * 32 sizeof(request_t)); 33 34 /* Response queue. */ 35 ptr += req->length * sizeof(request_t); 36 memcpy(ptr, rsp->ring, rsp->length * 37 sizeof(response_t)); 38 39 return ptr + (rsp->length * sizeof(response_t)); 40 } 41 42 static int 43 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, 44 uint32_t ram_dwords, void **nxt) 45 { 46 int rval; 47 uint32_t cnt, stat, timer, dwords, idx; 48 uint16_t mb0; 49 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 50 dma_addr_t dump_dma = ha->gid_list_dma; 51 uint32_t *dump = (uint32_t *)ha->gid_list; 52 53 rval = QLA_SUCCESS; 54 mb0 = 0; 55 56 WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); 57 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 58 59 dwords = GID_LIST_SIZE / 4; 60 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; 61 cnt += dwords, addr += dwords) { 62 if (cnt + dwords > ram_dwords) 63 dwords = ram_dwords - cnt; 64 65 WRT_REG_WORD(®->mailbox1, LSW(addr)); 66 WRT_REG_WORD(®->mailbox8, MSW(addr)); 67 68 WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); 69 WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); 70 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); 71 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); 72 73 WRT_REG_WORD(®->mailbox4, MSW(dwords)); 74 WRT_REG_WORD(®->mailbox5, LSW(dwords)); 75 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 76 77 for (timer = 6000000; timer; timer--) { 78 /* Check for pending interrupts. */ 79 stat = RD_REG_DWORD(®->host_status); 80 if (stat & HSRX_RISC_INT) { 81 stat &= 0xff; 82 83 if (stat == 0x1 || stat == 0x2 || 84 stat == 0x10 || stat == 0x11) { 85 set_bit(MBX_INTERRUPT, 86 &ha->mbx_cmd_flags); 87 88 mb0 = RD_REG_WORD(®->mailbox0); 89 90 WRT_REG_DWORD(®->hccr, 91 HCCRX_CLR_RISC_INT); 92 RD_REG_DWORD(®->hccr); 93 break; 94 } 95 96 /* Clear this intr; it wasn't a mailbox intr */ 97 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); 98 RD_REG_DWORD(®->hccr); 99 } 100 udelay(5); 101 } 102 103 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 104 rval = mb0 & MBS_MASK; 105 for (idx = 0; idx < dwords; idx++) 106 ram[cnt + idx] = swab32(dump[idx]); 107 } else { 108 rval = QLA_FUNCTION_FAILED; 109 } 110 } 111 112 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; 113 return rval; 114 } 115 116 static int 117 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, 118 uint32_t cram_size, void **nxt) 119 { 120 int rval; 121 122 /* Code RAM. */ 123 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); 124 if (rval != QLA_SUCCESS) 125 return rval; 126 127 /* External Memory. */ 128 return qla24xx_dump_ram(ha, 0x100000, *nxt, 129 ha->fw_memory_size - 0x100000 + 1, nxt); 130 } 131 132 static uint32_t * 133 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, 134 uint32_t count, uint32_t *buf) 135 { 136 uint32_t __iomem *dmp_reg; 137 138 WRT_REG_DWORD(®->iobase_addr, iobase); 139 dmp_reg = ®->iobase_window; 140 while (count--) 141 *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); 142 143 return buf; 144 } 145 146 static inline int 147 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) 148 { 149 int rval = QLA_SUCCESS; 150 uint32_t cnt; 151 152 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); 153 for (cnt = 30000; 154 ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && 155 rval == QLA_SUCCESS; cnt--) { 156 if (cnt) 157 udelay(100); 158 else 159 rval = QLA_FUNCTION_TIMEOUT; 160 } 161 162 return rval; 163 } 164 165 static int 166 qla24xx_soft_reset(struct qla_hw_data *ha) 167 { 168 int rval = QLA_SUCCESS; 169 uint32_t cnt; 170 uint16_t mb0, wd; 171 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 172 173 /* Reset RISC. */ 174 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 175 for (cnt = 0; cnt < 30000; cnt++) { 176 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 177 break; 178 179 udelay(10); 180 } 181 182 WRT_REG_DWORD(®->ctrl_status, 183 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 184 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 185 186 udelay(100); 187 /* Wait for firmware to complete NVRAM accesses. */ 188 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); 189 for (cnt = 10000 ; cnt && mb0; cnt--) { 190 udelay(5); 191 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); 192 barrier(); 193 } 194 195 /* Wait for soft-reset to complete. */ 196 for (cnt = 0; cnt < 30000; cnt++) { 197 if ((RD_REG_DWORD(®->ctrl_status) & 198 CSRX_ISP_SOFT_RESET) == 0) 199 break; 200 201 udelay(10); 202 } 203 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 204 RD_REG_DWORD(®->hccr); /* PCI Posting. */ 205 206 for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && 207 rval == QLA_SUCCESS; cnt--) { 208 if (cnt) 209 udelay(100); 210 else 211 rval = QLA_FUNCTION_TIMEOUT; 212 } 213 214 return rval; 215 } 216 217 static int 218 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, 219 uint32_t ram_words, void **nxt) 220 { 221 int rval; 222 uint32_t cnt, stat, timer, words, idx; 223 uint16_t mb0; 224 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 225 dma_addr_t dump_dma = ha->gid_list_dma; 226 uint16_t *dump = (uint16_t *)ha->gid_list; 227 228 rval = QLA_SUCCESS; 229 mb0 = 0; 230 231 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); 232 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 233 234 words = GID_LIST_SIZE / 2; 235 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; 236 cnt += words, addr += words) { 237 if (cnt + words > ram_words) 238 words = ram_words - cnt; 239 240 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); 241 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); 242 243 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); 244 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); 245 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); 246 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); 247 248 WRT_MAILBOX_REG(ha, reg, 4, words); 249 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 250 251 for (timer = 6000000; timer; timer--) { 252 /* Check for pending interrupts. */ 253 stat = RD_REG_DWORD(®->u.isp2300.host_status); 254 if (stat & HSR_RISC_INT) { 255 stat &= 0xff; 256 257 if (stat == 0x1 || stat == 0x2) { 258 set_bit(MBX_INTERRUPT, 259 &ha->mbx_cmd_flags); 260 261 mb0 = RD_MAILBOX_REG(ha, reg, 0); 262 263 /* Release mailbox registers. */ 264 WRT_REG_WORD(®->semaphore, 0); 265 WRT_REG_WORD(®->hccr, 266 HCCR_CLR_RISC_INT); 267 RD_REG_WORD(®->hccr); 268 break; 269 } else if (stat == 0x10 || stat == 0x11) { 270 set_bit(MBX_INTERRUPT, 271 &ha->mbx_cmd_flags); 272 273 mb0 = RD_MAILBOX_REG(ha, reg, 0); 274 275 WRT_REG_WORD(®->hccr, 276 HCCR_CLR_RISC_INT); 277 RD_REG_WORD(®->hccr); 278 break; 279 } 280 281 /* clear this intr; it wasn't a mailbox intr */ 282 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 283 RD_REG_WORD(®->hccr); 284 } 285 udelay(5); 286 } 287 288 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 289 rval = mb0 & MBS_MASK; 290 for (idx = 0; idx < words; idx++) 291 ram[cnt + idx] = swab16(dump[idx]); 292 } else { 293 rval = QLA_FUNCTION_FAILED; 294 } 295 } 296 297 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; 298 return rval; 299 } 300 301 static inline void 302 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, 303 uint16_t *buf) 304 { 305 uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; 306 307 while (count--) 308 *buf++ = htons(RD_REG_WORD(dmp_reg++)); 309 } 310 311 static inline void * 312 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) 313 { 314 if (!ha->eft) 315 return ptr; 316 317 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); 318 return ptr + ntohl(ha->fw_dump->eft_size); 319 } 320 321 static inline void * 322 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 323 { 324 uint32_t cnt; 325 uint32_t *iter_reg; 326 struct qla2xxx_fce_chain *fcec = ptr; 327 328 if (!ha->fce) 329 return ptr; 330 331 *last_chain = &fcec->type; 332 fcec->type = __constant_htonl(DUMP_CHAIN_FCE); 333 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + 334 fce_calc_size(ha->fce_bufs)); 335 fcec->size = htonl(fce_calc_size(ha->fce_bufs)); 336 fcec->addr_l = htonl(LSD(ha->fce_dma)); 337 fcec->addr_h = htonl(MSD(ha->fce_dma)); 338 339 iter_reg = fcec->eregs; 340 for (cnt = 0; cnt < 8; cnt++) 341 *iter_reg++ = htonl(ha->fce_mb[cnt]); 342 343 memcpy(iter_reg, ha->fce, ntohl(fcec->size)); 344 345 return iter_reg; 346 } 347 348 static inline void * 349 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 350 { 351 uint32_t cnt, que_idx; 352 uint8_t que_cnt; 353 struct qla2xxx_mq_chain *mq = ptr; 354 struct device_reg_25xxmq __iomem *reg; 355 356 if (!ha->mqenable) 357 return ptr; 358 359 mq = ptr; 360 *last_chain = &mq->type; 361 mq->type = __constant_htonl(DUMP_CHAIN_MQ); 362 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain)); 363 364 que_cnt = ha->max_req_queues > ha->max_rsp_queues ? 365 ha->max_req_queues : ha->max_rsp_queues; 366 mq->count = htonl(que_cnt); 367 for (cnt = 0; cnt < que_cnt; cnt++) { 368 reg = (struct device_reg_25xxmq *) ((void *) 369 ha->mqiobase + cnt * QLA_QUE_PAGE); 370 que_idx = cnt * 4; 371 mq->qregs[que_idx] = htonl(RD_REG_DWORD(®->req_q_in)); 372 mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(®->req_q_out)); 373 mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(®->rsp_q_in)); 374 mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(®->rsp_q_out)); 375 } 376 377 return ptr + sizeof(struct qla2xxx_mq_chain); 378 } 379 380 /** 381 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 382 * @ha: HA context 383 * @hardware_locked: Called with the hardware_lock 384 */ 385 void 386 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 387 { 388 int rval; 389 uint32_t cnt; 390 struct qla_hw_data *ha = vha->hw; 391 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 392 uint16_t __iomem *dmp_reg; 393 unsigned long flags; 394 struct qla2300_fw_dump *fw; 395 void *nxt; 396 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 397 398 flags = 0; 399 400 if (!hardware_locked) 401 spin_lock_irqsave(&ha->hardware_lock, flags); 402 403 if (!ha->fw_dump) { 404 qla_printk(KERN_WARNING, ha, 405 "No buffer available for dump!!!\n"); 406 goto qla2300_fw_dump_failed; 407 } 408 409 if (ha->fw_dumped) { 410 qla_printk(KERN_WARNING, ha, 411 "Firmware has been previously dumped (%p) -- ignoring " 412 "request...\n", ha->fw_dump); 413 goto qla2300_fw_dump_failed; 414 } 415 fw = &ha->fw_dump->isp.isp23; 416 qla2xxx_prep_dump(ha, ha->fw_dump); 417 418 rval = QLA_SUCCESS; 419 fw->hccr = htons(RD_REG_WORD(®->hccr)); 420 421 /* Pause RISC. */ 422 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 423 if (IS_QLA2300(ha)) { 424 for (cnt = 30000; 425 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 426 rval == QLA_SUCCESS; cnt--) { 427 if (cnt) 428 udelay(100); 429 else 430 rval = QLA_FUNCTION_TIMEOUT; 431 } 432 } else { 433 RD_REG_WORD(®->hccr); /* PCI Posting. */ 434 udelay(10); 435 } 436 437 if (rval == QLA_SUCCESS) { 438 dmp_reg = ®->flash_address; 439 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 440 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 441 442 dmp_reg = ®->u.isp2300.req_q_in; 443 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) 444 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 445 446 dmp_reg = ®->u.isp2300.mailbox0; 447 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 448 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 449 450 WRT_REG_WORD(®->ctrl_status, 0x40); 451 qla2xxx_read_window(reg, 32, fw->resp_dma_reg); 452 453 WRT_REG_WORD(®->ctrl_status, 0x50); 454 qla2xxx_read_window(reg, 48, fw->dma_reg); 455 456 WRT_REG_WORD(®->ctrl_status, 0x00); 457 dmp_reg = ®->risc_hw; 458 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 459 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 460 461 WRT_REG_WORD(®->pcr, 0x2000); 462 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 463 464 WRT_REG_WORD(®->pcr, 0x2200); 465 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 466 467 WRT_REG_WORD(®->pcr, 0x2400); 468 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 469 470 WRT_REG_WORD(®->pcr, 0x2600); 471 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 472 473 WRT_REG_WORD(®->pcr, 0x2800); 474 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 475 476 WRT_REG_WORD(®->pcr, 0x2A00); 477 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 478 479 WRT_REG_WORD(®->pcr, 0x2C00); 480 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 481 482 WRT_REG_WORD(®->pcr, 0x2E00); 483 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 484 485 WRT_REG_WORD(®->ctrl_status, 0x10); 486 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); 487 488 WRT_REG_WORD(®->ctrl_status, 0x20); 489 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 490 491 WRT_REG_WORD(®->ctrl_status, 0x30); 492 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 493 494 /* Reset RISC. */ 495 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 496 for (cnt = 0; cnt < 30000; cnt++) { 497 if ((RD_REG_WORD(®->ctrl_status) & 498 CSR_ISP_SOFT_RESET) == 0) 499 break; 500 501 udelay(10); 502 } 503 } 504 505 if (!IS_QLA2300(ha)) { 506 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 507 rval == QLA_SUCCESS; cnt--) { 508 if (cnt) 509 udelay(100); 510 else 511 rval = QLA_FUNCTION_TIMEOUT; 512 } 513 } 514 515 /* Get RISC SRAM. */ 516 if (rval == QLA_SUCCESS) 517 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, 518 sizeof(fw->risc_ram) / 2, &nxt); 519 520 /* Get stack SRAM. */ 521 if (rval == QLA_SUCCESS) 522 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, 523 sizeof(fw->stack_ram) / 2, &nxt); 524 525 /* Get data SRAM. */ 526 if (rval == QLA_SUCCESS) 527 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, 528 ha->fw_memory_size - 0x11000 + 1, &nxt); 529 530 if (rval == QLA_SUCCESS) 531 qla2xxx_copy_queues(ha, nxt); 532 533 if (rval != QLA_SUCCESS) { 534 qla_printk(KERN_WARNING, ha, 535 "Failed to dump firmware (%x)!!!\n", rval); 536 ha->fw_dumped = 0; 537 538 } else { 539 qla_printk(KERN_INFO, ha, 540 "Firmware dump saved to temp buffer (%ld/%p).\n", 541 base_vha->host_no, ha->fw_dump); 542 ha->fw_dumped = 1; 543 } 544 545 qla2300_fw_dump_failed: 546 if (!hardware_locked) 547 spin_unlock_irqrestore(&ha->hardware_lock, flags); 548 } 549 550 /** 551 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. 552 * @ha: HA context 553 * @hardware_locked: Called with the hardware_lock 554 */ 555 void 556 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 557 { 558 int rval; 559 uint32_t cnt, timer; 560 uint16_t risc_address; 561 uint16_t mb0, mb2; 562 struct qla_hw_data *ha = vha->hw; 563 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 564 uint16_t __iomem *dmp_reg; 565 unsigned long flags; 566 struct qla2100_fw_dump *fw; 567 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 568 569 risc_address = 0; 570 mb0 = mb2 = 0; 571 flags = 0; 572 573 if (!hardware_locked) 574 spin_lock_irqsave(&ha->hardware_lock, flags); 575 576 if (!ha->fw_dump) { 577 qla_printk(KERN_WARNING, ha, 578 "No buffer available for dump!!!\n"); 579 goto qla2100_fw_dump_failed; 580 } 581 582 if (ha->fw_dumped) { 583 qla_printk(KERN_WARNING, ha, 584 "Firmware has been previously dumped (%p) -- ignoring " 585 "request...\n", ha->fw_dump); 586 goto qla2100_fw_dump_failed; 587 } 588 fw = &ha->fw_dump->isp.isp21; 589 qla2xxx_prep_dump(ha, ha->fw_dump); 590 591 rval = QLA_SUCCESS; 592 fw->hccr = htons(RD_REG_WORD(®->hccr)); 593 594 /* Pause RISC. */ 595 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 596 for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 597 rval == QLA_SUCCESS; cnt--) { 598 if (cnt) 599 udelay(100); 600 else 601 rval = QLA_FUNCTION_TIMEOUT; 602 } 603 if (rval == QLA_SUCCESS) { 604 dmp_reg = ®->flash_address; 605 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 606 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 607 608 dmp_reg = ®->u.isp2100.mailbox0; 609 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 610 if (cnt == 8) 611 dmp_reg = ®->u_end.isp2200.mailbox8; 612 613 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 614 } 615 616 dmp_reg = ®->u.isp2100.unused_2[0]; 617 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 618 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 619 620 WRT_REG_WORD(®->ctrl_status, 0x00); 621 dmp_reg = ®->risc_hw; 622 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 623 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 624 625 WRT_REG_WORD(®->pcr, 0x2000); 626 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 627 628 WRT_REG_WORD(®->pcr, 0x2100); 629 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 630 631 WRT_REG_WORD(®->pcr, 0x2200); 632 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 633 634 WRT_REG_WORD(®->pcr, 0x2300); 635 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 636 637 WRT_REG_WORD(®->pcr, 0x2400); 638 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 639 640 WRT_REG_WORD(®->pcr, 0x2500); 641 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 642 643 WRT_REG_WORD(®->pcr, 0x2600); 644 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 645 646 WRT_REG_WORD(®->pcr, 0x2700); 647 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 648 649 WRT_REG_WORD(®->ctrl_status, 0x10); 650 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); 651 652 WRT_REG_WORD(®->ctrl_status, 0x20); 653 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 654 655 WRT_REG_WORD(®->ctrl_status, 0x30); 656 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 657 658 /* Reset the ISP. */ 659 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 660 } 661 662 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 663 rval == QLA_SUCCESS; cnt--) { 664 if (cnt) 665 udelay(100); 666 else 667 rval = QLA_FUNCTION_TIMEOUT; 668 } 669 670 /* Pause RISC. */ 671 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && 672 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { 673 674 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 675 for (cnt = 30000; 676 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 677 rval == QLA_SUCCESS; cnt--) { 678 if (cnt) 679 udelay(100); 680 else 681 rval = QLA_FUNCTION_TIMEOUT; 682 } 683 if (rval == QLA_SUCCESS) { 684 /* Set memory configuration and timing. */ 685 if (IS_QLA2100(ha)) 686 WRT_REG_WORD(®->mctr, 0xf1); 687 else 688 WRT_REG_WORD(®->mctr, 0xf2); 689 RD_REG_WORD(®->mctr); /* PCI Posting. */ 690 691 /* Release RISC. */ 692 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 693 } 694 } 695 696 if (rval == QLA_SUCCESS) { 697 /* Get RISC SRAM. */ 698 risc_address = 0x1000; 699 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); 700 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 701 } 702 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; 703 cnt++, risc_address++) { 704 WRT_MAILBOX_REG(ha, reg, 1, risc_address); 705 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 706 707 for (timer = 6000000; timer != 0; timer--) { 708 /* Check for pending interrupts. */ 709 if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { 710 if (RD_REG_WORD(®->semaphore) & BIT_0) { 711 set_bit(MBX_INTERRUPT, 712 &ha->mbx_cmd_flags); 713 714 mb0 = RD_MAILBOX_REG(ha, reg, 0); 715 mb2 = RD_MAILBOX_REG(ha, reg, 2); 716 717 WRT_REG_WORD(®->semaphore, 0); 718 WRT_REG_WORD(®->hccr, 719 HCCR_CLR_RISC_INT); 720 RD_REG_WORD(®->hccr); 721 break; 722 } 723 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 724 RD_REG_WORD(®->hccr); 725 } 726 udelay(5); 727 } 728 729 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 730 rval = mb0 & MBS_MASK; 731 fw->risc_ram[cnt] = htons(mb2); 732 } else { 733 rval = QLA_FUNCTION_FAILED; 734 } 735 } 736 737 if (rval == QLA_SUCCESS) 738 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); 739 740 if (rval != QLA_SUCCESS) { 741 qla_printk(KERN_WARNING, ha, 742 "Failed to dump firmware (%x)!!!\n", rval); 743 ha->fw_dumped = 0; 744 745 } else { 746 qla_printk(KERN_INFO, ha, 747 "Firmware dump saved to temp buffer (%ld/%p).\n", 748 base_vha->host_no, ha->fw_dump); 749 ha->fw_dumped = 1; 750 } 751 752 qla2100_fw_dump_failed: 753 if (!hardware_locked) 754 spin_unlock_irqrestore(&ha->hardware_lock, flags); 755 } 756 757 void 758 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 759 { 760 int rval; 761 uint32_t cnt; 762 uint32_t risc_address; 763 struct qla_hw_data *ha = vha->hw; 764 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 765 uint32_t __iomem *dmp_reg; 766 uint32_t *iter_reg; 767 uint16_t __iomem *mbx_reg; 768 unsigned long flags; 769 struct qla24xx_fw_dump *fw; 770 uint32_t ext_mem_cnt; 771 void *nxt; 772 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 773 774 risc_address = ext_mem_cnt = 0; 775 flags = 0; 776 777 if (!hardware_locked) 778 spin_lock_irqsave(&ha->hardware_lock, flags); 779 780 if (!ha->fw_dump) { 781 qla_printk(KERN_WARNING, ha, 782 "No buffer available for dump!!!\n"); 783 goto qla24xx_fw_dump_failed; 784 } 785 786 if (ha->fw_dumped) { 787 qla_printk(KERN_WARNING, ha, 788 "Firmware has been previously dumped (%p) -- ignoring " 789 "request...\n", ha->fw_dump); 790 goto qla24xx_fw_dump_failed; 791 } 792 fw = &ha->fw_dump->isp.isp24; 793 qla2xxx_prep_dump(ha, ha->fw_dump); 794 795 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 796 797 /* Pause RISC. */ 798 rval = qla24xx_pause_risc(reg); 799 if (rval != QLA_SUCCESS) 800 goto qla24xx_fw_dump_failed_0; 801 802 /* Host interface registers. */ 803 dmp_reg = ®->flash_addr; 804 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 805 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 806 807 /* Disable interrupts. */ 808 WRT_REG_DWORD(®->ictrl, 0); 809 RD_REG_DWORD(®->ictrl); 810 811 /* Shadow registers. */ 812 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 813 RD_REG_DWORD(®->iobase_addr); 814 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 815 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 816 817 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 818 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 819 820 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 821 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 822 823 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 824 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 825 826 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 827 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 828 829 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 830 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 831 832 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 833 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 834 835 /* Mailbox registers. */ 836 mbx_reg = ®->mailbox0; 837 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 838 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 839 840 /* Transfer sequence registers. */ 841 iter_reg = fw->xseq_gp_reg; 842 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 843 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 844 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 845 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 846 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 847 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 848 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 849 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 850 851 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); 852 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 853 854 /* Receive sequence registers. */ 855 iter_reg = fw->rseq_gp_reg; 856 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 857 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 858 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 859 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 860 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 861 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 862 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 863 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 864 865 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); 866 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 867 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 868 869 /* Command DMA registers. */ 870 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 871 872 /* Queues. */ 873 iter_reg = fw->req0_dma_reg; 874 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 875 dmp_reg = ®->iobase_q; 876 for (cnt = 0; cnt < 7; cnt++) 877 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 878 879 iter_reg = fw->resp0_dma_reg; 880 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 881 dmp_reg = ®->iobase_q; 882 for (cnt = 0; cnt < 7; cnt++) 883 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 884 885 iter_reg = fw->req1_dma_reg; 886 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 887 dmp_reg = ®->iobase_q; 888 for (cnt = 0; cnt < 7; cnt++) 889 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 890 891 /* Transmit DMA registers. */ 892 iter_reg = fw->xmt0_dma_reg; 893 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 894 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 895 896 iter_reg = fw->xmt1_dma_reg; 897 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 898 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 899 900 iter_reg = fw->xmt2_dma_reg; 901 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 902 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 903 904 iter_reg = fw->xmt3_dma_reg; 905 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 906 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 907 908 iter_reg = fw->xmt4_dma_reg; 909 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 910 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 911 912 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 913 914 /* Receive DMA registers. */ 915 iter_reg = fw->rcvt0_data_dma_reg; 916 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 917 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 918 919 iter_reg = fw->rcvt1_data_dma_reg; 920 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 921 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 922 923 /* RISC registers. */ 924 iter_reg = fw->risc_gp_reg; 925 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 926 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 927 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 928 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 929 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 930 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 931 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 932 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 933 934 /* Local memory controller registers. */ 935 iter_reg = fw->lmc_reg; 936 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 937 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 938 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 939 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 940 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 941 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 942 qla24xx_read_window(reg, 0x3060, 16, iter_reg); 943 944 /* Fibre Protocol Module registers. */ 945 iter_reg = fw->fpm_hdw_reg; 946 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 947 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 948 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 949 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 950 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 951 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 952 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 953 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 954 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 955 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 956 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 957 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 958 959 /* Frame Buffer registers. */ 960 iter_reg = fw->fb_hdw_reg; 961 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 962 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 963 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 964 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 965 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 966 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 967 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 968 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 969 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 970 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 971 qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 972 973 rval = qla24xx_soft_reset(ha); 974 if (rval != QLA_SUCCESS) 975 goto qla24xx_fw_dump_failed_0; 976 977 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 978 &nxt); 979 if (rval != QLA_SUCCESS) 980 goto qla24xx_fw_dump_failed_0; 981 982 nxt = qla2xxx_copy_queues(ha, nxt); 983 984 qla24xx_copy_eft(ha, nxt); 985 986 qla24xx_fw_dump_failed_0: 987 if (rval != QLA_SUCCESS) { 988 qla_printk(KERN_WARNING, ha, 989 "Failed to dump firmware (%x)!!!\n", rval); 990 ha->fw_dumped = 0; 991 992 } else { 993 qla_printk(KERN_INFO, ha, 994 "Firmware dump saved to temp buffer (%ld/%p).\n", 995 base_vha->host_no, ha->fw_dump); 996 ha->fw_dumped = 1; 997 } 998 999 qla24xx_fw_dump_failed: 1000 if (!hardware_locked) 1001 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1002 } 1003 1004 void 1005 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1006 { 1007 int rval; 1008 uint32_t cnt; 1009 uint32_t risc_address; 1010 struct qla_hw_data *ha = vha->hw; 1011 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1012 uint32_t __iomem *dmp_reg; 1013 uint32_t *iter_reg; 1014 uint16_t __iomem *mbx_reg; 1015 unsigned long flags; 1016 struct qla25xx_fw_dump *fw; 1017 uint32_t ext_mem_cnt; 1018 void *nxt, *nxt_chain; 1019 uint32_t *last_chain = NULL; 1020 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1021 1022 risc_address = ext_mem_cnt = 0; 1023 flags = 0; 1024 1025 if (!hardware_locked) 1026 spin_lock_irqsave(&ha->hardware_lock, flags); 1027 1028 if (!ha->fw_dump) { 1029 qla_printk(KERN_WARNING, ha, 1030 "No buffer available for dump!!!\n"); 1031 goto qla25xx_fw_dump_failed; 1032 } 1033 1034 if (ha->fw_dumped) { 1035 qla_printk(KERN_WARNING, ha, 1036 "Firmware has been previously dumped (%p) -- ignoring " 1037 "request...\n", ha->fw_dump); 1038 goto qla25xx_fw_dump_failed; 1039 } 1040 fw = &ha->fw_dump->isp.isp25; 1041 qla2xxx_prep_dump(ha, ha->fw_dump); 1042 ha->fw_dump->version = __constant_htonl(2); 1043 1044 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1045 1046 /* Pause RISC. */ 1047 rval = qla24xx_pause_risc(reg); 1048 if (rval != QLA_SUCCESS) 1049 goto qla25xx_fw_dump_failed_0; 1050 1051 /* Host/Risc registers. */ 1052 iter_reg = fw->host_risc_reg; 1053 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1054 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1055 1056 /* PCIe registers. */ 1057 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1058 RD_REG_DWORD(®->iobase_addr); 1059 WRT_REG_DWORD(®->iobase_window, 0x01); 1060 dmp_reg = ®->iobase_c4; 1061 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1062 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1063 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1064 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1065 1066 WRT_REG_DWORD(®->iobase_window, 0x00); 1067 RD_REG_DWORD(®->iobase_window); 1068 1069 /* Host interface registers. */ 1070 dmp_reg = ®->flash_addr; 1071 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1072 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1073 1074 /* Disable interrupts. */ 1075 WRT_REG_DWORD(®->ictrl, 0); 1076 RD_REG_DWORD(®->ictrl); 1077 1078 /* Shadow registers. */ 1079 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1080 RD_REG_DWORD(®->iobase_addr); 1081 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1082 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1083 1084 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1085 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1086 1087 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1088 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1089 1090 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1091 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1092 1093 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1094 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1095 1096 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1097 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1098 1099 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1100 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1101 1102 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1103 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1104 1105 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1106 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1107 1108 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1109 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1110 1111 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1112 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1113 1114 /* RISC I/O register. */ 1115 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1116 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1117 1118 /* Mailbox registers. */ 1119 mbx_reg = ®->mailbox0; 1120 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1121 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1122 1123 /* Transfer sequence registers. */ 1124 iter_reg = fw->xseq_gp_reg; 1125 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1126 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1127 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1128 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1129 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1130 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1131 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1132 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1133 1134 iter_reg = fw->xseq_0_reg; 1135 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1136 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1137 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1138 1139 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1140 1141 /* Receive sequence registers. */ 1142 iter_reg = fw->rseq_gp_reg; 1143 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1144 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1145 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1146 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1147 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1148 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1149 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1150 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1151 1152 iter_reg = fw->rseq_0_reg; 1153 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1154 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1155 1156 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1157 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1158 1159 /* Auxiliary sequence registers. */ 1160 iter_reg = fw->aseq_gp_reg; 1161 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1162 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1163 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1164 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1165 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1166 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1167 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1168 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1169 1170 iter_reg = fw->aseq_0_reg; 1171 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1172 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1173 1174 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1175 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1176 1177 /* Command DMA registers. */ 1178 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1179 1180 /* Queues. */ 1181 iter_reg = fw->req0_dma_reg; 1182 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1183 dmp_reg = ®->iobase_q; 1184 for (cnt = 0; cnt < 7; cnt++) 1185 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1186 1187 iter_reg = fw->resp0_dma_reg; 1188 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1189 dmp_reg = ®->iobase_q; 1190 for (cnt = 0; cnt < 7; cnt++) 1191 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1192 1193 iter_reg = fw->req1_dma_reg; 1194 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1195 dmp_reg = ®->iobase_q; 1196 for (cnt = 0; cnt < 7; cnt++) 1197 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1198 1199 /* Transmit DMA registers. */ 1200 iter_reg = fw->xmt0_dma_reg; 1201 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1202 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1203 1204 iter_reg = fw->xmt1_dma_reg; 1205 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1206 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1207 1208 iter_reg = fw->xmt2_dma_reg; 1209 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1210 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1211 1212 iter_reg = fw->xmt3_dma_reg; 1213 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1214 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1215 1216 iter_reg = fw->xmt4_dma_reg; 1217 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1218 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1219 1220 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1221 1222 /* Receive DMA registers. */ 1223 iter_reg = fw->rcvt0_data_dma_reg; 1224 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1225 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1226 1227 iter_reg = fw->rcvt1_data_dma_reg; 1228 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1229 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1230 1231 /* RISC registers. */ 1232 iter_reg = fw->risc_gp_reg; 1233 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1234 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1235 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1236 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1237 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1238 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1239 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1240 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1241 1242 /* Local memory controller registers. */ 1243 iter_reg = fw->lmc_reg; 1244 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1245 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1246 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1247 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1248 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1249 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1250 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1251 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1252 1253 /* Fibre Protocol Module registers. */ 1254 iter_reg = fw->fpm_hdw_reg; 1255 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1256 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1257 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1258 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1259 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1260 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1261 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1262 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1263 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1264 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1265 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1266 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1267 1268 /* Frame Buffer registers. */ 1269 iter_reg = fw->fb_hdw_reg; 1270 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1271 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1272 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1273 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1274 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1275 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1276 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1277 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1278 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1279 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1280 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1281 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1282 1283 /* Multi queue registers */ 1284 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1285 &last_chain); 1286 1287 rval = qla24xx_soft_reset(ha); 1288 if (rval != QLA_SUCCESS) 1289 goto qla25xx_fw_dump_failed_0; 1290 1291 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1292 &nxt); 1293 if (rval != QLA_SUCCESS) 1294 goto qla25xx_fw_dump_failed_0; 1295 1296 nxt = qla2xxx_copy_queues(ha, nxt); 1297 1298 nxt = qla24xx_copy_eft(ha, nxt); 1299 1300 /* Chain entries -- started with MQ. */ 1301 qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1302 if (last_chain) { 1303 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 1304 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 1305 } 1306 1307 qla25xx_fw_dump_failed_0: 1308 if (rval != QLA_SUCCESS) { 1309 qla_printk(KERN_WARNING, ha, 1310 "Failed to dump firmware (%x)!!!\n", rval); 1311 ha->fw_dumped = 0; 1312 1313 } else { 1314 qla_printk(KERN_INFO, ha, 1315 "Firmware dump saved to temp buffer (%ld/%p).\n", 1316 base_vha->host_no, ha->fw_dump); 1317 ha->fw_dumped = 1; 1318 } 1319 1320 qla25xx_fw_dump_failed: 1321 if (!hardware_locked) 1322 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1323 } 1324 1325 void 1326 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1327 { 1328 int rval; 1329 uint32_t cnt; 1330 uint32_t risc_address; 1331 struct qla_hw_data *ha = vha->hw; 1332 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1333 uint32_t __iomem *dmp_reg; 1334 uint32_t *iter_reg; 1335 uint16_t __iomem *mbx_reg; 1336 unsigned long flags; 1337 struct qla81xx_fw_dump *fw; 1338 uint32_t ext_mem_cnt; 1339 void *nxt, *nxt_chain; 1340 uint32_t *last_chain = NULL; 1341 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1342 1343 risc_address = ext_mem_cnt = 0; 1344 flags = 0; 1345 1346 if (!hardware_locked) 1347 spin_lock_irqsave(&ha->hardware_lock, flags); 1348 1349 if (!ha->fw_dump) { 1350 qla_printk(KERN_WARNING, ha, 1351 "No buffer available for dump!!!\n"); 1352 goto qla81xx_fw_dump_failed; 1353 } 1354 1355 if (ha->fw_dumped) { 1356 qla_printk(KERN_WARNING, ha, 1357 "Firmware has been previously dumped (%p) -- ignoring " 1358 "request...\n", ha->fw_dump); 1359 goto qla81xx_fw_dump_failed; 1360 } 1361 fw = &ha->fw_dump->isp.isp81; 1362 qla2xxx_prep_dump(ha, ha->fw_dump); 1363 1364 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1365 1366 /* Pause RISC. */ 1367 rval = qla24xx_pause_risc(reg); 1368 if (rval != QLA_SUCCESS) 1369 goto qla81xx_fw_dump_failed_0; 1370 1371 /* Host/Risc registers. */ 1372 iter_reg = fw->host_risc_reg; 1373 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1374 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1375 1376 /* PCIe registers. */ 1377 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1378 RD_REG_DWORD(®->iobase_addr); 1379 WRT_REG_DWORD(®->iobase_window, 0x01); 1380 dmp_reg = ®->iobase_c4; 1381 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1382 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1383 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1384 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1385 1386 WRT_REG_DWORD(®->iobase_window, 0x00); 1387 RD_REG_DWORD(®->iobase_window); 1388 1389 /* Host interface registers. */ 1390 dmp_reg = ®->flash_addr; 1391 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1392 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1393 1394 /* Disable interrupts. */ 1395 WRT_REG_DWORD(®->ictrl, 0); 1396 RD_REG_DWORD(®->ictrl); 1397 1398 /* Shadow registers. */ 1399 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1400 RD_REG_DWORD(®->iobase_addr); 1401 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1402 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1403 1404 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1405 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1406 1407 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1408 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1409 1410 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1411 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1412 1413 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1414 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1415 1416 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1417 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1418 1419 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1420 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1421 1422 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1423 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1424 1425 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1426 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1427 1428 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1429 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1430 1431 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1432 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1433 1434 /* RISC I/O register. */ 1435 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1436 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1437 1438 /* Mailbox registers. */ 1439 mbx_reg = ®->mailbox0; 1440 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1441 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1442 1443 /* Transfer sequence registers. */ 1444 iter_reg = fw->xseq_gp_reg; 1445 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1446 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1447 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1448 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1449 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1450 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1451 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1452 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1453 1454 iter_reg = fw->xseq_0_reg; 1455 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1456 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1457 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1458 1459 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1460 1461 /* Receive sequence registers. */ 1462 iter_reg = fw->rseq_gp_reg; 1463 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1464 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1465 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1466 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1467 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1468 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1469 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1470 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1471 1472 iter_reg = fw->rseq_0_reg; 1473 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1474 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1475 1476 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1477 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1478 1479 /* Auxiliary sequence registers. */ 1480 iter_reg = fw->aseq_gp_reg; 1481 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1482 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1483 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1484 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1485 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1486 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1487 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1488 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1489 1490 iter_reg = fw->aseq_0_reg; 1491 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1492 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1493 1494 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1495 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1496 1497 /* Command DMA registers. */ 1498 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1499 1500 /* Queues. */ 1501 iter_reg = fw->req0_dma_reg; 1502 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1503 dmp_reg = ®->iobase_q; 1504 for (cnt = 0; cnt < 7; cnt++) 1505 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1506 1507 iter_reg = fw->resp0_dma_reg; 1508 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1509 dmp_reg = ®->iobase_q; 1510 for (cnt = 0; cnt < 7; cnt++) 1511 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1512 1513 iter_reg = fw->req1_dma_reg; 1514 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1515 dmp_reg = ®->iobase_q; 1516 for (cnt = 0; cnt < 7; cnt++) 1517 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1518 1519 /* Transmit DMA registers. */ 1520 iter_reg = fw->xmt0_dma_reg; 1521 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1522 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1523 1524 iter_reg = fw->xmt1_dma_reg; 1525 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1526 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1527 1528 iter_reg = fw->xmt2_dma_reg; 1529 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1530 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1531 1532 iter_reg = fw->xmt3_dma_reg; 1533 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1534 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1535 1536 iter_reg = fw->xmt4_dma_reg; 1537 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1538 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1539 1540 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1541 1542 /* Receive DMA registers. */ 1543 iter_reg = fw->rcvt0_data_dma_reg; 1544 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1545 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1546 1547 iter_reg = fw->rcvt1_data_dma_reg; 1548 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1549 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1550 1551 /* RISC registers. */ 1552 iter_reg = fw->risc_gp_reg; 1553 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1554 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1555 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1556 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1557 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1558 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1559 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1560 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1561 1562 /* Local memory controller registers. */ 1563 iter_reg = fw->lmc_reg; 1564 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1565 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1566 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1567 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1568 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1569 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1570 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1571 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1572 1573 /* Fibre Protocol Module registers. */ 1574 iter_reg = fw->fpm_hdw_reg; 1575 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1576 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1577 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1578 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1579 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1580 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1581 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1582 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1583 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1584 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1585 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1586 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1587 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); 1588 qla24xx_read_window(reg, 0x40D0, 16, iter_reg); 1589 1590 /* Frame Buffer registers. */ 1591 iter_reg = fw->fb_hdw_reg; 1592 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1593 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1594 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1595 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1596 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1597 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1598 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1599 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1600 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1601 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1602 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1603 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); 1604 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1605 1606 /* Multi queue registers */ 1607 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1608 &last_chain); 1609 1610 rval = qla24xx_soft_reset(ha); 1611 if (rval != QLA_SUCCESS) 1612 goto qla81xx_fw_dump_failed_0; 1613 1614 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1615 &nxt); 1616 if (rval != QLA_SUCCESS) 1617 goto qla81xx_fw_dump_failed_0; 1618 1619 nxt = qla2xxx_copy_queues(ha, nxt); 1620 1621 nxt = qla24xx_copy_eft(ha, nxt); 1622 1623 /* Chain entries -- started with MQ. */ 1624 qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1625 if (last_chain) { 1626 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 1627 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 1628 } 1629 1630 qla81xx_fw_dump_failed_0: 1631 if (rval != QLA_SUCCESS) { 1632 qla_printk(KERN_WARNING, ha, 1633 "Failed to dump firmware (%x)!!!\n", rval); 1634 ha->fw_dumped = 0; 1635 1636 } else { 1637 qla_printk(KERN_INFO, ha, 1638 "Firmware dump saved to temp buffer (%ld/%p).\n", 1639 base_vha->host_no, ha->fw_dump); 1640 ha->fw_dumped = 1; 1641 } 1642 1643 qla81xx_fw_dump_failed: 1644 if (!hardware_locked) 1645 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1646 } 1647 1648 /****************************************************************************/ 1649 /* Driver Debug Functions. */ 1650 /****************************************************************************/ 1651 1652 void 1653 qla2x00_dump_regs(scsi_qla_host_t *vha) 1654 { 1655 int i; 1656 struct qla_hw_data *ha = vha->hw; 1657 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1658 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 1659 uint16_t __iomem *mbx_reg; 1660 1661 mbx_reg = IS_FWI2_CAPABLE(ha) ? ®24->mailbox0: 1662 MAILBOX_REG(ha, reg, 0); 1663 1664 printk("Mailbox registers:\n"); 1665 for (i = 0; i < 6; i++) 1666 printk("scsi(%ld): mbox %d 0x%04x \n", vha->host_no, i, 1667 RD_REG_WORD(mbx_reg++)); 1668 } 1669 1670 1671 void 1672 qla2x00_dump_buffer(uint8_t * b, uint32_t size) 1673 { 1674 uint32_t cnt; 1675 uint8_t c; 1676 1677 printk(" 0 1 2 3 4 5 6 7 8 9 " 1678 "Ah Bh Ch Dh Eh Fh\n"); 1679 printk("----------------------------------------" 1680 "----------------------\n"); 1681 1682 for (cnt = 0; cnt < size;) { 1683 c = *b++; 1684 printk("%02x",(uint32_t) c); 1685 cnt++; 1686 if (!(cnt % 16)) 1687 printk("\n"); 1688 else 1689 printk(" "); 1690 } 1691 if (cnt % 16) 1692 printk("\n"); 1693 } 1694 1695 1696