1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8 /* 9 * Table for showing the current message id in use for particular level 10 * Change this table for addition of log/debug messages. 11 * ---------------------------------------------------------------------- 12 * | Level | Last Value Used | Holes | 13 * ---------------------------------------------------------------------- 14 * | Module Init and Probe | 0x017d | 0x004b,0x0141 | 15 * | | | 0x0144,0x0146 | 16 * | | | 0x015b-0x0160 | 17 * | | | 0x016e-0x0170 | 18 * | Mailbox commands | 0x1187 | 0x1018-0x1019 | 19 * | | | 0x10ca | 20 * | | | 0x1115-0x1116 | 21 * | | | 0x111a-0x111b | 22 * | | | 0x1155-0x1158 | 23 * | Device Discovery | 0x2095 | 0x2020-0x2022, | 24 * | | | 0x2011-0x2012, | 25 * | | | 0x2016 | 26 * | Queue Command and IO tracing | 0x3059 | 0x3006-0x300b | 27 * | | | 0x3027-0x3028 | 28 * | | | 0x303d-0x3041 | 29 * | | | 0x302d,0x3033 | 30 * | | | 0x3036,0x3038 | 31 * | | | 0x303a | 32 * | DPC Thread | 0x4023 | 0x4002,0x4013 | 33 * | Async Events | 0x5087 | 0x502b-0x502f | 34 * | | | 0x5047,0x5052 | 35 * | | | 0x5084,0x5075 | 36 * | | | 0x503d,0x5044 | 37 * | | | 0x507b | 38 * | Timer Routines | 0x6012 | | 39 * | User Space Interactions | 0x70e2 | 0x7018,0x702e | 40 * | | | 0x7020,0x7024 | 41 * | | | 0x7039,0x7045 | 42 * | | | 0x7073-0x7075 | 43 * | | | 0x70a5-0x70a6 | 44 * | | | 0x70a8,0x70ab | 45 * | | | 0x70ad-0x70ae | 46 * | | | 0x70d7-0x70db | 47 * | | | 0x70de-0x70df | 48 * | Task Management | 0x803d | 0x8025-0x8026 | 49 * | | | 0x800b,0x8039 | 50 * | AER/EEH | 0x9011 | | 51 * | Virtual Port | 0xa007 | | 52 * | ISP82XX Specific | 0xb14c | 0xb002,0xb024 | 53 * | | | 0xb09e,0xb0ae | 54 * | | | 0xb0e0-0xb0ef | 55 * | | | 0xb085,0xb0dc | 56 * | | | 0xb107,0xb108 | 57 * | | | 0xb111,0xb11e | 58 * | | | 0xb12c,0xb12d | 59 * | | | 0xb13a,0xb142 | 60 * | | | 0xb13c-0xb140 | 61 * | | | 0xb149 | 62 * | MultiQ | 0xc00c | | 63 * | Misc | 0xd2ff | 0xd017-0xd019 | 64 * | | | 0xd020 | 65 * | | | 0xd02e-0xd0ff | 66 * | | | 0xd101-0xd1fe | 67 * | | | 0xd212-0xd2fe | 68 * | Target Mode | 0xe070 | 0xe021 | 69 * | Target Mode Management | 0xf072 | 0xf002-0xf003 | 70 * | | | 0xf046-0xf049 | 71 * | Target Mode Task Management | 0x1000b | | 72 * ---------------------------------------------------------------------- 73 */ 74 75 #include "qla_def.h" 76 77 #include <linux/delay.h> 78 79 static uint32_t ql_dbg_offset = 0x800; 80 81 static inline void 82 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) 83 { 84 fw_dump->fw_major_version = htonl(ha->fw_major_version); 85 fw_dump->fw_minor_version = htonl(ha->fw_minor_version); 86 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); 87 fw_dump->fw_attributes = htonl(ha->fw_attributes); 88 89 fw_dump->vendor = htonl(ha->pdev->vendor); 90 fw_dump->device = htonl(ha->pdev->device); 91 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); 92 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); 93 } 94 95 static inline void * 96 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) 97 { 98 struct req_que *req = ha->req_q_map[0]; 99 struct rsp_que *rsp = ha->rsp_q_map[0]; 100 /* Request queue. */ 101 memcpy(ptr, req->ring, req->length * 102 sizeof(request_t)); 103 104 /* Response queue. */ 105 ptr += req->length * sizeof(request_t); 106 memcpy(ptr, rsp->ring, rsp->length * 107 sizeof(response_t)); 108 109 return ptr + (rsp->length * sizeof(response_t)); 110 } 111 112 int 113 qla27xx_dump_mpi_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, 114 uint32_t ram_dwords, void **nxt) 115 { 116 int rval; 117 uint32_t cnt, stat, timer, dwords, idx; 118 uint16_t mb0, mb1; 119 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 120 dma_addr_t dump_dma = ha->gid_list_dma; 121 uint32_t *dump = (uint32_t *)ha->gid_list; 122 123 rval = QLA_SUCCESS; 124 mb0 = 0; 125 126 WRT_REG_WORD(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM); 127 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 128 129 dwords = qla2x00_gid_list_size(ha) / 4; 130 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; 131 cnt += dwords, addr += dwords) { 132 if (cnt + dwords > ram_dwords) 133 dwords = ram_dwords - cnt; 134 135 WRT_REG_WORD(®->mailbox1, LSW(addr)); 136 WRT_REG_WORD(®->mailbox8, MSW(addr)); 137 138 WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); 139 WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); 140 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); 141 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); 142 143 WRT_REG_WORD(®->mailbox4, MSW(dwords)); 144 WRT_REG_WORD(®->mailbox5, LSW(dwords)); 145 146 WRT_REG_WORD(®->mailbox9, 0); 147 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 148 149 ha->flags.mbox_int = 0; 150 for (timer = 6000000; timer; timer--) { 151 /* Check for pending interrupts. */ 152 stat = RD_REG_DWORD(®->host_status); 153 if (stat & HSRX_RISC_INT) { 154 stat &= 0xff; 155 156 if (stat == 0x1 || stat == 0x2 || 157 stat == 0x10 || stat == 0x11) { 158 set_bit(MBX_INTERRUPT, 159 &ha->mbx_cmd_flags); 160 161 mb0 = RD_REG_WORD(®->mailbox0); 162 mb1 = RD_REG_WORD(®->mailbox1); 163 164 WRT_REG_DWORD(®->hccr, 165 HCCRX_CLR_RISC_INT); 166 RD_REG_DWORD(®->hccr); 167 break; 168 } 169 170 /* Clear this intr; it wasn't a mailbox intr */ 171 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); 172 RD_REG_DWORD(®->hccr); 173 } 174 udelay(5); 175 } 176 ha->flags.mbox_int = 1; 177 178 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 179 rval = mb0 & MBS_MASK; 180 for (idx = 0; idx < dwords; idx++) 181 ram[cnt + idx] = IS_QLA27XX(ha) ? 182 le32_to_cpu(dump[idx]) : swab32(dump[idx]); 183 } else { 184 rval = QLA_FUNCTION_FAILED; 185 } 186 } 187 188 *nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL; 189 return rval; 190 } 191 192 int 193 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, 194 uint32_t ram_dwords, void **nxt) 195 { 196 int rval; 197 uint32_t cnt, stat, timer, dwords, idx; 198 uint16_t mb0; 199 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 200 dma_addr_t dump_dma = ha->gid_list_dma; 201 uint32_t *dump = (uint32_t *)ha->gid_list; 202 203 rval = QLA_SUCCESS; 204 mb0 = 0; 205 206 WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); 207 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 208 209 dwords = qla2x00_gid_list_size(ha) / 4; 210 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; 211 cnt += dwords, addr += dwords) { 212 if (cnt + dwords > ram_dwords) 213 dwords = ram_dwords - cnt; 214 215 WRT_REG_WORD(®->mailbox1, LSW(addr)); 216 WRT_REG_WORD(®->mailbox8, MSW(addr)); 217 218 WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); 219 WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); 220 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); 221 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); 222 223 WRT_REG_WORD(®->mailbox4, MSW(dwords)); 224 WRT_REG_WORD(®->mailbox5, LSW(dwords)); 225 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 226 227 ha->flags.mbox_int = 0; 228 for (timer = 6000000; timer; timer--) { 229 /* Check for pending interrupts. */ 230 stat = RD_REG_DWORD(®->host_status); 231 if (stat & HSRX_RISC_INT) { 232 stat &= 0xff; 233 234 if (stat == 0x1 || stat == 0x2 || 235 stat == 0x10 || stat == 0x11) { 236 set_bit(MBX_INTERRUPT, 237 &ha->mbx_cmd_flags); 238 239 mb0 = RD_REG_WORD(®->mailbox0); 240 241 WRT_REG_DWORD(®->hccr, 242 HCCRX_CLR_RISC_INT); 243 RD_REG_DWORD(®->hccr); 244 break; 245 } 246 247 /* Clear this intr; it wasn't a mailbox intr */ 248 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); 249 RD_REG_DWORD(®->hccr); 250 } 251 udelay(5); 252 } 253 ha->flags.mbox_int = 1; 254 255 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 256 rval = mb0 & MBS_MASK; 257 for (idx = 0; idx < dwords; idx++) 258 ram[cnt + idx] = IS_QLA27XX(ha) ? 259 le32_to_cpu(dump[idx]) : swab32(dump[idx]); 260 } else { 261 rval = QLA_FUNCTION_FAILED; 262 } 263 } 264 265 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; 266 return rval; 267 } 268 269 static int 270 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, 271 uint32_t cram_size, void **nxt) 272 { 273 int rval; 274 275 /* Code RAM. */ 276 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); 277 if (rval != QLA_SUCCESS) 278 return rval; 279 280 /* External Memory. */ 281 return qla24xx_dump_ram(ha, 0x100000, *nxt, 282 ha->fw_memory_size - 0x100000 + 1, nxt); 283 } 284 285 static uint32_t * 286 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, 287 uint32_t count, uint32_t *buf) 288 { 289 uint32_t __iomem *dmp_reg; 290 291 WRT_REG_DWORD(®->iobase_addr, iobase); 292 dmp_reg = ®->iobase_window; 293 while (count--) 294 *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); 295 296 return buf; 297 } 298 299 int 300 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) 301 { 302 int rval = QLA_SUCCESS; 303 uint32_t cnt; 304 305 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); 306 for (cnt = 30000; 307 ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && 308 rval == QLA_SUCCESS; cnt--) { 309 if (cnt) 310 udelay(100); 311 else 312 rval = QLA_FUNCTION_TIMEOUT; 313 } 314 315 return rval; 316 } 317 318 int 319 qla24xx_soft_reset(struct qla_hw_data *ha) 320 { 321 int rval = QLA_SUCCESS; 322 uint32_t cnt; 323 uint16_t mb0, wd; 324 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 325 326 /* Reset RISC. */ 327 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 328 for (cnt = 0; cnt < 30000; cnt++) { 329 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 330 break; 331 332 udelay(10); 333 } 334 335 WRT_REG_DWORD(®->ctrl_status, 336 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 337 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 338 339 udelay(100); 340 /* Wait for firmware to complete NVRAM accesses. */ 341 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); 342 for (cnt = 10000 ; cnt && mb0; cnt--) { 343 udelay(5); 344 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); 345 barrier(); 346 } 347 348 /* Wait for soft-reset to complete. */ 349 for (cnt = 0; cnt < 30000; cnt++) { 350 if ((RD_REG_DWORD(®->ctrl_status) & 351 CSRX_ISP_SOFT_RESET) == 0) 352 break; 353 354 udelay(10); 355 } 356 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 357 RD_REG_DWORD(®->hccr); /* PCI Posting. */ 358 359 for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && 360 rval == QLA_SUCCESS; cnt--) { 361 if (cnt) 362 udelay(100); 363 else 364 rval = QLA_FUNCTION_TIMEOUT; 365 } 366 367 return rval; 368 } 369 370 static int 371 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, 372 uint32_t ram_words, void **nxt) 373 { 374 int rval; 375 uint32_t cnt, stat, timer, words, idx; 376 uint16_t mb0; 377 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 378 dma_addr_t dump_dma = ha->gid_list_dma; 379 uint16_t *dump = (uint16_t *)ha->gid_list; 380 381 rval = QLA_SUCCESS; 382 mb0 = 0; 383 384 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); 385 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 386 387 words = qla2x00_gid_list_size(ha) / 2; 388 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; 389 cnt += words, addr += words) { 390 if (cnt + words > ram_words) 391 words = ram_words - cnt; 392 393 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); 394 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); 395 396 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); 397 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); 398 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); 399 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); 400 401 WRT_MAILBOX_REG(ha, reg, 4, words); 402 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 403 404 for (timer = 6000000; timer; timer--) { 405 /* Check for pending interrupts. */ 406 stat = RD_REG_DWORD(®->u.isp2300.host_status); 407 if (stat & HSR_RISC_INT) { 408 stat &= 0xff; 409 410 if (stat == 0x1 || stat == 0x2) { 411 set_bit(MBX_INTERRUPT, 412 &ha->mbx_cmd_flags); 413 414 mb0 = RD_MAILBOX_REG(ha, reg, 0); 415 416 /* Release mailbox registers. */ 417 WRT_REG_WORD(®->semaphore, 0); 418 WRT_REG_WORD(®->hccr, 419 HCCR_CLR_RISC_INT); 420 RD_REG_WORD(®->hccr); 421 break; 422 } else if (stat == 0x10 || stat == 0x11) { 423 set_bit(MBX_INTERRUPT, 424 &ha->mbx_cmd_flags); 425 426 mb0 = RD_MAILBOX_REG(ha, reg, 0); 427 428 WRT_REG_WORD(®->hccr, 429 HCCR_CLR_RISC_INT); 430 RD_REG_WORD(®->hccr); 431 break; 432 } 433 434 /* clear this intr; it wasn't a mailbox intr */ 435 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 436 RD_REG_WORD(®->hccr); 437 } 438 udelay(5); 439 } 440 441 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 442 rval = mb0 & MBS_MASK; 443 for (idx = 0; idx < words; idx++) 444 ram[cnt + idx] = swab16(dump[idx]); 445 } else { 446 rval = QLA_FUNCTION_FAILED; 447 } 448 } 449 450 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; 451 return rval; 452 } 453 454 static inline void 455 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, 456 uint16_t *buf) 457 { 458 uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; 459 460 while (count--) 461 *buf++ = htons(RD_REG_WORD(dmp_reg++)); 462 } 463 464 static inline void * 465 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) 466 { 467 if (!ha->eft) 468 return ptr; 469 470 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); 471 return ptr + ntohl(ha->fw_dump->eft_size); 472 } 473 474 static inline void * 475 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 476 { 477 uint32_t cnt; 478 uint32_t *iter_reg; 479 struct qla2xxx_fce_chain *fcec = ptr; 480 481 if (!ha->fce) 482 return ptr; 483 484 *last_chain = &fcec->type; 485 fcec->type = __constant_htonl(DUMP_CHAIN_FCE); 486 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + 487 fce_calc_size(ha->fce_bufs)); 488 fcec->size = htonl(fce_calc_size(ha->fce_bufs)); 489 fcec->addr_l = htonl(LSD(ha->fce_dma)); 490 fcec->addr_h = htonl(MSD(ha->fce_dma)); 491 492 iter_reg = fcec->eregs; 493 for (cnt = 0; cnt < 8; cnt++) 494 *iter_reg++ = htonl(ha->fce_mb[cnt]); 495 496 memcpy(iter_reg, ha->fce, ntohl(fcec->size)); 497 498 return (char *)iter_reg + ntohl(fcec->size); 499 } 500 501 static inline void * 502 qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr, 503 uint32_t **last_chain) 504 { 505 struct qla2xxx_mqueue_chain *q; 506 struct qla2xxx_mqueue_header *qh; 507 uint32_t num_queues; 508 int que; 509 struct { 510 int length; 511 void *ring; 512 } aq, *aqp; 513 514 if (!ha->tgt.atio_ring) 515 return ptr; 516 517 num_queues = 1; 518 aqp = &aq; 519 aqp->length = ha->tgt.atio_q_length; 520 aqp->ring = ha->tgt.atio_ring; 521 522 for (que = 0; que < num_queues; que++) { 523 /* aqp = ha->atio_q_map[que]; */ 524 q = ptr; 525 *last_chain = &q->type; 526 q->type = __constant_htonl(DUMP_CHAIN_QUEUE); 527 q->chain_size = htonl( 528 sizeof(struct qla2xxx_mqueue_chain) + 529 sizeof(struct qla2xxx_mqueue_header) + 530 (aqp->length * sizeof(request_t))); 531 ptr += sizeof(struct qla2xxx_mqueue_chain); 532 533 /* Add header. */ 534 qh = ptr; 535 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE); 536 qh->number = htonl(que); 537 qh->size = htonl(aqp->length * sizeof(request_t)); 538 ptr += sizeof(struct qla2xxx_mqueue_header); 539 540 /* Add data. */ 541 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t)); 542 543 ptr += aqp->length * sizeof(request_t); 544 } 545 546 return ptr; 547 } 548 549 static inline void * 550 qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 551 { 552 struct qla2xxx_mqueue_chain *q; 553 struct qla2xxx_mqueue_header *qh; 554 struct req_que *req; 555 struct rsp_que *rsp; 556 int que; 557 558 if (!ha->mqenable) 559 return ptr; 560 561 /* Request queues */ 562 for (que = 1; que < ha->max_req_queues; que++) { 563 req = ha->req_q_map[que]; 564 if (!req) 565 break; 566 567 /* Add chain. */ 568 q = ptr; 569 *last_chain = &q->type; 570 q->type = __constant_htonl(DUMP_CHAIN_QUEUE); 571 q->chain_size = htonl( 572 sizeof(struct qla2xxx_mqueue_chain) + 573 sizeof(struct qla2xxx_mqueue_header) + 574 (req->length * sizeof(request_t))); 575 ptr += sizeof(struct qla2xxx_mqueue_chain); 576 577 /* Add header. */ 578 qh = ptr; 579 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE); 580 qh->number = htonl(que); 581 qh->size = htonl(req->length * sizeof(request_t)); 582 ptr += sizeof(struct qla2xxx_mqueue_header); 583 584 /* Add data. */ 585 memcpy(ptr, req->ring, req->length * sizeof(request_t)); 586 ptr += req->length * sizeof(request_t); 587 } 588 589 /* Response queues */ 590 for (que = 1; que < ha->max_rsp_queues; que++) { 591 rsp = ha->rsp_q_map[que]; 592 if (!rsp) 593 break; 594 595 /* Add chain. */ 596 q = ptr; 597 *last_chain = &q->type; 598 q->type = __constant_htonl(DUMP_CHAIN_QUEUE); 599 q->chain_size = htonl( 600 sizeof(struct qla2xxx_mqueue_chain) + 601 sizeof(struct qla2xxx_mqueue_header) + 602 (rsp->length * sizeof(response_t))); 603 ptr += sizeof(struct qla2xxx_mqueue_chain); 604 605 /* Add header. */ 606 qh = ptr; 607 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE); 608 qh->number = htonl(que); 609 qh->size = htonl(rsp->length * sizeof(response_t)); 610 ptr += sizeof(struct qla2xxx_mqueue_header); 611 612 /* Add data. */ 613 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t)); 614 ptr += rsp->length * sizeof(response_t); 615 } 616 617 return ptr; 618 } 619 620 static inline void * 621 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 622 { 623 uint32_t cnt, que_idx; 624 uint8_t que_cnt; 625 struct qla2xxx_mq_chain *mq = ptr; 626 device_reg_t __iomem *reg; 627 628 if (!ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 629 return ptr; 630 631 mq = ptr; 632 *last_chain = &mq->type; 633 mq->type = __constant_htonl(DUMP_CHAIN_MQ); 634 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain)); 635 636 que_cnt = ha->max_req_queues > ha->max_rsp_queues ? 637 ha->max_req_queues : ha->max_rsp_queues; 638 mq->count = htonl(que_cnt); 639 for (cnt = 0; cnt < que_cnt; cnt++) { 640 reg = ISP_QUE_REG(ha, cnt); 641 que_idx = cnt * 4; 642 mq->qregs[que_idx] = 643 htonl(RD_REG_DWORD(®->isp25mq.req_q_in)); 644 mq->qregs[que_idx+1] = 645 htonl(RD_REG_DWORD(®->isp25mq.req_q_out)); 646 mq->qregs[que_idx+2] = 647 htonl(RD_REG_DWORD(®->isp25mq.rsp_q_in)); 648 mq->qregs[que_idx+3] = 649 htonl(RD_REG_DWORD(®->isp25mq.rsp_q_out)); 650 } 651 652 return ptr + sizeof(struct qla2xxx_mq_chain); 653 } 654 655 void 656 qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) 657 { 658 struct qla_hw_data *ha = vha->hw; 659 660 if (rval != QLA_SUCCESS) { 661 ql_log(ql_log_warn, vha, 0xd000, 662 "Failed to dump firmware (%x).\n", rval); 663 ha->fw_dumped = 0; 664 } else { 665 ql_log(ql_log_info, vha, 0xd001, 666 "Firmware dump saved to temp buffer (%ld/%p).\n", 667 vha->host_no, ha->fw_dump); 668 ha->fw_dumped = 1; 669 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 670 } 671 } 672 673 /** 674 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 675 * @ha: HA context 676 * @hardware_locked: Called with the hardware_lock 677 */ 678 void 679 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 680 { 681 int rval; 682 uint32_t cnt; 683 struct qla_hw_data *ha = vha->hw; 684 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 685 uint16_t __iomem *dmp_reg; 686 unsigned long flags; 687 struct qla2300_fw_dump *fw; 688 void *nxt; 689 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 690 691 flags = 0; 692 693 if (!hardware_locked) 694 spin_lock_irqsave(&ha->hardware_lock, flags); 695 696 if (!ha->fw_dump) { 697 ql_log(ql_log_warn, vha, 0xd002, 698 "No buffer available for dump.\n"); 699 goto qla2300_fw_dump_failed; 700 } 701 702 if (ha->fw_dumped) { 703 ql_log(ql_log_warn, vha, 0xd003, 704 "Firmware has been previously dumped (%p) " 705 "-- ignoring request.\n", 706 ha->fw_dump); 707 goto qla2300_fw_dump_failed; 708 } 709 fw = &ha->fw_dump->isp.isp23; 710 qla2xxx_prep_dump(ha, ha->fw_dump); 711 712 rval = QLA_SUCCESS; 713 fw->hccr = htons(RD_REG_WORD(®->hccr)); 714 715 /* Pause RISC. */ 716 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 717 if (IS_QLA2300(ha)) { 718 for (cnt = 30000; 719 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 720 rval == QLA_SUCCESS; cnt--) { 721 if (cnt) 722 udelay(100); 723 else 724 rval = QLA_FUNCTION_TIMEOUT; 725 } 726 } else { 727 RD_REG_WORD(®->hccr); /* PCI Posting. */ 728 udelay(10); 729 } 730 731 if (rval == QLA_SUCCESS) { 732 dmp_reg = ®->flash_address; 733 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 734 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 735 736 dmp_reg = ®->u.isp2300.req_q_in; 737 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) 738 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 739 740 dmp_reg = ®->u.isp2300.mailbox0; 741 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 742 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 743 744 WRT_REG_WORD(®->ctrl_status, 0x40); 745 qla2xxx_read_window(reg, 32, fw->resp_dma_reg); 746 747 WRT_REG_WORD(®->ctrl_status, 0x50); 748 qla2xxx_read_window(reg, 48, fw->dma_reg); 749 750 WRT_REG_WORD(®->ctrl_status, 0x00); 751 dmp_reg = ®->risc_hw; 752 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 753 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 754 755 WRT_REG_WORD(®->pcr, 0x2000); 756 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 757 758 WRT_REG_WORD(®->pcr, 0x2200); 759 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 760 761 WRT_REG_WORD(®->pcr, 0x2400); 762 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 763 764 WRT_REG_WORD(®->pcr, 0x2600); 765 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 766 767 WRT_REG_WORD(®->pcr, 0x2800); 768 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 769 770 WRT_REG_WORD(®->pcr, 0x2A00); 771 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 772 773 WRT_REG_WORD(®->pcr, 0x2C00); 774 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 775 776 WRT_REG_WORD(®->pcr, 0x2E00); 777 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 778 779 WRT_REG_WORD(®->ctrl_status, 0x10); 780 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); 781 782 WRT_REG_WORD(®->ctrl_status, 0x20); 783 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 784 785 WRT_REG_WORD(®->ctrl_status, 0x30); 786 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 787 788 /* Reset RISC. */ 789 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 790 for (cnt = 0; cnt < 30000; cnt++) { 791 if ((RD_REG_WORD(®->ctrl_status) & 792 CSR_ISP_SOFT_RESET) == 0) 793 break; 794 795 udelay(10); 796 } 797 } 798 799 if (!IS_QLA2300(ha)) { 800 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 801 rval == QLA_SUCCESS; cnt--) { 802 if (cnt) 803 udelay(100); 804 else 805 rval = QLA_FUNCTION_TIMEOUT; 806 } 807 } 808 809 /* Get RISC SRAM. */ 810 if (rval == QLA_SUCCESS) 811 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, 812 sizeof(fw->risc_ram) / 2, &nxt); 813 814 /* Get stack SRAM. */ 815 if (rval == QLA_SUCCESS) 816 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, 817 sizeof(fw->stack_ram) / 2, &nxt); 818 819 /* Get data SRAM. */ 820 if (rval == QLA_SUCCESS) 821 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, 822 ha->fw_memory_size - 0x11000 + 1, &nxt); 823 824 if (rval == QLA_SUCCESS) 825 qla2xxx_copy_queues(ha, nxt); 826 827 qla2xxx_dump_post_process(base_vha, rval); 828 829 qla2300_fw_dump_failed: 830 if (!hardware_locked) 831 spin_unlock_irqrestore(&ha->hardware_lock, flags); 832 } 833 834 /** 835 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. 836 * @ha: HA context 837 * @hardware_locked: Called with the hardware_lock 838 */ 839 void 840 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 841 { 842 int rval; 843 uint32_t cnt, timer; 844 uint16_t risc_address; 845 uint16_t mb0, mb2; 846 struct qla_hw_data *ha = vha->hw; 847 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 848 uint16_t __iomem *dmp_reg; 849 unsigned long flags; 850 struct qla2100_fw_dump *fw; 851 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 852 853 risc_address = 0; 854 mb0 = mb2 = 0; 855 flags = 0; 856 857 if (!hardware_locked) 858 spin_lock_irqsave(&ha->hardware_lock, flags); 859 860 if (!ha->fw_dump) { 861 ql_log(ql_log_warn, vha, 0xd004, 862 "No buffer available for dump.\n"); 863 goto qla2100_fw_dump_failed; 864 } 865 866 if (ha->fw_dumped) { 867 ql_log(ql_log_warn, vha, 0xd005, 868 "Firmware has been previously dumped (%p) " 869 "-- ignoring request.\n", 870 ha->fw_dump); 871 goto qla2100_fw_dump_failed; 872 } 873 fw = &ha->fw_dump->isp.isp21; 874 qla2xxx_prep_dump(ha, ha->fw_dump); 875 876 rval = QLA_SUCCESS; 877 fw->hccr = htons(RD_REG_WORD(®->hccr)); 878 879 /* Pause RISC. */ 880 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 881 for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 882 rval == QLA_SUCCESS; cnt--) { 883 if (cnt) 884 udelay(100); 885 else 886 rval = QLA_FUNCTION_TIMEOUT; 887 } 888 if (rval == QLA_SUCCESS) { 889 dmp_reg = ®->flash_address; 890 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 891 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 892 893 dmp_reg = ®->u.isp2100.mailbox0; 894 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 895 if (cnt == 8) 896 dmp_reg = ®->u_end.isp2200.mailbox8; 897 898 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 899 } 900 901 dmp_reg = ®->u.isp2100.unused_2[0]; 902 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 903 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 904 905 WRT_REG_WORD(®->ctrl_status, 0x00); 906 dmp_reg = ®->risc_hw; 907 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 908 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 909 910 WRT_REG_WORD(®->pcr, 0x2000); 911 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 912 913 WRT_REG_WORD(®->pcr, 0x2100); 914 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 915 916 WRT_REG_WORD(®->pcr, 0x2200); 917 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 918 919 WRT_REG_WORD(®->pcr, 0x2300); 920 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 921 922 WRT_REG_WORD(®->pcr, 0x2400); 923 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 924 925 WRT_REG_WORD(®->pcr, 0x2500); 926 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 927 928 WRT_REG_WORD(®->pcr, 0x2600); 929 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 930 931 WRT_REG_WORD(®->pcr, 0x2700); 932 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 933 934 WRT_REG_WORD(®->ctrl_status, 0x10); 935 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); 936 937 WRT_REG_WORD(®->ctrl_status, 0x20); 938 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 939 940 WRT_REG_WORD(®->ctrl_status, 0x30); 941 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 942 943 /* Reset the ISP. */ 944 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 945 } 946 947 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 948 rval == QLA_SUCCESS; cnt--) { 949 if (cnt) 950 udelay(100); 951 else 952 rval = QLA_FUNCTION_TIMEOUT; 953 } 954 955 /* Pause RISC. */ 956 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && 957 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { 958 959 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 960 for (cnt = 30000; 961 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 962 rval == QLA_SUCCESS; cnt--) { 963 if (cnt) 964 udelay(100); 965 else 966 rval = QLA_FUNCTION_TIMEOUT; 967 } 968 if (rval == QLA_SUCCESS) { 969 /* Set memory configuration and timing. */ 970 if (IS_QLA2100(ha)) 971 WRT_REG_WORD(®->mctr, 0xf1); 972 else 973 WRT_REG_WORD(®->mctr, 0xf2); 974 RD_REG_WORD(®->mctr); /* PCI Posting. */ 975 976 /* Release RISC. */ 977 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 978 } 979 } 980 981 if (rval == QLA_SUCCESS) { 982 /* Get RISC SRAM. */ 983 risc_address = 0x1000; 984 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); 985 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 986 } 987 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; 988 cnt++, risc_address++) { 989 WRT_MAILBOX_REG(ha, reg, 1, risc_address); 990 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 991 992 for (timer = 6000000; timer != 0; timer--) { 993 /* Check for pending interrupts. */ 994 if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { 995 if (RD_REG_WORD(®->semaphore) & BIT_0) { 996 set_bit(MBX_INTERRUPT, 997 &ha->mbx_cmd_flags); 998 999 mb0 = RD_MAILBOX_REG(ha, reg, 0); 1000 mb2 = RD_MAILBOX_REG(ha, reg, 2); 1001 1002 WRT_REG_WORD(®->semaphore, 0); 1003 WRT_REG_WORD(®->hccr, 1004 HCCR_CLR_RISC_INT); 1005 RD_REG_WORD(®->hccr); 1006 break; 1007 } 1008 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 1009 RD_REG_WORD(®->hccr); 1010 } 1011 udelay(5); 1012 } 1013 1014 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1015 rval = mb0 & MBS_MASK; 1016 fw->risc_ram[cnt] = htons(mb2); 1017 } else { 1018 rval = QLA_FUNCTION_FAILED; 1019 } 1020 } 1021 1022 if (rval == QLA_SUCCESS) 1023 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); 1024 1025 qla2xxx_dump_post_process(base_vha, rval); 1026 1027 qla2100_fw_dump_failed: 1028 if (!hardware_locked) 1029 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1030 } 1031 1032 void 1033 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1034 { 1035 int rval; 1036 uint32_t cnt; 1037 uint32_t risc_address; 1038 struct qla_hw_data *ha = vha->hw; 1039 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1040 uint32_t __iomem *dmp_reg; 1041 uint32_t *iter_reg; 1042 uint16_t __iomem *mbx_reg; 1043 unsigned long flags; 1044 struct qla24xx_fw_dump *fw; 1045 uint32_t ext_mem_cnt; 1046 void *nxt; 1047 void *nxt_chain; 1048 uint32_t *last_chain = NULL; 1049 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1050 1051 if (IS_P3P_TYPE(ha)) 1052 return; 1053 1054 risc_address = ext_mem_cnt = 0; 1055 flags = 0; 1056 1057 if (!hardware_locked) 1058 spin_lock_irqsave(&ha->hardware_lock, flags); 1059 1060 if (!ha->fw_dump) { 1061 ql_log(ql_log_warn, vha, 0xd006, 1062 "No buffer available for dump.\n"); 1063 goto qla24xx_fw_dump_failed; 1064 } 1065 1066 if (ha->fw_dumped) { 1067 ql_log(ql_log_warn, vha, 0xd007, 1068 "Firmware has been previously dumped (%p) " 1069 "-- ignoring request.\n", 1070 ha->fw_dump); 1071 goto qla24xx_fw_dump_failed; 1072 } 1073 fw = &ha->fw_dump->isp.isp24; 1074 qla2xxx_prep_dump(ha, ha->fw_dump); 1075 1076 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1077 1078 /* Pause RISC. */ 1079 rval = qla24xx_pause_risc(reg); 1080 if (rval != QLA_SUCCESS) 1081 goto qla24xx_fw_dump_failed_0; 1082 1083 /* Host interface registers. */ 1084 dmp_reg = ®->flash_addr; 1085 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1086 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1087 1088 /* Disable interrupts. */ 1089 WRT_REG_DWORD(®->ictrl, 0); 1090 RD_REG_DWORD(®->ictrl); 1091 1092 /* Shadow registers. */ 1093 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1094 RD_REG_DWORD(®->iobase_addr); 1095 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1096 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1097 1098 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1099 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1100 1101 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1102 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1103 1104 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1105 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1106 1107 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1108 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1109 1110 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1111 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1112 1113 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1114 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1115 1116 /* Mailbox registers. */ 1117 mbx_reg = ®->mailbox0; 1118 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1119 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1120 1121 /* Transfer sequence registers. */ 1122 iter_reg = fw->xseq_gp_reg; 1123 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1124 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1125 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1126 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1127 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1128 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1129 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1130 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1131 1132 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); 1133 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1134 1135 /* Receive sequence registers. */ 1136 iter_reg = fw->rseq_gp_reg; 1137 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1138 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1139 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1140 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1141 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1142 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1143 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1144 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1145 1146 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); 1147 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1148 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1149 1150 /* Command DMA registers. */ 1151 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1152 1153 /* Queues. */ 1154 iter_reg = fw->req0_dma_reg; 1155 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1156 dmp_reg = ®->iobase_q; 1157 for (cnt = 0; cnt < 7; cnt++) 1158 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1159 1160 iter_reg = fw->resp0_dma_reg; 1161 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1162 dmp_reg = ®->iobase_q; 1163 for (cnt = 0; cnt < 7; cnt++) 1164 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1165 1166 iter_reg = fw->req1_dma_reg; 1167 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1168 dmp_reg = ®->iobase_q; 1169 for (cnt = 0; cnt < 7; cnt++) 1170 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1171 1172 /* Transmit DMA registers. */ 1173 iter_reg = fw->xmt0_dma_reg; 1174 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1175 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1176 1177 iter_reg = fw->xmt1_dma_reg; 1178 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1179 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1180 1181 iter_reg = fw->xmt2_dma_reg; 1182 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1183 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1184 1185 iter_reg = fw->xmt3_dma_reg; 1186 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1187 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1188 1189 iter_reg = fw->xmt4_dma_reg; 1190 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1191 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1192 1193 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1194 1195 /* Receive DMA registers. */ 1196 iter_reg = fw->rcvt0_data_dma_reg; 1197 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1198 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1199 1200 iter_reg = fw->rcvt1_data_dma_reg; 1201 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1202 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1203 1204 /* RISC registers. */ 1205 iter_reg = fw->risc_gp_reg; 1206 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1207 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1208 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1209 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1210 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1211 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1212 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1213 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1214 1215 /* Local memory controller registers. */ 1216 iter_reg = fw->lmc_reg; 1217 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1218 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1219 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1220 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1221 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1222 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1223 qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1224 1225 /* Fibre Protocol Module registers. */ 1226 iter_reg = fw->fpm_hdw_reg; 1227 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1228 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1229 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1230 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1231 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1232 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1233 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1234 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1235 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1236 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1237 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1238 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1239 1240 /* Frame Buffer registers. */ 1241 iter_reg = fw->fb_hdw_reg; 1242 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1243 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1244 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1245 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1246 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1247 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1248 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1249 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1250 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1251 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1252 qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1253 1254 rval = qla24xx_soft_reset(ha); 1255 if (rval != QLA_SUCCESS) 1256 goto qla24xx_fw_dump_failed_0; 1257 1258 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1259 &nxt); 1260 if (rval != QLA_SUCCESS) 1261 goto qla24xx_fw_dump_failed_0; 1262 1263 nxt = qla2xxx_copy_queues(ha, nxt); 1264 1265 qla24xx_copy_eft(ha, nxt); 1266 1267 nxt_chain = (void *)ha->fw_dump + ha->chain_offset; 1268 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1269 if (last_chain) { 1270 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 1271 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 1272 } 1273 1274 /* Adjust valid length. */ 1275 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1276 1277 qla24xx_fw_dump_failed_0: 1278 qla2xxx_dump_post_process(base_vha, rval); 1279 1280 qla24xx_fw_dump_failed: 1281 if (!hardware_locked) 1282 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1283 } 1284 1285 void 1286 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1287 { 1288 int rval; 1289 uint32_t cnt; 1290 uint32_t risc_address; 1291 struct qla_hw_data *ha = vha->hw; 1292 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1293 uint32_t __iomem *dmp_reg; 1294 uint32_t *iter_reg; 1295 uint16_t __iomem *mbx_reg; 1296 unsigned long flags; 1297 struct qla25xx_fw_dump *fw; 1298 uint32_t ext_mem_cnt; 1299 void *nxt, *nxt_chain; 1300 uint32_t *last_chain = NULL; 1301 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1302 1303 risc_address = ext_mem_cnt = 0; 1304 flags = 0; 1305 1306 if (!hardware_locked) 1307 spin_lock_irqsave(&ha->hardware_lock, flags); 1308 1309 if (!ha->fw_dump) { 1310 ql_log(ql_log_warn, vha, 0xd008, 1311 "No buffer available for dump.\n"); 1312 goto qla25xx_fw_dump_failed; 1313 } 1314 1315 if (ha->fw_dumped) { 1316 ql_log(ql_log_warn, vha, 0xd009, 1317 "Firmware has been previously dumped (%p) " 1318 "-- ignoring request.\n", 1319 ha->fw_dump); 1320 goto qla25xx_fw_dump_failed; 1321 } 1322 fw = &ha->fw_dump->isp.isp25; 1323 qla2xxx_prep_dump(ha, ha->fw_dump); 1324 ha->fw_dump->version = __constant_htonl(2); 1325 1326 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1327 1328 /* Pause RISC. */ 1329 rval = qla24xx_pause_risc(reg); 1330 if (rval != QLA_SUCCESS) 1331 goto qla25xx_fw_dump_failed_0; 1332 1333 /* Host/Risc registers. */ 1334 iter_reg = fw->host_risc_reg; 1335 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1336 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1337 1338 /* PCIe registers. */ 1339 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1340 RD_REG_DWORD(®->iobase_addr); 1341 WRT_REG_DWORD(®->iobase_window, 0x01); 1342 dmp_reg = ®->iobase_c4; 1343 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1344 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1345 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1346 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1347 1348 WRT_REG_DWORD(®->iobase_window, 0x00); 1349 RD_REG_DWORD(®->iobase_window); 1350 1351 /* Host interface registers. */ 1352 dmp_reg = ®->flash_addr; 1353 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1354 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1355 1356 /* Disable interrupts. */ 1357 WRT_REG_DWORD(®->ictrl, 0); 1358 RD_REG_DWORD(®->ictrl); 1359 1360 /* Shadow registers. */ 1361 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1362 RD_REG_DWORD(®->iobase_addr); 1363 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1364 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1365 1366 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1367 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1368 1369 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1370 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1371 1372 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1373 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1374 1375 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1376 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1377 1378 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1379 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1380 1381 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1382 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1383 1384 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1385 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1386 1387 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1388 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1389 1390 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1391 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1392 1393 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1394 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1395 1396 /* RISC I/O register. */ 1397 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1398 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1399 1400 /* Mailbox registers. */ 1401 mbx_reg = ®->mailbox0; 1402 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1403 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1404 1405 /* Transfer sequence registers. */ 1406 iter_reg = fw->xseq_gp_reg; 1407 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1408 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1409 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1410 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1411 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1412 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1413 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1414 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1415 1416 iter_reg = fw->xseq_0_reg; 1417 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1418 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1419 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1420 1421 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1422 1423 /* Receive sequence registers. */ 1424 iter_reg = fw->rseq_gp_reg; 1425 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1426 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1427 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1428 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1429 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1430 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1431 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1432 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1433 1434 iter_reg = fw->rseq_0_reg; 1435 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1436 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1437 1438 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1439 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1440 1441 /* Auxiliary sequence registers. */ 1442 iter_reg = fw->aseq_gp_reg; 1443 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1444 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1445 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1446 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1447 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1448 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1449 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1450 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1451 1452 iter_reg = fw->aseq_0_reg; 1453 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1454 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1455 1456 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1457 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1458 1459 /* Command DMA registers. */ 1460 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1461 1462 /* Queues. */ 1463 iter_reg = fw->req0_dma_reg; 1464 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1465 dmp_reg = ®->iobase_q; 1466 for (cnt = 0; cnt < 7; cnt++) 1467 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1468 1469 iter_reg = fw->resp0_dma_reg; 1470 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1471 dmp_reg = ®->iobase_q; 1472 for (cnt = 0; cnt < 7; cnt++) 1473 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1474 1475 iter_reg = fw->req1_dma_reg; 1476 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1477 dmp_reg = ®->iobase_q; 1478 for (cnt = 0; cnt < 7; cnt++) 1479 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1480 1481 /* Transmit DMA registers. */ 1482 iter_reg = fw->xmt0_dma_reg; 1483 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1484 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1485 1486 iter_reg = fw->xmt1_dma_reg; 1487 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1488 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1489 1490 iter_reg = fw->xmt2_dma_reg; 1491 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1492 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1493 1494 iter_reg = fw->xmt3_dma_reg; 1495 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1496 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1497 1498 iter_reg = fw->xmt4_dma_reg; 1499 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1500 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1501 1502 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1503 1504 /* Receive DMA registers. */ 1505 iter_reg = fw->rcvt0_data_dma_reg; 1506 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1507 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1508 1509 iter_reg = fw->rcvt1_data_dma_reg; 1510 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1511 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1512 1513 /* RISC registers. */ 1514 iter_reg = fw->risc_gp_reg; 1515 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1516 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1517 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1518 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1519 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1520 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1521 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1522 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1523 1524 /* Local memory controller registers. */ 1525 iter_reg = fw->lmc_reg; 1526 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1527 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1528 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1529 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1530 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1531 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1532 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1533 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1534 1535 /* Fibre Protocol Module registers. */ 1536 iter_reg = fw->fpm_hdw_reg; 1537 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1538 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1539 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1540 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1541 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1542 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1543 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1544 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1545 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1546 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1547 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1548 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1549 1550 /* Frame Buffer registers. */ 1551 iter_reg = fw->fb_hdw_reg; 1552 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1553 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1554 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1555 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1556 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1557 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1558 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1559 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1560 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1561 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1562 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1563 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1564 1565 /* Multi queue registers */ 1566 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1567 &last_chain); 1568 1569 rval = qla24xx_soft_reset(ha); 1570 if (rval != QLA_SUCCESS) 1571 goto qla25xx_fw_dump_failed_0; 1572 1573 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1574 &nxt); 1575 if (rval != QLA_SUCCESS) 1576 goto qla25xx_fw_dump_failed_0; 1577 1578 nxt = qla2xxx_copy_queues(ha, nxt); 1579 1580 qla24xx_copy_eft(ha, nxt); 1581 1582 /* Chain entries -- started with MQ. */ 1583 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1584 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 1585 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1586 if (last_chain) { 1587 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 1588 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 1589 } 1590 1591 /* Adjust valid length. */ 1592 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1593 1594 qla25xx_fw_dump_failed_0: 1595 qla2xxx_dump_post_process(base_vha, rval); 1596 1597 qla25xx_fw_dump_failed: 1598 if (!hardware_locked) 1599 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1600 } 1601 1602 void 1603 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1604 { 1605 int rval; 1606 uint32_t cnt; 1607 uint32_t risc_address; 1608 struct qla_hw_data *ha = vha->hw; 1609 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1610 uint32_t __iomem *dmp_reg; 1611 uint32_t *iter_reg; 1612 uint16_t __iomem *mbx_reg; 1613 unsigned long flags; 1614 struct qla81xx_fw_dump *fw; 1615 uint32_t ext_mem_cnt; 1616 void *nxt, *nxt_chain; 1617 uint32_t *last_chain = NULL; 1618 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1619 1620 risc_address = ext_mem_cnt = 0; 1621 flags = 0; 1622 1623 if (!hardware_locked) 1624 spin_lock_irqsave(&ha->hardware_lock, flags); 1625 1626 if (!ha->fw_dump) { 1627 ql_log(ql_log_warn, vha, 0xd00a, 1628 "No buffer available for dump.\n"); 1629 goto qla81xx_fw_dump_failed; 1630 } 1631 1632 if (ha->fw_dumped) { 1633 ql_log(ql_log_warn, vha, 0xd00b, 1634 "Firmware has been previously dumped (%p) " 1635 "-- ignoring request.\n", 1636 ha->fw_dump); 1637 goto qla81xx_fw_dump_failed; 1638 } 1639 fw = &ha->fw_dump->isp.isp81; 1640 qla2xxx_prep_dump(ha, ha->fw_dump); 1641 1642 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1643 1644 /* Pause RISC. */ 1645 rval = qla24xx_pause_risc(reg); 1646 if (rval != QLA_SUCCESS) 1647 goto qla81xx_fw_dump_failed_0; 1648 1649 /* Host/Risc registers. */ 1650 iter_reg = fw->host_risc_reg; 1651 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1652 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1653 1654 /* PCIe registers. */ 1655 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1656 RD_REG_DWORD(®->iobase_addr); 1657 WRT_REG_DWORD(®->iobase_window, 0x01); 1658 dmp_reg = ®->iobase_c4; 1659 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1660 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1661 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1662 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1663 1664 WRT_REG_DWORD(®->iobase_window, 0x00); 1665 RD_REG_DWORD(®->iobase_window); 1666 1667 /* Host interface registers. */ 1668 dmp_reg = ®->flash_addr; 1669 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1670 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1671 1672 /* Disable interrupts. */ 1673 WRT_REG_DWORD(®->ictrl, 0); 1674 RD_REG_DWORD(®->ictrl); 1675 1676 /* Shadow registers. */ 1677 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1678 RD_REG_DWORD(®->iobase_addr); 1679 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1680 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1681 1682 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1683 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1684 1685 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1686 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1687 1688 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1689 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1690 1691 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1692 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1693 1694 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1695 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1696 1697 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1698 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1699 1700 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1701 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1702 1703 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1704 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1705 1706 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1707 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1708 1709 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1710 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1711 1712 /* RISC I/O register. */ 1713 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1714 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1715 1716 /* Mailbox registers. */ 1717 mbx_reg = ®->mailbox0; 1718 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1719 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1720 1721 /* Transfer sequence registers. */ 1722 iter_reg = fw->xseq_gp_reg; 1723 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1724 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1725 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1726 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1727 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1728 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1729 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1730 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1731 1732 iter_reg = fw->xseq_0_reg; 1733 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1734 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1735 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1736 1737 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1738 1739 /* Receive sequence registers. */ 1740 iter_reg = fw->rseq_gp_reg; 1741 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1742 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1743 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1744 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1745 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1746 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1747 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1748 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1749 1750 iter_reg = fw->rseq_0_reg; 1751 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1752 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1753 1754 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1755 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1756 1757 /* Auxiliary sequence registers. */ 1758 iter_reg = fw->aseq_gp_reg; 1759 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1760 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1761 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1762 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1763 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1764 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1765 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1766 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1767 1768 iter_reg = fw->aseq_0_reg; 1769 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1770 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1771 1772 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1773 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1774 1775 /* Command DMA registers. */ 1776 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1777 1778 /* Queues. */ 1779 iter_reg = fw->req0_dma_reg; 1780 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1781 dmp_reg = ®->iobase_q; 1782 for (cnt = 0; cnt < 7; cnt++) 1783 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1784 1785 iter_reg = fw->resp0_dma_reg; 1786 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1787 dmp_reg = ®->iobase_q; 1788 for (cnt = 0; cnt < 7; cnt++) 1789 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1790 1791 iter_reg = fw->req1_dma_reg; 1792 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1793 dmp_reg = ®->iobase_q; 1794 for (cnt = 0; cnt < 7; cnt++) 1795 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1796 1797 /* Transmit DMA registers. */ 1798 iter_reg = fw->xmt0_dma_reg; 1799 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1800 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1801 1802 iter_reg = fw->xmt1_dma_reg; 1803 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1804 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1805 1806 iter_reg = fw->xmt2_dma_reg; 1807 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1808 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1809 1810 iter_reg = fw->xmt3_dma_reg; 1811 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1812 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1813 1814 iter_reg = fw->xmt4_dma_reg; 1815 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1816 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1817 1818 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1819 1820 /* Receive DMA registers. */ 1821 iter_reg = fw->rcvt0_data_dma_reg; 1822 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1823 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1824 1825 iter_reg = fw->rcvt1_data_dma_reg; 1826 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1827 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1828 1829 /* RISC registers. */ 1830 iter_reg = fw->risc_gp_reg; 1831 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1832 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1833 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1834 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1835 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1836 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1837 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1838 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1839 1840 /* Local memory controller registers. */ 1841 iter_reg = fw->lmc_reg; 1842 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1843 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1844 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1845 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1846 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1847 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1848 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1849 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1850 1851 /* Fibre Protocol Module registers. */ 1852 iter_reg = fw->fpm_hdw_reg; 1853 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1854 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1855 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1856 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1857 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1858 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1859 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1860 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1861 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1862 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1863 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1864 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1865 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); 1866 qla24xx_read_window(reg, 0x40D0, 16, iter_reg); 1867 1868 /* Frame Buffer registers. */ 1869 iter_reg = fw->fb_hdw_reg; 1870 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1871 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1872 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1873 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1874 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1875 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1876 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1877 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1878 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1879 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1880 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1881 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); 1882 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1883 1884 /* Multi queue registers */ 1885 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1886 &last_chain); 1887 1888 rval = qla24xx_soft_reset(ha); 1889 if (rval != QLA_SUCCESS) 1890 goto qla81xx_fw_dump_failed_0; 1891 1892 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1893 &nxt); 1894 if (rval != QLA_SUCCESS) 1895 goto qla81xx_fw_dump_failed_0; 1896 1897 nxt = qla2xxx_copy_queues(ha, nxt); 1898 1899 qla24xx_copy_eft(ha, nxt); 1900 1901 /* Chain entries -- started with MQ. */ 1902 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1903 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 1904 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1905 if (last_chain) { 1906 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 1907 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 1908 } 1909 1910 /* Adjust valid length. */ 1911 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1912 1913 qla81xx_fw_dump_failed_0: 1914 qla2xxx_dump_post_process(base_vha, rval); 1915 1916 qla81xx_fw_dump_failed: 1917 if (!hardware_locked) 1918 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1919 } 1920 1921 void 1922 qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1923 { 1924 int rval; 1925 uint32_t cnt, reg_data; 1926 uint32_t risc_address; 1927 struct qla_hw_data *ha = vha->hw; 1928 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1929 uint32_t __iomem *dmp_reg; 1930 uint32_t *iter_reg; 1931 uint16_t __iomem *mbx_reg; 1932 unsigned long flags; 1933 struct qla83xx_fw_dump *fw; 1934 uint32_t ext_mem_cnt; 1935 void *nxt, *nxt_chain; 1936 uint32_t *last_chain = NULL; 1937 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1938 1939 risc_address = ext_mem_cnt = 0; 1940 flags = 0; 1941 1942 if (!hardware_locked) 1943 spin_lock_irqsave(&ha->hardware_lock, flags); 1944 1945 if (!ha->fw_dump) { 1946 ql_log(ql_log_warn, vha, 0xd00c, 1947 "No buffer available for dump!!!\n"); 1948 goto qla83xx_fw_dump_failed; 1949 } 1950 1951 if (ha->fw_dumped) { 1952 ql_log(ql_log_warn, vha, 0xd00d, 1953 "Firmware has been previously dumped (%p) -- ignoring " 1954 "request...\n", ha->fw_dump); 1955 goto qla83xx_fw_dump_failed; 1956 } 1957 fw = &ha->fw_dump->isp.isp83; 1958 qla2xxx_prep_dump(ha, ha->fw_dump); 1959 1960 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1961 1962 /* Pause RISC. */ 1963 rval = qla24xx_pause_risc(reg); 1964 if (rval != QLA_SUCCESS) 1965 goto qla83xx_fw_dump_failed_0; 1966 1967 WRT_REG_DWORD(®->iobase_addr, 0x6000); 1968 dmp_reg = ®->iobase_window; 1969 reg_data = RD_REG_DWORD(dmp_reg); 1970 WRT_REG_DWORD(dmp_reg, 0); 1971 1972 dmp_reg = ®->unused_4_1[0]; 1973 reg_data = RD_REG_DWORD(dmp_reg); 1974 WRT_REG_DWORD(dmp_reg, 0); 1975 1976 WRT_REG_DWORD(®->iobase_addr, 0x6010); 1977 dmp_reg = ®->unused_4_1[2]; 1978 reg_data = RD_REG_DWORD(dmp_reg); 1979 WRT_REG_DWORD(dmp_reg, 0); 1980 1981 /* select PCR and disable ecc checking and correction */ 1982 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1983 RD_REG_DWORD(®->iobase_addr); 1984 WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */ 1985 1986 /* Host/Risc registers. */ 1987 iter_reg = fw->host_risc_reg; 1988 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1989 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1990 qla24xx_read_window(reg, 0x7040, 16, iter_reg); 1991 1992 /* PCIe registers. */ 1993 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1994 RD_REG_DWORD(®->iobase_addr); 1995 WRT_REG_DWORD(®->iobase_window, 0x01); 1996 dmp_reg = ®->iobase_c4; 1997 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1998 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1999 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 2000 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 2001 2002 WRT_REG_DWORD(®->iobase_window, 0x00); 2003 RD_REG_DWORD(®->iobase_window); 2004 2005 /* Host interface registers. */ 2006 dmp_reg = ®->flash_addr; 2007 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 2008 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 2009 2010 /* Disable interrupts. */ 2011 WRT_REG_DWORD(®->ictrl, 0); 2012 RD_REG_DWORD(®->ictrl); 2013 2014 /* Shadow registers. */ 2015 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 2016 RD_REG_DWORD(®->iobase_addr); 2017 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 2018 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2019 2020 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 2021 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2022 2023 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 2024 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2025 2026 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 2027 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2028 2029 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 2030 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2031 2032 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 2033 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2034 2035 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 2036 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2037 2038 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 2039 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2040 2041 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 2042 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2043 2044 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 2045 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2046 2047 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 2048 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2049 2050 /* RISC I/O register. */ 2051 WRT_REG_DWORD(®->iobase_addr, 0x0010); 2052 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 2053 2054 /* Mailbox registers. */ 2055 mbx_reg = ®->mailbox0; 2056 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 2057 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 2058 2059 /* Transfer sequence registers. */ 2060 iter_reg = fw->xseq_gp_reg; 2061 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); 2062 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); 2063 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); 2064 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); 2065 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); 2066 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); 2067 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); 2068 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); 2069 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 2070 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 2071 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 2072 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 2073 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 2074 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 2075 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 2076 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 2077 2078 iter_reg = fw->xseq_0_reg; 2079 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 2080 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 2081 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 2082 2083 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 2084 2085 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); 2086 2087 /* Receive sequence registers. */ 2088 iter_reg = fw->rseq_gp_reg; 2089 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); 2090 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); 2091 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); 2092 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); 2093 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); 2094 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); 2095 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); 2096 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); 2097 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 2098 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 2099 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 2100 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 2101 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 2102 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 2103 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 2104 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 2105 2106 iter_reg = fw->rseq_0_reg; 2107 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 2108 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 2109 2110 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 2111 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 2112 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); 2113 2114 /* Auxiliary sequence registers. */ 2115 iter_reg = fw->aseq_gp_reg; 2116 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 2117 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 2118 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 2119 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 2120 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 2121 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 2122 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 2123 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); 2124 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); 2125 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); 2126 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); 2127 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); 2128 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); 2129 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); 2130 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); 2131 qla24xx_read_window(reg, 0xB170, 16, iter_reg); 2132 2133 iter_reg = fw->aseq_0_reg; 2134 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 2135 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 2136 2137 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 2138 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 2139 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); 2140 2141 /* Command DMA registers. */ 2142 iter_reg = fw->cmd_dma_reg; 2143 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); 2144 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); 2145 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); 2146 qla24xx_read_window(reg, 0x71F0, 16, iter_reg); 2147 2148 /* Queues. */ 2149 iter_reg = fw->req0_dma_reg; 2150 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 2151 dmp_reg = ®->iobase_q; 2152 for (cnt = 0; cnt < 7; cnt++) 2153 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2154 2155 iter_reg = fw->resp0_dma_reg; 2156 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 2157 dmp_reg = ®->iobase_q; 2158 for (cnt = 0; cnt < 7; cnt++) 2159 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2160 2161 iter_reg = fw->req1_dma_reg; 2162 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 2163 dmp_reg = ®->iobase_q; 2164 for (cnt = 0; cnt < 7; cnt++) 2165 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2166 2167 /* Transmit DMA registers. */ 2168 iter_reg = fw->xmt0_dma_reg; 2169 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 2170 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 2171 2172 iter_reg = fw->xmt1_dma_reg; 2173 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 2174 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 2175 2176 iter_reg = fw->xmt2_dma_reg; 2177 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 2178 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 2179 2180 iter_reg = fw->xmt3_dma_reg; 2181 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 2182 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 2183 2184 iter_reg = fw->xmt4_dma_reg; 2185 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 2186 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 2187 2188 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 2189 2190 /* Receive DMA registers. */ 2191 iter_reg = fw->rcvt0_data_dma_reg; 2192 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 2193 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 2194 2195 iter_reg = fw->rcvt1_data_dma_reg; 2196 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 2197 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 2198 2199 /* RISC registers. */ 2200 iter_reg = fw->risc_gp_reg; 2201 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 2202 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 2203 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 2204 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 2205 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 2206 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 2207 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 2208 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 2209 2210 /* Local memory controller registers. */ 2211 iter_reg = fw->lmc_reg; 2212 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 2213 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 2214 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 2215 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 2216 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 2217 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 2218 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 2219 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 2220 2221 /* Fibre Protocol Module registers. */ 2222 iter_reg = fw->fpm_hdw_reg; 2223 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 2224 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 2225 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 2226 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 2227 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 2228 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 2229 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 2230 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 2231 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 2232 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 2233 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 2234 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 2235 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); 2236 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); 2237 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); 2238 qla24xx_read_window(reg, 0x40F0, 16, iter_reg); 2239 2240 /* RQ0 Array registers. */ 2241 iter_reg = fw->rq0_array_reg; 2242 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); 2243 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); 2244 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); 2245 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); 2246 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); 2247 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); 2248 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); 2249 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); 2250 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); 2251 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); 2252 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); 2253 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); 2254 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); 2255 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); 2256 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); 2257 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); 2258 2259 /* RQ1 Array registers. */ 2260 iter_reg = fw->rq1_array_reg; 2261 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); 2262 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); 2263 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); 2264 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); 2265 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); 2266 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); 2267 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); 2268 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); 2269 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); 2270 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); 2271 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); 2272 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); 2273 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); 2274 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); 2275 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); 2276 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); 2277 2278 /* RP0 Array registers. */ 2279 iter_reg = fw->rp0_array_reg; 2280 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); 2281 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); 2282 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); 2283 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); 2284 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); 2285 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); 2286 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); 2287 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); 2288 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); 2289 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); 2290 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); 2291 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); 2292 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); 2293 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); 2294 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); 2295 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); 2296 2297 /* RP1 Array registers. */ 2298 iter_reg = fw->rp1_array_reg; 2299 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); 2300 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); 2301 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); 2302 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); 2303 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); 2304 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); 2305 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); 2306 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); 2307 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); 2308 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); 2309 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); 2310 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); 2311 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); 2312 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); 2313 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); 2314 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); 2315 2316 iter_reg = fw->at0_array_reg; 2317 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); 2318 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); 2319 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); 2320 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); 2321 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); 2322 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); 2323 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); 2324 qla24xx_read_window(reg, 0x70F0, 16, iter_reg); 2325 2326 /* I/O Queue Control registers. */ 2327 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); 2328 2329 /* Frame Buffer registers. */ 2330 iter_reg = fw->fb_hdw_reg; 2331 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 2332 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 2333 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 2334 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 2335 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 2336 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); 2337 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); 2338 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 2339 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 2340 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 2341 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 2342 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 2343 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 2344 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); 2345 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); 2346 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); 2347 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); 2348 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); 2349 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); 2350 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); 2351 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); 2352 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); 2353 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); 2354 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); 2355 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); 2356 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); 2357 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 2358 2359 /* Multi queue registers */ 2360 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 2361 &last_chain); 2362 2363 rval = qla24xx_soft_reset(ha); 2364 if (rval != QLA_SUCCESS) { 2365 ql_log(ql_log_warn, vha, 0xd00e, 2366 "SOFT RESET FAILED, forcing continuation of dump!!!\n"); 2367 rval = QLA_SUCCESS; 2368 2369 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n"); 2370 2371 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); 2372 RD_REG_DWORD(®->hccr); 2373 2374 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); 2375 RD_REG_DWORD(®->hccr); 2376 2377 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 2378 RD_REG_DWORD(®->hccr); 2379 2380 for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--) 2381 udelay(5); 2382 2383 if (!cnt) { 2384 nxt = fw->code_ram; 2385 nxt += sizeof(fw->code_ram); 2386 nxt += (ha->fw_memory_size - 0x100000 + 1); 2387 goto copy_queue; 2388 } else 2389 ql_log(ql_log_warn, vha, 0xd010, 2390 "bigger hammer success?\n"); 2391 } 2392 2393 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 2394 &nxt); 2395 if (rval != QLA_SUCCESS) 2396 goto qla83xx_fw_dump_failed_0; 2397 2398 copy_queue: 2399 nxt = qla2xxx_copy_queues(ha, nxt); 2400 2401 qla24xx_copy_eft(ha, nxt); 2402 2403 /* Chain entries -- started with MQ. */ 2404 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 2405 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 2406 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 2407 if (last_chain) { 2408 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 2409 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 2410 } 2411 2412 /* Adjust valid length. */ 2413 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 2414 2415 qla83xx_fw_dump_failed_0: 2416 qla2xxx_dump_post_process(base_vha, rval); 2417 2418 qla83xx_fw_dump_failed: 2419 if (!hardware_locked) 2420 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2421 } 2422 2423 /****************************************************************************/ 2424 /* Driver Debug Functions. */ 2425 /****************************************************************************/ 2426 2427 static inline int 2428 ql_mask_match(uint32_t level) 2429 { 2430 if (ql2xextended_error_logging == 1) 2431 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 2432 return (level & ql2xextended_error_logging) == level; 2433 } 2434 2435 /* 2436 * This function is for formatting and logging debug information. 2437 * It is to be used when vha is available. It formats the message 2438 * and logs it to the messages file. 2439 * parameters: 2440 * level: The level of the debug messages to be printed. 2441 * If ql2xextended_error_logging value is correctly set, 2442 * this message will appear in the messages file. 2443 * vha: Pointer to the scsi_qla_host_t. 2444 * id: This is a unique identifier for the level. It identifies the 2445 * part of the code from where the message originated. 2446 * msg: The message to be displayed. 2447 */ 2448 void 2449 ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) 2450 { 2451 va_list va; 2452 struct va_format vaf; 2453 2454 if (!ql_mask_match(level)) 2455 return; 2456 2457 va_start(va, fmt); 2458 2459 vaf.fmt = fmt; 2460 vaf.va = &va; 2461 2462 if (vha != NULL) { 2463 const struct pci_dev *pdev = vha->hw->pdev; 2464 /* <module-name> <pci-name> <msg-id>:<host> Message */ 2465 pr_warn("%s [%s]-%04x:%ld: %pV", 2466 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, 2467 vha->host_no, &vaf); 2468 } else { 2469 pr_warn("%s [%s]-%04x: : %pV", 2470 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); 2471 } 2472 2473 va_end(va); 2474 2475 } 2476 2477 /* 2478 * This function is for formatting and logging debug information. 2479 * It is to be used when vha is not available and pci is available, 2480 * i.e., before host allocation. It formats the message and logs it 2481 * to the messages file. 2482 * parameters: 2483 * level: The level of the debug messages to be printed. 2484 * If ql2xextended_error_logging value is correctly set, 2485 * this message will appear in the messages file. 2486 * pdev: Pointer to the struct pci_dev. 2487 * id: This is a unique id for the level. It identifies the part 2488 * of the code from where the message originated. 2489 * msg: The message to be displayed. 2490 */ 2491 void 2492 ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, 2493 const char *fmt, ...) 2494 { 2495 va_list va; 2496 struct va_format vaf; 2497 2498 if (pdev == NULL) 2499 return; 2500 if (!ql_mask_match(level)) 2501 return; 2502 2503 va_start(va, fmt); 2504 2505 vaf.fmt = fmt; 2506 vaf.va = &va; 2507 2508 /* <module-name> <dev-name>:<msg-id> Message */ 2509 pr_warn("%s [%s]-%04x: : %pV", 2510 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf); 2511 2512 va_end(va); 2513 } 2514 2515 /* 2516 * This function is for formatting and logging log messages. 2517 * It is to be used when vha is available. It formats the message 2518 * and logs it to the messages file. All the messages will be logged 2519 * irrespective of value of ql2xextended_error_logging. 2520 * parameters: 2521 * level: The level of the log messages to be printed in the 2522 * messages file. 2523 * vha: Pointer to the scsi_qla_host_t 2524 * id: This is a unique id for the level. It identifies the 2525 * part of the code from where the message originated. 2526 * msg: The message to be displayed. 2527 */ 2528 void 2529 ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) 2530 { 2531 va_list va; 2532 struct va_format vaf; 2533 char pbuf[128]; 2534 2535 if (level > ql_errlev) 2536 return; 2537 2538 if (vha != NULL) { 2539 const struct pci_dev *pdev = vha->hw->pdev; 2540 /* <module-name> <msg-id>:<host> Message */ 2541 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", 2542 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no); 2543 } else { 2544 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2545 QL_MSGHDR, "0000:00:00.0", id); 2546 } 2547 pbuf[sizeof(pbuf) - 1] = 0; 2548 2549 va_start(va, fmt); 2550 2551 vaf.fmt = fmt; 2552 vaf.va = &va; 2553 2554 switch (level) { 2555 case ql_log_fatal: /* FATAL LOG */ 2556 pr_crit("%s%pV", pbuf, &vaf); 2557 break; 2558 case ql_log_warn: 2559 pr_err("%s%pV", pbuf, &vaf); 2560 break; 2561 case ql_log_info: 2562 pr_warn("%s%pV", pbuf, &vaf); 2563 break; 2564 default: 2565 pr_info("%s%pV", pbuf, &vaf); 2566 break; 2567 } 2568 2569 va_end(va); 2570 } 2571 2572 /* 2573 * This function is for formatting and logging log messages. 2574 * It is to be used when vha is not available and pci is available, 2575 * i.e., before host allocation. It formats the message and logs 2576 * it to the messages file. All the messages are logged irrespective 2577 * of the value of ql2xextended_error_logging. 2578 * parameters: 2579 * level: The level of the log messages to be printed in the 2580 * messages file. 2581 * pdev: Pointer to the struct pci_dev. 2582 * id: This is a unique id for the level. It identifies the 2583 * part of the code from where the message originated. 2584 * msg: The message to be displayed. 2585 */ 2586 void 2587 ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, 2588 const char *fmt, ...) 2589 { 2590 va_list va; 2591 struct va_format vaf; 2592 char pbuf[128]; 2593 2594 if (pdev == NULL) 2595 return; 2596 if (level > ql_errlev) 2597 return; 2598 2599 /* <module-name> <dev-name>:<msg-id> Message */ 2600 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2601 QL_MSGHDR, dev_name(&(pdev->dev)), id); 2602 pbuf[sizeof(pbuf) - 1] = 0; 2603 2604 va_start(va, fmt); 2605 2606 vaf.fmt = fmt; 2607 vaf.va = &va; 2608 2609 switch (level) { 2610 case ql_log_fatal: /* FATAL LOG */ 2611 pr_crit("%s%pV", pbuf, &vaf); 2612 break; 2613 case ql_log_warn: 2614 pr_err("%s%pV", pbuf, &vaf); 2615 break; 2616 case ql_log_info: 2617 pr_warn("%s%pV", pbuf, &vaf); 2618 break; 2619 default: 2620 pr_info("%s%pV", pbuf, &vaf); 2621 break; 2622 } 2623 2624 va_end(va); 2625 } 2626 2627 void 2628 ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id) 2629 { 2630 int i; 2631 struct qla_hw_data *ha = vha->hw; 2632 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2633 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 2634 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 2635 uint16_t __iomem *mbx_reg; 2636 2637 if (!ql_mask_match(level)) 2638 return; 2639 2640 if (IS_P3P_TYPE(ha)) 2641 mbx_reg = ®82->mailbox_in[0]; 2642 else if (IS_FWI2_CAPABLE(ha)) 2643 mbx_reg = ®24->mailbox0; 2644 else 2645 mbx_reg = MAILBOX_REG(ha, reg, 0); 2646 2647 ql_dbg(level, vha, id, "Mailbox registers:\n"); 2648 for (i = 0; i < 6; i++) 2649 ql_dbg(level, vha, id, 2650 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); 2651 } 2652 2653 2654 void 2655 ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id, 2656 uint8_t *b, uint32_t size) 2657 { 2658 uint32_t cnt; 2659 uint8_t c; 2660 2661 if (!ql_mask_match(level)) 2662 return; 2663 2664 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 " 2665 "9 Ah Bh Ch Dh Eh Fh\n"); 2666 ql_dbg(level, vha, id, "----------------------------------" 2667 "----------------------------\n"); 2668 2669 ql_dbg(level, vha, id, " "); 2670 for (cnt = 0; cnt < size;) { 2671 c = *b++; 2672 printk("%02x", (uint32_t) c); 2673 cnt++; 2674 if (!(cnt % 16)) 2675 printk("\n"); 2676 else 2677 printk(" "); 2678 } 2679 if (cnt % 16) 2680 ql_dbg(level, vha, id, "\n"); 2681 } 2682