1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8 /* 9 * Table for showing the current message id in use for particular level 10 * Change this table for addition of log/debug messages. 11 * ---------------------------------------------------------------------- 12 * | Level | Last Value Used | Holes | 13 * ---------------------------------------------------------------------- 14 * | Module Init and Probe | 0x017f | 0x0146 | 15 * | | | 0x015b-0x0160 | 16 * | | | 0x016e-0x0170 | 17 * | Mailbox commands | 0x1192 | | 18 * | | | | 19 * | Device Discovery | 0x2016 | 0x2020-0x2022, | 20 * | | | 0x2011-0x2012, | 21 * | | | 0x2099-0x20a4 | 22 * | Queue Command and IO tracing | 0x3074 | 0x300b | 23 * | | | 0x3027-0x3028 | 24 * | | | 0x303d-0x3041 | 25 * | | | 0x302d,0x3033 | 26 * | | | 0x3036,0x3038 | 27 * | | | 0x303a | 28 * | DPC Thread | 0x4023 | 0x4002,0x4013 | 29 * | Async Events | 0x5089 | 0x502b-0x502f | 30 * | | | 0x5084,0x5075 | 31 * | | | 0x503d,0x5044 | 32 * | | | 0x507b,0x505f | 33 * | Timer Routines | 0x6012 | | 34 * | User Space Interactions | 0x70e65 | 0x7018,0x702e | 35 * | | | 0x7020,0x7024 | 36 * | | | 0x7039,0x7045 | 37 * | | | 0x7073-0x7075 | 38 * | | | 0x70a5-0x70a6 | 39 * | | | 0x70a8,0x70ab | 40 * | | | 0x70ad-0x70ae | 41 * | | | 0x70d7-0x70db | 42 * | | | 0x70de-0x70df | 43 * | Task Management | 0x803d | 0x8000,0x800b | 44 * | | | 0x8019 | 45 * | | | 0x8025,0x8026 | 46 * | | | 0x8031,0x8032 | 47 * | | | 0x8039,0x803c | 48 * | AER/EEH | 0x9011 | | 49 * | Virtual Port | 0xa007 | | 50 * | ISP82XX Specific | 0xb157 | 0xb002,0xb024 | 51 * | | | 0xb09e,0xb0ae | 52 * | | | 0xb0c3,0xb0c6 | 53 * | | | 0xb0e0-0xb0ef | 54 * | | | 0xb085,0xb0dc | 55 * | | | 0xb107,0xb108 | 56 * | | | 0xb111,0xb11e | 57 * | | | 0xb12c,0xb12d | 58 * | | | 0xb13a,0xb142 | 59 * | | | 0xb13c-0xb140 | 60 * | | | 0xb149 | 61 * | MultiQ | 0xc00c | | 62 * | Misc | 0xd301 | 0xd031-0xd0ff | 63 * | | | 0xd101-0xd1fe | 64 * | | | 0xd214-0xd2fe | 65 * | Target Mode | 0xe080 | | 66 * | Target Mode Management | 0xf09b | 0xf002 | 67 * | | | 0xf046-0xf049 | 68 * | Target Mode Task Management | 0x1000d | | 69 * ---------------------------------------------------------------------- 70 */ 71 72 #include "qla_def.h" 73 74 #include <linux/delay.h> 75 76 static uint32_t ql_dbg_offset = 0x800; 77 78 static inline void 79 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) 80 { 81 fw_dump->fw_major_version = htonl(ha->fw_major_version); 82 fw_dump->fw_minor_version = htonl(ha->fw_minor_version); 83 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); 84 fw_dump->fw_attributes = htonl(ha->fw_attributes); 85 86 fw_dump->vendor = htonl(ha->pdev->vendor); 87 fw_dump->device = htonl(ha->pdev->device); 88 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); 89 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); 90 } 91 92 static inline void * 93 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) 94 { 95 struct req_que *req = ha->req_q_map[0]; 96 struct rsp_que *rsp = ha->rsp_q_map[0]; 97 /* Request queue. */ 98 memcpy(ptr, req->ring, req->length * 99 sizeof(request_t)); 100 101 /* Response queue. */ 102 ptr += req->length * sizeof(request_t); 103 memcpy(ptr, rsp->ring, rsp->length * 104 sizeof(response_t)); 105 106 return ptr + (rsp->length * sizeof(response_t)); 107 } 108 109 int 110 qla27xx_dump_mpi_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, 111 uint32_t ram_dwords, void **nxt) 112 { 113 int rval; 114 uint32_t cnt, stat, timer, dwords, idx; 115 uint16_t mb0; 116 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 117 dma_addr_t dump_dma = ha->gid_list_dma; 118 uint32_t *dump = (uint32_t *)ha->gid_list; 119 120 rval = QLA_SUCCESS; 121 mb0 = 0; 122 123 WRT_REG_WORD(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM); 124 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 125 126 dwords = qla2x00_gid_list_size(ha) / 4; 127 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; 128 cnt += dwords, addr += dwords) { 129 if (cnt + dwords > ram_dwords) 130 dwords = ram_dwords - cnt; 131 132 WRT_REG_WORD(®->mailbox1, LSW(addr)); 133 WRT_REG_WORD(®->mailbox8, MSW(addr)); 134 135 WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); 136 WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); 137 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); 138 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); 139 140 WRT_REG_WORD(®->mailbox4, MSW(dwords)); 141 WRT_REG_WORD(®->mailbox5, LSW(dwords)); 142 143 WRT_REG_WORD(®->mailbox9, 0); 144 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 145 146 ha->flags.mbox_int = 0; 147 for (timer = 6000000; timer; timer--) { 148 /* Check for pending interrupts. */ 149 stat = RD_REG_DWORD(®->host_status); 150 if (stat & HSRX_RISC_INT) { 151 stat &= 0xff; 152 153 if (stat == 0x1 || stat == 0x2 || 154 stat == 0x10 || stat == 0x11) { 155 set_bit(MBX_INTERRUPT, 156 &ha->mbx_cmd_flags); 157 158 mb0 = RD_REG_WORD(®->mailbox0); 159 RD_REG_WORD(®->mailbox1); 160 161 WRT_REG_DWORD(®->hccr, 162 HCCRX_CLR_RISC_INT); 163 RD_REG_DWORD(®->hccr); 164 break; 165 } 166 167 /* Clear this intr; it wasn't a mailbox intr */ 168 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); 169 RD_REG_DWORD(®->hccr); 170 } 171 udelay(5); 172 } 173 ha->flags.mbox_int = 1; 174 175 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 176 rval = mb0 & MBS_MASK; 177 for (idx = 0; idx < dwords; idx++) 178 ram[cnt + idx] = IS_QLA27XX(ha) ? 179 le32_to_cpu(dump[idx]) : swab32(dump[idx]); 180 } else { 181 rval = QLA_FUNCTION_FAILED; 182 } 183 } 184 185 *nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL; 186 return rval; 187 } 188 189 int 190 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, 191 uint32_t ram_dwords, void **nxt) 192 { 193 int rval; 194 uint32_t cnt, stat, timer, dwords, idx; 195 uint16_t mb0; 196 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 197 dma_addr_t dump_dma = ha->gid_list_dma; 198 uint32_t *dump = (uint32_t *)ha->gid_list; 199 200 rval = QLA_SUCCESS; 201 mb0 = 0; 202 203 WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); 204 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 205 206 dwords = qla2x00_gid_list_size(ha) / 4; 207 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; 208 cnt += dwords, addr += dwords) { 209 if (cnt + dwords > ram_dwords) 210 dwords = ram_dwords - cnt; 211 212 WRT_REG_WORD(®->mailbox1, LSW(addr)); 213 WRT_REG_WORD(®->mailbox8, MSW(addr)); 214 215 WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); 216 WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); 217 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); 218 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); 219 220 WRT_REG_WORD(®->mailbox4, MSW(dwords)); 221 WRT_REG_WORD(®->mailbox5, LSW(dwords)); 222 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 223 224 ha->flags.mbox_int = 0; 225 for (timer = 6000000; timer; timer--) { 226 /* Check for pending interrupts. */ 227 stat = RD_REG_DWORD(®->host_status); 228 if (stat & HSRX_RISC_INT) { 229 stat &= 0xff; 230 231 if (stat == 0x1 || stat == 0x2 || 232 stat == 0x10 || stat == 0x11) { 233 set_bit(MBX_INTERRUPT, 234 &ha->mbx_cmd_flags); 235 236 mb0 = RD_REG_WORD(®->mailbox0); 237 238 WRT_REG_DWORD(®->hccr, 239 HCCRX_CLR_RISC_INT); 240 RD_REG_DWORD(®->hccr); 241 break; 242 } 243 244 /* Clear this intr; it wasn't a mailbox intr */ 245 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); 246 RD_REG_DWORD(®->hccr); 247 } 248 udelay(5); 249 } 250 ha->flags.mbox_int = 1; 251 252 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 253 rval = mb0 & MBS_MASK; 254 for (idx = 0; idx < dwords; idx++) 255 ram[cnt + idx] = IS_QLA27XX(ha) ? 256 le32_to_cpu(dump[idx]) : swab32(dump[idx]); 257 } else { 258 rval = QLA_FUNCTION_FAILED; 259 } 260 } 261 262 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; 263 return rval; 264 } 265 266 static int 267 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, 268 uint32_t cram_size, void **nxt) 269 { 270 int rval; 271 272 /* Code RAM. */ 273 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); 274 if (rval != QLA_SUCCESS) 275 return rval; 276 277 set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags); 278 279 /* External Memory. */ 280 rval = qla24xx_dump_ram(ha, 0x100000, *nxt, 281 ha->fw_memory_size - 0x100000 + 1, nxt); 282 if (rval == QLA_SUCCESS) 283 set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags); 284 285 return rval; 286 } 287 288 static uint32_t * 289 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, 290 uint32_t count, uint32_t *buf) 291 { 292 uint32_t __iomem *dmp_reg; 293 294 WRT_REG_DWORD(®->iobase_addr, iobase); 295 dmp_reg = ®->iobase_window; 296 while (count--) 297 *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); 298 299 return buf; 300 } 301 302 void 303 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha) 304 { 305 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); 306 307 /* 100 usec delay is sufficient enough for hardware to pause RISC */ 308 udelay(100); 309 if (RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) 310 set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags); 311 } 312 313 int 314 qla24xx_soft_reset(struct qla_hw_data *ha) 315 { 316 int rval = QLA_SUCCESS; 317 uint32_t cnt; 318 uint16_t wd; 319 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 320 321 /* 322 * Reset RISC. The delay is dependent on system architecture. 323 * Driver can proceed with the reset sequence after waiting 324 * for a timeout period. 325 */ 326 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 327 for (cnt = 0; cnt < 30000; cnt++) { 328 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 329 break; 330 331 udelay(10); 332 } 333 if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) 334 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); 335 336 WRT_REG_DWORD(®->ctrl_status, 337 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 338 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 339 340 udelay(100); 341 342 /* Wait for soft-reset to complete. */ 343 for (cnt = 0; cnt < 30000; cnt++) { 344 if ((RD_REG_DWORD(®->ctrl_status) & 345 CSRX_ISP_SOFT_RESET) == 0) 346 break; 347 348 udelay(10); 349 } 350 if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) 351 set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags); 352 353 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 354 RD_REG_DWORD(®->hccr); /* PCI Posting. */ 355 356 for (cnt = 10000; RD_REG_WORD(®->mailbox0) != 0 && 357 rval == QLA_SUCCESS; cnt--) { 358 if (cnt) 359 udelay(10); 360 else 361 rval = QLA_FUNCTION_TIMEOUT; 362 } 363 if (rval == QLA_SUCCESS) 364 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); 365 366 return rval; 367 } 368 369 static int 370 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, 371 uint32_t ram_words, void **nxt) 372 { 373 int rval; 374 uint32_t cnt, stat, timer, words, idx; 375 uint16_t mb0; 376 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 377 dma_addr_t dump_dma = ha->gid_list_dma; 378 uint16_t *dump = (uint16_t *)ha->gid_list; 379 380 rval = QLA_SUCCESS; 381 mb0 = 0; 382 383 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); 384 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 385 386 words = qla2x00_gid_list_size(ha) / 2; 387 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; 388 cnt += words, addr += words) { 389 if (cnt + words > ram_words) 390 words = ram_words - cnt; 391 392 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); 393 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); 394 395 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); 396 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); 397 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); 398 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); 399 400 WRT_MAILBOX_REG(ha, reg, 4, words); 401 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 402 403 for (timer = 6000000; timer; timer--) { 404 /* Check for pending interrupts. */ 405 stat = RD_REG_DWORD(®->u.isp2300.host_status); 406 if (stat & HSR_RISC_INT) { 407 stat &= 0xff; 408 409 if (stat == 0x1 || stat == 0x2) { 410 set_bit(MBX_INTERRUPT, 411 &ha->mbx_cmd_flags); 412 413 mb0 = RD_MAILBOX_REG(ha, reg, 0); 414 415 /* Release mailbox registers. */ 416 WRT_REG_WORD(®->semaphore, 0); 417 WRT_REG_WORD(®->hccr, 418 HCCR_CLR_RISC_INT); 419 RD_REG_WORD(®->hccr); 420 break; 421 } else if (stat == 0x10 || stat == 0x11) { 422 set_bit(MBX_INTERRUPT, 423 &ha->mbx_cmd_flags); 424 425 mb0 = RD_MAILBOX_REG(ha, reg, 0); 426 427 WRT_REG_WORD(®->hccr, 428 HCCR_CLR_RISC_INT); 429 RD_REG_WORD(®->hccr); 430 break; 431 } 432 433 /* clear this intr; it wasn't a mailbox intr */ 434 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 435 RD_REG_WORD(®->hccr); 436 } 437 udelay(5); 438 } 439 440 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 441 rval = mb0 & MBS_MASK; 442 for (idx = 0; idx < words; idx++) 443 ram[cnt + idx] = swab16(dump[idx]); 444 } else { 445 rval = QLA_FUNCTION_FAILED; 446 } 447 } 448 449 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; 450 return rval; 451 } 452 453 static inline void 454 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, 455 uint16_t *buf) 456 { 457 uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; 458 459 while (count--) 460 *buf++ = htons(RD_REG_WORD(dmp_reg++)); 461 } 462 463 static inline void * 464 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) 465 { 466 if (!ha->eft) 467 return ptr; 468 469 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); 470 return ptr + ntohl(ha->fw_dump->eft_size); 471 } 472 473 static inline void * 474 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 475 { 476 uint32_t cnt; 477 uint32_t *iter_reg; 478 struct qla2xxx_fce_chain *fcec = ptr; 479 480 if (!ha->fce) 481 return ptr; 482 483 *last_chain = &fcec->type; 484 fcec->type = htonl(DUMP_CHAIN_FCE); 485 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + 486 fce_calc_size(ha->fce_bufs)); 487 fcec->size = htonl(fce_calc_size(ha->fce_bufs)); 488 fcec->addr_l = htonl(LSD(ha->fce_dma)); 489 fcec->addr_h = htonl(MSD(ha->fce_dma)); 490 491 iter_reg = fcec->eregs; 492 for (cnt = 0; cnt < 8; cnt++) 493 *iter_reg++ = htonl(ha->fce_mb[cnt]); 494 495 memcpy(iter_reg, ha->fce, ntohl(fcec->size)); 496 497 return (char *)iter_reg + ntohl(fcec->size); 498 } 499 500 static inline void * 501 qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr, 502 uint32_t **last_chain) 503 { 504 struct qla2xxx_mqueue_chain *q; 505 struct qla2xxx_mqueue_header *qh; 506 uint32_t num_queues; 507 int que; 508 struct { 509 int length; 510 void *ring; 511 } aq, *aqp; 512 513 if (!ha->tgt.atio_ring) 514 return ptr; 515 516 num_queues = 1; 517 aqp = &aq; 518 aqp->length = ha->tgt.atio_q_length; 519 aqp->ring = ha->tgt.atio_ring; 520 521 for (que = 0; que < num_queues; que++) { 522 /* aqp = ha->atio_q_map[que]; */ 523 q = ptr; 524 *last_chain = &q->type; 525 q->type = htonl(DUMP_CHAIN_QUEUE); 526 q->chain_size = htonl( 527 sizeof(struct qla2xxx_mqueue_chain) + 528 sizeof(struct qla2xxx_mqueue_header) + 529 (aqp->length * sizeof(request_t))); 530 ptr += sizeof(struct qla2xxx_mqueue_chain); 531 532 /* Add header. */ 533 qh = ptr; 534 qh->queue = htonl(TYPE_ATIO_QUEUE); 535 qh->number = htonl(que); 536 qh->size = htonl(aqp->length * sizeof(request_t)); 537 ptr += sizeof(struct qla2xxx_mqueue_header); 538 539 /* Add data. */ 540 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t)); 541 542 ptr += aqp->length * sizeof(request_t); 543 } 544 545 return ptr; 546 } 547 548 static inline void * 549 qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 550 { 551 struct qla2xxx_mqueue_chain *q; 552 struct qla2xxx_mqueue_header *qh; 553 struct req_que *req; 554 struct rsp_que *rsp; 555 int que; 556 557 if (!ha->mqenable) 558 return ptr; 559 560 /* Request queues */ 561 for (que = 1; que < ha->max_req_queues; que++) { 562 req = ha->req_q_map[que]; 563 if (!req) 564 break; 565 566 /* Add chain. */ 567 q = ptr; 568 *last_chain = &q->type; 569 q->type = htonl(DUMP_CHAIN_QUEUE); 570 q->chain_size = htonl( 571 sizeof(struct qla2xxx_mqueue_chain) + 572 sizeof(struct qla2xxx_mqueue_header) + 573 (req->length * sizeof(request_t))); 574 ptr += sizeof(struct qla2xxx_mqueue_chain); 575 576 /* Add header. */ 577 qh = ptr; 578 qh->queue = htonl(TYPE_REQUEST_QUEUE); 579 qh->number = htonl(que); 580 qh->size = htonl(req->length * sizeof(request_t)); 581 ptr += sizeof(struct qla2xxx_mqueue_header); 582 583 /* Add data. */ 584 memcpy(ptr, req->ring, req->length * sizeof(request_t)); 585 ptr += req->length * sizeof(request_t); 586 } 587 588 /* Response queues */ 589 for (que = 1; que < ha->max_rsp_queues; que++) { 590 rsp = ha->rsp_q_map[que]; 591 if (!rsp) 592 break; 593 594 /* Add chain. */ 595 q = ptr; 596 *last_chain = &q->type; 597 q->type = htonl(DUMP_CHAIN_QUEUE); 598 q->chain_size = htonl( 599 sizeof(struct qla2xxx_mqueue_chain) + 600 sizeof(struct qla2xxx_mqueue_header) + 601 (rsp->length * sizeof(response_t))); 602 ptr += sizeof(struct qla2xxx_mqueue_chain); 603 604 /* Add header. */ 605 qh = ptr; 606 qh->queue = htonl(TYPE_RESPONSE_QUEUE); 607 qh->number = htonl(que); 608 qh->size = htonl(rsp->length * sizeof(response_t)); 609 ptr += sizeof(struct qla2xxx_mqueue_header); 610 611 /* Add data. */ 612 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t)); 613 ptr += rsp->length * sizeof(response_t); 614 } 615 616 return ptr; 617 } 618 619 static inline void * 620 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 621 { 622 uint32_t cnt, que_idx; 623 uint8_t que_cnt; 624 struct qla2xxx_mq_chain *mq = ptr; 625 device_reg_t *reg; 626 627 if (!ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) 628 return ptr; 629 630 mq = ptr; 631 *last_chain = &mq->type; 632 mq->type = htonl(DUMP_CHAIN_MQ); 633 mq->chain_size = htonl(sizeof(struct qla2xxx_mq_chain)); 634 635 que_cnt = ha->max_req_queues > ha->max_rsp_queues ? 636 ha->max_req_queues : ha->max_rsp_queues; 637 mq->count = htonl(que_cnt); 638 for (cnt = 0; cnt < que_cnt; cnt++) { 639 reg = ISP_QUE_REG(ha, cnt); 640 que_idx = cnt * 4; 641 mq->qregs[que_idx] = 642 htonl(RD_REG_DWORD(®->isp25mq.req_q_in)); 643 mq->qregs[que_idx+1] = 644 htonl(RD_REG_DWORD(®->isp25mq.req_q_out)); 645 mq->qregs[que_idx+2] = 646 htonl(RD_REG_DWORD(®->isp25mq.rsp_q_in)); 647 mq->qregs[que_idx+3] = 648 htonl(RD_REG_DWORD(®->isp25mq.rsp_q_out)); 649 } 650 651 return ptr + sizeof(struct qla2xxx_mq_chain); 652 } 653 654 void 655 qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) 656 { 657 struct qla_hw_data *ha = vha->hw; 658 659 if (rval != QLA_SUCCESS) { 660 ql_log(ql_log_warn, vha, 0xd000, 661 "Failed to dump firmware (%x), dump status flags (0x%lx).\n", 662 rval, ha->fw_dump_cap_flags); 663 ha->fw_dumped = 0; 664 } else { 665 ql_log(ql_log_info, vha, 0xd001, 666 "Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n", 667 vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags); 668 ha->fw_dumped = 1; 669 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 670 } 671 } 672 673 /** 674 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 675 * @ha: HA context 676 * @hardware_locked: Called with the hardware_lock 677 */ 678 void 679 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 680 { 681 int rval; 682 uint32_t cnt; 683 struct qla_hw_data *ha = vha->hw; 684 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 685 uint16_t __iomem *dmp_reg; 686 unsigned long flags; 687 struct qla2300_fw_dump *fw; 688 void *nxt; 689 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 690 691 flags = 0; 692 693 #ifndef __CHECKER__ 694 if (!hardware_locked) 695 spin_lock_irqsave(&ha->hardware_lock, flags); 696 #endif 697 698 if (!ha->fw_dump) { 699 ql_log(ql_log_warn, vha, 0xd002, 700 "No buffer available for dump.\n"); 701 goto qla2300_fw_dump_failed; 702 } 703 704 if (ha->fw_dumped) { 705 ql_log(ql_log_warn, vha, 0xd003, 706 "Firmware has been previously dumped (%p) " 707 "-- ignoring request.\n", 708 ha->fw_dump); 709 goto qla2300_fw_dump_failed; 710 } 711 fw = &ha->fw_dump->isp.isp23; 712 qla2xxx_prep_dump(ha, ha->fw_dump); 713 714 rval = QLA_SUCCESS; 715 fw->hccr = htons(RD_REG_WORD(®->hccr)); 716 717 /* Pause RISC. */ 718 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 719 if (IS_QLA2300(ha)) { 720 for (cnt = 30000; 721 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 722 rval == QLA_SUCCESS; cnt--) { 723 if (cnt) 724 udelay(100); 725 else 726 rval = QLA_FUNCTION_TIMEOUT; 727 } 728 } else { 729 RD_REG_WORD(®->hccr); /* PCI Posting. */ 730 udelay(10); 731 } 732 733 if (rval == QLA_SUCCESS) { 734 dmp_reg = ®->flash_address; 735 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 736 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 737 738 dmp_reg = ®->u.isp2300.req_q_in; 739 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) 740 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 741 742 dmp_reg = ®->u.isp2300.mailbox0; 743 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 744 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 745 746 WRT_REG_WORD(®->ctrl_status, 0x40); 747 qla2xxx_read_window(reg, 32, fw->resp_dma_reg); 748 749 WRT_REG_WORD(®->ctrl_status, 0x50); 750 qla2xxx_read_window(reg, 48, fw->dma_reg); 751 752 WRT_REG_WORD(®->ctrl_status, 0x00); 753 dmp_reg = ®->risc_hw; 754 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 755 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 756 757 WRT_REG_WORD(®->pcr, 0x2000); 758 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 759 760 WRT_REG_WORD(®->pcr, 0x2200); 761 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 762 763 WRT_REG_WORD(®->pcr, 0x2400); 764 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 765 766 WRT_REG_WORD(®->pcr, 0x2600); 767 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 768 769 WRT_REG_WORD(®->pcr, 0x2800); 770 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 771 772 WRT_REG_WORD(®->pcr, 0x2A00); 773 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 774 775 WRT_REG_WORD(®->pcr, 0x2C00); 776 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 777 778 WRT_REG_WORD(®->pcr, 0x2E00); 779 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 780 781 WRT_REG_WORD(®->ctrl_status, 0x10); 782 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); 783 784 WRT_REG_WORD(®->ctrl_status, 0x20); 785 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 786 787 WRT_REG_WORD(®->ctrl_status, 0x30); 788 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 789 790 /* Reset RISC. */ 791 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 792 for (cnt = 0; cnt < 30000; cnt++) { 793 if ((RD_REG_WORD(®->ctrl_status) & 794 CSR_ISP_SOFT_RESET) == 0) 795 break; 796 797 udelay(10); 798 } 799 } 800 801 if (!IS_QLA2300(ha)) { 802 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 803 rval == QLA_SUCCESS; cnt--) { 804 if (cnt) 805 udelay(100); 806 else 807 rval = QLA_FUNCTION_TIMEOUT; 808 } 809 } 810 811 /* Get RISC SRAM. */ 812 if (rval == QLA_SUCCESS) 813 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, 814 sizeof(fw->risc_ram) / 2, &nxt); 815 816 /* Get stack SRAM. */ 817 if (rval == QLA_SUCCESS) 818 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, 819 sizeof(fw->stack_ram) / 2, &nxt); 820 821 /* Get data SRAM. */ 822 if (rval == QLA_SUCCESS) 823 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, 824 ha->fw_memory_size - 0x11000 + 1, &nxt); 825 826 if (rval == QLA_SUCCESS) 827 qla2xxx_copy_queues(ha, nxt); 828 829 qla2xxx_dump_post_process(base_vha, rval); 830 831 qla2300_fw_dump_failed: 832 #ifndef __CHECKER__ 833 if (!hardware_locked) 834 spin_unlock_irqrestore(&ha->hardware_lock, flags); 835 #else 836 ; 837 #endif 838 } 839 840 /** 841 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. 842 * @ha: HA context 843 * @hardware_locked: Called with the hardware_lock 844 */ 845 void 846 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 847 { 848 int rval; 849 uint32_t cnt, timer; 850 uint16_t risc_address; 851 uint16_t mb0, mb2; 852 struct qla_hw_data *ha = vha->hw; 853 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 854 uint16_t __iomem *dmp_reg; 855 unsigned long flags; 856 struct qla2100_fw_dump *fw; 857 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 858 859 risc_address = 0; 860 mb0 = mb2 = 0; 861 flags = 0; 862 863 #ifndef __CHECKER__ 864 if (!hardware_locked) 865 spin_lock_irqsave(&ha->hardware_lock, flags); 866 #endif 867 868 if (!ha->fw_dump) { 869 ql_log(ql_log_warn, vha, 0xd004, 870 "No buffer available for dump.\n"); 871 goto qla2100_fw_dump_failed; 872 } 873 874 if (ha->fw_dumped) { 875 ql_log(ql_log_warn, vha, 0xd005, 876 "Firmware has been previously dumped (%p) " 877 "-- ignoring request.\n", 878 ha->fw_dump); 879 goto qla2100_fw_dump_failed; 880 } 881 fw = &ha->fw_dump->isp.isp21; 882 qla2xxx_prep_dump(ha, ha->fw_dump); 883 884 rval = QLA_SUCCESS; 885 fw->hccr = htons(RD_REG_WORD(®->hccr)); 886 887 /* Pause RISC. */ 888 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 889 for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 890 rval == QLA_SUCCESS; cnt--) { 891 if (cnt) 892 udelay(100); 893 else 894 rval = QLA_FUNCTION_TIMEOUT; 895 } 896 if (rval == QLA_SUCCESS) { 897 dmp_reg = ®->flash_address; 898 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 899 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 900 901 dmp_reg = ®->u.isp2100.mailbox0; 902 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 903 if (cnt == 8) 904 dmp_reg = ®->u_end.isp2200.mailbox8; 905 906 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 907 } 908 909 dmp_reg = ®->u.isp2100.unused_2[0]; 910 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 911 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 912 913 WRT_REG_WORD(®->ctrl_status, 0x00); 914 dmp_reg = ®->risc_hw; 915 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 916 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 917 918 WRT_REG_WORD(®->pcr, 0x2000); 919 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 920 921 WRT_REG_WORD(®->pcr, 0x2100); 922 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 923 924 WRT_REG_WORD(®->pcr, 0x2200); 925 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 926 927 WRT_REG_WORD(®->pcr, 0x2300); 928 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 929 930 WRT_REG_WORD(®->pcr, 0x2400); 931 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 932 933 WRT_REG_WORD(®->pcr, 0x2500); 934 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 935 936 WRT_REG_WORD(®->pcr, 0x2600); 937 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 938 939 WRT_REG_WORD(®->pcr, 0x2700); 940 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 941 942 WRT_REG_WORD(®->ctrl_status, 0x10); 943 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); 944 945 WRT_REG_WORD(®->ctrl_status, 0x20); 946 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 947 948 WRT_REG_WORD(®->ctrl_status, 0x30); 949 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 950 951 /* Reset the ISP. */ 952 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 953 } 954 955 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 956 rval == QLA_SUCCESS; cnt--) { 957 if (cnt) 958 udelay(100); 959 else 960 rval = QLA_FUNCTION_TIMEOUT; 961 } 962 963 /* Pause RISC. */ 964 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && 965 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { 966 967 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 968 for (cnt = 30000; 969 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 970 rval == QLA_SUCCESS; cnt--) { 971 if (cnt) 972 udelay(100); 973 else 974 rval = QLA_FUNCTION_TIMEOUT; 975 } 976 if (rval == QLA_SUCCESS) { 977 /* Set memory configuration and timing. */ 978 if (IS_QLA2100(ha)) 979 WRT_REG_WORD(®->mctr, 0xf1); 980 else 981 WRT_REG_WORD(®->mctr, 0xf2); 982 RD_REG_WORD(®->mctr); /* PCI Posting. */ 983 984 /* Release RISC. */ 985 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 986 } 987 } 988 989 if (rval == QLA_SUCCESS) { 990 /* Get RISC SRAM. */ 991 risc_address = 0x1000; 992 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); 993 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 994 } 995 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; 996 cnt++, risc_address++) { 997 WRT_MAILBOX_REG(ha, reg, 1, risc_address); 998 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 999 1000 for (timer = 6000000; timer != 0; timer--) { 1001 /* Check for pending interrupts. */ 1002 if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { 1003 if (RD_REG_WORD(®->semaphore) & BIT_0) { 1004 set_bit(MBX_INTERRUPT, 1005 &ha->mbx_cmd_flags); 1006 1007 mb0 = RD_MAILBOX_REG(ha, reg, 0); 1008 mb2 = RD_MAILBOX_REG(ha, reg, 2); 1009 1010 WRT_REG_WORD(®->semaphore, 0); 1011 WRT_REG_WORD(®->hccr, 1012 HCCR_CLR_RISC_INT); 1013 RD_REG_WORD(®->hccr); 1014 break; 1015 } 1016 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 1017 RD_REG_WORD(®->hccr); 1018 } 1019 udelay(5); 1020 } 1021 1022 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1023 rval = mb0 & MBS_MASK; 1024 fw->risc_ram[cnt] = htons(mb2); 1025 } else { 1026 rval = QLA_FUNCTION_FAILED; 1027 } 1028 } 1029 1030 if (rval == QLA_SUCCESS) 1031 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); 1032 1033 qla2xxx_dump_post_process(base_vha, rval); 1034 1035 qla2100_fw_dump_failed: 1036 #ifndef __CHECKER__ 1037 if (!hardware_locked) 1038 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1039 #else 1040 ; 1041 #endif 1042 } 1043 1044 void 1045 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1046 { 1047 int rval; 1048 uint32_t cnt; 1049 struct qla_hw_data *ha = vha->hw; 1050 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1051 uint32_t __iomem *dmp_reg; 1052 uint32_t *iter_reg; 1053 uint16_t __iomem *mbx_reg; 1054 unsigned long flags; 1055 struct qla24xx_fw_dump *fw; 1056 void *nxt; 1057 void *nxt_chain; 1058 uint32_t *last_chain = NULL; 1059 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1060 1061 if (IS_P3P_TYPE(ha)) 1062 return; 1063 1064 flags = 0; 1065 ha->fw_dump_cap_flags = 0; 1066 1067 #ifndef __CHECKER__ 1068 if (!hardware_locked) 1069 spin_lock_irqsave(&ha->hardware_lock, flags); 1070 #endif 1071 1072 if (!ha->fw_dump) { 1073 ql_log(ql_log_warn, vha, 0xd006, 1074 "No buffer available for dump.\n"); 1075 goto qla24xx_fw_dump_failed; 1076 } 1077 1078 if (ha->fw_dumped) { 1079 ql_log(ql_log_warn, vha, 0xd007, 1080 "Firmware has been previously dumped (%p) " 1081 "-- ignoring request.\n", 1082 ha->fw_dump); 1083 goto qla24xx_fw_dump_failed; 1084 } 1085 fw = &ha->fw_dump->isp.isp24; 1086 qla2xxx_prep_dump(ha, ha->fw_dump); 1087 1088 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1089 1090 /* 1091 * Pause RISC. No need to track timeout, as resetting the chip 1092 * is the right approach incase of pause timeout 1093 */ 1094 qla24xx_pause_risc(reg, ha); 1095 1096 /* Host interface registers. */ 1097 dmp_reg = ®->flash_addr; 1098 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1099 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1100 1101 /* Disable interrupts. */ 1102 WRT_REG_DWORD(®->ictrl, 0); 1103 RD_REG_DWORD(®->ictrl); 1104 1105 /* Shadow registers. */ 1106 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1107 RD_REG_DWORD(®->iobase_addr); 1108 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1109 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1110 1111 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1112 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1113 1114 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1115 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1116 1117 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1118 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1119 1120 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1121 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1122 1123 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1124 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1125 1126 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1127 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1128 1129 /* Mailbox registers. */ 1130 mbx_reg = ®->mailbox0; 1131 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1132 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1133 1134 /* Transfer sequence registers. */ 1135 iter_reg = fw->xseq_gp_reg; 1136 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1137 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1138 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1139 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1140 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1141 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1142 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1143 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1144 1145 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); 1146 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1147 1148 /* Receive sequence registers. */ 1149 iter_reg = fw->rseq_gp_reg; 1150 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1151 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1152 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1153 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1154 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1155 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1156 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1157 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1158 1159 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); 1160 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1161 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1162 1163 /* Command DMA registers. */ 1164 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1165 1166 /* Queues. */ 1167 iter_reg = fw->req0_dma_reg; 1168 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1169 dmp_reg = ®->iobase_q; 1170 for (cnt = 0; cnt < 7; cnt++) 1171 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1172 1173 iter_reg = fw->resp0_dma_reg; 1174 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1175 dmp_reg = ®->iobase_q; 1176 for (cnt = 0; cnt < 7; cnt++) 1177 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1178 1179 iter_reg = fw->req1_dma_reg; 1180 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1181 dmp_reg = ®->iobase_q; 1182 for (cnt = 0; cnt < 7; cnt++) 1183 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1184 1185 /* Transmit DMA registers. */ 1186 iter_reg = fw->xmt0_dma_reg; 1187 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1188 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1189 1190 iter_reg = fw->xmt1_dma_reg; 1191 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1192 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1193 1194 iter_reg = fw->xmt2_dma_reg; 1195 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1196 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1197 1198 iter_reg = fw->xmt3_dma_reg; 1199 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1200 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1201 1202 iter_reg = fw->xmt4_dma_reg; 1203 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1204 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1205 1206 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1207 1208 /* Receive DMA registers. */ 1209 iter_reg = fw->rcvt0_data_dma_reg; 1210 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1211 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1212 1213 iter_reg = fw->rcvt1_data_dma_reg; 1214 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1215 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1216 1217 /* RISC registers. */ 1218 iter_reg = fw->risc_gp_reg; 1219 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1220 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1221 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1222 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1223 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1224 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1225 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1226 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1227 1228 /* Local memory controller registers. */ 1229 iter_reg = fw->lmc_reg; 1230 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1231 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1232 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1233 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1234 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1235 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1236 qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1237 1238 /* Fibre Protocol Module registers. */ 1239 iter_reg = fw->fpm_hdw_reg; 1240 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1241 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1242 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1243 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1244 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1245 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1246 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1247 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1248 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1249 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1250 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1251 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1252 1253 /* Frame Buffer registers. */ 1254 iter_reg = fw->fb_hdw_reg; 1255 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1256 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1257 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1258 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1259 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1260 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1261 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1262 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1263 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1264 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1265 qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1266 1267 rval = qla24xx_soft_reset(ha); 1268 if (rval != QLA_SUCCESS) 1269 goto qla24xx_fw_dump_failed_0; 1270 1271 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1272 &nxt); 1273 if (rval != QLA_SUCCESS) 1274 goto qla24xx_fw_dump_failed_0; 1275 1276 nxt = qla2xxx_copy_queues(ha, nxt); 1277 1278 qla24xx_copy_eft(ha, nxt); 1279 1280 nxt_chain = (void *)ha->fw_dump + ha->chain_offset; 1281 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1282 if (last_chain) { 1283 ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); 1284 *last_chain |= htonl(DUMP_CHAIN_LAST); 1285 } 1286 1287 /* Adjust valid length. */ 1288 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1289 1290 qla24xx_fw_dump_failed_0: 1291 qla2xxx_dump_post_process(base_vha, rval); 1292 1293 qla24xx_fw_dump_failed: 1294 #ifndef __CHECKER__ 1295 if (!hardware_locked) 1296 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1297 #else 1298 ; 1299 #endif 1300 } 1301 1302 void 1303 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1304 { 1305 int rval; 1306 uint32_t cnt; 1307 struct qla_hw_data *ha = vha->hw; 1308 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1309 uint32_t __iomem *dmp_reg; 1310 uint32_t *iter_reg; 1311 uint16_t __iomem *mbx_reg; 1312 unsigned long flags; 1313 struct qla25xx_fw_dump *fw; 1314 void *nxt, *nxt_chain; 1315 uint32_t *last_chain = NULL; 1316 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1317 1318 flags = 0; 1319 ha->fw_dump_cap_flags = 0; 1320 1321 #ifndef __CHECKER__ 1322 if (!hardware_locked) 1323 spin_lock_irqsave(&ha->hardware_lock, flags); 1324 #endif 1325 1326 if (!ha->fw_dump) { 1327 ql_log(ql_log_warn, vha, 0xd008, 1328 "No buffer available for dump.\n"); 1329 goto qla25xx_fw_dump_failed; 1330 } 1331 1332 if (ha->fw_dumped) { 1333 ql_log(ql_log_warn, vha, 0xd009, 1334 "Firmware has been previously dumped (%p) " 1335 "-- ignoring request.\n", 1336 ha->fw_dump); 1337 goto qla25xx_fw_dump_failed; 1338 } 1339 fw = &ha->fw_dump->isp.isp25; 1340 qla2xxx_prep_dump(ha, ha->fw_dump); 1341 ha->fw_dump->version = htonl(2); 1342 1343 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1344 1345 /* 1346 * Pause RISC. No need to track timeout, as resetting the chip 1347 * is the right approach incase of pause timeout 1348 */ 1349 qla24xx_pause_risc(reg, ha); 1350 1351 /* Host/Risc registers. */ 1352 iter_reg = fw->host_risc_reg; 1353 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1354 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1355 1356 /* PCIe registers. */ 1357 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1358 RD_REG_DWORD(®->iobase_addr); 1359 WRT_REG_DWORD(®->iobase_window, 0x01); 1360 dmp_reg = ®->iobase_c4; 1361 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1362 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1363 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1364 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1365 1366 WRT_REG_DWORD(®->iobase_window, 0x00); 1367 RD_REG_DWORD(®->iobase_window); 1368 1369 /* Host interface registers. */ 1370 dmp_reg = ®->flash_addr; 1371 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1372 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1373 1374 /* Disable interrupts. */ 1375 WRT_REG_DWORD(®->ictrl, 0); 1376 RD_REG_DWORD(®->ictrl); 1377 1378 /* Shadow registers. */ 1379 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1380 RD_REG_DWORD(®->iobase_addr); 1381 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1382 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1383 1384 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1385 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1386 1387 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1388 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1389 1390 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1391 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1392 1393 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1394 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1395 1396 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1397 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1398 1399 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1400 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1401 1402 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1403 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1404 1405 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1406 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1407 1408 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1409 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1410 1411 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1412 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1413 1414 /* RISC I/O register. */ 1415 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1416 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1417 1418 /* Mailbox registers. */ 1419 mbx_reg = ®->mailbox0; 1420 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1421 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1422 1423 /* Transfer sequence registers. */ 1424 iter_reg = fw->xseq_gp_reg; 1425 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1426 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1427 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1428 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1429 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1430 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1431 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1432 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1433 1434 iter_reg = fw->xseq_0_reg; 1435 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1436 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1437 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1438 1439 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1440 1441 /* Receive sequence registers. */ 1442 iter_reg = fw->rseq_gp_reg; 1443 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1444 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1445 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1446 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1447 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1448 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1449 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1450 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1451 1452 iter_reg = fw->rseq_0_reg; 1453 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1454 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1455 1456 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1457 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1458 1459 /* Auxiliary sequence registers. */ 1460 iter_reg = fw->aseq_gp_reg; 1461 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1462 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1463 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1464 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1465 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1466 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1467 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1468 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1469 1470 iter_reg = fw->aseq_0_reg; 1471 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1472 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1473 1474 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1475 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1476 1477 /* Command DMA registers. */ 1478 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1479 1480 /* Queues. */ 1481 iter_reg = fw->req0_dma_reg; 1482 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1483 dmp_reg = ®->iobase_q; 1484 for (cnt = 0; cnt < 7; cnt++) 1485 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1486 1487 iter_reg = fw->resp0_dma_reg; 1488 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1489 dmp_reg = ®->iobase_q; 1490 for (cnt = 0; cnt < 7; cnt++) 1491 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1492 1493 iter_reg = fw->req1_dma_reg; 1494 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1495 dmp_reg = ®->iobase_q; 1496 for (cnt = 0; cnt < 7; cnt++) 1497 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1498 1499 /* Transmit DMA registers. */ 1500 iter_reg = fw->xmt0_dma_reg; 1501 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1502 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1503 1504 iter_reg = fw->xmt1_dma_reg; 1505 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1506 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1507 1508 iter_reg = fw->xmt2_dma_reg; 1509 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1510 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1511 1512 iter_reg = fw->xmt3_dma_reg; 1513 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1514 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1515 1516 iter_reg = fw->xmt4_dma_reg; 1517 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1518 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1519 1520 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1521 1522 /* Receive DMA registers. */ 1523 iter_reg = fw->rcvt0_data_dma_reg; 1524 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1525 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1526 1527 iter_reg = fw->rcvt1_data_dma_reg; 1528 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1529 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1530 1531 /* RISC registers. */ 1532 iter_reg = fw->risc_gp_reg; 1533 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1534 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1535 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1536 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1537 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1538 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1539 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1540 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1541 1542 /* Local memory controller registers. */ 1543 iter_reg = fw->lmc_reg; 1544 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1545 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1546 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1547 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1548 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1549 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1550 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1551 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1552 1553 /* Fibre Protocol Module registers. */ 1554 iter_reg = fw->fpm_hdw_reg; 1555 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1556 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1557 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1558 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1559 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1560 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1561 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1562 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1563 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1564 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1565 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1566 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1567 1568 /* Frame Buffer registers. */ 1569 iter_reg = fw->fb_hdw_reg; 1570 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1571 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1572 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1573 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1574 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1575 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1576 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1577 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1578 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1579 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1580 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1581 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1582 1583 /* Multi queue registers */ 1584 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1585 &last_chain); 1586 1587 rval = qla24xx_soft_reset(ha); 1588 if (rval != QLA_SUCCESS) 1589 goto qla25xx_fw_dump_failed_0; 1590 1591 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1592 &nxt); 1593 if (rval != QLA_SUCCESS) 1594 goto qla25xx_fw_dump_failed_0; 1595 1596 nxt = qla2xxx_copy_queues(ha, nxt); 1597 1598 qla24xx_copy_eft(ha, nxt); 1599 1600 /* Chain entries -- started with MQ. */ 1601 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1602 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 1603 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1604 if (last_chain) { 1605 ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); 1606 *last_chain |= htonl(DUMP_CHAIN_LAST); 1607 } 1608 1609 /* Adjust valid length. */ 1610 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1611 1612 qla25xx_fw_dump_failed_0: 1613 qla2xxx_dump_post_process(base_vha, rval); 1614 1615 qla25xx_fw_dump_failed: 1616 #ifndef __CHECKER__ 1617 if (!hardware_locked) 1618 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1619 #else 1620 ; 1621 #endif 1622 } 1623 1624 void 1625 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1626 { 1627 int rval; 1628 uint32_t cnt; 1629 struct qla_hw_data *ha = vha->hw; 1630 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1631 uint32_t __iomem *dmp_reg; 1632 uint32_t *iter_reg; 1633 uint16_t __iomem *mbx_reg; 1634 unsigned long flags; 1635 struct qla81xx_fw_dump *fw; 1636 void *nxt, *nxt_chain; 1637 uint32_t *last_chain = NULL; 1638 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1639 1640 flags = 0; 1641 ha->fw_dump_cap_flags = 0; 1642 1643 #ifndef __CHECKER__ 1644 if (!hardware_locked) 1645 spin_lock_irqsave(&ha->hardware_lock, flags); 1646 #endif 1647 1648 if (!ha->fw_dump) { 1649 ql_log(ql_log_warn, vha, 0xd00a, 1650 "No buffer available for dump.\n"); 1651 goto qla81xx_fw_dump_failed; 1652 } 1653 1654 if (ha->fw_dumped) { 1655 ql_log(ql_log_warn, vha, 0xd00b, 1656 "Firmware has been previously dumped (%p) " 1657 "-- ignoring request.\n", 1658 ha->fw_dump); 1659 goto qla81xx_fw_dump_failed; 1660 } 1661 fw = &ha->fw_dump->isp.isp81; 1662 qla2xxx_prep_dump(ha, ha->fw_dump); 1663 1664 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1665 1666 /* 1667 * Pause RISC. No need to track timeout, as resetting the chip 1668 * is the right approach incase of pause timeout 1669 */ 1670 qla24xx_pause_risc(reg, ha); 1671 1672 /* Host/Risc registers. */ 1673 iter_reg = fw->host_risc_reg; 1674 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1675 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1676 1677 /* PCIe registers. */ 1678 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1679 RD_REG_DWORD(®->iobase_addr); 1680 WRT_REG_DWORD(®->iobase_window, 0x01); 1681 dmp_reg = ®->iobase_c4; 1682 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1683 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1684 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1685 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1686 1687 WRT_REG_DWORD(®->iobase_window, 0x00); 1688 RD_REG_DWORD(®->iobase_window); 1689 1690 /* Host interface registers. */ 1691 dmp_reg = ®->flash_addr; 1692 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1693 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1694 1695 /* Disable interrupts. */ 1696 WRT_REG_DWORD(®->ictrl, 0); 1697 RD_REG_DWORD(®->ictrl); 1698 1699 /* Shadow registers. */ 1700 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1701 RD_REG_DWORD(®->iobase_addr); 1702 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1703 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1704 1705 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1706 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1707 1708 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1709 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1710 1711 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1712 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1713 1714 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1715 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1716 1717 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1718 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1719 1720 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1721 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1722 1723 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1724 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1725 1726 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1727 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1728 1729 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1730 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1731 1732 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1733 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1734 1735 /* RISC I/O register. */ 1736 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1737 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1738 1739 /* Mailbox registers. */ 1740 mbx_reg = ®->mailbox0; 1741 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1742 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1743 1744 /* Transfer sequence registers. */ 1745 iter_reg = fw->xseq_gp_reg; 1746 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1747 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1748 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1749 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1750 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1751 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1752 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1753 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1754 1755 iter_reg = fw->xseq_0_reg; 1756 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1757 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1758 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1759 1760 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1761 1762 /* Receive sequence registers. */ 1763 iter_reg = fw->rseq_gp_reg; 1764 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1765 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1766 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1767 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1768 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1769 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1770 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1771 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1772 1773 iter_reg = fw->rseq_0_reg; 1774 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1775 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1776 1777 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1778 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1779 1780 /* Auxiliary sequence registers. */ 1781 iter_reg = fw->aseq_gp_reg; 1782 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1783 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1784 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1785 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1786 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1787 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1788 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1789 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1790 1791 iter_reg = fw->aseq_0_reg; 1792 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1793 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1794 1795 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1796 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1797 1798 /* Command DMA registers. */ 1799 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1800 1801 /* Queues. */ 1802 iter_reg = fw->req0_dma_reg; 1803 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1804 dmp_reg = ®->iobase_q; 1805 for (cnt = 0; cnt < 7; cnt++) 1806 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1807 1808 iter_reg = fw->resp0_dma_reg; 1809 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1810 dmp_reg = ®->iobase_q; 1811 for (cnt = 0; cnt < 7; cnt++) 1812 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1813 1814 iter_reg = fw->req1_dma_reg; 1815 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1816 dmp_reg = ®->iobase_q; 1817 for (cnt = 0; cnt < 7; cnt++) 1818 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1819 1820 /* Transmit DMA registers. */ 1821 iter_reg = fw->xmt0_dma_reg; 1822 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1823 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1824 1825 iter_reg = fw->xmt1_dma_reg; 1826 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1827 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1828 1829 iter_reg = fw->xmt2_dma_reg; 1830 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1831 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1832 1833 iter_reg = fw->xmt3_dma_reg; 1834 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1835 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1836 1837 iter_reg = fw->xmt4_dma_reg; 1838 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1839 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1840 1841 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1842 1843 /* Receive DMA registers. */ 1844 iter_reg = fw->rcvt0_data_dma_reg; 1845 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1846 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1847 1848 iter_reg = fw->rcvt1_data_dma_reg; 1849 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1850 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1851 1852 /* RISC registers. */ 1853 iter_reg = fw->risc_gp_reg; 1854 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1855 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1856 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1857 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1858 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1859 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1860 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1861 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1862 1863 /* Local memory controller registers. */ 1864 iter_reg = fw->lmc_reg; 1865 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1866 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1867 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1868 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1869 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1870 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1871 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1872 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1873 1874 /* Fibre Protocol Module registers. */ 1875 iter_reg = fw->fpm_hdw_reg; 1876 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1877 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1878 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1879 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1880 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1881 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1882 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1883 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1884 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1885 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1886 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1887 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1888 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); 1889 qla24xx_read_window(reg, 0x40D0, 16, iter_reg); 1890 1891 /* Frame Buffer registers. */ 1892 iter_reg = fw->fb_hdw_reg; 1893 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1894 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1895 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1896 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1897 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1898 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1899 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1900 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1901 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1902 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1903 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1904 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); 1905 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1906 1907 /* Multi queue registers */ 1908 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1909 &last_chain); 1910 1911 rval = qla24xx_soft_reset(ha); 1912 if (rval != QLA_SUCCESS) 1913 goto qla81xx_fw_dump_failed_0; 1914 1915 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1916 &nxt); 1917 if (rval != QLA_SUCCESS) 1918 goto qla81xx_fw_dump_failed_0; 1919 1920 nxt = qla2xxx_copy_queues(ha, nxt); 1921 1922 qla24xx_copy_eft(ha, nxt); 1923 1924 /* Chain entries -- started with MQ. */ 1925 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1926 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 1927 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1928 if (last_chain) { 1929 ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); 1930 *last_chain |= htonl(DUMP_CHAIN_LAST); 1931 } 1932 1933 /* Adjust valid length. */ 1934 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1935 1936 qla81xx_fw_dump_failed_0: 1937 qla2xxx_dump_post_process(base_vha, rval); 1938 1939 qla81xx_fw_dump_failed: 1940 #ifndef __CHECKER__ 1941 if (!hardware_locked) 1942 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1943 #else 1944 ; 1945 #endif 1946 } 1947 1948 void 1949 qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1950 { 1951 int rval; 1952 uint32_t cnt; 1953 struct qla_hw_data *ha = vha->hw; 1954 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1955 uint32_t __iomem *dmp_reg; 1956 uint32_t *iter_reg; 1957 uint16_t __iomem *mbx_reg; 1958 unsigned long flags; 1959 struct qla83xx_fw_dump *fw; 1960 void *nxt, *nxt_chain; 1961 uint32_t *last_chain = NULL; 1962 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1963 1964 flags = 0; 1965 ha->fw_dump_cap_flags = 0; 1966 1967 #ifndef __CHECKER__ 1968 if (!hardware_locked) 1969 spin_lock_irqsave(&ha->hardware_lock, flags); 1970 #endif 1971 1972 if (!ha->fw_dump) { 1973 ql_log(ql_log_warn, vha, 0xd00c, 1974 "No buffer available for dump!!!\n"); 1975 goto qla83xx_fw_dump_failed; 1976 } 1977 1978 if (ha->fw_dumped) { 1979 ql_log(ql_log_warn, vha, 0xd00d, 1980 "Firmware has been previously dumped (%p) -- ignoring " 1981 "request...\n", ha->fw_dump); 1982 goto qla83xx_fw_dump_failed; 1983 } 1984 fw = &ha->fw_dump->isp.isp83; 1985 qla2xxx_prep_dump(ha, ha->fw_dump); 1986 1987 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1988 1989 /* 1990 * Pause RISC. No need to track timeout, as resetting the chip 1991 * is the right approach incase of pause timeout 1992 */ 1993 qla24xx_pause_risc(reg, ha); 1994 1995 WRT_REG_DWORD(®->iobase_addr, 0x6000); 1996 dmp_reg = ®->iobase_window; 1997 RD_REG_DWORD(dmp_reg); 1998 WRT_REG_DWORD(dmp_reg, 0); 1999 2000 dmp_reg = ®->unused_4_1[0]; 2001 RD_REG_DWORD(dmp_reg); 2002 WRT_REG_DWORD(dmp_reg, 0); 2003 2004 WRT_REG_DWORD(®->iobase_addr, 0x6010); 2005 dmp_reg = ®->unused_4_1[2]; 2006 RD_REG_DWORD(dmp_reg); 2007 WRT_REG_DWORD(dmp_reg, 0); 2008 2009 /* select PCR and disable ecc checking and correction */ 2010 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 2011 RD_REG_DWORD(®->iobase_addr); 2012 WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */ 2013 2014 /* Host/Risc registers. */ 2015 iter_reg = fw->host_risc_reg; 2016 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 2017 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); 2018 qla24xx_read_window(reg, 0x7040, 16, iter_reg); 2019 2020 /* PCIe registers. */ 2021 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 2022 RD_REG_DWORD(®->iobase_addr); 2023 WRT_REG_DWORD(®->iobase_window, 0x01); 2024 dmp_reg = ®->iobase_c4; 2025 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 2026 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 2027 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 2028 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 2029 2030 WRT_REG_DWORD(®->iobase_window, 0x00); 2031 RD_REG_DWORD(®->iobase_window); 2032 2033 /* Host interface registers. */ 2034 dmp_reg = ®->flash_addr; 2035 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 2036 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 2037 2038 /* Disable interrupts. */ 2039 WRT_REG_DWORD(®->ictrl, 0); 2040 RD_REG_DWORD(®->ictrl); 2041 2042 /* Shadow registers. */ 2043 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 2044 RD_REG_DWORD(®->iobase_addr); 2045 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 2046 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2047 2048 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 2049 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2050 2051 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 2052 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2053 2054 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 2055 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2056 2057 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 2058 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2059 2060 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 2061 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2062 2063 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 2064 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2065 2066 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 2067 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2068 2069 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 2070 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2071 2072 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 2073 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2074 2075 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 2076 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 2077 2078 /* RISC I/O register. */ 2079 WRT_REG_DWORD(®->iobase_addr, 0x0010); 2080 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 2081 2082 /* Mailbox registers. */ 2083 mbx_reg = ®->mailbox0; 2084 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 2085 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 2086 2087 /* Transfer sequence registers. */ 2088 iter_reg = fw->xseq_gp_reg; 2089 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); 2090 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); 2091 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); 2092 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); 2093 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); 2094 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); 2095 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); 2096 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); 2097 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 2098 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 2099 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 2100 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 2101 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 2102 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 2103 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 2104 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 2105 2106 iter_reg = fw->xseq_0_reg; 2107 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 2108 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 2109 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 2110 2111 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 2112 2113 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); 2114 2115 /* Receive sequence registers. */ 2116 iter_reg = fw->rseq_gp_reg; 2117 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); 2118 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); 2119 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); 2120 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); 2121 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); 2122 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); 2123 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); 2124 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); 2125 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 2126 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 2127 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 2128 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 2129 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 2130 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 2131 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 2132 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 2133 2134 iter_reg = fw->rseq_0_reg; 2135 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 2136 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 2137 2138 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 2139 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 2140 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); 2141 2142 /* Auxiliary sequence registers. */ 2143 iter_reg = fw->aseq_gp_reg; 2144 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 2145 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 2146 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 2147 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 2148 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 2149 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 2150 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 2151 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); 2152 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); 2153 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); 2154 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); 2155 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); 2156 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); 2157 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); 2158 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); 2159 qla24xx_read_window(reg, 0xB170, 16, iter_reg); 2160 2161 iter_reg = fw->aseq_0_reg; 2162 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 2163 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 2164 2165 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 2166 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 2167 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); 2168 2169 /* Command DMA registers. */ 2170 iter_reg = fw->cmd_dma_reg; 2171 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); 2172 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); 2173 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); 2174 qla24xx_read_window(reg, 0x71F0, 16, iter_reg); 2175 2176 /* Queues. */ 2177 iter_reg = fw->req0_dma_reg; 2178 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 2179 dmp_reg = ®->iobase_q; 2180 for (cnt = 0; cnt < 7; cnt++) 2181 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2182 2183 iter_reg = fw->resp0_dma_reg; 2184 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 2185 dmp_reg = ®->iobase_q; 2186 for (cnt = 0; cnt < 7; cnt++) 2187 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2188 2189 iter_reg = fw->req1_dma_reg; 2190 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 2191 dmp_reg = ®->iobase_q; 2192 for (cnt = 0; cnt < 7; cnt++) 2193 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2194 2195 /* Transmit DMA registers. */ 2196 iter_reg = fw->xmt0_dma_reg; 2197 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 2198 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 2199 2200 iter_reg = fw->xmt1_dma_reg; 2201 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 2202 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 2203 2204 iter_reg = fw->xmt2_dma_reg; 2205 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 2206 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 2207 2208 iter_reg = fw->xmt3_dma_reg; 2209 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 2210 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 2211 2212 iter_reg = fw->xmt4_dma_reg; 2213 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 2214 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 2215 2216 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 2217 2218 /* Receive DMA registers. */ 2219 iter_reg = fw->rcvt0_data_dma_reg; 2220 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 2221 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 2222 2223 iter_reg = fw->rcvt1_data_dma_reg; 2224 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 2225 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 2226 2227 /* RISC registers. */ 2228 iter_reg = fw->risc_gp_reg; 2229 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 2230 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 2231 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 2232 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 2233 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 2234 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 2235 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 2236 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 2237 2238 /* Local memory controller registers. */ 2239 iter_reg = fw->lmc_reg; 2240 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 2241 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 2242 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 2243 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 2244 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 2245 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 2246 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 2247 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 2248 2249 /* Fibre Protocol Module registers. */ 2250 iter_reg = fw->fpm_hdw_reg; 2251 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 2252 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 2253 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 2254 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 2255 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 2256 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 2257 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 2258 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 2259 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 2260 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 2261 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 2262 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 2263 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); 2264 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); 2265 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); 2266 qla24xx_read_window(reg, 0x40F0, 16, iter_reg); 2267 2268 /* RQ0 Array registers. */ 2269 iter_reg = fw->rq0_array_reg; 2270 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); 2271 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); 2272 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); 2273 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); 2274 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); 2275 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); 2276 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); 2277 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); 2278 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); 2279 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); 2280 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); 2281 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); 2282 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); 2283 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); 2284 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); 2285 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); 2286 2287 /* RQ1 Array registers. */ 2288 iter_reg = fw->rq1_array_reg; 2289 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); 2290 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); 2291 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); 2292 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); 2293 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); 2294 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); 2295 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); 2296 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); 2297 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); 2298 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); 2299 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); 2300 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); 2301 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); 2302 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); 2303 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); 2304 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); 2305 2306 /* RP0 Array registers. */ 2307 iter_reg = fw->rp0_array_reg; 2308 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); 2309 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); 2310 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); 2311 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); 2312 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); 2313 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); 2314 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); 2315 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); 2316 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); 2317 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); 2318 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); 2319 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); 2320 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); 2321 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); 2322 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); 2323 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); 2324 2325 /* RP1 Array registers. */ 2326 iter_reg = fw->rp1_array_reg; 2327 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); 2328 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); 2329 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); 2330 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); 2331 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); 2332 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); 2333 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); 2334 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); 2335 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); 2336 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); 2337 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); 2338 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); 2339 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); 2340 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); 2341 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); 2342 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); 2343 2344 iter_reg = fw->at0_array_reg; 2345 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); 2346 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); 2347 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); 2348 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); 2349 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); 2350 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); 2351 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); 2352 qla24xx_read_window(reg, 0x70F0, 16, iter_reg); 2353 2354 /* I/O Queue Control registers. */ 2355 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); 2356 2357 /* Frame Buffer registers. */ 2358 iter_reg = fw->fb_hdw_reg; 2359 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 2360 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 2361 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 2362 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 2363 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 2364 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); 2365 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); 2366 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 2367 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 2368 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 2369 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 2370 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 2371 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 2372 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); 2373 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); 2374 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); 2375 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); 2376 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); 2377 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); 2378 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); 2379 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); 2380 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); 2381 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); 2382 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); 2383 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); 2384 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); 2385 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 2386 2387 /* Multi queue registers */ 2388 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 2389 &last_chain); 2390 2391 rval = qla24xx_soft_reset(ha); 2392 if (rval != QLA_SUCCESS) { 2393 ql_log(ql_log_warn, vha, 0xd00e, 2394 "SOFT RESET FAILED, forcing continuation of dump!!!\n"); 2395 rval = QLA_SUCCESS; 2396 2397 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n"); 2398 2399 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); 2400 RD_REG_DWORD(®->hccr); 2401 2402 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); 2403 RD_REG_DWORD(®->hccr); 2404 2405 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 2406 RD_REG_DWORD(®->hccr); 2407 2408 for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--) 2409 udelay(5); 2410 2411 if (!cnt) { 2412 nxt = fw->code_ram; 2413 nxt += sizeof(fw->code_ram); 2414 nxt += (ha->fw_memory_size - 0x100000 + 1); 2415 goto copy_queue; 2416 } else { 2417 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); 2418 ql_log(ql_log_warn, vha, 0xd010, 2419 "bigger hammer success?\n"); 2420 } 2421 } 2422 2423 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 2424 &nxt); 2425 if (rval != QLA_SUCCESS) 2426 goto qla83xx_fw_dump_failed_0; 2427 2428 copy_queue: 2429 nxt = qla2xxx_copy_queues(ha, nxt); 2430 2431 qla24xx_copy_eft(ha, nxt); 2432 2433 /* Chain entries -- started with MQ. */ 2434 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 2435 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 2436 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 2437 if (last_chain) { 2438 ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); 2439 *last_chain |= htonl(DUMP_CHAIN_LAST); 2440 } 2441 2442 /* Adjust valid length. */ 2443 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 2444 2445 qla83xx_fw_dump_failed_0: 2446 qla2xxx_dump_post_process(base_vha, rval); 2447 2448 qla83xx_fw_dump_failed: 2449 #ifndef __CHECKER__ 2450 if (!hardware_locked) 2451 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2452 #else 2453 ; 2454 #endif 2455 } 2456 2457 /****************************************************************************/ 2458 /* Driver Debug Functions. */ 2459 /****************************************************************************/ 2460 2461 static inline int 2462 ql_mask_match(uint32_t level) 2463 { 2464 if (ql2xextended_error_logging == 1) 2465 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 2466 return (level & ql2xextended_error_logging) == level; 2467 } 2468 2469 /* 2470 * This function is for formatting and logging debug information. 2471 * It is to be used when vha is available. It formats the message 2472 * and logs it to the messages file. 2473 * parameters: 2474 * level: The level of the debug messages to be printed. 2475 * If ql2xextended_error_logging value is correctly set, 2476 * this message will appear in the messages file. 2477 * vha: Pointer to the scsi_qla_host_t. 2478 * id: This is a unique identifier for the level. It identifies the 2479 * part of the code from where the message originated. 2480 * msg: The message to be displayed. 2481 */ 2482 void 2483 ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) 2484 { 2485 va_list va; 2486 struct va_format vaf; 2487 2488 if (!ql_mask_match(level)) 2489 return; 2490 2491 va_start(va, fmt); 2492 2493 vaf.fmt = fmt; 2494 vaf.va = &va; 2495 2496 if (vha != NULL) { 2497 const struct pci_dev *pdev = vha->hw->pdev; 2498 /* <module-name> <pci-name> <msg-id>:<host> Message */ 2499 pr_warn("%s [%s]-%04x:%ld: %pV", 2500 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, 2501 vha->host_no, &vaf); 2502 } else { 2503 pr_warn("%s [%s]-%04x: : %pV", 2504 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); 2505 } 2506 2507 va_end(va); 2508 2509 } 2510 2511 /* 2512 * This function is for formatting and logging debug information. 2513 * It is to be used when vha is not available and pci is available, 2514 * i.e., before host allocation. It formats the message and logs it 2515 * to the messages file. 2516 * parameters: 2517 * level: The level of the debug messages to be printed. 2518 * If ql2xextended_error_logging value is correctly set, 2519 * this message will appear in the messages file. 2520 * pdev: Pointer to the struct pci_dev. 2521 * id: This is a unique id for the level. It identifies the part 2522 * of the code from where the message originated. 2523 * msg: The message to be displayed. 2524 */ 2525 void 2526 ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, 2527 const char *fmt, ...) 2528 { 2529 va_list va; 2530 struct va_format vaf; 2531 2532 if (pdev == NULL) 2533 return; 2534 if (!ql_mask_match(level)) 2535 return; 2536 2537 va_start(va, fmt); 2538 2539 vaf.fmt = fmt; 2540 vaf.va = &va; 2541 2542 /* <module-name> <dev-name>:<msg-id> Message */ 2543 pr_warn("%s [%s]-%04x: : %pV", 2544 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf); 2545 2546 va_end(va); 2547 } 2548 2549 /* 2550 * This function is for formatting and logging log messages. 2551 * It is to be used when vha is available. It formats the message 2552 * and logs it to the messages file. All the messages will be logged 2553 * irrespective of value of ql2xextended_error_logging. 2554 * parameters: 2555 * level: The level of the log messages to be printed in the 2556 * messages file. 2557 * vha: Pointer to the scsi_qla_host_t 2558 * id: This is a unique id for the level. It identifies the 2559 * part of the code from where the message originated. 2560 * msg: The message to be displayed. 2561 */ 2562 void 2563 ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) 2564 { 2565 va_list va; 2566 struct va_format vaf; 2567 char pbuf[128]; 2568 2569 if (level > ql_errlev) 2570 return; 2571 2572 if (vha != NULL) { 2573 const struct pci_dev *pdev = vha->hw->pdev; 2574 /* <module-name> <msg-id>:<host> Message */ 2575 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", 2576 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no); 2577 } else { 2578 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2579 QL_MSGHDR, "0000:00:00.0", id); 2580 } 2581 pbuf[sizeof(pbuf) - 1] = 0; 2582 2583 va_start(va, fmt); 2584 2585 vaf.fmt = fmt; 2586 vaf.va = &va; 2587 2588 switch (level) { 2589 case ql_log_fatal: /* FATAL LOG */ 2590 pr_crit("%s%pV", pbuf, &vaf); 2591 break; 2592 case ql_log_warn: 2593 pr_err("%s%pV", pbuf, &vaf); 2594 break; 2595 case ql_log_info: 2596 pr_warn("%s%pV", pbuf, &vaf); 2597 break; 2598 default: 2599 pr_info("%s%pV", pbuf, &vaf); 2600 break; 2601 } 2602 2603 va_end(va); 2604 } 2605 2606 /* 2607 * This function is for formatting and logging log messages. 2608 * It is to be used when vha is not available and pci is available, 2609 * i.e., before host allocation. It formats the message and logs 2610 * it to the messages file. All the messages are logged irrespective 2611 * of the value of ql2xextended_error_logging. 2612 * parameters: 2613 * level: The level of the log messages to be printed in the 2614 * messages file. 2615 * pdev: Pointer to the struct pci_dev. 2616 * id: This is a unique id for the level. It identifies the 2617 * part of the code from where the message originated. 2618 * msg: The message to be displayed. 2619 */ 2620 void 2621 ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, 2622 const char *fmt, ...) 2623 { 2624 va_list va; 2625 struct va_format vaf; 2626 char pbuf[128]; 2627 2628 if (pdev == NULL) 2629 return; 2630 if (level > ql_errlev) 2631 return; 2632 2633 /* <module-name> <dev-name>:<msg-id> Message */ 2634 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2635 QL_MSGHDR, dev_name(&(pdev->dev)), id); 2636 pbuf[sizeof(pbuf) - 1] = 0; 2637 2638 va_start(va, fmt); 2639 2640 vaf.fmt = fmt; 2641 vaf.va = &va; 2642 2643 switch (level) { 2644 case ql_log_fatal: /* FATAL LOG */ 2645 pr_crit("%s%pV", pbuf, &vaf); 2646 break; 2647 case ql_log_warn: 2648 pr_err("%s%pV", pbuf, &vaf); 2649 break; 2650 case ql_log_info: 2651 pr_warn("%s%pV", pbuf, &vaf); 2652 break; 2653 default: 2654 pr_info("%s%pV", pbuf, &vaf); 2655 break; 2656 } 2657 2658 va_end(va); 2659 } 2660 2661 void 2662 ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id) 2663 { 2664 int i; 2665 struct qla_hw_data *ha = vha->hw; 2666 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2667 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 2668 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 2669 uint16_t __iomem *mbx_reg; 2670 2671 if (!ql_mask_match(level)) 2672 return; 2673 2674 if (IS_P3P_TYPE(ha)) 2675 mbx_reg = ®82->mailbox_in[0]; 2676 else if (IS_FWI2_CAPABLE(ha)) 2677 mbx_reg = ®24->mailbox0; 2678 else 2679 mbx_reg = MAILBOX_REG(ha, reg, 0); 2680 2681 ql_dbg(level, vha, id, "Mailbox registers:\n"); 2682 for (i = 0; i < 6; i++) 2683 ql_dbg(level, vha, id, 2684 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); 2685 } 2686 2687 2688 void 2689 ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id, 2690 uint8_t *b, uint32_t size) 2691 { 2692 uint32_t cnt; 2693 uint8_t c; 2694 2695 if (!ql_mask_match(level)) 2696 return; 2697 2698 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 " 2699 "9 Ah Bh Ch Dh Eh Fh\n"); 2700 ql_dbg(level, vha, id, "----------------------------------" 2701 "----------------------------\n"); 2702 2703 ql_dbg(level, vha, id, " "); 2704 for (cnt = 0; cnt < size;) { 2705 c = *b++; 2706 printk("%02x", (uint32_t) c); 2707 cnt++; 2708 if (!(cnt % 16)) 2709 printk("\n"); 2710 else 2711 printk(" "); 2712 } 2713 if (cnt % 16) 2714 ql_dbg(level, vha, id, "\n"); 2715 } 2716