1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8 /* 9 * Table for showing the current message id in use for particular level 10 * Change this table for addition of log/debug messages. 11 * ---------------------------------------------------------------------- 12 * | Level | Last Value Used | Holes | 13 * ---------------------------------------------------------------------- 14 * | Module Init and Probe | 0x015b | 0x4b,0xba,0xfa | 15 * | | | 0x0x015a | 16 * | Mailbox commands | 0x1187 | 0x111a-0x111b | 17 * | | | 0x1155-0x1158 | 18 * | | | 0x1018-0x1019 | 19 * | | | 0x1115-0x1116 | 20 * | | | 0x10ca | 21 * | Device Discovery | 0x2095 | 0x2020-0x2022, | 22 * | | | 0x2011-0x2012, | 23 * | | | 0x2016 | 24 * | Queue Command and IO tracing | 0x3059 | 0x3006-0x300b | 25 * | | | 0x3027-0x3028 | 26 * | | | 0x303d-0x3041 | 27 * | | | 0x302d,0x3033 | 28 * | | | 0x3036,0x3038 | 29 * | | | 0x303a | 30 * | DPC Thread | 0x4023 | 0x4002,0x4013 | 31 * | Async Events | 0x5087 | 0x502b-0x502f | 32 * | | | 0x5047,0x5052 | 33 * | | | 0x5084,0x5075 | 34 * | | | 0x503d,0x5044 | 35 * | Timer Routines | 0x6012 | | 36 * | User Space Interactions | 0x70e1 | 0x7018,0x702e, | 37 * | | | 0x7020,0x7024, | 38 * | | | 0x7039,0x7045, | 39 * | | | 0x7073-0x7075, | 40 * | | | 0x707b,0x708c, | 41 * | | | 0x70a5,0x70a6, | 42 * | | | 0x70a8,0x70ab, | 43 * | | | 0x70ad-0x70ae, | 44 * | | | 0x70d1-0x70db, | 45 * | | | 0x7047,0x703b | 46 * | | | 0x70de-0x70df, | 47 * | Task Management | 0x803d | 0x8025-0x8026 | 48 * | | | 0x800b,0x8039 | 49 * | AER/EEH | 0x9011 | | 50 * | Virtual Port | 0xa007 | | 51 * | ISP82XX Specific | 0xb14c | 0xb002,0xb024 | 52 * | | | 0xb09e,0xb0ae | 53 * | | | 0xb0e0-0xb0ef | 54 * | | | 0xb085,0xb0dc | 55 * | | | 0xb107,0xb108 | 56 * | | | 0xb111,0xb11e | 57 * | | | 0xb12c,0xb12d | 58 * | | | 0xb13a,0xb142 | 59 * | | | 0xb13c-0xb140 | 60 * | | | 0xb149 | 61 * | MultiQ | 0xc00c | | 62 * | Misc | 0xd010 | | 63 * | Target Mode | 0xe070 | 0xe021 | 64 * | Target Mode Management | 0xf072 | 0xf002-0xf003 | 65 * | | | 0xf046-0xf049 | 66 * | Target Mode Task Management | 0x1000b | | 67 * ---------------------------------------------------------------------- 68 */ 69 70 #include "qla_def.h" 71 72 #include <linux/delay.h> 73 74 static uint32_t ql_dbg_offset = 0x800; 75 76 static inline void 77 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) 78 { 79 fw_dump->fw_major_version = htonl(ha->fw_major_version); 80 fw_dump->fw_minor_version = htonl(ha->fw_minor_version); 81 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); 82 fw_dump->fw_attributes = htonl(ha->fw_attributes); 83 84 fw_dump->vendor = htonl(ha->pdev->vendor); 85 fw_dump->device = htonl(ha->pdev->device); 86 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); 87 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); 88 } 89 90 static inline void * 91 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) 92 { 93 struct req_que *req = ha->req_q_map[0]; 94 struct rsp_que *rsp = ha->rsp_q_map[0]; 95 /* Request queue. */ 96 memcpy(ptr, req->ring, req->length * 97 sizeof(request_t)); 98 99 /* Response queue. */ 100 ptr += req->length * sizeof(request_t); 101 memcpy(ptr, rsp->ring, rsp->length * 102 sizeof(response_t)); 103 104 return ptr + (rsp->length * sizeof(response_t)); 105 } 106 107 static int 108 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, 109 uint32_t ram_dwords, void **nxt) 110 { 111 int rval; 112 uint32_t cnt, stat, timer, dwords, idx; 113 uint16_t mb0; 114 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 115 dma_addr_t dump_dma = ha->gid_list_dma; 116 uint32_t *dump = (uint32_t *)ha->gid_list; 117 118 rval = QLA_SUCCESS; 119 mb0 = 0; 120 121 WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); 122 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 123 124 dwords = qla2x00_gid_list_size(ha) / 4; 125 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; 126 cnt += dwords, addr += dwords) { 127 if (cnt + dwords > ram_dwords) 128 dwords = ram_dwords - cnt; 129 130 WRT_REG_WORD(®->mailbox1, LSW(addr)); 131 WRT_REG_WORD(®->mailbox8, MSW(addr)); 132 133 WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); 134 WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); 135 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); 136 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); 137 138 WRT_REG_WORD(®->mailbox4, MSW(dwords)); 139 WRT_REG_WORD(®->mailbox5, LSW(dwords)); 140 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 141 142 for (timer = 6000000; timer; timer--) { 143 /* Check for pending interrupts. */ 144 stat = RD_REG_DWORD(®->host_status); 145 if (stat & HSRX_RISC_INT) { 146 stat &= 0xff; 147 148 if (stat == 0x1 || stat == 0x2 || 149 stat == 0x10 || stat == 0x11) { 150 set_bit(MBX_INTERRUPT, 151 &ha->mbx_cmd_flags); 152 153 mb0 = RD_REG_WORD(®->mailbox0); 154 155 WRT_REG_DWORD(®->hccr, 156 HCCRX_CLR_RISC_INT); 157 RD_REG_DWORD(®->hccr); 158 break; 159 } 160 161 /* Clear this intr; it wasn't a mailbox intr */ 162 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); 163 RD_REG_DWORD(®->hccr); 164 } 165 udelay(5); 166 } 167 168 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 169 rval = mb0 & MBS_MASK; 170 for (idx = 0; idx < dwords; idx++) 171 ram[cnt + idx] = swab32(dump[idx]); 172 } else { 173 rval = QLA_FUNCTION_FAILED; 174 } 175 } 176 177 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; 178 return rval; 179 } 180 181 static int 182 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, 183 uint32_t cram_size, void **nxt) 184 { 185 int rval; 186 187 /* Code RAM. */ 188 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); 189 if (rval != QLA_SUCCESS) 190 return rval; 191 192 /* External Memory. */ 193 return qla24xx_dump_ram(ha, 0x100000, *nxt, 194 ha->fw_memory_size - 0x100000 + 1, nxt); 195 } 196 197 static uint32_t * 198 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, 199 uint32_t count, uint32_t *buf) 200 { 201 uint32_t __iomem *dmp_reg; 202 203 WRT_REG_DWORD(®->iobase_addr, iobase); 204 dmp_reg = ®->iobase_window; 205 while (count--) 206 *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); 207 208 return buf; 209 } 210 211 static inline int 212 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) 213 { 214 int rval = QLA_SUCCESS; 215 uint32_t cnt; 216 217 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); 218 for (cnt = 30000; 219 ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && 220 rval == QLA_SUCCESS; cnt--) { 221 if (cnt) 222 udelay(100); 223 else 224 rval = QLA_FUNCTION_TIMEOUT; 225 } 226 227 return rval; 228 } 229 230 static int 231 qla24xx_soft_reset(struct qla_hw_data *ha) 232 { 233 int rval = QLA_SUCCESS; 234 uint32_t cnt; 235 uint16_t mb0, wd; 236 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 237 238 /* Reset RISC. */ 239 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 240 for (cnt = 0; cnt < 30000; cnt++) { 241 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 242 break; 243 244 udelay(10); 245 } 246 247 WRT_REG_DWORD(®->ctrl_status, 248 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 249 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 250 251 udelay(100); 252 /* Wait for firmware to complete NVRAM accesses. */ 253 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); 254 for (cnt = 10000 ; cnt && mb0; cnt--) { 255 udelay(5); 256 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); 257 barrier(); 258 } 259 260 /* Wait for soft-reset to complete. */ 261 for (cnt = 0; cnt < 30000; cnt++) { 262 if ((RD_REG_DWORD(®->ctrl_status) & 263 CSRX_ISP_SOFT_RESET) == 0) 264 break; 265 266 udelay(10); 267 } 268 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 269 RD_REG_DWORD(®->hccr); /* PCI Posting. */ 270 271 for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && 272 rval == QLA_SUCCESS; cnt--) { 273 if (cnt) 274 udelay(100); 275 else 276 rval = QLA_FUNCTION_TIMEOUT; 277 } 278 279 return rval; 280 } 281 282 static int 283 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, 284 uint32_t ram_words, void **nxt) 285 { 286 int rval; 287 uint32_t cnt, stat, timer, words, idx; 288 uint16_t mb0; 289 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 290 dma_addr_t dump_dma = ha->gid_list_dma; 291 uint16_t *dump = (uint16_t *)ha->gid_list; 292 293 rval = QLA_SUCCESS; 294 mb0 = 0; 295 296 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); 297 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 298 299 words = qla2x00_gid_list_size(ha) / 2; 300 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; 301 cnt += words, addr += words) { 302 if (cnt + words > ram_words) 303 words = ram_words - cnt; 304 305 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); 306 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); 307 308 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); 309 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); 310 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); 311 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); 312 313 WRT_MAILBOX_REG(ha, reg, 4, words); 314 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 315 316 for (timer = 6000000; timer; timer--) { 317 /* Check for pending interrupts. */ 318 stat = RD_REG_DWORD(®->u.isp2300.host_status); 319 if (stat & HSR_RISC_INT) { 320 stat &= 0xff; 321 322 if (stat == 0x1 || stat == 0x2) { 323 set_bit(MBX_INTERRUPT, 324 &ha->mbx_cmd_flags); 325 326 mb0 = RD_MAILBOX_REG(ha, reg, 0); 327 328 /* Release mailbox registers. */ 329 WRT_REG_WORD(®->semaphore, 0); 330 WRT_REG_WORD(®->hccr, 331 HCCR_CLR_RISC_INT); 332 RD_REG_WORD(®->hccr); 333 break; 334 } else if (stat == 0x10 || stat == 0x11) { 335 set_bit(MBX_INTERRUPT, 336 &ha->mbx_cmd_flags); 337 338 mb0 = RD_MAILBOX_REG(ha, reg, 0); 339 340 WRT_REG_WORD(®->hccr, 341 HCCR_CLR_RISC_INT); 342 RD_REG_WORD(®->hccr); 343 break; 344 } 345 346 /* clear this intr; it wasn't a mailbox intr */ 347 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 348 RD_REG_WORD(®->hccr); 349 } 350 udelay(5); 351 } 352 353 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 354 rval = mb0 & MBS_MASK; 355 for (idx = 0; idx < words; idx++) 356 ram[cnt + idx] = swab16(dump[idx]); 357 } else { 358 rval = QLA_FUNCTION_FAILED; 359 } 360 } 361 362 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; 363 return rval; 364 } 365 366 static inline void 367 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, 368 uint16_t *buf) 369 { 370 uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; 371 372 while (count--) 373 *buf++ = htons(RD_REG_WORD(dmp_reg++)); 374 } 375 376 static inline void * 377 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) 378 { 379 if (!ha->eft) 380 return ptr; 381 382 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); 383 return ptr + ntohl(ha->fw_dump->eft_size); 384 } 385 386 static inline void * 387 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 388 { 389 uint32_t cnt; 390 uint32_t *iter_reg; 391 struct qla2xxx_fce_chain *fcec = ptr; 392 393 if (!ha->fce) 394 return ptr; 395 396 *last_chain = &fcec->type; 397 fcec->type = __constant_htonl(DUMP_CHAIN_FCE); 398 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + 399 fce_calc_size(ha->fce_bufs)); 400 fcec->size = htonl(fce_calc_size(ha->fce_bufs)); 401 fcec->addr_l = htonl(LSD(ha->fce_dma)); 402 fcec->addr_h = htonl(MSD(ha->fce_dma)); 403 404 iter_reg = fcec->eregs; 405 for (cnt = 0; cnt < 8; cnt++) 406 *iter_reg++ = htonl(ha->fce_mb[cnt]); 407 408 memcpy(iter_reg, ha->fce, ntohl(fcec->size)); 409 410 return (char *)iter_reg + ntohl(fcec->size); 411 } 412 413 static inline void * 414 qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr, 415 uint32_t **last_chain) 416 { 417 struct qla2xxx_mqueue_chain *q; 418 struct qla2xxx_mqueue_header *qh; 419 uint32_t num_queues; 420 int que; 421 struct { 422 int length; 423 void *ring; 424 } aq, *aqp; 425 426 if (!ha->tgt.atio_ring) 427 return ptr; 428 429 num_queues = 1; 430 aqp = &aq; 431 aqp->length = ha->tgt.atio_q_length; 432 aqp->ring = ha->tgt.atio_ring; 433 434 for (que = 0; que < num_queues; que++) { 435 /* aqp = ha->atio_q_map[que]; */ 436 q = ptr; 437 *last_chain = &q->type; 438 q->type = __constant_htonl(DUMP_CHAIN_QUEUE); 439 q->chain_size = htonl( 440 sizeof(struct qla2xxx_mqueue_chain) + 441 sizeof(struct qla2xxx_mqueue_header) + 442 (aqp->length * sizeof(request_t))); 443 ptr += sizeof(struct qla2xxx_mqueue_chain); 444 445 /* Add header. */ 446 qh = ptr; 447 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE); 448 qh->number = htonl(que); 449 qh->size = htonl(aqp->length * sizeof(request_t)); 450 ptr += sizeof(struct qla2xxx_mqueue_header); 451 452 /* Add data. */ 453 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t)); 454 455 ptr += aqp->length * sizeof(request_t); 456 } 457 458 return ptr; 459 } 460 461 static inline void * 462 qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 463 { 464 struct qla2xxx_mqueue_chain *q; 465 struct qla2xxx_mqueue_header *qh; 466 struct req_que *req; 467 struct rsp_que *rsp; 468 int que; 469 470 if (!ha->mqenable) 471 return ptr; 472 473 /* Request queues */ 474 for (que = 1; que < ha->max_req_queues; que++) { 475 req = ha->req_q_map[que]; 476 if (!req) 477 break; 478 479 /* Add chain. */ 480 q = ptr; 481 *last_chain = &q->type; 482 q->type = __constant_htonl(DUMP_CHAIN_QUEUE); 483 q->chain_size = htonl( 484 sizeof(struct qla2xxx_mqueue_chain) + 485 sizeof(struct qla2xxx_mqueue_header) + 486 (req->length * sizeof(request_t))); 487 ptr += sizeof(struct qla2xxx_mqueue_chain); 488 489 /* Add header. */ 490 qh = ptr; 491 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE); 492 qh->number = htonl(que); 493 qh->size = htonl(req->length * sizeof(request_t)); 494 ptr += sizeof(struct qla2xxx_mqueue_header); 495 496 /* Add data. */ 497 memcpy(ptr, req->ring, req->length * sizeof(request_t)); 498 ptr += req->length * sizeof(request_t); 499 } 500 501 /* Response queues */ 502 for (que = 1; que < ha->max_rsp_queues; que++) { 503 rsp = ha->rsp_q_map[que]; 504 if (!rsp) 505 break; 506 507 /* Add chain. */ 508 q = ptr; 509 *last_chain = &q->type; 510 q->type = __constant_htonl(DUMP_CHAIN_QUEUE); 511 q->chain_size = htonl( 512 sizeof(struct qla2xxx_mqueue_chain) + 513 sizeof(struct qla2xxx_mqueue_header) + 514 (rsp->length * sizeof(response_t))); 515 ptr += sizeof(struct qla2xxx_mqueue_chain); 516 517 /* Add header. */ 518 qh = ptr; 519 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE); 520 qh->number = htonl(que); 521 qh->size = htonl(rsp->length * sizeof(response_t)); 522 ptr += sizeof(struct qla2xxx_mqueue_header); 523 524 /* Add data. */ 525 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t)); 526 ptr += rsp->length * sizeof(response_t); 527 } 528 529 return ptr; 530 } 531 532 static inline void * 533 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 534 { 535 uint32_t cnt, que_idx; 536 uint8_t que_cnt; 537 struct qla2xxx_mq_chain *mq = ptr; 538 device_reg_t __iomem *reg; 539 540 if (!ha->mqenable || IS_QLA83XX(ha)) 541 return ptr; 542 543 mq = ptr; 544 *last_chain = &mq->type; 545 mq->type = __constant_htonl(DUMP_CHAIN_MQ); 546 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain)); 547 548 que_cnt = ha->max_req_queues > ha->max_rsp_queues ? 549 ha->max_req_queues : ha->max_rsp_queues; 550 mq->count = htonl(que_cnt); 551 for (cnt = 0; cnt < que_cnt; cnt++) { 552 reg = ISP_QUE_REG(ha, cnt); 553 que_idx = cnt * 4; 554 mq->qregs[que_idx] = 555 htonl(RD_REG_DWORD(®->isp25mq.req_q_in)); 556 mq->qregs[que_idx+1] = 557 htonl(RD_REG_DWORD(®->isp25mq.req_q_out)); 558 mq->qregs[que_idx+2] = 559 htonl(RD_REG_DWORD(®->isp25mq.rsp_q_in)); 560 mq->qregs[que_idx+3] = 561 htonl(RD_REG_DWORD(®->isp25mq.rsp_q_out)); 562 } 563 564 return ptr + sizeof(struct qla2xxx_mq_chain); 565 } 566 567 void 568 qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) 569 { 570 struct qla_hw_data *ha = vha->hw; 571 572 if (rval != QLA_SUCCESS) { 573 ql_log(ql_log_warn, vha, 0xd000, 574 "Failed to dump firmware (%x).\n", rval); 575 ha->fw_dumped = 0; 576 } else { 577 ql_log(ql_log_info, vha, 0xd001, 578 "Firmware dump saved to temp buffer (%ld/%p).\n", 579 vha->host_no, ha->fw_dump); 580 ha->fw_dumped = 1; 581 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 582 } 583 } 584 585 /** 586 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 587 * @ha: HA context 588 * @hardware_locked: Called with the hardware_lock 589 */ 590 void 591 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 592 { 593 int rval; 594 uint32_t cnt; 595 struct qla_hw_data *ha = vha->hw; 596 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 597 uint16_t __iomem *dmp_reg; 598 unsigned long flags; 599 struct qla2300_fw_dump *fw; 600 void *nxt; 601 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 602 603 flags = 0; 604 605 if (!hardware_locked) 606 spin_lock_irqsave(&ha->hardware_lock, flags); 607 608 if (!ha->fw_dump) { 609 ql_log(ql_log_warn, vha, 0xd002, 610 "No buffer available for dump.\n"); 611 goto qla2300_fw_dump_failed; 612 } 613 614 if (ha->fw_dumped) { 615 ql_log(ql_log_warn, vha, 0xd003, 616 "Firmware has been previously dumped (%p) " 617 "-- ignoring request.\n", 618 ha->fw_dump); 619 goto qla2300_fw_dump_failed; 620 } 621 fw = &ha->fw_dump->isp.isp23; 622 qla2xxx_prep_dump(ha, ha->fw_dump); 623 624 rval = QLA_SUCCESS; 625 fw->hccr = htons(RD_REG_WORD(®->hccr)); 626 627 /* Pause RISC. */ 628 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 629 if (IS_QLA2300(ha)) { 630 for (cnt = 30000; 631 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 632 rval == QLA_SUCCESS; cnt--) { 633 if (cnt) 634 udelay(100); 635 else 636 rval = QLA_FUNCTION_TIMEOUT; 637 } 638 } else { 639 RD_REG_WORD(®->hccr); /* PCI Posting. */ 640 udelay(10); 641 } 642 643 if (rval == QLA_SUCCESS) { 644 dmp_reg = ®->flash_address; 645 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 646 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 647 648 dmp_reg = ®->u.isp2300.req_q_in; 649 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) 650 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 651 652 dmp_reg = ®->u.isp2300.mailbox0; 653 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 654 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 655 656 WRT_REG_WORD(®->ctrl_status, 0x40); 657 qla2xxx_read_window(reg, 32, fw->resp_dma_reg); 658 659 WRT_REG_WORD(®->ctrl_status, 0x50); 660 qla2xxx_read_window(reg, 48, fw->dma_reg); 661 662 WRT_REG_WORD(®->ctrl_status, 0x00); 663 dmp_reg = ®->risc_hw; 664 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 665 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 666 667 WRT_REG_WORD(®->pcr, 0x2000); 668 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 669 670 WRT_REG_WORD(®->pcr, 0x2200); 671 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 672 673 WRT_REG_WORD(®->pcr, 0x2400); 674 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 675 676 WRT_REG_WORD(®->pcr, 0x2600); 677 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 678 679 WRT_REG_WORD(®->pcr, 0x2800); 680 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 681 682 WRT_REG_WORD(®->pcr, 0x2A00); 683 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 684 685 WRT_REG_WORD(®->pcr, 0x2C00); 686 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 687 688 WRT_REG_WORD(®->pcr, 0x2E00); 689 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 690 691 WRT_REG_WORD(®->ctrl_status, 0x10); 692 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); 693 694 WRT_REG_WORD(®->ctrl_status, 0x20); 695 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 696 697 WRT_REG_WORD(®->ctrl_status, 0x30); 698 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 699 700 /* Reset RISC. */ 701 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 702 for (cnt = 0; cnt < 30000; cnt++) { 703 if ((RD_REG_WORD(®->ctrl_status) & 704 CSR_ISP_SOFT_RESET) == 0) 705 break; 706 707 udelay(10); 708 } 709 } 710 711 if (!IS_QLA2300(ha)) { 712 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 713 rval == QLA_SUCCESS; cnt--) { 714 if (cnt) 715 udelay(100); 716 else 717 rval = QLA_FUNCTION_TIMEOUT; 718 } 719 } 720 721 /* Get RISC SRAM. */ 722 if (rval == QLA_SUCCESS) 723 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, 724 sizeof(fw->risc_ram) / 2, &nxt); 725 726 /* Get stack SRAM. */ 727 if (rval == QLA_SUCCESS) 728 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, 729 sizeof(fw->stack_ram) / 2, &nxt); 730 731 /* Get data SRAM. */ 732 if (rval == QLA_SUCCESS) 733 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, 734 ha->fw_memory_size - 0x11000 + 1, &nxt); 735 736 if (rval == QLA_SUCCESS) 737 qla2xxx_copy_queues(ha, nxt); 738 739 qla2xxx_dump_post_process(base_vha, rval); 740 741 qla2300_fw_dump_failed: 742 if (!hardware_locked) 743 spin_unlock_irqrestore(&ha->hardware_lock, flags); 744 } 745 746 /** 747 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. 748 * @ha: HA context 749 * @hardware_locked: Called with the hardware_lock 750 */ 751 void 752 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 753 { 754 int rval; 755 uint32_t cnt, timer; 756 uint16_t risc_address; 757 uint16_t mb0, mb2; 758 struct qla_hw_data *ha = vha->hw; 759 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 760 uint16_t __iomem *dmp_reg; 761 unsigned long flags; 762 struct qla2100_fw_dump *fw; 763 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 764 765 risc_address = 0; 766 mb0 = mb2 = 0; 767 flags = 0; 768 769 if (!hardware_locked) 770 spin_lock_irqsave(&ha->hardware_lock, flags); 771 772 if (!ha->fw_dump) { 773 ql_log(ql_log_warn, vha, 0xd004, 774 "No buffer available for dump.\n"); 775 goto qla2100_fw_dump_failed; 776 } 777 778 if (ha->fw_dumped) { 779 ql_log(ql_log_warn, vha, 0xd005, 780 "Firmware has been previously dumped (%p) " 781 "-- ignoring request.\n", 782 ha->fw_dump); 783 goto qla2100_fw_dump_failed; 784 } 785 fw = &ha->fw_dump->isp.isp21; 786 qla2xxx_prep_dump(ha, ha->fw_dump); 787 788 rval = QLA_SUCCESS; 789 fw->hccr = htons(RD_REG_WORD(®->hccr)); 790 791 /* Pause RISC. */ 792 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 793 for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 794 rval == QLA_SUCCESS; cnt--) { 795 if (cnt) 796 udelay(100); 797 else 798 rval = QLA_FUNCTION_TIMEOUT; 799 } 800 if (rval == QLA_SUCCESS) { 801 dmp_reg = ®->flash_address; 802 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 803 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 804 805 dmp_reg = ®->u.isp2100.mailbox0; 806 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 807 if (cnt == 8) 808 dmp_reg = ®->u_end.isp2200.mailbox8; 809 810 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 811 } 812 813 dmp_reg = ®->u.isp2100.unused_2[0]; 814 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 815 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 816 817 WRT_REG_WORD(®->ctrl_status, 0x00); 818 dmp_reg = ®->risc_hw; 819 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 820 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 821 822 WRT_REG_WORD(®->pcr, 0x2000); 823 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 824 825 WRT_REG_WORD(®->pcr, 0x2100); 826 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 827 828 WRT_REG_WORD(®->pcr, 0x2200); 829 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 830 831 WRT_REG_WORD(®->pcr, 0x2300); 832 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 833 834 WRT_REG_WORD(®->pcr, 0x2400); 835 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 836 837 WRT_REG_WORD(®->pcr, 0x2500); 838 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 839 840 WRT_REG_WORD(®->pcr, 0x2600); 841 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 842 843 WRT_REG_WORD(®->pcr, 0x2700); 844 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 845 846 WRT_REG_WORD(®->ctrl_status, 0x10); 847 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); 848 849 WRT_REG_WORD(®->ctrl_status, 0x20); 850 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 851 852 WRT_REG_WORD(®->ctrl_status, 0x30); 853 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 854 855 /* Reset the ISP. */ 856 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 857 } 858 859 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 860 rval == QLA_SUCCESS; cnt--) { 861 if (cnt) 862 udelay(100); 863 else 864 rval = QLA_FUNCTION_TIMEOUT; 865 } 866 867 /* Pause RISC. */ 868 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && 869 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { 870 871 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 872 for (cnt = 30000; 873 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 874 rval == QLA_SUCCESS; cnt--) { 875 if (cnt) 876 udelay(100); 877 else 878 rval = QLA_FUNCTION_TIMEOUT; 879 } 880 if (rval == QLA_SUCCESS) { 881 /* Set memory configuration and timing. */ 882 if (IS_QLA2100(ha)) 883 WRT_REG_WORD(®->mctr, 0xf1); 884 else 885 WRT_REG_WORD(®->mctr, 0xf2); 886 RD_REG_WORD(®->mctr); /* PCI Posting. */ 887 888 /* Release RISC. */ 889 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 890 } 891 } 892 893 if (rval == QLA_SUCCESS) { 894 /* Get RISC SRAM. */ 895 risc_address = 0x1000; 896 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); 897 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 898 } 899 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; 900 cnt++, risc_address++) { 901 WRT_MAILBOX_REG(ha, reg, 1, risc_address); 902 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 903 904 for (timer = 6000000; timer != 0; timer--) { 905 /* Check for pending interrupts. */ 906 if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { 907 if (RD_REG_WORD(®->semaphore) & BIT_0) { 908 set_bit(MBX_INTERRUPT, 909 &ha->mbx_cmd_flags); 910 911 mb0 = RD_MAILBOX_REG(ha, reg, 0); 912 mb2 = RD_MAILBOX_REG(ha, reg, 2); 913 914 WRT_REG_WORD(®->semaphore, 0); 915 WRT_REG_WORD(®->hccr, 916 HCCR_CLR_RISC_INT); 917 RD_REG_WORD(®->hccr); 918 break; 919 } 920 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 921 RD_REG_WORD(®->hccr); 922 } 923 udelay(5); 924 } 925 926 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 927 rval = mb0 & MBS_MASK; 928 fw->risc_ram[cnt] = htons(mb2); 929 } else { 930 rval = QLA_FUNCTION_FAILED; 931 } 932 } 933 934 if (rval == QLA_SUCCESS) 935 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); 936 937 qla2xxx_dump_post_process(base_vha, rval); 938 939 qla2100_fw_dump_failed: 940 if (!hardware_locked) 941 spin_unlock_irqrestore(&ha->hardware_lock, flags); 942 } 943 944 void 945 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 946 { 947 int rval; 948 uint32_t cnt; 949 uint32_t risc_address; 950 struct qla_hw_data *ha = vha->hw; 951 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 952 uint32_t __iomem *dmp_reg; 953 uint32_t *iter_reg; 954 uint16_t __iomem *mbx_reg; 955 unsigned long flags; 956 struct qla24xx_fw_dump *fw; 957 uint32_t ext_mem_cnt; 958 void *nxt; 959 void *nxt_chain; 960 uint32_t *last_chain = NULL; 961 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 962 963 if (IS_P3P_TYPE(ha)) 964 return; 965 966 risc_address = ext_mem_cnt = 0; 967 flags = 0; 968 969 if (!hardware_locked) 970 spin_lock_irqsave(&ha->hardware_lock, flags); 971 972 if (!ha->fw_dump) { 973 ql_log(ql_log_warn, vha, 0xd006, 974 "No buffer available for dump.\n"); 975 goto qla24xx_fw_dump_failed; 976 } 977 978 if (ha->fw_dumped) { 979 ql_log(ql_log_warn, vha, 0xd007, 980 "Firmware has been previously dumped (%p) " 981 "-- ignoring request.\n", 982 ha->fw_dump); 983 goto qla24xx_fw_dump_failed; 984 } 985 fw = &ha->fw_dump->isp.isp24; 986 qla2xxx_prep_dump(ha, ha->fw_dump); 987 988 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 989 990 /* Pause RISC. */ 991 rval = qla24xx_pause_risc(reg); 992 if (rval != QLA_SUCCESS) 993 goto qla24xx_fw_dump_failed_0; 994 995 /* Host interface registers. */ 996 dmp_reg = ®->flash_addr; 997 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 998 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 999 1000 /* Disable interrupts. */ 1001 WRT_REG_DWORD(®->ictrl, 0); 1002 RD_REG_DWORD(®->ictrl); 1003 1004 /* Shadow registers. */ 1005 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1006 RD_REG_DWORD(®->iobase_addr); 1007 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1008 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1009 1010 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1011 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1012 1013 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1014 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1015 1016 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1017 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1018 1019 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1020 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1021 1022 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1023 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1024 1025 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1026 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1027 1028 /* Mailbox registers. */ 1029 mbx_reg = ®->mailbox0; 1030 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1031 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1032 1033 /* Transfer sequence registers. */ 1034 iter_reg = fw->xseq_gp_reg; 1035 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1036 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1037 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1038 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1039 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1040 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1041 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1042 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1043 1044 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); 1045 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1046 1047 /* Receive sequence registers. */ 1048 iter_reg = fw->rseq_gp_reg; 1049 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1050 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1051 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1052 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1053 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1054 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1055 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1056 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1057 1058 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); 1059 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1060 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1061 1062 /* Command DMA registers. */ 1063 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1064 1065 /* Queues. */ 1066 iter_reg = fw->req0_dma_reg; 1067 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1068 dmp_reg = ®->iobase_q; 1069 for (cnt = 0; cnt < 7; cnt++) 1070 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1071 1072 iter_reg = fw->resp0_dma_reg; 1073 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1074 dmp_reg = ®->iobase_q; 1075 for (cnt = 0; cnt < 7; cnt++) 1076 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1077 1078 iter_reg = fw->req1_dma_reg; 1079 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1080 dmp_reg = ®->iobase_q; 1081 for (cnt = 0; cnt < 7; cnt++) 1082 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1083 1084 /* Transmit DMA registers. */ 1085 iter_reg = fw->xmt0_dma_reg; 1086 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1087 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1088 1089 iter_reg = fw->xmt1_dma_reg; 1090 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1091 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1092 1093 iter_reg = fw->xmt2_dma_reg; 1094 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1095 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1096 1097 iter_reg = fw->xmt3_dma_reg; 1098 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1099 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1100 1101 iter_reg = fw->xmt4_dma_reg; 1102 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1103 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1104 1105 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1106 1107 /* Receive DMA registers. */ 1108 iter_reg = fw->rcvt0_data_dma_reg; 1109 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1110 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1111 1112 iter_reg = fw->rcvt1_data_dma_reg; 1113 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1114 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1115 1116 /* RISC registers. */ 1117 iter_reg = fw->risc_gp_reg; 1118 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1119 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1120 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1121 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1122 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1123 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1124 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1125 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1126 1127 /* Local memory controller registers. */ 1128 iter_reg = fw->lmc_reg; 1129 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1130 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1131 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1132 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1133 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1134 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1135 qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1136 1137 /* Fibre Protocol Module registers. */ 1138 iter_reg = fw->fpm_hdw_reg; 1139 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1140 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1141 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1142 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1143 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1144 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1145 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1146 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1147 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1148 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1149 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1150 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1151 1152 /* Frame Buffer registers. */ 1153 iter_reg = fw->fb_hdw_reg; 1154 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1155 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1156 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1157 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1158 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1159 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1160 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1161 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1162 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1163 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1164 qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1165 1166 rval = qla24xx_soft_reset(ha); 1167 if (rval != QLA_SUCCESS) 1168 goto qla24xx_fw_dump_failed_0; 1169 1170 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1171 &nxt); 1172 if (rval != QLA_SUCCESS) 1173 goto qla24xx_fw_dump_failed_0; 1174 1175 nxt = qla2xxx_copy_queues(ha, nxt); 1176 1177 qla24xx_copy_eft(ha, nxt); 1178 1179 nxt_chain = (void *)ha->fw_dump + ha->chain_offset; 1180 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1181 if (last_chain) { 1182 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 1183 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 1184 } 1185 1186 /* Adjust valid length. */ 1187 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1188 1189 qla24xx_fw_dump_failed_0: 1190 qla2xxx_dump_post_process(base_vha, rval); 1191 1192 qla24xx_fw_dump_failed: 1193 if (!hardware_locked) 1194 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1195 } 1196 1197 void 1198 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1199 { 1200 int rval; 1201 uint32_t cnt; 1202 uint32_t risc_address; 1203 struct qla_hw_data *ha = vha->hw; 1204 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1205 uint32_t __iomem *dmp_reg; 1206 uint32_t *iter_reg; 1207 uint16_t __iomem *mbx_reg; 1208 unsigned long flags; 1209 struct qla25xx_fw_dump *fw; 1210 uint32_t ext_mem_cnt; 1211 void *nxt, *nxt_chain; 1212 uint32_t *last_chain = NULL; 1213 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1214 1215 risc_address = ext_mem_cnt = 0; 1216 flags = 0; 1217 1218 if (!hardware_locked) 1219 spin_lock_irqsave(&ha->hardware_lock, flags); 1220 1221 if (!ha->fw_dump) { 1222 ql_log(ql_log_warn, vha, 0xd008, 1223 "No buffer available for dump.\n"); 1224 goto qla25xx_fw_dump_failed; 1225 } 1226 1227 if (ha->fw_dumped) { 1228 ql_log(ql_log_warn, vha, 0xd009, 1229 "Firmware has been previously dumped (%p) " 1230 "-- ignoring request.\n", 1231 ha->fw_dump); 1232 goto qla25xx_fw_dump_failed; 1233 } 1234 fw = &ha->fw_dump->isp.isp25; 1235 qla2xxx_prep_dump(ha, ha->fw_dump); 1236 ha->fw_dump->version = __constant_htonl(2); 1237 1238 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1239 1240 /* Pause RISC. */ 1241 rval = qla24xx_pause_risc(reg); 1242 if (rval != QLA_SUCCESS) 1243 goto qla25xx_fw_dump_failed_0; 1244 1245 /* Host/Risc registers. */ 1246 iter_reg = fw->host_risc_reg; 1247 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1248 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1249 1250 /* PCIe registers. */ 1251 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1252 RD_REG_DWORD(®->iobase_addr); 1253 WRT_REG_DWORD(®->iobase_window, 0x01); 1254 dmp_reg = ®->iobase_c4; 1255 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1256 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1257 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1258 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1259 1260 WRT_REG_DWORD(®->iobase_window, 0x00); 1261 RD_REG_DWORD(®->iobase_window); 1262 1263 /* Host interface registers. */ 1264 dmp_reg = ®->flash_addr; 1265 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1266 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1267 1268 /* Disable interrupts. */ 1269 WRT_REG_DWORD(®->ictrl, 0); 1270 RD_REG_DWORD(®->ictrl); 1271 1272 /* Shadow registers. */ 1273 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1274 RD_REG_DWORD(®->iobase_addr); 1275 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1276 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1277 1278 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1279 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1280 1281 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1282 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1283 1284 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1285 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1286 1287 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1288 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1289 1290 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1291 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1292 1293 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1294 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1295 1296 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1297 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1298 1299 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1300 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1301 1302 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1303 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1304 1305 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1306 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1307 1308 /* RISC I/O register. */ 1309 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1310 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1311 1312 /* Mailbox registers. */ 1313 mbx_reg = ®->mailbox0; 1314 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1315 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1316 1317 /* Transfer sequence registers. */ 1318 iter_reg = fw->xseq_gp_reg; 1319 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1320 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1321 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1322 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1323 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1324 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1325 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1326 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1327 1328 iter_reg = fw->xseq_0_reg; 1329 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1330 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1331 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1332 1333 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1334 1335 /* Receive sequence registers. */ 1336 iter_reg = fw->rseq_gp_reg; 1337 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1338 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1339 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1340 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1341 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1342 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1343 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1344 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1345 1346 iter_reg = fw->rseq_0_reg; 1347 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1348 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1349 1350 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1351 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1352 1353 /* Auxiliary sequence registers. */ 1354 iter_reg = fw->aseq_gp_reg; 1355 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1356 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1357 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1358 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1359 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1360 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1361 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1362 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1363 1364 iter_reg = fw->aseq_0_reg; 1365 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1366 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1367 1368 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1369 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1370 1371 /* Command DMA registers. */ 1372 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1373 1374 /* Queues. */ 1375 iter_reg = fw->req0_dma_reg; 1376 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1377 dmp_reg = ®->iobase_q; 1378 for (cnt = 0; cnt < 7; cnt++) 1379 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1380 1381 iter_reg = fw->resp0_dma_reg; 1382 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1383 dmp_reg = ®->iobase_q; 1384 for (cnt = 0; cnt < 7; cnt++) 1385 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1386 1387 iter_reg = fw->req1_dma_reg; 1388 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1389 dmp_reg = ®->iobase_q; 1390 for (cnt = 0; cnt < 7; cnt++) 1391 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1392 1393 /* Transmit DMA registers. */ 1394 iter_reg = fw->xmt0_dma_reg; 1395 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1396 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1397 1398 iter_reg = fw->xmt1_dma_reg; 1399 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1400 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1401 1402 iter_reg = fw->xmt2_dma_reg; 1403 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1404 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1405 1406 iter_reg = fw->xmt3_dma_reg; 1407 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1408 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1409 1410 iter_reg = fw->xmt4_dma_reg; 1411 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1412 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1413 1414 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1415 1416 /* Receive DMA registers. */ 1417 iter_reg = fw->rcvt0_data_dma_reg; 1418 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1419 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1420 1421 iter_reg = fw->rcvt1_data_dma_reg; 1422 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1423 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1424 1425 /* RISC registers. */ 1426 iter_reg = fw->risc_gp_reg; 1427 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1428 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1429 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1430 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1431 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1432 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1433 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1434 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1435 1436 /* Local memory controller registers. */ 1437 iter_reg = fw->lmc_reg; 1438 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1439 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1440 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1441 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1442 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1443 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1444 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1445 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1446 1447 /* Fibre Protocol Module registers. */ 1448 iter_reg = fw->fpm_hdw_reg; 1449 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1450 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1451 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1452 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1453 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1454 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1455 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1456 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1457 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1458 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1459 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1460 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1461 1462 /* Frame Buffer registers. */ 1463 iter_reg = fw->fb_hdw_reg; 1464 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1465 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1466 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1467 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1468 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1469 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1470 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1471 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1472 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1473 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1474 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1475 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1476 1477 /* Multi queue registers */ 1478 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1479 &last_chain); 1480 1481 rval = qla24xx_soft_reset(ha); 1482 if (rval != QLA_SUCCESS) 1483 goto qla25xx_fw_dump_failed_0; 1484 1485 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1486 &nxt); 1487 if (rval != QLA_SUCCESS) 1488 goto qla25xx_fw_dump_failed_0; 1489 1490 nxt = qla2xxx_copy_queues(ha, nxt); 1491 1492 qla24xx_copy_eft(ha, nxt); 1493 1494 /* Chain entries -- started with MQ. */ 1495 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1496 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 1497 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1498 if (last_chain) { 1499 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 1500 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 1501 } 1502 1503 /* Adjust valid length. */ 1504 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1505 1506 qla25xx_fw_dump_failed_0: 1507 qla2xxx_dump_post_process(base_vha, rval); 1508 1509 qla25xx_fw_dump_failed: 1510 if (!hardware_locked) 1511 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1512 } 1513 1514 void 1515 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1516 { 1517 int rval; 1518 uint32_t cnt; 1519 uint32_t risc_address; 1520 struct qla_hw_data *ha = vha->hw; 1521 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1522 uint32_t __iomem *dmp_reg; 1523 uint32_t *iter_reg; 1524 uint16_t __iomem *mbx_reg; 1525 unsigned long flags; 1526 struct qla81xx_fw_dump *fw; 1527 uint32_t ext_mem_cnt; 1528 void *nxt, *nxt_chain; 1529 uint32_t *last_chain = NULL; 1530 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1531 1532 risc_address = ext_mem_cnt = 0; 1533 flags = 0; 1534 1535 if (!hardware_locked) 1536 spin_lock_irqsave(&ha->hardware_lock, flags); 1537 1538 if (!ha->fw_dump) { 1539 ql_log(ql_log_warn, vha, 0xd00a, 1540 "No buffer available for dump.\n"); 1541 goto qla81xx_fw_dump_failed; 1542 } 1543 1544 if (ha->fw_dumped) { 1545 ql_log(ql_log_warn, vha, 0xd00b, 1546 "Firmware has been previously dumped (%p) " 1547 "-- ignoring request.\n", 1548 ha->fw_dump); 1549 goto qla81xx_fw_dump_failed; 1550 } 1551 fw = &ha->fw_dump->isp.isp81; 1552 qla2xxx_prep_dump(ha, ha->fw_dump); 1553 1554 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1555 1556 /* Pause RISC. */ 1557 rval = qla24xx_pause_risc(reg); 1558 if (rval != QLA_SUCCESS) 1559 goto qla81xx_fw_dump_failed_0; 1560 1561 /* Host/Risc registers. */ 1562 iter_reg = fw->host_risc_reg; 1563 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1564 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1565 1566 /* PCIe registers. */ 1567 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1568 RD_REG_DWORD(®->iobase_addr); 1569 WRT_REG_DWORD(®->iobase_window, 0x01); 1570 dmp_reg = ®->iobase_c4; 1571 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1572 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1573 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1574 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1575 1576 WRT_REG_DWORD(®->iobase_window, 0x00); 1577 RD_REG_DWORD(®->iobase_window); 1578 1579 /* Host interface registers. */ 1580 dmp_reg = ®->flash_addr; 1581 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1582 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1583 1584 /* Disable interrupts. */ 1585 WRT_REG_DWORD(®->ictrl, 0); 1586 RD_REG_DWORD(®->ictrl); 1587 1588 /* Shadow registers. */ 1589 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1590 RD_REG_DWORD(®->iobase_addr); 1591 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1592 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1593 1594 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1595 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1596 1597 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1598 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1599 1600 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1601 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1602 1603 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1604 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1605 1606 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1607 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1608 1609 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1610 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1611 1612 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1613 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1614 1615 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1616 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1617 1618 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1619 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1620 1621 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1622 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1623 1624 /* RISC I/O register. */ 1625 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1626 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1627 1628 /* Mailbox registers. */ 1629 mbx_reg = ®->mailbox0; 1630 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1631 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1632 1633 /* Transfer sequence registers. */ 1634 iter_reg = fw->xseq_gp_reg; 1635 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1636 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1637 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1638 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1639 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1640 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1641 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1642 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1643 1644 iter_reg = fw->xseq_0_reg; 1645 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1646 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1647 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1648 1649 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1650 1651 /* Receive sequence registers. */ 1652 iter_reg = fw->rseq_gp_reg; 1653 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1654 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1655 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1656 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1657 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1658 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1659 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1660 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1661 1662 iter_reg = fw->rseq_0_reg; 1663 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1664 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1665 1666 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1667 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1668 1669 /* Auxiliary sequence registers. */ 1670 iter_reg = fw->aseq_gp_reg; 1671 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1672 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1673 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1674 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1675 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1676 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1677 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1678 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1679 1680 iter_reg = fw->aseq_0_reg; 1681 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1682 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1683 1684 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1685 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1686 1687 /* Command DMA registers. */ 1688 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1689 1690 /* Queues. */ 1691 iter_reg = fw->req0_dma_reg; 1692 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1693 dmp_reg = ®->iobase_q; 1694 for (cnt = 0; cnt < 7; cnt++) 1695 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1696 1697 iter_reg = fw->resp0_dma_reg; 1698 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1699 dmp_reg = ®->iobase_q; 1700 for (cnt = 0; cnt < 7; cnt++) 1701 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1702 1703 iter_reg = fw->req1_dma_reg; 1704 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1705 dmp_reg = ®->iobase_q; 1706 for (cnt = 0; cnt < 7; cnt++) 1707 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1708 1709 /* Transmit DMA registers. */ 1710 iter_reg = fw->xmt0_dma_reg; 1711 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1712 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1713 1714 iter_reg = fw->xmt1_dma_reg; 1715 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1716 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1717 1718 iter_reg = fw->xmt2_dma_reg; 1719 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1720 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1721 1722 iter_reg = fw->xmt3_dma_reg; 1723 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1724 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1725 1726 iter_reg = fw->xmt4_dma_reg; 1727 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1728 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1729 1730 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1731 1732 /* Receive DMA registers. */ 1733 iter_reg = fw->rcvt0_data_dma_reg; 1734 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1735 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1736 1737 iter_reg = fw->rcvt1_data_dma_reg; 1738 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1739 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1740 1741 /* RISC registers. */ 1742 iter_reg = fw->risc_gp_reg; 1743 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1744 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1745 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1746 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1747 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1748 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1749 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1750 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1751 1752 /* Local memory controller registers. */ 1753 iter_reg = fw->lmc_reg; 1754 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1755 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1756 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1757 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1758 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1759 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1760 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1761 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1762 1763 /* Fibre Protocol Module registers. */ 1764 iter_reg = fw->fpm_hdw_reg; 1765 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1766 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1767 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1768 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1769 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1770 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1771 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1772 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1773 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1774 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1775 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1776 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1777 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); 1778 qla24xx_read_window(reg, 0x40D0, 16, iter_reg); 1779 1780 /* Frame Buffer registers. */ 1781 iter_reg = fw->fb_hdw_reg; 1782 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1783 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1784 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1785 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1786 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1787 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1788 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1789 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1790 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1791 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1792 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1793 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); 1794 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1795 1796 /* Multi queue registers */ 1797 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1798 &last_chain); 1799 1800 rval = qla24xx_soft_reset(ha); 1801 if (rval != QLA_SUCCESS) 1802 goto qla81xx_fw_dump_failed_0; 1803 1804 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1805 &nxt); 1806 if (rval != QLA_SUCCESS) 1807 goto qla81xx_fw_dump_failed_0; 1808 1809 nxt = qla2xxx_copy_queues(ha, nxt); 1810 1811 qla24xx_copy_eft(ha, nxt); 1812 1813 /* Chain entries -- started with MQ. */ 1814 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1815 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 1816 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1817 if (last_chain) { 1818 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 1819 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 1820 } 1821 1822 /* Adjust valid length. */ 1823 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1824 1825 qla81xx_fw_dump_failed_0: 1826 qla2xxx_dump_post_process(base_vha, rval); 1827 1828 qla81xx_fw_dump_failed: 1829 if (!hardware_locked) 1830 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1831 } 1832 1833 void 1834 qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1835 { 1836 int rval; 1837 uint32_t cnt, reg_data; 1838 uint32_t risc_address; 1839 struct qla_hw_data *ha = vha->hw; 1840 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1841 uint32_t __iomem *dmp_reg; 1842 uint32_t *iter_reg; 1843 uint16_t __iomem *mbx_reg; 1844 unsigned long flags; 1845 struct qla83xx_fw_dump *fw; 1846 uint32_t ext_mem_cnt; 1847 void *nxt, *nxt_chain; 1848 uint32_t *last_chain = NULL; 1849 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1850 1851 risc_address = ext_mem_cnt = 0; 1852 flags = 0; 1853 1854 if (!hardware_locked) 1855 spin_lock_irqsave(&ha->hardware_lock, flags); 1856 1857 if (!ha->fw_dump) { 1858 ql_log(ql_log_warn, vha, 0xd00c, 1859 "No buffer available for dump!!!\n"); 1860 goto qla83xx_fw_dump_failed; 1861 } 1862 1863 if (ha->fw_dumped) { 1864 ql_log(ql_log_warn, vha, 0xd00d, 1865 "Firmware has been previously dumped (%p) -- ignoring " 1866 "request...\n", ha->fw_dump); 1867 goto qla83xx_fw_dump_failed; 1868 } 1869 fw = &ha->fw_dump->isp.isp83; 1870 qla2xxx_prep_dump(ha, ha->fw_dump); 1871 1872 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1873 1874 /* Pause RISC. */ 1875 rval = qla24xx_pause_risc(reg); 1876 if (rval != QLA_SUCCESS) 1877 goto qla83xx_fw_dump_failed_0; 1878 1879 WRT_REG_DWORD(®->iobase_addr, 0x6000); 1880 dmp_reg = ®->iobase_window; 1881 reg_data = RD_REG_DWORD(dmp_reg); 1882 WRT_REG_DWORD(dmp_reg, 0); 1883 1884 dmp_reg = ®->unused_4_1[0]; 1885 reg_data = RD_REG_DWORD(dmp_reg); 1886 WRT_REG_DWORD(dmp_reg, 0); 1887 1888 WRT_REG_DWORD(®->iobase_addr, 0x6010); 1889 dmp_reg = ®->unused_4_1[2]; 1890 reg_data = RD_REG_DWORD(dmp_reg); 1891 WRT_REG_DWORD(dmp_reg, 0); 1892 1893 /* select PCR and disable ecc checking and correction */ 1894 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1895 RD_REG_DWORD(®->iobase_addr); 1896 WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */ 1897 1898 /* Host/Risc registers. */ 1899 iter_reg = fw->host_risc_reg; 1900 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1901 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1902 qla24xx_read_window(reg, 0x7040, 16, iter_reg); 1903 1904 /* PCIe registers. */ 1905 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1906 RD_REG_DWORD(®->iobase_addr); 1907 WRT_REG_DWORD(®->iobase_window, 0x01); 1908 dmp_reg = ®->iobase_c4; 1909 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1910 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1911 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1912 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1913 1914 WRT_REG_DWORD(®->iobase_window, 0x00); 1915 RD_REG_DWORD(®->iobase_window); 1916 1917 /* Host interface registers. */ 1918 dmp_reg = ®->flash_addr; 1919 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1920 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1921 1922 /* Disable interrupts. */ 1923 WRT_REG_DWORD(®->ictrl, 0); 1924 RD_REG_DWORD(®->ictrl); 1925 1926 /* Shadow registers. */ 1927 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1928 RD_REG_DWORD(®->iobase_addr); 1929 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1930 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1931 1932 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1933 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1934 1935 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1936 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1937 1938 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1939 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1940 1941 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1942 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1943 1944 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1945 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1946 1947 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1948 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1949 1950 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1951 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1952 1953 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1954 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1955 1956 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1957 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1958 1959 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1960 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1961 1962 /* RISC I/O register. */ 1963 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1964 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1965 1966 /* Mailbox registers. */ 1967 mbx_reg = ®->mailbox0; 1968 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1969 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1970 1971 /* Transfer sequence registers. */ 1972 iter_reg = fw->xseq_gp_reg; 1973 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); 1974 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); 1975 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); 1976 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); 1977 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); 1978 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); 1979 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); 1980 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); 1981 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1982 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1983 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1984 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1985 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1986 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1987 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1988 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1989 1990 iter_reg = fw->xseq_0_reg; 1991 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1992 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1993 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1994 1995 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1996 1997 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); 1998 1999 /* Receive sequence registers. */ 2000 iter_reg = fw->rseq_gp_reg; 2001 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); 2002 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); 2003 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); 2004 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); 2005 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); 2006 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); 2007 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); 2008 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); 2009 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 2010 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 2011 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 2012 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 2013 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 2014 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 2015 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 2016 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 2017 2018 iter_reg = fw->rseq_0_reg; 2019 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 2020 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 2021 2022 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 2023 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 2024 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); 2025 2026 /* Auxiliary sequence registers. */ 2027 iter_reg = fw->aseq_gp_reg; 2028 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 2029 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 2030 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 2031 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 2032 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 2033 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 2034 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 2035 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); 2036 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); 2037 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); 2038 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); 2039 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); 2040 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); 2041 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); 2042 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); 2043 qla24xx_read_window(reg, 0xB170, 16, iter_reg); 2044 2045 iter_reg = fw->aseq_0_reg; 2046 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 2047 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 2048 2049 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 2050 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 2051 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); 2052 2053 /* Command DMA registers. */ 2054 iter_reg = fw->cmd_dma_reg; 2055 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); 2056 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); 2057 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); 2058 qla24xx_read_window(reg, 0x71F0, 16, iter_reg); 2059 2060 /* Queues. */ 2061 iter_reg = fw->req0_dma_reg; 2062 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 2063 dmp_reg = ®->iobase_q; 2064 for (cnt = 0; cnt < 7; cnt++) 2065 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2066 2067 iter_reg = fw->resp0_dma_reg; 2068 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 2069 dmp_reg = ®->iobase_q; 2070 for (cnt = 0; cnt < 7; cnt++) 2071 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2072 2073 iter_reg = fw->req1_dma_reg; 2074 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 2075 dmp_reg = ®->iobase_q; 2076 for (cnt = 0; cnt < 7; cnt++) 2077 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2078 2079 /* Transmit DMA registers. */ 2080 iter_reg = fw->xmt0_dma_reg; 2081 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 2082 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 2083 2084 iter_reg = fw->xmt1_dma_reg; 2085 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 2086 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 2087 2088 iter_reg = fw->xmt2_dma_reg; 2089 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 2090 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 2091 2092 iter_reg = fw->xmt3_dma_reg; 2093 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 2094 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 2095 2096 iter_reg = fw->xmt4_dma_reg; 2097 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 2098 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 2099 2100 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 2101 2102 /* Receive DMA registers. */ 2103 iter_reg = fw->rcvt0_data_dma_reg; 2104 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 2105 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 2106 2107 iter_reg = fw->rcvt1_data_dma_reg; 2108 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 2109 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 2110 2111 /* RISC registers. */ 2112 iter_reg = fw->risc_gp_reg; 2113 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 2114 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 2115 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 2116 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 2117 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 2118 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 2119 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 2120 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 2121 2122 /* Local memory controller registers. */ 2123 iter_reg = fw->lmc_reg; 2124 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 2125 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 2126 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 2127 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 2128 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 2129 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 2130 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 2131 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 2132 2133 /* Fibre Protocol Module registers. */ 2134 iter_reg = fw->fpm_hdw_reg; 2135 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 2136 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 2137 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 2138 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 2139 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 2140 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 2141 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 2142 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 2143 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 2144 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 2145 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 2146 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 2147 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); 2148 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); 2149 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); 2150 qla24xx_read_window(reg, 0x40F0, 16, iter_reg); 2151 2152 /* RQ0 Array registers. */ 2153 iter_reg = fw->rq0_array_reg; 2154 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); 2155 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); 2156 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); 2157 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); 2158 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); 2159 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); 2160 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); 2161 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); 2162 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); 2163 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); 2164 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); 2165 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); 2166 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); 2167 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); 2168 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); 2169 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); 2170 2171 /* RQ1 Array registers. */ 2172 iter_reg = fw->rq1_array_reg; 2173 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); 2174 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); 2175 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); 2176 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); 2177 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); 2178 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); 2179 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); 2180 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); 2181 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); 2182 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); 2183 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); 2184 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); 2185 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); 2186 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); 2187 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); 2188 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); 2189 2190 /* RP0 Array registers. */ 2191 iter_reg = fw->rp0_array_reg; 2192 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); 2193 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); 2194 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); 2195 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); 2196 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); 2197 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); 2198 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); 2199 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); 2200 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); 2201 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); 2202 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); 2203 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); 2204 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); 2205 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); 2206 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); 2207 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); 2208 2209 /* RP1 Array registers. */ 2210 iter_reg = fw->rp1_array_reg; 2211 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); 2212 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); 2213 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); 2214 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); 2215 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); 2216 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); 2217 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); 2218 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); 2219 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); 2220 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); 2221 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); 2222 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); 2223 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); 2224 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); 2225 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); 2226 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); 2227 2228 iter_reg = fw->at0_array_reg; 2229 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); 2230 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); 2231 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); 2232 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); 2233 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); 2234 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); 2235 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); 2236 qla24xx_read_window(reg, 0x70F0, 16, iter_reg); 2237 2238 /* I/O Queue Control registers. */ 2239 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); 2240 2241 /* Frame Buffer registers. */ 2242 iter_reg = fw->fb_hdw_reg; 2243 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 2244 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 2245 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 2246 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 2247 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 2248 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); 2249 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); 2250 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 2251 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 2252 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 2253 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 2254 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 2255 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 2256 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); 2257 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); 2258 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); 2259 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); 2260 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); 2261 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); 2262 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); 2263 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); 2264 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); 2265 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); 2266 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); 2267 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); 2268 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); 2269 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 2270 2271 /* Multi queue registers */ 2272 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 2273 &last_chain); 2274 2275 rval = qla24xx_soft_reset(ha); 2276 if (rval != QLA_SUCCESS) { 2277 ql_log(ql_log_warn, vha, 0xd00e, 2278 "SOFT RESET FAILED, forcing continuation of dump!!!\n"); 2279 rval = QLA_SUCCESS; 2280 2281 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n"); 2282 2283 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); 2284 RD_REG_DWORD(®->hccr); 2285 2286 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); 2287 RD_REG_DWORD(®->hccr); 2288 2289 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 2290 RD_REG_DWORD(®->hccr); 2291 2292 for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--) 2293 udelay(5); 2294 2295 if (!cnt) { 2296 nxt = fw->code_ram; 2297 nxt += sizeof(fw->code_ram); 2298 nxt += (ha->fw_memory_size - 0x100000 + 1); 2299 goto copy_queue; 2300 } else 2301 ql_log(ql_log_warn, vha, 0xd010, 2302 "bigger hammer success?\n"); 2303 } 2304 2305 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 2306 &nxt); 2307 if (rval != QLA_SUCCESS) 2308 goto qla83xx_fw_dump_failed_0; 2309 2310 copy_queue: 2311 nxt = qla2xxx_copy_queues(ha, nxt); 2312 2313 qla24xx_copy_eft(ha, nxt); 2314 2315 /* Chain entries -- started with MQ. */ 2316 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 2317 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 2318 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 2319 if (last_chain) { 2320 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 2321 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 2322 } 2323 2324 /* Adjust valid length. */ 2325 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 2326 2327 qla83xx_fw_dump_failed_0: 2328 qla2xxx_dump_post_process(base_vha, rval); 2329 2330 qla83xx_fw_dump_failed: 2331 if (!hardware_locked) 2332 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2333 } 2334 2335 /****************************************************************************/ 2336 /* Driver Debug Functions. */ 2337 /****************************************************************************/ 2338 2339 static inline int 2340 ql_mask_match(uint32_t level) 2341 { 2342 if (ql2xextended_error_logging == 1) 2343 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 2344 return (level & ql2xextended_error_logging) == level; 2345 } 2346 2347 /* 2348 * This function is for formatting and logging debug information. 2349 * It is to be used when vha is available. It formats the message 2350 * and logs it to the messages file. 2351 * parameters: 2352 * level: The level of the debug messages to be printed. 2353 * If ql2xextended_error_logging value is correctly set, 2354 * this message will appear in the messages file. 2355 * vha: Pointer to the scsi_qla_host_t. 2356 * id: This is a unique identifier for the level. It identifies the 2357 * part of the code from where the message originated. 2358 * msg: The message to be displayed. 2359 */ 2360 void 2361 ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) 2362 { 2363 va_list va; 2364 struct va_format vaf; 2365 2366 if (!ql_mask_match(level)) 2367 return; 2368 2369 va_start(va, fmt); 2370 2371 vaf.fmt = fmt; 2372 vaf.va = &va; 2373 2374 if (vha != NULL) { 2375 const struct pci_dev *pdev = vha->hw->pdev; 2376 /* <module-name> <pci-name> <msg-id>:<host> Message */ 2377 pr_warn("%s [%s]-%04x:%ld: %pV", 2378 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, 2379 vha->host_no, &vaf); 2380 } else { 2381 pr_warn("%s [%s]-%04x: : %pV", 2382 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); 2383 } 2384 2385 va_end(va); 2386 2387 } 2388 2389 /* 2390 * This function is for formatting and logging debug information. 2391 * It is to be used when vha is not available and pci is available, 2392 * i.e., before host allocation. It formats the message and logs it 2393 * to the messages file. 2394 * parameters: 2395 * level: The level of the debug messages to be printed. 2396 * If ql2xextended_error_logging value is correctly set, 2397 * this message will appear in the messages file. 2398 * pdev: Pointer to the struct pci_dev. 2399 * id: This is a unique id for the level. It identifies the part 2400 * of the code from where the message originated. 2401 * msg: The message to be displayed. 2402 */ 2403 void 2404 ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, 2405 const char *fmt, ...) 2406 { 2407 va_list va; 2408 struct va_format vaf; 2409 2410 if (pdev == NULL) 2411 return; 2412 if (!ql_mask_match(level)) 2413 return; 2414 2415 va_start(va, fmt); 2416 2417 vaf.fmt = fmt; 2418 vaf.va = &va; 2419 2420 /* <module-name> <dev-name>:<msg-id> Message */ 2421 pr_warn("%s [%s]-%04x: : %pV", 2422 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf); 2423 2424 va_end(va); 2425 } 2426 2427 /* 2428 * This function is for formatting and logging log messages. 2429 * It is to be used when vha is available. It formats the message 2430 * and logs it to the messages file. All the messages will be logged 2431 * irrespective of value of ql2xextended_error_logging. 2432 * parameters: 2433 * level: The level of the log messages to be printed in the 2434 * messages file. 2435 * vha: Pointer to the scsi_qla_host_t 2436 * id: This is a unique id for the level. It identifies the 2437 * part of the code from where the message originated. 2438 * msg: The message to be displayed. 2439 */ 2440 void 2441 ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) 2442 { 2443 va_list va; 2444 struct va_format vaf; 2445 char pbuf[128]; 2446 2447 if (level > ql_errlev) 2448 return; 2449 2450 if (vha != NULL) { 2451 const struct pci_dev *pdev = vha->hw->pdev; 2452 /* <module-name> <msg-id>:<host> Message */ 2453 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", 2454 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no); 2455 } else { 2456 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2457 QL_MSGHDR, "0000:00:00.0", id); 2458 } 2459 pbuf[sizeof(pbuf) - 1] = 0; 2460 2461 va_start(va, fmt); 2462 2463 vaf.fmt = fmt; 2464 vaf.va = &va; 2465 2466 switch (level) { 2467 case ql_log_fatal: /* FATAL LOG */ 2468 pr_crit("%s%pV", pbuf, &vaf); 2469 break; 2470 case ql_log_warn: 2471 pr_err("%s%pV", pbuf, &vaf); 2472 break; 2473 case ql_log_info: 2474 pr_warn("%s%pV", pbuf, &vaf); 2475 break; 2476 default: 2477 pr_info("%s%pV", pbuf, &vaf); 2478 break; 2479 } 2480 2481 va_end(va); 2482 } 2483 2484 /* 2485 * This function is for formatting and logging log messages. 2486 * It is to be used when vha is not available and pci is available, 2487 * i.e., before host allocation. It formats the message and logs 2488 * it to the messages file. All the messages are logged irrespective 2489 * of the value of ql2xextended_error_logging. 2490 * parameters: 2491 * level: The level of the log messages to be printed in the 2492 * messages file. 2493 * pdev: Pointer to the struct pci_dev. 2494 * id: This is a unique id for the level. It identifies the 2495 * part of the code from where the message originated. 2496 * msg: The message to be displayed. 2497 */ 2498 void 2499 ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, 2500 const char *fmt, ...) 2501 { 2502 va_list va; 2503 struct va_format vaf; 2504 char pbuf[128]; 2505 2506 if (pdev == NULL) 2507 return; 2508 if (level > ql_errlev) 2509 return; 2510 2511 /* <module-name> <dev-name>:<msg-id> Message */ 2512 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2513 QL_MSGHDR, dev_name(&(pdev->dev)), id); 2514 pbuf[sizeof(pbuf) - 1] = 0; 2515 2516 va_start(va, fmt); 2517 2518 vaf.fmt = fmt; 2519 vaf.va = &va; 2520 2521 switch (level) { 2522 case ql_log_fatal: /* FATAL LOG */ 2523 pr_crit("%s%pV", pbuf, &vaf); 2524 break; 2525 case ql_log_warn: 2526 pr_err("%s%pV", pbuf, &vaf); 2527 break; 2528 case ql_log_info: 2529 pr_warn("%s%pV", pbuf, &vaf); 2530 break; 2531 default: 2532 pr_info("%s%pV", pbuf, &vaf); 2533 break; 2534 } 2535 2536 va_end(va); 2537 } 2538 2539 void 2540 ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id) 2541 { 2542 int i; 2543 struct qla_hw_data *ha = vha->hw; 2544 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2545 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 2546 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 2547 uint16_t __iomem *mbx_reg; 2548 2549 if (!ql_mask_match(level)) 2550 return; 2551 2552 if (IS_P3P_TYPE(ha)) 2553 mbx_reg = ®82->mailbox_in[0]; 2554 else if (IS_FWI2_CAPABLE(ha)) 2555 mbx_reg = ®24->mailbox0; 2556 else 2557 mbx_reg = MAILBOX_REG(ha, reg, 0); 2558 2559 ql_dbg(level, vha, id, "Mailbox registers:\n"); 2560 for (i = 0; i < 6; i++) 2561 ql_dbg(level, vha, id, 2562 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); 2563 } 2564 2565 2566 void 2567 ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id, 2568 uint8_t *b, uint32_t size) 2569 { 2570 uint32_t cnt; 2571 uint8_t c; 2572 2573 if (!ql_mask_match(level)) 2574 return; 2575 2576 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 " 2577 "9 Ah Bh Ch Dh Eh Fh\n"); 2578 ql_dbg(level, vha, id, "----------------------------------" 2579 "----------------------------\n"); 2580 2581 ql_dbg(level, vha, id, " "); 2582 for (cnt = 0; cnt < size;) { 2583 c = *b++; 2584 printk("%02x", (uint32_t) c); 2585 cnt++; 2586 if (!(cnt % 16)) 2587 printk("\n"); 2588 else 2589 printk(" "); 2590 } 2591 if (cnt % 16) 2592 ql_dbg(level, vha, id, "\n"); 2593 } 2594