1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_BSG_H 8 #define __QLA_BSG_H 9 10 /* BSG Vendor specific commands */ 11 #define QL_VND_LOOPBACK 0x01 12 #define QL_VND_A84_RESET 0x02 13 #define QL_VND_A84_UPDATE_FW 0x03 14 #define QL_VND_A84_MGMT_CMD 0x04 15 #define QL_VND_IIDMA 0x05 16 #define QL_VND_FCP_PRIO_CFG_CMD 0x06 17 #define QL_VND_READ_FLASH 0x07 18 #define QL_VND_UPDATE_FLASH 0x08 19 #define QL_VND_SET_FRU_VERSION 0x0B 20 #define QL_VND_READ_FRU_STATUS 0x0C 21 #define QL_VND_WRITE_FRU_STATUS 0x0D 22 #define QL_VND_DIAG_IO_CMD 0x0A 23 #define QL_VND_WRITE_I2C 0x10 24 #define QL_VND_READ_I2C 0x11 25 #define QL_VND_FX00_MGMT_CMD 0x12 26 #define QL_VND_SERDES_OP 0x13 27 28 /* BSG Vendor specific subcode returns */ 29 #define EXT_STATUS_OK 0 30 #define EXT_STATUS_ERR 1 31 #define EXT_STATUS_BUSY 2 32 #define EXT_STATUS_INVALID_PARAM 6 33 #define EXT_STATUS_DATA_OVERRUN 7 34 #define EXT_STATUS_DATA_UNDERRUN 8 35 #define EXT_STATUS_MAILBOX 11 36 #define EXT_STATUS_NO_MEMORY 17 37 #define EXT_STATUS_DEVICE_OFFLINE 22 38 39 /* 40 * To support bidirectional iocb 41 * BSG Vendor specific returns 42 */ 43 #define EXT_STATUS_NOT_SUPPORTED 27 44 #define EXT_STATUS_INVALID_CFG 28 45 #define EXT_STATUS_DMA_ERR 29 46 #define EXT_STATUS_TIMEOUT 30 47 #define EXT_STATUS_THREAD_FAILED 31 48 #define EXT_STATUS_DATA_CMP_FAILED 32 49 50 /* BSG definations for interpreting CommandSent field */ 51 #define INT_DEF_LB_LOOPBACK_CMD 0 52 #define INT_DEF_LB_ECHO_CMD 1 53 54 /* Loopback related definations */ 55 #define INTERNAL_LOOPBACK 0xF1 56 #define EXTERNAL_LOOPBACK 0xF2 57 #define ENABLE_INTERNAL_LOOPBACK 0x02 58 #define ENABLE_EXTERNAL_LOOPBACK 0x04 59 #define INTERNAL_LOOPBACK_MASK 0x000E 60 #define MAX_ELS_FRAME_PAYLOAD 252 61 #define ELS_OPCODE_BYTE 0x10 62 63 /* BSG Vendor specific definations */ 64 #define A84_ISSUE_WRITE_TYPE_CMD 0 65 #define A84_ISSUE_READ_TYPE_CMD 1 66 #define A84_CLEANUP_CMD 2 67 #define A84_ISSUE_RESET_OP_FW 3 68 #define A84_ISSUE_RESET_DIAG_FW 4 69 #define A84_ISSUE_UPDATE_OPFW_CMD 5 70 #define A84_ISSUE_UPDATE_DIAGFW_CMD 6 71 72 struct qla84_mgmt_param { 73 union { 74 struct { 75 uint32_t start_addr; 76 } mem; /* for QLA84_MGMT_READ/WRITE_MEM */ 77 struct { 78 uint32_t id; 79 #define QLA84_MGMT_CONFIG_ID_UIF 1 80 #define QLA84_MGMT_CONFIG_ID_FCOE_COS 2 81 #define QLA84_MGMT_CONFIG_ID_PAUSE 3 82 #define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4 83 84 uint32_t param0; 85 uint32_t param1; 86 } config; /* for QLA84_MGMT_CHNG_CONFIG */ 87 88 struct { 89 uint32_t type; 90 #define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */ 91 #define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */ 92 #define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */ 93 #define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */ 94 #define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */ 95 #define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */ 96 #define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */ 97 98 uint32_t context; 99 /* 100 * context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA 101 */ 102 #define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0 103 #define IC_LOG_DATA_LOG_ID_LEARN_LOG 1 104 #define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2 105 #define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3 106 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4 107 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5 108 #define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6 109 #define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7 110 #define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8 111 #define IC_LOG_DATA_LOG_ID_DCX_LOG 9 112 113 /* 114 * context definitions for QLA84_MGMT_INFO_PORT_STAT 115 */ 116 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0 117 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1 118 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2 119 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3 120 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4 121 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5 122 123 124 /* 125 * context definitions for QLA84_MGMT_INFO_LIF_STAT 126 */ 127 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0 128 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1 129 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2 130 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3 131 #define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6 132 133 } info; /* for QLA84_MGMT_GET_INFO */ 134 } u; 135 }; 136 137 struct qla84_msg_mgmt { 138 uint16_t cmd; 139 #define QLA84_MGMT_READ_MEM 0x00 140 #define QLA84_MGMT_WRITE_MEM 0x01 141 #define QLA84_MGMT_CHNG_CONFIG 0x02 142 #define QLA84_MGMT_GET_INFO 0x03 143 uint16_t rsrvd; 144 struct qla84_mgmt_param mgmtp;/* parameters for cmd */ 145 uint32_t len; /* bytes in payload following this struct */ 146 uint8_t payload[0]; /* payload for cmd */ 147 }; 148 149 struct qla_bsg_a84_mgmt { 150 struct qla84_msg_mgmt mgmt; 151 } __attribute__ ((packed)); 152 153 struct qla_scsi_addr { 154 uint16_t bus; 155 uint16_t target; 156 } __attribute__ ((packed)); 157 158 struct qla_ext_dest_addr { 159 union { 160 uint8_t wwnn[8]; 161 uint8_t wwpn[8]; 162 uint8_t id[4]; 163 struct qla_scsi_addr scsi_addr; 164 } dest_addr; 165 uint16_t dest_type; 166 #define EXT_DEF_TYPE_WWPN 2 167 uint16_t lun; 168 uint16_t padding[2]; 169 } __attribute__ ((packed)); 170 171 struct qla_port_param { 172 struct qla_ext_dest_addr fc_scsi_addr; 173 uint16_t mode; 174 uint16_t speed; 175 } __attribute__ ((packed)); 176 177 178 /* FRU VPD */ 179 180 #define MAX_FRU_SIZE 36 181 182 struct qla_field_address { 183 uint16_t offset; 184 uint16_t device; 185 uint16_t option; 186 } __packed; 187 188 struct qla_field_info { 189 uint8_t version[MAX_FRU_SIZE]; 190 } __packed; 191 192 struct qla_image_version { 193 struct qla_field_address field_address; 194 struct qla_field_info field_info; 195 } __packed; 196 197 struct qla_image_version_list { 198 uint32_t count; 199 struct qla_image_version version[0]; 200 } __packed; 201 202 struct qla_status_reg { 203 struct qla_field_address field_address; 204 uint8_t status_reg; 205 uint8_t reserved[7]; 206 } __packed; 207 208 struct qla_i2c_access { 209 uint16_t device; 210 uint16_t offset; 211 uint16_t option; 212 uint16_t length; 213 uint8_t buffer[0x40]; 214 } __packed; 215 216 /* 26xx serdes register interface */ 217 218 /* serdes reg commands */ 219 #define INT_SC_SERDES_READ_REG 1 220 #define INT_SC_SERDES_WRITE_REG 2 221 222 struct qla_serdes_reg { 223 uint16_t cmd; 224 uint16_t addr; 225 uint16_t val; 226 } __packed; 227 228 #endif 229