1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_BSG_H 8 #define __QLA_BSG_H 9 10 /* BSG Vendor specific commands */ 11 #define QL_VND_LOOPBACK 0x01 12 #define QL_VND_A84_RESET 0x02 13 #define QL_VND_A84_UPDATE_FW 0x03 14 #define QL_VND_A84_MGMT_CMD 0x04 15 #define QL_VND_IIDMA 0x05 16 #define QL_VND_FCP_PRIO_CFG_CMD 0x06 17 #define QL_VND_READ_FLASH 0x07 18 #define QL_VND_UPDATE_FLASH 0x08 19 #define QL_VND_SET_FRU_VERSION 0x0B 20 #define QL_VND_READ_FRU_STATUS 0x0C 21 #define QL_VND_WRITE_FRU_STATUS 0x0D 22 #define QL_VND_DIAG_IO_CMD 0x0A 23 #define QL_VND_WRITE_I2C 0x10 24 #define QL_VND_READ_I2C 0x11 25 #define QL_VND_FX00_MGMT_CMD 0x12 26 #define QL_VND_SERDES_OP 0x13 27 #define QL_VND_SERDES_OP_EX 0x14 28 29 /* BSG Vendor specific subcode returns */ 30 #define EXT_STATUS_OK 0 31 #define EXT_STATUS_ERR 1 32 #define EXT_STATUS_BUSY 2 33 #define EXT_STATUS_INVALID_PARAM 6 34 #define EXT_STATUS_DATA_OVERRUN 7 35 #define EXT_STATUS_DATA_UNDERRUN 8 36 #define EXT_STATUS_MAILBOX 11 37 #define EXT_STATUS_NO_MEMORY 17 38 #define EXT_STATUS_DEVICE_OFFLINE 22 39 40 /* 41 * To support bidirectional iocb 42 * BSG Vendor specific returns 43 */ 44 #define EXT_STATUS_NOT_SUPPORTED 27 45 #define EXT_STATUS_INVALID_CFG 28 46 #define EXT_STATUS_DMA_ERR 29 47 #define EXT_STATUS_TIMEOUT 30 48 #define EXT_STATUS_THREAD_FAILED 31 49 #define EXT_STATUS_DATA_CMP_FAILED 32 50 51 /* BSG definations for interpreting CommandSent field */ 52 #define INT_DEF_LB_LOOPBACK_CMD 0 53 #define INT_DEF_LB_ECHO_CMD 1 54 55 /* Loopback related definations */ 56 #define INTERNAL_LOOPBACK 0xF1 57 #define EXTERNAL_LOOPBACK 0xF2 58 #define ENABLE_INTERNAL_LOOPBACK 0x02 59 #define ENABLE_EXTERNAL_LOOPBACK 0x04 60 #define INTERNAL_LOOPBACK_MASK 0x000E 61 #define MAX_ELS_FRAME_PAYLOAD 252 62 #define ELS_OPCODE_BYTE 0x10 63 64 /* BSG Vendor specific definations */ 65 #define A84_ISSUE_WRITE_TYPE_CMD 0 66 #define A84_ISSUE_READ_TYPE_CMD 1 67 #define A84_CLEANUP_CMD 2 68 #define A84_ISSUE_RESET_OP_FW 3 69 #define A84_ISSUE_RESET_DIAG_FW 4 70 #define A84_ISSUE_UPDATE_OPFW_CMD 5 71 #define A84_ISSUE_UPDATE_DIAGFW_CMD 6 72 73 struct qla84_mgmt_param { 74 union { 75 struct { 76 uint32_t start_addr; 77 } mem; /* for QLA84_MGMT_READ/WRITE_MEM */ 78 struct { 79 uint32_t id; 80 #define QLA84_MGMT_CONFIG_ID_UIF 1 81 #define QLA84_MGMT_CONFIG_ID_FCOE_COS 2 82 #define QLA84_MGMT_CONFIG_ID_PAUSE 3 83 #define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4 84 85 uint32_t param0; 86 uint32_t param1; 87 } config; /* for QLA84_MGMT_CHNG_CONFIG */ 88 89 struct { 90 uint32_t type; 91 #define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */ 92 #define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */ 93 #define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */ 94 #define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */ 95 #define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */ 96 #define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */ 97 #define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */ 98 99 uint32_t context; 100 /* 101 * context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA 102 */ 103 #define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0 104 #define IC_LOG_DATA_LOG_ID_LEARN_LOG 1 105 #define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2 106 #define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3 107 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4 108 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5 109 #define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6 110 #define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7 111 #define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8 112 #define IC_LOG_DATA_LOG_ID_DCX_LOG 9 113 114 /* 115 * context definitions for QLA84_MGMT_INFO_PORT_STAT 116 */ 117 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0 118 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1 119 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2 120 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3 121 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4 122 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5 123 124 125 /* 126 * context definitions for QLA84_MGMT_INFO_LIF_STAT 127 */ 128 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0 129 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1 130 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2 131 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3 132 #define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6 133 134 } info; /* for QLA84_MGMT_GET_INFO */ 135 } u; 136 }; 137 138 struct qla84_msg_mgmt { 139 uint16_t cmd; 140 #define QLA84_MGMT_READ_MEM 0x00 141 #define QLA84_MGMT_WRITE_MEM 0x01 142 #define QLA84_MGMT_CHNG_CONFIG 0x02 143 #define QLA84_MGMT_GET_INFO 0x03 144 uint16_t rsrvd; 145 struct qla84_mgmt_param mgmtp;/* parameters for cmd */ 146 uint32_t len; /* bytes in payload following this struct */ 147 uint8_t payload[0]; /* payload for cmd */ 148 }; 149 150 struct qla_bsg_a84_mgmt { 151 struct qla84_msg_mgmt mgmt; 152 } __attribute__ ((packed)); 153 154 struct qla_scsi_addr { 155 uint16_t bus; 156 uint16_t target; 157 } __attribute__ ((packed)); 158 159 struct qla_ext_dest_addr { 160 union { 161 uint8_t wwnn[8]; 162 uint8_t wwpn[8]; 163 uint8_t id[4]; 164 struct qla_scsi_addr scsi_addr; 165 } dest_addr; 166 uint16_t dest_type; 167 #define EXT_DEF_TYPE_WWPN 2 168 uint16_t lun; 169 uint16_t padding[2]; 170 } __attribute__ ((packed)); 171 172 struct qla_port_param { 173 struct qla_ext_dest_addr fc_scsi_addr; 174 uint16_t mode; 175 uint16_t speed; 176 } __attribute__ ((packed)); 177 178 179 /* FRU VPD */ 180 181 #define MAX_FRU_SIZE 36 182 183 struct qla_field_address { 184 uint16_t offset; 185 uint16_t device; 186 uint16_t option; 187 } __packed; 188 189 struct qla_field_info { 190 uint8_t version[MAX_FRU_SIZE]; 191 } __packed; 192 193 struct qla_image_version { 194 struct qla_field_address field_address; 195 struct qla_field_info field_info; 196 } __packed; 197 198 struct qla_image_version_list { 199 uint32_t count; 200 struct qla_image_version version[0]; 201 } __packed; 202 203 struct qla_status_reg { 204 struct qla_field_address field_address; 205 uint8_t status_reg; 206 uint8_t reserved[7]; 207 } __packed; 208 209 struct qla_i2c_access { 210 uint16_t device; 211 uint16_t offset; 212 uint16_t option; 213 uint16_t length; 214 uint8_t buffer[0x40]; 215 } __packed; 216 217 /* 26xx serdes register interface */ 218 219 /* serdes reg commands */ 220 #define INT_SC_SERDES_READ_REG 1 221 #define INT_SC_SERDES_WRITE_REG 2 222 223 struct qla_serdes_reg { 224 uint16_t cmd; 225 uint16_t addr; 226 uint16_t val; 227 } __packed; 228 229 struct qla_serdes_reg_ex { 230 uint16_t cmd; 231 uint32_t addr; 232 uint32_t val; 233 } __packed; 234 235 #endif 236