1 /****************************************************************************** 2 * QLOGIC LINUX SOFTWARE 3 * 4 * QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver 5 * Copyright (C) 2000 Qlogic Corporation 6 * (www.qlogic.com) 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2, or (at your option) any 11 * later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 ******************************************************************************/ 19 20 #ifndef _QLA1280_H 21 #define _QLA1280_H 22 23 /* 24 * Data bit definitions. 25 */ 26 #define BIT_0 0x1 27 #define BIT_1 0x2 28 #define BIT_2 0x4 29 #define BIT_3 0x8 30 #define BIT_4 0x10 31 #define BIT_5 0x20 32 #define BIT_6 0x40 33 #define BIT_7 0x80 34 #define BIT_8 0x100 35 #define BIT_9 0x200 36 #define BIT_10 0x400 37 #define BIT_11 0x800 38 #define BIT_12 0x1000 39 #define BIT_13 0x2000 40 #define BIT_14 0x4000 41 #define BIT_15 0x8000 42 #define BIT_16 0x10000 43 #define BIT_17 0x20000 44 #define BIT_18 0x40000 45 #define BIT_19 0x80000 46 #define BIT_20 0x100000 47 #define BIT_21 0x200000 48 #define BIT_22 0x400000 49 #define BIT_23 0x800000 50 #define BIT_24 0x1000000 51 #define BIT_25 0x2000000 52 #define BIT_26 0x4000000 53 #define BIT_27 0x8000000 54 #define BIT_28 0x10000000 55 #define BIT_29 0x20000000 56 #define BIT_30 0x40000000 57 #define BIT_31 0x80000000 58 59 #if MEMORY_MAPPED_IO 60 #define RD_REG_WORD(addr) readw_relaxed(addr) 61 #define RD_REG_WORD_dmasync(addr) readw(addr) 62 #define WRT_REG_WORD(addr, data) writew(data, addr) 63 #else /* MEMORY_MAPPED_IO */ 64 #define RD_REG_WORD(addr) inw((unsigned long)addr) 65 #define RD_REG_WORD_dmasync(addr) RD_REG_WORD(addr) 66 #define WRT_REG_WORD(addr, data) outw(data, (unsigned long)addr) 67 #endif /* MEMORY_MAPPED_IO */ 68 69 /* 70 * Host adapter default definitions. 71 */ 72 #define MAX_BUSES 2 /* 2 */ 73 #define MAX_B_BITS 1 74 75 #define MAX_TARGETS 16 /* 16 */ 76 #define MAX_T_BITS 4 /* 4 */ 77 78 #define MAX_LUNS 8 /* 32 */ 79 #define MAX_L_BITS 3 /* 5 */ 80 81 /* 82 * Watchdog time quantum 83 */ 84 #define QLA1280_WDG_TIME_QUANTUM 5 /* In seconds */ 85 86 /* Command retry count (0-65535) */ 87 #define COMMAND_RETRY_COUNT 255 88 89 /* Maximum outstanding commands in ISP queues */ 90 #define MAX_OUTSTANDING_COMMANDS 512 91 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS + 2) 92 93 /* ISP request and response entry counts (37-65535) */ 94 #define REQUEST_ENTRY_CNT 255 /* Number of request entries. */ 95 #define RESPONSE_ENTRY_CNT 63 /* Number of response entries. */ 96 97 /* 98 * SCSI Request Block structure (sp) that is placed 99 * on cmd->SCp location of every I/O 100 */ 101 struct srb { 102 struct list_head list; /* (8/16) LU queue */ 103 struct scsi_cmnd *cmd; /* (4/8) SCSI command block */ 104 /* NOTE: the sp->cmd will be NULL when this completion is 105 * called, so you should know the scsi_cmnd when using this */ 106 struct completion *wait; 107 dma_addr_t saved_dma_handle; /* for unmap of single transfers */ 108 uint8_t flags; /* (1) Status flags. */ 109 uint8_t dir; /* direction of transfer */ 110 }; 111 112 /* 113 * SRB flag definitions 114 */ 115 #define SRB_TIMEOUT (1 << 0) /* Command timed out */ 116 #define SRB_SENT (1 << 1) /* Command sent to ISP */ 117 #define SRB_ABORT_PENDING (1 << 2) /* Command abort sent to device */ 118 #define SRB_ABORTED (1 << 3) /* Command aborted command already */ 119 120 /* 121 * ISP I/O Register Set structure definitions. 122 */ 123 struct device_reg { 124 uint16_t id_l; /* ID low */ 125 uint16_t id_h; /* ID high */ 126 uint16_t cfg_0; /* Configuration 0 */ 127 #define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */ 128 #define ISP_CFG0_1020 BIT_0 /* ISP1020 */ 129 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */ 130 #define ISP_CFG0_1040 BIT_2 /* ISP1040 */ 131 #define ISP_CFG0_1040A BIT_3 /* ISP1040A */ 132 #define ISP_CFG0_1040B BIT_4 /* ISP1040B */ 133 #define ISP_CFG0_1040C BIT_5 /* ISP1040C */ 134 uint16_t cfg_1; /* Configuration 1 */ 135 #define ISP_CFG1_F128 BIT_6 /* 128-byte FIFO threshold */ 136 #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */ 137 #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */ 138 #define ISP_CFG1_F16 BIT_4 /* 128-byte FIFO threshold */ 139 #define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */ 140 #define ISP_CFG1_SXP BIT_0 /* SXP register select */ 141 uint16_t ictrl; /* Interface control */ 142 #define ISP_RESET BIT_0 /* ISP soft reset */ 143 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */ 144 #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */ 145 #define ISP_FLASH_ENABLE BIT_8 /* Flash BIOS Read/Write enable */ 146 #define ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */ 147 uint16_t istatus; /* Interface status */ 148 #define PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */ 149 #define RISC_INT BIT_2 /* RISC interrupt */ 150 #define PCI_INT BIT_1 /* PCI interrupt */ 151 uint16_t semaphore; /* Semaphore */ 152 uint16_t nvram; /* NVRAM register. */ 153 #define NV_DESELECT 0 154 #define NV_CLOCK BIT_0 155 #define NV_SELECT BIT_1 156 #define NV_DATA_OUT BIT_2 157 #define NV_DATA_IN BIT_3 158 uint16_t flash_data; /* Flash BIOS data */ 159 uint16_t flash_address; /* Flash BIOS address */ 160 161 uint16_t unused_1[0x06]; 162 163 /* cdma_* and ddma_* are 1040 only */ 164 uint16_t cdma_cfg; 165 #define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */ 166 #define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */ 167 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */ 168 #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ 169 uint16_t cdma_ctrl; 170 uint16_t cdma_status; 171 uint16_t cdma_fifo_status; 172 uint16_t cdma_count; 173 uint16_t cdma_reserved; 174 uint16_t cdma_address_count_0; 175 uint16_t cdma_address_count_1; 176 uint16_t cdma_address_count_2; 177 uint16_t cdma_address_count_3; 178 179 uint16_t unused_2[0x06]; 180 181 uint16_t ddma_cfg; 182 #define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */ 183 #define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */ 184 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */ 185 #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ 186 uint16_t ddma_ctrl; 187 uint16_t ddma_status; 188 uint16_t ddma_fifo_status; 189 uint16_t ddma_xfer_count_low; 190 uint16_t ddma_xfer_count_high; 191 uint16_t ddma_addr_count_0; 192 uint16_t ddma_addr_count_1; 193 uint16_t ddma_addr_count_2; 194 uint16_t ddma_addr_count_3; 195 196 uint16_t unused_3[0x0e]; 197 198 uint16_t mailbox0; /* Mailbox 0 */ 199 uint16_t mailbox1; /* Mailbox 1 */ 200 uint16_t mailbox2; /* Mailbox 2 */ 201 uint16_t mailbox3; /* Mailbox 3 */ 202 uint16_t mailbox4; /* Mailbox 4 */ 203 uint16_t mailbox5; /* Mailbox 5 */ 204 uint16_t mailbox6; /* Mailbox 6 */ 205 uint16_t mailbox7; /* Mailbox 7 */ 206 207 uint16_t unused_4[0x20];/* 0x80-0xbf Gap */ 208 209 uint16_t host_cmd; /* Host command and control */ 210 #define HOST_INT BIT_7 /* host interrupt bit */ 211 #define BIOS_ENABLE BIT_0 212 213 uint16_t unused_5[0x5]; /* 0xc2-0xcb Gap */ 214 215 uint16_t gpio_data; 216 uint16_t gpio_enable; 217 218 uint16_t unused_6[0x11]; /* d0-f0 */ 219 uint16_t scsiControlPins; /* f2 */ 220 }; 221 222 #define MAILBOX_REGISTER_COUNT 8 223 224 /* 225 * ISP product identification definitions in mailboxes after reset. 226 */ 227 #define PROD_ID_1 0x4953 228 #define PROD_ID_2 0x0000 229 #define PROD_ID_2a 0x5020 230 #define PROD_ID_3 0x2020 231 #define PROD_ID_4 0x1 232 233 /* 234 * ISP host command and control register command definitions 235 */ 236 #define HC_RESET_RISC 0x1000 /* Reset RISC */ 237 #define HC_PAUSE_RISC 0x2000 /* Pause RISC */ 238 #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 239 #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */ 240 #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 241 #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 242 #define HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */ 243 244 /* 245 * ISP mailbox Self-Test status codes 246 */ 247 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 248 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 249 #define MBS_SHADOW_LD_ERR 2 /* Shadow Load Error. */ 250 #define MBS_BUSY 4 /* Busy. */ 251 252 /* 253 * ISP mailbox command complete status codes 254 */ 255 #define MBS_CMD_CMP 0x4000 /* Command Complete. */ 256 #define MBS_INV_CMD 0x4001 /* Invalid Command. */ 257 #define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */ 258 #define MBS_TEST_FAILED 0x4003 /* Test Failed. */ 259 #define MBS_CMD_ERR 0x4005 /* Command Error. */ 260 #define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */ 261 262 /* 263 * ISP mailbox asynchronous event status codes 264 */ 265 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 266 #define MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */ 267 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 268 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 269 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 270 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 271 #define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */ 272 #define MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */ 273 #define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */ 274 #define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */ 275 276 /* 277 * ISP mailbox commands 278 */ 279 #define MBC_NOP 0 /* No Operation */ 280 #define MBC_LOAD_RAM 1 /* Load RAM */ 281 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware */ 282 #define MBC_DUMP_RAM 3 /* Dump RAM contents */ 283 #define MBC_WRITE_RAM_WORD 4 /* Write ram word */ 284 #define MBC_READ_RAM_WORD 5 /* Read ram word */ 285 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 286 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum */ 287 #define MBC_ABOUT_FIRMWARE 8 /* Get firmware revision */ 288 #define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue */ 289 #define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue */ 290 #define MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command */ 291 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command */ 292 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN) */ 293 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID) */ 294 #define MBC_BUS_RESET 0x18 /* SCSI bus reset */ 295 #define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay */ 296 #define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters */ 297 #define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID */ 298 #define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout */ 299 #define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay */ 300 #define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit */ 301 #define MBC_SET_CLOCK_RATE 0x34 /* Set clock rate */ 302 #define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state */ 303 #define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time */ 304 #define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters */ 305 #define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters */ 306 #define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */ 307 #define MBC_SET_RESET_DELAY_PARAMETERS 0x3A /* Set reset delay parameters */ 308 #define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word */ 309 #define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word */ 310 #define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */ 311 #define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64 */ 312 #define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode */ 313 #define MBC_SET_DATA_OVERRUN_RECOVERY 0x5A /* Set data overrun recovery mode */ 314 315 /* 316 * ISP Get/Set Target Parameters mailbox command control flags. 317 */ 318 #define TP_PPR BIT_5 /* PPR */ 319 #define TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */ 320 #define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */ 321 #define TP_AUTO_REQUEST_SENSE BIT_10 /* Automatic request sense. */ 322 #define TP_TAGGED_QUEUE BIT_11 /* Tagged queuing. */ 323 #define TP_SYNC BIT_12 /* Synchronous data transfers. */ 324 #define TP_WIDE BIT_13 /* Wide data transfers. */ 325 #define TP_PARITY BIT_14 /* Parity checking. */ 326 #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */ 327 328 /* 329 * NVRAM Command values. 330 */ 331 #define NV_START_BIT BIT_2 332 #define NV_WRITE_OP (BIT_26 | BIT_24) 333 #define NV_READ_OP (BIT_26 | BIT_25) 334 #define NV_ERASE_OP (BIT_26 | BIT_25 | BIT_24) 335 #define NV_MASK_OP (BIT_26 | BIT_25 | BIT_24) 336 #define NV_DELAY_COUNT 10 337 338 /* 339 * QLogic ISP1280/ISP12160 NVRAM structure definition. 340 */ 341 struct nvram { 342 uint8_t id0; /* 0 */ 343 uint8_t id1; /* 1 */ 344 uint8_t id2; /* 2 */ 345 uint8_t id3; /* 3 */ 346 uint8_t version; /* 4 */ 347 348 struct { 349 uint8_t bios_configuration_mode:2; 350 uint8_t bios_disable:1; 351 uint8_t selectable_scsi_boot_enable:1; 352 uint8_t cd_rom_boot_enable:1; 353 uint8_t disable_loading_risc_code:1; 354 uint8_t enable_64bit_addressing:1; 355 uint8_t unused_7:1; 356 } cntr_flags_1; /* 5 */ 357 358 struct { 359 uint8_t boot_lun_number:5; 360 uint8_t scsi_bus_number:1; 361 uint8_t unused_6:1; 362 uint8_t unused_7:1; 363 } cntr_flags_2l; /* 7 */ 364 365 struct { 366 uint8_t boot_target_number:4; 367 uint8_t unused_12:1; 368 uint8_t unused_13:1; 369 uint8_t unused_14:1; 370 uint8_t unused_15:1; 371 } cntr_flags_2h; /* 8 */ 372 373 uint16_t unused_8; /* 8, 9 */ 374 uint16_t unused_10; /* 10, 11 */ 375 uint16_t unused_12; /* 12, 13 */ 376 uint16_t unused_14; /* 14, 15 */ 377 378 struct { 379 uint8_t reserved:2; 380 uint8_t burst_enable:1; 381 uint8_t reserved_1:1; 382 uint8_t fifo_threshold:4; 383 } isp_config; /* 16 */ 384 385 /* Termination 386 * 0 = Disable, 1 = high only, 3 = Auto term 387 */ 388 struct { 389 uint8_t scsi_bus_1_control:2; 390 uint8_t scsi_bus_0_control:2; 391 uint8_t unused_0:1; 392 uint8_t unused_1:1; 393 uint8_t unused_2:1; 394 uint8_t auto_term_support:1; 395 } termination; /* 17 */ 396 397 uint16_t isp_parameter; /* 18, 19 */ 398 399 union { 400 uint16_t w; 401 struct { 402 uint16_t enable_fast_posting:1; 403 uint16_t report_lvd_bus_transition:1; 404 uint16_t unused_2:1; 405 uint16_t unused_3:1; 406 uint16_t disable_iosbs_with_bus_reset_status:1; 407 uint16_t disable_synchronous_backoff:1; 408 uint16_t unused_6:1; 409 uint16_t synchronous_backoff_reporting:1; 410 uint16_t disable_reselection_fairness:1; 411 uint16_t unused_9:1; 412 uint16_t unused_10:1; 413 uint16_t unused_11:1; 414 uint16_t unused_12:1; 415 uint16_t unused_13:1; 416 uint16_t unused_14:1; 417 uint16_t unused_15:1; 418 } f; 419 } firmware_feature; /* 20, 21 */ 420 421 uint16_t unused_22; /* 22, 23 */ 422 423 struct { 424 struct { 425 uint8_t initiator_id:4; 426 uint8_t scsi_reset_disable:1; 427 uint8_t scsi_bus_size:1; 428 uint8_t scsi_bus_type:1; 429 uint8_t unused_7:1; 430 } config_1; /* 24 */ 431 432 uint8_t bus_reset_delay; /* 25 */ 433 uint8_t retry_count; /* 26 */ 434 uint8_t retry_delay; /* 27 */ 435 436 struct { 437 uint8_t async_data_setup_time:4; 438 uint8_t req_ack_active_negation:1; 439 uint8_t data_line_active_negation:1; 440 uint8_t unused_6:1; 441 uint8_t unused_7:1; 442 } config_2; /* 28 */ 443 444 uint8_t unused_29; /* 29 */ 445 446 uint16_t selection_timeout; /* 30, 31 */ 447 uint16_t max_queue_depth; /* 32, 33 */ 448 449 uint16_t unused_34; /* 34, 35 */ 450 uint16_t unused_36; /* 36, 37 */ 451 uint16_t unused_38; /* 38, 39 */ 452 453 struct { 454 struct { 455 uint8_t renegotiate_on_error:1; 456 uint8_t stop_queue_on_check:1; 457 uint8_t auto_request_sense:1; 458 uint8_t tag_queuing:1; 459 uint8_t enable_sync:1; 460 uint8_t enable_wide:1; 461 uint8_t parity_checking:1; 462 uint8_t disconnect_allowed:1; 463 } parameter; /* 40 */ 464 465 uint8_t execution_throttle; /* 41 */ 466 uint8_t sync_period; /* 42 */ 467 468 union { /* 43 */ 469 uint8_t flags_43; 470 struct { 471 uint8_t sync_offset:4; 472 uint8_t device_enable:1; 473 uint8_t lun_disable:1; 474 uint8_t unused_6:1; 475 uint8_t unused_7:1; 476 } flags1x80; 477 struct { 478 uint8_t sync_offset:5; 479 uint8_t device_enable:1; 480 uint8_t unused_6:1; 481 uint8_t unused_7:1; 482 } flags1x160; 483 } flags; 484 union { /* PPR flags for the 1x160 controllers */ 485 uint8_t unused_44; 486 struct { 487 uint8_t ppr_options:4; 488 uint8_t ppr_bus_width:2; 489 uint8_t unused_8:1; 490 uint8_t enable_ppr:1; 491 } flags; /* 44 */ 492 } ppr_1x160; 493 uint8_t unused_45; /* 45 */ 494 } target[MAX_TARGETS]; 495 } bus[MAX_BUSES]; 496 497 uint16_t unused_248; /* 248, 249 */ 498 499 uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */ 500 501 union { /* 254 */ 502 uint8_t unused_254; 503 uint8_t system_id_pointer; 504 } sysid_1x160; 505 506 uint8_t chksum; /* 255 */ 507 }; 508 509 /* 510 * ISP queue - command entry structure definition. 511 */ 512 #define MAX_CMDSZ 12 /* SCSI maximum CDB size. */ 513 struct cmd_entry { 514 uint8_t entry_type; /* Entry type. */ 515 #define COMMAND_TYPE 1 /* Command entry */ 516 uint8_t entry_count; /* Entry count. */ 517 uint8_t sys_define; /* System defined. */ 518 uint8_t entry_status; /* Entry Status. */ 519 __le32 handle; /* System handle. */ 520 uint8_t lun; /* SCSI LUN */ 521 uint8_t target; /* SCSI ID */ 522 __le16 cdb_len; /* SCSI command length. */ 523 __le16 control_flags; /* Control flags. */ 524 __le16 reserved; 525 __le16 timeout; /* Command timeout. */ 526 __le16 dseg_count; /* Data segment count. */ 527 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 528 __le32 dseg_0_address; /* Data segment 0 address. */ 529 __le32 dseg_0_length; /* Data segment 0 length. */ 530 __le32 dseg_1_address; /* Data segment 1 address. */ 531 __le32 dseg_1_length; /* Data segment 1 length. */ 532 __le32 dseg_2_address; /* Data segment 2 address. */ 533 __le32 dseg_2_length; /* Data segment 2 length. */ 534 __le32 dseg_3_address; /* Data segment 3 address. */ 535 __le32 dseg_3_length; /* Data segment 3 length. */ 536 }; 537 538 /* 539 * ISP queue - continuation entry structure definition. 540 */ 541 struct cont_entry { 542 uint8_t entry_type; /* Entry type. */ 543 #define CONTINUE_TYPE 2 /* Continuation entry. */ 544 uint8_t entry_count; /* Entry count. */ 545 uint8_t sys_define; /* System defined. */ 546 uint8_t entry_status; /* Entry Status. */ 547 __le32 reserved; /* Reserved */ 548 __le32 dseg_0_address; /* Data segment 0 address. */ 549 __le32 dseg_0_length; /* Data segment 0 length. */ 550 __le32 dseg_1_address; /* Data segment 1 address. */ 551 __le32 dseg_1_length; /* Data segment 1 length. */ 552 __le32 dseg_2_address; /* Data segment 2 address. */ 553 __le32 dseg_2_length; /* Data segment 2 length. */ 554 __le32 dseg_3_address; /* Data segment 3 address. */ 555 __le32 dseg_3_length; /* Data segment 3 length. */ 556 __le32 dseg_4_address; /* Data segment 4 address. */ 557 __le32 dseg_4_length; /* Data segment 4 length. */ 558 __le32 dseg_5_address; /* Data segment 5 address. */ 559 __le32 dseg_5_length; /* Data segment 5 length. */ 560 __le32 dseg_6_address; /* Data segment 6 address. */ 561 __le32 dseg_6_length; /* Data segment 6 length. */ 562 }; 563 564 /* 565 * ISP queue - status entry structure definition. 566 */ 567 struct response { 568 uint8_t entry_type; /* Entry type. */ 569 #define STATUS_TYPE 3 /* Status entry. */ 570 uint8_t entry_count; /* Entry count. */ 571 uint8_t sys_define; /* System defined. */ 572 uint8_t entry_status; /* Entry Status. */ 573 #define RF_CONT BIT_0 /* Continuation. */ 574 #define RF_FULL BIT_1 /* Full */ 575 #define RF_BAD_HEADER BIT_2 /* Bad header. */ 576 #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */ 577 __le32 handle; /* System handle. */ 578 __le16 scsi_status; /* SCSI status. */ 579 __le16 comp_status; /* Completion status. */ 580 __le16 state_flags; /* State flags. */ 581 #define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */ 582 #define SF_GOT_SENSE BIT_13 /* Got Sense */ 583 #define SF_GOT_STATUS BIT_12 /* Got Status */ 584 #define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */ 585 #define SF_SENT_CDB BIT_10 /* Send CDB */ 586 #define SF_GOT_TARGET BIT_9 /* */ 587 #define SF_GOT_BUS BIT_8 /* */ 588 __le16 status_flags; /* Status flags. */ 589 __le16 time; /* Time. */ 590 __le16 req_sense_length;/* Request sense data length. */ 591 __le32 residual_length; /* Residual transfer length. */ 592 __le16 reserved[4]; 593 uint8_t req_sense_data[32]; /* Request sense data. */ 594 }; 595 596 /* 597 * ISP queue - marker entry structure definition. 598 */ 599 struct mrk_entry { 600 uint8_t entry_type; /* Entry type. */ 601 #define MARKER_TYPE 4 /* Marker entry. */ 602 uint8_t entry_count; /* Entry count. */ 603 uint8_t sys_define; /* System defined. */ 604 uint8_t entry_status; /* Entry Status. */ 605 __le32 reserved; 606 uint8_t lun; /* SCSI LUN */ 607 uint8_t target; /* SCSI ID */ 608 uint8_t modifier; /* Modifier (7-0). */ 609 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 610 #define MK_SYNC_ID 1 /* Synchronize ID */ 611 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 612 uint8_t reserved_1[53]; 613 }; 614 615 /* 616 * ISP queue - extended command entry structure definition. 617 * 618 * Unused by the driver! 619 */ 620 struct ecmd_entry { 621 uint8_t entry_type; /* Entry type. */ 622 #define EXTENDED_CMD_TYPE 5 /* Extended command entry. */ 623 uint8_t entry_count; /* Entry count. */ 624 uint8_t sys_define; /* System defined. */ 625 uint8_t entry_status; /* Entry Status. */ 626 uint32_t handle; /* System handle. */ 627 uint8_t lun; /* SCSI LUN */ 628 uint8_t target; /* SCSI ID */ 629 __le16 cdb_len; /* SCSI command length. */ 630 __le16 control_flags; /* Control flags. */ 631 __le16 reserved; 632 __le16 timeout; /* Command timeout. */ 633 __le16 dseg_count; /* Data segment count. */ 634 uint8_t scsi_cdb[88]; /* SCSI command words. */ 635 }; 636 637 /* 638 * ISP queue - 64-Bit addressing, command entry structure definition. 639 */ 640 typedef struct { 641 uint8_t entry_type; /* Entry type. */ 642 #define COMMAND_A64_TYPE 9 /* Command A64 entry */ 643 uint8_t entry_count; /* Entry count. */ 644 uint8_t sys_define; /* System defined. */ 645 uint8_t entry_status; /* Entry Status. */ 646 __le32 handle; /* System handle. */ 647 uint8_t lun; /* SCSI LUN */ 648 uint8_t target; /* SCSI ID */ 649 __le16 cdb_len; /* SCSI command length. */ 650 __le16 control_flags; /* Control flags. */ 651 __le16 reserved; 652 __le16 timeout; /* Command timeout. */ 653 __le16 dseg_count; /* Data segment count. */ 654 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 655 __le32 reserved_1[2]; /* unused */ 656 __le32 dseg_0_address[2]; /* Data segment 0 address. */ 657 __le32 dseg_0_length; /* Data segment 0 length. */ 658 __le32 dseg_1_address[2]; /* Data segment 1 address. */ 659 __le32 dseg_1_length; /* Data segment 1 length. */ 660 } cmd_a64_entry_t, request_t; 661 662 /* 663 * ISP queue - 64-Bit addressing, continuation entry structure definition. 664 */ 665 struct cont_a64_entry { 666 uint8_t entry_type; /* Entry type. */ 667 #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */ 668 uint8_t entry_count; /* Entry count. */ 669 uint8_t sys_define; /* System defined. */ 670 uint8_t entry_status; /* Entry Status. */ 671 __le32 dseg_0_address[2]; /* Data segment 0 address. */ 672 __le32 dseg_0_length; /* Data segment 0 length. */ 673 __le32 dseg_1_address[2]; /* Data segment 1 address. */ 674 __le32 dseg_1_length; /* Data segment 1 length. */ 675 __le32 dseg_2_address[2]; /* Data segment 2 address. */ 676 __le32 dseg_2_length; /* Data segment 2 length. */ 677 __le32 dseg_3_address[2]; /* Data segment 3 address. */ 678 __le32 dseg_3_length; /* Data segment 3 length. */ 679 __le32 dseg_4_address[2]; /* Data segment 4 address. */ 680 __le32 dseg_4_length; /* Data segment 4 length. */ 681 }; 682 683 /* 684 * ISP queue - enable LUN entry structure definition. 685 */ 686 struct elun_entry { 687 uint8_t entry_type; /* Entry type. */ 688 #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */ 689 uint8_t entry_count; /* Entry count. */ 690 uint8_t reserved_1; 691 uint8_t entry_status; /* Entry Status not used. */ 692 __le32 reserved_2; 693 __le16 lun; /* Bit 15 is bus number. */ 694 __le16 reserved_4; 695 __le32 option_flags; 696 uint8_t status; 697 uint8_t reserved_5; 698 uint8_t command_count; /* Number of ATIOs allocated. */ 699 uint8_t immed_notify_count; /* Number of Immediate Notify */ 700 /* entries allocated. */ 701 uint8_t group_6_length; /* SCSI CDB length for group 6 */ 702 /* commands (2-26). */ 703 uint8_t group_7_length; /* SCSI CDB length for group 7 */ 704 /* commands (2-26). */ 705 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 706 __le16 reserved_6[20]; 707 }; 708 709 /* 710 * ISP queue - modify LUN entry structure definition. 711 * 712 * Unused by the driver! 713 */ 714 struct modify_lun_entry { 715 uint8_t entry_type; /* Entry type. */ 716 #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */ 717 uint8_t entry_count; /* Entry count. */ 718 uint8_t reserved_1; 719 uint8_t entry_status; /* Entry Status. */ 720 __le32 reserved_2; 721 uint8_t lun; /* SCSI LUN */ 722 uint8_t reserved_3; 723 uint8_t operators; 724 uint8_t reserved_4; 725 __le32 option_flags; 726 uint8_t status; 727 uint8_t reserved_5; 728 uint8_t command_count; /* Number of ATIOs allocated. */ 729 uint8_t immed_notify_count; /* Number of Immediate Notify */ 730 /* entries allocated. */ 731 __le16 reserved_6; 732 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 733 __le16 reserved_7[20]; 734 }; 735 736 /* 737 * ISP queue - immediate notify entry structure definition. 738 */ 739 struct notify_entry { 740 uint8_t entry_type; /* Entry type. */ 741 #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */ 742 uint8_t entry_count; /* Entry count. */ 743 uint8_t reserved_1; 744 uint8_t entry_status; /* Entry Status. */ 745 __le32 reserved_2; 746 uint8_t lun; 747 uint8_t initiator_id; 748 uint8_t reserved_3; 749 uint8_t target_id; 750 __le32 option_flags; 751 uint8_t status; 752 uint8_t reserved_4; 753 uint8_t tag_value; /* Received queue tag message value */ 754 uint8_t tag_type; /* Received queue tag message type */ 755 /* entries allocated. */ 756 __le16 seq_id; 757 uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */ 758 __le16 reserved_5[8]; 759 uint8_t sense_data[18]; 760 }; 761 762 /* 763 * ISP queue - notify acknowledge entry structure definition. 764 */ 765 struct nack_entry { 766 uint8_t entry_type; /* Entry type. */ 767 #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */ 768 uint8_t entry_count; /* Entry count. */ 769 uint8_t reserved_1; 770 uint8_t entry_status; /* Entry Status. */ 771 __le32 reserved_2; 772 uint8_t lun; 773 uint8_t initiator_id; 774 uint8_t reserved_3; 775 uint8_t target_id; 776 __le32 option_flags; 777 uint8_t status; 778 uint8_t event; 779 __le16 seq_id; 780 __le16 reserved_4[22]; 781 }; 782 783 /* 784 * ISP queue - Accept Target I/O (ATIO) entry structure definition. 785 */ 786 struct atio_entry { 787 uint8_t entry_type; /* Entry type. */ 788 #define ACCEPT_TGT_IO_TYPE 6 /* Accept target I/O entry. */ 789 uint8_t entry_count; /* Entry count. */ 790 uint8_t reserved_1; 791 uint8_t entry_status; /* Entry Status. */ 792 __le32 reserved_2; 793 uint8_t lun; 794 uint8_t initiator_id; 795 uint8_t cdb_len; 796 uint8_t target_id; 797 __le32 option_flags; 798 uint8_t status; 799 uint8_t scsi_status; 800 uint8_t tag_value; /* Received queue tag message value */ 801 uint8_t tag_type; /* Received queue tag message type */ 802 uint8_t cdb[26]; 803 uint8_t sense_data[18]; 804 }; 805 806 /* 807 * ISP queue - Continue Target I/O (CTIO) entry structure definition. 808 */ 809 struct ctio_entry { 810 uint8_t entry_type; /* Entry type. */ 811 #define CONTINUE_TGT_IO_TYPE 7 /* CTIO entry */ 812 uint8_t entry_count; /* Entry count. */ 813 uint8_t reserved_1; 814 uint8_t entry_status; /* Entry Status. */ 815 __le32 reserved_2; 816 uint8_t lun; /* SCSI LUN */ 817 uint8_t initiator_id; 818 uint8_t reserved_3; 819 uint8_t target_id; 820 __le32 option_flags; 821 uint8_t status; 822 uint8_t scsi_status; 823 uint8_t tag_value; /* Received queue tag message value */ 824 uint8_t tag_type; /* Received queue tag message type */ 825 __le32 transfer_length; 826 __le32 residual; 827 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 828 __le16 dseg_count; /* Data segment count. */ 829 __le32 dseg_0_address; /* Data segment 0 address. */ 830 __le32 dseg_0_length; /* Data segment 0 length. */ 831 __le32 dseg_1_address; /* Data segment 1 address. */ 832 __le32 dseg_1_length; /* Data segment 1 length. */ 833 __le32 dseg_2_address; /* Data segment 2 address. */ 834 __le32 dseg_2_length; /* Data segment 2 length. */ 835 __le32 dseg_3_address; /* Data segment 3 address. */ 836 __le32 dseg_3_length; /* Data segment 3 length. */ 837 }; 838 839 /* 840 * ISP queue - CTIO returned entry structure definition. 841 */ 842 struct ctio_ret_entry { 843 uint8_t entry_type; /* Entry type. */ 844 #define CTIO_RET_TYPE 7 /* CTIO return entry */ 845 uint8_t entry_count; /* Entry count. */ 846 uint8_t reserved_1; 847 uint8_t entry_status; /* Entry Status. */ 848 __le32 reserved_2; 849 uint8_t lun; /* SCSI LUN */ 850 uint8_t initiator_id; 851 uint8_t reserved_3; 852 uint8_t target_id; 853 __le32 option_flags; 854 uint8_t status; 855 uint8_t scsi_status; 856 uint8_t tag_value; /* Received queue tag message value */ 857 uint8_t tag_type; /* Received queue tag message type */ 858 __le32 transfer_length; 859 __le32 residual; 860 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 861 __le16 dseg_count; /* Data segment count. */ 862 __le32 dseg_0_address; /* Data segment 0 address. */ 863 __le32 dseg_0_length; /* Data segment 0 length. */ 864 __le32 dseg_1_address; /* Data segment 1 address. */ 865 __le16 dseg_1_length; /* Data segment 1 length. */ 866 uint8_t sense_data[18]; 867 }; 868 869 /* 870 * ISP queue - CTIO A64 entry structure definition. 871 */ 872 struct ctio_a64_entry { 873 uint8_t entry_type; /* Entry type. */ 874 #define CTIO_A64_TYPE 0xF /* CTIO A64 entry */ 875 uint8_t entry_count; /* Entry count. */ 876 uint8_t reserved_1; 877 uint8_t entry_status; /* Entry Status. */ 878 __le32 reserved_2; 879 uint8_t lun; /* SCSI LUN */ 880 uint8_t initiator_id; 881 uint8_t reserved_3; 882 uint8_t target_id; 883 __le32 option_flags; 884 uint8_t status; 885 uint8_t scsi_status; 886 uint8_t tag_value; /* Received queue tag message value */ 887 uint8_t tag_type; /* Received queue tag message type */ 888 __le32 transfer_length; 889 __le32 residual; 890 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 891 __le16 dseg_count; /* Data segment count. */ 892 __le32 reserved_4[2]; 893 __le32 dseg_0_address[2];/* Data segment 0 address. */ 894 __le32 dseg_0_length; /* Data segment 0 length. */ 895 __le32 dseg_1_address[2];/* Data segment 1 address. */ 896 __le32 dseg_1_length; /* Data segment 1 length. */ 897 }; 898 899 /* 900 * ISP queue - CTIO returned entry structure definition. 901 */ 902 struct ctio_a64_ret_entry { 903 uint8_t entry_type; /* Entry type. */ 904 #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */ 905 uint8_t entry_count; /* Entry count. */ 906 uint8_t reserved_1; 907 uint8_t entry_status; /* Entry Status. */ 908 __le32 reserved_2; 909 uint8_t lun; /* SCSI LUN */ 910 uint8_t initiator_id; 911 uint8_t reserved_3; 912 uint8_t target_id; 913 __le32 option_flags; 914 uint8_t status; 915 uint8_t scsi_status; 916 uint8_t tag_value; /* Received queue tag message value */ 917 uint8_t tag_type; /* Received queue tag message type */ 918 __le32 transfer_length; 919 __le32 residual; 920 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 921 __le16 dseg_count; /* Data segment count. */ 922 __le16 reserved_4[7]; 923 uint8_t sense_data[18]; 924 }; 925 926 /* 927 * ISP request and response queue entry sizes 928 */ 929 #define RESPONSE_ENTRY_SIZE (sizeof(struct response)) 930 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 931 932 /* 933 * ISP status entry - completion status definitions. 934 */ 935 #define CS_COMPLETE 0x0 /* No errors */ 936 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 937 #define CS_DMA 0x2 /* A DMA direction error. */ 938 #define CS_TRANSPORT 0x3 /* Transport error. */ 939 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 940 #define CS_ABORTED 0x5 /* System aborted command. */ 941 #define CS_TIMEOUT 0x6 /* Timeout error. */ 942 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 943 #define CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */ 944 #define CS_STATUS_OVERRUN 0x9 /* Status Overrun. */ 945 #define CS_BAD_MSG 0xA /* Bad msg after status phase. */ 946 #define CS_NO_MSG_OUT 0xB /* No msg out after selection. */ 947 #define CS_EXTENDED_ID 0xC /* Extended ID failed. */ 948 #define CS_IDE_MSG 0xD /* Target rejected IDE msg. */ 949 #define CS_ABORT_MSG 0xE /* Target rejected abort msg. */ 950 #define CS_REJECT_MSG 0xF /* Target rejected reject msg. */ 951 #define CS_NOP_MSG 0x10 /* Target rejected NOP msg. */ 952 #define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */ 953 #define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */ 954 #define CS_ID_MSG 0x13 /* Target rejected ID msg. */ 955 #define CS_FREE 0x14 /* Unexpected bus free. */ 956 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 957 #define CS_TRANACTION_1 0x18 /* Transaction error 1 */ 958 #define CS_TRANACTION_2 0x19 /* Transaction error 2 */ 959 #define CS_TRANACTION_3 0x1a /* Transaction error 3 */ 960 #define CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */ 961 #define CS_DEV_QUEUE_FULL 0x1c /* Device queue full */ 962 #define CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */ 963 #define CS_ARS_FAILED 0x1e /* ARS failed */ 964 #define CS_LVD_BUS_ERROR 0x21 /* LVD bus error */ 965 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 966 #define CS_UNKNOWN 0x81 /* Driver defined */ 967 #define CS_RETRY 0x82 /* Driver defined */ 968 969 /* 970 * ISP target entries - Option flags bit definitions. 971 */ 972 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */ 973 #define OF_DATA_IN BIT_6 /* Data in to initiator */ 974 /* (data from target to initiator) */ 975 #define OF_DATA_OUT BIT_7 /* Data out from initiator */ 976 /* (data from initiator to target) */ 977 #define OF_NO_DATA (BIT_7 | BIT_6) 978 #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */ 979 #define OF_DISABLE_SDP BIT_24 /* Disable sending save data ptr */ 980 #define OF_SEND_RDP BIT_26 /* Send restore data pointers msg */ 981 #define OF_FORCE_DISC BIT_30 /* Disconnects mandatory */ 982 #define OF_SSTS BIT_31 /* Send SCSI status */ 983 984 985 /* 986 * BUS parameters/settings structure - UNUSED 987 */ 988 struct bus_param { 989 uint8_t id; /* Host adapter SCSI id */ 990 uint8_t bus_reset_delay; /* SCSI bus reset delay. */ 991 uint8_t failed_reset_count; /* number of time reset failed */ 992 uint8_t unused; 993 uint16_t device_enables; /* Device enable bits. */ 994 uint16_t lun_disables; /* LUN disable bits. */ 995 uint16_t qtag_enables; /* Tag queue enables. */ 996 uint16_t hiwat; /* High water mark per device. */ 997 uint8_t reset_marker:1; 998 uint8_t disable_scsi_reset:1; 999 uint8_t scsi_bus_dead:1; /* SCSI Bus is Dead, when 5 back to back resets failed */ 1000 }; 1001 1002 1003 struct qla_driver_setup { 1004 uint32_t no_sync:1; 1005 uint32_t no_wide:1; 1006 uint32_t no_ppr:1; 1007 uint32_t no_nvram:1; 1008 uint16_t sync_mask; 1009 uint16_t wide_mask; 1010 uint16_t ppr_mask; 1011 }; 1012 1013 1014 /* 1015 * Linux Host Adapter structure 1016 */ 1017 struct scsi_qla_host { 1018 /* Linux adapter configuration data */ 1019 struct Scsi_Host *host; /* pointer to host data */ 1020 struct scsi_qla_host *next; 1021 struct device_reg __iomem *iobase; /* Base Memory-mapped I/O address */ 1022 1023 unsigned char __iomem *mmpbase; /* memory mapped address */ 1024 unsigned long host_no; 1025 struct pci_dev *pdev; 1026 uint8_t devnum; 1027 uint8_t revision; 1028 uint8_t ports; 1029 1030 unsigned long actthreads; 1031 unsigned long isr_count; /* Interrupt count */ 1032 unsigned long spurious_int; 1033 1034 /* Outstandings ISP commands. */ 1035 struct srb *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; 1036 1037 /* BUS configuration data */ 1038 struct bus_param bus_settings[MAX_BUSES]; 1039 1040 /* Received ISP mailbox data. */ 1041 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 1042 1043 dma_addr_t request_dma; /* Physical Address */ 1044 request_t *request_ring; /* Base virtual address */ 1045 request_t *request_ring_ptr; /* Current address. */ 1046 uint16_t req_ring_index; /* Current index. */ 1047 uint16_t req_q_cnt; /* Number of available entries. */ 1048 1049 dma_addr_t response_dma; /* Physical address. */ 1050 struct response *response_ring; /* Base virtual address */ 1051 struct response *response_ring_ptr; /* Current address. */ 1052 uint16_t rsp_ring_index; /* Current index. */ 1053 1054 struct list_head done_q; /* Done queue */ 1055 1056 struct completion *mailbox_wait; 1057 1058 volatile struct { 1059 uint32_t online:1; /* 0 */ 1060 uint32_t reset_marker:1; /* 1 */ 1061 uint32_t disable_host_adapter:1; /* 2 */ 1062 uint32_t reset_active:1; /* 3 */ 1063 uint32_t abort_isp_active:1; /* 4 */ 1064 uint32_t disable_risc_code_load:1; /* 5 */ 1065 #ifdef __ia64__ 1066 uint32_t use_pci_vchannel:1; 1067 #endif 1068 } flags; 1069 1070 struct nvram nvram; 1071 int nvram_valid; 1072 }; 1073 1074 #endif /* _QLA1280_H */ 1075