1 /* 2 * pmcraid.h -- PMC Sierra MaxRAID controller driver header file 3 * 4 * Written By: Anil Ravindranath<anil_ravindranath@pmc-sierra.com> 5 * PMC-Sierra Inc 6 * 7 * Copyright (C) 2008, 2009 PMC Sierra Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24 #ifndef _PMCRAID_H 25 #define _PMCRAID_H 26 27 #include <linux/version.h> 28 #include <linux/types.h> 29 #include <linux/completion.h> 30 #include <linux/list.h> 31 #include <scsi/scsi.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <linux/cdev.h> 34 #include <net/netlink.h> 35 #include <net/genetlink.h> 36 #include <linux/connector.h> 37 /* 38 * Driver name : string representing the driver name 39 * Device file : /dev file to be used for management interfaces 40 * Driver version: version string in major_version.minor_version.patch format 41 * Driver date : date information in "Mon dd yyyy" format 42 */ 43 #define PMCRAID_DRIVER_NAME "PMC MaxRAID" 44 #define PMCRAID_DEVFILE "pmcsas" 45 #define PMCRAID_DRIVER_VERSION "1.0.2" 46 #define PMCRAID_DRIVER_DATE __DATE__ 47 48 /* Maximum number of adapters supported by current version of the driver */ 49 #define PMCRAID_MAX_ADAPTERS 1024 50 51 /* Bit definitions as per firmware, bit position [0][1][2].....[31] */ 52 #define PMC_BIT8(n) (1 << (7-n)) 53 #define PMC_BIT16(n) (1 << (15-n)) 54 #define PMC_BIT32(n) (1 << (31-n)) 55 56 /* PMC PCI vendor ID and device ID values */ 57 #define PCI_VENDOR_ID_PMC 0x11F8 58 #define PCI_DEVICE_ID_PMC_MAXRAID 0x5220 59 60 /* 61 * MAX_CMD : maximum commands that can be outstanding with IOA 62 * MAX_IO_CMD : command blocks available for IO commands 63 * MAX_HCAM_CMD : command blocks avaibale for HCAMS 64 * MAX_INTERNAL_CMD : command blocks avaible for internal commands like reset 65 */ 66 #define PMCRAID_MAX_CMD 1024 67 #define PMCRAID_MAX_IO_CMD 1020 68 #define PMCRAID_MAX_HCAM_CMD 2 69 #define PMCRAID_MAX_INTERNAL_CMD 2 70 71 /* MAX_IOADLS : max number of scatter-gather lists supported by IOA 72 * IOADLS_INTERNAL : number of ioadls included as part of IOARCB. 73 * IOADLS_EXTERNAL : number of ioadls allocated external to IOARCB 74 */ 75 #define PMCRAID_IOADLS_INTERNAL 27 76 #define PMCRAID_IOADLS_EXTERNAL 37 77 #define PMCRAID_MAX_IOADLS PMCRAID_IOADLS_INTERNAL 78 79 /* HRRQ_ENTRY_SIZE : size of hrrq buffer 80 * IOARCB_ALIGNMENT : alignment required for IOARCB 81 * IOADL_ALIGNMENT : alignment requirement for IOADLs 82 * MSIX_VECTORS : number of MSIX vectors supported 83 */ 84 #define HRRQ_ENTRY_SIZE sizeof(__le32) 85 #define PMCRAID_IOARCB_ALIGNMENT 32 86 #define PMCRAID_IOADL_ALIGNMENT 16 87 #define PMCRAID_IOASA_ALIGNMENT 4 88 #define PMCRAID_NUM_MSIX_VECTORS 1 89 90 /* various other limits */ 91 #define PMCRAID_VENDOR_ID_LEN 8 92 #define PMCRAID_PRODUCT_ID_LEN 16 93 #define PMCRAID_SERIAL_NUM_LEN 8 94 #define PMCRAID_LUN_LEN 8 95 #define PMCRAID_MAX_CDB_LEN 16 96 #define PMCRAID_DEVICE_ID_LEN 8 97 #define PMCRAID_SENSE_DATA_LEN 256 98 #define PMCRAID_ADD_CMD_PARAM_LEN 48 99 100 #define PMCRAID_MAX_BUS_TO_SCAN 1 101 #define PMCRAID_MAX_NUM_TARGETS_PER_BUS 256 102 #define PMCRAID_MAX_NUM_LUNS_PER_TARGET 8 103 104 /* IOA bus/target/lun number of IOA resources */ 105 #define PMCRAID_IOA_BUS_ID 0xfe 106 #define PMCRAID_IOA_TARGET_ID 0xff 107 #define PMCRAID_IOA_LUN_ID 0xff 108 #define PMCRAID_VSET_BUS_ID 0x1 109 #define PMCRAID_VSET_LUN_ID 0x0 110 #define PMCRAID_PHYS_BUS_ID 0x0 111 #define PMCRAID_VIRTUAL_ENCL_BUS_ID 0x8 112 #define PMCRAID_MAX_VSET_TARGETS 0x7F 113 #define PMCRAID_MAX_VSET_LUNS_PER_TARGET 8 114 115 #define PMCRAID_IOA_MAX_SECTORS 32767 116 #define PMCRAID_VSET_MAX_SECTORS 512 117 #define PMCRAID_MAX_CMD_PER_LUN 254 118 119 /* Number of configuration table entries (resources) */ 120 #define PMCRAID_MAX_NUM_OF_VSETS 240 121 122 /* Todo : Check max limit for Phase 1 */ 123 #define PMCRAID_MAX_NUM_OF_PHY_DEVS 256 124 125 /* MAX_NUM_OF_DEVS includes 1 FP, 1 Dummy Enclosure device */ 126 #define PMCRAID_MAX_NUM_OF_DEVS \ 127 (PMCRAID_MAX_NUM_OF_VSETS + PMCRAID_MAX_NUM_OF_PHY_DEVS + 2) 128 129 #define PMCRAID_MAX_RESOURCES PMCRAID_MAX_NUM_OF_DEVS 130 131 /* Adapter Commands used by driver */ 132 #define PMCRAID_QUERY_RESOURCE_STATE 0xC2 133 #define PMCRAID_RESET_DEVICE 0xC3 134 /* options to select reset target */ 135 #define ENABLE_RESET_MODIFIER 0x80 136 #define RESET_DEVICE_LUN 0x40 137 #define RESET_DEVICE_TARGET 0x20 138 #define RESET_DEVICE_BUS 0x10 139 140 #define PMCRAID_IDENTIFY_HRRQ 0xC4 141 #define PMCRAID_QUERY_IOA_CONFIG 0xC5 142 #define PMCRAID_QUERY_CMD_STATUS 0xCB 143 #define PMCRAID_ABORT_CMD 0xC7 144 145 /* CANCEL ALL command, provides option for setting SYNC_COMPLETE 146 * on the target resources for which commands got cancelled 147 */ 148 #define PMCRAID_CANCEL_ALL_REQUESTS 0xCE 149 #define PMCRAID_SYNC_COMPLETE_AFTER_CANCEL PMC_BIT8(0) 150 151 /* HCAM command and types of HCAM supported by IOA */ 152 #define PMCRAID_HOST_CONTROLLED_ASYNC 0xCF 153 #define PMCRAID_HCAM_CODE_CONFIG_CHANGE 0x01 154 #define PMCRAID_HCAM_CODE_LOG_DATA 0x02 155 156 /* IOA shutdown command and various shutdown types */ 157 #define PMCRAID_IOA_SHUTDOWN 0xF7 158 #define PMCRAID_SHUTDOWN_NORMAL 0x00 159 #define PMCRAID_SHUTDOWN_PREPARE_FOR_NORMAL 0x40 160 #define PMCRAID_SHUTDOWN_NONE 0x100 161 #define PMCRAID_SHUTDOWN_ABBREV 0x80 162 163 /* SET SUPPORTED DEVICES command and the option to select all the 164 * devices to be supported 165 */ 166 #define PMCRAID_SET_SUPPORTED_DEVICES 0xFB 167 #define ALL_DEVICES_SUPPORTED PMC_BIT8(0) 168 169 /* This option is used with SCSI WRITE_BUFFER command */ 170 #define PMCRAID_WR_BUF_DOWNLOAD_AND_SAVE 0x05 171 172 /* IOASC Codes used by driver */ 173 #define PMCRAID_IOASC_SENSE_MASK 0xFFFFFF00 174 #define PMCRAID_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) 175 #define PMCRAID_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) 176 #define PMCRAID_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) 177 #define PMCRAID_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) 178 179 #define PMCRAID_IOASC_GOOD_COMPLETION 0x00000000 180 #define PMCRAID_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 181 #define PMCRAID_IOASC_NR_IOA_RESET_REQUIRED 0x02048000 182 #define PMCRAID_IOASC_NR_SYNC_REQUIRED 0x023F0000 183 #define PMCRAID_IOASC_ME_READ_ERROR_NO_REALLOC 0x03110C00 184 #define PMCRAID_IOASC_HW_CANNOT_COMMUNICATE 0x04050000 185 #define PMCRAID_IOASC_HW_DEVICE_TIMEOUT 0x04080100 186 #define PMCRAID_IOASC_HW_DEVICE_BUS_STATUS_ERROR 0x04448500 187 #define PMCRAID_IOASC_HW_IOA_RESET_REQUIRED 0x04448600 188 #define PMCRAID_IOASC_IR_INVALID_RESOURCE_HANDLE 0x05250000 189 #define PMCRAID_IOASC_AC_TERMINATED_BY_HOST 0x0B5A0000 190 #define PMCRAID_IOASC_UA_BUS_WAS_RESET 0x06290000 191 #define PMCRAID_IOASC_UA_BUS_WAS_RESET_BY_OTHER 0x06298000 192 193 /* Driver defined IOASCs */ 194 #define PMCRAID_IOASC_IOA_WAS_RESET 0x10000001 195 #define PMCRAID_IOASC_PCI_ACCESS_ERROR 0x10000002 196 197 /* Various timeout values (in milliseconds) used. If any of these are chip 198 * specific, move them to pmcraid_chip_details structure. 199 */ 200 #define PMCRAID_PCI_DEASSERT_TIMEOUT 2000 201 #define PMCRAID_BIST_TIMEOUT 2000 202 #define PMCRAID_AENWAIT_TIMEOUT 5000 203 #define PMCRAID_TRANSOP_TIMEOUT 60000 204 205 #define PMCRAID_RESET_TIMEOUT (2 * HZ) 206 #define PMCRAID_CHECK_FOR_RESET_TIMEOUT ((HZ / 10)) 207 #define PMCRAID_VSET_IO_TIMEOUT (60 * HZ) 208 #define PMCRAID_INTERNAL_TIMEOUT (60 * HZ) 209 #define PMCRAID_SHUTDOWN_TIMEOUT (150 * HZ) 210 #define PMCRAID_RESET_BUS_TIMEOUT (60 * HZ) 211 #define PMCRAID_RESET_HOST_TIMEOUT (150 * HZ) 212 #define PMCRAID_REQUEST_SENSE_TIMEOUT (30 * HZ) 213 #define PMCRAID_SET_SUP_DEV_TIMEOUT (2 * 60 * HZ) 214 215 /* structure to represent a scatter-gather element (IOADL descriptor) */ 216 struct pmcraid_ioadl_desc { 217 __le64 address; 218 __le32 data_len; 219 __u8 reserved[3]; 220 __u8 flags; 221 } __attribute__((packed, aligned(PMCRAID_IOADL_ALIGNMENT))); 222 223 /* pmcraid_ioadl_desc.flags values */ 224 #define IOADL_FLAGS_CHAINED PMC_BIT8(0) 225 #define IOADL_FLAGS_LAST_DESC PMC_BIT8(1) 226 #define IOADL_FLAGS_READ_LAST PMC_BIT8(1) 227 #define IOADL_FLAGS_WRITE_LAST PMC_BIT8(1) 228 229 230 /* additional IOARCB data which can be CDB or additional request parameters 231 * or list of IOADLs. Firmware supports max of 512 bytes for IOARCB, hence then 232 * number of IOADLs are limted to 27. In case they are more than 27, they will 233 * be used in chained form 234 */ 235 struct pmcraid_ioarcb_add_data { 236 union { 237 struct pmcraid_ioadl_desc ioadl[PMCRAID_IOADLS_INTERNAL]; 238 __u8 add_cmd_params[PMCRAID_ADD_CMD_PARAM_LEN]; 239 } u; 240 }; 241 242 /* 243 * IOA Request Control Block 244 */ 245 struct pmcraid_ioarcb { 246 __le64 ioarcb_bus_addr; 247 __le32 resource_handle; 248 __le32 response_handle; 249 __le64 ioadl_bus_addr; 250 __le32 ioadl_length; 251 __le32 data_transfer_length; 252 __le64 ioasa_bus_addr; 253 __le16 ioasa_len; 254 __le16 cmd_timeout; 255 __le16 add_cmd_param_offset; 256 __le16 add_cmd_param_length; 257 __le32 reserved1[2]; 258 __le32 reserved2; 259 __u8 request_type; 260 __u8 request_flags0; 261 __u8 request_flags1; 262 __u8 hrrq_id; 263 __u8 cdb[PMCRAID_MAX_CDB_LEN]; 264 struct pmcraid_ioarcb_add_data add_data; 265 } __attribute__((packed, aligned(PMCRAID_IOARCB_ALIGNMENT))); 266 267 /* well known resource handle values */ 268 #define PMCRAID_IOA_RES_HANDLE 0xffffffff 269 #define PMCRAID_INVALID_RES_HANDLE 0 270 271 /* pmcraid_ioarcb.request_type values */ 272 #define REQ_TYPE_SCSI 0x00 273 #define REQ_TYPE_IOACMD 0x01 274 #define REQ_TYPE_HCAM 0x02 275 276 /* pmcraid_ioarcb.flags0 values */ 277 #define TRANSFER_DIR_WRITE PMC_BIT8(0) 278 #define INHIBIT_UL_CHECK PMC_BIT8(2) 279 #define SYNC_OVERRIDE PMC_BIT8(3) 280 #define SYNC_COMPLETE PMC_BIT8(4) 281 #define NO_LINK_DESCS PMC_BIT8(5) 282 283 /* pmcraid_ioarcb.flags1 values */ 284 #define DELAY_AFTER_RESET PMC_BIT8(0) 285 #define TASK_TAG_SIMPLE 0x10 286 #define TASK_TAG_ORDERED 0x20 287 #define TASK_TAG_QUEUE_HEAD 0x30 288 289 /* toggle bit offset in response handle */ 290 #define HRRQ_TOGGLE_BIT 0x01 291 #define HRRQ_RESPONSE_BIT 0x02 292 293 /* IOA Status Area */ 294 struct pmcraid_ioasa_vset { 295 __le32 failing_lba_hi; 296 __le32 failing_lba_lo; 297 __le32 reserved; 298 } __attribute__((packed, aligned(4))); 299 300 struct pmcraid_ioasa { 301 __le32 ioasc; 302 __le16 returned_status_length; 303 __le16 available_status_length; 304 __le32 residual_data_length; 305 __le32 ilid; 306 __le32 fd_ioasc; 307 __le32 fd_res_address; 308 __le32 fd_res_handle; 309 __le32 reserved; 310 311 /* resource specific sense information */ 312 union { 313 struct pmcraid_ioasa_vset vset; 314 } u; 315 316 /* IOA autosense data */ 317 __le16 auto_sense_length; 318 __le16 error_data_length; 319 __u8 sense_data[PMCRAID_SENSE_DATA_LEN]; 320 } __attribute__((packed, aligned(4))); 321 322 #define PMCRAID_DRIVER_ILID 0xffffffff 323 324 /* Config Table Entry per Resource */ 325 struct pmcraid_config_table_entry { 326 __u8 resource_type; 327 __u8 bus_protocol; 328 __le16 array_id; 329 __u8 common_flags0; 330 __u8 common_flags1; 331 __u8 unique_flags0; 332 __u8 unique_flags1; /*also used as vset target_id */ 333 __le32 resource_handle; 334 __le32 resource_address; 335 __u8 device_id[PMCRAID_DEVICE_ID_LEN]; 336 __u8 lun[PMCRAID_LUN_LEN]; 337 } __attribute__((packed, aligned(4))); 338 339 /* resource types (config_table_entry.resource_type values) */ 340 #define RES_TYPE_AF_DASD 0x00 341 #define RES_TYPE_GSCSI 0x01 342 #define RES_TYPE_VSET 0x02 343 #define RES_TYPE_IOA_FP 0xFF 344 345 #define RES_IS_IOA(res) ((res).resource_type == RES_TYPE_IOA_FP) 346 #define RES_IS_GSCSI(res) ((res).resource_type == RES_TYPE_GSCSI) 347 #define RES_IS_VSET(res) ((res).resource_type == RES_TYPE_VSET) 348 #define RES_IS_AFDASD(res) ((res).resource_type == RES_TYPE_AF_DASD) 349 350 /* bus_protocol values used by driver */ 351 #define RES_TYPE_VENCLOSURE 0x8 352 353 /* config_table_entry.common_flags0 */ 354 #define MULTIPATH_RESOURCE PMC_BIT32(0) 355 356 /* unique_flags1 */ 357 #define IMPORT_MODE_MANUAL PMC_BIT8(0) 358 359 /* well known resource handle values */ 360 #define RES_HANDLE_IOA 0xFFFFFFFF 361 #define RES_HANDLE_NONE 0x00000000 362 363 /* well known resource address values */ 364 #define RES_ADDRESS_IOAFP 0xFEFFFFFF 365 #define RES_ADDRESS_INVALID 0xFFFFFFFF 366 367 /* BUS/TARGET/LUN values from resource_addrr */ 368 #define RES_BUS(res_addr) (le32_to_cpu(res_addr) & 0xFF) 369 #define RES_TARGET(res_addr) ((le32_to_cpu(res_addr) >> 16) & 0xFF) 370 #define RES_LUN(res_addr) 0x0 371 372 /* configuration table structure */ 373 struct pmcraid_config_table { 374 __le16 num_entries; 375 __u8 table_format; 376 __u8 reserved1; 377 __u8 flags; 378 __u8 reserved2[11]; 379 struct pmcraid_config_table_entry entries[PMCRAID_MAX_RESOURCES]; 380 } __attribute__((packed, aligned(4))); 381 382 /* config_table.flags value */ 383 #define MICROCODE_UPDATE_REQUIRED PMC_BIT32(0) 384 385 /* 386 * HCAM format 387 */ 388 #define PMCRAID_HOSTRCB_LDNSIZE 4056 389 390 /* Error log notification format */ 391 struct pmcraid_hostrcb_error { 392 __le32 fd_ioasc; 393 __le32 fd_ra; 394 __le32 fd_rh; 395 __le32 prc; 396 union { 397 __u8 data[PMCRAID_HOSTRCB_LDNSIZE]; 398 } u; 399 } __attribute__ ((packed, aligned(4))); 400 401 struct pmcraid_hcam_hdr { 402 __u8 op_code; 403 __u8 notification_type; 404 __u8 notification_lost; 405 __u8 flags; 406 __u8 overlay_id; 407 __u8 reserved1[3]; 408 __le32 ilid; 409 __le32 timestamp1; 410 __le32 timestamp2; 411 __le32 data_len; 412 } __attribute__((packed, aligned(4))); 413 414 #define PMCRAID_AEN_GROUP 0x3 415 416 struct pmcraid_hcam_ccn { 417 struct pmcraid_hcam_hdr header; 418 struct pmcraid_config_table_entry cfg_entry; 419 } __attribute__((packed, aligned(4))); 420 421 struct pmcraid_hcam_ldn { 422 struct pmcraid_hcam_hdr header; 423 struct pmcraid_hostrcb_error error_log; 424 } __attribute__((packed, aligned(4))); 425 426 /* pmcraid_hcam.op_code values */ 427 #define HOSTRCB_TYPE_CCN 0xE1 428 #define HOSTRCB_TYPE_LDN 0xE2 429 430 /* pmcraid_hcam.notification_type values */ 431 #define NOTIFICATION_TYPE_ENTRY_CHANGED 0x0 432 #define NOTIFICATION_TYPE_ENTRY_NEW 0x1 433 #define NOTIFICATION_TYPE_ENTRY_DELETED 0x2 434 #define NOTIFICATION_TYPE_ERROR_LOG 0x10 435 #define NOTIFICATION_TYPE_INFORMATION_LOG 0x11 436 437 #define HOSTRCB_NOTIFICATIONS_LOST PMC_BIT8(0) 438 439 /* pmcraid_hcam.flags values */ 440 #define HOSTRCB_INTERNAL_OP_ERROR PMC_BIT8(0) 441 #define HOSTRCB_ERROR_RESPONSE_SENT PMC_BIT8(1) 442 443 /* pmcraid_hcam.overlay_id values */ 444 #define HOSTRCB_OVERLAY_ID_08 0x08 445 #define HOSTRCB_OVERLAY_ID_09 0x09 446 #define HOSTRCB_OVERLAY_ID_11 0x11 447 #define HOSTRCB_OVERLAY_ID_12 0x12 448 #define HOSTRCB_OVERLAY_ID_13 0x13 449 #define HOSTRCB_OVERLAY_ID_14 0x14 450 #define HOSTRCB_OVERLAY_ID_16 0x16 451 #define HOSTRCB_OVERLAY_ID_17 0x17 452 #define HOSTRCB_OVERLAY_ID_20 0x20 453 #define HOSTRCB_OVERLAY_ID_FF 0xFF 454 455 /* Implementation specific card details */ 456 struct pmcraid_chip_details { 457 /* hardware register offsets */ 458 unsigned long ioastatus; 459 unsigned long ioarrin; 460 unsigned long mailbox; 461 unsigned long global_intr_mask; 462 unsigned long ioa_host_intr; 463 unsigned long ioa_host_intr_clr; 464 unsigned long ioa_host_mask; 465 unsigned long ioa_host_mask_clr; 466 unsigned long host_ioa_intr; 467 unsigned long host_ioa_intr_clr; 468 469 /* timeout used during transitional to operational state */ 470 unsigned long transop_timeout; 471 }; 472 473 /* IOA to HOST doorbells (interrupts) */ 474 #define INTRS_TRANSITION_TO_OPERATIONAL PMC_BIT32(0) 475 #define INTRS_IOARCB_TRANSFER_FAILED PMC_BIT32(3) 476 #define INTRS_IOA_UNIT_CHECK PMC_BIT32(4) 477 #define INTRS_NO_HRRQ_FOR_CMD_RESPONSE PMC_BIT32(5) 478 #define INTRS_CRITICAL_OP_IN_PROGRESS PMC_BIT32(6) 479 #define INTRS_IO_DEBUG_ACK PMC_BIT32(7) 480 #define INTRS_IOARRIN_LOST PMC_BIT32(27) 481 #define INTRS_SYSTEM_BUS_MMIO_ERROR PMC_BIT32(28) 482 #define INTRS_IOA_PROCESSOR_ERROR PMC_BIT32(29) 483 #define INTRS_HRRQ_VALID PMC_BIT32(30) 484 #define INTRS_OPERATIONAL_STATUS PMC_BIT32(0) 485 486 /* Host to IOA Doorbells */ 487 #define DOORBELL_RUNTIME_RESET PMC_BIT32(1) 488 #define DOORBELL_IOA_RESET_ALERT PMC_BIT32(7) 489 #define DOORBELL_IOA_DEBUG_ALERT PMC_BIT32(9) 490 #define DOORBELL_ENABLE_DESTRUCTIVE_DIAGS PMC_BIT32(8) 491 #define DOORBELL_IOA_START_BIST PMC_BIT32(23) 492 #define DOORBELL_RESET_IOA PMC_BIT32(31) 493 494 /* Global interrupt mask register value */ 495 #define GLOBAL_INTERRUPT_MASK 0x4ULL 496 497 #define PMCRAID_ERROR_INTERRUPTS (INTRS_IOARCB_TRANSFER_FAILED | \ 498 INTRS_IOA_UNIT_CHECK | \ 499 INTRS_NO_HRRQ_FOR_CMD_RESPONSE | \ 500 INTRS_IOARRIN_LOST | \ 501 INTRS_SYSTEM_BUS_MMIO_ERROR | \ 502 INTRS_IOA_PROCESSOR_ERROR) 503 504 #define PMCRAID_PCI_INTERRUPTS (PMCRAID_ERROR_INTERRUPTS | \ 505 INTRS_HRRQ_VALID | \ 506 INTRS_CRITICAL_OP_IN_PROGRESS |\ 507 INTRS_TRANSITION_TO_OPERATIONAL) 508 509 /* control_block, associated with each of the commands contains IOARCB, IOADLs 510 * memory for IOASA. Additional 3 * 16 bytes are allocated in order to support 511 * additional request parameters (of max size 48) any command. 512 */ 513 struct pmcraid_control_block { 514 struct pmcraid_ioarcb ioarcb; 515 struct pmcraid_ioadl_desc ioadl[PMCRAID_IOADLS_EXTERNAL + 3]; 516 struct pmcraid_ioasa ioasa; 517 } __attribute__ ((packed, aligned(PMCRAID_IOARCB_ALIGNMENT))); 518 519 /* pmcraid_sglist - Scatter-gather list allocated for passthrough ioctls 520 */ 521 struct pmcraid_sglist { 522 u32 order; 523 u32 num_sg; 524 u32 num_dma_sg; 525 u32 buffer_len; 526 struct scatterlist scatterlist[1]; 527 }; 528 529 /* pmcraid_cmd - LLD representation of SCSI command */ 530 struct pmcraid_cmd { 531 532 /* Ptr and bus address of DMA.able control block for this command */ 533 struct pmcraid_control_block *ioa_cb; 534 dma_addr_t ioa_cb_bus_addr; 535 536 /* sense buffer for REQUEST SENSE command if firmware is not sending 537 * auto sense data 538 */ 539 dma_addr_t sense_buffer_dma; 540 dma_addr_t dma_handle; 541 u8 *sense_buffer; 542 543 /* pointer to mid layer structure of SCSI commands */ 544 struct scsi_cmnd *scsi_cmd; 545 546 struct list_head free_list; 547 struct completion wait_for_completion; 548 struct timer_list timer; /* needed for internal commands */ 549 u32 timeout; /* current timeout value */ 550 u32 index; /* index into the command list */ 551 u8 completion_req; /* for handling internal commands */ 552 u8 release; /* for handling completions */ 553 554 void (*cmd_done) (struct pmcraid_cmd *); 555 struct pmcraid_instance *drv_inst; 556 557 struct pmcraid_sglist *sglist; /* used for passthrough IOCTLs */ 558 559 /* scratch used during reset sequence */ 560 union { 561 unsigned long time_left; 562 struct pmcraid_resource_entry *res; 563 } u; 564 }; 565 566 /* 567 * Interrupt registers of IOA 568 */ 569 struct pmcraid_interrupts { 570 void __iomem *ioa_host_interrupt_reg; 571 void __iomem *ioa_host_interrupt_clr_reg; 572 void __iomem *ioa_host_interrupt_mask_reg; 573 void __iomem *ioa_host_interrupt_mask_clr_reg; 574 void __iomem *global_interrupt_mask_reg; 575 void __iomem *host_ioa_interrupt_reg; 576 void __iomem *host_ioa_interrupt_clr_reg; 577 }; 578 579 /* ISR parameters LLD allocates (one for each MSI-X if enabled) vectors */ 580 struct pmcraid_isr_param { 581 u8 hrrq_id; /* hrrq entry index */ 582 u16 vector; /* allocated msi-x vector */ 583 struct pmcraid_instance *drv_inst; 584 }; 585 586 /* AEN message header sent as part of event data to applications */ 587 struct pmcraid_aen_msg { 588 u32 hostno; 589 u32 length; 590 u8 reserved[8]; 591 u8 data[0]; 592 }; 593 594 struct pmcraid_hostrcb { 595 struct pmcraid_instance *drv_inst; 596 struct pmcraid_aen_msg *msg; 597 struct pmcraid_hcam_hdr *hcam; /* pointer to hcam buffer */ 598 struct pmcraid_cmd *cmd; /* pointer to command block used */ 599 dma_addr_t baddr; /* system address of hcam buffer */ 600 atomic_t ignore; /* process HCAM response ? */ 601 }; 602 603 #define PMCRAID_AEN_HDR_SIZE sizeof(struct pmcraid_aen_msg) 604 605 606 607 /* 608 * Per adapter structure maintained by LLD 609 */ 610 struct pmcraid_instance { 611 /* Array of allowed-to-be-exposed resources, initialized from 612 * Configutation Table, later updated with CCNs 613 */ 614 struct pmcraid_resource_entry *res_entries; 615 616 struct list_head free_res_q; /* res_entries lists for easy lookup */ 617 struct list_head used_res_q; /* List of to be exposed resources */ 618 spinlock_t resource_lock; /* spinlock to protect resource list */ 619 620 void __iomem *mapped_dma_addr; 621 void __iomem *ioa_status; /* Iomapped IOA status register */ 622 void __iomem *mailbox; /* Iomapped mailbox register */ 623 void __iomem *ioarrin; /* IOmapped IOARR IN register */ 624 625 struct pmcraid_interrupts int_regs; 626 struct pmcraid_chip_details *chip_cfg; 627 628 /* HostRCBs needed for HCAM */ 629 struct pmcraid_hostrcb ldn; 630 struct pmcraid_hostrcb ccn; 631 632 633 /* Bus address of start of HRRQ */ 634 dma_addr_t hrrq_start_bus_addr[PMCRAID_NUM_MSIX_VECTORS]; 635 636 /* Pointer to 1st entry of HRRQ */ 637 __be32 *hrrq_start[PMCRAID_NUM_MSIX_VECTORS]; 638 639 /* Pointer to last entry of HRRQ */ 640 __be32 *hrrq_end[PMCRAID_NUM_MSIX_VECTORS]; 641 642 /* Pointer to current pointer of hrrq */ 643 __be32 *hrrq_curr[PMCRAID_NUM_MSIX_VECTORS]; 644 645 /* Lock for HRRQ access */ 646 spinlock_t hrrq_lock[PMCRAID_NUM_MSIX_VECTORS]; 647 648 /* Expected toggle bit at host */ 649 u8 host_toggle_bit[PMCRAID_NUM_MSIX_VECTORS]; 650 651 /* No of Reset IOA retries . IOA marked dead if threshold exceeds */ 652 u8 ioa_reset_attempts; 653 #define PMCRAID_RESET_ATTEMPTS 3 654 655 /* Wait Q for threads to wait for Reset IOA completion */ 656 wait_queue_head_t reset_wait_q; 657 struct pmcraid_cmd *reset_cmd; 658 659 /* structures for supporting SIGIO based AEN. */ 660 struct fasync_struct *aen_queue; 661 struct mutex aen_queue_lock; /* lock for aen subscribers list */ 662 struct cdev cdev; 663 664 struct Scsi_Host *host; /* mid layer interface structure handle */ 665 struct pci_dev *pdev; /* PCI device structure handle */ 666 667 u8 current_log_level; /* default level for logging IOASC errors */ 668 669 u8 num_hrrq; /* Number of interrupt vectors allocated */ 670 dev_t dev; /* Major-Minor numbers for Char device */ 671 672 /* Used as ISR handler argument */ 673 struct pmcraid_isr_param hrrq_vector[PMCRAID_NUM_MSIX_VECTORS]; 674 675 /* configuration table */ 676 struct pmcraid_config_table *cfg_table; 677 dma_addr_t cfg_table_bus_addr; 678 679 /* structures related to command blocks */ 680 struct kmem_cache *cmd_cachep; /* cache for cmd blocks */ 681 struct pci_pool *control_pool; /* pool for control blocks */ 682 char cmd_pool_name[64]; /* name of cmd cache */ 683 char ctl_pool_name[64]; /* name of control cache */ 684 685 struct pmcraid_cmd *cmd_list[PMCRAID_MAX_CMD]; 686 687 struct list_head free_cmd_pool; 688 struct list_head pending_cmd_pool; 689 spinlock_t free_pool_lock; /* free pool lock */ 690 spinlock_t pending_pool_lock; /* pending pool lock */ 691 692 /* No of IO commands pending with FW */ 693 atomic_t outstanding_cmds; 694 695 /* should add/delete resources to mid-layer now ?*/ 696 atomic_t expose_resources; 697 698 /* Tasklet to handle deferred processing */ 699 struct tasklet_struct isr_tasklet[PMCRAID_NUM_MSIX_VECTORS]; 700 701 /* Work-queue (Shared) for deferred reset processing */ 702 struct work_struct worker_q; 703 704 705 u32 ioa_state:4; /* For IOA Reset sequence FSM */ 706 #define IOA_STATE_OPERATIONAL 0x0 707 #define IOA_STATE_UNKNOWN 0x1 708 #define IOA_STATE_DEAD 0x2 709 #define IOA_STATE_IN_SOFT_RESET 0x3 710 #define IOA_STATE_IN_HARD_RESET 0x4 711 #define IOA_STATE_IN_RESET_ALERT 0x5 712 #define IOA_STATE_IN_BRINGDOWN 0x6 713 #define IOA_STATE_IN_BRINGUP 0x7 714 715 u32 ioa_reset_in_progress:1; /* true if IOA reset is in progress */ 716 u32 ioa_hard_reset:1; /* TRUE if Hard Reset is needed */ 717 u32 ioa_unit_check:1; /* Indicates Unit Check condition */ 718 u32 ioa_bringdown:1; /* whether IOA needs to be brought down */ 719 u32 force_ioa_reset:1; /* force adapter reset ? */ 720 u32 reinit_cfg_table:1; /* reinit config table due to lost CCN */ 721 u32 ioa_shutdown_type:2;/* shutdown type used during reset */ 722 #define SHUTDOWN_NONE 0x0 723 #define SHUTDOWN_NORMAL 0x1 724 #define SHUTDOWN_ABBREV 0x2 725 726 }; 727 728 /* LLD maintained resource entry structure */ 729 struct pmcraid_resource_entry { 730 struct list_head queue; /* link to "to be exposed" resources */ 731 struct pmcraid_config_table_entry cfg_entry; 732 struct scsi_device *scsi_dev; /* Link scsi_device structure */ 733 atomic_t read_failures; /* count of failed READ commands */ 734 atomic_t write_failures; /* count of failed WRITE commands */ 735 736 /* To indicate add/delete/modify during CCN */ 737 u8 change_detected; 738 #define RES_CHANGE_ADD 0x1 /* add this to mid-layer */ 739 #define RES_CHANGE_DEL 0x2 /* remove this from mid-layer */ 740 741 u8 reset_progress; /* Device is resetting */ 742 743 /* 744 * When IOA asks for sync (i.e. IOASC = Not Ready, Sync Required), this 745 * flag will be set, mid layer will be asked to retry. In the next 746 * attempt, this flag will be checked in queuecommand() to set 747 * SYNC_COMPLETE flag in IOARCB (flag_0). 748 */ 749 u8 sync_reqd; 750 751 /* target indicates the mapped target_id assigned to this resource if 752 * this is VSET resource. For non-VSET resources this will be un-used 753 * or zero 754 */ 755 u8 target; 756 }; 757 758 /* Data structures used in IOASC error code logging */ 759 struct pmcraid_ioasc_error { 760 u32 ioasc_code; /* IOASC code */ 761 u8 log_level; /* default log level assignment. */ 762 char *error_string; 763 }; 764 765 /* Initial log_level assignments for various IOASCs */ 766 #define IOASC_LOG_LEVEL_NONE 0x0 /* no logging */ 767 #define IOASC_LOG_LEVEL_MUST 0x1 /* must log: all high-severity errors */ 768 #define IOASC_LOG_LEVEL_HARD 0x2 /* optional – low severity errors */ 769 770 /* Error information maintained by LLD. LLD initializes the pmcraid_error_table 771 * statically. 772 */ 773 static struct pmcraid_ioasc_error pmcraid_ioasc_error_table[] = { 774 {0x01180600, IOASC_LOG_LEVEL_MUST, 775 "Recovered Error, soft media error, sector reassignment suggested"}, 776 {0x015D0000, IOASC_LOG_LEVEL_MUST, 777 "Recovered Error, failure prediction threshold exceeded"}, 778 {0x015D9200, IOASC_LOG_LEVEL_MUST, 779 "Recovered Error, soft Cache Card Battery error threshold"}, 780 {0x015D9200, IOASC_LOG_LEVEL_MUST, 781 "Recovered Error, soft Cache Card Battery error threshold"}, 782 {0x02048000, IOASC_LOG_LEVEL_MUST, 783 "Not Ready, IOA Reset Required"}, 784 {0x02408500, IOASC_LOG_LEVEL_MUST, 785 "Not Ready, IOA microcode download required"}, 786 {0x03110B00, IOASC_LOG_LEVEL_MUST, 787 "Medium Error, data unreadable, reassignment suggested"}, 788 {0x03110C00, IOASC_LOG_LEVEL_MUST, 789 "Medium Error, data unreadable do not reassign"}, 790 {0x03310000, IOASC_LOG_LEVEL_MUST, 791 "Medium Error, media corrupted"}, 792 {0x04050000, IOASC_LOG_LEVEL_MUST, 793 "Hardware Error, IOA can't communicate with device"}, 794 {0x04080000, IOASC_LOG_LEVEL_MUST, 795 "Hardware Error, device bus error"}, 796 {0x04080000, IOASC_LOG_LEVEL_MUST, 797 "Hardware Error, device bus is not functioning"}, 798 {0x04118000, IOASC_LOG_LEVEL_MUST, 799 "Hardware Error, IOA reserved area data check"}, 800 {0x04118100, IOASC_LOG_LEVEL_MUST, 801 "Hardware Error, IOA reserved area invalid data pattern"}, 802 {0x04118200, IOASC_LOG_LEVEL_MUST, 803 "Hardware Error, IOA reserved area LRC error"}, 804 {0x04320000, IOASC_LOG_LEVEL_MUST, 805 "Hardware Error, reassignment space exhausted"}, 806 {0x04330000, IOASC_LOG_LEVEL_MUST, 807 "Hardware Error, data transfer underlength error"}, 808 {0x04330000, IOASC_LOG_LEVEL_MUST, 809 "Hardware Error, data transfer overlength error"}, 810 {0x04418000, IOASC_LOG_LEVEL_MUST, 811 "Hardware Error, PCI bus error"}, 812 {0x04440000, IOASC_LOG_LEVEL_MUST, 813 "Hardware Error, device error"}, 814 {0x04448300, IOASC_LOG_LEVEL_MUST, 815 "Hardware Error, undefined device response"}, 816 {0x04448400, IOASC_LOG_LEVEL_MUST, 817 "Hardware Error, IOA microcode error"}, 818 {0x04448600, IOASC_LOG_LEVEL_MUST, 819 "Hardware Error, IOA reset required"}, 820 {0x04449200, IOASC_LOG_LEVEL_MUST, 821 "Hardware Error, hard Cache Fearuee Card Battery error"}, 822 {0x0444A000, IOASC_LOG_LEVEL_MUST, 823 "Hardware Error, failed device altered"}, 824 {0x0444A200, IOASC_LOG_LEVEL_MUST, 825 "Hardware Error, data check after reassignment"}, 826 {0x0444A300, IOASC_LOG_LEVEL_MUST, 827 "Hardware Error, LRC error after reassignment"}, 828 {0x044A0000, IOASC_LOG_LEVEL_MUST, 829 "Hardware Error, device bus error (msg/cmd phase)"}, 830 {0x04670400, IOASC_LOG_LEVEL_MUST, 831 "Hardware Error, new device can't be used"}, 832 {0x04678000, IOASC_LOG_LEVEL_MUST, 833 "Hardware Error, invalid multiadapter configuration"}, 834 {0x04678100, IOASC_LOG_LEVEL_MUST, 835 "Hardware Error, incorrect connection between enclosures"}, 836 {0x04678200, IOASC_LOG_LEVEL_MUST, 837 "Hardware Error, connections exceed IOA design limits"}, 838 {0x04678300, IOASC_LOG_LEVEL_MUST, 839 "Hardware Error, incorrect multipath connection"}, 840 {0x04679000, IOASC_LOG_LEVEL_MUST, 841 "Hardware Error, command to LUN failed"}, 842 {0x064C8000, IOASC_LOG_LEVEL_HARD, 843 "Unit Attention, cache exists for missing/failed device"}, 844 {0x06670100, IOASC_LOG_LEVEL_HARD, 845 "Unit Attention, incompatible exposed mode device"}, 846 {0x06670600, IOASC_LOG_LEVEL_HARD, 847 "Unit Attention, attachment of logical unit failed"}, 848 {0x06678000, IOASC_LOG_LEVEL_MUST, 849 "Unit Attention, cables exceed connective design limit"}, 850 {0x06678300, IOASC_LOG_LEVEL_MUST, 851 "Unit Attention, incomplete multipath connection between" \ 852 "IOA and enclosure"}, 853 {0x06678400, IOASC_LOG_LEVEL_MUST, 854 "Unit Attention, incomplete multipath connection between" \ 855 "device and enclosure"}, 856 {0x06678500, IOASC_LOG_LEVEL_MUST, 857 "Unit Attention, incomplete multipath connection between" \ 858 "IOA and remote IOA"}, 859 {0x06678600, IOASC_LOG_LEVEL_HARD, 860 "Unit Attention, missing remote IOA"}, 861 {0x06679100, IOASC_LOG_LEVEL_HARD, 862 "Unit Attention, enclosure doesn't support required multipath" \ 863 "function"}, 864 {0x06698200, IOASC_LOG_LEVEL_HARD, 865 "Unit Attention, corrupt array parity detected on device"}, 866 {0x066B0200, IOASC_LOG_LEVEL_MUST, 867 "Unit Attention, array exposed"}, 868 {0x066B8200, IOASC_LOG_LEVEL_HARD, 869 "Unit Attention, exposed array is still protected"}, 870 {0x066B9200, IOASC_LOG_LEVEL_MUST, 871 "Unit Attention, Multipath redundancy level got worse"}, 872 {0x07270000, IOASC_LOG_LEVEL_HARD, 873 "Data Protect, device is read/write protected by IOA"}, 874 {0x07278000, IOASC_LOG_LEVEL_HARD, 875 "Data Protect, IOA doesn't support device attribute"}, 876 {0x07278100, IOASC_LOG_LEVEL_HARD, 877 "Data Protect, NVRAM mirroring prohibited"}, 878 {0x07278400, IOASC_LOG_LEVEL_MUST, 879 "Data Protect, array is short 2 or more devices"}, 880 {0x07278600, IOASC_LOG_LEVEL_MUST, 881 "Data Protect, exposed array is short a required device"}, 882 {0x07278700, IOASC_LOG_LEVEL_MUST, 883 "Data Protect, array members not at required addresses"}, 884 {0x07278800, IOASC_LOG_LEVEL_MUST, 885 "Data Protect, exposed mode device resource address conflict"}, 886 {0x07278900, IOASC_LOG_LEVEL_MUST, 887 "Data Protect, incorrect resource address of exposed mode device"}, 888 {0x07278A00, IOASC_LOG_LEVEL_MUST, 889 "Data Protect, Array is missing a device and parity is out of sync"}, 890 {0x07278B00, IOASC_LOG_LEVEL_MUST, 891 "Data Protect, maximum number of arrays already exist"}, 892 {0x07278C00, IOASC_LOG_LEVEL_HARD, 893 "Data Protect, cannot locate cache data for device"}, 894 {0x07278D00, IOASC_LOG_LEVEL_HARD, 895 "Data Protect, cache data exits for a changed device"}, 896 {0x07279100, IOASC_LOG_LEVEL_MUST, 897 "Data Protect, detection of a device requiring format"}, 898 {0x07279200, IOASC_LOG_LEVEL_MUST, 899 "Data Protect, IOA exceeds maximum number of devices"}, 900 {0x07279600, IOASC_LOG_LEVEL_MUST, 901 "Data Protect, missing array, volume set is not functional"}, 902 {0x07279700, IOASC_LOG_LEVEL_MUST, 903 "Data Protect, single device for a volume set"}, 904 {0x07279800, IOASC_LOG_LEVEL_MUST, 905 "Data Protect, missing multiple devices for a volume set"}, 906 {0x07279900, IOASC_LOG_LEVEL_HARD, 907 "Data Protect, maximum number of volument sets already exists"}, 908 {0x07279A00, IOASC_LOG_LEVEL_MUST, 909 "Data Protect, other volume set problem"}, 910 }; 911 912 /* macros to help in debugging */ 913 #define pmcraid_err(...) \ 914 printk(KERN_ERR "MaxRAID: "__VA_ARGS__) 915 916 #define pmcraid_info(...) \ 917 if (pmcraid_debug_log) \ 918 printk(KERN_INFO "MaxRAID: "__VA_ARGS__) 919 920 /* check if given command is a SCSI READ or SCSI WRITE command */ 921 #define SCSI_READ_CMD 0x1 /* any of SCSI READ commands */ 922 #define SCSI_WRITE_CMD 0x2 /* any of SCSI WRITE commands */ 923 #define SCSI_CMD_TYPE(opcode) \ 924 ({ u8 op = opcode; u8 __type = 0;\ 925 if (op == READ_6 || op == READ_10 || op == READ_12 || op == READ_16)\ 926 __type = SCSI_READ_CMD;\ 927 else if (op == WRITE_6 || op == WRITE_10 || op == WRITE_12 || \ 928 op == WRITE_16)\ 929 __type = SCSI_WRITE_CMD;\ 930 __type;\ 931 }) 932 933 #define IS_SCSI_READ_WRITE(opcode) \ 934 ({ u8 __type = SCSI_CMD_TYPE(opcode); \ 935 (__type == SCSI_READ_CMD || __type == SCSI_WRITE_CMD) ? 1 : 0;\ 936 }) 937 938 939 /* 940 * pmcraid_ioctl_header - definition of header structure that preceeds all the 941 * buffers given as ioctl arguments. 942 * 943 * .signature : always ASCII string, "PMCRAID" 944 * .reserved : not used 945 * .buffer_length : length of the buffer following the header 946 */ 947 struct pmcraid_ioctl_header { 948 u8 signature[8]; 949 u32 reserved; 950 u32 buffer_length; 951 }; 952 953 #define PMCRAID_IOCTL_SIGNATURE "PMCRAID" 954 955 956 /* 957 * pmcraid_event_details - defines AEN details that apps can retrieve from LLD 958 * 959 * .rcb_ccn - complete RCB of CCN 960 * .rcb_ldn - complete RCB of CCN 961 */ 962 struct pmcraid_event_details { 963 struct pmcraid_hcam_ccn rcb_ccn; 964 struct pmcraid_hcam_ldn rcb_ldn; 965 }; 966 967 /* 968 * pmcraid_driver_ioctl_buffer - structure passed as argument to most of the 969 * PMC driver handled ioctls. 970 */ 971 struct pmcraid_driver_ioctl_buffer { 972 struct pmcraid_ioctl_header ioctl_header; 973 struct pmcraid_event_details event_details; 974 }; 975 976 /* 977 * pmcraid_passthrough_ioctl_buffer - structure given as argument to 978 * passthrough(or firmware handled) IOCTL commands. Note that ioarcb requires 979 * 32-byte alignment so, it is necessary to pack this structure to avoid any 980 * holes between ioctl_header and passthrough buffer 981 * 982 * .ioactl_header : ioctl header 983 * .ioarcb : filled-up ioarcb buffer, driver always reads this buffer 984 * .ioasa : buffer for ioasa, driver fills this with IOASA from firmware 985 * .request_buffer: The I/O buffer (flat), driver reads/writes to this based on 986 * the transfer directions passed in ioarcb.flags0. Contents 987 * of this buffer are valid only when ioarcb.data_transfer_len 988 * is not zero. 989 */ 990 struct pmcraid_passthrough_ioctl_buffer { 991 struct pmcraid_ioctl_header ioctl_header; 992 struct pmcraid_ioarcb ioarcb; 993 struct pmcraid_ioasa ioasa; 994 u8 request_buffer[1]; 995 } __attribute__ ((packed)); 996 997 /* 998 * keys to differentiate between driver handled IOCTLs and passthrough 999 * IOCTLs passed to IOA. driver determines the ioctl type using macro 1000 * _IOC_TYPE 1001 */ 1002 #define PMCRAID_DRIVER_IOCTL 'D' 1003 #define PMCRAID_PASSTHROUGH_IOCTL 'F' 1004 1005 #define DRV_IOCTL(n, size) \ 1006 _IOC(_IOC_READ|_IOC_WRITE, PMCRAID_DRIVER_IOCTL, (n), (size)) 1007 1008 #define FMW_IOCTL(n, size) \ 1009 _IOC(_IOC_READ|_IOC_WRITE, PMCRAID_PASSTHROUGH_IOCTL, (n), (size)) 1010 1011 /* 1012 * _ARGSIZE: macro that gives size of the argument type passed to an IOCTL cmd. 1013 * This is to facilitate applications avoiding un-necessary memory allocations. 1014 * For example, most of driver handled ioctls do not require ioarcb, ioasa. 1015 */ 1016 #define _ARGSIZE(arg) (sizeof(struct pmcraid_ioctl_header) + sizeof(arg)) 1017 1018 /* Driver handled IOCTL command definitions */ 1019 1020 #define PMCRAID_IOCTL_RESET_ADAPTER \ 1021 DRV_IOCTL(5, sizeof(struct pmcraid_ioctl_header)) 1022 1023 /* passthrough/firmware handled commands */ 1024 #define PMCRAID_IOCTL_PASSTHROUGH_COMMAND \ 1025 FMW_IOCTL(1, sizeof(struct pmcraid_passthrough_ioctl_buffer)) 1026 1027 #define PMCRAID_IOCTL_DOWNLOAD_MICROCODE \ 1028 FMW_IOCTL(2, sizeof(struct pmcraid_passthrough_ioctl_buffer)) 1029 1030 1031 #endif /* _PMCRAID_H */ 1032