1 /* 2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 PMC-Sierra, Inc., 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm80xx_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 #define SMP_DIRECT 1 47 #define SMP_INDIRECT 2 48 49 50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value) 51 { 52 u32 reg_val; 53 unsigned long start; 54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); 55 /* confirm the setting is written */ 56 start = jiffies + HZ; /* 1 sec */ 57 do { 58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); 59 } while ((reg_val != shift_value) && time_before(jiffies, start)); 60 if (reg_val != shift_value) { 61 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n", 62 reg_val); 63 return -1; 64 } 65 return 0; 66 } 67 68 static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset, 69 const void *destination, 70 u32 dw_count, u32 bus_base_number) 71 { 72 u32 index, value, offset; 73 u32 *destination1; 74 destination1 = (u32 *)destination; 75 76 for (index = 0; index < dw_count; index += 4, destination1++) { 77 offset = (soffset + index); 78 if (offset < (64 * 1024)) { 79 value = pm8001_cr32(pm8001_ha, bus_base_number, offset); 80 *destination1 = cpu_to_le32(value); 81 } 82 } 83 return; 84 } 85 86 ssize_t pm80xx_get_fatal_dump(struct device *cdev, 87 struct device_attribute *attr, char *buf) 88 { 89 struct Scsi_Host *shost = class_to_shost(cdev); 90 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 91 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 92 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; 93 u32 accum_len , reg_val, index, *temp; 94 u32 status = 1; 95 unsigned long start; 96 u8 *direct_data; 97 char *fatal_error_data = buf; 98 u32 length_to_read; 99 u32 offset; 100 101 pm8001_ha->forensic_info.data_buf.direct_data = buf; 102 if (pm8001_ha->chip_id == chip_8001) { 103 pm8001_ha->forensic_info.data_buf.direct_data += 104 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 105 "Not supported for SPC controller"); 106 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 107 (char *)buf; 108 } 109 /* initialize variables for very first call from host application */ 110 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 111 pm8001_dbg(pm8001_ha, IO, 112 "forensic_info TYPE_NON_FATAL..............\n"); 113 direct_data = (u8 *)fatal_error_data; 114 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; 115 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; 116 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 117 pm8001_ha->forensic_info.data_buf.read_len = 0; 118 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 119 120 /* Write signature to fatal dump table */ 121 pm8001_mw32(fatal_table_address, 122 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd); 123 124 pm8001_ha->forensic_info.data_buf.direct_data = direct_data; 125 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status); 126 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n", 127 pm8001_ha->forensic_info.data_buf.read_len); 128 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n", 129 pm8001_ha->forensic_info.data_buf.direct_len); 130 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n", 131 pm8001_ha->forensic_info.data_buf.direct_offset); 132 } 133 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 134 /* start to get data */ 135 /* Program the MEMBASE II Shifting Register with 0x00.*/ 136 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 137 pm8001_ha->fatal_forensic_shift_offset); 138 pm8001_ha->forensic_last_offset = 0; 139 pm8001_ha->forensic_fatal_step = 0; 140 pm8001_ha->fatal_bar_loc = 0; 141 } 142 143 /* Read until accum_len is retrived */ 144 accum_len = pm8001_mr32(fatal_table_address, 145 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 146 /* Determine length of data between previously stored transfer length 147 * and current accumulated transfer length 148 */ 149 length_to_read = 150 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer; 151 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n", 152 accum_len); 153 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n", 154 length_to_read); 155 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n", 156 pm8001_ha->forensic_last_offset); 157 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n", 158 pm8001_ha->forensic_info.data_buf.read_len); 159 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n", 160 pm8001_ha->forensic_info.data_buf.direct_len); 161 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n", 162 pm8001_ha->forensic_info.data_buf.direct_offset); 163 164 /* If accumulated length failed to read correctly fail the attempt.*/ 165 if (accum_len == 0xFFFFFFFF) { 166 pm8001_dbg(pm8001_ha, IO, 167 "Possible PCI issue 0x%x not expected\n", 168 accum_len); 169 return status; 170 } 171 /* If accumulated length is zero fail the attempt */ 172 if (accum_len == 0) { 173 pm8001_ha->forensic_info.data_buf.direct_data += 174 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 175 "%08x ", 0xFFFFFFFF); 176 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 177 (char *)buf; 178 } 179 /* Accumulated length is good so start capturing the first data */ 180 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 181 if (pm8001_ha->forensic_fatal_step == 0) { 182 moreData: 183 /* If data to read is less than SYSFS_OFFSET then reduce the 184 * length of dataLen 185 */ 186 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET 187 > length_to_read) { 188 pm8001_ha->forensic_info.data_buf.direct_len = 189 length_to_read - 190 pm8001_ha->forensic_last_offset; 191 } else { 192 pm8001_ha->forensic_info.data_buf.direct_len = 193 SYSFS_OFFSET; 194 } 195 if (pm8001_ha->forensic_info.data_buf.direct_data) { 196 /* Data is in bar, copy to host memory */ 197 pm80xx_pci_mem_copy(pm8001_ha, 198 pm8001_ha->fatal_bar_loc, 199 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, 200 pm8001_ha->forensic_info.data_buf.direct_len, 1); 201 } 202 pm8001_ha->fatal_bar_loc += 203 pm8001_ha->forensic_info.data_buf.direct_len; 204 pm8001_ha->forensic_info.data_buf.direct_offset += 205 pm8001_ha->forensic_info.data_buf.direct_len; 206 pm8001_ha->forensic_last_offset += 207 pm8001_ha->forensic_info.data_buf.direct_len; 208 pm8001_ha->forensic_info.data_buf.read_len = 209 pm8001_ha->forensic_info.data_buf.direct_len; 210 211 if (pm8001_ha->forensic_last_offset >= length_to_read) { 212 pm8001_ha->forensic_info.data_buf.direct_data += 213 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 214 "%08x ", 3); 215 for (index = 0; index < 216 (pm8001_ha->forensic_info.data_buf.direct_len 217 / 4); index++) { 218 pm8001_ha->forensic_info.data_buf.direct_data += 219 sprintf( 220 pm8001_ha->forensic_info.data_buf.direct_data, 221 "%08x ", *(temp + index)); 222 } 223 224 pm8001_ha->fatal_bar_loc = 0; 225 pm8001_ha->forensic_fatal_step = 1; 226 pm8001_ha->fatal_forensic_shift_offset = 0; 227 pm8001_ha->forensic_last_offset = 0; 228 status = 0; 229 offset = (int) 230 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 231 - (char *)buf); 232 pm8001_dbg(pm8001_ha, IO, 233 "get_fatal_spcv:return1 0x%x\n", offset); 234 return (char *)pm8001_ha-> 235 forensic_info.data_buf.direct_data - 236 (char *)buf; 237 } 238 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { 239 pm8001_ha->forensic_info.data_buf.direct_data += 240 sprintf(pm8001_ha-> 241 forensic_info.data_buf.direct_data, 242 "%08x ", 2); 243 for (index = 0; index < 244 (pm8001_ha->forensic_info.data_buf.direct_len 245 / 4); index++) { 246 pm8001_ha->forensic_info.data_buf.direct_data 247 += sprintf(pm8001_ha-> 248 forensic_info.data_buf.direct_data, 249 "%08x ", *(temp + index)); 250 } 251 status = 0; 252 offset = (int) 253 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 254 - (char *)buf); 255 pm8001_dbg(pm8001_ha, IO, 256 "get_fatal_spcv:return2 0x%x\n", offset); 257 return (char *)pm8001_ha-> 258 forensic_info.data_buf.direct_data - 259 (char *)buf; 260 } 261 262 /* Increment the MEMBASE II Shifting Register value by 0x100.*/ 263 pm8001_ha->forensic_info.data_buf.direct_data += 264 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 265 "%08x ", 2); 266 for (index = 0; index < 267 (pm8001_ha->forensic_info.data_buf.direct_len 268 / 4) ; index++) { 269 pm8001_ha->forensic_info.data_buf.direct_data += 270 sprintf(pm8001_ha-> 271 forensic_info.data_buf.direct_data, 272 "%08x ", *(temp + index)); 273 } 274 pm8001_ha->fatal_forensic_shift_offset += 0x100; 275 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 276 pm8001_ha->fatal_forensic_shift_offset); 277 pm8001_ha->fatal_bar_loc = 0; 278 status = 0; 279 offset = (int) 280 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 281 - (char *)buf); 282 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n", 283 offset); 284 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 285 (char *)buf; 286 } 287 if (pm8001_ha->forensic_fatal_step == 1) { 288 /* store previous accumulated length before triggering next 289 * accumulated length update 290 */ 291 pm8001_ha->forensic_preserved_accumulated_transfer = 292 pm8001_mr32(fatal_table_address, 293 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 294 295 /* continue capturing the fatal log until Dump status is 0x3 */ 296 if (pm8001_mr32(fatal_table_address, 297 MPI_FATAL_EDUMP_TABLE_STATUS) < 298 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) { 299 300 /* reset fddstat bit by writing to zero*/ 301 pm8001_mw32(fatal_table_address, 302 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0); 303 304 /* set dump control value to '1' so that new data will 305 * be transferred to shared memory 306 */ 307 pm8001_mw32(fatal_table_address, 308 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 309 MPI_FATAL_EDUMP_HANDSHAKE_RDY); 310 311 /*Poll FDDHSHK until clear */ 312 start = jiffies + (2 * HZ); /* 2 sec */ 313 314 do { 315 reg_val = pm8001_mr32(fatal_table_address, 316 MPI_FATAL_EDUMP_TABLE_HANDSHAKE); 317 } while ((reg_val) && time_before(jiffies, start)); 318 319 if (reg_val != 0) { 320 pm8001_dbg(pm8001_ha, FAIL, 321 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n", 322 reg_val); 323 /* Fail the dump if a timeout occurs */ 324 pm8001_ha->forensic_info.data_buf.direct_data += 325 sprintf( 326 pm8001_ha->forensic_info.data_buf.direct_data, 327 "%08x ", 0xFFFFFFFF); 328 return((char *) 329 pm8001_ha->forensic_info.data_buf.direct_data 330 - (char *)buf); 331 } 332 /* Poll status register until set to 2 or 333 * 3 for up to 2 seconds 334 */ 335 start = jiffies + (2 * HZ); /* 2 sec */ 336 337 do { 338 reg_val = pm8001_mr32(fatal_table_address, 339 MPI_FATAL_EDUMP_TABLE_STATUS); 340 } while (((reg_val != 2) && (reg_val != 3)) && 341 time_before(jiffies, start)); 342 343 if (reg_val < 2) { 344 pm8001_dbg(pm8001_ha, FAIL, 345 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n", 346 reg_val); 347 /* Fail the dump if a timeout occurs */ 348 pm8001_ha->forensic_info.data_buf.direct_data += 349 sprintf( 350 pm8001_ha->forensic_info.data_buf.direct_data, 351 "%08x ", 0xFFFFFFFF); 352 return((char *)pm8001_ha->forensic_info.data_buf.direct_data - 353 (char *)buf); 354 } 355 /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */ 356 pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */ 357 pm8001_cw32(pm8001_ha, 0, 358 MEMBASE_II_SHIFT_REGISTER, 359 pm8001_ha->fatal_forensic_shift_offset); 360 } 361 /* Read the next block of the debug data.*/ 362 length_to_read = pm8001_mr32(fatal_table_address, 363 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) - 364 pm8001_ha->forensic_preserved_accumulated_transfer; 365 if (length_to_read != 0x0) { 366 pm8001_ha->forensic_fatal_step = 0; 367 goto moreData; 368 } else { 369 pm8001_ha->forensic_info.data_buf.direct_data += 370 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 371 "%08x ", 4); 372 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF; 373 pm8001_ha->forensic_info.data_buf.direct_len = 0; 374 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 375 pm8001_ha->forensic_info.data_buf.read_len = 0; 376 } 377 } 378 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data 379 - (char *)buf); 380 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset); 381 return ((char *)pm8001_ha->forensic_info.data_buf.direct_data - 382 (char *)buf); 383 } 384 385 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma 386 * location by the firmware. 387 */ 388 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev, 389 struct device_attribute *attr, char *buf) 390 { 391 struct Scsi_Host *shost = class_to_shost(cdev); 392 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 393 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 394 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr; 395 u32 accum_len = 0; 396 u32 total_len = 0; 397 u32 reg_val = 0; 398 u32 *temp = NULL; 399 u32 index = 0; 400 u32 output_length; 401 unsigned long start = 0; 402 char *buf_copy = buf; 403 404 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 405 if (++pm8001_ha->non_fatal_count == 1) { 406 if (pm8001_ha->chip_id == chip_8001) { 407 snprintf(pm8001_ha->forensic_info.data_buf.direct_data, 408 PAGE_SIZE, "Not supported for SPC controller"); 409 return 0; 410 } 411 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n"); 412 /* 413 * Step 1: Write the host buffer parameters in the MPI Fatal and 414 * Non-Fatal Error Dump Capture Table.This is the buffer 415 * where debug data will be DMAed to. 416 */ 417 pm8001_mw32(nonfatal_table_address, 418 MPI_FATAL_EDUMP_TABLE_LO_OFFSET, 419 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo); 420 421 pm8001_mw32(nonfatal_table_address, 422 MPI_FATAL_EDUMP_TABLE_HI_OFFSET, 423 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi); 424 425 pm8001_mw32(nonfatal_table_address, 426 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET); 427 428 /* Optionally, set the DUMPCTRL bit to 1 if the host 429 * keeps sending active I/Os while capturing the non-fatal 430 * debug data. Otherwise, leave this bit set to zero 431 */ 432 pm8001_mw32(nonfatal_table_address, 433 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY); 434 435 /* 436 * Step 2: Clear Accumulative Length of Debug Data Transferred 437 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump 438 * Capture Table to zero. 439 */ 440 pm8001_mw32(nonfatal_table_address, 441 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0); 442 443 /* initiallize previous accumulated length to 0 */ 444 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 445 pm8001_ha->non_fatal_read_length = 0; 446 } 447 448 total_len = pm8001_mr32(nonfatal_table_address, 449 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN); 450 /* 451 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT] 452 * field and then request that the SPCv controller transfer the debug 453 * data by setting bit 7 of the Inbound Doorbell Set Register. 454 */ 455 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0); 456 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, 457 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP); 458 459 /* 460 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for 461 * 2 seconds) until register bit 7 is cleared. 462 * This step only indicates the request is accepted by the controller. 463 */ 464 start = jiffies + (2 * HZ); /* 2 sec */ 465 do { 466 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) & 467 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP; 468 } while ((reg_val != 0) && time_before(jiffies, start)); 469 470 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non 471 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in 472 * the MPI Fatal and Non-Fatal Error Dump Capture Table. 473 */ 474 start = jiffies + (2 * HZ); /* 2 sec */ 475 do { 476 reg_val = pm8001_mr32(nonfatal_table_address, 477 MPI_FATAL_EDUMP_TABLE_STATUS); 478 } while ((!reg_val) && time_before(jiffies, start)); 479 480 if ((reg_val == 0x00) || 481 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) || 482 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) { 483 pm8001_ha->non_fatal_read_length = 0; 484 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF); 485 pm8001_ha->non_fatal_count = 0; 486 return (buf_copy - buf); 487 } else if (reg_val == 488 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) { 489 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2); 490 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) || 491 (pm8001_ha->non_fatal_read_length >= total_len)) { 492 pm8001_ha->non_fatal_read_length = 0; 493 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4); 494 pm8001_ha->non_fatal_count = 0; 495 } 496 accum_len = pm8001_mr32(nonfatal_table_address, 497 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 498 output_length = accum_len - 499 pm8001_ha->forensic_preserved_accumulated_transfer; 500 501 for (index = 0; index < output_length/4; index++) 502 buf_copy += snprintf(buf_copy, PAGE_SIZE, 503 "%08x ", *(temp+index)); 504 505 pm8001_ha->non_fatal_read_length += output_length; 506 507 /* store current accumulated length to use in next iteration as 508 * the previous accumulated length 509 */ 510 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len; 511 return (buf_copy - buf); 512 } 513 514 /** 515 * read_main_config_table - read the configure table and save it. 516 * @pm8001_ha: our hba card information 517 */ 518 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 519 { 520 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 521 522 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = 523 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); 524 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = 525 pm8001_mr32(address, MAIN_INTERFACE_REVISION); 526 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = 527 pm8001_mr32(address, MAIN_FW_REVISION); 528 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = 529 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); 530 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = 531 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); 532 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = 533 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); 534 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = 535 pm8001_mr32(address, MAIN_GST_OFFSET); 536 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = 537 pm8001_mr32(address, MAIN_IBQ_OFFSET); 538 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = 539 pm8001_mr32(address, MAIN_OBQ_OFFSET); 540 541 /* read Error Dump Offset and Length */ 542 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = 543 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 544 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = 545 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 546 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = 547 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 548 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = 549 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 550 551 /* read GPIO LED settings from the configuration table */ 552 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = 553 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); 554 555 /* read analog Setting offset from the configuration table */ 556 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = 557 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 558 559 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = 560 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); 561 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = 562 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); 563 /* read port recover and reset timeout */ 564 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer = 565 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER); 566 /* read ILA and inactive firmware version */ 567 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version = 568 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE); 569 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version = 570 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION); 571 572 pm8001_dbg(pm8001_ha, DEV, 573 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n", 574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature, 575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev, 576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev); 577 578 pm8001_dbg(pm8001_ha, DEV, 579 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n", 580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset, 581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset, 582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset, 583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset, 584 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset); 585 586 pm8001_dbg(pm8001_ha, DEV, 587 "Main cfg table; ila rev:%x Inactive fw rev:%x\n", 588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version, 589 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version); 590 } 591 592 /** 593 * read_general_status_table - read the general status table and save it. 594 * @pm8001_ha: our hba card information 595 */ 596 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 597 { 598 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 599 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = 600 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); 601 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = 602 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); 603 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = 604 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); 605 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = 606 pm8001_mr32(address, GST_MSGUTCNT_OFFSET); 607 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = 608 pm8001_mr32(address, GST_IOPTCNT_OFFSET); 609 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = 610 pm8001_mr32(address, GST_GPIO_INPUT_VAL); 611 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = 612 pm8001_mr32(address, GST_RERRINFO_OFFSET0); 613 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = 614 pm8001_mr32(address, GST_RERRINFO_OFFSET1); 615 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = 616 pm8001_mr32(address, GST_RERRINFO_OFFSET2); 617 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = 618 pm8001_mr32(address, GST_RERRINFO_OFFSET3); 619 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = 620 pm8001_mr32(address, GST_RERRINFO_OFFSET4); 621 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = 622 pm8001_mr32(address, GST_RERRINFO_OFFSET5); 623 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = 624 pm8001_mr32(address, GST_RERRINFO_OFFSET6); 625 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = 626 pm8001_mr32(address, GST_RERRINFO_OFFSET7); 627 } 628 /** 629 * read_phy_attr_table - read the phy attribute table and save it. 630 * @pm8001_ha: our hba card information 631 */ 632 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) 633 { 634 void __iomem *address = pm8001_ha->pspa_q_tbl_addr; 635 pm8001_ha->phy_attr_table.phystart1_16[0] = 636 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); 637 pm8001_ha->phy_attr_table.phystart1_16[1] = 638 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); 639 pm8001_ha->phy_attr_table.phystart1_16[2] = 640 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); 641 pm8001_ha->phy_attr_table.phystart1_16[3] = 642 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); 643 pm8001_ha->phy_attr_table.phystart1_16[4] = 644 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); 645 pm8001_ha->phy_attr_table.phystart1_16[5] = 646 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); 647 pm8001_ha->phy_attr_table.phystart1_16[6] = 648 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); 649 pm8001_ha->phy_attr_table.phystart1_16[7] = 650 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); 651 pm8001_ha->phy_attr_table.phystart1_16[8] = 652 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); 653 pm8001_ha->phy_attr_table.phystart1_16[9] = 654 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); 655 pm8001_ha->phy_attr_table.phystart1_16[10] = 656 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); 657 pm8001_ha->phy_attr_table.phystart1_16[11] = 658 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); 659 pm8001_ha->phy_attr_table.phystart1_16[12] = 660 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); 661 pm8001_ha->phy_attr_table.phystart1_16[13] = 662 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); 663 pm8001_ha->phy_attr_table.phystart1_16[14] = 664 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); 665 pm8001_ha->phy_attr_table.phystart1_16[15] = 666 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); 667 668 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = 669 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); 670 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = 671 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); 672 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = 673 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); 674 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = 675 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); 676 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = 677 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); 678 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = 679 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); 680 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = 681 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); 682 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = 683 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); 684 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = 685 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); 686 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = 687 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); 688 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = 689 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); 690 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = 691 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); 692 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = 693 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); 694 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = 695 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); 696 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = 697 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); 698 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = 699 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); 700 701 } 702 703 /** 704 * read_inbnd_queue_table - read the inbound queue table and save it. 705 * @pm8001_ha: our hba card information 706 */ 707 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 708 { 709 int i; 710 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 711 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 712 u32 offset = i * 0x20; 713 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 714 get_pci_bar_index(pm8001_mr32(address, 715 (offset + IB_PIPCI_BAR))); 716 pm8001_ha->inbnd_q_tbl[i].pi_offset = 717 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); 718 } 719 } 720 721 /** 722 * read_outbnd_queue_table - read the outbound queue table and save it. 723 * @pm8001_ha: our hba card information 724 */ 725 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 726 { 727 int i; 728 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 729 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 730 u32 offset = i * 0x24; 731 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 732 get_pci_bar_index(pm8001_mr32(address, 733 (offset + OB_CIPCI_BAR))); 734 pm8001_ha->outbnd_q_tbl[i].ci_offset = 735 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); 736 } 737 } 738 739 /** 740 * init_default_table_values - init the default table. 741 * @pm8001_ha: our hba card information 742 */ 743 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 744 { 745 int i; 746 u32 offsetib, offsetob; 747 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 748 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 749 u32 ib_offset = pm8001_ha->ib_offset; 750 u32 ob_offset = pm8001_ha->ob_offset; 751 u32 ci_offset = pm8001_ha->ci_offset; 752 u32 pi_offset = pm8001_ha->pi_offset; 753 754 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = 755 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 756 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = 757 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 758 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = 759 PM8001_EVENT_LOG_SIZE; 760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; 761 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = 762 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 763 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = 764 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 765 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = 766 PM8001_EVENT_LOG_SIZE; 767 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; 768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; 769 770 /* Disable end to end CRC checking */ 771 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); 772 773 for (i = 0; i < pm8001_ha->max_q_num; i++) { 774 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 775 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 776 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 777 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; 778 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 779 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; 780 pm8001_ha->inbnd_q_tbl[i].base_virt = 781 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; 782 pm8001_ha->inbnd_q_tbl[i].total_length = 783 pm8001_ha->memoryMap.region[ib_offset + i].total_len; 784 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 785 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; 786 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 787 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; 788 pm8001_ha->inbnd_q_tbl[i].ci_virt = 789 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; 790 offsetib = i * 0x20; 791 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 792 get_pci_bar_index(pm8001_mr32(addressib, 793 (offsetib + 0x14))); 794 pm8001_ha->inbnd_q_tbl[i].pi_offset = 795 pm8001_mr32(addressib, (offsetib + 0x18)); 796 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 797 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 798 799 pm8001_dbg(pm8001_ha, DEV, 800 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i, 801 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar, 802 pm8001_ha->inbnd_q_tbl[i].pi_offset); 803 } 804 for (i = 0; i < pm8001_ha->max_q_num; i++) { 805 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 806 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 807 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 808 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; 809 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 810 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; 811 pm8001_ha->outbnd_q_tbl[i].base_virt = 812 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; 813 pm8001_ha->outbnd_q_tbl[i].total_length = 814 pm8001_ha->memoryMap.region[ob_offset + i].total_len; 815 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 816 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; 817 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 818 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; 819 /* interrupt vector based on oq */ 820 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); 821 pm8001_ha->outbnd_q_tbl[i].pi_virt = 822 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; 823 offsetob = i * 0x24; 824 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 825 get_pci_bar_index(pm8001_mr32(addressob, 826 offsetob + 0x14)); 827 pm8001_ha->outbnd_q_tbl[i].ci_offset = 828 pm8001_mr32(addressob, (offsetob + 0x18)); 829 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 830 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 831 832 pm8001_dbg(pm8001_ha, DEV, 833 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i, 834 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar, 835 pm8001_ha->outbnd_q_tbl[i].ci_offset); 836 } 837 } 838 839 /** 840 * update_main_config_table - update the main default table to the HBA. 841 * @pm8001_ha: our hba card information 842 */ 843 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 844 { 845 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 846 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, 847 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); 848 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, 849 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); 850 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, 851 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); 852 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, 853 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); 854 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, 855 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); 856 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, 857 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); 858 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, 859 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); 860 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, 861 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); 862 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, 863 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); 864 /* Update Fatal error interrupt vector */ 865 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 866 ((pm8001_ha->max_q_num - 1) << 8); 867 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, 868 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); 869 pm8001_dbg(pm8001_ha, DEV, 870 "Updated Fatal error interrupt vector 0x%x\n", 871 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)); 872 873 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, 874 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); 875 876 /* SPCv specific */ 877 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; 878 /* Set GPIOLED to 0x2 for LED indicator */ 879 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; 880 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, 881 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); 882 pm8001_dbg(pm8001_ha, DEV, 883 "Programming DW 0x21 in main cfg table with 0x%x\n", 884 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)); 885 886 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 887 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 888 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, 889 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); 890 891 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000; 892 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 893 PORT_RECOVERY_TIMEOUT; 894 if (pm8001_ha->chip_id == chip_8006) { 895 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 896 0x0000ffff; 897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 898 CHIP_8006_PORT_RECOVERY_TIMEOUT; 899 } 900 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 901 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 902 } 903 904 /** 905 * update_inbnd_queue_table - update the inbound queue table to the HBA. 906 * @pm8001_ha: our hba card information 907 * @number: entry in the queue 908 */ 909 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 910 int number) 911 { 912 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 913 u16 offset = number * 0x20; 914 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, 915 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 916 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, 917 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 918 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, 919 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 920 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, 921 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 922 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, 923 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 924 925 pm8001_dbg(pm8001_ha, DEV, 926 "IQ %d: Element pri size 0x%x\n", 927 number, 928 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 929 930 pm8001_dbg(pm8001_ha, DEV, 931 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n", 932 pm8001_ha->inbnd_q_tbl[number].upper_base_addr, 933 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 934 935 pm8001_dbg(pm8001_ha, DEV, 936 "CI upper base addr 0x%x CI lower base addr 0x%x\n", 937 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr, 938 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 939 } 940 941 /** 942 * update_outbnd_queue_table - update the outbound queue table to the HBA. 943 * @pm8001_ha: our hba card information 944 * @number: entry in the queue 945 */ 946 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 947 int number) 948 { 949 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 950 u16 offset = number * 0x24; 951 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, 952 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 953 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, 954 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 955 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, 956 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 957 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, 958 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 959 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, 960 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 961 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, 962 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 963 964 pm8001_dbg(pm8001_ha, DEV, 965 "OQ %d: Element pri size 0x%x\n", 966 number, 967 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 968 969 pm8001_dbg(pm8001_ha, DEV, 970 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n", 971 pm8001_ha->outbnd_q_tbl[number].upper_base_addr, 972 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 973 974 pm8001_dbg(pm8001_ha, DEV, 975 "PI upper base addr 0x%x PI lower base addr 0x%x\n", 976 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr, 977 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 978 } 979 980 /** 981 * mpi_init_check - check firmware initialization status. 982 * @pm8001_ha: our hba card information 983 */ 984 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 985 { 986 u32 max_wait_count; 987 u32 value; 988 u32 gst_len_mpistate; 989 990 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 991 table is updated */ 992 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); 993 /* wait until Inbound DoorBell Clear Register toggled */ 994 if (IS_SPCV_12G(pm8001_ha->pdev)) { 995 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 996 } else { 997 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 998 } 999 do { 1000 msleep(FW_READY_INTERVAL); 1001 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1002 value &= SPCv_MSGU_CFG_TABLE_UPDATE; 1003 } while ((value != 0) && (--max_wait_count)); 1004 1005 if (!max_wait_count) { 1006 /* additional check */ 1007 pm8001_dbg(pm8001_ha, FAIL, 1008 "Inb doorbell clear not toggled[value:%x]\n", 1009 value); 1010 return -EBUSY; 1011 } 1012 /* check the MPI-State for initialization upto 100ms*/ 1013 max_wait_count = 5;/* 100 msec */ 1014 do { 1015 msleep(FW_READY_INTERVAL); 1016 gst_len_mpistate = 1017 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1018 GST_GSTLEN_MPIS_OFFSET); 1019 } while ((GST_MPI_STATE_INIT != 1020 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); 1021 if (!max_wait_count) 1022 return -EBUSY; 1023 1024 /* check MPI Initialization error */ 1025 gst_len_mpistate = gst_len_mpistate >> 16; 1026 if (0x0000 != gst_len_mpistate) 1027 return -EBUSY; 1028 1029 return 0; 1030 } 1031 1032 /** 1033 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 1034 * This function sleeps hence it must not be used in atomic context. 1035 * @pm8001_ha: our hba card information 1036 */ 1037 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 1038 { 1039 u32 value; 1040 u32 max_wait_count; 1041 u32 max_wait_time; 1042 u32 expected_mask; 1043 int ret = 0; 1044 1045 /* reset / PCIe ready */ 1046 max_wait_time = max_wait_count = 5; /* 100 milli sec */ 1047 do { 1048 msleep(FW_READY_INTERVAL); 1049 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1050 } while ((value == 0xFFFFFFFF) && (--max_wait_count)); 1051 1052 /* check ila, RAAE and iops status */ 1053 if ((pm8001_ha->chip_id != chip_8008) && 1054 (pm8001_ha->chip_id != chip_8009)) { 1055 max_wait_time = max_wait_count = 180; /* 3600 milli sec */ 1056 expected_mask = SCRATCH_PAD_ILA_READY | 1057 SCRATCH_PAD_RAAE_READY | 1058 SCRATCH_PAD_IOP0_READY | 1059 SCRATCH_PAD_IOP1_READY; 1060 } else { 1061 max_wait_time = max_wait_count = 170; /* 3400 milli sec */ 1062 expected_mask = SCRATCH_PAD_ILA_READY | 1063 SCRATCH_PAD_RAAE_READY | 1064 SCRATCH_PAD_IOP0_READY; 1065 } 1066 do { 1067 msleep(FW_READY_INTERVAL); 1068 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1069 } while (((value & expected_mask) != 1070 expected_mask) && (--max_wait_count)); 1071 if (!max_wait_count) { 1072 pm8001_dbg(pm8001_ha, INIT, 1073 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n", 1074 max_wait_time * FW_READY_INTERVAL, value); 1075 ret = -1; 1076 } else { 1077 pm8001_dbg(pm8001_ha, MSG, 1078 "All FW components ready by %d ms\n", 1079 (max_wait_time - max_wait_count) * FW_READY_INTERVAL); 1080 } 1081 return ret; 1082 } 1083 1084 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 1085 { 1086 void __iomem *base_addr; 1087 u32 value; 1088 u32 offset; 1089 u32 pcibar; 1090 u32 pcilogic; 1091 1092 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1093 1094 /** 1095 * lower 26 bits of SCRATCHPAD0 register describes offset within the 1096 * PCIe BAR where the MPI configuration table is present 1097 */ 1098 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ 1099 1100 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n", 1101 offset, value); 1102 /** 1103 * Upper 6 bits describe the offset within PCI config space where BAR 1104 * is located. 1105 */ 1106 pcilogic = (value & 0xFC000000) >> 26; 1107 pcibar = get_pci_bar_index(pcilogic); 1108 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); 1109 1110 /** 1111 * Make sure the offset falls inside the ioremapped PCI BAR 1112 */ 1113 if (offset > pm8001_ha->io_mem[pcibar].memsize) { 1114 pm8001_dbg(pm8001_ha, FAIL, 1115 "Main cfg tbl offset outside %u > %u\n", 1116 offset, pm8001_ha->io_mem[pcibar].memsize); 1117 return -EBUSY; 1118 } 1119 pm8001_ha->main_cfg_tbl_addr = base_addr = 1120 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 1121 1122 /** 1123 * Validate main configuration table address: first DWord should read 1124 * "PMCS" 1125 */ 1126 value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0); 1127 if (memcmp(&value, "PMCS", 4) != 0) { 1128 pm8001_dbg(pm8001_ha, FAIL, 1129 "BAD main config signature 0x%x\n", 1130 value); 1131 return -EBUSY; 1132 } 1133 pm8001_dbg(pm8001_ha, INIT, 1134 "VALID main config signature 0x%x\n", value); 1135 pm8001_ha->general_stat_tbl_addr = 1136 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 1137 0xFFFFFF); 1138 pm8001_ha->inbnd_q_tbl_addr = 1139 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & 1140 0xFFFFFF); 1141 pm8001_ha->outbnd_q_tbl_addr = 1142 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & 1143 0xFFFFFF); 1144 pm8001_ha->ivt_tbl_addr = 1145 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & 1146 0xFFFFFF); 1147 pm8001_ha->pspa_q_tbl_addr = 1148 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & 1149 0xFFFFFF); 1150 pm8001_ha->fatal_tbl_addr = 1151 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & 1152 0xFFFFFF); 1153 1154 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n", 1155 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)); 1156 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n", 1157 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)); 1158 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n", 1159 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)); 1160 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n", 1161 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)); 1162 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n", 1163 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)); 1164 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n", 1165 pm8001_ha->main_cfg_tbl_addr, 1166 pm8001_ha->general_stat_tbl_addr); 1167 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n", 1168 pm8001_ha->inbnd_q_tbl_addr, 1169 pm8001_ha->outbnd_q_tbl_addr); 1170 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n", 1171 pm8001_ha->pspa_q_tbl_addr, 1172 pm8001_ha->ivt_tbl_addr); 1173 return 0; 1174 } 1175 1176 /** 1177 * pm80xx_set_thermal_config - support the thermal configuration 1178 * @pm8001_ha: our hba card information. 1179 */ 1180 int 1181 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) 1182 { 1183 struct set_ctrl_cfg_req payload; 1184 struct inbound_queue_table *circularQ; 1185 int rc; 1186 u32 tag; 1187 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1188 u32 page_code; 1189 1190 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1191 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1192 if (rc) 1193 return -1; 1194 1195 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1196 payload.tag = cpu_to_le32(tag); 1197 1198 if (IS_SPCV_12G(pm8001_ha->pdev)) 1199 page_code = THERMAL_PAGE_CODE_7H; 1200 else 1201 page_code = THERMAL_PAGE_CODE_8H; 1202 1203 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) | 1204 (THERMAL_ENABLE << 8) | page_code; 1205 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8); 1206 1207 pm8001_dbg(pm8001_ha, DEV, 1208 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n", 1209 payload.cfg_pg[0], payload.cfg_pg[1]); 1210 1211 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1212 sizeof(payload), 0); 1213 if (rc) 1214 pm8001_tag_free(pm8001_ha, tag); 1215 return rc; 1216 1217 } 1218 1219 /** 1220 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol 1221 * Timer configuration page 1222 * @pm8001_ha: our hba card information. 1223 */ 1224 static int 1225 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) 1226 { 1227 struct set_ctrl_cfg_req payload; 1228 struct inbound_queue_table *circularQ; 1229 SASProtocolTimerConfig_t SASConfigPage; 1230 int rc; 1231 u32 tag; 1232 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1233 1234 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1235 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); 1236 1237 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1238 1239 if (rc) 1240 return -1; 1241 1242 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1243 payload.tag = cpu_to_le32(tag); 1244 1245 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE; 1246 SASConfigPage.MST_MSI = 3 << 15; 1247 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO; 1248 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) | 1249 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER; 1250 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME; 1251 1252 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF) 1253 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF; 1254 1255 1256 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) | 1257 SAS_OPNRJT_RTRY_INTVL; 1258 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16) 1259 | SAS_COPNRJT_RTRY_TMO; 1260 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16) 1261 | SAS_COPNRJT_RTRY_THR; 1262 SASConfigPage.MAX_AIP = SAS_MAX_AIP; 1263 1264 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n", 1265 SASConfigPage.pageCode); 1266 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n", 1267 SASConfigPage.MST_MSI); 1268 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n", 1269 SASConfigPage.STP_SSP_MCT_TMO); 1270 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n", 1271 SASConfigPage.STP_FRM_TMO); 1272 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n", 1273 SASConfigPage.STP_IDLE_TMO); 1274 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n", 1275 SASConfigPage.OPNRJT_RTRY_INTVL); 1276 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n", 1277 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO); 1278 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n", 1279 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR); 1280 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n", 1281 SASConfigPage.MAX_AIP); 1282 1283 memcpy(&payload.cfg_pg, &SASConfigPage, 1284 sizeof(SASProtocolTimerConfig_t)); 1285 1286 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1287 sizeof(payload), 0); 1288 if (rc) 1289 pm8001_tag_free(pm8001_ha, tag); 1290 1291 return rc; 1292 } 1293 1294 /** 1295 * pm80xx_get_encrypt_info - Check for encryption 1296 * @pm8001_ha: our hba card information. 1297 */ 1298 static int 1299 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) 1300 { 1301 u32 scratch3_value; 1302 int ret = -1; 1303 1304 /* Read encryption status from SCRATCH PAD 3 */ 1305 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1306 1307 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1308 SCRATCH_PAD3_ENC_READY) { 1309 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1310 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1311 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1312 SCRATCH_PAD3_SMF_ENABLED) 1313 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1314 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1315 SCRATCH_PAD3_SMA_ENABLED) 1316 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1317 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1318 SCRATCH_PAD3_SMB_ENABLED) 1319 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1320 pm8001_ha->encrypt_info.status = 0; 1321 pm8001_dbg(pm8001_ha, INIT, 1322 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", 1323 scratch3_value, 1324 pm8001_ha->encrypt_info.cipher_mode, 1325 pm8001_ha->encrypt_info.sec_mode, 1326 pm8001_ha->encrypt_info.status); 1327 ret = 0; 1328 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == 1329 SCRATCH_PAD3_ENC_DISABLED) { 1330 pm8001_dbg(pm8001_ha, INIT, 1331 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", 1332 scratch3_value); 1333 pm8001_ha->encrypt_info.status = 0xFFFFFFFF; 1334 pm8001_ha->encrypt_info.cipher_mode = 0; 1335 pm8001_ha->encrypt_info.sec_mode = 0; 1336 ret = 0; 1337 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1338 SCRATCH_PAD3_ENC_DIS_ERR) { 1339 pm8001_ha->encrypt_info.status = 1340 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1341 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1342 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1343 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1344 SCRATCH_PAD3_SMF_ENABLED) 1345 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1346 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1347 SCRATCH_PAD3_SMA_ENABLED) 1348 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1349 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1350 SCRATCH_PAD3_SMB_ENABLED) 1351 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1352 pm8001_dbg(pm8001_ha, INIT, 1353 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1354 scratch3_value, 1355 pm8001_ha->encrypt_info.cipher_mode, 1356 pm8001_ha->encrypt_info.sec_mode, 1357 pm8001_ha->encrypt_info.status); 1358 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1359 SCRATCH_PAD3_ENC_ENA_ERR) { 1360 1361 pm8001_ha->encrypt_info.status = 1362 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1363 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1364 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1365 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1366 SCRATCH_PAD3_SMF_ENABLED) 1367 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1368 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1369 SCRATCH_PAD3_SMA_ENABLED) 1370 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1371 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1372 SCRATCH_PAD3_SMB_ENABLED) 1373 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1374 1375 pm8001_dbg(pm8001_ha, INIT, 1376 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1377 scratch3_value, 1378 pm8001_ha->encrypt_info.cipher_mode, 1379 pm8001_ha->encrypt_info.sec_mode, 1380 pm8001_ha->encrypt_info.status); 1381 } 1382 return ret; 1383 } 1384 1385 /** 1386 * pm80xx_encrypt_update - update flash with encryption informtion 1387 * @pm8001_ha: our hba card information. 1388 */ 1389 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) 1390 { 1391 struct kek_mgmt_req payload; 1392 struct inbound_queue_table *circularQ; 1393 int rc; 1394 u32 tag; 1395 u32 opc = OPC_INB_KEK_MANAGEMENT; 1396 1397 memset(&payload, 0, sizeof(struct kek_mgmt_req)); 1398 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1399 if (rc) 1400 return -1; 1401 1402 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1403 payload.tag = cpu_to_le32(tag); 1404 /* Currently only one key is used. New KEK index is 1. 1405 * Current KEK index is 1. Store KEK to NVRAM is 1. 1406 */ 1407 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) | 1408 KEK_MGMT_SUBOP_KEYCARDUPDATE); 1409 1410 pm8001_dbg(pm8001_ha, DEV, 1411 "Saving Encryption info to flash. payload 0x%x\n", 1412 payload.new_curidx_ksop); 1413 1414 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1415 sizeof(payload), 0); 1416 if (rc) 1417 pm8001_tag_free(pm8001_ha, tag); 1418 1419 return rc; 1420 } 1421 1422 /** 1423 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 1424 * @pm8001_ha: our hba card information 1425 */ 1426 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) 1427 { 1428 int ret; 1429 u8 i = 0; 1430 1431 /* check the firmware status */ 1432 if (-1 == check_fw_ready(pm8001_ha)) { 1433 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1434 return -EBUSY; 1435 } 1436 1437 /* Initialize the controller fatal error flag */ 1438 pm8001_ha->controller_fatal_error = false; 1439 1440 /* Initialize pci space address eg: mpi offset */ 1441 ret = init_pci_device_addresses(pm8001_ha); 1442 if (ret) { 1443 pm8001_dbg(pm8001_ha, FAIL, 1444 "Failed to init pci addresses"); 1445 return ret; 1446 } 1447 init_default_table_values(pm8001_ha); 1448 read_main_config_table(pm8001_ha); 1449 read_general_status_table(pm8001_ha); 1450 read_inbnd_queue_table(pm8001_ha); 1451 read_outbnd_queue_table(pm8001_ha); 1452 read_phy_attr_table(pm8001_ha); 1453 1454 /* update main config table ,inbound table and outbound table */ 1455 update_main_config_table(pm8001_ha); 1456 for (i = 0; i < pm8001_ha->max_q_num; i++) { 1457 update_inbnd_queue_table(pm8001_ha, i); 1458 update_outbnd_queue_table(pm8001_ha, i); 1459 } 1460 /* notify firmware update finished and check initialization status */ 1461 if (0 == mpi_init_check(pm8001_ha)) { 1462 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n"); 1463 } else 1464 return -EBUSY; 1465 1466 /* send SAS protocol timer configuration page to FW */ 1467 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha); 1468 1469 /* Check for encryption */ 1470 if (pm8001_ha->chip->encrypt) { 1471 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n"); 1472 ret = pm80xx_get_encrypt_info(pm8001_ha); 1473 if (ret == -1) { 1474 pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n"); 1475 if (pm8001_ha->encrypt_info.status == 0x81) { 1476 pm8001_dbg(pm8001_ha, INIT, 1477 "Encryption enabled with error.Saving encryption key to flash\n"); 1478 pm80xx_encrypt_update(pm8001_ha); 1479 } 1480 } 1481 } 1482 return 0; 1483 } 1484 1485 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 1486 { 1487 u32 max_wait_count; 1488 u32 value; 1489 u32 gst_len_mpistate; 1490 int ret; 1491 1492 ret = init_pci_device_addresses(pm8001_ha); 1493 if (ret) { 1494 pm8001_dbg(pm8001_ha, FAIL, 1495 "Failed to init pci addresses"); 1496 return ret; 1497 } 1498 1499 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 1500 table is stop */ 1501 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); 1502 1503 /* wait until Inbound DoorBell Clear Register toggled */ 1504 if (IS_SPCV_12G(pm8001_ha->pdev)) { 1505 max_wait_count = 4 * 1000 * 1000;/* 4 sec */ 1506 } else { 1507 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1508 } 1509 do { 1510 udelay(1); 1511 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1512 value &= SPCv_MSGU_CFG_TABLE_RESET; 1513 } while ((value != 0) && (--max_wait_count)); 1514 1515 if (!max_wait_count) { 1516 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value); 1517 return -1; 1518 } 1519 1520 /* check the MPI-State for termination in progress */ 1521 /* wait until Inbound DoorBell Clear Register toggled */ 1522 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */ 1523 do { 1524 udelay(1); 1525 gst_len_mpistate = 1526 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1527 GST_GSTLEN_MPIS_OFFSET); 1528 if (GST_MPI_STATE_UNINIT == 1529 (gst_len_mpistate & GST_MPI_STATE_MASK)) 1530 break; 1531 } while (--max_wait_count); 1532 if (!max_wait_count) { 1533 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", 1534 gst_len_mpistate & GST_MPI_STATE_MASK); 1535 return -1; 1536 } 1537 1538 return 0; 1539 } 1540 1541 /** 1542 * pm80xx_fatal_errors - returns non zero *ONLY* when fatal errors 1543 * @pm8001_ha: our hba card information 1544 * 1545 * Fatal errors are recoverable only after a host reboot. 1546 */ 1547 int 1548 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha) 1549 { 1550 int ret = 0; 1551 u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0, 1552 MSGU_HOST_SCRATCH_PAD_6); 1553 u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0, 1554 MSGU_HOST_SCRATCH_PAD_7); 1555 u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1556 u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1557 u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1558 1559 if (pm8001_ha->chip_id != chip_8006 && 1560 pm8001_ha->chip_id != chip_8074 && 1561 pm8001_ha->chip_id != chip_8076) { 1562 return 0; 1563 } 1564 1565 if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) { 1566 pm8001_dbg(pm8001_ha, FAIL, 1567 "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n", 1568 scratch_pad1, scratch_pad2, scratch_pad3, 1569 scratch_pad_rsvd0, scratch_pad_rsvd1); 1570 ret = 1; 1571 } 1572 1573 return ret; 1574 } 1575 1576 /** 1577 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 1578 * the FW register status to the originated status. 1579 * @pm8001_ha: our hba card information 1580 */ 1581 1582 static int 1583 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 1584 { 1585 u32 regval; 1586 u32 bootloader_state; 1587 u32 ibutton0, ibutton1; 1588 1589 /* Process MPI table uninitialization only if FW is ready */ 1590 if (!pm8001_ha->controller_fatal_error) { 1591 /* Check if MPI is in ready state to reset */ 1592 if (mpi_uninit_check(pm8001_ha) != 0) { 1593 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1594 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1595 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1596 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1597 pm8001_dbg(pm8001_ha, FAIL, 1598 "MPI state is not ready scratch: %x:%x:%x:%x\n", 1599 r0, r1, r2, r3); 1600 /* if things aren't ready but the bootloader is ok then 1601 * try the reset anyway. 1602 */ 1603 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK) 1604 return -1; 1605 } 1606 } 1607 /* checked for reset register normal state; 0x0 */ 1608 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1609 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n", 1610 regval); 1611 1612 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); 1613 msleep(500); 1614 1615 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1616 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n", 1617 regval); 1618 1619 if ((regval & SPCv_SOFT_RESET_READ_MASK) == 1620 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { 1621 pm8001_dbg(pm8001_ha, MSG, 1622 " soft reset successful [regval: 0x%x]\n", 1623 regval); 1624 } else { 1625 pm8001_dbg(pm8001_ha, MSG, 1626 " soft reset failed [regval: 0x%x]\n", 1627 regval); 1628 1629 /* check bootloader is successfully executed or in HDA mode */ 1630 bootloader_state = 1631 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1632 SCRATCH_PAD1_BOOTSTATE_MASK; 1633 1634 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { 1635 pm8001_dbg(pm8001_ha, MSG, 1636 "Bootloader state - HDA mode SEEPROM\n"); 1637 } else if (bootloader_state == 1638 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { 1639 pm8001_dbg(pm8001_ha, MSG, 1640 "Bootloader state - HDA mode Bootstrap Pin\n"); 1641 } else if (bootloader_state == 1642 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { 1643 pm8001_dbg(pm8001_ha, MSG, 1644 "Bootloader state - HDA mode soft reset\n"); 1645 } else if (bootloader_state == 1646 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { 1647 pm8001_dbg(pm8001_ha, MSG, 1648 "Bootloader state-HDA mode critical error\n"); 1649 } 1650 return -EBUSY; 1651 } 1652 1653 /* check the firmware status after reset */ 1654 if (-1 == check_fw_ready(pm8001_ha)) { 1655 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1656 /* check iButton feature support for motherboard controller */ 1657 if (pm8001_ha->pdev->subsystem_vendor != 1658 PCI_VENDOR_ID_ADAPTEC2 && 1659 pm8001_ha->pdev->subsystem_vendor != 1660 PCI_VENDOR_ID_ATTO && 1661 pm8001_ha->pdev->subsystem_vendor != 0) { 1662 ibutton0 = pm8001_cr32(pm8001_ha, 0, 1663 MSGU_HOST_SCRATCH_PAD_6); 1664 ibutton1 = pm8001_cr32(pm8001_ha, 0, 1665 MSGU_HOST_SCRATCH_PAD_7); 1666 if (!ibutton0 && !ibutton1) { 1667 pm8001_dbg(pm8001_ha, FAIL, 1668 "iButton Feature is not Available!!!\n"); 1669 return -EBUSY; 1670 } 1671 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { 1672 pm8001_dbg(pm8001_ha, FAIL, 1673 "CRC Check for iButton Feature Failed!!!\n"); 1674 return -EBUSY; 1675 } 1676 } 1677 } 1678 pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n"); 1679 return 0; 1680 } 1681 1682 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1683 { 1684 u32 i; 1685 1686 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n"); 1687 1688 /* do SPCv chip reset. */ 1689 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); 1690 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n"); 1691 1692 /* Check this ..whether delay is required or no */ 1693 /* delay 10 usec */ 1694 udelay(10); 1695 1696 /* wait for 20 msec until the firmware gets reloaded */ 1697 i = 20; 1698 do { 1699 mdelay(1); 1700 } while ((--i) != 0); 1701 1702 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); 1703 } 1704 1705 /** 1706 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1707 * @pm8001_ha: our hba card information 1708 */ 1709 static void 1710 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1711 { 1712 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1713 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1714 } 1715 1716 /** 1717 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1718 * @pm8001_ha: our hba card information 1719 */ 1720 static void 1721 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1722 { 1723 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); 1724 } 1725 1726 /** 1727 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1728 * @pm8001_ha: our hba card information 1729 * @vec: interrupt number to enable 1730 */ 1731 static void 1732 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1733 { 1734 #ifdef PM8001_USE_MSIX 1735 u32 mask; 1736 mask = (u32)(1 << vec); 1737 1738 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); 1739 return; 1740 #endif 1741 pm80xx_chip_intx_interrupt_enable(pm8001_ha); 1742 1743 } 1744 1745 /** 1746 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt 1747 * @pm8001_ha: our hba card information 1748 * @vec: interrupt number to disable 1749 */ 1750 static void 1751 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1752 { 1753 #ifdef PM8001_USE_MSIX 1754 u32 mask; 1755 if (vec == 0xFF) 1756 mask = 0xFFFFFFFF; 1757 else 1758 mask = (u32)(1 << vec); 1759 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); 1760 return; 1761 #endif 1762 pm80xx_chip_intx_interrupt_disable(pm8001_ha); 1763 } 1764 1765 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1766 struct pm8001_device *pm8001_ha_dev) 1767 { 1768 int res; 1769 u32 ccb_tag; 1770 struct pm8001_ccb_info *ccb; 1771 struct sas_task *task = NULL; 1772 struct task_abort_req task_abort; 1773 struct inbound_queue_table *circularQ; 1774 u32 opc = OPC_INB_SATA_ABORT; 1775 int ret; 1776 1777 if (!pm8001_ha_dev) { 1778 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n"); 1779 return; 1780 } 1781 1782 task = sas_alloc_slow_task(GFP_ATOMIC); 1783 1784 if (!task) { 1785 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n"); 1786 return; 1787 } 1788 1789 task->task_done = pm8001_task_done; 1790 1791 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1792 if (res) { 1793 sas_free_task(task); 1794 return; 1795 } 1796 1797 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1798 ccb->device = pm8001_ha_dev; 1799 ccb->ccb_tag = ccb_tag; 1800 ccb->task = task; 1801 1802 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1803 1804 memset(&task_abort, 0, sizeof(task_abort)); 1805 task_abort.abort_all = cpu_to_le32(1); 1806 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1807 task_abort.tag = cpu_to_le32(ccb_tag); 1808 1809 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 1810 sizeof(task_abort), 0); 1811 pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n"); 1812 if (ret) { 1813 sas_free_task(task); 1814 pm8001_tag_free(pm8001_ha, ccb_tag); 1815 } 1816 } 1817 1818 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha, 1819 struct pm8001_device *pm8001_ha_dev) 1820 { 1821 struct sata_start_req sata_cmd; 1822 int res; 1823 u32 ccb_tag; 1824 struct pm8001_ccb_info *ccb; 1825 struct sas_task *task = NULL; 1826 struct host_to_dev_fis fis; 1827 struct domain_device *dev; 1828 struct inbound_queue_table *circularQ; 1829 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1830 1831 task = sas_alloc_slow_task(GFP_ATOMIC); 1832 1833 if (!task) { 1834 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n"); 1835 return; 1836 } 1837 task->task_done = pm8001_task_done; 1838 1839 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1840 if (res) { 1841 sas_free_task(task); 1842 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n"); 1843 return; 1844 } 1845 1846 /* allocate domain device by ourselves as libsas 1847 * is not going to provide any 1848 */ 1849 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1850 if (!dev) { 1851 sas_free_task(task); 1852 pm8001_tag_free(pm8001_ha, ccb_tag); 1853 pm8001_dbg(pm8001_ha, FAIL, 1854 "Domain device cannot be allocated\n"); 1855 return; 1856 } 1857 1858 task->dev = dev; 1859 task->dev->lldd_dev = pm8001_ha_dev; 1860 1861 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1862 ccb->device = pm8001_ha_dev; 1863 ccb->ccb_tag = ccb_tag; 1864 ccb->task = task; 1865 ccb->n_elem = 0; 1866 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1867 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1868 1869 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1870 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1871 1872 /* construct read log FIS */ 1873 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1874 fis.fis_type = 0x27; 1875 fis.flags = 0x80; 1876 fis.command = ATA_CMD_READ_LOG_EXT; 1877 fis.lbal = 0x10; 1878 fis.sector_count = 0x1; 1879 1880 sata_cmd.tag = cpu_to_le32(ccb_tag); 1881 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1882 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9)); 1883 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1884 1885 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 1886 sizeof(sata_cmd), 0); 1887 pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n"); 1888 if (res) { 1889 sas_free_task(task); 1890 pm8001_tag_free(pm8001_ha, ccb_tag); 1891 kfree(dev); 1892 } 1893 } 1894 1895 /** 1896 * mpi_ssp_completion- process the event that FW response to the SSP request. 1897 * @pm8001_ha: our hba card information 1898 * @piomb: the message contents of this outbound message. 1899 * 1900 * When FW has completed a ssp request for example a IO request, after it has 1901 * filled the SG data with the data, it will trigger this event represent 1902 * that he has finished the job,please check the coresponding buffer. 1903 * So we will tell the caller who maybe waiting the result to tell upper layer 1904 * that the task has been finished. 1905 */ 1906 static void 1907 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1908 { 1909 struct sas_task *t; 1910 struct pm8001_ccb_info *ccb; 1911 unsigned long flags; 1912 u32 status; 1913 u32 param; 1914 u32 tag; 1915 struct ssp_completion_resp *psspPayload; 1916 struct task_status_struct *ts; 1917 struct ssp_response_iu *iu; 1918 struct pm8001_device *pm8001_dev; 1919 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1920 status = le32_to_cpu(psspPayload->status); 1921 tag = le32_to_cpu(psspPayload->tag); 1922 ccb = &pm8001_ha->ccb_info[tag]; 1923 if ((status == IO_ABORTED) && ccb->open_retry) { 1924 /* Being completed by another */ 1925 ccb->open_retry = 0; 1926 return; 1927 } 1928 pm8001_dev = ccb->device; 1929 param = le32_to_cpu(psspPayload->param); 1930 t = ccb->task; 1931 1932 if (status && status != IO_UNDERFLOW) 1933 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); 1934 if (unlikely(!t || !t->lldd_task || !t->dev)) 1935 return; 1936 ts = &t->task_status; 1937 1938 pm8001_dbg(pm8001_ha, DEV, 1939 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t); 1940 1941 /* Print sas address of IO failed device */ 1942 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1943 (status != IO_UNDERFLOW)) 1944 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n", 1945 SAS_ADDR(t->dev->sas_addr)); 1946 1947 switch (status) { 1948 case IO_SUCCESS: 1949 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n", 1950 param); 1951 if (param == 0) { 1952 ts->resp = SAS_TASK_COMPLETE; 1953 ts->stat = SAM_STAT_GOOD; 1954 } else { 1955 ts->resp = SAS_TASK_COMPLETE; 1956 ts->stat = SAS_PROTO_RESPONSE; 1957 ts->residual = param; 1958 iu = &psspPayload->ssp_resp_iu; 1959 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1960 } 1961 if (pm8001_dev) 1962 atomic_dec(&pm8001_dev->running_req); 1963 break; 1964 case IO_ABORTED: 1965 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 1966 ts->resp = SAS_TASK_COMPLETE; 1967 ts->stat = SAS_ABORTED_TASK; 1968 if (pm8001_dev) 1969 atomic_dec(&pm8001_dev->running_req); 1970 break; 1971 case IO_UNDERFLOW: 1972 /* SSP Completion with error */ 1973 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n", 1974 param); 1975 ts->resp = SAS_TASK_COMPLETE; 1976 ts->stat = SAS_DATA_UNDERRUN; 1977 ts->residual = param; 1978 if (pm8001_dev) 1979 atomic_dec(&pm8001_dev->running_req); 1980 break; 1981 case IO_NO_DEVICE: 1982 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 1983 ts->resp = SAS_TASK_UNDELIVERED; 1984 ts->stat = SAS_PHY_DOWN; 1985 if (pm8001_dev) 1986 atomic_dec(&pm8001_dev->running_req); 1987 break; 1988 case IO_XFER_ERROR_BREAK: 1989 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 1990 ts->resp = SAS_TASK_COMPLETE; 1991 ts->stat = SAS_OPEN_REJECT; 1992 /* Force the midlayer to retry */ 1993 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1994 if (pm8001_dev) 1995 atomic_dec(&pm8001_dev->running_req); 1996 break; 1997 case IO_XFER_ERROR_PHY_NOT_READY: 1998 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 1999 ts->resp = SAS_TASK_COMPLETE; 2000 ts->stat = SAS_OPEN_REJECT; 2001 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2002 if (pm8001_dev) 2003 atomic_dec(&pm8001_dev->running_req); 2004 break; 2005 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME: 2006 pm8001_dbg(pm8001_ha, IO, 2007 "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"); 2008 ts->resp = SAS_TASK_COMPLETE; 2009 ts->stat = SAS_OPEN_REJECT; 2010 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2011 if (pm8001_dev) 2012 atomic_dec(&pm8001_dev->running_req); 2013 break; 2014 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2015 pm8001_dbg(pm8001_ha, IO, 2016 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2017 ts->resp = SAS_TASK_COMPLETE; 2018 ts->stat = SAS_OPEN_REJECT; 2019 ts->open_rej_reason = SAS_OREJ_EPROTO; 2020 if (pm8001_dev) 2021 atomic_dec(&pm8001_dev->running_req); 2022 break; 2023 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2024 pm8001_dbg(pm8001_ha, IO, 2025 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2026 ts->resp = SAS_TASK_COMPLETE; 2027 ts->stat = SAS_OPEN_REJECT; 2028 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2029 if (pm8001_dev) 2030 atomic_dec(&pm8001_dev->running_req); 2031 break; 2032 case IO_OPEN_CNX_ERROR_BREAK: 2033 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2034 ts->resp = SAS_TASK_COMPLETE; 2035 ts->stat = SAS_OPEN_REJECT; 2036 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2037 if (pm8001_dev) 2038 atomic_dec(&pm8001_dev->running_req); 2039 break; 2040 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2041 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2042 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2043 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2044 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2045 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2046 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2047 ts->resp = SAS_TASK_COMPLETE; 2048 ts->stat = SAS_OPEN_REJECT; 2049 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2050 if (!t->uldd_task) 2051 pm8001_handle_event(pm8001_ha, 2052 pm8001_dev, 2053 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2054 break; 2055 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2056 pm8001_dbg(pm8001_ha, IO, 2057 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2058 ts->resp = SAS_TASK_COMPLETE; 2059 ts->stat = SAS_OPEN_REJECT; 2060 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2061 if (pm8001_dev) 2062 atomic_dec(&pm8001_dev->running_req); 2063 break; 2064 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2065 pm8001_dbg(pm8001_ha, IO, 2066 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2067 ts->resp = SAS_TASK_COMPLETE; 2068 ts->stat = SAS_OPEN_REJECT; 2069 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2070 if (pm8001_dev) 2071 atomic_dec(&pm8001_dev->running_req); 2072 break; 2073 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2074 pm8001_dbg(pm8001_ha, IO, 2075 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2076 ts->resp = SAS_TASK_UNDELIVERED; 2077 ts->stat = SAS_OPEN_REJECT; 2078 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2079 if (pm8001_dev) 2080 atomic_dec(&pm8001_dev->running_req); 2081 break; 2082 case IO_XFER_ERROR_NAK_RECEIVED: 2083 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2084 ts->resp = SAS_TASK_COMPLETE; 2085 ts->stat = SAS_OPEN_REJECT; 2086 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2087 if (pm8001_dev) 2088 atomic_dec(&pm8001_dev->running_req); 2089 break; 2090 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2091 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2092 ts->resp = SAS_TASK_COMPLETE; 2093 ts->stat = SAS_NAK_R_ERR; 2094 if (pm8001_dev) 2095 atomic_dec(&pm8001_dev->running_req); 2096 break; 2097 case IO_XFER_ERROR_DMA: 2098 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2099 ts->resp = SAS_TASK_COMPLETE; 2100 ts->stat = SAS_OPEN_REJECT; 2101 if (pm8001_dev) 2102 atomic_dec(&pm8001_dev->running_req); 2103 break; 2104 case IO_XFER_OPEN_RETRY_TIMEOUT: 2105 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2106 ts->resp = SAS_TASK_COMPLETE; 2107 ts->stat = SAS_OPEN_REJECT; 2108 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2109 if (pm8001_dev) 2110 atomic_dec(&pm8001_dev->running_req); 2111 break; 2112 case IO_XFER_ERROR_OFFSET_MISMATCH: 2113 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2114 ts->resp = SAS_TASK_COMPLETE; 2115 ts->stat = SAS_OPEN_REJECT; 2116 if (pm8001_dev) 2117 atomic_dec(&pm8001_dev->running_req); 2118 break; 2119 case IO_PORT_IN_RESET: 2120 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2121 ts->resp = SAS_TASK_COMPLETE; 2122 ts->stat = SAS_OPEN_REJECT; 2123 if (pm8001_dev) 2124 atomic_dec(&pm8001_dev->running_req); 2125 break; 2126 case IO_DS_NON_OPERATIONAL: 2127 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2128 ts->resp = SAS_TASK_COMPLETE; 2129 ts->stat = SAS_OPEN_REJECT; 2130 if (!t->uldd_task) 2131 pm8001_handle_event(pm8001_ha, 2132 pm8001_dev, 2133 IO_DS_NON_OPERATIONAL); 2134 break; 2135 case IO_DS_IN_RECOVERY: 2136 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2137 ts->resp = SAS_TASK_COMPLETE; 2138 ts->stat = SAS_OPEN_REJECT; 2139 if (pm8001_dev) 2140 atomic_dec(&pm8001_dev->running_req); 2141 break; 2142 case IO_TM_TAG_NOT_FOUND: 2143 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n"); 2144 ts->resp = SAS_TASK_COMPLETE; 2145 ts->stat = SAS_OPEN_REJECT; 2146 if (pm8001_dev) 2147 atomic_dec(&pm8001_dev->running_req); 2148 break; 2149 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 2150 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"); 2151 ts->resp = SAS_TASK_COMPLETE; 2152 ts->stat = SAS_OPEN_REJECT; 2153 if (pm8001_dev) 2154 atomic_dec(&pm8001_dev->running_req); 2155 break; 2156 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2157 pm8001_dbg(pm8001_ha, IO, 2158 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2159 ts->resp = SAS_TASK_COMPLETE; 2160 ts->stat = SAS_OPEN_REJECT; 2161 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2162 if (pm8001_dev) 2163 atomic_dec(&pm8001_dev->running_req); 2164 break; 2165 default: 2166 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2167 /* not allowed case. Therefore, return failed status */ 2168 ts->resp = SAS_TASK_COMPLETE; 2169 ts->stat = SAS_OPEN_REJECT; 2170 if (pm8001_dev) 2171 atomic_dec(&pm8001_dev->running_req); 2172 break; 2173 } 2174 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ", 2175 psspPayload->ssp_resp_iu.status); 2176 spin_lock_irqsave(&t->task_state_lock, flags); 2177 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2178 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2179 t->task_state_flags |= SAS_TASK_STATE_DONE; 2180 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2181 spin_unlock_irqrestore(&t->task_state_lock, flags); 2182 pm8001_dbg(pm8001_ha, FAIL, 2183 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2184 t, status, ts->resp, ts->stat); 2185 if (t->slow_task) 2186 complete(&t->slow_task->completion); 2187 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2188 } else { 2189 spin_unlock_irqrestore(&t->task_state_lock, flags); 2190 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2191 mb();/* in order to force CPU ordering */ 2192 t->task_done(t); 2193 } 2194 } 2195 2196 /*See the comments for mpi_ssp_completion */ 2197 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2198 { 2199 struct sas_task *t; 2200 unsigned long flags; 2201 struct task_status_struct *ts; 2202 struct pm8001_ccb_info *ccb; 2203 struct pm8001_device *pm8001_dev; 2204 struct ssp_event_resp *psspPayload = 2205 (struct ssp_event_resp *)(piomb + 4); 2206 u32 event = le32_to_cpu(psspPayload->event); 2207 u32 tag = le32_to_cpu(psspPayload->tag); 2208 u32 port_id = le32_to_cpu(psspPayload->port_id); 2209 2210 ccb = &pm8001_ha->ccb_info[tag]; 2211 t = ccb->task; 2212 pm8001_dev = ccb->device; 2213 if (event) 2214 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); 2215 if (unlikely(!t || !t->lldd_task || !t->dev)) 2216 return; 2217 ts = &t->task_status; 2218 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2219 port_id, tag, event); 2220 switch (event) { 2221 case IO_OVERFLOW: 2222 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2223 ts->resp = SAS_TASK_COMPLETE; 2224 ts->stat = SAS_DATA_OVERRUN; 2225 ts->residual = 0; 2226 if (pm8001_dev) 2227 atomic_dec(&pm8001_dev->running_req); 2228 break; 2229 case IO_XFER_ERROR_BREAK: 2230 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2231 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2232 return; 2233 case IO_XFER_ERROR_PHY_NOT_READY: 2234 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2235 ts->resp = SAS_TASK_COMPLETE; 2236 ts->stat = SAS_OPEN_REJECT; 2237 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2238 break; 2239 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2240 pm8001_dbg(pm8001_ha, IO, 2241 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2242 ts->resp = SAS_TASK_COMPLETE; 2243 ts->stat = SAS_OPEN_REJECT; 2244 ts->open_rej_reason = SAS_OREJ_EPROTO; 2245 break; 2246 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2247 pm8001_dbg(pm8001_ha, IO, 2248 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2249 ts->resp = SAS_TASK_COMPLETE; 2250 ts->stat = SAS_OPEN_REJECT; 2251 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2252 break; 2253 case IO_OPEN_CNX_ERROR_BREAK: 2254 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2255 ts->resp = SAS_TASK_COMPLETE; 2256 ts->stat = SAS_OPEN_REJECT; 2257 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2258 break; 2259 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2260 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2261 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2262 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2263 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2264 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2265 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2266 ts->resp = SAS_TASK_COMPLETE; 2267 ts->stat = SAS_OPEN_REJECT; 2268 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2269 if (!t->uldd_task) 2270 pm8001_handle_event(pm8001_ha, 2271 pm8001_dev, 2272 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2273 break; 2274 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2275 pm8001_dbg(pm8001_ha, IO, 2276 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2277 ts->resp = SAS_TASK_COMPLETE; 2278 ts->stat = SAS_OPEN_REJECT; 2279 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2280 break; 2281 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2282 pm8001_dbg(pm8001_ha, IO, 2283 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2284 ts->resp = SAS_TASK_COMPLETE; 2285 ts->stat = SAS_OPEN_REJECT; 2286 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2287 break; 2288 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2289 pm8001_dbg(pm8001_ha, IO, 2290 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2291 ts->resp = SAS_TASK_COMPLETE; 2292 ts->stat = SAS_OPEN_REJECT; 2293 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2294 break; 2295 case IO_XFER_ERROR_NAK_RECEIVED: 2296 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2297 ts->resp = SAS_TASK_COMPLETE; 2298 ts->stat = SAS_OPEN_REJECT; 2299 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2300 break; 2301 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2302 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2303 ts->resp = SAS_TASK_COMPLETE; 2304 ts->stat = SAS_NAK_R_ERR; 2305 break; 2306 case IO_XFER_OPEN_RETRY_TIMEOUT: 2307 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2308 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2309 return; 2310 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2311 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2312 ts->resp = SAS_TASK_COMPLETE; 2313 ts->stat = SAS_DATA_OVERRUN; 2314 break; 2315 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2316 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2317 ts->resp = SAS_TASK_COMPLETE; 2318 ts->stat = SAS_DATA_OVERRUN; 2319 break; 2320 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2321 pm8001_dbg(pm8001_ha, IO, 2322 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2323 ts->resp = SAS_TASK_COMPLETE; 2324 ts->stat = SAS_DATA_OVERRUN; 2325 break; 2326 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2327 pm8001_dbg(pm8001_ha, IO, 2328 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"); 2329 ts->resp = SAS_TASK_COMPLETE; 2330 ts->stat = SAS_DATA_OVERRUN; 2331 break; 2332 case IO_XFER_ERROR_OFFSET_MISMATCH: 2333 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2334 ts->resp = SAS_TASK_COMPLETE; 2335 ts->stat = SAS_DATA_OVERRUN; 2336 break; 2337 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2338 pm8001_dbg(pm8001_ha, IO, 2339 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2340 ts->resp = SAS_TASK_COMPLETE; 2341 ts->stat = SAS_DATA_OVERRUN; 2342 break; 2343 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2344 pm8001_dbg(pm8001_ha, IOERR, 2345 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2346 /* TBC: used default set values */ 2347 ts->resp = SAS_TASK_COMPLETE; 2348 ts->stat = SAS_DATA_OVERRUN; 2349 break; 2350 case IO_XFER_CMD_FRAME_ISSUED: 2351 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2352 return; 2353 default: 2354 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2355 /* not allowed case. Therefore, return failed status */ 2356 ts->resp = SAS_TASK_COMPLETE; 2357 ts->stat = SAS_DATA_OVERRUN; 2358 break; 2359 } 2360 spin_lock_irqsave(&t->task_state_lock, flags); 2361 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2362 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2363 t->task_state_flags |= SAS_TASK_STATE_DONE; 2364 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2365 spin_unlock_irqrestore(&t->task_state_lock, flags); 2366 pm8001_dbg(pm8001_ha, FAIL, 2367 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2368 t, event, ts->resp, ts->stat); 2369 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2370 } else { 2371 spin_unlock_irqrestore(&t->task_state_lock, flags); 2372 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2373 mb();/* in order to force CPU ordering */ 2374 t->task_done(t); 2375 } 2376 } 2377 2378 /*See the comments for mpi_ssp_completion */ 2379 static void 2380 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2381 { 2382 struct sas_task *t; 2383 struct pm8001_ccb_info *ccb; 2384 u32 param; 2385 u32 status; 2386 u32 tag; 2387 int i, j; 2388 u8 sata_addr_low[4]; 2389 u32 temp_sata_addr_low, temp_sata_addr_hi; 2390 u8 sata_addr_hi[4]; 2391 struct sata_completion_resp *psataPayload; 2392 struct task_status_struct *ts; 2393 struct ata_task_resp *resp ; 2394 u32 *sata_resp; 2395 struct pm8001_device *pm8001_dev; 2396 unsigned long flags; 2397 2398 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2399 status = le32_to_cpu(psataPayload->status); 2400 tag = le32_to_cpu(psataPayload->tag); 2401 2402 if (!tag) { 2403 pm8001_dbg(pm8001_ha, FAIL, "tag null\n"); 2404 return; 2405 } 2406 ccb = &pm8001_ha->ccb_info[tag]; 2407 param = le32_to_cpu(psataPayload->param); 2408 if (ccb) { 2409 t = ccb->task; 2410 pm8001_dev = ccb->device; 2411 } else { 2412 pm8001_dbg(pm8001_ha, FAIL, "ccb null\n"); 2413 return; 2414 } 2415 2416 if (t) { 2417 if (t->dev && (t->dev->lldd_dev)) 2418 pm8001_dev = t->dev->lldd_dev; 2419 } else { 2420 pm8001_dbg(pm8001_ha, FAIL, "task null\n"); 2421 return; 2422 } 2423 2424 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2425 && unlikely(!t || !t->lldd_task || !t->dev)) { 2426 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2427 return; 2428 } 2429 2430 ts = &t->task_status; 2431 if (!ts) { 2432 pm8001_dbg(pm8001_ha, FAIL, "ts null\n"); 2433 return; 2434 } 2435 2436 if (status != IO_SUCCESS) { 2437 pm8001_dbg(pm8001_ha, FAIL, 2438 "IO failed device_id %u status 0x%x tag %d\n", 2439 pm8001_dev->device_id, status, tag); 2440 } 2441 2442 /* Print sas address of IO failed device */ 2443 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2444 (status != IO_UNDERFLOW)) { 2445 if (!((t->dev->parent) && 2446 (dev_is_expander(t->dev->parent->dev_type)))) { 2447 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++) 2448 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2449 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++) 2450 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2451 memcpy(&temp_sata_addr_low, sata_addr_low, 2452 sizeof(sata_addr_low)); 2453 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2454 sizeof(sata_addr_hi)); 2455 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2456 |((temp_sata_addr_hi << 8) & 2457 0xff0000) | 2458 ((temp_sata_addr_hi >> 8) 2459 & 0xff00) | 2460 ((temp_sata_addr_hi << 24) & 2461 0xff000000)); 2462 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2463 & 0xff) | 2464 ((temp_sata_addr_low << 8) 2465 & 0xff0000) | 2466 ((temp_sata_addr_low >> 8) 2467 & 0xff00) | 2468 ((temp_sata_addr_low << 24) 2469 & 0xff000000)) + 2470 pm8001_dev->attached_phy + 2471 0x10); 2472 pm8001_dbg(pm8001_ha, FAIL, 2473 "SAS Address of IO Failure Drive:%08x%08x\n", 2474 temp_sata_addr_hi, 2475 temp_sata_addr_low); 2476 2477 } else { 2478 pm8001_dbg(pm8001_ha, FAIL, 2479 "SAS Address of IO Failure Drive:%016llx\n", 2480 SAS_ADDR(t->dev->sas_addr)); 2481 } 2482 } 2483 switch (status) { 2484 case IO_SUCCESS: 2485 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2486 if (param == 0) { 2487 ts->resp = SAS_TASK_COMPLETE; 2488 ts->stat = SAM_STAT_GOOD; 2489 /* check if response is for SEND READ LOG */ 2490 if (pm8001_dev && 2491 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2492 /* set new bit for abort_all */ 2493 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2494 /* clear bit for read log */ 2495 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2496 pm80xx_send_abort_all(pm8001_ha, pm8001_dev); 2497 /* Free the tag */ 2498 pm8001_tag_free(pm8001_ha, tag); 2499 sas_free_task(t); 2500 return; 2501 } 2502 } else { 2503 u8 len; 2504 ts->resp = SAS_TASK_COMPLETE; 2505 ts->stat = SAS_PROTO_RESPONSE; 2506 ts->residual = param; 2507 pm8001_dbg(pm8001_ha, IO, 2508 "SAS_PROTO_RESPONSE len = %d\n", 2509 param); 2510 sata_resp = &psataPayload->sata_resp[0]; 2511 resp = (struct ata_task_resp *)ts->buf; 2512 if (t->ata_task.dma_xfer == 0 && 2513 t->data_dir == DMA_FROM_DEVICE) { 2514 len = sizeof(struct pio_setup_fis); 2515 pm8001_dbg(pm8001_ha, IO, 2516 "PIO read len = %d\n", len); 2517 } else if (t->ata_task.use_ncq) { 2518 len = sizeof(struct set_dev_bits_fis); 2519 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n", 2520 len); 2521 } else { 2522 len = sizeof(struct dev_to_host_fis); 2523 pm8001_dbg(pm8001_ha, IO, "other len = %d\n", 2524 len); 2525 } 2526 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2527 resp->frame_len = len; 2528 memcpy(&resp->ending_fis[0], sata_resp, len); 2529 ts->buf_valid_size = sizeof(*resp); 2530 } else 2531 pm8001_dbg(pm8001_ha, IO, 2532 "response too large\n"); 2533 } 2534 if (pm8001_dev) 2535 atomic_dec(&pm8001_dev->running_req); 2536 break; 2537 case IO_ABORTED: 2538 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 2539 ts->resp = SAS_TASK_COMPLETE; 2540 ts->stat = SAS_ABORTED_TASK; 2541 if (pm8001_dev) 2542 atomic_dec(&pm8001_dev->running_req); 2543 break; 2544 /* following cases are to do cases */ 2545 case IO_UNDERFLOW: 2546 /* SATA Completion with error */ 2547 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param); 2548 ts->resp = SAS_TASK_COMPLETE; 2549 ts->stat = SAS_DATA_UNDERRUN; 2550 ts->residual = param; 2551 if (pm8001_dev) 2552 atomic_dec(&pm8001_dev->running_req); 2553 break; 2554 case IO_NO_DEVICE: 2555 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2556 ts->resp = SAS_TASK_UNDELIVERED; 2557 ts->stat = SAS_PHY_DOWN; 2558 if (pm8001_dev) 2559 atomic_dec(&pm8001_dev->running_req); 2560 break; 2561 case IO_XFER_ERROR_BREAK: 2562 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2563 ts->resp = SAS_TASK_COMPLETE; 2564 ts->stat = SAS_INTERRUPTED; 2565 if (pm8001_dev) 2566 atomic_dec(&pm8001_dev->running_req); 2567 break; 2568 case IO_XFER_ERROR_PHY_NOT_READY: 2569 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2570 ts->resp = SAS_TASK_COMPLETE; 2571 ts->stat = SAS_OPEN_REJECT; 2572 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2573 if (pm8001_dev) 2574 atomic_dec(&pm8001_dev->running_req); 2575 break; 2576 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2577 pm8001_dbg(pm8001_ha, IO, 2578 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2579 ts->resp = SAS_TASK_COMPLETE; 2580 ts->stat = SAS_OPEN_REJECT; 2581 ts->open_rej_reason = SAS_OREJ_EPROTO; 2582 if (pm8001_dev) 2583 atomic_dec(&pm8001_dev->running_req); 2584 break; 2585 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2586 pm8001_dbg(pm8001_ha, IO, 2587 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2588 ts->resp = SAS_TASK_COMPLETE; 2589 ts->stat = SAS_OPEN_REJECT; 2590 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2591 if (pm8001_dev) 2592 atomic_dec(&pm8001_dev->running_req); 2593 break; 2594 case IO_OPEN_CNX_ERROR_BREAK: 2595 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2596 ts->resp = SAS_TASK_COMPLETE; 2597 ts->stat = SAS_OPEN_REJECT; 2598 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2599 if (pm8001_dev) 2600 atomic_dec(&pm8001_dev->running_req); 2601 break; 2602 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2603 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2604 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2605 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2606 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2607 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2608 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2609 ts->resp = SAS_TASK_COMPLETE; 2610 ts->stat = SAS_DEV_NO_RESPONSE; 2611 if (!t->uldd_task) { 2612 pm8001_handle_event(pm8001_ha, 2613 pm8001_dev, 2614 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2615 ts->resp = SAS_TASK_UNDELIVERED; 2616 ts->stat = SAS_QUEUE_FULL; 2617 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2618 return; 2619 } 2620 break; 2621 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2622 pm8001_dbg(pm8001_ha, IO, 2623 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2624 ts->resp = SAS_TASK_UNDELIVERED; 2625 ts->stat = SAS_OPEN_REJECT; 2626 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2627 if (!t->uldd_task) { 2628 pm8001_handle_event(pm8001_ha, 2629 pm8001_dev, 2630 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2631 ts->resp = SAS_TASK_UNDELIVERED; 2632 ts->stat = SAS_QUEUE_FULL; 2633 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2634 return; 2635 } 2636 break; 2637 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2638 pm8001_dbg(pm8001_ha, IO, 2639 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2640 ts->resp = SAS_TASK_COMPLETE; 2641 ts->stat = SAS_OPEN_REJECT; 2642 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2643 if (pm8001_dev) 2644 atomic_dec(&pm8001_dev->running_req); 2645 break; 2646 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2647 pm8001_dbg(pm8001_ha, IO, 2648 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"); 2649 ts->resp = SAS_TASK_COMPLETE; 2650 ts->stat = SAS_DEV_NO_RESPONSE; 2651 if (!t->uldd_task) { 2652 pm8001_handle_event(pm8001_ha, 2653 pm8001_dev, 2654 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2655 ts->resp = SAS_TASK_UNDELIVERED; 2656 ts->stat = SAS_QUEUE_FULL; 2657 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2658 return; 2659 } 2660 break; 2661 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2662 pm8001_dbg(pm8001_ha, IO, 2663 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2664 ts->resp = SAS_TASK_COMPLETE; 2665 ts->stat = SAS_OPEN_REJECT; 2666 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2667 if (pm8001_dev) 2668 atomic_dec(&pm8001_dev->running_req); 2669 break; 2670 case IO_XFER_ERROR_NAK_RECEIVED: 2671 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2672 ts->resp = SAS_TASK_COMPLETE; 2673 ts->stat = SAS_NAK_R_ERR; 2674 if (pm8001_dev) 2675 atomic_dec(&pm8001_dev->running_req); 2676 break; 2677 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2678 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2679 ts->resp = SAS_TASK_COMPLETE; 2680 ts->stat = SAS_NAK_R_ERR; 2681 if (pm8001_dev) 2682 atomic_dec(&pm8001_dev->running_req); 2683 break; 2684 case IO_XFER_ERROR_DMA: 2685 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2686 ts->resp = SAS_TASK_COMPLETE; 2687 ts->stat = SAS_ABORTED_TASK; 2688 if (pm8001_dev) 2689 atomic_dec(&pm8001_dev->running_req); 2690 break; 2691 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2692 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"); 2693 ts->resp = SAS_TASK_UNDELIVERED; 2694 ts->stat = SAS_DEV_NO_RESPONSE; 2695 if (pm8001_dev) 2696 atomic_dec(&pm8001_dev->running_req); 2697 break; 2698 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2699 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2700 ts->resp = SAS_TASK_COMPLETE; 2701 ts->stat = SAS_DATA_UNDERRUN; 2702 if (pm8001_dev) 2703 atomic_dec(&pm8001_dev->running_req); 2704 break; 2705 case IO_XFER_OPEN_RETRY_TIMEOUT: 2706 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2707 ts->resp = SAS_TASK_COMPLETE; 2708 ts->stat = SAS_OPEN_TO; 2709 if (pm8001_dev) 2710 atomic_dec(&pm8001_dev->running_req); 2711 break; 2712 case IO_PORT_IN_RESET: 2713 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2714 ts->resp = SAS_TASK_COMPLETE; 2715 ts->stat = SAS_DEV_NO_RESPONSE; 2716 if (pm8001_dev) 2717 atomic_dec(&pm8001_dev->running_req); 2718 break; 2719 case IO_DS_NON_OPERATIONAL: 2720 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2721 ts->resp = SAS_TASK_COMPLETE; 2722 ts->stat = SAS_DEV_NO_RESPONSE; 2723 if (!t->uldd_task) { 2724 pm8001_handle_event(pm8001_ha, pm8001_dev, 2725 IO_DS_NON_OPERATIONAL); 2726 ts->resp = SAS_TASK_UNDELIVERED; 2727 ts->stat = SAS_QUEUE_FULL; 2728 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2729 return; 2730 } 2731 break; 2732 case IO_DS_IN_RECOVERY: 2733 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2734 ts->resp = SAS_TASK_COMPLETE; 2735 ts->stat = SAS_DEV_NO_RESPONSE; 2736 if (pm8001_dev) 2737 atomic_dec(&pm8001_dev->running_req); 2738 break; 2739 case IO_DS_IN_ERROR: 2740 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n"); 2741 ts->resp = SAS_TASK_COMPLETE; 2742 ts->stat = SAS_DEV_NO_RESPONSE; 2743 if (!t->uldd_task) { 2744 pm8001_handle_event(pm8001_ha, pm8001_dev, 2745 IO_DS_IN_ERROR); 2746 ts->resp = SAS_TASK_UNDELIVERED; 2747 ts->stat = SAS_QUEUE_FULL; 2748 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2749 return; 2750 } 2751 break; 2752 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2753 pm8001_dbg(pm8001_ha, IO, 2754 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2755 ts->resp = SAS_TASK_COMPLETE; 2756 ts->stat = SAS_OPEN_REJECT; 2757 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2758 if (pm8001_dev) 2759 atomic_dec(&pm8001_dev->running_req); 2760 break; 2761 default: 2762 pm8001_dbg(pm8001_ha, DEVIO, 2763 "Unknown status device_id %u status 0x%x tag %d\n", 2764 pm8001_dev->device_id, status, tag); 2765 /* not allowed case. Therefore, return failed status */ 2766 ts->resp = SAS_TASK_COMPLETE; 2767 ts->stat = SAS_DEV_NO_RESPONSE; 2768 if (pm8001_dev) 2769 atomic_dec(&pm8001_dev->running_req); 2770 break; 2771 } 2772 spin_lock_irqsave(&t->task_state_lock, flags); 2773 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2774 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2775 t->task_state_flags |= SAS_TASK_STATE_DONE; 2776 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2777 spin_unlock_irqrestore(&t->task_state_lock, flags); 2778 pm8001_dbg(pm8001_ha, FAIL, 2779 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2780 t, status, ts->resp, ts->stat); 2781 if (t->slow_task) 2782 complete(&t->slow_task->completion); 2783 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2784 } else { 2785 spin_unlock_irqrestore(&t->task_state_lock, flags); 2786 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2787 } 2788 } 2789 2790 /*See the comments for mpi_ssp_completion */ 2791 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2792 { 2793 struct sas_task *t; 2794 struct task_status_struct *ts; 2795 struct pm8001_ccb_info *ccb; 2796 struct pm8001_device *pm8001_dev; 2797 struct sata_event_resp *psataPayload = 2798 (struct sata_event_resp *)(piomb + 4); 2799 u32 event = le32_to_cpu(psataPayload->event); 2800 u32 tag = le32_to_cpu(psataPayload->tag); 2801 u32 port_id = le32_to_cpu(psataPayload->port_id); 2802 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2803 unsigned long flags; 2804 2805 ccb = &pm8001_ha->ccb_info[tag]; 2806 2807 if (ccb) { 2808 t = ccb->task; 2809 pm8001_dev = ccb->device; 2810 } else { 2811 pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n"); 2812 return; 2813 } 2814 if (event) 2815 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); 2816 2817 /* Check if this is NCQ error */ 2818 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2819 /* find device using device id */ 2820 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2821 /* send read log extension */ 2822 if (pm8001_dev) 2823 pm80xx_send_read_log(pm8001_ha, pm8001_dev); 2824 return; 2825 } 2826 2827 if (unlikely(!t || !t->lldd_task || !t->dev)) { 2828 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2829 return; 2830 } 2831 2832 ts = &t->task_status; 2833 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2834 port_id, tag, event); 2835 switch (event) { 2836 case IO_OVERFLOW: 2837 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2838 ts->resp = SAS_TASK_COMPLETE; 2839 ts->stat = SAS_DATA_OVERRUN; 2840 ts->residual = 0; 2841 if (pm8001_dev) 2842 atomic_dec(&pm8001_dev->running_req); 2843 break; 2844 case IO_XFER_ERROR_BREAK: 2845 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2846 ts->resp = SAS_TASK_COMPLETE; 2847 ts->stat = SAS_INTERRUPTED; 2848 break; 2849 case IO_XFER_ERROR_PHY_NOT_READY: 2850 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2851 ts->resp = SAS_TASK_COMPLETE; 2852 ts->stat = SAS_OPEN_REJECT; 2853 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2854 break; 2855 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2856 pm8001_dbg(pm8001_ha, IO, 2857 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2858 ts->resp = SAS_TASK_COMPLETE; 2859 ts->stat = SAS_OPEN_REJECT; 2860 ts->open_rej_reason = SAS_OREJ_EPROTO; 2861 break; 2862 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2863 pm8001_dbg(pm8001_ha, IO, 2864 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2865 ts->resp = SAS_TASK_COMPLETE; 2866 ts->stat = SAS_OPEN_REJECT; 2867 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2868 break; 2869 case IO_OPEN_CNX_ERROR_BREAK: 2870 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2871 ts->resp = SAS_TASK_COMPLETE; 2872 ts->stat = SAS_OPEN_REJECT; 2873 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2874 break; 2875 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2876 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2877 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2878 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2879 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2880 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2881 pm8001_dbg(pm8001_ha, FAIL, 2882 "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2883 ts->resp = SAS_TASK_UNDELIVERED; 2884 ts->stat = SAS_DEV_NO_RESPONSE; 2885 if (!t->uldd_task) { 2886 pm8001_handle_event(pm8001_ha, 2887 pm8001_dev, 2888 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2889 ts->resp = SAS_TASK_COMPLETE; 2890 ts->stat = SAS_QUEUE_FULL; 2891 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2892 return; 2893 } 2894 break; 2895 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2896 pm8001_dbg(pm8001_ha, IO, 2897 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2898 ts->resp = SAS_TASK_UNDELIVERED; 2899 ts->stat = SAS_OPEN_REJECT; 2900 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2901 break; 2902 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2903 pm8001_dbg(pm8001_ha, IO, 2904 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2905 ts->resp = SAS_TASK_COMPLETE; 2906 ts->stat = SAS_OPEN_REJECT; 2907 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2908 break; 2909 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2910 pm8001_dbg(pm8001_ha, IO, 2911 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2912 ts->resp = SAS_TASK_COMPLETE; 2913 ts->stat = SAS_OPEN_REJECT; 2914 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2915 break; 2916 case IO_XFER_ERROR_NAK_RECEIVED: 2917 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2918 ts->resp = SAS_TASK_COMPLETE; 2919 ts->stat = SAS_NAK_R_ERR; 2920 break; 2921 case IO_XFER_ERROR_PEER_ABORTED: 2922 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n"); 2923 ts->resp = SAS_TASK_COMPLETE; 2924 ts->stat = SAS_NAK_R_ERR; 2925 break; 2926 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2927 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2928 ts->resp = SAS_TASK_COMPLETE; 2929 ts->stat = SAS_DATA_UNDERRUN; 2930 break; 2931 case IO_XFER_OPEN_RETRY_TIMEOUT: 2932 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2933 ts->resp = SAS_TASK_COMPLETE; 2934 ts->stat = SAS_OPEN_TO; 2935 break; 2936 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2937 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2938 ts->resp = SAS_TASK_COMPLETE; 2939 ts->stat = SAS_OPEN_TO; 2940 break; 2941 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2942 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2943 ts->resp = SAS_TASK_COMPLETE; 2944 ts->stat = SAS_OPEN_TO; 2945 break; 2946 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2947 pm8001_dbg(pm8001_ha, IO, 2948 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2949 ts->resp = SAS_TASK_COMPLETE; 2950 ts->stat = SAS_OPEN_TO; 2951 break; 2952 case IO_XFER_ERROR_OFFSET_MISMATCH: 2953 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2954 ts->resp = SAS_TASK_COMPLETE; 2955 ts->stat = SAS_OPEN_TO; 2956 break; 2957 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2958 pm8001_dbg(pm8001_ha, IO, 2959 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2960 ts->resp = SAS_TASK_COMPLETE; 2961 ts->stat = SAS_OPEN_TO; 2962 break; 2963 case IO_XFER_CMD_FRAME_ISSUED: 2964 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2965 break; 2966 case IO_XFER_PIO_SETUP_ERROR: 2967 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n"); 2968 ts->resp = SAS_TASK_COMPLETE; 2969 ts->stat = SAS_OPEN_TO; 2970 break; 2971 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2972 pm8001_dbg(pm8001_ha, FAIL, 2973 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2974 /* TBC: used default set values */ 2975 ts->resp = SAS_TASK_COMPLETE; 2976 ts->stat = SAS_OPEN_TO; 2977 break; 2978 case IO_XFER_DMA_ACTIVATE_TIMEOUT: 2979 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n"); 2980 /* TBC: used default set values */ 2981 ts->resp = SAS_TASK_COMPLETE; 2982 ts->stat = SAS_OPEN_TO; 2983 break; 2984 default: 2985 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event); 2986 /* not allowed case. Therefore, return failed status */ 2987 ts->resp = SAS_TASK_COMPLETE; 2988 ts->stat = SAS_OPEN_TO; 2989 break; 2990 } 2991 spin_lock_irqsave(&t->task_state_lock, flags); 2992 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2993 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2994 t->task_state_flags |= SAS_TASK_STATE_DONE; 2995 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2996 spin_unlock_irqrestore(&t->task_state_lock, flags); 2997 pm8001_dbg(pm8001_ha, FAIL, 2998 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2999 t, event, ts->resp, ts->stat); 3000 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3001 } else { 3002 spin_unlock_irqrestore(&t->task_state_lock, flags); 3003 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 3004 } 3005 } 3006 3007 /*See the comments for mpi_ssp_completion */ 3008 static void 3009 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 3010 { 3011 u32 param, i; 3012 struct sas_task *t; 3013 struct pm8001_ccb_info *ccb; 3014 unsigned long flags; 3015 u32 status; 3016 u32 tag; 3017 struct smp_completion_resp *psmpPayload; 3018 struct task_status_struct *ts; 3019 struct pm8001_device *pm8001_dev; 3020 char *pdma_respaddr = NULL; 3021 3022 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 3023 status = le32_to_cpu(psmpPayload->status); 3024 tag = le32_to_cpu(psmpPayload->tag); 3025 3026 ccb = &pm8001_ha->ccb_info[tag]; 3027 param = le32_to_cpu(psmpPayload->param); 3028 t = ccb->task; 3029 ts = &t->task_status; 3030 pm8001_dev = ccb->device; 3031 if (status) 3032 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); 3033 if (unlikely(!t || !t->lldd_task || !t->dev)) 3034 return; 3035 3036 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status); 3037 3038 switch (status) { 3039 3040 case IO_SUCCESS: 3041 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 3042 ts->resp = SAS_TASK_COMPLETE; 3043 ts->stat = SAM_STAT_GOOD; 3044 if (pm8001_dev) 3045 atomic_dec(&pm8001_dev->running_req); 3046 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 3047 pm8001_dbg(pm8001_ha, IO, 3048 "DIRECT RESPONSE Length:%d\n", 3049 param); 3050 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64 3051 ((u64)sg_dma_address 3052 (&t->smp_task.smp_resp)))); 3053 for (i = 0; i < param; i++) { 3054 *(pdma_respaddr+i) = psmpPayload->_r_a[i]; 3055 pm8001_dbg(pm8001_ha, IO, 3056 "SMP Byte%d DMA data 0x%x psmp 0x%x\n", 3057 i, *(pdma_respaddr + i), 3058 psmpPayload->_r_a[i]); 3059 } 3060 } 3061 break; 3062 case IO_ABORTED: 3063 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n"); 3064 ts->resp = SAS_TASK_COMPLETE; 3065 ts->stat = SAS_ABORTED_TASK; 3066 if (pm8001_dev) 3067 atomic_dec(&pm8001_dev->running_req); 3068 break; 3069 case IO_OVERFLOW: 3070 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 3071 ts->resp = SAS_TASK_COMPLETE; 3072 ts->stat = SAS_DATA_OVERRUN; 3073 ts->residual = 0; 3074 if (pm8001_dev) 3075 atomic_dec(&pm8001_dev->running_req); 3076 break; 3077 case IO_NO_DEVICE: 3078 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 3079 ts->resp = SAS_TASK_COMPLETE; 3080 ts->stat = SAS_PHY_DOWN; 3081 break; 3082 case IO_ERROR_HW_TIMEOUT: 3083 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n"); 3084 ts->resp = SAS_TASK_COMPLETE; 3085 ts->stat = SAM_STAT_BUSY; 3086 break; 3087 case IO_XFER_ERROR_BREAK: 3088 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 3089 ts->resp = SAS_TASK_COMPLETE; 3090 ts->stat = SAM_STAT_BUSY; 3091 break; 3092 case IO_XFER_ERROR_PHY_NOT_READY: 3093 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 3094 ts->resp = SAS_TASK_COMPLETE; 3095 ts->stat = SAM_STAT_BUSY; 3096 break; 3097 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3098 pm8001_dbg(pm8001_ha, IO, 3099 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 3100 ts->resp = SAS_TASK_COMPLETE; 3101 ts->stat = SAS_OPEN_REJECT; 3102 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3103 break; 3104 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3105 pm8001_dbg(pm8001_ha, IO, 3106 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 3107 ts->resp = SAS_TASK_COMPLETE; 3108 ts->stat = SAS_OPEN_REJECT; 3109 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3110 break; 3111 case IO_OPEN_CNX_ERROR_BREAK: 3112 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 3113 ts->resp = SAS_TASK_COMPLETE; 3114 ts->stat = SAS_OPEN_REJECT; 3115 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 3116 break; 3117 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3118 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 3119 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 3120 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 3121 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 3122 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 3123 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 3124 ts->resp = SAS_TASK_COMPLETE; 3125 ts->stat = SAS_OPEN_REJECT; 3126 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3127 pm8001_handle_event(pm8001_ha, 3128 pm8001_dev, 3129 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 3130 break; 3131 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3132 pm8001_dbg(pm8001_ha, IO, 3133 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 3134 ts->resp = SAS_TASK_COMPLETE; 3135 ts->stat = SAS_OPEN_REJECT; 3136 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 3137 break; 3138 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3139 pm8001_dbg(pm8001_ha, IO, 3140 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 3141 ts->resp = SAS_TASK_COMPLETE; 3142 ts->stat = SAS_OPEN_REJECT; 3143 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 3144 break; 3145 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3146 pm8001_dbg(pm8001_ha, IO, 3147 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 3148 ts->resp = SAS_TASK_COMPLETE; 3149 ts->stat = SAS_OPEN_REJECT; 3150 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 3151 break; 3152 case IO_XFER_ERROR_RX_FRAME: 3153 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n"); 3154 ts->resp = SAS_TASK_COMPLETE; 3155 ts->stat = SAS_DEV_NO_RESPONSE; 3156 break; 3157 case IO_XFER_OPEN_RETRY_TIMEOUT: 3158 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 3159 ts->resp = SAS_TASK_COMPLETE; 3160 ts->stat = SAS_OPEN_REJECT; 3161 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3162 break; 3163 case IO_ERROR_INTERNAL_SMP_RESOURCE: 3164 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n"); 3165 ts->resp = SAS_TASK_COMPLETE; 3166 ts->stat = SAS_QUEUE_FULL; 3167 break; 3168 case IO_PORT_IN_RESET: 3169 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 3170 ts->resp = SAS_TASK_COMPLETE; 3171 ts->stat = SAS_OPEN_REJECT; 3172 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3173 break; 3174 case IO_DS_NON_OPERATIONAL: 3175 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 3176 ts->resp = SAS_TASK_COMPLETE; 3177 ts->stat = SAS_DEV_NO_RESPONSE; 3178 break; 3179 case IO_DS_IN_RECOVERY: 3180 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 3181 ts->resp = SAS_TASK_COMPLETE; 3182 ts->stat = SAS_OPEN_REJECT; 3183 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3184 break; 3185 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3186 pm8001_dbg(pm8001_ha, IO, 3187 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 3188 ts->resp = SAS_TASK_COMPLETE; 3189 ts->stat = SAS_OPEN_REJECT; 3190 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3191 break; 3192 default: 3193 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 3194 ts->resp = SAS_TASK_COMPLETE; 3195 ts->stat = SAS_DEV_NO_RESPONSE; 3196 /* not allowed case. Therefore, return failed status */ 3197 break; 3198 } 3199 spin_lock_irqsave(&t->task_state_lock, flags); 3200 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3201 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3202 t->task_state_flags |= SAS_TASK_STATE_DONE; 3203 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3204 spin_unlock_irqrestore(&t->task_state_lock, flags); 3205 pm8001_dbg(pm8001_ha, FAIL, 3206 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n", 3207 t, status, ts->resp, ts->stat); 3208 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3209 } else { 3210 spin_unlock_irqrestore(&t->task_state_lock, flags); 3211 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3212 mb();/* in order to force CPU ordering */ 3213 t->task_done(t); 3214 } 3215 } 3216 3217 /** 3218 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3219 * @pm8001_ha: our hba card information 3220 * @Qnum: the outbound queue message number. 3221 * @SEA: source of event to ack 3222 * @port_id: port id. 3223 * @phyId: phy id. 3224 * @param0: parameter 0. 3225 * @param1: parameter 1. 3226 */ 3227 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3228 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3229 { 3230 struct hw_event_ack_req payload; 3231 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3232 3233 struct inbound_queue_table *circularQ; 3234 3235 memset((u8 *)&payload, 0, sizeof(payload)); 3236 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 3237 payload.tag = cpu_to_le32(1); 3238 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3239 ((phyId & 0xFF) << 24) | (port_id & 0xFF)); 3240 payload.param0 = cpu_to_le32(param0); 3241 payload.param1 = cpu_to_le32(param1); 3242 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 3243 sizeof(payload), 0); 3244 } 3245 3246 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3247 u32 phyId, u32 phy_op); 3248 3249 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha, 3250 void *piomb) 3251 { 3252 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4); 3253 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3254 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3255 u32 lr_status_evt_portid = 3256 le32_to_cpu(pPayload->lr_status_evt_portid); 3257 u8 deviceType = pPayload->sas_identify.dev_type; 3258 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3259 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3260 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3261 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3262 3263 if (deviceType == SAS_END_DEVICE) { 3264 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3265 PHY_NOTIFY_ENABLE_SPINUP); 3266 } 3267 3268 port->wide_port_phymap |= (1U << phy_id); 3269 pm8001_get_lrate_mode(phy, link_rate); 3270 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3271 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3272 phy->phy_attached = 1; 3273 } 3274 3275 /** 3276 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3277 * @pm8001_ha: our hba card information 3278 * @piomb: IO message buffer 3279 */ 3280 static void 3281 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3282 { 3283 struct hw_event_resp *pPayload = 3284 (struct hw_event_resp *)(piomb + 4); 3285 u32 lr_status_evt_portid = 3286 le32_to_cpu(pPayload->lr_status_evt_portid); 3287 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3288 3289 u8 link_rate = 3290 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3291 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3292 u8 phy_id = 3293 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3294 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3295 3296 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3297 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3298 unsigned long flags; 3299 u8 deviceType = pPayload->sas_identify.dev_type; 3300 port->port_state = portstate; 3301 port->wide_port_phymap |= (1U << phy_id); 3302 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3303 pm8001_dbg(pm8001_ha, MSG, 3304 "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n", 3305 port_id, phy_id, link_rate, portstate, deviceType); 3306 3307 switch (deviceType) { 3308 case SAS_PHY_UNUSED: 3309 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n"); 3310 break; 3311 case SAS_END_DEVICE: 3312 pm8001_dbg(pm8001_ha, MSG, "end device.\n"); 3313 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3314 PHY_NOTIFY_ENABLE_SPINUP); 3315 port->port_attached = 1; 3316 pm8001_get_lrate_mode(phy, link_rate); 3317 break; 3318 case SAS_EDGE_EXPANDER_DEVICE: 3319 pm8001_dbg(pm8001_ha, MSG, "expander device.\n"); 3320 port->port_attached = 1; 3321 pm8001_get_lrate_mode(phy, link_rate); 3322 break; 3323 case SAS_FANOUT_EXPANDER_DEVICE: 3324 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n"); 3325 port->port_attached = 1; 3326 pm8001_get_lrate_mode(phy, link_rate); 3327 break; 3328 default: 3329 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n", 3330 deviceType); 3331 break; 3332 } 3333 phy->phy_type |= PORT_TYPE_SAS; 3334 phy->identify.device_type = deviceType; 3335 phy->phy_attached = 1; 3336 if (phy->identify.device_type == SAS_END_DEVICE) 3337 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3338 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3339 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3340 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3341 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3342 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3343 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3344 sizeof(struct sas_identify_frame)-4); 3345 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3346 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3347 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3348 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3349 mdelay(200); /* delay a moment to wait for disk to spin up */ 3350 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3351 } 3352 3353 /** 3354 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3355 * @pm8001_ha: our hba card information 3356 * @piomb: IO message buffer 3357 */ 3358 static void 3359 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3360 { 3361 struct hw_event_resp *pPayload = 3362 (struct hw_event_resp *)(piomb + 4); 3363 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3364 u32 lr_status_evt_portid = 3365 le32_to_cpu(pPayload->lr_status_evt_portid); 3366 u8 link_rate = 3367 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3368 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3369 u8 phy_id = 3370 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3371 3372 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3373 3374 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3375 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3376 unsigned long flags; 3377 pm8001_dbg(pm8001_ha, DEVIO, 3378 "port id %d, phy id %d link_rate %d portstate 0x%x\n", 3379 port_id, phy_id, link_rate, portstate); 3380 3381 port->port_state = portstate; 3382 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3383 port->port_attached = 1; 3384 pm8001_get_lrate_mode(phy, link_rate); 3385 phy->phy_type |= PORT_TYPE_SATA; 3386 phy->phy_attached = 1; 3387 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3388 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3389 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3390 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3391 sizeof(struct dev_to_host_fis)); 3392 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3393 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3394 phy->identify.device_type = SAS_SATA_DEV; 3395 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3396 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3397 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3398 } 3399 3400 /** 3401 * hw_event_phy_down -we should notify the libsas the phy is down. 3402 * @pm8001_ha: our hba card information 3403 * @piomb: IO message buffer 3404 */ 3405 static void 3406 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3407 { 3408 struct hw_event_resp *pPayload = 3409 (struct hw_event_resp *)(piomb + 4); 3410 3411 u32 lr_status_evt_portid = 3412 le32_to_cpu(pPayload->lr_status_evt_portid); 3413 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3414 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3415 u8 phy_id = 3416 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3417 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3418 3419 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3420 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3421 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA); 3422 port->port_state = portstate; 3423 phy->identify.device_type = 0; 3424 phy->phy_attached = 0; 3425 switch (portstate) { 3426 case PORT_VALID: 3427 break; 3428 case PORT_INVALID: 3429 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n", 3430 port_id); 3431 pm8001_dbg(pm8001_ha, MSG, 3432 " Last phy Down and port invalid\n"); 3433 if (port_sata) { 3434 phy->phy_type = 0; 3435 port->port_attached = 0; 3436 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3437 port_id, phy_id, 0, 0); 3438 } 3439 sas_phy_disconnected(&phy->sas_phy); 3440 break; 3441 case PORT_IN_RESET: 3442 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n", 3443 port_id); 3444 break; 3445 case PORT_NOT_ESTABLISHED: 3446 pm8001_dbg(pm8001_ha, MSG, 3447 " Phy Down and PORT_NOT_ESTABLISHED\n"); 3448 port->port_attached = 0; 3449 break; 3450 case PORT_LOSTCOMM: 3451 pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n"); 3452 pm8001_dbg(pm8001_ha, MSG, 3453 " Last phy Down and port invalid\n"); 3454 if (port_sata) { 3455 port->port_attached = 0; 3456 phy->phy_type = 0; 3457 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3458 port_id, phy_id, 0, 0); 3459 } 3460 sas_phy_disconnected(&phy->sas_phy); 3461 break; 3462 default: 3463 port->port_attached = 0; 3464 pm8001_dbg(pm8001_ha, DEVIO, 3465 " Phy Down and(default) = 0x%x\n", 3466 portstate); 3467 break; 3468 3469 } 3470 if (port_sata && (portstate != PORT_IN_RESET)) 3471 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL, 3472 GFP_ATOMIC); 3473 } 3474 3475 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3476 { 3477 struct phy_start_resp *pPayload = 3478 (struct phy_start_resp *)(piomb + 4); 3479 u32 status = 3480 le32_to_cpu(pPayload->status); 3481 u32 phy_id = 3482 le32_to_cpu(pPayload->phyid); 3483 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3484 3485 pm8001_dbg(pm8001_ha, INIT, 3486 "phy start resp status:0x%x, phyid:0x%x\n", 3487 status, phy_id); 3488 if (status == 0) { 3489 phy->phy_state = PHY_LINK_DOWN; 3490 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3491 phy->enable_completion != NULL) { 3492 complete(phy->enable_completion); 3493 phy->enable_completion = NULL; 3494 } 3495 } 3496 return 0; 3497 3498 } 3499 3500 /** 3501 * mpi_thermal_hw_event -The hw event has come. 3502 * @pm8001_ha: our hba card information 3503 * @piomb: IO message buffer 3504 */ 3505 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3506 { 3507 struct thermal_hw_event *pPayload = 3508 (struct thermal_hw_event *)(piomb + 4); 3509 3510 u32 thermal_event = le32_to_cpu(pPayload->thermal_event); 3511 u32 rht_lht = le32_to_cpu(pPayload->rht_lht); 3512 3513 if (thermal_event & 0x40) { 3514 pm8001_dbg(pm8001_ha, IO, 3515 "Thermal Event: Local high temperature violated!\n"); 3516 pm8001_dbg(pm8001_ha, IO, 3517 "Thermal Event: Measured local high temperature %d\n", 3518 ((rht_lht & 0xFF00) >> 8)); 3519 } 3520 if (thermal_event & 0x10) { 3521 pm8001_dbg(pm8001_ha, IO, 3522 "Thermal Event: Remote high temperature violated!\n"); 3523 pm8001_dbg(pm8001_ha, IO, 3524 "Thermal Event: Measured remote high temperature %d\n", 3525 ((rht_lht & 0xFF000000) >> 24)); 3526 } 3527 return 0; 3528 } 3529 3530 /** 3531 * mpi_hw_event -The hw event has come. 3532 * @pm8001_ha: our hba card information 3533 * @piomb: IO message buffer 3534 */ 3535 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3536 { 3537 unsigned long flags, i; 3538 struct hw_event_resp *pPayload = 3539 (struct hw_event_resp *)(piomb + 4); 3540 u32 lr_status_evt_portid = 3541 le32_to_cpu(pPayload->lr_status_evt_portid); 3542 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3543 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3544 u8 phy_id = 3545 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3546 u16 eventType = 3547 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); 3548 u8 status = 3549 (u8)((lr_status_evt_portid & 0x0F000000) >> 24); 3550 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3551 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3552 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3553 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3554 pm8001_dbg(pm8001_ha, DEV, 3555 "portid:%d phyid:%d event:0x%x status:0x%x\n", 3556 port_id, phy_id, eventType, status); 3557 3558 switch (eventType) { 3559 3560 case HW_EVENT_SAS_PHY_UP: 3561 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n"); 3562 hw_event_sas_phy_up(pm8001_ha, piomb); 3563 break; 3564 case HW_EVENT_SATA_PHY_UP: 3565 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n"); 3566 hw_event_sata_phy_up(pm8001_ha, piomb); 3567 break; 3568 case HW_EVENT_SATA_SPINUP_HOLD: 3569 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n"); 3570 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD, 3571 GFP_ATOMIC); 3572 break; 3573 case HW_EVENT_PHY_DOWN: 3574 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n"); 3575 hw_event_phy_down(pm8001_ha, piomb); 3576 if (pm8001_ha->reset_in_progress) { 3577 pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n"); 3578 return 0; 3579 } 3580 phy->phy_attached = 0; 3581 phy->phy_state = PHY_LINK_DISABLE; 3582 break; 3583 case HW_EVENT_PORT_INVALID: 3584 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n"); 3585 sas_phy_disconnected(sas_phy); 3586 phy->phy_attached = 0; 3587 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3588 GFP_ATOMIC); 3589 break; 3590 /* the broadcast change primitive received, tell the LIBSAS this event 3591 to revalidate the sas domain*/ 3592 case HW_EVENT_BROADCAST_CHANGE: 3593 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n"); 3594 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3595 port_id, phy_id, 1, 0); 3596 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3597 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3598 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3599 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3600 GFP_ATOMIC); 3601 break; 3602 case HW_EVENT_PHY_ERROR: 3603 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n"); 3604 sas_phy_disconnected(&phy->sas_phy); 3605 phy->phy_attached = 0; 3606 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC); 3607 break; 3608 case HW_EVENT_BROADCAST_EXP: 3609 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n"); 3610 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3611 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3612 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3613 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3614 GFP_ATOMIC); 3615 break; 3616 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3617 pm8001_dbg(pm8001_ha, MSG, 3618 "HW_EVENT_LINK_ERR_INVALID_DWORD\n"); 3619 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3620 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3621 break; 3622 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3623 pm8001_dbg(pm8001_ha, MSG, 3624 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"); 3625 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3626 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3627 port_id, phy_id, 0, 0); 3628 break; 3629 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3630 pm8001_dbg(pm8001_ha, MSG, 3631 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n"); 3632 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3633 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3634 port_id, phy_id, 0, 0); 3635 break; 3636 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3637 pm8001_dbg(pm8001_ha, MSG, 3638 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"); 3639 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3640 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3641 port_id, phy_id, 0, 0); 3642 break; 3643 case HW_EVENT_MALFUNCTION: 3644 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n"); 3645 break; 3646 case HW_EVENT_BROADCAST_SES: 3647 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n"); 3648 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3649 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3650 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3651 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3652 GFP_ATOMIC); 3653 break; 3654 case HW_EVENT_INBOUND_CRC_ERROR: 3655 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n"); 3656 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3657 HW_EVENT_INBOUND_CRC_ERROR, 3658 port_id, phy_id, 0, 0); 3659 break; 3660 case HW_EVENT_HARD_RESET_RECEIVED: 3661 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n"); 3662 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC); 3663 break; 3664 case HW_EVENT_ID_FRAME_TIMEOUT: 3665 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n"); 3666 sas_phy_disconnected(sas_phy); 3667 phy->phy_attached = 0; 3668 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3669 GFP_ATOMIC); 3670 break; 3671 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3672 pm8001_dbg(pm8001_ha, MSG, 3673 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"); 3674 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3675 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3676 port_id, phy_id, 0, 0); 3677 sas_phy_disconnected(sas_phy); 3678 phy->phy_attached = 0; 3679 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3680 GFP_ATOMIC); 3681 break; 3682 case HW_EVENT_PORT_RESET_TIMER_TMO: 3683 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n"); 3684 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3685 port_id, phy_id, 0, 0); 3686 sas_phy_disconnected(sas_phy); 3687 phy->phy_attached = 0; 3688 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3689 GFP_ATOMIC); 3690 if (pm8001_ha->phy[phy_id].reset_completion) { 3691 pm8001_ha->phy[phy_id].port_reset_status = 3692 PORT_RESET_TMO; 3693 complete(pm8001_ha->phy[phy_id].reset_completion); 3694 pm8001_ha->phy[phy_id].reset_completion = NULL; 3695 } 3696 break; 3697 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3698 pm8001_dbg(pm8001_ha, MSG, 3699 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"); 3700 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3701 HW_EVENT_PORT_RECOVERY_TIMER_TMO, 3702 port_id, phy_id, 0, 0); 3703 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 3704 if (port->wide_port_phymap & (1 << i)) { 3705 phy = &pm8001_ha->phy[i]; 3706 sas_notify_phy_event(&phy->sas_phy, 3707 PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC); 3708 port->wide_port_phymap &= ~(1 << i); 3709 } 3710 } 3711 break; 3712 case HW_EVENT_PORT_RECOVER: 3713 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n"); 3714 hw_event_port_recover(pm8001_ha, piomb); 3715 break; 3716 case HW_EVENT_PORT_RESET_COMPLETE: 3717 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n"); 3718 if (pm8001_ha->phy[phy_id].reset_completion) { 3719 pm8001_ha->phy[phy_id].port_reset_status = 3720 PORT_RESET_SUCCESS; 3721 complete(pm8001_ha->phy[phy_id].reset_completion); 3722 pm8001_ha->phy[phy_id].reset_completion = NULL; 3723 } 3724 break; 3725 case EVENT_BROADCAST_ASYNCH_EVENT: 3726 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n"); 3727 break; 3728 default: 3729 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n", 3730 eventType); 3731 break; 3732 } 3733 return 0; 3734 } 3735 3736 /** 3737 * mpi_phy_stop_resp - SPCv specific 3738 * @pm8001_ha: our hba card information 3739 * @piomb: IO message buffer 3740 */ 3741 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3742 { 3743 struct phy_stop_resp *pPayload = 3744 (struct phy_stop_resp *)(piomb + 4); 3745 u32 status = 3746 le32_to_cpu(pPayload->status); 3747 u32 phyid = 3748 le32_to_cpu(pPayload->phyid) & 0xFF; 3749 struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; 3750 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n", 3751 phyid, status); 3752 if (status == PHY_STOP_SUCCESS || 3753 status == PHY_STOP_ERR_DEVICE_ATTACHED) 3754 phy->phy_state = PHY_LINK_DISABLE; 3755 return 0; 3756 } 3757 3758 /** 3759 * mpi_set_controller_config_resp - SPCv specific 3760 * @pm8001_ha: our hba card information 3761 * @piomb: IO message buffer 3762 */ 3763 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3764 void *piomb) 3765 { 3766 struct set_ctrl_cfg_resp *pPayload = 3767 (struct set_ctrl_cfg_resp *)(piomb + 4); 3768 u32 status = le32_to_cpu(pPayload->status); 3769 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); 3770 3771 pm8001_dbg(pm8001_ha, MSG, 3772 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", 3773 status, err_qlfr_pgcd); 3774 3775 return 0; 3776 } 3777 3778 /** 3779 * mpi_get_controller_config_resp - SPCv specific 3780 * @pm8001_ha: our hba card information 3781 * @piomb: IO message buffer 3782 */ 3783 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3784 void *piomb) 3785 { 3786 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3787 3788 return 0; 3789 } 3790 3791 /** 3792 * mpi_get_phy_profile_resp - SPCv specific 3793 * @pm8001_ha: our hba card information 3794 * @piomb: IO message buffer 3795 */ 3796 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3797 void *piomb) 3798 { 3799 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3800 3801 return 0; 3802 } 3803 3804 /** 3805 * mpi_flash_op_ext_resp - SPCv specific 3806 * @pm8001_ha: our hba card information 3807 * @piomb: IO message buffer 3808 */ 3809 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3810 { 3811 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3812 3813 return 0; 3814 } 3815 3816 /** 3817 * mpi_set_phy_profile_resp - SPCv specific 3818 * @pm8001_ha: our hba card information 3819 * @piomb: IO message buffer 3820 */ 3821 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3822 void *piomb) 3823 { 3824 u32 tag; 3825 u8 page_code; 3826 int rc = 0; 3827 struct set_phy_profile_resp *pPayload = 3828 (struct set_phy_profile_resp *)(piomb + 4); 3829 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); 3830 u32 status = le32_to_cpu(pPayload->status); 3831 3832 tag = le32_to_cpu(pPayload->tag); 3833 page_code = (u8)((ppc_phyid & 0xFF00) >> 8); 3834 if (status) { 3835 /* status is FAILED */ 3836 pm8001_dbg(pm8001_ha, FAIL, 3837 "PhyProfile command failed with status 0x%08X\n", 3838 status); 3839 rc = -1; 3840 } else { 3841 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) { 3842 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n", 3843 page_code); 3844 rc = -1; 3845 } 3846 } 3847 pm8001_tag_free(pm8001_ha, tag); 3848 return rc; 3849 } 3850 3851 /** 3852 * mpi_kek_management_resp - SPCv specific 3853 * @pm8001_ha: our hba card information 3854 * @piomb: IO message buffer 3855 */ 3856 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, 3857 void *piomb) 3858 { 3859 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); 3860 3861 u32 status = le32_to_cpu(pPayload->status); 3862 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); 3863 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); 3864 3865 pm8001_dbg(pm8001_ha, MSG, 3866 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", 3867 status, kidx_new_curr_ksop, err_qlfr); 3868 3869 return 0; 3870 } 3871 3872 /** 3873 * mpi_dek_management_resp - SPCv specific 3874 * @pm8001_ha: our hba card information 3875 * @piomb: IO message buffer 3876 */ 3877 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, 3878 void *piomb) 3879 { 3880 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3881 3882 return 0; 3883 } 3884 3885 /** 3886 * ssp_coalesced_comp_resp - SPCv specific 3887 * @pm8001_ha: our hba card information 3888 * @piomb: IO message buffer 3889 */ 3890 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, 3891 void *piomb) 3892 { 3893 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3894 3895 return 0; 3896 } 3897 3898 /** 3899 * process_one_iomb - process one outbound Queue memory block 3900 * @pm8001_ha: our hba card information 3901 * @piomb: IO message buffer 3902 */ 3903 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3904 { 3905 __le32 pHeader = *(__le32 *)piomb; 3906 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); 3907 3908 switch (opc) { 3909 case OPC_OUB_ECHO: 3910 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n"); 3911 break; 3912 case OPC_OUB_HW_EVENT: 3913 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n"); 3914 mpi_hw_event(pm8001_ha, piomb); 3915 break; 3916 case OPC_OUB_THERM_HW_EVENT: 3917 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n"); 3918 mpi_thermal_hw_event(pm8001_ha, piomb); 3919 break; 3920 case OPC_OUB_SSP_COMP: 3921 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n"); 3922 mpi_ssp_completion(pm8001_ha, piomb); 3923 break; 3924 case OPC_OUB_SMP_COMP: 3925 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n"); 3926 mpi_smp_completion(pm8001_ha, piomb); 3927 break; 3928 case OPC_OUB_LOCAL_PHY_CNTRL: 3929 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n"); 3930 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3931 break; 3932 case OPC_OUB_DEV_REGIST: 3933 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n"); 3934 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3935 break; 3936 case OPC_OUB_DEREG_DEV: 3937 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n"); 3938 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3939 break; 3940 case OPC_OUB_GET_DEV_HANDLE: 3941 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n"); 3942 break; 3943 case OPC_OUB_SATA_COMP: 3944 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n"); 3945 mpi_sata_completion(pm8001_ha, piomb); 3946 break; 3947 case OPC_OUB_SATA_EVENT: 3948 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n"); 3949 mpi_sata_event(pm8001_ha, piomb); 3950 break; 3951 case OPC_OUB_SSP_EVENT: 3952 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n"); 3953 mpi_ssp_event(pm8001_ha, piomb); 3954 break; 3955 case OPC_OUB_DEV_HANDLE_ARRIV: 3956 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n"); 3957 /*This is for target*/ 3958 break; 3959 case OPC_OUB_SSP_RECV_EVENT: 3960 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n"); 3961 /*This is for target*/ 3962 break; 3963 case OPC_OUB_FW_FLASH_UPDATE: 3964 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n"); 3965 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3966 break; 3967 case OPC_OUB_GPIO_RESPONSE: 3968 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n"); 3969 break; 3970 case OPC_OUB_GPIO_EVENT: 3971 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n"); 3972 break; 3973 case OPC_OUB_GENERAL_EVENT: 3974 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n"); 3975 pm8001_mpi_general_event(pm8001_ha, piomb); 3976 break; 3977 case OPC_OUB_SSP_ABORT_RSP: 3978 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n"); 3979 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3980 break; 3981 case OPC_OUB_SATA_ABORT_RSP: 3982 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n"); 3983 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3984 break; 3985 case OPC_OUB_SAS_DIAG_MODE_START_END: 3986 pm8001_dbg(pm8001_ha, MSG, 3987 "OPC_OUB_SAS_DIAG_MODE_START_END\n"); 3988 break; 3989 case OPC_OUB_SAS_DIAG_EXECUTE: 3990 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n"); 3991 break; 3992 case OPC_OUB_GET_TIME_STAMP: 3993 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n"); 3994 break; 3995 case OPC_OUB_SAS_HW_EVENT_ACK: 3996 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n"); 3997 break; 3998 case OPC_OUB_PORT_CONTROL: 3999 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n"); 4000 break; 4001 case OPC_OUB_SMP_ABORT_RSP: 4002 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n"); 4003 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4004 break; 4005 case OPC_OUB_GET_NVMD_DATA: 4006 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n"); 4007 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 4008 break; 4009 case OPC_OUB_SET_NVMD_DATA: 4010 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n"); 4011 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 4012 break; 4013 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 4014 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n"); 4015 break; 4016 case OPC_OUB_SET_DEVICE_STATE: 4017 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n"); 4018 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 4019 break; 4020 case OPC_OUB_GET_DEVICE_STATE: 4021 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n"); 4022 break; 4023 case OPC_OUB_SET_DEV_INFO: 4024 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n"); 4025 break; 4026 /* spcv specifc commands */ 4027 case OPC_OUB_PHY_START_RESP: 4028 pm8001_dbg(pm8001_ha, MSG, 4029 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc); 4030 mpi_phy_start_resp(pm8001_ha, piomb); 4031 break; 4032 case OPC_OUB_PHY_STOP_RESP: 4033 pm8001_dbg(pm8001_ha, MSG, 4034 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc); 4035 mpi_phy_stop_resp(pm8001_ha, piomb); 4036 break; 4037 case OPC_OUB_SET_CONTROLLER_CONFIG: 4038 pm8001_dbg(pm8001_ha, MSG, 4039 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc); 4040 mpi_set_controller_config_resp(pm8001_ha, piomb); 4041 break; 4042 case OPC_OUB_GET_CONTROLLER_CONFIG: 4043 pm8001_dbg(pm8001_ha, MSG, 4044 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc); 4045 mpi_get_controller_config_resp(pm8001_ha, piomb); 4046 break; 4047 case OPC_OUB_GET_PHY_PROFILE: 4048 pm8001_dbg(pm8001_ha, MSG, 4049 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc); 4050 mpi_get_phy_profile_resp(pm8001_ha, piomb); 4051 break; 4052 case OPC_OUB_FLASH_OP_EXT: 4053 pm8001_dbg(pm8001_ha, MSG, 4054 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc); 4055 mpi_flash_op_ext_resp(pm8001_ha, piomb); 4056 break; 4057 case OPC_OUB_SET_PHY_PROFILE: 4058 pm8001_dbg(pm8001_ha, MSG, 4059 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc); 4060 mpi_set_phy_profile_resp(pm8001_ha, piomb); 4061 break; 4062 case OPC_OUB_KEK_MANAGEMENT_RESP: 4063 pm8001_dbg(pm8001_ha, MSG, 4064 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc); 4065 mpi_kek_management_resp(pm8001_ha, piomb); 4066 break; 4067 case OPC_OUB_DEK_MANAGEMENT_RESP: 4068 pm8001_dbg(pm8001_ha, MSG, 4069 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc); 4070 mpi_dek_management_resp(pm8001_ha, piomb); 4071 break; 4072 case OPC_OUB_SSP_COALESCED_COMP_RESP: 4073 pm8001_dbg(pm8001_ha, MSG, 4074 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc); 4075 ssp_coalesced_comp_resp(pm8001_ha, piomb); 4076 break; 4077 default: 4078 pm8001_dbg(pm8001_ha, DEVIO, 4079 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc); 4080 break; 4081 } 4082 } 4083 4084 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha) 4085 { 4086 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n", 4087 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); 4088 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n", 4089 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)); 4090 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n", 4091 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)); 4092 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n", 4093 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); 4094 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n", 4095 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)); 4096 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n", 4097 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)); 4098 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n", 4099 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)); 4100 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n", 4101 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)); 4102 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n", 4103 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)); 4104 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n", 4105 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)); 4106 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n", 4107 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)); 4108 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n", 4109 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)); 4110 } 4111 4112 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4113 { 4114 struct outbound_queue_table *circularQ; 4115 void *pMsg1 = NULL; 4116 u8 bc; 4117 u32 ret = MPI_IO_STATUS_FAIL; 4118 unsigned long flags; 4119 u32 regval; 4120 4121 if (vec == (pm8001_ha->max_q_num - 1)) { 4122 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 4123 if ((regval & SCRATCH_PAD_MIPSALL_READY) != 4124 SCRATCH_PAD_MIPSALL_READY) { 4125 pm8001_ha->controller_fatal_error = true; 4126 pm8001_dbg(pm8001_ha, FAIL, 4127 "Firmware Fatal error! Regval:0x%x\n", 4128 regval); 4129 print_scratchpad_registers(pm8001_ha); 4130 return ret; 4131 } 4132 } 4133 spin_lock_irqsave(&pm8001_ha->lock, flags); 4134 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4135 do { 4136 /* spurious interrupt during setup if kexec-ing and 4137 * driver doing a doorbell access w/ the pre-kexec oq 4138 * interrupt setup. 4139 */ 4140 if (!circularQ->pi_virt) 4141 break; 4142 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4143 if (MPI_IO_STATUS_SUCCESS == ret) { 4144 /* process the outbound message */ 4145 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 4146 /* free the message from the outbound circular buffer */ 4147 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4148 circularQ, bc); 4149 } 4150 if (MPI_IO_STATUS_BUSY == ret) { 4151 /* Update the producer index from SPC */ 4152 circularQ->producer_index = 4153 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4154 if (le32_to_cpu(circularQ->producer_index) == 4155 circularQ->consumer_idx) 4156 /* OQ is empty */ 4157 break; 4158 } 4159 } while (1); 4160 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 4161 return ret; 4162 } 4163 4164 /* DMA_... to our direction translation. */ 4165 static const u8 data_dir_flags[] = { 4166 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4167 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4168 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4169 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4170 }; 4171 4172 static void build_smp_cmd(u32 deviceID, __le32 hTag, 4173 struct smp_req *psmp_cmd, int mode, int length) 4174 { 4175 psmp_cmd->tag = hTag; 4176 psmp_cmd->device_id = cpu_to_le32(deviceID); 4177 if (mode == SMP_DIRECT) { 4178 length = length - 4; /* subtract crc */ 4179 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); 4180 } else { 4181 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4182 } 4183 } 4184 4185 /** 4186 * pm8001_chip_smp_req - send a SMP task to FW 4187 * @pm8001_ha: our hba card information. 4188 * @ccb: the ccb information this request used. 4189 */ 4190 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4191 struct pm8001_ccb_info *ccb) 4192 { 4193 int elem, rc; 4194 struct sas_task *task = ccb->task; 4195 struct domain_device *dev = task->dev; 4196 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4197 struct scatterlist *sg_req, *sg_resp; 4198 u32 req_len, resp_len; 4199 struct smp_req smp_cmd; 4200 u32 opc; 4201 struct inbound_queue_table *circularQ; 4202 char *preq_dma_addr = NULL; 4203 __le64 tmp_addr; 4204 u32 i, length; 4205 4206 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4207 /* 4208 * DMA-map SMP request, response buffers 4209 */ 4210 sg_req = &task->smp_task.smp_req; 4211 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4212 if (!elem) 4213 return -ENOMEM; 4214 req_len = sg_dma_len(sg_req); 4215 4216 sg_resp = &task->smp_task.smp_resp; 4217 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4218 if (!elem) { 4219 rc = -ENOMEM; 4220 goto err_out; 4221 } 4222 resp_len = sg_dma_len(sg_resp); 4223 /* must be in dwords */ 4224 if ((req_len & 0x3) || (resp_len & 0x3)) { 4225 rc = -EINVAL; 4226 goto err_out_2; 4227 } 4228 4229 opc = OPC_INB_SMP_REQUEST; 4230 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4231 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4232 4233 length = sg_req->length; 4234 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length); 4235 if (!(length - 8)) 4236 pm8001_ha->smp_exp_mode = SMP_DIRECT; 4237 else 4238 pm8001_ha->smp_exp_mode = SMP_INDIRECT; 4239 4240 4241 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 4242 preq_dma_addr = (char *)phys_to_virt(tmp_addr); 4243 4244 /* INDIRECT MODE command settings. Use DMA */ 4245 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { 4246 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n"); 4247 /* for SPCv indirect mode. Place the top 4 bytes of 4248 * SMP Request header here. */ 4249 for (i = 0; i < 4; i++) 4250 smp_cmd.smp_req16[i] = *(preq_dma_addr + i); 4251 /* exclude top 4 bytes for SMP req header */ 4252 smp_cmd.long_smp_req.long_req_addr = 4253 cpu_to_le64((u64)sg_dma_address 4254 (&task->smp_task.smp_req) + 4); 4255 /* exclude 4 bytes for SMP req header and CRC */ 4256 smp_cmd.long_smp_req.long_req_size = 4257 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); 4258 smp_cmd.long_smp_req.long_resp_addr = 4259 cpu_to_le64((u64)sg_dma_address 4260 (&task->smp_task.smp_resp)); 4261 smp_cmd.long_smp_req.long_resp_size = 4262 cpu_to_le32((u32)sg_dma_len 4263 (&task->smp_task.smp_resp)-4); 4264 } else { /* DIRECT MODE */ 4265 smp_cmd.long_smp_req.long_req_addr = 4266 cpu_to_le64((u64)sg_dma_address 4267 (&task->smp_task.smp_req)); 4268 smp_cmd.long_smp_req.long_req_size = 4269 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4270 smp_cmd.long_smp_req.long_resp_addr = 4271 cpu_to_le64((u64)sg_dma_address 4272 (&task->smp_task.smp_resp)); 4273 smp_cmd.long_smp_req.long_resp_size = 4274 cpu_to_le32 4275 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4276 } 4277 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 4278 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n"); 4279 for (i = 0; i < length; i++) 4280 if (i < 16) { 4281 smp_cmd.smp_req16[i] = *(preq_dma_addr+i); 4282 pm8001_dbg(pm8001_ha, IO, 4283 "Byte[%d]:%x (DMA data:%x)\n", 4284 i, smp_cmd.smp_req16[i], 4285 *(preq_dma_addr)); 4286 } else { 4287 smp_cmd.smp_req[i] = *(preq_dma_addr+i); 4288 pm8001_dbg(pm8001_ha, IO, 4289 "Byte[%d]:%x (DMA data:%x)\n", 4290 i, smp_cmd.smp_req[i], 4291 *(preq_dma_addr)); 4292 } 4293 } 4294 4295 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, 4296 &smp_cmd, pm8001_ha->smp_exp_mode, length); 4297 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd, 4298 sizeof(smp_cmd), 0); 4299 if (rc) 4300 goto err_out_2; 4301 return 0; 4302 4303 err_out_2: 4304 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4305 DMA_FROM_DEVICE); 4306 err_out: 4307 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4308 DMA_TO_DEVICE); 4309 return rc; 4310 } 4311 4312 static int check_enc_sas_cmd(struct sas_task *task) 4313 { 4314 u8 cmd = task->ssp_task.cmd->cmnd[0]; 4315 4316 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) 4317 return 1; 4318 else 4319 return 0; 4320 } 4321 4322 static int check_enc_sat_cmd(struct sas_task *task) 4323 { 4324 int ret = 0; 4325 switch (task->ata_task.fis.command) { 4326 case ATA_CMD_FPDMA_READ: 4327 case ATA_CMD_READ_EXT: 4328 case ATA_CMD_READ: 4329 case ATA_CMD_FPDMA_WRITE: 4330 case ATA_CMD_WRITE_EXT: 4331 case ATA_CMD_WRITE: 4332 case ATA_CMD_PIO_READ: 4333 case ATA_CMD_PIO_READ_EXT: 4334 case ATA_CMD_PIO_WRITE: 4335 case ATA_CMD_PIO_WRITE_EXT: 4336 ret = 1; 4337 break; 4338 default: 4339 ret = 0; 4340 break; 4341 } 4342 return ret; 4343 } 4344 4345 /** 4346 * pm80xx_chip_ssp_io_req - send a SSP task to FW 4347 * @pm8001_ha: our hba card information. 4348 * @ccb: the ccb information this request used. 4349 */ 4350 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4351 struct pm8001_ccb_info *ccb) 4352 { 4353 struct sas_task *task = ccb->task; 4354 struct domain_device *dev = task->dev; 4355 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4356 struct ssp_ini_io_start_req ssp_cmd; 4357 u32 tag = ccb->ccb_tag; 4358 int ret; 4359 u64 phys_addr, start_addr, end_addr; 4360 u32 end_addr_high, end_addr_low; 4361 struct inbound_queue_table *circularQ; 4362 u32 q_index, cpu_id; 4363 u32 opc = OPC_INB_SSPINIIOSTART; 4364 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4365 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4366 /* data address domain added for spcv; set to 0 by host, 4367 * used internally by controller 4368 * 0 for SAS 1.1 and SAS 2.0 compatible TLR 4369 */ 4370 ssp_cmd.dad_dir_m_tlr = 4371 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); 4372 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4373 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4374 ssp_cmd.tag = cpu_to_le32(tag); 4375 if (task->ssp_task.enable_first_burst) 4376 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4377 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4378 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4379 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4380 task->ssp_task.cmd->cmd_len); 4381 cpu_id = smp_processor_id(); 4382 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num); 4383 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4384 4385 /* Check if encryption is set */ 4386 if (pm8001_ha->chip->encrypt && 4387 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { 4388 pm8001_dbg(pm8001_ha, IO, 4389 "Encryption enabled.Sending Encrypt SAS command 0x%x\n", 4390 task->ssp_task.cmd->cmnd[0]); 4391 opc = OPC_INB_SSP_INI_DIF_ENC_IO; 4392 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ 4393 ssp_cmd.dad_dir_m_tlr = cpu_to_le32 4394 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); 4395 4396 /* fill in PRD (scatter/gather) table, if any */ 4397 if (task->num_scatter > 1) { 4398 pm8001_chip_make_sg(task->scatter, 4399 ccb->n_elem, ccb->buf_prd); 4400 phys_addr = ccb->ccb_dma_handle; 4401 ssp_cmd.enc_addr_low = 4402 cpu_to_le32(lower_32_bits(phys_addr)); 4403 ssp_cmd.enc_addr_high = 4404 cpu_to_le32(upper_32_bits(phys_addr)); 4405 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4406 } else if (task->num_scatter == 1) { 4407 u64 dma_addr = sg_dma_address(task->scatter); 4408 ssp_cmd.enc_addr_low = 4409 cpu_to_le32(lower_32_bits(dma_addr)); 4410 ssp_cmd.enc_addr_high = 4411 cpu_to_le32(upper_32_bits(dma_addr)); 4412 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4413 ssp_cmd.enc_esgl = 0; 4414 /* Check 4G Boundary */ 4415 start_addr = cpu_to_le64(dma_addr); 4416 end_addr = (start_addr + ssp_cmd.enc_len) - 1; 4417 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4418 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4419 if (end_addr_high != ssp_cmd.enc_addr_high) { 4420 pm8001_dbg(pm8001_ha, FAIL, 4421 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4422 start_addr, ssp_cmd.enc_len, 4423 end_addr_high, end_addr_low); 4424 pm8001_chip_make_sg(task->scatter, 1, 4425 ccb->buf_prd); 4426 phys_addr = ccb->ccb_dma_handle; 4427 ssp_cmd.enc_addr_low = 4428 cpu_to_le32(lower_32_bits(phys_addr)); 4429 ssp_cmd.enc_addr_high = 4430 cpu_to_le32(upper_32_bits(phys_addr)); 4431 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4432 } 4433 } else if (task->num_scatter == 0) { 4434 ssp_cmd.enc_addr_low = 0; 4435 ssp_cmd.enc_addr_high = 0; 4436 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4437 ssp_cmd.enc_esgl = 0; 4438 } 4439 /* XTS mode. All other fields are 0 */ 4440 ssp_cmd.key_cmode = 0x6 << 4; 4441 /* set tweak values. Should be the start lba */ 4442 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | 4443 (task->ssp_task.cmd->cmnd[3] << 16) | 4444 (task->ssp_task.cmd->cmnd[4] << 8) | 4445 (task->ssp_task.cmd->cmnd[5])); 4446 } else { 4447 pm8001_dbg(pm8001_ha, IO, 4448 "Sending Normal SAS command 0x%x inb q %x\n", 4449 task->ssp_task.cmd->cmnd[0], q_index); 4450 /* fill in PRD (scatter/gather) table, if any */ 4451 if (task->num_scatter > 1) { 4452 pm8001_chip_make_sg(task->scatter, ccb->n_elem, 4453 ccb->buf_prd); 4454 phys_addr = ccb->ccb_dma_handle; 4455 ssp_cmd.addr_low = 4456 cpu_to_le32(lower_32_bits(phys_addr)); 4457 ssp_cmd.addr_high = 4458 cpu_to_le32(upper_32_bits(phys_addr)); 4459 ssp_cmd.esgl = cpu_to_le32(1<<31); 4460 } else if (task->num_scatter == 1) { 4461 u64 dma_addr = sg_dma_address(task->scatter); 4462 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4463 ssp_cmd.addr_high = 4464 cpu_to_le32(upper_32_bits(dma_addr)); 4465 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4466 ssp_cmd.esgl = 0; 4467 /* Check 4G Boundary */ 4468 start_addr = cpu_to_le64(dma_addr); 4469 end_addr = (start_addr + ssp_cmd.len) - 1; 4470 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4471 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4472 if (end_addr_high != ssp_cmd.addr_high) { 4473 pm8001_dbg(pm8001_ha, FAIL, 4474 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4475 start_addr, ssp_cmd.len, 4476 end_addr_high, end_addr_low); 4477 pm8001_chip_make_sg(task->scatter, 1, 4478 ccb->buf_prd); 4479 phys_addr = ccb->ccb_dma_handle; 4480 ssp_cmd.addr_low = 4481 cpu_to_le32(lower_32_bits(phys_addr)); 4482 ssp_cmd.addr_high = 4483 cpu_to_le32(upper_32_bits(phys_addr)); 4484 ssp_cmd.esgl = cpu_to_le32(1<<31); 4485 } 4486 } else if (task->num_scatter == 0) { 4487 ssp_cmd.addr_low = 0; 4488 ssp_cmd.addr_high = 0; 4489 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4490 ssp_cmd.esgl = 0; 4491 } 4492 } 4493 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4494 &ssp_cmd, sizeof(ssp_cmd), q_index); 4495 return ret; 4496 } 4497 4498 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4499 struct pm8001_ccb_info *ccb) 4500 { 4501 struct sas_task *task = ccb->task; 4502 struct domain_device *dev = task->dev; 4503 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4504 u32 tag = ccb->ccb_tag; 4505 int ret; 4506 u32 q_index, cpu_id; 4507 struct sata_start_req sata_cmd; 4508 u32 hdr_tag, ncg_tag = 0; 4509 u64 phys_addr, start_addr, end_addr; 4510 u32 end_addr_high, end_addr_low; 4511 u32 ATAP = 0x0; 4512 u32 dir; 4513 struct inbound_queue_table *circularQ; 4514 unsigned long flags; 4515 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4516 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4517 cpu_id = smp_processor_id(); 4518 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num); 4519 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4520 4521 if (task->data_dir == DMA_NONE) { 4522 ATAP = 0x04; /* no data*/ 4523 pm8001_dbg(pm8001_ha, IO, "no data\n"); 4524 } else if (likely(!task->ata_task.device_control_reg_update)) { 4525 if (task->ata_task.dma_xfer) { 4526 ATAP = 0x06; /* DMA */ 4527 pm8001_dbg(pm8001_ha, IO, "DMA\n"); 4528 } else { 4529 ATAP = 0x05; /* PIO*/ 4530 pm8001_dbg(pm8001_ha, IO, "PIO\n"); 4531 } 4532 if (task->ata_task.use_ncq && 4533 dev->sata_dev.class != ATA_DEV_ATAPI) { 4534 ATAP = 0x07; /* FPDMA */ 4535 pm8001_dbg(pm8001_ha, IO, "FPDMA\n"); 4536 } 4537 } 4538 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4539 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4540 ncg_tag = hdr_tag; 4541 } 4542 dir = data_dir_flags[task->data_dir] << 8; 4543 sata_cmd.tag = cpu_to_le32(tag); 4544 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4545 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4546 4547 sata_cmd.sata_fis = task->ata_task.fis; 4548 if (likely(!task->ata_task.device_control_reg_update)) 4549 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4550 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4551 4552 /* Check if encryption is set */ 4553 if (pm8001_ha->chip->encrypt && 4554 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { 4555 pm8001_dbg(pm8001_ha, IO, 4556 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", 4557 sata_cmd.sata_fis.command); 4558 opc = OPC_INB_SATA_DIF_ENC_IO; 4559 4560 /* set encryption bit */ 4561 sata_cmd.ncqtag_atap_dir_m_dad = 4562 cpu_to_le32(((ncg_tag & 0xff)<<16)| 4563 ((ATAP & 0x3f) << 10) | 0x20 | dir); 4564 /* dad (bit 0-1) is 0 */ 4565 /* fill in PRD (scatter/gather) table, if any */ 4566 if (task->num_scatter > 1) { 4567 pm8001_chip_make_sg(task->scatter, 4568 ccb->n_elem, ccb->buf_prd); 4569 phys_addr = ccb->ccb_dma_handle; 4570 sata_cmd.enc_addr_low = lower_32_bits(phys_addr); 4571 sata_cmd.enc_addr_high = upper_32_bits(phys_addr); 4572 sata_cmd.enc_esgl = cpu_to_le32(1 << 31); 4573 } else if (task->num_scatter == 1) { 4574 u64 dma_addr = sg_dma_address(task->scatter); 4575 sata_cmd.enc_addr_low = lower_32_bits(dma_addr); 4576 sata_cmd.enc_addr_high = upper_32_bits(dma_addr); 4577 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4578 sata_cmd.enc_esgl = 0; 4579 /* Check 4G Boundary */ 4580 start_addr = cpu_to_le64(dma_addr); 4581 end_addr = (start_addr + sata_cmd.enc_len) - 1; 4582 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4583 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4584 if (end_addr_high != sata_cmd.enc_addr_high) { 4585 pm8001_dbg(pm8001_ha, FAIL, 4586 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4587 start_addr, sata_cmd.enc_len, 4588 end_addr_high, end_addr_low); 4589 pm8001_chip_make_sg(task->scatter, 1, 4590 ccb->buf_prd); 4591 phys_addr = ccb->ccb_dma_handle; 4592 sata_cmd.enc_addr_low = 4593 lower_32_bits(phys_addr); 4594 sata_cmd.enc_addr_high = 4595 upper_32_bits(phys_addr); 4596 sata_cmd.enc_esgl = 4597 cpu_to_le32(1 << 31); 4598 } 4599 } else if (task->num_scatter == 0) { 4600 sata_cmd.enc_addr_low = 0; 4601 sata_cmd.enc_addr_high = 0; 4602 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4603 sata_cmd.enc_esgl = 0; 4604 } 4605 /* XTS mode. All other fields are 0 */ 4606 sata_cmd.key_index_mode = 0x6 << 4; 4607 /* set tweak values. Should be the start lba */ 4608 sata_cmd.twk_val0 = 4609 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | 4610 (sata_cmd.sata_fis.lbah << 16) | 4611 (sata_cmd.sata_fis.lbam << 8) | 4612 (sata_cmd.sata_fis.lbal)); 4613 sata_cmd.twk_val1 = 4614 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | 4615 (sata_cmd.sata_fis.lbam_exp)); 4616 } else { 4617 pm8001_dbg(pm8001_ha, IO, 4618 "Sending Normal SATA command 0x%x inb %x\n", 4619 sata_cmd.sata_fis.command, q_index); 4620 /* dad (bit 0-1) is 0 */ 4621 sata_cmd.ncqtag_atap_dir_m_dad = 4622 cpu_to_le32(((ncg_tag & 0xff)<<16) | 4623 ((ATAP & 0x3f) << 10) | dir); 4624 4625 /* fill in PRD (scatter/gather) table, if any */ 4626 if (task->num_scatter > 1) { 4627 pm8001_chip_make_sg(task->scatter, 4628 ccb->n_elem, ccb->buf_prd); 4629 phys_addr = ccb->ccb_dma_handle; 4630 sata_cmd.addr_low = lower_32_bits(phys_addr); 4631 sata_cmd.addr_high = upper_32_bits(phys_addr); 4632 sata_cmd.esgl = cpu_to_le32(1 << 31); 4633 } else if (task->num_scatter == 1) { 4634 u64 dma_addr = sg_dma_address(task->scatter); 4635 sata_cmd.addr_low = lower_32_bits(dma_addr); 4636 sata_cmd.addr_high = upper_32_bits(dma_addr); 4637 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4638 sata_cmd.esgl = 0; 4639 /* Check 4G Boundary */ 4640 start_addr = cpu_to_le64(dma_addr); 4641 end_addr = (start_addr + sata_cmd.len) - 1; 4642 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4643 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4644 if (end_addr_high != sata_cmd.addr_high) { 4645 pm8001_dbg(pm8001_ha, FAIL, 4646 "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4647 start_addr, sata_cmd.len, 4648 end_addr_high, end_addr_low); 4649 pm8001_chip_make_sg(task->scatter, 1, 4650 ccb->buf_prd); 4651 phys_addr = ccb->ccb_dma_handle; 4652 sata_cmd.addr_low = 4653 lower_32_bits(phys_addr); 4654 sata_cmd.addr_high = 4655 upper_32_bits(phys_addr); 4656 sata_cmd.esgl = cpu_to_le32(1 << 31); 4657 } 4658 } else if (task->num_scatter == 0) { 4659 sata_cmd.addr_low = 0; 4660 sata_cmd.addr_high = 0; 4661 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4662 sata_cmd.esgl = 0; 4663 } 4664 /* scsi cdb */ 4665 sata_cmd.atapi_scsi_cdb[0] = 4666 cpu_to_le32(((task->ata_task.atapi_packet[0]) | 4667 (task->ata_task.atapi_packet[1] << 8) | 4668 (task->ata_task.atapi_packet[2] << 16) | 4669 (task->ata_task.atapi_packet[3] << 24))); 4670 sata_cmd.atapi_scsi_cdb[1] = 4671 cpu_to_le32(((task->ata_task.atapi_packet[4]) | 4672 (task->ata_task.atapi_packet[5] << 8) | 4673 (task->ata_task.atapi_packet[6] << 16) | 4674 (task->ata_task.atapi_packet[7] << 24))); 4675 sata_cmd.atapi_scsi_cdb[2] = 4676 cpu_to_le32(((task->ata_task.atapi_packet[8]) | 4677 (task->ata_task.atapi_packet[9] << 8) | 4678 (task->ata_task.atapi_packet[10] << 16) | 4679 (task->ata_task.atapi_packet[11] << 24))); 4680 sata_cmd.atapi_scsi_cdb[3] = 4681 cpu_to_le32(((task->ata_task.atapi_packet[12]) | 4682 (task->ata_task.atapi_packet[13] << 8) | 4683 (task->ata_task.atapi_packet[14] << 16) | 4684 (task->ata_task.atapi_packet[15] << 24))); 4685 } 4686 4687 /* Check for read log for failed drive and return */ 4688 if (sata_cmd.sata_fis.command == 0x2f) { 4689 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4690 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4691 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4692 struct task_status_struct *ts; 4693 4694 pm8001_ha_dev->id &= 0xDFFFFFFF; 4695 ts = &task->task_status; 4696 4697 spin_lock_irqsave(&task->task_state_lock, flags); 4698 ts->resp = SAS_TASK_COMPLETE; 4699 ts->stat = SAM_STAT_GOOD; 4700 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4701 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4702 task->task_state_flags |= SAS_TASK_STATE_DONE; 4703 if (unlikely((task->task_state_flags & 4704 SAS_TASK_STATE_ABORTED))) { 4705 spin_unlock_irqrestore(&task->task_state_lock, 4706 flags); 4707 pm8001_dbg(pm8001_ha, FAIL, 4708 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n", 4709 task, ts->resp, 4710 ts->stat); 4711 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4712 return 0; 4713 } else { 4714 spin_unlock_irqrestore(&task->task_state_lock, 4715 flags); 4716 pm8001_ccb_task_free_done(pm8001_ha, task, 4717 ccb, tag); 4718 atomic_dec(&pm8001_ha_dev->running_req); 4719 return 0; 4720 } 4721 } 4722 } 4723 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4724 &sata_cmd, sizeof(sata_cmd), q_index); 4725 return ret; 4726 } 4727 4728 /** 4729 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND 4730 * @pm8001_ha: our hba card information. 4731 * @phy_id: the phy id which we wanted to start up. 4732 */ 4733 static int 4734 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4735 { 4736 struct phy_start_req payload; 4737 struct inbound_queue_table *circularQ; 4738 int ret; 4739 u32 tag = 0x01; 4740 u32 opcode = OPC_INB_PHYSTART; 4741 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4742 memset(&payload, 0, sizeof(payload)); 4743 payload.tag = cpu_to_le32(tag); 4744 4745 pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id); 4746 4747 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4748 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id); 4749 /* SSC Disable and SAS Analog ST configuration */ 4750 /** 4751 payload.ase_sh_lm_slr_phyid = 4752 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | 4753 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | 4754 phy_id); 4755 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need 4756 **/ 4757 4758 payload.sas_identify.dev_type = SAS_END_DEVICE; 4759 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4760 memcpy(payload.sas_identify.sas_addr, 4761 &pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4762 payload.sas_identify.phy_id = phy_id; 4763 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4764 sizeof(payload), 0); 4765 return ret; 4766 } 4767 4768 /** 4769 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4770 * @pm8001_ha: our hba card information. 4771 * @phy_id: the phy id which we wanted to start up. 4772 */ 4773 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4774 u8 phy_id) 4775 { 4776 struct phy_stop_req payload; 4777 struct inbound_queue_table *circularQ; 4778 int ret; 4779 u32 tag = 0x01; 4780 u32 opcode = OPC_INB_PHYSTOP; 4781 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4782 memset(&payload, 0, sizeof(payload)); 4783 payload.tag = cpu_to_le32(tag); 4784 payload.phy_id = cpu_to_le32(phy_id); 4785 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4786 sizeof(payload), 0); 4787 return ret; 4788 } 4789 4790 /* 4791 * see comments on pm8001_mpi_reg_resp. 4792 */ 4793 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4794 struct pm8001_device *pm8001_dev, u32 flag) 4795 { 4796 struct reg_dev_req payload; 4797 u32 opc; 4798 u32 stp_sspsmp_sata = 0x4; 4799 struct inbound_queue_table *circularQ; 4800 u32 linkrate, phy_id; 4801 int rc, tag = 0xdeadbeef; 4802 struct pm8001_ccb_info *ccb; 4803 u8 retryFlag = 0x1; 4804 u16 firstBurstSize = 0; 4805 u16 ITNT = 2000; 4806 struct domain_device *dev = pm8001_dev->sas_device; 4807 struct domain_device *parent_dev = dev->parent; 4808 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4809 4810 memset(&payload, 0, sizeof(payload)); 4811 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4812 if (rc) 4813 return rc; 4814 ccb = &pm8001_ha->ccb_info[tag]; 4815 ccb->device = pm8001_dev; 4816 ccb->ccb_tag = tag; 4817 payload.tag = cpu_to_le32(tag); 4818 4819 if (flag == 1) { 4820 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4821 } else { 4822 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4823 stp_sspsmp_sata = 0x00; /* stp*/ 4824 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4825 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4826 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4827 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4828 } 4829 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4830 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4831 else 4832 phy_id = pm8001_dev->attached_phy; 4833 4834 opc = OPC_INB_REG_DEV; 4835 4836 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4837 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4838 4839 payload.phyid_portid = 4840 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) | 4841 ((phy_id & 0xFF) << 8)); 4842 4843 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | 4844 ((linkrate & 0x0F) << 24) | 4845 ((stp_sspsmp_sata & 0x03) << 28)); 4846 payload.firstburstsize_ITNexustimeout = 4847 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4848 4849 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4850 SAS_ADDR_SIZE); 4851 4852 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4853 sizeof(payload), 0); 4854 if (rc) 4855 pm8001_tag_free(pm8001_ha, tag); 4856 4857 return rc; 4858 } 4859 4860 /** 4861 * pm80xx_chip_phy_ctl_req - support the local phy operation 4862 * @pm8001_ha: our hba card information. 4863 * @phyId: the phy id which we wanted to operate 4864 * @phy_op: phy operation to request 4865 */ 4866 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4867 u32 phyId, u32 phy_op) 4868 { 4869 u32 tag; 4870 int rc; 4871 struct local_phy_ctl_req payload; 4872 struct inbound_queue_table *circularQ; 4873 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4874 memset(&payload, 0, sizeof(payload)); 4875 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4876 if (rc) 4877 return rc; 4878 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4879 payload.tag = cpu_to_le32(tag); 4880 payload.phyop_phyid = 4881 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); 4882 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4883 sizeof(payload), 0); 4884 } 4885 4886 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4887 { 4888 #ifdef PM8001_USE_MSIX 4889 return 1; 4890 #else 4891 u32 value; 4892 4893 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4894 if (value) 4895 return 1; 4896 return 0; 4897 #endif 4898 } 4899 4900 /** 4901 * pm8001_chip_isr - PM8001 isr handler. 4902 * @pm8001_ha: our hba card information. 4903 * @vec: irq number. 4904 */ 4905 static irqreturn_t 4906 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4907 { 4908 pm80xx_chip_interrupt_disable(pm8001_ha, vec); 4909 pm8001_dbg(pm8001_ha, DEVIO, 4910 "irq vec %d, ODMR:0x%x\n", 4911 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); 4912 process_oq(pm8001_ha, vec); 4913 pm80xx_chip_interrupt_enable(pm8001_ha, vec); 4914 return IRQ_HANDLED; 4915 } 4916 4917 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha, 4918 u32 operation, u32 phyid, 4919 u32 length, u32 *buf) 4920 { 4921 u32 tag , i, j = 0; 4922 int rc; 4923 struct set_phy_profile_req payload; 4924 struct inbound_queue_table *circularQ; 4925 u32 opc = OPC_INB_SET_PHY_PROFILE; 4926 4927 memset(&payload, 0, sizeof(payload)); 4928 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4929 if (rc) 4930 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n"); 4931 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4932 payload.tag = cpu_to_le32(tag); 4933 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF)); 4934 pm8001_dbg(pm8001_ha, INIT, 4935 " phy profile command for phy %x ,length is %d\n", 4936 payload.ppc_phyid, length); 4937 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { 4938 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i)); 4939 j++; 4940 } 4941 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4942 sizeof(payload), 0); 4943 if (rc) 4944 pm8001_tag_free(pm8001_ha, tag); 4945 } 4946 4947 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 4948 u32 length, u8 *buf) 4949 { 4950 u32 i; 4951 4952 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 4953 mpi_set_phy_profile_req(pm8001_ha, 4954 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf); 4955 length = length + PHY_DWORD_LENGTH; 4956 } 4957 pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n"); 4958 } 4959 4960 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, 4961 u32 phy, u32 length, u32 *buf) 4962 { 4963 u32 tag, opc; 4964 int rc, i; 4965 struct set_phy_profile_req payload; 4966 struct inbound_queue_table *circularQ; 4967 4968 memset(&payload, 0, sizeof(payload)); 4969 4970 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4971 if (rc) 4972 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n"); 4973 4974 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4975 opc = OPC_INB_SET_PHY_PROFILE; 4976 4977 payload.tag = cpu_to_le32(tag); 4978 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8) 4979 | (phy & 0xFF)); 4980 4981 for (i = 0; i < length; i++) 4982 payload.reserved[i] = cpu_to_le32(*(buf + i)); 4983 4984 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4985 sizeof(payload), 0); 4986 if (rc) 4987 pm8001_tag_free(pm8001_ha, tag); 4988 4989 pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy); 4990 } 4991 const struct pm8001_dispatch pm8001_80xx_dispatch = { 4992 .name = "pmc80xx", 4993 .chip_init = pm80xx_chip_init, 4994 .chip_soft_rst = pm80xx_chip_soft_rst, 4995 .chip_rst = pm80xx_hw_chip_rst, 4996 .chip_iounmap = pm8001_chip_iounmap, 4997 .isr = pm80xx_chip_isr, 4998 .is_our_interrupt = pm80xx_chip_is_our_interrupt, 4999 .isr_process_oq = process_oq, 5000 .interrupt_enable = pm80xx_chip_interrupt_enable, 5001 .interrupt_disable = pm80xx_chip_interrupt_disable, 5002 .make_prd = pm8001_chip_make_sg, 5003 .smp_req = pm80xx_chip_smp_req, 5004 .ssp_io_req = pm80xx_chip_ssp_io_req, 5005 .sata_req = pm80xx_chip_sata_req, 5006 .phy_start_req = pm80xx_chip_phy_start_req, 5007 .phy_stop_req = pm80xx_chip_phy_stop_req, 5008 .reg_dev_req = pm80xx_chip_reg_dev_req, 5009 .dereg_dev_req = pm8001_chip_dereg_dev_req, 5010 .phy_ctl_req = pm80xx_chip_phy_ctl_req, 5011 .task_abort = pm8001_chip_abort_task, 5012 .ssp_tm_req = pm8001_chip_ssp_tm_req, 5013 .get_nvmd_req = pm8001_chip_get_nvmd_req, 5014 .set_nvmd_req = pm8001_chip_set_nvmd_req, 5015 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 5016 .set_dev_state_req = pm8001_chip_set_dev_state_req, 5017 .fatal_errors = pm80xx_fatal_errors, 5018 }; 5019