1 /* 2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 PMC-Sierra, Inc., 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm80xx_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 #define SMP_DIRECT 1 47 #define SMP_INDIRECT 2 48 49 50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value) 51 { 52 u32 reg_val; 53 unsigned long start; 54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); 55 /* confirm the setting is written */ 56 start = jiffies + HZ; /* 1 sec */ 57 do { 58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); 59 } while ((reg_val != shift_value) && time_before(jiffies, start)); 60 if (reg_val != shift_value) { 61 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n", 62 reg_val); 63 return -1; 64 } 65 return 0; 66 } 67 68 static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset, 69 const void *destination, 70 u32 dw_count, u32 bus_base_number) 71 { 72 u32 index, value, offset; 73 u32 *destination1; 74 destination1 = (u32 *)destination; 75 76 for (index = 0; index < dw_count; index += 4, destination1++) { 77 offset = (soffset + index); 78 if (offset < (64 * 1024)) { 79 value = pm8001_cr32(pm8001_ha, bus_base_number, offset); 80 *destination1 = cpu_to_le32(value); 81 } 82 } 83 return; 84 } 85 86 ssize_t pm80xx_get_fatal_dump(struct device *cdev, 87 struct device_attribute *attr, char *buf) 88 { 89 struct Scsi_Host *shost = class_to_shost(cdev); 90 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 91 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 92 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; 93 u32 accum_len, reg_val, index, *temp; 94 u32 status = 1; 95 unsigned long start; 96 u8 *direct_data; 97 char *fatal_error_data = buf; 98 u32 length_to_read; 99 u32 offset; 100 101 pm8001_ha->forensic_info.data_buf.direct_data = buf; 102 if (pm8001_ha->chip_id == chip_8001) { 103 pm8001_ha->forensic_info.data_buf.direct_data += 104 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 105 "Not supported for SPC controller"); 106 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 107 (char *)buf; 108 } 109 /* initialize variables for very first call from host application */ 110 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 111 pm8001_dbg(pm8001_ha, IO, 112 "forensic_info TYPE_NON_FATAL..............\n"); 113 direct_data = (u8 *)fatal_error_data; 114 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; 115 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; 116 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 117 pm8001_ha->forensic_info.data_buf.read_len = 0; 118 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 119 120 /* Write signature to fatal dump table */ 121 pm8001_mw32(fatal_table_address, 122 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd); 123 124 pm8001_ha->forensic_info.data_buf.direct_data = direct_data; 125 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status); 126 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n", 127 pm8001_ha->forensic_info.data_buf.read_len); 128 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n", 129 pm8001_ha->forensic_info.data_buf.direct_len); 130 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n", 131 pm8001_ha->forensic_info.data_buf.direct_offset); 132 } 133 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 134 /* start to get data */ 135 /* Program the MEMBASE II Shifting Register with 0x00.*/ 136 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 137 pm8001_ha->fatal_forensic_shift_offset); 138 pm8001_ha->forensic_last_offset = 0; 139 pm8001_ha->forensic_fatal_step = 0; 140 pm8001_ha->fatal_bar_loc = 0; 141 } 142 143 /* Read until accum_len is retrieved */ 144 accum_len = pm8001_mr32(fatal_table_address, 145 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 146 /* Determine length of data between previously stored transfer length 147 * and current accumulated transfer length 148 */ 149 length_to_read = 150 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer; 151 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n", 152 accum_len); 153 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n", 154 length_to_read); 155 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n", 156 pm8001_ha->forensic_last_offset); 157 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n", 158 pm8001_ha->forensic_info.data_buf.read_len); 159 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n", 160 pm8001_ha->forensic_info.data_buf.direct_len); 161 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n", 162 pm8001_ha->forensic_info.data_buf.direct_offset); 163 164 /* If accumulated length failed to read correctly fail the attempt.*/ 165 if (accum_len == 0xFFFFFFFF) { 166 pm8001_dbg(pm8001_ha, IO, 167 "Possible PCI issue 0x%x not expected\n", 168 accum_len); 169 return status; 170 } 171 /* If accumulated length is zero fail the attempt */ 172 if (accum_len == 0) { 173 pm8001_ha->forensic_info.data_buf.direct_data += 174 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 175 "%08x ", 0xFFFFFFFF); 176 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 177 (char *)buf; 178 } 179 /* Accumulated length is good so start capturing the first data */ 180 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 181 if (pm8001_ha->forensic_fatal_step == 0) { 182 moreData: 183 /* If data to read is less than SYSFS_OFFSET then reduce the 184 * length of dataLen 185 */ 186 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET 187 > length_to_read) { 188 pm8001_ha->forensic_info.data_buf.direct_len = 189 length_to_read - 190 pm8001_ha->forensic_last_offset; 191 } else { 192 pm8001_ha->forensic_info.data_buf.direct_len = 193 SYSFS_OFFSET; 194 } 195 if (pm8001_ha->forensic_info.data_buf.direct_data) { 196 /* Data is in bar, copy to host memory */ 197 pm80xx_pci_mem_copy(pm8001_ha, 198 pm8001_ha->fatal_bar_loc, 199 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, 200 pm8001_ha->forensic_info.data_buf.direct_len, 1); 201 } 202 pm8001_ha->fatal_bar_loc += 203 pm8001_ha->forensic_info.data_buf.direct_len; 204 pm8001_ha->forensic_info.data_buf.direct_offset += 205 pm8001_ha->forensic_info.data_buf.direct_len; 206 pm8001_ha->forensic_last_offset += 207 pm8001_ha->forensic_info.data_buf.direct_len; 208 pm8001_ha->forensic_info.data_buf.read_len = 209 pm8001_ha->forensic_info.data_buf.direct_len; 210 211 if (pm8001_ha->forensic_last_offset >= length_to_read) { 212 pm8001_ha->forensic_info.data_buf.direct_data += 213 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 214 "%08x ", 3); 215 for (index = 0; index < 216 (pm8001_ha->forensic_info.data_buf.direct_len 217 / 4); index++) { 218 pm8001_ha->forensic_info.data_buf.direct_data += 219 sprintf( 220 pm8001_ha->forensic_info.data_buf.direct_data, 221 "%08x ", *(temp + index)); 222 } 223 224 pm8001_ha->fatal_bar_loc = 0; 225 pm8001_ha->forensic_fatal_step = 1; 226 pm8001_ha->fatal_forensic_shift_offset = 0; 227 pm8001_ha->forensic_last_offset = 0; 228 status = 0; 229 offset = (int) 230 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 231 - (char *)buf); 232 pm8001_dbg(pm8001_ha, IO, 233 "get_fatal_spcv:return1 0x%x\n", offset); 234 return (char *)pm8001_ha-> 235 forensic_info.data_buf.direct_data - 236 (char *)buf; 237 } 238 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { 239 pm8001_ha->forensic_info.data_buf.direct_data += 240 sprintf(pm8001_ha-> 241 forensic_info.data_buf.direct_data, 242 "%08x ", 2); 243 for (index = 0; index < 244 (pm8001_ha->forensic_info.data_buf.direct_len 245 / 4); index++) { 246 pm8001_ha->forensic_info.data_buf.direct_data 247 += sprintf(pm8001_ha-> 248 forensic_info.data_buf.direct_data, 249 "%08x ", *(temp + index)); 250 } 251 status = 0; 252 offset = (int) 253 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 254 - (char *)buf); 255 pm8001_dbg(pm8001_ha, IO, 256 "get_fatal_spcv:return2 0x%x\n", offset); 257 return (char *)pm8001_ha-> 258 forensic_info.data_buf.direct_data - 259 (char *)buf; 260 } 261 262 /* Increment the MEMBASE II Shifting Register value by 0x100.*/ 263 pm8001_ha->forensic_info.data_buf.direct_data += 264 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 265 "%08x ", 2); 266 for (index = 0; index < 267 (pm8001_ha->forensic_info.data_buf.direct_len 268 / 4) ; index++) { 269 pm8001_ha->forensic_info.data_buf.direct_data += 270 sprintf(pm8001_ha-> 271 forensic_info.data_buf.direct_data, 272 "%08x ", *(temp + index)); 273 } 274 pm8001_ha->fatal_forensic_shift_offset += 0x100; 275 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 276 pm8001_ha->fatal_forensic_shift_offset); 277 pm8001_ha->fatal_bar_loc = 0; 278 status = 0; 279 offset = (int) 280 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 281 - (char *)buf); 282 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n", 283 offset); 284 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 285 (char *)buf; 286 } 287 if (pm8001_ha->forensic_fatal_step == 1) { 288 /* store previous accumulated length before triggering next 289 * accumulated length update 290 */ 291 pm8001_ha->forensic_preserved_accumulated_transfer = 292 pm8001_mr32(fatal_table_address, 293 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 294 295 /* continue capturing the fatal log until Dump status is 0x3 */ 296 if (pm8001_mr32(fatal_table_address, 297 MPI_FATAL_EDUMP_TABLE_STATUS) < 298 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) { 299 300 /* reset fddstat bit by writing to zero*/ 301 pm8001_mw32(fatal_table_address, 302 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0); 303 304 /* set dump control value to '1' so that new data will 305 * be transferred to shared memory 306 */ 307 pm8001_mw32(fatal_table_address, 308 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 309 MPI_FATAL_EDUMP_HANDSHAKE_RDY); 310 311 /*Poll FDDHSHK until clear */ 312 start = jiffies + (2 * HZ); /* 2 sec */ 313 314 do { 315 reg_val = pm8001_mr32(fatal_table_address, 316 MPI_FATAL_EDUMP_TABLE_HANDSHAKE); 317 } while ((reg_val) && time_before(jiffies, start)); 318 319 if (reg_val != 0) { 320 pm8001_dbg(pm8001_ha, FAIL, 321 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n", 322 reg_val); 323 /* Fail the dump if a timeout occurs */ 324 pm8001_ha->forensic_info.data_buf.direct_data += 325 sprintf( 326 pm8001_ha->forensic_info.data_buf.direct_data, 327 "%08x ", 0xFFFFFFFF); 328 return((char *) 329 pm8001_ha->forensic_info.data_buf.direct_data 330 - (char *)buf); 331 } 332 /* Poll status register until set to 2 or 333 * 3 for up to 2 seconds 334 */ 335 start = jiffies + (2 * HZ); /* 2 sec */ 336 337 do { 338 reg_val = pm8001_mr32(fatal_table_address, 339 MPI_FATAL_EDUMP_TABLE_STATUS); 340 } while (((reg_val != 2) && (reg_val != 3)) && 341 time_before(jiffies, start)); 342 343 if (reg_val < 2) { 344 pm8001_dbg(pm8001_ha, FAIL, 345 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n", 346 reg_val); 347 /* Fail the dump if a timeout occurs */ 348 pm8001_ha->forensic_info.data_buf.direct_data += 349 sprintf( 350 pm8001_ha->forensic_info.data_buf.direct_data, 351 "%08x ", 0xFFFFFFFF); 352 return((char *)pm8001_ha->forensic_info.data_buf.direct_data - 353 (char *)buf); 354 } 355 /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */ 356 pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */ 357 pm8001_cw32(pm8001_ha, 0, 358 MEMBASE_II_SHIFT_REGISTER, 359 pm8001_ha->fatal_forensic_shift_offset); 360 } 361 /* Read the next block of the debug data.*/ 362 length_to_read = pm8001_mr32(fatal_table_address, 363 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) - 364 pm8001_ha->forensic_preserved_accumulated_transfer; 365 if (length_to_read != 0x0) { 366 pm8001_ha->forensic_fatal_step = 0; 367 goto moreData; 368 } else { 369 pm8001_ha->forensic_info.data_buf.direct_data += 370 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 371 "%08x ", 4); 372 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF; 373 pm8001_ha->forensic_info.data_buf.direct_len = 0; 374 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 375 pm8001_ha->forensic_info.data_buf.read_len = 0; 376 } 377 } 378 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data 379 - (char *)buf); 380 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset); 381 return ((char *)pm8001_ha->forensic_info.data_buf.direct_data - 382 (char *)buf); 383 } 384 385 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma 386 * location by the firmware. 387 */ 388 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev, 389 struct device_attribute *attr, char *buf) 390 { 391 struct Scsi_Host *shost = class_to_shost(cdev); 392 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 393 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 394 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr; 395 u32 accum_len = 0; 396 u32 total_len = 0; 397 u32 reg_val = 0; 398 u32 *temp = NULL; 399 u32 index = 0; 400 u32 output_length; 401 unsigned long start = 0; 402 char *buf_copy = buf; 403 404 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 405 if (++pm8001_ha->non_fatal_count == 1) { 406 if (pm8001_ha->chip_id == chip_8001) { 407 snprintf(pm8001_ha->forensic_info.data_buf.direct_data, 408 PAGE_SIZE, "Not supported for SPC controller"); 409 return 0; 410 } 411 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n"); 412 /* 413 * Step 1: Write the host buffer parameters in the MPI Fatal and 414 * Non-Fatal Error Dump Capture Table.This is the buffer 415 * where debug data will be DMAed to. 416 */ 417 pm8001_mw32(nonfatal_table_address, 418 MPI_FATAL_EDUMP_TABLE_LO_OFFSET, 419 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo); 420 421 pm8001_mw32(nonfatal_table_address, 422 MPI_FATAL_EDUMP_TABLE_HI_OFFSET, 423 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi); 424 425 pm8001_mw32(nonfatal_table_address, 426 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET); 427 428 /* Optionally, set the DUMPCTRL bit to 1 if the host 429 * keeps sending active I/Os while capturing the non-fatal 430 * debug data. Otherwise, leave this bit set to zero 431 */ 432 pm8001_mw32(nonfatal_table_address, 433 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY); 434 435 /* 436 * Step 2: Clear Accumulative Length of Debug Data Transferred 437 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump 438 * Capture Table to zero. 439 */ 440 pm8001_mw32(nonfatal_table_address, 441 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0); 442 443 /* initiallize previous accumulated length to 0 */ 444 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 445 pm8001_ha->non_fatal_read_length = 0; 446 } 447 448 total_len = pm8001_mr32(nonfatal_table_address, 449 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN); 450 /* 451 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT] 452 * field and then request that the SPCv controller transfer the debug 453 * data by setting bit 7 of the Inbound Doorbell Set Register. 454 */ 455 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0); 456 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, 457 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP); 458 459 /* 460 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for 461 * 2 seconds) until register bit 7 is cleared. 462 * This step only indicates the request is accepted by the controller. 463 */ 464 start = jiffies + (2 * HZ); /* 2 sec */ 465 do { 466 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) & 467 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP; 468 } while ((reg_val != 0) && time_before(jiffies, start)); 469 470 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non 471 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in 472 * the MPI Fatal and Non-Fatal Error Dump Capture Table. 473 */ 474 start = jiffies + (2 * HZ); /* 2 sec */ 475 do { 476 reg_val = pm8001_mr32(nonfatal_table_address, 477 MPI_FATAL_EDUMP_TABLE_STATUS); 478 } while ((!reg_val) && time_before(jiffies, start)); 479 480 if ((reg_val == 0x00) || 481 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) || 482 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) { 483 pm8001_ha->non_fatal_read_length = 0; 484 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF); 485 pm8001_ha->non_fatal_count = 0; 486 return (buf_copy - buf); 487 } else if (reg_val == 488 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) { 489 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2); 490 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) || 491 (pm8001_ha->non_fatal_read_length >= total_len)) { 492 pm8001_ha->non_fatal_read_length = 0; 493 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4); 494 pm8001_ha->non_fatal_count = 0; 495 } 496 accum_len = pm8001_mr32(nonfatal_table_address, 497 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 498 output_length = accum_len - 499 pm8001_ha->forensic_preserved_accumulated_transfer; 500 501 for (index = 0; index < output_length/4; index++) 502 buf_copy += snprintf(buf_copy, PAGE_SIZE, 503 "%08x ", *(temp+index)); 504 505 pm8001_ha->non_fatal_read_length += output_length; 506 507 /* store current accumulated length to use in next iteration as 508 * the previous accumulated length 509 */ 510 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len; 511 return (buf_copy - buf); 512 } 513 514 /** 515 * read_main_config_table - read the configure table and save it. 516 * @pm8001_ha: our hba card information 517 */ 518 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 519 { 520 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 521 522 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = 523 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); 524 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = 525 pm8001_mr32(address, MAIN_INTERFACE_REVISION); 526 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = 527 pm8001_mr32(address, MAIN_FW_REVISION); 528 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = 529 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); 530 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = 531 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); 532 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = 533 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); 534 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = 535 pm8001_mr32(address, MAIN_GST_OFFSET); 536 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = 537 pm8001_mr32(address, MAIN_IBQ_OFFSET); 538 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = 539 pm8001_mr32(address, MAIN_OBQ_OFFSET); 540 541 /* read Error Dump Offset and Length */ 542 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = 543 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 544 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = 545 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 546 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = 547 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 548 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = 549 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 550 551 /* read GPIO LED settings from the configuration table */ 552 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = 553 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); 554 555 /* read analog Setting offset from the configuration table */ 556 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = 557 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 558 559 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = 560 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); 561 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = 562 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); 563 /* read port recover and reset timeout */ 564 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer = 565 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER); 566 /* read ILA and inactive firmware version */ 567 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version = 568 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE); 569 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version = 570 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION); 571 572 pm8001_dbg(pm8001_ha, DEV, 573 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n", 574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature, 575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev, 576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev); 577 578 pm8001_dbg(pm8001_ha, DEV, 579 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n", 580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset, 581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset, 582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset, 583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset, 584 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset); 585 586 pm8001_dbg(pm8001_ha, DEV, 587 "Main cfg table; ila rev:%x Inactive fw rev:%x\n", 588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version, 589 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version); 590 } 591 592 /** 593 * read_general_status_table - read the general status table and save it. 594 * @pm8001_ha: our hba card information 595 */ 596 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 597 { 598 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 599 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = 600 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); 601 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = 602 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); 603 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = 604 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); 605 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = 606 pm8001_mr32(address, GST_MSGUTCNT_OFFSET); 607 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = 608 pm8001_mr32(address, GST_IOPTCNT_OFFSET); 609 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = 610 pm8001_mr32(address, GST_GPIO_INPUT_VAL); 611 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = 612 pm8001_mr32(address, GST_RERRINFO_OFFSET0); 613 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = 614 pm8001_mr32(address, GST_RERRINFO_OFFSET1); 615 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = 616 pm8001_mr32(address, GST_RERRINFO_OFFSET2); 617 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = 618 pm8001_mr32(address, GST_RERRINFO_OFFSET3); 619 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = 620 pm8001_mr32(address, GST_RERRINFO_OFFSET4); 621 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = 622 pm8001_mr32(address, GST_RERRINFO_OFFSET5); 623 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = 624 pm8001_mr32(address, GST_RERRINFO_OFFSET6); 625 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = 626 pm8001_mr32(address, GST_RERRINFO_OFFSET7); 627 } 628 /** 629 * read_phy_attr_table - read the phy attribute table and save it. 630 * @pm8001_ha: our hba card information 631 */ 632 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) 633 { 634 void __iomem *address = pm8001_ha->pspa_q_tbl_addr; 635 pm8001_ha->phy_attr_table.phystart1_16[0] = 636 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); 637 pm8001_ha->phy_attr_table.phystart1_16[1] = 638 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); 639 pm8001_ha->phy_attr_table.phystart1_16[2] = 640 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); 641 pm8001_ha->phy_attr_table.phystart1_16[3] = 642 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); 643 pm8001_ha->phy_attr_table.phystart1_16[4] = 644 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); 645 pm8001_ha->phy_attr_table.phystart1_16[5] = 646 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); 647 pm8001_ha->phy_attr_table.phystart1_16[6] = 648 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); 649 pm8001_ha->phy_attr_table.phystart1_16[7] = 650 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); 651 pm8001_ha->phy_attr_table.phystart1_16[8] = 652 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); 653 pm8001_ha->phy_attr_table.phystart1_16[9] = 654 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); 655 pm8001_ha->phy_attr_table.phystart1_16[10] = 656 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); 657 pm8001_ha->phy_attr_table.phystart1_16[11] = 658 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); 659 pm8001_ha->phy_attr_table.phystart1_16[12] = 660 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); 661 pm8001_ha->phy_attr_table.phystart1_16[13] = 662 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); 663 pm8001_ha->phy_attr_table.phystart1_16[14] = 664 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); 665 pm8001_ha->phy_attr_table.phystart1_16[15] = 666 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); 667 668 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = 669 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); 670 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = 671 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); 672 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = 673 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); 674 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = 675 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); 676 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = 677 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); 678 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = 679 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); 680 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = 681 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); 682 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = 683 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); 684 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = 685 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); 686 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = 687 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); 688 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = 689 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); 690 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = 691 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); 692 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = 693 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); 694 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = 695 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); 696 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = 697 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); 698 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = 699 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); 700 701 } 702 703 /** 704 * read_inbnd_queue_table - read the inbound queue table and save it. 705 * @pm8001_ha: our hba card information 706 */ 707 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 708 { 709 int i; 710 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 711 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 712 u32 offset = i * 0x20; 713 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 714 get_pci_bar_index(pm8001_mr32(address, 715 (offset + IB_PIPCI_BAR))); 716 pm8001_ha->inbnd_q_tbl[i].pi_offset = 717 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); 718 } 719 } 720 721 /** 722 * read_outbnd_queue_table - read the outbound queue table and save it. 723 * @pm8001_ha: our hba card information 724 */ 725 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 726 { 727 int i; 728 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 729 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 730 u32 offset = i * 0x24; 731 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 732 get_pci_bar_index(pm8001_mr32(address, 733 (offset + OB_CIPCI_BAR))); 734 pm8001_ha->outbnd_q_tbl[i].ci_offset = 735 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); 736 } 737 } 738 739 /** 740 * init_default_table_values - init the default table. 741 * @pm8001_ha: our hba card information 742 */ 743 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 744 { 745 int i; 746 u32 offsetib, offsetob; 747 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 748 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 749 u32 ib_offset = pm8001_ha->ib_offset; 750 u32 ob_offset = pm8001_ha->ob_offset; 751 u32 ci_offset = pm8001_ha->ci_offset; 752 u32 pi_offset = pm8001_ha->pi_offset; 753 754 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = 755 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 756 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = 757 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 758 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = 759 PM8001_EVENT_LOG_SIZE; 760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; 761 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = 762 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 763 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = 764 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 765 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = 766 PM8001_EVENT_LOG_SIZE; 767 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; 768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; 769 770 /* Disable end to end CRC checking */ 771 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); 772 773 for (i = 0; i < pm8001_ha->max_q_num; i++) { 774 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 775 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 776 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 777 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; 778 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 779 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; 780 pm8001_ha->inbnd_q_tbl[i].base_virt = 781 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; 782 pm8001_ha->inbnd_q_tbl[i].total_length = 783 pm8001_ha->memoryMap.region[ib_offset + i].total_len; 784 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 785 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; 786 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 787 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; 788 pm8001_ha->inbnd_q_tbl[i].ci_virt = 789 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; 790 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0); 791 offsetib = i * 0x20; 792 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 793 get_pci_bar_index(pm8001_mr32(addressib, 794 (offsetib + 0x14))); 795 pm8001_ha->inbnd_q_tbl[i].pi_offset = 796 pm8001_mr32(addressib, (offsetib + 0x18)); 797 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 798 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 799 800 pm8001_dbg(pm8001_ha, DEV, 801 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i, 802 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar, 803 pm8001_ha->inbnd_q_tbl[i].pi_offset); 804 } 805 for (i = 0; i < pm8001_ha->max_q_num; i++) { 806 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 807 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 808 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 809 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; 810 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 811 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; 812 pm8001_ha->outbnd_q_tbl[i].base_virt = 813 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; 814 pm8001_ha->outbnd_q_tbl[i].total_length = 815 pm8001_ha->memoryMap.region[ob_offset + i].total_len; 816 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 817 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; 818 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 819 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; 820 /* interrupt vector based on oq */ 821 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); 822 pm8001_ha->outbnd_q_tbl[i].pi_virt = 823 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; 824 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0); 825 offsetob = i * 0x24; 826 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 827 get_pci_bar_index(pm8001_mr32(addressob, 828 offsetob + 0x14)); 829 pm8001_ha->outbnd_q_tbl[i].ci_offset = 830 pm8001_mr32(addressob, (offsetob + 0x18)); 831 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 832 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 833 834 pm8001_dbg(pm8001_ha, DEV, 835 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i, 836 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar, 837 pm8001_ha->outbnd_q_tbl[i].ci_offset); 838 } 839 } 840 841 /** 842 * update_main_config_table - update the main default table to the HBA. 843 * @pm8001_ha: our hba card information 844 */ 845 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 846 { 847 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 848 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, 849 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); 850 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, 851 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); 852 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, 853 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); 854 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, 855 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); 856 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, 857 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); 858 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, 859 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); 860 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, 861 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); 862 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, 863 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); 864 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, 865 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); 866 /* Update Fatal error interrupt vector */ 867 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 868 ((pm8001_ha->max_q_num - 1) << 8); 869 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, 870 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); 871 pm8001_dbg(pm8001_ha, DEV, 872 "Updated Fatal error interrupt vector 0x%x\n", 873 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)); 874 875 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, 876 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); 877 878 /* SPCv specific */ 879 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; 880 /* Set GPIOLED to 0x2 for LED indicator */ 881 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; 882 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, 883 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); 884 pm8001_dbg(pm8001_ha, DEV, 885 "Programming DW 0x21 in main cfg table with 0x%x\n", 886 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)); 887 888 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 889 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 890 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, 891 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); 892 893 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000; 894 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 895 PORT_RECOVERY_TIMEOUT; 896 if (pm8001_ha->chip_id == chip_8006) { 897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 898 0x0000ffff; 899 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 900 CHIP_8006_PORT_RECOVERY_TIMEOUT; 901 } 902 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 903 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 904 } 905 906 /** 907 * update_inbnd_queue_table - update the inbound queue table to the HBA. 908 * @pm8001_ha: our hba card information 909 * @number: entry in the queue 910 */ 911 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 912 int number) 913 { 914 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 915 u16 offset = number * 0x20; 916 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, 917 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 918 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, 919 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 920 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, 921 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 922 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, 923 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 924 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, 925 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 926 927 pm8001_dbg(pm8001_ha, DEV, 928 "IQ %d: Element pri size 0x%x\n", 929 number, 930 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 931 932 pm8001_dbg(pm8001_ha, DEV, 933 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n", 934 pm8001_ha->inbnd_q_tbl[number].upper_base_addr, 935 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 936 937 pm8001_dbg(pm8001_ha, DEV, 938 "CI upper base addr 0x%x CI lower base addr 0x%x\n", 939 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr, 940 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 941 } 942 943 /** 944 * update_outbnd_queue_table - update the outbound queue table to the HBA. 945 * @pm8001_ha: our hba card information 946 * @number: entry in the queue 947 */ 948 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 949 int number) 950 { 951 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 952 u16 offset = number * 0x24; 953 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, 954 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 955 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, 956 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 957 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, 958 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 959 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, 960 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 961 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, 962 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 963 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, 964 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 965 966 pm8001_dbg(pm8001_ha, DEV, 967 "OQ %d: Element pri size 0x%x\n", 968 number, 969 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 970 971 pm8001_dbg(pm8001_ha, DEV, 972 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n", 973 pm8001_ha->outbnd_q_tbl[number].upper_base_addr, 974 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 975 976 pm8001_dbg(pm8001_ha, DEV, 977 "PI upper base addr 0x%x PI lower base addr 0x%x\n", 978 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr, 979 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 980 } 981 982 /** 983 * mpi_init_check - check firmware initialization status. 984 * @pm8001_ha: our hba card information 985 */ 986 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 987 { 988 u32 max_wait_count; 989 u32 value; 990 u32 gst_len_mpistate; 991 992 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 993 table is updated */ 994 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); 995 /* wait until Inbound DoorBell Clear Register toggled */ 996 if (IS_SPCV_12G(pm8001_ha->pdev)) { 997 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 998 } else { 999 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 1000 } 1001 do { 1002 msleep(FW_READY_INTERVAL); 1003 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1004 value &= SPCv_MSGU_CFG_TABLE_UPDATE; 1005 } while ((value != 0) && (--max_wait_count)); 1006 1007 if (!max_wait_count) { 1008 /* additional check */ 1009 pm8001_dbg(pm8001_ha, FAIL, 1010 "Inb doorbell clear not toggled[value:%x]\n", 1011 value); 1012 return -EBUSY; 1013 } 1014 /* check the MPI-State for initialization up to 100ms*/ 1015 max_wait_count = 5;/* 100 msec */ 1016 do { 1017 msleep(FW_READY_INTERVAL); 1018 gst_len_mpistate = 1019 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1020 GST_GSTLEN_MPIS_OFFSET); 1021 } while ((GST_MPI_STATE_INIT != 1022 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); 1023 if (!max_wait_count) 1024 return -EBUSY; 1025 1026 /* check MPI Initialization error */ 1027 gst_len_mpistate = gst_len_mpistate >> 16; 1028 if (0x0000 != gst_len_mpistate) 1029 return -EBUSY; 1030 1031 return 0; 1032 } 1033 1034 /** 1035 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 1036 * This function sleeps hence it must not be used in atomic context. 1037 * @pm8001_ha: our hba card information 1038 */ 1039 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 1040 { 1041 u32 value; 1042 u32 max_wait_count; 1043 u32 max_wait_time; 1044 u32 expected_mask; 1045 int ret = 0; 1046 1047 /* reset / PCIe ready */ 1048 max_wait_time = max_wait_count = 5; /* 100 milli sec */ 1049 do { 1050 msleep(FW_READY_INTERVAL); 1051 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1052 } while ((value == 0xFFFFFFFF) && (--max_wait_count)); 1053 1054 /* check ila, RAAE and iops status */ 1055 if ((pm8001_ha->chip_id != chip_8008) && 1056 (pm8001_ha->chip_id != chip_8009)) { 1057 max_wait_time = max_wait_count = 180; /* 3600 milli sec */ 1058 expected_mask = SCRATCH_PAD_ILA_READY | 1059 SCRATCH_PAD_RAAE_READY | 1060 SCRATCH_PAD_IOP0_READY | 1061 SCRATCH_PAD_IOP1_READY; 1062 } else { 1063 max_wait_time = max_wait_count = 170; /* 3400 milli sec */ 1064 expected_mask = SCRATCH_PAD_ILA_READY | 1065 SCRATCH_PAD_RAAE_READY | 1066 SCRATCH_PAD_IOP0_READY; 1067 } 1068 do { 1069 msleep(FW_READY_INTERVAL); 1070 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1071 } while (((value & expected_mask) != 1072 expected_mask) && (--max_wait_count)); 1073 if (!max_wait_count) { 1074 pm8001_dbg(pm8001_ha, INIT, 1075 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n", 1076 max_wait_time * FW_READY_INTERVAL, value); 1077 ret = -1; 1078 } else { 1079 pm8001_dbg(pm8001_ha, MSG, 1080 "All FW components ready by %d ms\n", 1081 (max_wait_time - max_wait_count) * FW_READY_INTERVAL); 1082 } 1083 return ret; 1084 } 1085 1086 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 1087 { 1088 void __iomem *base_addr; 1089 u32 value; 1090 u32 offset; 1091 u32 pcibar; 1092 u32 pcilogic; 1093 1094 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1095 1096 /* 1097 * lower 26 bits of SCRATCHPAD0 register describes offset within the 1098 * PCIe BAR where the MPI configuration table is present 1099 */ 1100 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ 1101 1102 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n", 1103 offset, value); 1104 /* 1105 * Upper 6 bits describe the offset within PCI config space where BAR 1106 * is located. 1107 */ 1108 pcilogic = (value & 0xFC000000) >> 26; 1109 pcibar = get_pci_bar_index(pcilogic); 1110 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); 1111 1112 /* 1113 * Make sure the offset falls inside the ioremapped PCI BAR 1114 */ 1115 if (offset > pm8001_ha->io_mem[pcibar].memsize) { 1116 pm8001_dbg(pm8001_ha, FAIL, 1117 "Main cfg tbl offset outside %u > %u\n", 1118 offset, pm8001_ha->io_mem[pcibar].memsize); 1119 return -EBUSY; 1120 } 1121 pm8001_ha->main_cfg_tbl_addr = base_addr = 1122 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 1123 1124 /* 1125 * Validate main configuration table address: first DWord should read 1126 * "PMCS" 1127 */ 1128 value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0); 1129 if (memcmp(&value, "PMCS", 4) != 0) { 1130 pm8001_dbg(pm8001_ha, FAIL, 1131 "BAD main config signature 0x%x\n", 1132 value); 1133 return -EBUSY; 1134 } 1135 pm8001_dbg(pm8001_ha, INIT, 1136 "VALID main config signature 0x%x\n", value); 1137 pm8001_ha->general_stat_tbl_addr = 1138 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 1139 0xFFFFFF); 1140 pm8001_ha->inbnd_q_tbl_addr = 1141 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & 1142 0xFFFFFF); 1143 pm8001_ha->outbnd_q_tbl_addr = 1144 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & 1145 0xFFFFFF); 1146 pm8001_ha->ivt_tbl_addr = 1147 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & 1148 0xFFFFFF); 1149 pm8001_ha->pspa_q_tbl_addr = 1150 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & 1151 0xFFFFFF); 1152 pm8001_ha->fatal_tbl_addr = 1153 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & 1154 0xFFFFFF); 1155 1156 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n", 1157 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)); 1158 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n", 1159 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)); 1160 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n", 1161 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)); 1162 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n", 1163 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)); 1164 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n", 1165 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)); 1166 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n", 1167 pm8001_ha->main_cfg_tbl_addr, 1168 pm8001_ha->general_stat_tbl_addr); 1169 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n", 1170 pm8001_ha->inbnd_q_tbl_addr, 1171 pm8001_ha->outbnd_q_tbl_addr); 1172 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n", 1173 pm8001_ha->pspa_q_tbl_addr, 1174 pm8001_ha->ivt_tbl_addr); 1175 return 0; 1176 } 1177 1178 /** 1179 * pm80xx_set_thermal_config - support the thermal configuration 1180 * @pm8001_ha: our hba card information. 1181 */ 1182 int 1183 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) 1184 { 1185 struct set_ctrl_cfg_req payload; 1186 struct inbound_queue_table *circularQ; 1187 int rc; 1188 u32 tag; 1189 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1190 u32 page_code; 1191 1192 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1193 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1194 if (rc) 1195 return -1; 1196 1197 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1198 payload.tag = cpu_to_le32(tag); 1199 1200 if (IS_SPCV_12G(pm8001_ha->pdev)) 1201 page_code = THERMAL_PAGE_CODE_7H; 1202 else 1203 page_code = THERMAL_PAGE_CODE_8H; 1204 1205 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) | 1206 (THERMAL_ENABLE << 8) | page_code; 1207 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8); 1208 1209 pm8001_dbg(pm8001_ha, DEV, 1210 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n", 1211 payload.cfg_pg[0], payload.cfg_pg[1]); 1212 1213 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1214 sizeof(payload), 0); 1215 if (rc) 1216 pm8001_tag_free(pm8001_ha, tag); 1217 return rc; 1218 1219 } 1220 1221 /** 1222 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol 1223 * Timer configuration page 1224 * @pm8001_ha: our hba card information. 1225 */ 1226 static int 1227 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) 1228 { 1229 struct set_ctrl_cfg_req payload; 1230 struct inbound_queue_table *circularQ; 1231 SASProtocolTimerConfig_t SASConfigPage; 1232 int rc; 1233 u32 tag; 1234 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1235 1236 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1237 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); 1238 1239 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1240 1241 if (rc) 1242 return -1; 1243 1244 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1245 payload.tag = cpu_to_le32(tag); 1246 1247 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE; 1248 SASConfigPage.MST_MSI = 3 << 15; 1249 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO; 1250 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) | 1251 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER; 1252 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME; 1253 1254 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF) 1255 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF; 1256 1257 1258 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) | 1259 SAS_OPNRJT_RTRY_INTVL; 1260 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16) 1261 | SAS_COPNRJT_RTRY_TMO; 1262 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16) 1263 | SAS_COPNRJT_RTRY_THR; 1264 SASConfigPage.MAX_AIP = SAS_MAX_AIP; 1265 1266 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n", 1267 SASConfigPage.pageCode); 1268 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n", 1269 SASConfigPage.MST_MSI); 1270 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n", 1271 SASConfigPage.STP_SSP_MCT_TMO); 1272 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n", 1273 SASConfigPage.STP_FRM_TMO); 1274 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n", 1275 SASConfigPage.STP_IDLE_TMO); 1276 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n", 1277 SASConfigPage.OPNRJT_RTRY_INTVL); 1278 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n", 1279 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO); 1280 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n", 1281 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR); 1282 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n", 1283 SASConfigPage.MAX_AIP); 1284 1285 memcpy(&payload.cfg_pg, &SASConfigPage, 1286 sizeof(SASProtocolTimerConfig_t)); 1287 1288 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1289 sizeof(payload), 0); 1290 if (rc) 1291 pm8001_tag_free(pm8001_ha, tag); 1292 1293 return rc; 1294 } 1295 1296 /** 1297 * pm80xx_get_encrypt_info - Check for encryption 1298 * @pm8001_ha: our hba card information. 1299 */ 1300 static int 1301 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) 1302 { 1303 u32 scratch3_value; 1304 int ret = -1; 1305 1306 /* Read encryption status from SCRATCH PAD 3 */ 1307 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1308 1309 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1310 SCRATCH_PAD3_ENC_READY) { 1311 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1312 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1313 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1314 SCRATCH_PAD3_SMF_ENABLED) 1315 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1316 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1317 SCRATCH_PAD3_SMA_ENABLED) 1318 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1319 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1320 SCRATCH_PAD3_SMB_ENABLED) 1321 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1322 pm8001_ha->encrypt_info.status = 0; 1323 pm8001_dbg(pm8001_ha, INIT, 1324 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", 1325 scratch3_value, 1326 pm8001_ha->encrypt_info.cipher_mode, 1327 pm8001_ha->encrypt_info.sec_mode, 1328 pm8001_ha->encrypt_info.status); 1329 ret = 0; 1330 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == 1331 SCRATCH_PAD3_ENC_DISABLED) { 1332 pm8001_dbg(pm8001_ha, INIT, 1333 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", 1334 scratch3_value); 1335 pm8001_ha->encrypt_info.status = 0xFFFFFFFF; 1336 pm8001_ha->encrypt_info.cipher_mode = 0; 1337 pm8001_ha->encrypt_info.sec_mode = 0; 1338 ret = 0; 1339 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1340 SCRATCH_PAD3_ENC_DIS_ERR) { 1341 pm8001_ha->encrypt_info.status = 1342 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1343 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1344 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1345 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1346 SCRATCH_PAD3_SMF_ENABLED) 1347 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1348 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1349 SCRATCH_PAD3_SMA_ENABLED) 1350 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1351 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1352 SCRATCH_PAD3_SMB_ENABLED) 1353 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1354 pm8001_dbg(pm8001_ha, INIT, 1355 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1356 scratch3_value, 1357 pm8001_ha->encrypt_info.cipher_mode, 1358 pm8001_ha->encrypt_info.sec_mode, 1359 pm8001_ha->encrypt_info.status); 1360 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1361 SCRATCH_PAD3_ENC_ENA_ERR) { 1362 1363 pm8001_ha->encrypt_info.status = 1364 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1365 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1366 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1367 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1368 SCRATCH_PAD3_SMF_ENABLED) 1369 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1370 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1371 SCRATCH_PAD3_SMA_ENABLED) 1372 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1373 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1374 SCRATCH_PAD3_SMB_ENABLED) 1375 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1376 1377 pm8001_dbg(pm8001_ha, INIT, 1378 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1379 scratch3_value, 1380 pm8001_ha->encrypt_info.cipher_mode, 1381 pm8001_ha->encrypt_info.sec_mode, 1382 pm8001_ha->encrypt_info.status); 1383 } 1384 return ret; 1385 } 1386 1387 /** 1388 * pm80xx_encrypt_update - update flash with encryption information 1389 * @pm8001_ha: our hba card information. 1390 */ 1391 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) 1392 { 1393 struct kek_mgmt_req payload; 1394 struct inbound_queue_table *circularQ; 1395 int rc; 1396 u32 tag; 1397 u32 opc = OPC_INB_KEK_MANAGEMENT; 1398 1399 memset(&payload, 0, sizeof(struct kek_mgmt_req)); 1400 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1401 if (rc) 1402 return -1; 1403 1404 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1405 payload.tag = cpu_to_le32(tag); 1406 /* Currently only one key is used. New KEK index is 1. 1407 * Current KEK index is 1. Store KEK to NVRAM is 1. 1408 */ 1409 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) | 1410 KEK_MGMT_SUBOP_KEYCARDUPDATE); 1411 1412 pm8001_dbg(pm8001_ha, DEV, 1413 "Saving Encryption info to flash. payload 0x%x\n", 1414 payload.new_curidx_ksop); 1415 1416 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1417 sizeof(payload), 0); 1418 if (rc) 1419 pm8001_tag_free(pm8001_ha, tag); 1420 1421 return rc; 1422 } 1423 1424 /** 1425 * pm80xx_chip_init - the main init function that initializes whole PM8001 chip. 1426 * @pm8001_ha: our hba card information 1427 */ 1428 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) 1429 { 1430 int ret; 1431 u8 i = 0; 1432 1433 /* check the firmware status */ 1434 if (-1 == check_fw_ready(pm8001_ha)) { 1435 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1436 return -EBUSY; 1437 } 1438 1439 /* Initialize the controller fatal error flag */ 1440 pm8001_ha->controller_fatal_error = false; 1441 1442 /* Initialize pci space address eg: mpi offset */ 1443 ret = init_pci_device_addresses(pm8001_ha); 1444 if (ret) { 1445 pm8001_dbg(pm8001_ha, FAIL, 1446 "Failed to init pci addresses"); 1447 return ret; 1448 } 1449 init_default_table_values(pm8001_ha); 1450 read_main_config_table(pm8001_ha); 1451 read_general_status_table(pm8001_ha); 1452 read_inbnd_queue_table(pm8001_ha); 1453 read_outbnd_queue_table(pm8001_ha); 1454 read_phy_attr_table(pm8001_ha); 1455 1456 /* update main config table ,inbound table and outbound table */ 1457 update_main_config_table(pm8001_ha); 1458 for (i = 0; i < pm8001_ha->max_q_num; i++) { 1459 update_inbnd_queue_table(pm8001_ha, i); 1460 update_outbnd_queue_table(pm8001_ha, i); 1461 } 1462 /* notify firmware update finished and check initialization status */ 1463 if (0 == mpi_init_check(pm8001_ha)) { 1464 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n"); 1465 } else 1466 return -EBUSY; 1467 1468 /* send SAS protocol timer configuration page to FW */ 1469 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha); 1470 1471 /* Check for encryption */ 1472 if (pm8001_ha->chip->encrypt) { 1473 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n"); 1474 ret = pm80xx_get_encrypt_info(pm8001_ha); 1475 if (ret == -1) { 1476 pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n"); 1477 if (pm8001_ha->encrypt_info.status == 0x81) { 1478 pm8001_dbg(pm8001_ha, INIT, 1479 "Encryption enabled with error.Saving encryption key to flash\n"); 1480 pm80xx_encrypt_update(pm8001_ha); 1481 } 1482 } 1483 } 1484 return 0; 1485 } 1486 1487 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 1488 { 1489 u32 max_wait_count; 1490 u32 value; 1491 u32 gst_len_mpistate; 1492 int ret; 1493 1494 ret = init_pci_device_addresses(pm8001_ha); 1495 if (ret) { 1496 pm8001_dbg(pm8001_ha, FAIL, 1497 "Failed to init pci addresses"); 1498 return ret; 1499 } 1500 1501 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 1502 table is stop */ 1503 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); 1504 1505 /* wait until Inbound DoorBell Clear Register toggled */ 1506 if (IS_SPCV_12G(pm8001_ha->pdev)) { 1507 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 1508 } else { 1509 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 1510 } 1511 do { 1512 msleep(FW_READY_INTERVAL); 1513 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1514 value &= SPCv_MSGU_CFG_TABLE_RESET; 1515 } while ((value != 0) && (--max_wait_count)); 1516 1517 if (!max_wait_count) { 1518 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value); 1519 return -1; 1520 } 1521 1522 /* check the MPI-State for termination in progress */ 1523 /* wait until Inbound DoorBell Clear Register toggled */ 1524 max_wait_count = 100; /* 2 sec for spcv/ve */ 1525 do { 1526 msleep(FW_READY_INTERVAL); 1527 gst_len_mpistate = 1528 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1529 GST_GSTLEN_MPIS_OFFSET); 1530 if (GST_MPI_STATE_UNINIT == 1531 (gst_len_mpistate & GST_MPI_STATE_MASK)) 1532 break; 1533 } while (--max_wait_count); 1534 if (!max_wait_count) { 1535 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", 1536 gst_len_mpistate & GST_MPI_STATE_MASK); 1537 return -1; 1538 } 1539 1540 return 0; 1541 } 1542 1543 /** 1544 * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors 1545 * @pm8001_ha: our hba card information 1546 * 1547 * Fatal errors are recoverable only after a host reboot. 1548 */ 1549 int 1550 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha) 1551 { 1552 int ret = 0; 1553 u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0, 1554 MSGU_HOST_SCRATCH_PAD_6); 1555 u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0, 1556 MSGU_HOST_SCRATCH_PAD_7); 1557 u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1558 u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1559 u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1560 1561 if (pm8001_ha->chip_id != chip_8006 && 1562 pm8001_ha->chip_id != chip_8074 && 1563 pm8001_ha->chip_id != chip_8076) { 1564 return 0; 1565 } 1566 1567 if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) { 1568 pm8001_dbg(pm8001_ha, FAIL, 1569 "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n", 1570 scratch_pad1, scratch_pad2, scratch_pad3, 1571 scratch_pad_rsvd0, scratch_pad_rsvd1); 1572 ret = 1; 1573 } 1574 1575 return ret; 1576 } 1577 1578 /** 1579 * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all 1580 * FW register status are reset to the originated status. 1581 * @pm8001_ha: our hba card information 1582 */ 1583 1584 static int 1585 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 1586 { 1587 u32 regval; 1588 u32 bootloader_state; 1589 u32 ibutton0, ibutton1; 1590 1591 /* Process MPI table uninitialization only if FW is ready */ 1592 if (!pm8001_ha->controller_fatal_error) { 1593 /* Check if MPI is in ready state to reset */ 1594 if (mpi_uninit_check(pm8001_ha) != 0) { 1595 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1596 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1597 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1598 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1599 pm8001_dbg(pm8001_ha, FAIL, 1600 "MPI state is not ready scratch: %x:%x:%x:%x\n", 1601 r0, r1, r2, r3); 1602 /* if things aren't ready but the bootloader is ok then 1603 * try the reset anyway. 1604 */ 1605 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK) 1606 return -1; 1607 } 1608 } 1609 /* checked for reset register normal state; 0x0 */ 1610 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1611 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n", 1612 regval); 1613 1614 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); 1615 msleep(500); 1616 1617 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1618 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n", 1619 regval); 1620 1621 if ((regval & SPCv_SOFT_RESET_READ_MASK) == 1622 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { 1623 pm8001_dbg(pm8001_ha, MSG, 1624 " soft reset successful [regval: 0x%x]\n", 1625 regval); 1626 } else { 1627 pm8001_dbg(pm8001_ha, MSG, 1628 " soft reset failed [regval: 0x%x]\n", 1629 regval); 1630 1631 /* check bootloader is successfully executed or in HDA mode */ 1632 bootloader_state = 1633 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1634 SCRATCH_PAD1_BOOTSTATE_MASK; 1635 1636 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { 1637 pm8001_dbg(pm8001_ha, MSG, 1638 "Bootloader state - HDA mode SEEPROM\n"); 1639 } else if (bootloader_state == 1640 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { 1641 pm8001_dbg(pm8001_ha, MSG, 1642 "Bootloader state - HDA mode Bootstrap Pin\n"); 1643 } else if (bootloader_state == 1644 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { 1645 pm8001_dbg(pm8001_ha, MSG, 1646 "Bootloader state - HDA mode soft reset\n"); 1647 } else if (bootloader_state == 1648 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { 1649 pm8001_dbg(pm8001_ha, MSG, 1650 "Bootloader state-HDA mode critical error\n"); 1651 } 1652 return -EBUSY; 1653 } 1654 1655 /* check the firmware status after reset */ 1656 if (-1 == check_fw_ready(pm8001_ha)) { 1657 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1658 /* check iButton feature support for motherboard controller */ 1659 if (pm8001_ha->pdev->subsystem_vendor != 1660 PCI_VENDOR_ID_ADAPTEC2 && 1661 pm8001_ha->pdev->subsystem_vendor != 1662 PCI_VENDOR_ID_ATTO && 1663 pm8001_ha->pdev->subsystem_vendor != 0) { 1664 ibutton0 = pm8001_cr32(pm8001_ha, 0, 1665 MSGU_HOST_SCRATCH_PAD_6); 1666 ibutton1 = pm8001_cr32(pm8001_ha, 0, 1667 MSGU_HOST_SCRATCH_PAD_7); 1668 if (!ibutton0 && !ibutton1) { 1669 pm8001_dbg(pm8001_ha, FAIL, 1670 "iButton Feature is not Available!!!\n"); 1671 return -EBUSY; 1672 } 1673 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { 1674 pm8001_dbg(pm8001_ha, FAIL, 1675 "CRC Check for iButton Feature Failed!!!\n"); 1676 return -EBUSY; 1677 } 1678 } 1679 } 1680 pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n"); 1681 return 0; 1682 } 1683 1684 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1685 { 1686 u32 i; 1687 1688 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n"); 1689 1690 /* do SPCv chip reset. */ 1691 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); 1692 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n"); 1693 1694 /* Check this ..whether delay is required or no */ 1695 /* delay 10 usec */ 1696 udelay(10); 1697 1698 /* wait for 20 msec until the firmware gets reloaded */ 1699 i = 20; 1700 do { 1701 mdelay(1); 1702 } while ((--i) != 0); 1703 1704 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); 1705 } 1706 1707 /** 1708 * pm80xx_chip_intx_interrupt_enable - enable PM8001 chip interrupt 1709 * @pm8001_ha: our hba card information 1710 */ 1711 static void 1712 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1713 { 1714 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1715 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1716 } 1717 1718 /** 1719 * pm80xx_chip_intx_interrupt_disable - disable PM8001 chip interrupt 1720 * @pm8001_ha: our hba card information 1721 */ 1722 static void 1723 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1724 { 1725 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); 1726 } 1727 1728 /** 1729 * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt 1730 * @pm8001_ha: our hba card information 1731 * @vec: interrupt number to enable 1732 */ 1733 static void 1734 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1735 { 1736 #ifdef PM8001_USE_MSIX 1737 u32 mask; 1738 mask = (u32)(1 << vec); 1739 1740 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); 1741 return; 1742 #endif 1743 pm80xx_chip_intx_interrupt_enable(pm8001_ha); 1744 1745 } 1746 1747 /** 1748 * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt 1749 * @pm8001_ha: our hba card information 1750 * @vec: interrupt number to disable 1751 */ 1752 static void 1753 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1754 { 1755 #ifdef PM8001_USE_MSIX 1756 u32 mask; 1757 if (vec == 0xFF) 1758 mask = 0xFFFFFFFF; 1759 else 1760 mask = (u32)(1 << vec); 1761 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); 1762 return; 1763 #endif 1764 pm80xx_chip_intx_interrupt_disable(pm8001_ha); 1765 } 1766 1767 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1768 struct pm8001_device *pm8001_ha_dev) 1769 { 1770 int res; 1771 u32 ccb_tag; 1772 struct pm8001_ccb_info *ccb; 1773 struct sas_task *task = NULL; 1774 struct task_abort_req task_abort; 1775 struct inbound_queue_table *circularQ; 1776 u32 opc = OPC_INB_SATA_ABORT; 1777 int ret; 1778 1779 if (!pm8001_ha_dev) { 1780 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n"); 1781 return; 1782 } 1783 1784 task = sas_alloc_slow_task(GFP_ATOMIC); 1785 1786 if (!task) { 1787 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n"); 1788 return; 1789 } 1790 1791 task->task_done = pm8001_task_done; 1792 1793 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1794 if (res) { 1795 sas_free_task(task); 1796 return; 1797 } 1798 1799 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1800 ccb->device = pm8001_ha_dev; 1801 ccb->ccb_tag = ccb_tag; 1802 ccb->task = task; 1803 1804 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1805 1806 memset(&task_abort, 0, sizeof(task_abort)); 1807 task_abort.abort_all = cpu_to_le32(1); 1808 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1809 task_abort.tag = cpu_to_le32(ccb_tag); 1810 1811 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 1812 sizeof(task_abort), 0); 1813 pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n"); 1814 if (ret) { 1815 sas_free_task(task); 1816 pm8001_tag_free(pm8001_ha, ccb_tag); 1817 } 1818 } 1819 1820 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha, 1821 struct pm8001_device *pm8001_ha_dev) 1822 { 1823 struct sata_start_req sata_cmd; 1824 int res; 1825 u32 ccb_tag; 1826 struct pm8001_ccb_info *ccb; 1827 struct sas_task *task = NULL; 1828 struct host_to_dev_fis fis; 1829 struct domain_device *dev; 1830 struct inbound_queue_table *circularQ; 1831 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1832 1833 task = sas_alloc_slow_task(GFP_ATOMIC); 1834 1835 if (!task) { 1836 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n"); 1837 return; 1838 } 1839 task->task_done = pm8001_task_done; 1840 1841 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1842 if (res) { 1843 sas_free_task(task); 1844 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n"); 1845 return; 1846 } 1847 1848 /* allocate domain device by ourselves as libsas 1849 * is not going to provide any 1850 */ 1851 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1852 if (!dev) { 1853 sas_free_task(task); 1854 pm8001_tag_free(pm8001_ha, ccb_tag); 1855 pm8001_dbg(pm8001_ha, FAIL, 1856 "Domain device cannot be allocated\n"); 1857 return; 1858 } 1859 1860 task->dev = dev; 1861 task->dev->lldd_dev = pm8001_ha_dev; 1862 1863 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1864 ccb->device = pm8001_ha_dev; 1865 ccb->ccb_tag = ccb_tag; 1866 ccb->task = task; 1867 ccb->n_elem = 0; 1868 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1869 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1870 1871 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1872 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1873 1874 /* construct read log FIS */ 1875 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1876 fis.fis_type = 0x27; 1877 fis.flags = 0x80; 1878 fis.command = ATA_CMD_READ_LOG_EXT; 1879 fis.lbal = 0x10; 1880 fis.sector_count = 0x1; 1881 1882 sata_cmd.tag = cpu_to_le32(ccb_tag); 1883 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1884 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9)); 1885 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1886 1887 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 1888 sizeof(sata_cmd), 0); 1889 pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n"); 1890 if (res) { 1891 sas_free_task(task); 1892 pm8001_tag_free(pm8001_ha, ccb_tag); 1893 kfree(dev); 1894 } 1895 } 1896 1897 /** 1898 * mpi_ssp_completion - process the event that FW response to the SSP request. 1899 * @pm8001_ha: our hba card information 1900 * @piomb: the message contents of this outbound message. 1901 * 1902 * When FW has completed a ssp request for example a IO request, after it has 1903 * filled the SG data with the data, it will trigger this event representing 1904 * that he has finished the job; please check the corresponding buffer. 1905 * So we will tell the caller who maybe waiting the result to tell upper layer 1906 * that the task has been finished. 1907 */ 1908 static void 1909 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 1910 { 1911 struct sas_task *t; 1912 struct pm8001_ccb_info *ccb; 1913 unsigned long flags; 1914 u32 status; 1915 u32 param; 1916 u32 tag; 1917 struct ssp_completion_resp *psspPayload; 1918 struct task_status_struct *ts; 1919 struct ssp_response_iu *iu; 1920 struct pm8001_device *pm8001_dev; 1921 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1922 status = le32_to_cpu(psspPayload->status); 1923 tag = le32_to_cpu(psspPayload->tag); 1924 ccb = &pm8001_ha->ccb_info[tag]; 1925 if ((status == IO_ABORTED) && ccb->open_retry) { 1926 /* Being completed by another */ 1927 ccb->open_retry = 0; 1928 return; 1929 } 1930 pm8001_dev = ccb->device; 1931 param = le32_to_cpu(psspPayload->param); 1932 t = ccb->task; 1933 1934 if (status && status != IO_UNDERFLOW) 1935 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); 1936 if (unlikely(!t || !t->lldd_task || !t->dev)) 1937 return; 1938 ts = &t->task_status; 1939 1940 pm8001_dbg(pm8001_ha, DEV, 1941 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t); 1942 1943 /* Print sas address of IO failed device */ 1944 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1945 (status != IO_UNDERFLOW)) 1946 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n", 1947 SAS_ADDR(t->dev->sas_addr)); 1948 1949 switch (status) { 1950 case IO_SUCCESS: 1951 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n", 1952 param); 1953 if (param == 0) { 1954 ts->resp = SAS_TASK_COMPLETE; 1955 ts->stat = SAS_SAM_STAT_GOOD; 1956 } else { 1957 ts->resp = SAS_TASK_COMPLETE; 1958 ts->stat = SAS_PROTO_RESPONSE; 1959 ts->residual = param; 1960 iu = &psspPayload->ssp_resp_iu; 1961 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1962 } 1963 if (pm8001_dev) 1964 atomic_dec(&pm8001_dev->running_req); 1965 break; 1966 case IO_ABORTED: 1967 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 1968 ts->resp = SAS_TASK_COMPLETE; 1969 ts->stat = SAS_ABORTED_TASK; 1970 if (pm8001_dev) 1971 atomic_dec(&pm8001_dev->running_req); 1972 break; 1973 case IO_UNDERFLOW: 1974 /* SSP Completion with error */ 1975 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n", 1976 param); 1977 ts->resp = SAS_TASK_COMPLETE; 1978 ts->stat = SAS_DATA_UNDERRUN; 1979 ts->residual = param; 1980 if (pm8001_dev) 1981 atomic_dec(&pm8001_dev->running_req); 1982 break; 1983 case IO_NO_DEVICE: 1984 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 1985 ts->resp = SAS_TASK_UNDELIVERED; 1986 ts->stat = SAS_PHY_DOWN; 1987 if (pm8001_dev) 1988 atomic_dec(&pm8001_dev->running_req); 1989 break; 1990 case IO_XFER_ERROR_BREAK: 1991 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 1992 ts->resp = SAS_TASK_COMPLETE; 1993 ts->stat = SAS_OPEN_REJECT; 1994 /* Force the midlayer to retry */ 1995 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1996 if (pm8001_dev) 1997 atomic_dec(&pm8001_dev->running_req); 1998 break; 1999 case IO_XFER_ERROR_PHY_NOT_READY: 2000 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2001 ts->resp = SAS_TASK_COMPLETE; 2002 ts->stat = SAS_OPEN_REJECT; 2003 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2004 if (pm8001_dev) 2005 atomic_dec(&pm8001_dev->running_req); 2006 break; 2007 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME: 2008 pm8001_dbg(pm8001_ha, IO, 2009 "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"); 2010 ts->resp = SAS_TASK_COMPLETE; 2011 ts->stat = SAS_OPEN_REJECT; 2012 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2013 if (pm8001_dev) 2014 atomic_dec(&pm8001_dev->running_req); 2015 break; 2016 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2017 pm8001_dbg(pm8001_ha, IO, 2018 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2019 ts->resp = SAS_TASK_COMPLETE; 2020 ts->stat = SAS_OPEN_REJECT; 2021 ts->open_rej_reason = SAS_OREJ_EPROTO; 2022 if (pm8001_dev) 2023 atomic_dec(&pm8001_dev->running_req); 2024 break; 2025 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2026 pm8001_dbg(pm8001_ha, IO, 2027 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2028 ts->resp = SAS_TASK_COMPLETE; 2029 ts->stat = SAS_OPEN_REJECT; 2030 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2031 if (pm8001_dev) 2032 atomic_dec(&pm8001_dev->running_req); 2033 break; 2034 case IO_OPEN_CNX_ERROR_BREAK: 2035 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2036 ts->resp = SAS_TASK_COMPLETE; 2037 ts->stat = SAS_OPEN_REJECT; 2038 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2039 if (pm8001_dev) 2040 atomic_dec(&pm8001_dev->running_req); 2041 break; 2042 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2043 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2044 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2045 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2046 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2047 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2048 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2049 ts->resp = SAS_TASK_COMPLETE; 2050 ts->stat = SAS_OPEN_REJECT; 2051 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2052 if (!t->uldd_task) 2053 pm8001_handle_event(pm8001_ha, 2054 pm8001_dev, 2055 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2056 break; 2057 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2058 pm8001_dbg(pm8001_ha, IO, 2059 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2060 ts->resp = SAS_TASK_COMPLETE; 2061 ts->stat = SAS_OPEN_REJECT; 2062 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2063 if (pm8001_dev) 2064 atomic_dec(&pm8001_dev->running_req); 2065 break; 2066 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2067 pm8001_dbg(pm8001_ha, IO, 2068 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2069 ts->resp = SAS_TASK_COMPLETE; 2070 ts->stat = SAS_OPEN_REJECT; 2071 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2072 if (pm8001_dev) 2073 atomic_dec(&pm8001_dev->running_req); 2074 break; 2075 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2076 pm8001_dbg(pm8001_ha, IO, 2077 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2078 ts->resp = SAS_TASK_UNDELIVERED; 2079 ts->stat = SAS_OPEN_REJECT; 2080 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2081 if (pm8001_dev) 2082 atomic_dec(&pm8001_dev->running_req); 2083 break; 2084 case IO_XFER_ERROR_NAK_RECEIVED: 2085 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2086 ts->resp = SAS_TASK_COMPLETE; 2087 ts->stat = SAS_OPEN_REJECT; 2088 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2089 if (pm8001_dev) 2090 atomic_dec(&pm8001_dev->running_req); 2091 break; 2092 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2093 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2094 ts->resp = SAS_TASK_COMPLETE; 2095 ts->stat = SAS_NAK_R_ERR; 2096 if (pm8001_dev) 2097 atomic_dec(&pm8001_dev->running_req); 2098 break; 2099 case IO_XFER_ERROR_DMA: 2100 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2101 ts->resp = SAS_TASK_COMPLETE; 2102 ts->stat = SAS_OPEN_REJECT; 2103 if (pm8001_dev) 2104 atomic_dec(&pm8001_dev->running_req); 2105 break; 2106 case IO_XFER_OPEN_RETRY_TIMEOUT: 2107 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2108 ts->resp = SAS_TASK_COMPLETE; 2109 ts->stat = SAS_OPEN_REJECT; 2110 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2111 if (pm8001_dev) 2112 atomic_dec(&pm8001_dev->running_req); 2113 break; 2114 case IO_XFER_ERROR_OFFSET_MISMATCH: 2115 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2116 ts->resp = SAS_TASK_COMPLETE; 2117 ts->stat = SAS_OPEN_REJECT; 2118 if (pm8001_dev) 2119 atomic_dec(&pm8001_dev->running_req); 2120 break; 2121 case IO_PORT_IN_RESET: 2122 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2123 ts->resp = SAS_TASK_COMPLETE; 2124 ts->stat = SAS_OPEN_REJECT; 2125 if (pm8001_dev) 2126 atomic_dec(&pm8001_dev->running_req); 2127 break; 2128 case IO_DS_NON_OPERATIONAL: 2129 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2130 ts->resp = SAS_TASK_COMPLETE; 2131 ts->stat = SAS_OPEN_REJECT; 2132 if (!t->uldd_task) 2133 pm8001_handle_event(pm8001_ha, 2134 pm8001_dev, 2135 IO_DS_NON_OPERATIONAL); 2136 break; 2137 case IO_DS_IN_RECOVERY: 2138 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2139 ts->resp = SAS_TASK_COMPLETE; 2140 ts->stat = SAS_OPEN_REJECT; 2141 if (pm8001_dev) 2142 atomic_dec(&pm8001_dev->running_req); 2143 break; 2144 case IO_TM_TAG_NOT_FOUND: 2145 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n"); 2146 ts->resp = SAS_TASK_COMPLETE; 2147 ts->stat = SAS_OPEN_REJECT; 2148 if (pm8001_dev) 2149 atomic_dec(&pm8001_dev->running_req); 2150 break; 2151 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 2152 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"); 2153 ts->resp = SAS_TASK_COMPLETE; 2154 ts->stat = SAS_OPEN_REJECT; 2155 if (pm8001_dev) 2156 atomic_dec(&pm8001_dev->running_req); 2157 break; 2158 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2159 pm8001_dbg(pm8001_ha, IO, 2160 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2161 ts->resp = SAS_TASK_COMPLETE; 2162 ts->stat = SAS_OPEN_REJECT; 2163 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2164 if (pm8001_dev) 2165 atomic_dec(&pm8001_dev->running_req); 2166 break; 2167 default: 2168 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2169 /* not allowed case. Therefore, return failed status */ 2170 ts->resp = SAS_TASK_COMPLETE; 2171 ts->stat = SAS_OPEN_REJECT; 2172 if (pm8001_dev) 2173 atomic_dec(&pm8001_dev->running_req); 2174 break; 2175 } 2176 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ", 2177 psspPayload->ssp_resp_iu.status); 2178 spin_lock_irqsave(&t->task_state_lock, flags); 2179 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2180 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2181 t->task_state_flags |= SAS_TASK_STATE_DONE; 2182 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2183 spin_unlock_irqrestore(&t->task_state_lock, flags); 2184 pm8001_dbg(pm8001_ha, FAIL, 2185 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2186 t, status, ts->resp, ts->stat); 2187 if (t->slow_task) 2188 complete(&t->slow_task->completion); 2189 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2190 } else { 2191 spin_unlock_irqrestore(&t->task_state_lock, flags); 2192 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2193 mb();/* in order to force CPU ordering */ 2194 t->task_done(t); 2195 } 2196 } 2197 2198 /*See the comments for mpi_ssp_completion */ 2199 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 2200 { 2201 struct sas_task *t; 2202 unsigned long flags; 2203 struct task_status_struct *ts; 2204 struct pm8001_ccb_info *ccb; 2205 struct pm8001_device *pm8001_dev; 2206 struct ssp_event_resp *psspPayload = 2207 (struct ssp_event_resp *)(piomb + 4); 2208 u32 event = le32_to_cpu(psspPayload->event); 2209 u32 tag = le32_to_cpu(psspPayload->tag); 2210 u32 port_id = le32_to_cpu(psspPayload->port_id); 2211 2212 ccb = &pm8001_ha->ccb_info[tag]; 2213 t = ccb->task; 2214 pm8001_dev = ccb->device; 2215 if (event) 2216 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); 2217 if (unlikely(!t || !t->lldd_task || !t->dev)) 2218 return; 2219 ts = &t->task_status; 2220 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2221 port_id, tag, event); 2222 switch (event) { 2223 case IO_OVERFLOW: 2224 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2225 ts->resp = SAS_TASK_COMPLETE; 2226 ts->stat = SAS_DATA_OVERRUN; 2227 ts->residual = 0; 2228 if (pm8001_dev) 2229 atomic_dec(&pm8001_dev->running_req); 2230 break; 2231 case IO_XFER_ERROR_BREAK: 2232 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2233 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2234 return; 2235 case IO_XFER_ERROR_PHY_NOT_READY: 2236 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2237 ts->resp = SAS_TASK_COMPLETE; 2238 ts->stat = SAS_OPEN_REJECT; 2239 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2240 break; 2241 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2242 pm8001_dbg(pm8001_ha, IO, 2243 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2244 ts->resp = SAS_TASK_COMPLETE; 2245 ts->stat = SAS_OPEN_REJECT; 2246 ts->open_rej_reason = SAS_OREJ_EPROTO; 2247 break; 2248 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2249 pm8001_dbg(pm8001_ha, IO, 2250 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2251 ts->resp = SAS_TASK_COMPLETE; 2252 ts->stat = SAS_OPEN_REJECT; 2253 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2254 break; 2255 case IO_OPEN_CNX_ERROR_BREAK: 2256 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2257 ts->resp = SAS_TASK_COMPLETE; 2258 ts->stat = SAS_OPEN_REJECT; 2259 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2260 break; 2261 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2262 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2263 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2264 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2265 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2266 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2267 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2268 ts->resp = SAS_TASK_COMPLETE; 2269 ts->stat = SAS_OPEN_REJECT; 2270 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2271 if (!t->uldd_task) 2272 pm8001_handle_event(pm8001_ha, 2273 pm8001_dev, 2274 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2275 break; 2276 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2277 pm8001_dbg(pm8001_ha, IO, 2278 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2279 ts->resp = SAS_TASK_COMPLETE; 2280 ts->stat = SAS_OPEN_REJECT; 2281 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2282 break; 2283 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2284 pm8001_dbg(pm8001_ha, IO, 2285 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2286 ts->resp = SAS_TASK_COMPLETE; 2287 ts->stat = SAS_OPEN_REJECT; 2288 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2289 break; 2290 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2291 pm8001_dbg(pm8001_ha, IO, 2292 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2293 ts->resp = SAS_TASK_COMPLETE; 2294 ts->stat = SAS_OPEN_REJECT; 2295 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2296 break; 2297 case IO_XFER_ERROR_NAK_RECEIVED: 2298 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2299 ts->resp = SAS_TASK_COMPLETE; 2300 ts->stat = SAS_OPEN_REJECT; 2301 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2302 break; 2303 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2304 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2305 ts->resp = SAS_TASK_COMPLETE; 2306 ts->stat = SAS_NAK_R_ERR; 2307 break; 2308 case IO_XFER_OPEN_RETRY_TIMEOUT: 2309 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2310 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2311 return; 2312 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2313 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2314 ts->resp = SAS_TASK_COMPLETE; 2315 ts->stat = SAS_DATA_OVERRUN; 2316 break; 2317 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2318 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2319 ts->resp = SAS_TASK_COMPLETE; 2320 ts->stat = SAS_DATA_OVERRUN; 2321 break; 2322 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2323 pm8001_dbg(pm8001_ha, IO, 2324 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2325 ts->resp = SAS_TASK_COMPLETE; 2326 ts->stat = SAS_DATA_OVERRUN; 2327 break; 2328 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2329 pm8001_dbg(pm8001_ha, IO, 2330 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"); 2331 ts->resp = SAS_TASK_COMPLETE; 2332 ts->stat = SAS_DATA_OVERRUN; 2333 break; 2334 case IO_XFER_ERROR_OFFSET_MISMATCH: 2335 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2336 ts->resp = SAS_TASK_COMPLETE; 2337 ts->stat = SAS_DATA_OVERRUN; 2338 break; 2339 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2340 pm8001_dbg(pm8001_ha, IO, 2341 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2342 ts->resp = SAS_TASK_COMPLETE; 2343 ts->stat = SAS_DATA_OVERRUN; 2344 break; 2345 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2346 pm8001_dbg(pm8001_ha, IOERR, 2347 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2348 /* TBC: used default set values */ 2349 ts->resp = SAS_TASK_COMPLETE; 2350 ts->stat = SAS_DATA_OVERRUN; 2351 break; 2352 case IO_XFER_CMD_FRAME_ISSUED: 2353 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2354 return; 2355 default: 2356 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2357 /* not allowed case. Therefore, return failed status */ 2358 ts->resp = SAS_TASK_COMPLETE; 2359 ts->stat = SAS_DATA_OVERRUN; 2360 break; 2361 } 2362 spin_lock_irqsave(&t->task_state_lock, flags); 2363 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2364 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2365 t->task_state_flags |= SAS_TASK_STATE_DONE; 2366 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2367 spin_unlock_irqrestore(&t->task_state_lock, flags); 2368 pm8001_dbg(pm8001_ha, FAIL, 2369 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2370 t, event, ts->resp, ts->stat); 2371 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2372 } else { 2373 spin_unlock_irqrestore(&t->task_state_lock, flags); 2374 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2375 mb();/* in order to force CPU ordering */ 2376 t->task_done(t); 2377 } 2378 } 2379 2380 /*See the comments for mpi_ssp_completion */ 2381 static void 2382 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, 2383 struct outbound_queue_table *circularQ, void *piomb) 2384 { 2385 struct sas_task *t; 2386 struct pm8001_ccb_info *ccb; 2387 u32 param; 2388 u32 status; 2389 u32 tag; 2390 int i, j; 2391 u8 sata_addr_low[4]; 2392 u32 temp_sata_addr_low, temp_sata_addr_hi; 2393 u8 sata_addr_hi[4]; 2394 struct sata_completion_resp *psataPayload; 2395 struct task_status_struct *ts; 2396 struct ata_task_resp *resp ; 2397 u32 *sata_resp; 2398 struct pm8001_device *pm8001_dev; 2399 unsigned long flags; 2400 2401 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2402 status = le32_to_cpu(psataPayload->status); 2403 tag = le32_to_cpu(psataPayload->tag); 2404 2405 if (!tag) { 2406 pm8001_dbg(pm8001_ha, FAIL, "tag null\n"); 2407 return; 2408 } 2409 ccb = &pm8001_ha->ccb_info[tag]; 2410 param = le32_to_cpu(psataPayload->param); 2411 if (ccb) { 2412 t = ccb->task; 2413 pm8001_dev = ccb->device; 2414 } else { 2415 pm8001_dbg(pm8001_ha, FAIL, "ccb null\n"); 2416 return; 2417 } 2418 2419 if (t) { 2420 if (t->dev && (t->dev->lldd_dev)) 2421 pm8001_dev = t->dev->lldd_dev; 2422 } else { 2423 pm8001_dbg(pm8001_ha, FAIL, "task null\n"); 2424 return; 2425 } 2426 2427 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2428 && unlikely(!t || !t->lldd_task || !t->dev)) { 2429 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2430 return; 2431 } 2432 2433 ts = &t->task_status; 2434 if (!ts) { 2435 pm8001_dbg(pm8001_ha, FAIL, "ts null\n"); 2436 return; 2437 } 2438 2439 if (status != IO_SUCCESS) { 2440 pm8001_dbg(pm8001_ha, FAIL, 2441 "IO failed device_id %u status 0x%x tag %d\n", 2442 pm8001_dev->device_id, status, tag); 2443 } 2444 2445 /* Print sas address of IO failed device */ 2446 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2447 (status != IO_UNDERFLOW)) { 2448 if (!((t->dev->parent) && 2449 (dev_is_expander(t->dev->parent->dev_type)))) { 2450 for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++) 2451 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2452 for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++) 2453 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2454 memcpy(&temp_sata_addr_low, sata_addr_low, 2455 sizeof(sata_addr_low)); 2456 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2457 sizeof(sata_addr_hi)); 2458 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2459 |((temp_sata_addr_hi << 8) & 2460 0xff0000) | 2461 ((temp_sata_addr_hi >> 8) 2462 & 0xff00) | 2463 ((temp_sata_addr_hi << 24) & 2464 0xff000000)); 2465 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2466 & 0xff) | 2467 ((temp_sata_addr_low << 8) 2468 & 0xff0000) | 2469 ((temp_sata_addr_low >> 8) 2470 & 0xff00) | 2471 ((temp_sata_addr_low << 24) 2472 & 0xff000000)) + 2473 pm8001_dev->attached_phy + 2474 0x10); 2475 pm8001_dbg(pm8001_ha, FAIL, 2476 "SAS Address of IO Failure Drive:%08x%08x\n", 2477 temp_sata_addr_hi, 2478 temp_sata_addr_low); 2479 2480 } else { 2481 pm8001_dbg(pm8001_ha, FAIL, 2482 "SAS Address of IO Failure Drive:%016llx\n", 2483 SAS_ADDR(t->dev->sas_addr)); 2484 } 2485 } 2486 switch (status) { 2487 case IO_SUCCESS: 2488 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2489 if (param == 0) { 2490 ts->resp = SAS_TASK_COMPLETE; 2491 ts->stat = SAS_SAM_STAT_GOOD; 2492 /* check if response is for SEND READ LOG */ 2493 if (pm8001_dev && 2494 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2495 /* set new bit for abort_all */ 2496 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2497 /* clear bit for read log */ 2498 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2499 pm80xx_send_abort_all(pm8001_ha, pm8001_dev); 2500 /* Free the tag */ 2501 pm8001_tag_free(pm8001_ha, tag); 2502 sas_free_task(t); 2503 return; 2504 } 2505 } else { 2506 u8 len; 2507 ts->resp = SAS_TASK_COMPLETE; 2508 ts->stat = SAS_PROTO_RESPONSE; 2509 ts->residual = param; 2510 pm8001_dbg(pm8001_ha, IO, 2511 "SAS_PROTO_RESPONSE len = %d\n", 2512 param); 2513 sata_resp = &psataPayload->sata_resp[0]; 2514 resp = (struct ata_task_resp *)ts->buf; 2515 if (t->ata_task.dma_xfer == 0 && 2516 t->data_dir == DMA_FROM_DEVICE) { 2517 len = sizeof(struct pio_setup_fis); 2518 pm8001_dbg(pm8001_ha, IO, 2519 "PIO read len = %d\n", len); 2520 } else if (t->ata_task.use_ncq) { 2521 len = sizeof(struct set_dev_bits_fis); 2522 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n", 2523 len); 2524 } else { 2525 len = sizeof(struct dev_to_host_fis); 2526 pm8001_dbg(pm8001_ha, IO, "other len = %d\n", 2527 len); 2528 } 2529 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2530 resp->frame_len = len; 2531 memcpy(&resp->ending_fis[0], sata_resp, len); 2532 ts->buf_valid_size = sizeof(*resp); 2533 } else 2534 pm8001_dbg(pm8001_ha, IO, 2535 "response too large\n"); 2536 } 2537 if (pm8001_dev) 2538 atomic_dec(&pm8001_dev->running_req); 2539 break; 2540 case IO_ABORTED: 2541 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 2542 ts->resp = SAS_TASK_COMPLETE; 2543 ts->stat = SAS_ABORTED_TASK; 2544 if (pm8001_dev) 2545 atomic_dec(&pm8001_dev->running_req); 2546 break; 2547 /* following cases are to do cases */ 2548 case IO_UNDERFLOW: 2549 /* SATA Completion with error */ 2550 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param); 2551 ts->resp = SAS_TASK_COMPLETE; 2552 ts->stat = SAS_DATA_UNDERRUN; 2553 ts->residual = param; 2554 if (pm8001_dev) 2555 atomic_dec(&pm8001_dev->running_req); 2556 break; 2557 case IO_NO_DEVICE: 2558 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2559 ts->resp = SAS_TASK_UNDELIVERED; 2560 ts->stat = SAS_PHY_DOWN; 2561 if (pm8001_dev) 2562 atomic_dec(&pm8001_dev->running_req); 2563 break; 2564 case IO_XFER_ERROR_BREAK: 2565 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2566 ts->resp = SAS_TASK_COMPLETE; 2567 ts->stat = SAS_INTERRUPTED; 2568 if (pm8001_dev) 2569 atomic_dec(&pm8001_dev->running_req); 2570 break; 2571 case IO_XFER_ERROR_PHY_NOT_READY: 2572 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2573 ts->resp = SAS_TASK_COMPLETE; 2574 ts->stat = SAS_OPEN_REJECT; 2575 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2576 if (pm8001_dev) 2577 atomic_dec(&pm8001_dev->running_req); 2578 break; 2579 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2580 pm8001_dbg(pm8001_ha, IO, 2581 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2582 ts->resp = SAS_TASK_COMPLETE; 2583 ts->stat = SAS_OPEN_REJECT; 2584 ts->open_rej_reason = SAS_OREJ_EPROTO; 2585 if (pm8001_dev) 2586 atomic_dec(&pm8001_dev->running_req); 2587 break; 2588 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2589 pm8001_dbg(pm8001_ha, IO, 2590 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2591 ts->resp = SAS_TASK_COMPLETE; 2592 ts->stat = SAS_OPEN_REJECT; 2593 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2594 if (pm8001_dev) 2595 atomic_dec(&pm8001_dev->running_req); 2596 break; 2597 case IO_OPEN_CNX_ERROR_BREAK: 2598 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2599 ts->resp = SAS_TASK_COMPLETE; 2600 ts->stat = SAS_OPEN_REJECT; 2601 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2602 if (pm8001_dev) 2603 atomic_dec(&pm8001_dev->running_req); 2604 break; 2605 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2606 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2607 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2608 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2609 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2610 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2611 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2612 ts->resp = SAS_TASK_COMPLETE; 2613 ts->stat = SAS_DEV_NO_RESPONSE; 2614 if (!t->uldd_task) { 2615 pm8001_handle_event(pm8001_ha, 2616 pm8001_dev, 2617 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2618 ts->resp = SAS_TASK_UNDELIVERED; 2619 ts->stat = SAS_QUEUE_FULL; 2620 spin_unlock_irqrestore(&circularQ->oq_lock, 2621 circularQ->lock_flags); 2622 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2623 spin_lock_irqsave(&circularQ->oq_lock, 2624 circularQ->lock_flags); 2625 return; 2626 } 2627 break; 2628 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2629 pm8001_dbg(pm8001_ha, IO, 2630 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2631 ts->resp = SAS_TASK_UNDELIVERED; 2632 ts->stat = SAS_OPEN_REJECT; 2633 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2634 if (!t->uldd_task) { 2635 pm8001_handle_event(pm8001_ha, 2636 pm8001_dev, 2637 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2638 ts->resp = SAS_TASK_UNDELIVERED; 2639 ts->stat = SAS_QUEUE_FULL; 2640 spin_unlock_irqrestore(&circularQ->oq_lock, 2641 circularQ->lock_flags); 2642 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2643 spin_lock_irqsave(&circularQ->oq_lock, 2644 circularQ->lock_flags); 2645 return; 2646 } 2647 break; 2648 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2649 pm8001_dbg(pm8001_ha, IO, 2650 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2651 ts->resp = SAS_TASK_COMPLETE; 2652 ts->stat = SAS_OPEN_REJECT; 2653 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2654 if (pm8001_dev) 2655 atomic_dec(&pm8001_dev->running_req); 2656 break; 2657 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2658 pm8001_dbg(pm8001_ha, IO, 2659 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"); 2660 ts->resp = SAS_TASK_COMPLETE; 2661 ts->stat = SAS_DEV_NO_RESPONSE; 2662 if (!t->uldd_task) { 2663 pm8001_handle_event(pm8001_ha, 2664 pm8001_dev, 2665 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2666 ts->resp = SAS_TASK_UNDELIVERED; 2667 ts->stat = SAS_QUEUE_FULL; 2668 spin_unlock_irqrestore(&circularQ->oq_lock, 2669 circularQ->lock_flags); 2670 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2671 spin_lock_irqsave(&circularQ->oq_lock, 2672 circularQ->lock_flags); 2673 return; 2674 } 2675 break; 2676 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2677 pm8001_dbg(pm8001_ha, IO, 2678 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2679 ts->resp = SAS_TASK_COMPLETE; 2680 ts->stat = SAS_OPEN_REJECT; 2681 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2682 if (pm8001_dev) 2683 atomic_dec(&pm8001_dev->running_req); 2684 break; 2685 case IO_XFER_ERROR_NAK_RECEIVED: 2686 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2687 ts->resp = SAS_TASK_COMPLETE; 2688 ts->stat = SAS_NAK_R_ERR; 2689 if (pm8001_dev) 2690 atomic_dec(&pm8001_dev->running_req); 2691 break; 2692 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2693 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2694 ts->resp = SAS_TASK_COMPLETE; 2695 ts->stat = SAS_NAK_R_ERR; 2696 if (pm8001_dev) 2697 atomic_dec(&pm8001_dev->running_req); 2698 break; 2699 case IO_XFER_ERROR_DMA: 2700 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2701 ts->resp = SAS_TASK_COMPLETE; 2702 ts->stat = SAS_ABORTED_TASK; 2703 if (pm8001_dev) 2704 atomic_dec(&pm8001_dev->running_req); 2705 break; 2706 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2707 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"); 2708 ts->resp = SAS_TASK_UNDELIVERED; 2709 ts->stat = SAS_DEV_NO_RESPONSE; 2710 if (pm8001_dev) 2711 atomic_dec(&pm8001_dev->running_req); 2712 break; 2713 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2714 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2715 ts->resp = SAS_TASK_COMPLETE; 2716 ts->stat = SAS_DATA_UNDERRUN; 2717 if (pm8001_dev) 2718 atomic_dec(&pm8001_dev->running_req); 2719 break; 2720 case IO_XFER_OPEN_RETRY_TIMEOUT: 2721 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2722 ts->resp = SAS_TASK_COMPLETE; 2723 ts->stat = SAS_OPEN_TO; 2724 if (pm8001_dev) 2725 atomic_dec(&pm8001_dev->running_req); 2726 break; 2727 case IO_PORT_IN_RESET: 2728 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2729 ts->resp = SAS_TASK_COMPLETE; 2730 ts->stat = SAS_DEV_NO_RESPONSE; 2731 if (pm8001_dev) 2732 atomic_dec(&pm8001_dev->running_req); 2733 break; 2734 case IO_DS_NON_OPERATIONAL: 2735 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2736 ts->resp = SAS_TASK_COMPLETE; 2737 ts->stat = SAS_DEV_NO_RESPONSE; 2738 if (!t->uldd_task) { 2739 pm8001_handle_event(pm8001_ha, pm8001_dev, 2740 IO_DS_NON_OPERATIONAL); 2741 ts->resp = SAS_TASK_UNDELIVERED; 2742 ts->stat = SAS_QUEUE_FULL; 2743 spin_unlock_irqrestore(&circularQ->oq_lock, 2744 circularQ->lock_flags); 2745 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2746 spin_lock_irqsave(&circularQ->oq_lock, 2747 circularQ->lock_flags); 2748 return; 2749 } 2750 break; 2751 case IO_DS_IN_RECOVERY: 2752 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2753 ts->resp = SAS_TASK_COMPLETE; 2754 ts->stat = SAS_DEV_NO_RESPONSE; 2755 if (pm8001_dev) 2756 atomic_dec(&pm8001_dev->running_req); 2757 break; 2758 case IO_DS_IN_ERROR: 2759 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n"); 2760 ts->resp = SAS_TASK_COMPLETE; 2761 ts->stat = SAS_DEV_NO_RESPONSE; 2762 if (!t->uldd_task) { 2763 pm8001_handle_event(pm8001_ha, pm8001_dev, 2764 IO_DS_IN_ERROR); 2765 ts->resp = SAS_TASK_UNDELIVERED; 2766 ts->stat = SAS_QUEUE_FULL; 2767 spin_unlock_irqrestore(&circularQ->oq_lock, 2768 circularQ->lock_flags); 2769 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2770 spin_lock_irqsave(&circularQ->oq_lock, 2771 circularQ->lock_flags); 2772 return; 2773 } 2774 break; 2775 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2776 pm8001_dbg(pm8001_ha, IO, 2777 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2778 ts->resp = SAS_TASK_COMPLETE; 2779 ts->stat = SAS_OPEN_REJECT; 2780 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2781 if (pm8001_dev) 2782 atomic_dec(&pm8001_dev->running_req); 2783 break; 2784 default: 2785 pm8001_dbg(pm8001_ha, DEVIO, 2786 "Unknown status device_id %u status 0x%x tag %d\n", 2787 pm8001_dev->device_id, status, tag); 2788 /* not allowed case. Therefore, return failed status */ 2789 ts->resp = SAS_TASK_COMPLETE; 2790 ts->stat = SAS_DEV_NO_RESPONSE; 2791 if (pm8001_dev) 2792 atomic_dec(&pm8001_dev->running_req); 2793 break; 2794 } 2795 spin_lock_irqsave(&t->task_state_lock, flags); 2796 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2797 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2798 t->task_state_flags |= SAS_TASK_STATE_DONE; 2799 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2800 spin_unlock_irqrestore(&t->task_state_lock, flags); 2801 pm8001_dbg(pm8001_ha, FAIL, 2802 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2803 t, status, ts->resp, ts->stat); 2804 if (t->slow_task) 2805 complete(&t->slow_task->completion); 2806 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2807 } else { 2808 spin_unlock_irqrestore(&t->task_state_lock, flags); 2809 spin_unlock_irqrestore(&circularQ->oq_lock, 2810 circularQ->lock_flags); 2811 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2812 spin_lock_irqsave(&circularQ->oq_lock, 2813 circularQ->lock_flags); 2814 } 2815 } 2816 2817 /*See the comments for mpi_ssp_completion */ 2818 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, 2819 struct outbound_queue_table *circularQ, void *piomb) 2820 { 2821 struct sas_task *t; 2822 struct task_status_struct *ts; 2823 struct pm8001_ccb_info *ccb; 2824 struct pm8001_device *pm8001_dev; 2825 struct sata_event_resp *psataPayload = 2826 (struct sata_event_resp *)(piomb + 4); 2827 u32 event = le32_to_cpu(psataPayload->event); 2828 u32 tag = le32_to_cpu(psataPayload->tag); 2829 u32 port_id = le32_to_cpu(psataPayload->port_id); 2830 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2831 unsigned long flags; 2832 2833 ccb = &pm8001_ha->ccb_info[tag]; 2834 2835 if (ccb) { 2836 t = ccb->task; 2837 pm8001_dev = ccb->device; 2838 } else { 2839 pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n"); 2840 return; 2841 } 2842 if (event) 2843 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); 2844 2845 /* Check if this is NCQ error */ 2846 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2847 /* find device using device id */ 2848 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2849 /* send read log extension */ 2850 if (pm8001_dev) 2851 pm80xx_send_read_log(pm8001_ha, pm8001_dev); 2852 return; 2853 } 2854 2855 if (unlikely(!t || !t->lldd_task || !t->dev)) { 2856 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2857 return; 2858 } 2859 2860 ts = &t->task_status; 2861 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2862 port_id, tag, event); 2863 switch (event) { 2864 case IO_OVERFLOW: 2865 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2866 ts->resp = SAS_TASK_COMPLETE; 2867 ts->stat = SAS_DATA_OVERRUN; 2868 ts->residual = 0; 2869 if (pm8001_dev) 2870 atomic_dec(&pm8001_dev->running_req); 2871 break; 2872 case IO_XFER_ERROR_BREAK: 2873 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2874 ts->resp = SAS_TASK_COMPLETE; 2875 ts->stat = SAS_INTERRUPTED; 2876 break; 2877 case IO_XFER_ERROR_PHY_NOT_READY: 2878 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2879 ts->resp = SAS_TASK_COMPLETE; 2880 ts->stat = SAS_OPEN_REJECT; 2881 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2882 break; 2883 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2884 pm8001_dbg(pm8001_ha, IO, 2885 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2886 ts->resp = SAS_TASK_COMPLETE; 2887 ts->stat = SAS_OPEN_REJECT; 2888 ts->open_rej_reason = SAS_OREJ_EPROTO; 2889 break; 2890 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2891 pm8001_dbg(pm8001_ha, IO, 2892 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2893 ts->resp = SAS_TASK_COMPLETE; 2894 ts->stat = SAS_OPEN_REJECT; 2895 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2896 break; 2897 case IO_OPEN_CNX_ERROR_BREAK: 2898 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2899 ts->resp = SAS_TASK_COMPLETE; 2900 ts->stat = SAS_OPEN_REJECT; 2901 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2902 break; 2903 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2904 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2905 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2906 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2907 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2908 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2909 pm8001_dbg(pm8001_ha, FAIL, 2910 "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2911 ts->resp = SAS_TASK_UNDELIVERED; 2912 ts->stat = SAS_DEV_NO_RESPONSE; 2913 if (!t->uldd_task) { 2914 pm8001_handle_event(pm8001_ha, 2915 pm8001_dev, 2916 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2917 ts->resp = SAS_TASK_COMPLETE; 2918 ts->stat = SAS_QUEUE_FULL; 2919 spin_unlock_irqrestore(&circularQ->oq_lock, 2920 circularQ->lock_flags); 2921 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2922 spin_lock_irqsave(&circularQ->oq_lock, 2923 circularQ->lock_flags); 2924 return; 2925 } 2926 break; 2927 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2928 pm8001_dbg(pm8001_ha, IO, 2929 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2930 ts->resp = SAS_TASK_UNDELIVERED; 2931 ts->stat = SAS_OPEN_REJECT; 2932 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2933 break; 2934 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2935 pm8001_dbg(pm8001_ha, IO, 2936 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2937 ts->resp = SAS_TASK_COMPLETE; 2938 ts->stat = SAS_OPEN_REJECT; 2939 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2940 break; 2941 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2942 pm8001_dbg(pm8001_ha, IO, 2943 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2944 ts->resp = SAS_TASK_COMPLETE; 2945 ts->stat = SAS_OPEN_REJECT; 2946 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2947 break; 2948 case IO_XFER_ERROR_NAK_RECEIVED: 2949 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2950 ts->resp = SAS_TASK_COMPLETE; 2951 ts->stat = SAS_NAK_R_ERR; 2952 break; 2953 case IO_XFER_ERROR_PEER_ABORTED: 2954 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n"); 2955 ts->resp = SAS_TASK_COMPLETE; 2956 ts->stat = SAS_NAK_R_ERR; 2957 break; 2958 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2959 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2960 ts->resp = SAS_TASK_COMPLETE; 2961 ts->stat = SAS_DATA_UNDERRUN; 2962 break; 2963 case IO_XFER_OPEN_RETRY_TIMEOUT: 2964 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2965 ts->resp = SAS_TASK_COMPLETE; 2966 ts->stat = SAS_OPEN_TO; 2967 break; 2968 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2969 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2970 ts->resp = SAS_TASK_COMPLETE; 2971 ts->stat = SAS_OPEN_TO; 2972 break; 2973 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2974 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2975 ts->resp = SAS_TASK_COMPLETE; 2976 ts->stat = SAS_OPEN_TO; 2977 break; 2978 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2979 pm8001_dbg(pm8001_ha, IO, 2980 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2981 ts->resp = SAS_TASK_COMPLETE; 2982 ts->stat = SAS_OPEN_TO; 2983 break; 2984 case IO_XFER_ERROR_OFFSET_MISMATCH: 2985 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2986 ts->resp = SAS_TASK_COMPLETE; 2987 ts->stat = SAS_OPEN_TO; 2988 break; 2989 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2990 pm8001_dbg(pm8001_ha, IO, 2991 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2992 ts->resp = SAS_TASK_COMPLETE; 2993 ts->stat = SAS_OPEN_TO; 2994 break; 2995 case IO_XFER_CMD_FRAME_ISSUED: 2996 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2997 break; 2998 case IO_XFER_PIO_SETUP_ERROR: 2999 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n"); 3000 ts->resp = SAS_TASK_COMPLETE; 3001 ts->stat = SAS_OPEN_TO; 3002 break; 3003 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 3004 pm8001_dbg(pm8001_ha, FAIL, 3005 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 3006 /* TBC: used default set values */ 3007 ts->resp = SAS_TASK_COMPLETE; 3008 ts->stat = SAS_OPEN_TO; 3009 break; 3010 case IO_XFER_DMA_ACTIVATE_TIMEOUT: 3011 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n"); 3012 /* TBC: used default set values */ 3013 ts->resp = SAS_TASK_COMPLETE; 3014 ts->stat = SAS_OPEN_TO; 3015 break; 3016 default: 3017 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event); 3018 /* not allowed case. Therefore, return failed status */ 3019 ts->resp = SAS_TASK_COMPLETE; 3020 ts->stat = SAS_OPEN_TO; 3021 break; 3022 } 3023 spin_lock_irqsave(&t->task_state_lock, flags); 3024 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3025 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3026 t->task_state_flags |= SAS_TASK_STATE_DONE; 3027 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3028 spin_unlock_irqrestore(&t->task_state_lock, flags); 3029 pm8001_dbg(pm8001_ha, FAIL, 3030 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 3031 t, event, ts->resp, ts->stat); 3032 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3033 } else { 3034 spin_unlock_irqrestore(&t->task_state_lock, flags); 3035 spin_unlock_irqrestore(&circularQ->oq_lock, 3036 circularQ->lock_flags); 3037 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 3038 spin_lock_irqsave(&circularQ->oq_lock, 3039 circularQ->lock_flags); 3040 } 3041 } 3042 3043 /*See the comments for mpi_ssp_completion */ 3044 static void 3045 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 3046 { 3047 u32 param, i; 3048 struct sas_task *t; 3049 struct pm8001_ccb_info *ccb; 3050 unsigned long flags; 3051 u32 status; 3052 u32 tag; 3053 struct smp_completion_resp *psmpPayload; 3054 struct task_status_struct *ts; 3055 struct pm8001_device *pm8001_dev; 3056 char *pdma_respaddr = NULL; 3057 3058 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 3059 status = le32_to_cpu(psmpPayload->status); 3060 tag = le32_to_cpu(psmpPayload->tag); 3061 3062 ccb = &pm8001_ha->ccb_info[tag]; 3063 param = le32_to_cpu(psmpPayload->param); 3064 t = ccb->task; 3065 ts = &t->task_status; 3066 pm8001_dev = ccb->device; 3067 if (status) 3068 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); 3069 if (unlikely(!t || !t->lldd_task || !t->dev)) 3070 return; 3071 3072 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status); 3073 3074 switch (status) { 3075 3076 case IO_SUCCESS: 3077 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 3078 ts->resp = SAS_TASK_COMPLETE; 3079 ts->stat = SAS_SAM_STAT_GOOD; 3080 if (pm8001_dev) 3081 atomic_dec(&pm8001_dev->running_req); 3082 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 3083 pm8001_dbg(pm8001_ha, IO, 3084 "DIRECT RESPONSE Length:%d\n", 3085 param); 3086 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64 3087 ((u64)sg_dma_address 3088 (&t->smp_task.smp_resp)))); 3089 for (i = 0; i < param; i++) { 3090 *(pdma_respaddr+i) = psmpPayload->_r_a[i]; 3091 pm8001_dbg(pm8001_ha, IO, 3092 "SMP Byte%d DMA data 0x%x psmp 0x%x\n", 3093 i, *(pdma_respaddr + i), 3094 psmpPayload->_r_a[i]); 3095 } 3096 } 3097 break; 3098 case IO_ABORTED: 3099 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n"); 3100 ts->resp = SAS_TASK_COMPLETE; 3101 ts->stat = SAS_ABORTED_TASK; 3102 if (pm8001_dev) 3103 atomic_dec(&pm8001_dev->running_req); 3104 break; 3105 case IO_OVERFLOW: 3106 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 3107 ts->resp = SAS_TASK_COMPLETE; 3108 ts->stat = SAS_DATA_OVERRUN; 3109 ts->residual = 0; 3110 if (pm8001_dev) 3111 atomic_dec(&pm8001_dev->running_req); 3112 break; 3113 case IO_NO_DEVICE: 3114 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 3115 ts->resp = SAS_TASK_COMPLETE; 3116 ts->stat = SAS_PHY_DOWN; 3117 break; 3118 case IO_ERROR_HW_TIMEOUT: 3119 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n"); 3120 ts->resp = SAS_TASK_COMPLETE; 3121 ts->stat = SAS_SAM_STAT_BUSY; 3122 break; 3123 case IO_XFER_ERROR_BREAK: 3124 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 3125 ts->resp = SAS_TASK_COMPLETE; 3126 ts->stat = SAS_SAM_STAT_BUSY; 3127 break; 3128 case IO_XFER_ERROR_PHY_NOT_READY: 3129 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 3130 ts->resp = SAS_TASK_COMPLETE; 3131 ts->stat = SAS_SAM_STAT_BUSY; 3132 break; 3133 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3134 pm8001_dbg(pm8001_ha, IO, 3135 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 3136 ts->resp = SAS_TASK_COMPLETE; 3137 ts->stat = SAS_OPEN_REJECT; 3138 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3139 break; 3140 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3141 pm8001_dbg(pm8001_ha, IO, 3142 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 3143 ts->resp = SAS_TASK_COMPLETE; 3144 ts->stat = SAS_OPEN_REJECT; 3145 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3146 break; 3147 case IO_OPEN_CNX_ERROR_BREAK: 3148 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 3149 ts->resp = SAS_TASK_COMPLETE; 3150 ts->stat = SAS_OPEN_REJECT; 3151 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 3152 break; 3153 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3154 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 3155 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 3156 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 3157 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 3158 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 3159 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 3160 ts->resp = SAS_TASK_COMPLETE; 3161 ts->stat = SAS_OPEN_REJECT; 3162 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3163 pm8001_handle_event(pm8001_ha, 3164 pm8001_dev, 3165 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 3166 break; 3167 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3168 pm8001_dbg(pm8001_ha, IO, 3169 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 3170 ts->resp = SAS_TASK_COMPLETE; 3171 ts->stat = SAS_OPEN_REJECT; 3172 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 3173 break; 3174 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3175 pm8001_dbg(pm8001_ha, IO, 3176 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 3177 ts->resp = SAS_TASK_COMPLETE; 3178 ts->stat = SAS_OPEN_REJECT; 3179 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 3180 break; 3181 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3182 pm8001_dbg(pm8001_ha, IO, 3183 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 3184 ts->resp = SAS_TASK_COMPLETE; 3185 ts->stat = SAS_OPEN_REJECT; 3186 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 3187 break; 3188 case IO_XFER_ERROR_RX_FRAME: 3189 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n"); 3190 ts->resp = SAS_TASK_COMPLETE; 3191 ts->stat = SAS_DEV_NO_RESPONSE; 3192 break; 3193 case IO_XFER_OPEN_RETRY_TIMEOUT: 3194 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 3195 ts->resp = SAS_TASK_COMPLETE; 3196 ts->stat = SAS_OPEN_REJECT; 3197 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3198 break; 3199 case IO_ERROR_INTERNAL_SMP_RESOURCE: 3200 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n"); 3201 ts->resp = SAS_TASK_COMPLETE; 3202 ts->stat = SAS_QUEUE_FULL; 3203 break; 3204 case IO_PORT_IN_RESET: 3205 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 3206 ts->resp = SAS_TASK_COMPLETE; 3207 ts->stat = SAS_OPEN_REJECT; 3208 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3209 break; 3210 case IO_DS_NON_OPERATIONAL: 3211 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 3212 ts->resp = SAS_TASK_COMPLETE; 3213 ts->stat = SAS_DEV_NO_RESPONSE; 3214 break; 3215 case IO_DS_IN_RECOVERY: 3216 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 3217 ts->resp = SAS_TASK_COMPLETE; 3218 ts->stat = SAS_OPEN_REJECT; 3219 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3220 break; 3221 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3222 pm8001_dbg(pm8001_ha, IO, 3223 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 3224 ts->resp = SAS_TASK_COMPLETE; 3225 ts->stat = SAS_OPEN_REJECT; 3226 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3227 break; 3228 default: 3229 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 3230 ts->resp = SAS_TASK_COMPLETE; 3231 ts->stat = SAS_DEV_NO_RESPONSE; 3232 /* not allowed case. Therefore, return failed status */ 3233 break; 3234 } 3235 spin_lock_irqsave(&t->task_state_lock, flags); 3236 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3237 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3238 t->task_state_flags |= SAS_TASK_STATE_DONE; 3239 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3240 spin_unlock_irqrestore(&t->task_state_lock, flags); 3241 pm8001_dbg(pm8001_ha, FAIL, 3242 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n", 3243 t, status, ts->resp, ts->stat); 3244 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3245 } else { 3246 spin_unlock_irqrestore(&t->task_state_lock, flags); 3247 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3248 mb();/* in order to force CPU ordering */ 3249 t->task_done(t); 3250 } 3251 } 3252 3253 /** 3254 * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW. 3255 * @pm8001_ha: our hba card information 3256 * @Qnum: the outbound queue message number. 3257 * @SEA: source of event to ack 3258 * @port_id: port id. 3259 * @phyId: phy id. 3260 * @param0: parameter 0. 3261 * @param1: parameter 1. 3262 */ 3263 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3264 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3265 { 3266 struct hw_event_ack_req payload; 3267 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3268 3269 struct inbound_queue_table *circularQ; 3270 3271 memset((u8 *)&payload, 0, sizeof(payload)); 3272 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 3273 payload.tag = cpu_to_le32(1); 3274 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3275 ((phyId & 0xFF) << 24) | (port_id & 0xFF)); 3276 payload.param0 = cpu_to_le32(param0); 3277 payload.param1 = cpu_to_le32(param1); 3278 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 3279 sizeof(payload), 0); 3280 } 3281 3282 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3283 u32 phyId, u32 phy_op); 3284 3285 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha, 3286 void *piomb) 3287 { 3288 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4); 3289 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3290 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3291 u32 lr_status_evt_portid = 3292 le32_to_cpu(pPayload->lr_status_evt_portid); 3293 u8 deviceType = pPayload->sas_identify.dev_type; 3294 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3295 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3296 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3297 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3298 3299 if (deviceType == SAS_END_DEVICE) { 3300 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3301 PHY_NOTIFY_ENABLE_SPINUP); 3302 } 3303 3304 port->wide_port_phymap |= (1U << phy_id); 3305 pm8001_get_lrate_mode(phy, link_rate); 3306 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3307 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3308 phy->phy_attached = 1; 3309 } 3310 3311 /** 3312 * hw_event_sas_phy_up - FW tells me a SAS phy up event. 3313 * @pm8001_ha: our hba card information 3314 * @piomb: IO message buffer 3315 */ 3316 static void 3317 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3318 { 3319 struct hw_event_resp *pPayload = 3320 (struct hw_event_resp *)(piomb + 4); 3321 u32 lr_status_evt_portid = 3322 le32_to_cpu(pPayload->lr_status_evt_portid); 3323 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3324 3325 u8 link_rate = 3326 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3327 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3328 u8 phy_id = 3329 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3330 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3331 3332 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3333 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3334 unsigned long flags; 3335 u8 deviceType = pPayload->sas_identify.dev_type; 3336 phy->port = port; 3337 port->port_id = port_id; 3338 port->port_state = portstate; 3339 port->wide_port_phymap |= (1U << phy_id); 3340 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3341 pm8001_dbg(pm8001_ha, MSG, 3342 "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n", 3343 port_id, phy_id, link_rate, portstate, deviceType); 3344 3345 switch (deviceType) { 3346 case SAS_PHY_UNUSED: 3347 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n"); 3348 break; 3349 case SAS_END_DEVICE: 3350 pm8001_dbg(pm8001_ha, MSG, "end device.\n"); 3351 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3352 PHY_NOTIFY_ENABLE_SPINUP); 3353 port->port_attached = 1; 3354 pm8001_get_lrate_mode(phy, link_rate); 3355 break; 3356 case SAS_EDGE_EXPANDER_DEVICE: 3357 pm8001_dbg(pm8001_ha, MSG, "expander device.\n"); 3358 port->port_attached = 1; 3359 pm8001_get_lrate_mode(phy, link_rate); 3360 break; 3361 case SAS_FANOUT_EXPANDER_DEVICE: 3362 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n"); 3363 port->port_attached = 1; 3364 pm8001_get_lrate_mode(phy, link_rate); 3365 break; 3366 default: 3367 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n", 3368 deviceType); 3369 break; 3370 } 3371 phy->phy_type |= PORT_TYPE_SAS; 3372 phy->identify.device_type = deviceType; 3373 phy->phy_attached = 1; 3374 if (phy->identify.device_type == SAS_END_DEVICE) 3375 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3376 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3377 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3378 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3379 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3380 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3381 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3382 sizeof(struct sas_identify_frame)-4); 3383 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3384 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3385 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3386 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3387 mdelay(200); /* delay a moment to wait for disk to spin up */ 3388 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3389 } 3390 3391 /** 3392 * hw_event_sata_phy_up - FW tells me a SATA phy up event. 3393 * @pm8001_ha: our hba card information 3394 * @piomb: IO message buffer 3395 */ 3396 static void 3397 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3398 { 3399 struct hw_event_resp *pPayload = 3400 (struct hw_event_resp *)(piomb + 4); 3401 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3402 u32 lr_status_evt_portid = 3403 le32_to_cpu(pPayload->lr_status_evt_portid); 3404 u8 link_rate = 3405 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3406 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3407 u8 phy_id = 3408 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3409 3410 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3411 3412 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3413 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3414 unsigned long flags; 3415 pm8001_dbg(pm8001_ha, DEVIO, 3416 "port id %d, phy id %d link_rate %d portstate 0x%x\n", 3417 port_id, phy_id, link_rate, portstate); 3418 3419 phy->port = port; 3420 port->port_id = port_id; 3421 port->port_state = portstate; 3422 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3423 port->port_attached = 1; 3424 pm8001_get_lrate_mode(phy, link_rate); 3425 phy->phy_type |= PORT_TYPE_SATA; 3426 phy->phy_attached = 1; 3427 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3428 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3429 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3430 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3431 sizeof(struct dev_to_host_fis)); 3432 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3433 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3434 phy->identify.device_type = SAS_SATA_DEV; 3435 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3436 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3437 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3438 } 3439 3440 /** 3441 * hw_event_phy_down - we should notify the libsas the phy is down. 3442 * @pm8001_ha: our hba card information 3443 * @piomb: IO message buffer 3444 */ 3445 static void 3446 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3447 { 3448 struct hw_event_resp *pPayload = 3449 (struct hw_event_resp *)(piomb + 4); 3450 3451 u32 lr_status_evt_portid = 3452 le32_to_cpu(pPayload->lr_status_evt_portid); 3453 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3454 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3455 u8 phy_id = 3456 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3457 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3458 3459 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3460 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3461 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA); 3462 port->port_state = portstate; 3463 phy->identify.device_type = 0; 3464 phy->phy_attached = 0; 3465 switch (portstate) { 3466 case PORT_VALID: 3467 break; 3468 case PORT_INVALID: 3469 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n", 3470 port_id); 3471 pm8001_dbg(pm8001_ha, MSG, 3472 " Last phy Down and port invalid\n"); 3473 if (port_sata) { 3474 phy->phy_type = 0; 3475 port->port_attached = 0; 3476 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3477 port_id, phy_id, 0, 0); 3478 } 3479 sas_phy_disconnected(&phy->sas_phy); 3480 break; 3481 case PORT_IN_RESET: 3482 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n", 3483 port_id); 3484 break; 3485 case PORT_NOT_ESTABLISHED: 3486 pm8001_dbg(pm8001_ha, MSG, 3487 " Phy Down and PORT_NOT_ESTABLISHED\n"); 3488 port->port_attached = 0; 3489 break; 3490 case PORT_LOSTCOMM: 3491 pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n"); 3492 pm8001_dbg(pm8001_ha, MSG, 3493 " Last phy Down and port invalid\n"); 3494 if (port_sata) { 3495 port->port_attached = 0; 3496 phy->phy_type = 0; 3497 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3498 port_id, phy_id, 0, 0); 3499 } 3500 sas_phy_disconnected(&phy->sas_phy); 3501 break; 3502 default: 3503 port->port_attached = 0; 3504 pm8001_dbg(pm8001_ha, DEVIO, 3505 " Phy Down and(default) = 0x%x\n", 3506 portstate); 3507 break; 3508 3509 } 3510 if (port_sata && (portstate != PORT_IN_RESET)) 3511 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL, 3512 GFP_ATOMIC); 3513 } 3514 3515 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3516 { 3517 struct phy_start_resp *pPayload = 3518 (struct phy_start_resp *)(piomb + 4); 3519 u32 status = 3520 le32_to_cpu(pPayload->status); 3521 u32 phy_id = 3522 le32_to_cpu(pPayload->phyid); 3523 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3524 3525 pm8001_dbg(pm8001_ha, INIT, 3526 "phy start resp status:0x%x, phyid:0x%x\n", 3527 status, phy_id); 3528 if (status == 0) 3529 phy->phy_state = PHY_LINK_DOWN; 3530 3531 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3532 phy->enable_completion != NULL) { 3533 complete(phy->enable_completion); 3534 phy->enable_completion = NULL; 3535 } 3536 return 0; 3537 3538 } 3539 3540 /** 3541 * mpi_thermal_hw_event - a thermal hw event has come. 3542 * @pm8001_ha: our hba card information 3543 * @piomb: IO message buffer 3544 */ 3545 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3546 { 3547 struct thermal_hw_event *pPayload = 3548 (struct thermal_hw_event *)(piomb + 4); 3549 3550 u32 thermal_event = le32_to_cpu(pPayload->thermal_event); 3551 u32 rht_lht = le32_to_cpu(pPayload->rht_lht); 3552 3553 if (thermal_event & 0x40) { 3554 pm8001_dbg(pm8001_ha, IO, 3555 "Thermal Event: Local high temperature violated!\n"); 3556 pm8001_dbg(pm8001_ha, IO, 3557 "Thermal Event: Measured local high temperature %d\n", 3558 ((rht_lht & 0xFF00) >> 8)); 3559 } 3560 if (thermal_event & 0x10) { 3561 pm8001_dbg(pm8001_ha, IO, 3562 "Thermal Event: Remote high temperature violated!\n"); 3563 pm8001_dbg(pm8001_ha, IO, 3564 "Thermal Event: Measured remote high temperature %d\n", 3565 ((rht_lht & 0xFF000000) >> 24)); 3566 } 3567 return 0; 3568 } 3569 3570 /** 3571 * mpi_hw_event - The hw event has come. 3572 * @pm8001_ha: our hba card information 3573 * @piomb: IO message buffer 3574 */ 3575 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3576 { 3577 unsigned long flags, i; 3578 struct hw_event_resp *pPayload = 3579 (struct hw_event_resp *)(piomb + 4); 3580 u32 lr_status_evt_portid = 3581 le32_to_cpu(pPayload->lr_status_evt_portid); 3582 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3583 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3584 u8 phy_id = 3585 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3586 u16 eventType = 3587 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); 3588 u8 status = 3589 (u8)((lr_status_evt_portid & 0x0F000000) >> 24); 3590 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3591 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3592 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3593 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3594 pm8001_dbg(pm8001_ha, DEV, 3595 "portid:%d phyid:%d event:0x%x status:0x%x\n", 3596 port_id, phy_id, eventType, status); 3597 3598 switch (eventType) { 3599 3600 case HW_EVENT_SAS_PHY_UP: 3601 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n"); 3602 hw_event_sas_phy_up(pm8001_ha, piomb); 3603 break; 3604 case HW_EVENT_SATA_PHY_UP: 3605 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n"); 3606 hw_event_sata_phy_up(pm8001_ha, piomb); 3607 break; 3608 case HW_EVENT_SATA_SPINUP_HOLD: 3609 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n"); 3610 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD, 3611 GFP_ATOMIC); 3612 break; 3613 case HW_EVENT_PHY_DOWN: 3614 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n"); 3615 hw_event_phy_down(pm8001_ha, piomb); 3616 if (pm8001_ha->reset_in_progress) { 3617 pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n"); 3618 return 0; 3619 } 3620 phy->phy_attached = 0; 3621 phy->phy_state = PHY_LINK_DISABLE; 3622 break; 3623 case HW_EVENT_PORT_INVALID: 3624 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n"); 3625 sas_phy_disconnected(sas_phy); 3626 phy->phy_attached = 0; 3627 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3628 GFP_ATOMIC); 3629 break; 3630 /* the broadcast change primitive received, tell the LIBSAS this event 3631 to revalidate the sas domain*/ 3632 case HW_EVENT_BROADCAST_CHANGE: 3633 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n"); 3634 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3635 port_id, phy_id, 1, 0); 3636 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3637 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3638 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3639 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3640 GFP_ATOMIC); 3641 break; 3642 case HW_EVENT_PHY_ERROR: 3643 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n"); 3644 sas_phy_disconnected(&phy->sas_phy); 3645 phy->phy_attached = 0; 3646 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC); 3647 break; 3648 case HW_EVENT_BROADCAST_EXP: 3649 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n"); 3650 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3651 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3652 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3653 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3654 GFP_ATOMIC); 3655 break; 3656 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3657 pm8001_dbg(pm8001_ha, MSG, 3658 "HW_EVENT_LINK_ERR_INVALID_DWORD\n"); 3659 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3660 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3661 break; 3662 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3663 pm8001_dbg(pm8001_ha, MSG, 3664 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"); 3665 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3666 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3667 port_id, phy_id, 0, 0); 3668 break; 3669 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3670 pm8001_dbg(pm8001_ha, MSG, 3671 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n"); 3672 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3673 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3674 port_id, phy_id, 0, 0); 3675 break; 3676 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3677 pm8001_dbg(pm8001_ha, MSG, 3678 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"); 3679 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3680 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3681 port_id, phy_id, 0, 0); 3682 break; 3683 case HW_EVENT_MALFUNCTION: 3684 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n"); 3685 break; 3686 case HW_EVENT_BROADCAST_SES: 3687 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n"); 3688 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3689 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3690 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3691 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3692 GFP_ATOMIC); 3693 break; 3694 case HW_EVENT_INBOUND_CRC_ERROR: 3695 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n"); 3696 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3697 HW_EVENT_INBOUND_CRC_ERROR, 3698 port_id, phy_id, 0, 0); 3699 break; 3700 case HW_EVENT_HARD_RESET_RECEIVED: 3701 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n"); 3702 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC); 3703 break; 3704 case HW_EVENT_ID_FRAME_TIMEOUT: 3705 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n"); 3706 sas_phy_disconnected(sas_phy); 3707 phy->phy_attached = 0; 3708 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3709 GFP_ATOMIC); 3710 break; 3711 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3712 pm8001_dbg(pm8001_ha, MSG, 3713 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"); 3714 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3715 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3716 port_id, phy_id, 0, 0); 3717 sas_phy_disconnected(sas_phy); 3718 phy->phy_attached = 0; 3719 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3720 GFP_ATOMIC); 3721 break; 3722 case HW_EVENT_PORT_RESET_TIMER_TMO: 3723 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n"); 3724 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3725 port_id, phy_id, 0, 0); 3726 sas_phy_disconnected(sas_phy); 3727 phy->phy_attached = 0; 3728 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3729 GFP_ATOMIC); 3730 if (pm8001_ha->phy[phy_id].reset_completion) { 3731 pm8001_ha->phy[phy_id].port_reset_status = 3732 PORT_RESET_TMO; 3733 complete(pm8001_ha->phy[phy_id].reset_completion); 3734 pm8001_ha->phy[phy_id].reset_completion = NULL; 3735 } 3736 break; 3737 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3738 pm8001_dbg(pm8001_ha, MSG, 3739 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"); 3740 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3741 HW_EVENT_PORT_RECOVERY_TIMER_TMO, 3742 port_id, phy_id, 0, 0); 3743 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 3744 if (port->wide_port_phymap & (1 << i)) { 3745 phy = &pm8001_ha->phy[i]; 3746 sas_notify_phy_event(&phy->sas_phy, 3747 PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC); 3748 port->wide_port_phymap &= ~(1 << i); 3749 } 3750 } 3751 break; 3752 case HW_EVENT_PORT_RECOVER: 3753 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n"); 3754 hw_event_port_recover(pm8001_ha, piomb); 3755 break; 3756 case HW_EVENT_PORT_RESET_COMPLETE: 3757 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n"); 3758 if (pm8001_ha->phy[phy_id].reset_completion) { 3759 pm8001_ha->phy[phy_id].port_reset_status = 3760 PORT_RESET_SUCCESS; 3761 complete(pm8001_ha->phy[phy_id].reset_completion); 3762 pm8001_ha->phy[phy_id].reset_completion = NULL; 3763 } 3764 break; 3765 case EVENT_BROADCAST_ASYNCH_EVENT: 3766 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n"); 3767 break; 3768 default: 3769 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n", 3770 eventType); 3771 break; 3772 } 3773 return 0; 3774 } 3775 3776 /** 3777 * mpi_phy_stop_resp - SPCv specific 3778 * @pm8001_ha: our hba card information 3779 * @piomb: IO message buffer 3780 */ 3781 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3782 { 3783 struct phy_stop_resp *pPayload = 3784 (struct phy_stop_resp *)(piomb + 4); 3785 u32 status = 3786 le32_to_cpu(pPayload->status); 3787 u32 phyid = 3788 le32_to_cpu(pPayload->phyid) & 0xFF; 3789 struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; 3790 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n", 3791 phyid, status); 3792 if (status == PHY_STOP_SUCCESS || 3793 status == PHY_STOP_ERR_DEVICE_ATTACHED) 3794 phy->phy_state = PHY_LINK_DISABLE; 3795 return 0; 3796 } 3797 3798 /** 3799 * mpi_set_controller_config_resp - SPCv specific 3800 * @pm8001_ha: our hba card information 3801 * @piomb: IO message buffer 3802 */ 3803 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3804 void *piomb) 3805 { 3806 struct set_ctrl_cfg_resp *pPayload = 3807 (struct set_ctrl_cfg_resp *)(piomb + 4); 3808 u32 status = le32_to_cpu(pPayload->status); 3809 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); 3810 3811 pm8001_dbg(pm8001_ha, MSG, 3812 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", 3813 status, err_qlfr_pgcd); 3814 3815 return 0; 3816 } 3817 3818 /** 3819 * mpi_get_controller_config_resp - SPCv specific 3820 * @pm8001_ha: our hba card information 3821 * @piomb: IO message buffer 3822 */ 3823 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3824 void *piomb) 3825 { 3826 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3827 3828 return 0; 3829 } 3830 3831 /** 3832 * mpi_get_phy_profile_resp - SPCv specific 3833 * @pm8001_ha: our hba card information 3834 * @piomb: IO message buffer 3835 */ 3836 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3837 void *piomb) 3838 { 3839 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3840 3841 return 0; 3842 } 3843 3844 /** 3845 * mpi_flash_op_ext_resp - SPCv specific 3846 * @pm8001_ha: our hba card information 3847 * @piomb: IO message buffer 3848 */ 3849 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3850 { 3851 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3852 3853 return 0; 3854 } 3855 3856 /** 3857 * mpi_set_phy_profile_resp - SPCv specific 3858 * @pm8001_ha: our hba card information 3859 * @piomb: IO message buffer 3860 */ 3861 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3862 void *piomb) 3863 { 3864 u32 tag; 3865 u8 page_code; 3866 int rc = 0; 3867 struct set_phy_profile_resp *pPayload = 3868 (struct set_phy_profile_resp *)(piomb + 4); 3869 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); 3870 u32 status = le32_to_cpu(pPayload->status); 3871 3872 tag = le32_to_cpu(pPayload->tag); 3873 page_code = (u8)((ppc_phyid & 0xFF00) >> 8); 3874 if (status) { 3875 /* status is FAILED */ 3876 pm8001_dbg(pm8001_ha, FAIL, 3877 "PhyProfile command failed with status 0x%08X\n", 3878 status); 3879 rc = -1; 3880 } else { 3881 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) { 3882 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n", 3883 page_code); 3884 rc = -1; 3885 } 3886 } 3887 pm8001_tag_free(pm8001_ha, tag); 3888 return rc; 3889 } 3890 3891 /** 3892 * mpi_kek_management_resp - SPCv specific 3893 * @pm8001_ha: our hba card information 3894 * @piomb: IO message buffer 3895 */ 3896 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, 3897 void *piomb) 3898 { 3899 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); 3900 3901 u32 status = le32_to_cpu(pPayload->status); 3902 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); 3903 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); 3904 3905 pm8001_dbg(pm8001_ha, MSG, 3906 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", 3907 status, kidx_new_curr_ksop, err_qlfr); 3908 3909 return 0; 3910 } 3911 3912 /** 3913 * mpi_dek_management_resp - SPCv specific 3914 * @pm8001_ha: our hba card information 3915 * @piomb: IO message buffer 3916 */ 3917 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, 3918 void *piomb) 3919 { 3920 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3921 3922 return 0; 3923 } 3924 3925 /** 3926 * ssp_coalesced_comp_resp - SPCv specific 3927 * @pm8001_ha: our hba card information 3928 * @piomb: IO message buffer 3929 */ 3930 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, 3931 void *piomb) 3932 { 3933 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3934 3935 return 0; 3936 } 3937 3938 /** 3939 * process_one_iomb - process one outbound Queue memory block 3940 * @pm8001_ha: our hba card information 3941 * @piomb: IO message buffer 3942 */ 3943 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, 3944 struct outbound_queue_table *circularQ, void *piomb) 3945 { 3946 __le32 pHeader = *(__le32 *)piomb; 3947 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); 3948 3949 switch (opc) { 3950 case OPC_OUB_ECHO: 3951 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n"); 3952 break; 3953 case OPC_OUB_HW_EVENT: 3954 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n"); 3955 mpi_hw_event(pm8001_ha, piomb); 3956 break; 3957 case OPC_OUB_THERM_HW_EVENT: 3958 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n"); 3959 mpi_thermal_hw_event(pm8001_ha, piomb); 3960 break; 3961 case OPC_OUB_SSP_COMP: 3962 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n"); 3963 mpi_ssp_completion(pm8001_ha, piomb); 3964 break; 3965 case OPC_OUB_SMP_COMP: 3966 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n"); 3967 mpi_smp_completion(pm8001_ha, piomb); 3968 break; 3969 case OPC_OUB_LOCAL_PHY_CNTRL: 3970 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n"); 3971 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3972 break; 3973 case OPC_OUB_DEV_REGIST: 3974 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n"); 3975 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3976 break; 3977 case OPC_OUB_DEREG_DEV: 3978 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n"); 3979 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3980 break; 3981 case OPC_OUB_GET_DEV_HANDLE: 3982 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n"); 3983 break; 3984 case OPC_OUB_SATA_COMP: 3985 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n"); 3986 mpi_sata_completion(pm8001_ha, circularQ, piomb); 3987 break; 3988 case OPC_OUB_SATA_EVENT: 3989 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n"); 3990 mpi_sata_event(pm8001_ha, circularQ, piomb); 3991 break; 3992 case OPC_OUB_SSP_EVENT: 3993 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n"); 3994 mpi_ssp_event(pm8001_ha, piomb); 3995 break; 3996 case OPC_OUB_DEV_HANDLE_ARRIV: 3997 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n"); 3998 /*This is for target*/ 3999 break; 4000 case OPC_OUB_SSP_RECV_EVENT: 4001 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n"); 4002 /*This is for target*/ 4003 break; 4004 case OPC_OUB_FW_FLASH_UPDATE: 4005 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n"); 4006 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 4007 break; 4008 case OPC_OUB_GPIO_RESPONSE: 4009 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n"); 4010 break; 4011 case OPC_OUB_GPIO_EVENT: 4012 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n"); 4013 break; 4014 case OPC_OUB_GENERAL_EVENT: 4015 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n"); 4016 pm8001_mpi_general_event(pm8001_ha, piomb); 4017 break; 4018 case OPC_OUB_SSP_ABORT_RSP: 4019 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n"); 4020 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4021 break; 4022 case OPC_OUB_SATA_ABORT_RSP: 4023 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n"); 4024 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4025 break; 4026 case OPC_OUB_SAS_DIAG_MODE_START_END: 4027 pm8001_dbg(pm8001_ha, MSG, 4028 "OPC_OUB_SAS_DIAG_MODE_START_END\n"); 4029 break; 4030 case OPC_OUB_SAS_DIAG_EXECUTE: 4031 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n"); 4032 break; 4033 case OPC_OUB_GET_TIME_STAMP: 4034 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n"); 4035 break; 4036 case OPC_OUB_SAS_HW_EVENT_ACK: 4037 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n"); 4038 break; 4039 case OPC_OUB_PORT_CONTROL: 4040 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n"); 4041 break; 4042 case OPC_OUB_SMP_ABORT_RSP: 4043 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n"); 4044 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4045 break; 4046 case OPC_OUB_GET_NVMD_DATA: 4047 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n"); 4048 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 4049 break; 4050 case OPC_OUB_SET_NVMD_DATA: 4051 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n"); 4052 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 4053 break; 4054 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 4055 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n"); 4056 break; 4057 case OPC_OUB_SET_DEVICE_STATE: 4058 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n"); 4059 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 4060 break; 4061 case OPC_OUB_GET_DEVICE_STATE: 4062 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n"); 4063 break; 4064 case OPC_OUB_SET_DEV_INFO: 4065 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n"); 4066 break; 4067 /* spcv specific commands */ 4068 case OPC_OUB_PHY_START_RESP: 4069 pm8001_dbg(pm8001_ha, MSG, 4070 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc); 4071 mpi_phy_start_resp(pm8001_ha, piomb); 4072 break; 4073 case OPC_OUB_PHY_STOP_RESP: 4074 pm8001_dbg(pm8001_ha, MSG, 4075 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc); 4076 mpi_phy_stop_resp(pm8001_ha, piomb); 4077 break; 4078 case OPC_OUB_SET_CONTROLLER_CONFIG: 4079 pm8001_dbg(pm8001_ha, MSG, 4080 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc); 4081 mpi_set_controller_config_resp(pm8001_ha, piomb); 4082 break; 4083 case OPC_OUB_GET_CONTROLLER_CONFIG: 4084 pm8001_dbg(pm8001_ha, MSG, 4085 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc); 4086 mpi_get_controller_config_resp(pm8001_ha, piomb); 4087 break; 4088 case OPC_OUB_GET_PHY_PROFILE: 4089 pm8001_dbg(pm8001_ha, MSG, 4090 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc); 4091 mpi_get_phy_profile_resp(pm8001_ha, piomb); 4092 break; 4093 case OPC_OUB_FLASH_OP_EXT: 4094 pm8001_dbg(pm8001_ha, MSG, 4095 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc); 4096 mpi_flash_op_ext_resp(pm8001_ha, piomb); 4097 break; 4098 case OPC_OUB_SET_PHY_PROFILE: 4099 pm8001_dbg(pm8001_ha, MSG, 4100 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc); 4101 mpi_set_phy_profile_resp(pm8001_ha, piomb); 4102 break; 4103 case OPC_OUB_KEK_MANAGEMENT_RESP: 4104 pm8001_dbg(pm8001_ha, MSG, 4105 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc); 4106 mpi_kek_management_resp(pm8001_ha, piomb); 4107 break; 4108 case OPC_OUB_DEK_MANAGEMENT_RESP: 4109 pm8001_dbg(pm8001_ha, MSG, 4110 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc); 4111 mpi_dek_management_resp(pm8001_ha, piomb); 4112 break; 4113 case OPC_OUB_SSP_COALESCED_COMP_RESP: 4114 pm8001_dbg(pm8001_ha, MSG, 4115 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc); 4116 ssp_coalesced_comp_resp(pm8001_ha, piomb); 4117 break; 4118 default: 4119 pm8001_dbg(pm8001_ha, DEVIO, 4120 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc); 4121 break; 4122 } 4123 } 4124 4125 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha) 4126 { 4127 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n", 4128 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); 4129 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n", 4130 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)); 4131 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n", 4132 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)); 4133 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n", 4134 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); 4135 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n", 4136 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)); 4137 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n", 4138 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)); 4139 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n", 4140 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)); 4141 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n", 4142 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)); 4143 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n", 4144 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)); 4145 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n", 4146 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)); 4147 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n", 4148 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)); 4149 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n", 4150 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)); 4151 } 4152 4153 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4154 { 4155 struct outbound_queue_table *circularQ; 4156 void *pMsg1 = NULL; 4157 u8 bc; 4158 u32 ret = MPI_IO_STATUS_FAIL; 4159 u32 regval; 4160 4161 if (vec == (pm8001_ha->max_q_num - 1)) { 4162 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 4163 if ((regval & SCRATCH_PAD_MIPSALL_READY) != 4164 SCRATCH_PAD_MIPSALL_READY) { 4165 pm8001_ha->controller_fatal_error = true; 4166 pm8001_dbg(pm8001_ha, FAIL, 4167 "Firmware Fatal error! Regval:0x%x\n", 4168 regval); 4169 pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR); 4170 print_scratchpad_registers(pm8001_ha); 4171 return ret; 4172 } 4173 } 4174 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4175 spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags); 4176 do { 4177 /* spurious interrupt during setup if kexec-ing and 4178 * driver doing a doorbell access w/ the pre-kexec oq 4179 * interrupt setup. 4180 */ 4181 if (!circularQ->pi_virt) 4182 break; 4183 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4184 if (MPI_IO_STATUS_SUCCESS == ret) { 4185 /* process the outbound message */ 4186 process_one_iomb(pm8001_ha, circularQ, 4187 (void *)(pMsg1 - 4)); 4188 /* free the message from the outbound circular buffer */ 4189 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4190 circularQ, bc); 4191 } 4192 if (MPI_IO_STATUS_BUSY == ret) { 4193 /* Update the producer index from SPC */ 4194 circularQ->producer_index = 4195 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4196 if (le32_to_cpu(circularQ->producer_index) == 4197 circularQ->consumer_idx) 4198 /* OQ is empty */ 4199 break; 4200 } 4201 } while (1); 4202 spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags); 4203 return ret; 4204 } 4205 4206 /* DMA_... to our direction translation. */ 4207 static const u8 data_dir_flags[] = { 4208 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4209 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4210 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4211 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4212 }; 4213 4214 static void build_smp_cmd(u32 deviceID, __le32 hTag, 4215 struct smp_req *psmp_cmd, int mode, int length) 4216 { 4217 psmp_cmd->tag = hTag; 4218 psmp_cmd->device_id = cpu_to_le32(deviceID); 4219 if (mode == SMP_DIRECT) { 4220 length = length - 4; /* subtract crc */ 4221 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); 4222 } else { 4223 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4224 } 4225 } 4226 4227 /** 4228 * pm80xx_chip_smp_req - send an SMP task to FW 4229 * @pm8001_ha: our hba card information. 4230 * @ccb: the ccb information this request used. 4231 */ 4232 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4233 struct pm8001_ccb_info *ccb) 4234 { 4235 int elem, rc; 4236 struct sas_task *task = ccb->task; 4237 struct domain_device *dev = task->dev; 4238 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4239 struct scatterlist *sg_req, *sg_resp; 4240 u32 req_len, resp_len; 4241 struct smp_req smp_cmd; 4242 u32 opc; 4243 struct inbound_queue_table *circularQ; 4244 char *preq_dma_addr = NULL; 4245 __le64 tmp_addr; 4246 u32 i, length; 4247 4248 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4249 /* 4250 * DMA-map SMP request, response buffers 4251 */ 4252 sg_req = &task->smp_task.smp_req; 4253 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4254 if (!elem) 4255 return -ENOMEM; 4256 req_len = sg_dma_len(sg_req); 4257 4258 sg_resp = &task->smp_task.smp_resp; 4259 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4260 if (!elem) { 4261 rc = -ENOMEM; 4262 goto err_out; 4263 } 4264 resp_len = sg_dma_len(sg_resp); 4265 /* must be in dwords */ 4266 if ((req_len & 0x3) || (resp_len & 0x3)) { 4267 rc = -EINVAL; 4268 goto err_out_2; 4269 } 4270 4271 opc = OPC_INB_SMP_REQUEST; 4272 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4273 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4274 4275 length = sg_req->length; 4276 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length); 4277 if (!(length - 8)) 4278 pm8001_ha->smp_exp_mode = SMP_DIRECT; 4279 else 4280 pm8001_ha->smp_exp_mode = SMP_INDIRECT; 4281 4282 4283 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 4284 preq_dma_addr = (char *)phys_to_virt(tmp_addr); 4285 4286 /* INDIRECT MODE command settings. Use DMA */ 4287 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { 4288 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n"); 4289 /* for SPCv indirect mode. Place the top 4 bytes of 4290 * SMP Request header here. */ 4291 for (i = 0; i < 4; i++) 4292 smp_cmd.smp_req16[i] = *(preq_dma_addr + i); 4293 /* exclude top 4 bytes for SMP req header */ 4294 smp_cmd.long_smp_req.long_req_addr = 4295 cpu_to_le64((u64)sg_dma_address 4296 (&task->smp_task.smp_req) + 4); 4297 /* exclude 4 bytes for SMP req header and CRC */ 4298 smp_cmd.long_smp_req.long_req_size = 4299 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); 4300 smp_cmd.long_smp_req.long_resp_addr = 4301 cpu_to_le64((u64)sg_dma_address 4302 (&task->smp_task.smp_resp)); 4303 smp_cmd.long_smp_req.long_resp_size = 4304 cpu_to_le32((u32)sg_dma_len 4305 (&task->smp_task.smp_resp)-4); 4306 } else { /* DIRECT MODE */ 4307 smp_cmd.long_smp_req.long_req_addr = 4308 cpu_to_le64((u64)sg_dma_address 4309 (&task->smp_task.smp_req)); 4310 smp_cmd.long_smp_req.long_req_size = 4311 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4312 smp_cmd.long_smp_req.long_resp_addr = 4313 cpu_to_le64((u64)sg_dma_address 4314 (&task->smp_task.smp_resp)); 4315 smp_cmd.long_smp_req.long_resp_size = 4316 cpu_to_le32 4317 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4318 } 4319 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 4320 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n"); 4321 for (i = 0; i < length; i++) 4322 if (i < 16) { 4323 smp_cmd.smp_req16[i] = *(preq_dma_addr+i); 4324 pm8001_dbg(pm8001_ha, IO, 4325 "Byte[%d]:%x (DMA data:%x)\n", 4326 i, smp_cmd.smp_req16[i], 4327 *(preq_dma_addr)); 4328 } else { 4329 smp_cmd.smp_req[i] = *(preq_dma_addr+i); 4330 pm8001_dbg(pm8001_ha, IO, 4331 "Byte[%d]:%x (DMA data:%x)\n", 4332 i, smp_cmd.smp_req[i], 4333 *(preq_dma_addr)); 4334 } 4335 } 4336 4337 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, 4338 &smp_cmd, pm8001_ha->smp_exp_mode, length); 4339 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd, 4340 sizeof(smp_cmd), 0); 4341 if (rc) 4342 goto err_out_2; 4343 return 0; 4344 4345 err_out_2: 4346 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4347 DMA_FROM_DEVICE); 4348 err_out: 4349 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4350 DMA_TO_DEVICE); 4351 return rc; 4352 } 4353 4354 static int check_enc_sas_cmd(struct sas_task *task) 4355 { 4356 u8 cmd = task->ssp_task.cmd->cmnd[0]; 4357 4358 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) 4359 return 1; 4360 else 4361 return 0; 4362 } 4363 4364 static int check_enc_sat_cmd(struct sas_task *task) 4365 { 4366 int ret = 0; 4367 switch (task->ata_task.fis.command) { 4368 case ATA_CMD_FPDMA_READ: 4369 case ATA_CMD_READ_EXT: 4370 case ATA_CMD_READ: 4371 case ATA_CMD_FPDMA_WRITE: 4372 case ATA_CMD_WRITE_EXT: 4373 case ATA_CMD_WRITE: 4374 case ATA_CMD_PIO_READ: 4375 case ATA_CMD_PIO_READ_EXT: 4376 case ATA_CMD_PIO_WRITE: 4377 case ATA_CMD_PIO_WRITE_EXT: 4378 ret = 1; 4379 break; 4380 default: 4381 ret = 0; 4382 break; 4383 } 4384 return ret; 4385 } 4386 4387 /** 4388 * pm80xx_chip_ssp_io_req - send an SSP task to FW 4389 * @pm8001_ha: our hba card information. 4390 * @ccb: the ccb information this request used. 4391 */ 4392 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4393 struct pm8001_ccb_info *ccb) 4394 { 4395 struct sas_task *task = ccb->task; 4396 struct domain_device *dev = task->dev; 4397 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4398 struct ssp_ini_io_start_req ssp_cmd; 4399 u32 tag = ccb->ccb_tag; 4400 int ret; 4401 u64 phys_addr, start_addr, end_addr; 4402 u32 end_addr_high, end_addr_low; 4403 struct inbound_queue_table *circularQ; 4404 u32 q_index, cpu_id; 4405 u32 opc = OPC_INB_SSPINIIOSTART; 4406 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4407 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4408 /* data address domain added for spcv; set to 0 by host, 4409 * used internally by controller 4410 * 0 for SAS 1.1 and SAS 2.0 compatible TLR 4411 */ 4412 ssp_cmd.dad_dir_m_tlr = 4413 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); 4414 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4415 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4416 ssp_cmd.tag = cpu_to_le32(tag); 4417 if (task->ssp_task.enable_first_burst) 4418 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4419 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4420 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4421 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4422 task->ssp_task.cmd->cmd_len); 4423 cpu_id = smp_processor_id(); 4424 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num); 4425 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4426 4427 /* Check if encryption is set */ 4428 if (pm8001_ha->chip->encrypt && 4429 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { 4430 pm8001_dbg(pm8001_ha, IO, 4431 "Encryption enabled.Sending Encrypt SAS command 0x%x\n", 4432 task->ssp_task.cmd->cmnd[0]); 4433 opc = OPC_INB_SSP_INI_DIF_ENC_IO; 4434 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ 4435 ssp_cmd.dad_dir_m_tlr = cpu_to_le32 4436 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); 4437 4438 /* fill in PRD (scatter/gather) table, if any */ 4439 if (task->num_scatter > 1) { 4440 pm8001_chip_make_sg(task->scatter, 4441 ccb->n_elem, ccb->buf_prd); 4442 phys_addr = ccb->ccb_dma_handle; 4443 ssp_cmd.enc_addr_low = 4444 cpu_to_le32(lower_32_bits(phys_addr)); 4445 ssp_cmd.enc_addr_high = 4446 cpu_to_le32(upper_32_bits(phys_addr)); 4447 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4448 } else if (task->num_scatter == 1) { 4449 u64 dma_addr = sg_dma_address(task->scatter); 4450 ssp_cmd.enc_addr_low = 4451 cpu_to_le32(lower_32_bits(dma_addr)); 4452 ssp_cmd.enc_addr_high = 4453 cpu_to_le32(upper_32_bits(dma_addr)); 4454 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4455 ssp_cmd.enc_esgl = 0; 4456 /* Check 4G Boundary */ 4457 start_addr = cpu_to_le64(dma_addr); 4458 end_addr = (start_addr + ssp_cmd.enc_len) - 1; 4459 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4460 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4461 if (end_addr_high != ssp_cmd.enc_addr_high) { 4462 pm8001_dbg(pm8001_ha, FAIL, 4463 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4464 start_addr, ssp_cmd.enc_len, 4465 end_addr_high, end_addr_low); 4466 pm8001_chip_make_sg(task->scatter, 1, 4467 ccb->buf_prd); 4468 phys_addr = ccb->ccb_dma_handle; 4469 ssp_cmd.enc_addr_low = 4470 cpu_to_le32(lower_32_bits(phys_addr)); 4471 ssp_cmd.enc_addr_high = 4472 cpu_to_le32(upper_32_bits(phys_addr)); 4473 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4474 } 4475 } else if (task->num_scatter == 0) { 4476 ssp_cmd.enc_addr_low = 0; 4477 ssp_cmd.enc_addr_high = 0; 4478 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4479 ssp_cmd.enc_esgl = 0; 4480 } 4481 /* XTS mode. All other fields are 0 */ 4482 ssp_cmd.key_cmode = 0x6 << 4; 4483 /* set tweak values. Should be the start lba */ 4484 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | 4485 (task->ssp_task.cmd->cmnd[3] << 16) | 4486 (task->ssp_task.cmd->cmnd[4] << 8) | 4487 (task->ssp_task.cmd->cmnd[5])); 4488 } else { 4489 pm8001_dbg(pm8001_ha, IO, 4490 "Sending Normal SAS command 0x%x inb q %x\n", 4491 task->ssp_task.cmd->cmnd[0], q_index); 4492 /* fill in PRD (scatter/gather) table, if any */ 4493 if (task->num_scatter > 1) { 4494 pm8001_chip_make_sg(task->scatter, ccb->n_elem, 4495 ccb->buf_prd); 4496 phys_addr = ccb->ccb_dma_handle; 4497 ssp_cmd.addr_low = 4498 cpu_to_le32(lower_32_bits(phys_addr)); 4499 ssp_cmd.addr_high = 4500 cpu_to_le32(upper_32_bits(phys_addr)); 4501 ssp_cmd.esgl = cpu_to_le32(1<<31); 4502 } else if (task->num_scatter == 1) { 4503 u64 dma_addr = sg_dma_address(task->scatter); 4504 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4505 ssp_cmd.addr_high = 4506 cpu_to_le32(upper_32_bits(dma_addr)); 4507 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4508 ssp_cmd.esgl = 0; 4509 /* Check 4G Boundary */ 4510 start_addr = cpu_to_le64(dma_addr); 4511 end_addr = (start_addr + ssp_cmd.len) - 1; 4512 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4513 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4514 if (end_addr_high != ssp_cmd.addr_high) { 4515 pm8001_dbg(pm8001_ha, FAIL, 4516 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4517 start_addr, ssp_cmd.len, 4518 end_addr_high, end_addr_low); 4519 pm8001_chip_make_sg(task->scatter, 1, 4520 ccb->buf_prd); 4521 phys_addr = ccb->ccb_dma_handle; 4522 ssp_cmd.addr_low = 4523 cpu_to_le32(lower_32_bits(phys_addr)); 4524 ssp_cmd.addr_high = 4525 cpu_to_le32(upper_32_bits(phys_addr)); 4526 ssp_cmd.esgl = cpu_to_le32(1<<31); 4527 } 4528 } else if (task->num_scatter == 0) { 4529 ssp_cmd.addr_low = 0; 4530 ssp_cmd.addr_high = 0; 4531 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4532 ssp_cmd.esgl = 0; 4533 } 4534 } 4535 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4536 &ssp_cmd, sizeof(ssp_cmd), q_index); 4537 return ret; 4538 } 4539 4540 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4541 struct pm8001_ccb_info *ccb) 4542 { 4543 struct sas_task *task = ccb->task; 4544 struct domain_device *dev = task->dev; 4545 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4546 u32 tag = ccb->ccb_tag; 4547 int ret; 4548 u32 q_index, cpu_id; 4549 struct sata_start_req sata_cmd; 4550 u32 hdr_tag, ncg_tag = 0; 4551 u64 phys_addr, start_addr, end_addr; 4552 u32 end_addr_high, end_addr_low; 4553 u32 ATAP = 0x0; 4554 u32 dir; 4555 struct inbound_queue_table *circularQ; 4556 unsigned long flags; 4557 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4558 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4559 cpu_id = smp_processor_id(); 4560 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num); 4561 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4562 4563 if (task->data_dir == DMA_NONE) { 4564 ATAP = 0x04; /* no data*/ 4565 pm8001_dbg(pm8001_ha, IO, "no data\n"); 4566 } else if (likely(!task->ata_task.device_control_reg_update)) { 4567 if (task->ata_task.dma_xfer) { 4568 ATAP = 0x06; /* DMA */ 4569 pm8001_dbg(pm8001_ha, IO, "DMA\n"); 4570 } else { 4571 ATAP = 0x05; /* PIO*/ 4572 pm8001_dbg(pm8001_ha, IO, "PIO\n"); 4573 } 4574 if (task->ata_task.use_ncq && 4575 dev->sata_dev.class != ATA_DEV_ATAPI) { 4576 ATAP = 0x07; /* FPDMA */ 4577 pm8001_dbg(pm8001_ha, IO, "FPDMA\n"); 4578 } 4579 } 4580 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4581 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4582 ncg_tag = hdr_tag; 4583 } 4584 dir = data_dir_flags[task->data_dir] << 8; 4585 sata_cmd.tag = cpu_to_le32(tag); 4586 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4587 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4588 4589 sata_cmd.sata_fis = task->ata_task.fis; 4590 if (likely(!task->ata_task.device_control_reg_update)) 4591 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4592 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4593 4594 /* Check if encryption is set */ 4595 if (pm8001_ha->chip->encrypt && 4596 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { 4597 pm8001_dbg(pm8001_ha, IO, 4598 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", 4599 sata_cmd.sata_fis.command); 4600 opc = OPC_INB_SATA_DIF_ENC_IO; 4601 4602 /* set encryption bit */ 4603 sata_cmd.ncqtag_atap_dir_m_dad = 4604 cpu_to_le32(((ncg_tag & 0xff)<<16)| 4605 ((ATAP & 0x3f) << 10) | 0x20 | dir); 4606 /* dad (bit 0-1) is 0 */ 4607 /* fill in PRD (scatter/gather) table, if any */ 4608 if (task->num_scatter > 1) { 4609 pm8001_chip_make_sg(task->scatter, 4610 ccb->n_elem, ccb->buf_prd); 4611 phys_addr = ccb->ccb_dma_handle; 4612 sata_cmd.enc_addr_low = lower_32_bits(phys_addr); 4613 sata_cmd.enc_addr_high = upper_32_bits(phys_addr); 4614 sata_cmd.enc_esgl = cpu_to_le32(1 << 31); 4615 } else if (task->num_scatter == 1) { 4616 u64 dma_addr = sg_dma_address(task->scatter); 4617 sata_cmd.enc_addr_low = lower_32_bits(dma_addr); 4618 sata_cmd.enc_addr_high = upper_32_bits(dma_addr); 4619 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4620 sata_cmd.enc_esgl = 0; 4621 /* Check 4G Boundary */ 4622 start_addr = cpu_to_le64(dma_addr); 4623 end_addr = (start_addr + sata_cmd.enc_len) - 1; 4624 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4625 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4626 if (end_addr_high != sata_cmd.enc_addr_high) { 4627 pm8001_dbg(pm8001_ha, FAIL, 4628 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4629 start_addr, sata_cmd.enc_len, 4630 end_addr_high, end_addr_low); 4631 pm8001_chip_make_sg(task->scatter, 1, 4632 ccb->buf_prd); 4633 phys_addr = ccb->ccb_dma_handle; 4634 sata_cmd.enc_addr_low = 4635 lower_32_bits(phys_addr); 4636 sata_cmd.enc_addr_high = 4637 upper_32_bits(phys_addr); 4638 sata_cmd.enc_esgl = 4639 cpu_to_le32(1 << 31); 4640 } 4641 } else if (task->num_scatter == 0) { 4642 sata_cmd.enc_addr_low = 0; 4643 sata_cmd.enc_addr_high = 0; 4644 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4645 sata_cmd.enc_esgl = 0; 4646 } 4647 /* XTS mode. All other fields are 0 */ 4648 sata_cmd.key_index_mode = 0x6 << 4; 4649 /* set tweak values. Should be the start lba */ 4650 sata_cmd.twk_val0 = 4651 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | 4652 (sata_cmd.sata_fis.lbah << 16) | 4653 (sata_cmd.sata_fis.lbam << 8) | 4654 (sata_cmd.sata_fis.lbal)); 4655 sata_cmd.twk_val1 = 4656 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | 4657 (sata_cmd.sata_fis.lbam_exp)); 4658 } else { 4659 pm8001_dbg(pm8001_ha, IO, 4660 "Sending Normal SATA command 0x%x inb %x\n", 4661 sata_cmd.sata_fis.command, q_index); 4662 /* dad (bit 0-1) is 0 */ 4663 sata_cmd.ncqtag_atap_dir_m_dad = 4664 cpu_to_le32(((ncg_tag & 0xff)<<16) | 4665 ((ATAP & 0x3f) << 10) | dir); 4666 4667 /* fill in PRD (scatter/gather) table, if any */ 4668 if (task->num_scatter > 1) { 4669 pm8001_chip_make_sg(task->scatter, 4670 ccb->n_elem, ccb->buf_prd); 4671 phys_addr = ccb->ccb_dma_handle; 4672 sata_cmd.addr_low = lower_32_bits(phys_addr); 4673 sata_cmd.addr_high = upper_32_bits(phys_addr); 4674 sata_cmd.esgl = cpu_to_le32(1 << 31); 4675 } else if (task->num_scatter == 1) { 4676 u64 dma_addr = sg_dma_address(task->scatter); 4677 sata_cmd.addr_low = lower_32_bits(dma_addr); 4678 sata_cmd.addr_high = upper_32_bits(dma_addr); 4679 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4680 sata_cmd.esgl = 0; 4681 /* Check 4G Boundary */ 4682 start_addr = cpu_to_le64(dma_addr); 4683 end_addr = (start_addr + sata_cmd.len) - 1; 4684 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4685 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4686 if (end_addr_high != sata_cmd.addr_high) { 4687 pm8001_dbg(pm8001_ha, FAIL, 4688 "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4689 start_addr, sata_cmd.len, 4690 end_addr_high, end_addr_low); 4691 pm8001_chip_make_sg(task->scatter, 1, 4692 ccb->buf_prd); 4693 phys_addr = ccb->ccb_dma_handle; 4694 sata_cmd.addr_low = 4695 lower_32_bits(phys_addr); 4696 sata_cmd.addr_high = 4697 upper_32_bits(phys_addr); 4698 sata_cmd.esgl = cpu_to_le32(1 << 31); 4699 } 4700 } else if (task->num_scatter == 0) { 4701 sata_cmd.addr_low = 0; 4702 sata_cmd.addr_high = 0; 4703 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4704 sata_cmd.esgl = 0; 4705 } 4706 /* scsi cdb */ 4707 sata_cmd.atapi_scsi_cdb[0] = 4708 cpu_to_le32(((task->ata_task.atapi_packet[0]) | 4709 (task->ata_task.atapi_packet[1] << 8) | 4710 (task->ata_task.atapi_packet[2] << 16) | 4711 (task->ata_task.atapi_packet[3] << 24))); 4712 sata_cmd.atapi_scsi_cdb[1] = 4713 cpu_to_le32(((task->ata_task.atapi_packet[4]) | 4714 (task->ata_task.atapi_packet[5] << 8) | 4715 (task->ata_task.atapi_packet[6] << 16) | 4716 (task->ata_task.atapi_packet[7] << 24))); 4717 sata_cmd.atapi_scsi_cdb[2] = 4718 cpu_to_le32(((task->ata_task.atapi_packet[8]) | 4719 (task->ata_task.atapi_packet[9] << 8) | 4720 (task->ata_task.atapi_packet[10] << 16) | 4721 (task->ata_task.atapi_packet[11] << 24))); 4722 sata_cmd.atapi_scsi_cdb[3] = 4723 cpu_to_le32(((task->ata_task.atapi_packet[12]) | 4724 (task->ata_task.atapi_packet[13] << 8) | 4725 (task->ata_task.atapi_packet[14] << 16) | 4726 (task->ata_task.atapi_packet[15] << 24))); 4727 } 4728 4729 /* Check for read log for failed drive and return */ 4730 if (sata_cmd.sata_fis.command == 0x2f) { 4731 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4732 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4733 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4734 struct task_status_struct *ts; 4735 4736 pm8001_ha_dev->id &= 0xDFFFFFFF; 4737 ts = &task->task_status; 4738 4739 spin_lock_irqsave(&task->task_state_lock, flags); 4740 ts->resp = SAS_TASK_COMPLETE; 4741 ts->stat = SAS_SAM_STAT_GOOD; 4742 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4743 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4744 task->task_state_flags |= SAS_TASK_STATE_DONE; 4745 if (unlikely((task->task_state_flags & 4746 SAS_TASK_STATE_ABORTED))) { 4747 spin_unlock_irqrestore(&task->task_state_lock, 4748 flags); 4749 pm8001_dbg(pm8001_ha, FAIL, 4750 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n", 4751 task, ts->resp, 4752 ts->stat); 4753 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4754 return 0; 4755 } else { 4756 spin_unlock_irqrestore(&task->task_state_lock, 4757 flags); 4758 pm8001_ccb_task_free_done(pm8001_ha, task, 4759 ccb, tag); 4760 atomic_dec(&pm8001_ha_dev->running_req); 4761 return 0; 4762 } 4763 } 4764 } 4765 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4766 &sata_cmd, sizeof(sata_cmd), q_index); 4767 return ret; 4768 } 4769 4770 /** 4771 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND 4772 * @pm8001_ha: our hba card information. 4773 * @phy_id: the phy id which we wanted to start up. 4774 */ 4775 static int 4776 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4777 { 4778 struct phy_start_req payload; 4779 struct inbound_queue_table *circularQ; 4780 int ret; 4781 u32 tag = 0x01; 4782 u32 opcode = OPC_INB_PHYSTART; 4783 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4784 memset(&payload, 0, sizeof(payload)); 4785 payload.tag = cpu_to_le32(tag); 4786 4787 pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id); 4788 4789 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4790 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id); 4791 /* SSC Disable and SAS Analog ST configuration */ 4792 /* 4793 payload.ase_sh_lm_slr_phyid = 4794 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | 4795 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | 4796 phy_id); 4797 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need 4798 */ 4799 4800 payload.sas_identify.dev_type = SAS_END_DEVICE; 4801 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4802 memcpy(payload.sas_identify.sas_addr, 4803 &pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4804 payload.sas_identify.phy_id = phy_id; 4805 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4806 sizeof(payload), 0); 4807 return ret; 4808 } 4809 4810 /** 4811 * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4812 * @pm8001_ha: our hba card information. 4813 * @phy_id: the phy id which we wanted to start up. 4814 */ 4815 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4816 u8 phy_id) 4817 { 4818 struct phy_stop_req payload; 4819 struct inbound_queue_table *circularQ; 4820 int ret; 4821 u32 tag = 0x01; 4822 u32 opcode = OPC_INB_PHYSTOP; 4823 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4824 memset(&payload, 0, sizeof(payload)); 4825 payload.tag = cpu_to_le32(tag); 4826 payload.phy_id = cpu_to_le32(phy_id); 4827 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4828 sizeof(payload), 0); 4829 return ret; 4830 } 4831 4832 /* 4833 * see comments on pm8001_mpi_reg_resp. 4834 */ 4835 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4836 struct pm8001_device *pm8001_dev, u32 flag) 4837 { 4838 struct reg_dev_req payload; 4839 u32 opc; 4840 u32 stp_sspsmp_sata = 0x4; 4841 struct inbound_queue_table *circularQ; 4842 u32 linkrate, phy_id; 4843 int rc, tag = 0xdeadbeef; 4844 struct pm8001_ccb_info *ccb; 4845 u8 retryFlag = 0x1; 4846 u16 firstBurstSize = 0; 4847 u16 ITNT = 2000; 4848 struct domain_device *dev = pm8001_dev->sas_device; 4849 struct domain_device *parent_dev = dev->parent; 4850 struct pm8001_port *port = dev->port->lldd_port; 4851 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4852 4853 memset(&payload, 0, sizeof(payload)); 4854 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4855 if (rc) 4856 return rc; 4857 ccb = &pm8001_ha->ccb_info[tag]; 4858 ccb->device = pm8001_dev; 4859 ccb->ccb_tag = tag; 4860 payload.tag = cpu_to_le32(tag); 4861 4862 if (flag == 1) { 4863 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4864 } else { 4865 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4866 stp_sspsmp_sata = 0x00; /* stp*/ 4867 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4868 dev_is_expander(pm8001_dev->dev_type)) 4869 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4870 } 4871 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4872 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4873 else 4874 phy_id = pm8001_dev->attached_phy; 4875 4876 opc = OPC_INB_REG_DEV; 4877 4878 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4879 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4880 4881 payload.phyid_portid = 4882 cpu_to_le32(((port->port_id) & 0xFF) | 4883 ((phy_id & 0xFF) << 8)); 4884 4885 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | 4886 ((linkrate & 0x0F) << 24) | 4887 ((stp_sspsmp_sata & 0x03) << 28)); 4888 payload.firstburstsize_ITNexustimeout = 4889 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4890 4891 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4892 SAS_ADDR_SIZE); 4893 4894 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4895 sizeof(payload), 0); 4896 if (rc) 4897 pm8001_tag_free(pm8001_ha, tag); 4898 4899 return rc; 4900 } 4901 4902 /** 4903 * pm80xx_chip_phy_ctl_req - support the local phy operation 4904 * @pm8001_ha: our hba card information. 4905 * @phyId: the phy id which we wanted to operate 4906 * @phy_op: phy operation to request 4907 */ 4908 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4909 u32 phyId, u32 phy_op) 4910 { 4911 u32 tag; 4912 int rc; 4913 struct local_phy_ctl_req payload; 4914 struct inbound_queue_table *circularQ; 4915 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4916 memset(&payload, 0, sizeof(payload)); 4917 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4918 if (rc) 4919 return rc; 4920 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4921 payload.tag = cpu_to_le32(tag); 4922 payload.phyop_phyid = 4923 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); 4924 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4925 sizeof(payload), 0); 4926 } 4927 4928 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4929 { 4930 #ifdef PM8001_USE_MSIX 4931 return 1; 4932 #else 4933 u32 value; 4934 4935 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4936 if (value) 4937 return 1; 4938 return 0; 4939 #endif 4940 } 4941 4942 /** 4943 * pm80xx_chip_isr - PM8001 isr handler. 4944 * @pm8001_ha: our hba card information. 4945 * @vec: irq number. 4946 */ 4947 static irqreturn_t 4948 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4949 { 4950 pm80xx_chip_interrupt_disable(pm8001_ha, vec); 4951 pm8001_dbg(pm8001_ha, DEVIO, 4952 "irq vec %d, ODMR:0x%x\n", 4953 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); 4954 process_oq(pm8001_ha, vec); 4955 pm80xx_chip_interrupt_enable(pm8001_ha, vec); 4956 return IRQ_HANDLED; 4957 } 4958 4959 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha, 4960 u32 operation, u32 phyid, 4961 u32 length, u32 *buf) 4962 { 4963 u32 tag, i, j = 0; 4964 int rc; 4965 struct set_phy_profile_req payload; 4966 struct inbound_queue_table *circularQ; 4967 u32 opc = OPC_INB_SET_PHY_PROFILE; 4968 4969 memset(&payload, 0, sizeof(payload)); 4970 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4971 if (rc) 4972 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n"); 4973 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4974 payload.tag = cpu_to_le32(tag); 4975 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF)); 4976 pm8001_dbg(pm8001_ha, INIT, 4977 " phy profile command for phy %x ,length is %d\n", 4978 payload.ppc_phyid, length); 4979 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { 4980 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i)); 4981 j++; 4982 } 4983 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4984 sizeof(payload), 0); 4985 if (rc) 4986 pm8001_tag_free(pm8001_ha, tag); 4987 } 4988 4989 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 4990 u32 length, u8 *buf) 4991 { 4992 u32 i; 4993 4994 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 4995 mpi_set_phy_profile_req(pm8001_ha, 4996 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf); 4997 length = length + PHY_DWORD_LENGTH; 4998 } 4999 pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n"); 5000 } 5001 5002 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, 5003 u32 phy, u32 length, u32 *buf) 5004 { 5005 u32 tag, opc; 5006 int rc, i; 5007 struct set_phy_profile_req payload; 5008 struct inbound_queue_table *circularQ; 5009 5010 memset(&payload, 0, sizeof(payload)); 5011 5012 rc = pm8001_tag_alloc(pm8001_ha, &tag); 5013 if (rc) 5014 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n"); 5015 5016 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 5017 opc = OPC_INB_SET_PHY_PROFILE; 5018 5019 payload.tag = cpu_to_le32(tag); 5020 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8) 5021 | (phy & 0xFF)); 5022 5023 for (i = 0; i < length; i++) 5024 payload.reserved[i] = cpu_to_le32(*(buf + i)); 5025 5026 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 5027 sizeof(payload), 0); 5028 if (rc) 5029 pm8001_tag_free(pm8001_ha, tag); 5030 5031 pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy); 5032 } 5033 const struct pm8001_dispatch pm8001_80xx_dispatch = { 5034 .name = "pmc80xx", 5035 .chip_init = pm80xx_chip_init, 5036 .chip_soft_rst = pm80xx_chip_soft_rst, 5037 .chip_rst = pm80xx_hw_chip_rst, 5038 .chip_iounmap = pm8001_chip_iounmap, 5039 .isr = pm80xx_chip_isr, 5040 .is_our_interrupt = pm80xx_chip_is_our_interrupt, 5041 .isr_process_oq = process_oq, 5042 .interrupt_enable = pm80xx_chip_interrupt_enable, 5043 .interrupt_disable = pm80xx_chip_interrupt_disable, 5044 .make_prd = pm8001_chip_make_sg, 5045 .smp_req = pm80xx_chip_smp_req, 5046 .ssp_io_req = pm80xx_chip_ssp_io_req, 5047 .sata_req = pm80xx_chip_sata_req, 5048 .phy_start_req = pm80xx_chip_phy_start_req, 5049 .phy_stop_req = pm80xx_chip_phy_stop_req, 5050 .reg_dev_req = pm80xx_chip_reg_dev_req, 5051 .dereg_dev_req = pm8001_chip_dereg_dev_req, 5052 .phy_ctl_req = pm80xx_chip_phy_ctl_req, 5053 .task_abort = pm8001_chip_abort_task, 5054 .ssp_tm_req = pm8001_chip_ssp_tm_req, 5055 .get_nvmd_req = pm8001_chip_get_nvmd_req, 5056 .set_nvmd_req = pm8001_chip_set_nvmd_req, 5057 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 5058 .set_dev_state_req = pm8001_chip_set_dev_state_req, 5059 .fatal_errors = pm80xx_fatal_errors, 5060 }; 5061