1 /* 2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 PMC-Sierra, Inc., 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/version.h> 41 #include <linux/slab.h> 42 #include "pm8001_sas.h" 43 #include "pm80xx_hwi.h" 44 #include "pm8001_chips.h" 45 #include "pm8001_ctl.h" 46 47 #define SMP_DIRECT 1 48 #define SMP_INDIRECT 2 49 50 51 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value) 52 { 53 u32 reg_val; 54 unsigned long start; 55 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); 56 /* confirm the setting is written */ 57 start = jiffies + HZ; /* 1 sec */ 58 do { 59 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); 60 } while ((reg_val != shift_value) && time_before(jiffies, start)); 61 if (reg_val != shift_value) { 62 PM8001_FAIL_DBG(pm8001_ha, 63 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER" 64 " = 0x%x\n", reg_val)); 65 return -1; 66 } 67 return 0; 68 } 69 70 void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset, 71 const void *destination, 72 u32 dw_count, u32 bus_base_number) 73 { 74 u32 index, value, offset; 75 u32 *destination1; 76 destination1 = (u32 *)destination; 77 78 for (index = 0; index < dw_count; index += 4, destination1++) { 79 offset = (soffset + index); 80 if (offset < (64 * 1024)) { 81 value = pm8001_cr32(pm8001_ha, bus_base_number, offset); 82 *destination1 = cpu_to_le32(value); 83 } 84 } 85 return; 86 } 87 88 ssize_t pm80xx_get_fatal_dump(struct device *cdev, 89 struct device_attribute *attr, char *buf) 90 { 91 struct Scsi_Host *shost = class_to_shost(cdev); 92 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 93 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 94 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; 95 u32 accum_len , reg_val, index, *temp; 96 u32 status = 1; 97 unsigned long start; 98 u8 *direct_data; 99 char *fatal_error_data = buf; 100 u32 length_to_read; 101 u32 offset; 102 103 pm8001_ha->forensic_info.data_buf.direct_data = buf; 104 if (pm8001_ha->chip_id == chip_8001) { 105 pm8001_ha->forensic_info.data_buf.direct_data += 106 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 107 "Not supported for SPC controller"); 108 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 109 (char *)buf; 110 } 111 /* initialize variables for very first call from host application */ 112 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 113 PM8001_IO_DBG(pm8001_ha, 114 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n")); 115 direct_data = (u8 *)fatal_error_data; 116 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; 117 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; 118 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 119 pm8001_ha->forensic_info.data_buf.read_len = 0; 120 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 121 122 /* Write signature to fatal dump table */ 123 pm8001_mw32(fatal_table_address, 124 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd); 125 126 pm8001_ha->forensic_info.data_buf.direct_data = direct_data; 127 PM8001_IO_DBG(pm8001_ha, 128 pm8001_printk("ossaHwCB: status1 %d\n", status)); 129 PM8001_IO_DBG(pm8001_ha, 130 pm8001_printk("ossaHwCB: read_len 0x%x\n", 131 pm8001_ha->forensic_info.data_buf.read_len)); 132 PM8001_IO_DBG(pm8001_ha, 133 pm8001_printk("ossaHwCB: direct_len 0x%x\n", 134 pm8001_ha->forensic_info.data_buf.direct_len)); 135 PM8001_IO_DBG(pm8001_ha, 136 pm8001_printk("ossaHwCB: direct_offset 0x%x\n", 137 pm8001_ha->forensic_info.data_buf.direct_offset)); 138 } 139 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 140 /* start to get data */ 141 /* Program the MEMBASE II Shifting Register with 0x00.*/ 142 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 143 pm8001_ha->fatal_forensic_shift_offset); 144 pm8001_ha->forensic_last_offset = 0; 145 pm8001_ha->forensic_fatal_step = 0; 146 pm8001_ha->fatal_bar_loc = 0; 147 } 148 149 /* Read until accum_len is retrived */ 150 accum_len = pm8001_mr32(fatal_table_address, 151 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 152 /* Determine length of data between previously stored transfer length 153 * and current accumulated transfer length 154 */ 155 length_to_read = 156 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer; 157 PM8001_IO_DBG(pm8001_ha, 158 pm8001_printk("get_fatal_spcv: accum_len 0x%x\n", accum_len)); 159 PM8001_IO_DBG(pm8001_ha, 160 pm8001_printk("get_fatal_spcv: length_to_read 0x%x\n", 161 length_to_read)); 162 PM8001_IO_DBG(pm8001_ha, 163 pm8001_printk("get_fatal_spcv: last_offset 0x%x\n", 164 pm8001_ha->forensic_last_offset)); 165 PM8001_IO_DBG(pm8001_ha, 166 pm8001_printk("get_fatal_spcv: read_len 0x%x\n", 167 pm8001_ha->forensic_info.data_buf.read_len)); 168 PM8001_IO_DBG(pm8001_ha, 169 pm8001_printk("get_fatal_spcv:: direct_len 0x%x\n", 170 pm8001_ha->forensic_info.data_buf.direct_len)); 171 PM8001_IO_DBG(pm8001_ha, 172 pm8001_printk("get_fatal_spcv:: direct_offset 0x%x\n", 173 pm8001_ha->forensic_info.data_buf.direct_offset)); 174 175 /* If accumulated length failed to read correctly fail the attempt.*/ 176 if (accum_len == 0xFFFFFFFF) { 177 PM8001_IO_DBG(pm8001_ha, 178 pm8001_printk("Possible PCI issue 0x%x not expected\n", 179 accum_len)); 180 return status; 181 } 182 /* If accumulated length is zero fail the attempt */ 183 if (accum_len == 0) { 184 pm8001_ha->forensic_info.data_buf.direct_data += 185 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 186 "%08x ", 0xFFFFFFFF); 187 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 188 (char *)buf; 189 } 190 /* Accumulated length is good so start capturing the first data */ 191 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 192 if (pm8001_ha->forensic_fatal_step == 0) { 193 moreData: 194 /* If data to read is less than SYSFS_OFFSET then reduce the 195 * length of dataLen 196 */ 197 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET 198 > length_to_read) { 199 pm8001_ha->forensic_info.data_buf.direct_len = 200 length_to_read - 201 pm8001_ha->forensic_last_offset; 202 } else { 203 pm8001_ha->forensic_info.data_buf.direct_len = 204 SYSFS_OFFSET; 205 } 206 if (pm8001_ha->forensic_info.data_buf.direct_data) { 207 /* Data is in bar, copy to host memory */ 208 pm80xx_pci_mem_copy(pm8001_ha, 209 pm8001_ha->fatal_bar_loc, 210 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, 211 pm8001_ha->forensic_info.data_buf.direct_len, 1); 212 } 213 pm8001_ha->fatal_bar_loc += 214 pm8001_ha->forensic_info.data_buf.direct_len; 215 pm8001_ha->forensic_info.data_buf.direct_offset += 216 pm8001_ha->forensic_info.data_buf.direct_len; 217 pm8001_ha->forensic_last_offset += 218 pm8001_ha->forensic_info.data_buf.direct_len; 219 pm8001_ha->forensic_info.data_buf.read_len = 220 pm8001_ha->forensic_info.data_buf.direct_len; 221 222 if (pm8001_ha->forensic_last_offset >= length_to_read) { 223 pm8001_ha->forensic_info.data_buf.direct_data += 224 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 225 "%08x ", 3); 226 for (index = 0; index < 227 (pm8001_ha->forensic_info.data_buf.direct_len 228 / 4); index++) { 229 pm8001_ha->forensic_info.data_buf.direct_data += 230 sprintf( 231 pm8001_ha->forensic_info.data_buf.direct_data, 232 "%08x ", *(temp + index)); 233 } 234 235 pm8001_ha->fatal_bar_loc = 0; 236 pm8001_ha->forensic_fatal_step = 1; 237 pm8001_ha->fatal_forensic_shift_offset = 0; 238 pm8001_ha->forensic_last_offset = 0; 239 status = 0; 240 offset = (int) 241 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 242 - (char *)buf); 243 PM8001_IO_DBG(pm8001_ha, 244 pm8001_printk("get_fatal_spcv:return1 0x%x\n", offset)); 245 return (char *)pm8001_ha-> 246 forensic_info.data_buf.direct_data - 247 (char *)buf; 248 } 249 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { 250 pm8001_ha->forensic_info.data_buf.direct_data += 251 sprintf(pm8001_ha-> 252 forensic_info.data_buf.direct_data, 253 "%08x ", 2); 254 for (index = 0; index < 255 (pm8001_ha->forensic_info.data_buf.direct_len 256 / 4); index++) { 257 pm8001_ha->forensic_info.data_buf.direct_data 258 += sprintf(pm8001_ha-> 259 forensic_info.data_buf.direct_data, 260 "%08x ", *(temp + index)); 261 } 262 status = 0; 263 offset = (int) 264 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 265 - (char *)buf); 266 PM8001_IO_DBG(pm8001_ha, 267 pm8001_printk("get_fatal_spcv:return2 0x%x\n", offset)); 268 return (char *)pm8001_ha-> 269 forensic_info.data_buf.direct_data - 270 (char *)buf; 271 } 272 273 /* Increment the MEMBASE II Shifting Register value by 0x100.*/ 274 pm8001_ha->forensic_info.data_buf.direct_data += 275 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 276 "%08x ", 2); 277 for (index = 0; index < 278 (pm8001_ha->forensic_info.data_buf.direct_len 279 / 4) ; index++) { 280 pm8001_ha->forensic_info.data_buf.direct_data += 281 sprintf(pm8001_ha-> 282 forensic_info.data_buf.direct_data, 283 "%08x ", *(temp + index)); 284 } 285 pm8001_ha->fatal_forensic_shift_offset += 0x100; 286 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 287 pm8001_ha->fatal_forensic_shift_offset); 288 pm8001_ha->fatal_bar_loc = 0; 289 status = 0; 290 offset = (int) 291 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 292 - (char *)buf); 293 PM8001_IO_DBG(pm8001_ha, 294 pm8001_printk("get_fatal_spcv: return3 0x%x\n", offset)); 295 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 296 (char *)buf; 297 } 298 if (pm8001_ha->forensic_fatal_step == 1) { 299 /* store previous accumulated length before triggering next 300 * accumulated length update 301 */ 302 pm8001_ha->forensic_preserved_accumulated_transfer = 303 pm8001_mr32(fatal_table_address, 304 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 305 306 /* continue capturing the fatal log until Dump status is 0x3 */ 307 if (pm8001_mr32(fatal_table_address, 308 MPI_FATAL_EDUMP_TABLE_STATUS) < 309 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) { 310 311 /* reset fddstat bit by writing to zero*/ 312 pm8001_mw32(fatal_table_address, 313 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0); 314 315 /* set dump control value to '1' so that new data will 316 * be transferred to shared memory 317 */ 318 pm8001_mw32(fatal_table_address, 319 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 320 MPI_FATAL_EDUMP_HANDSHAKE_RDY); 321 322 /*Poll FDDHSHK until clear */ 323 start = jiffies + (2 * HZ); /* 2 sec */ 324 325 do { 326 reg_val = pm8001_mr32(fatal_table_address, 327 MPI_FATAL_EDUMP_TABLE_HANDSHAKE); 328 } while ((reg_val) && time_before(jiffies, start)); 329 330 if (reg_val != 0) { 331 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 332 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n", 333 reg_val)); 334 /* Fail the dump if a timeout occurs */ 335 pm8001_ha->forensic_info.data_buf.direct_data += 336 sprintf( 337 pm8001_ha->forensic_info.data_buf.direct_data, 338 "%08x ", 0xFFFFFFFF); 339 return((char *) 340 pm8001_ha->forensic_info.data_buf.direct_data 341 - (char *)buf); 342 } 343 /* Poll status register until set to 2 or 344 * 3 for up to 2 seconds 345 */ 346 start = jiffies + (2 * HZ); /* 2 sec */ 347 348 do { 349 reg_val = pm8001_mr32(fatal_table_address, 350 MPI_FATAL_EDUMP_TABLE_STATUS); 351 } while (((reg_val != 2) || (reg_val != 3)) && 352 time_before(jiffies, start)); 353 354 if (reg_val < 2) { 355 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 356 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n", 357 reg_val)); 358 /* Fail the dump if a timeout occurs */ 359 pm8001_ha->forensic_info.data_buf.direct_data += 360 sprintf( 361 pm8001_ha->forensic_info.data_buf.direct_data, 362 "%08x ", 0xFFFFFFFF); 363 pm8001_cw32(pm8001_ha, 0, 364 MEMBASE_II_SHIFT_REGISTER, 365 pm8001_ha->fatal_forensic_shift_offset); 366 } 367 /* Read the next block of the debug data.*/ 368 length_to_read = pm8001_mr32(fatal_table_address, 369 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) - 370 pm8001_ha->forensic_preserved_accumulated_transfer; 371 if (length_to_read != 0x0) { 372 pm8001_ha->forensic_fatal_step = 0; 373 goto moreData; 374 } else { 375 pm8001_ha->forensic_info.data_buf.direct_data += 376 sprintf( 377 pm8001_ha->forensic_info.data_buf.direct_data, 378 "%08x ", 4); 379 pm8001_ha->forensic_info.data_buf.read_len 380 = 0xFFFFFFFF; 381 pm8001_ha->forensic_info.data_buf.direct_len 382 = 0; 383 pm8001_ha->forensic_info.data_buf.direct_offset 384 = 0; 385 pm8001_ha->forensic_info.data_buf.read_len = 0; 386 } 387 } 388 } 389 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data 390 - (char *)buf); 391 PM8001_IO_DBG(pm8001_ha, 392 pm8001_printk("get_fatal_spcv: return4 0x%x\n", offset)); 393 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 394 (char *)buf; 395 } 396 397 /** 398 * read_main_config_table - read the configure table and save it. 399 * @pm8001_ha: our hba card information 400 */ 401 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 402 { 403 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 404 405 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = 406 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); 407 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = 408 pm8001_mr32(address, MAIN_INTERFACE_REVISION); 409 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = 410 pm8001_mr32(address, MAIN_FW_REVISION); 411 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = 412 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); 413 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = 414 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); 415 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = 416 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); 417 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = 418 pm8001_mr32(address, MAIN_GST_OFFSET); 419 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = 420 pm8001_mr32(address, MAIN_IBQ_OFFSET); 421 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = 422 pm8001_mr32(address, MAIN_OBQ_OFFSET); 423 424 /* read Error Dump Offset and Length */ 425 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = 426 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 427 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = 428 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 429 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = 430 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 431 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = 432 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 433 434 /* read GPIO LED settings from the configuration table */ 435 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = 436 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); 437 438 /* read analog Setting offset from the configuration table */ 439 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = 440 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 441 442 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = 443 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); 444 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = 445 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); 446 /* read port recover and reset timeout */ 447 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer = 448 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER); 449 /* read ILA and inactive firmware version */ 450 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version = 451 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE); 452 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version = 453 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION); 454 455 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 456 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n", 457 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature, 458 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev, 459 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev)); 460 461 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 462 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n", 463 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset, 464 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset, 465 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset, 466 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset, 467 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset)); 468 469 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 470 "Main cfg table; ila rev:%x Inactive fw rev:%x\n", 471 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version, 472 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version)); 473 } 474 475 /** 476 * read_general_status_table - read the general status table and save it. 477 * @pm8001_ha: our hba card information 478 */ 479 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 480 { 481 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 482 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = 483 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); 484 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = 485 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); 486 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = 487 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); 488 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = 489 pm8001_mr32(address, GST_MSGUTCNT_OFFSET); 490 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = 491 pm8001_mr32(address, GST_IOPTCNT_OFFSET); 492 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = 493 pm8001_mr32(address, GST_GPIO_INPUT_VAL); 494 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = 495 pm8001_mr32(address, GST_RERRINFO_OFFSET0); 496 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = 497 pm8001_mr32(address, GST_RERRINFO_OFFSET1); 498 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = 499 pm8001_mr32(address, GST_RERRINFO_OFFSET2); 500 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = 501 pm8001_mr32(address, GST_RERRINFO_OFFSET3); 502 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = 503 pm8001_mr32(address, GST_RERRINFO_OFFSET4); 504 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = 505 pm8001_mr32(address, GST_RERRINFO_OFFSET5); 506 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = 507 pm8001_mr32(address, GST_RERRINFO_OFFSET6); 508 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = 509 pm8001_mr32(address, GST_RERRINFO_OFFSET7); 510 } 511 /** 512 * read_phy_attr_table - read the phy attribute table and save it. 513 * @pm8001_ha: our hba card information 514 */ 515 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) 516 { 517 void __iomem *address = pm8001_ha->pspa_q_tbl_addr; 518 pm8001_ha->phy_attr_table.phystart1_16[0] = 519 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); 520 pm8001_ha->phy_attr_table.phystart1_16[1] = 521 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); 522 pm8001_ha->phy_attr_table.phystart1_16[2] = 523 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); 524 pm8001_ha->phy_attr_table.phystart1_16[3] = 525 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); 526 pm8001_ha->phy_attr_table.phystart1_16[4] = 527 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); 528 pm8001_ha->phy_attr_table.phystart1_16[5] = 529 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); 530 pm8001_ha->phy_attr_table.phystart1_16[6] = 531 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); 532 pm8001_ha->phy_attr_table.phystart1_16[7] = 533 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); 534 pm8001_ha->phy_attr_table.phystart1_16[8] = 535 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); 536 pm8001_ha->phy_attr_table.phystart1_16[9] = 537 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); 538 pm8001_ha->phy_attr_table.phystart1_16[10] = 539 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); 540 pm8001_ha->phy_attr_table.phystart1_16[11] = 541 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); 542 pm8001_ha->phy_attr_table.phystart1_16[12] = 543 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); 544 pm8001_ha->phy_attr_table.phystart1_16[13] = 545 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); 546 pm8001_ha->phy_attr_table.phystart1_16[14] = 547 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); 548 pm8001_ha->phy_attr_table.phystart1_16[15] = 549 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); 550 551 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = 552 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); 553 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = 554 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); 555 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = 556 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); 557 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = 558 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); 559 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = 560 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); 561 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = 562 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); 563 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = 564 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); 565 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = 566 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); 567 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = 568 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); 569 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = 570 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); 571 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = 572 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); 573 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = 574 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); 575 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = 576 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); 577 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = 578 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); 579 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = 580 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); 581 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = 582 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); 583 584 } 585 586 /** 587 * read_inbnd_queue_table - read the inbound queue table and save it. 588 * @pm8001_ha: our hba card information 589 */ 590 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 591 { 592 int i; 593 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 594 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 595 u32 offset = i * 0x20; 596 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 597 get_pci_bar_index(pm8001_mr32(address, 598 (offset + IB_PIPCI_BAR))); 599 pm8001_ha->inbnd_q_tbl[i].pi_offset = 600 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); 601 } 602 } 603 604 /** 605 * read_outbnd_queue_table - read the outbound queue table and save it. 606 * @pm8001_ha: our hba card information 607 */ 608 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 609 { 610 int i; 611 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 612 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 613 u32 offset = i * 0x24; 614 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 615 get_pci_bar_index(pm8001_mr32(address, 616 (offset + OB_CIPCI_BAR))); 617 pm8001_ha->outbnd_q_tbl[i].ci_offset = 618 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); 619 } 620 } 621 622 /** 623 * init_default_table_values - init the default table. 624 * @pm8001_ha: our hba card information 625 */ 626 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 627 { 628 int i; 629 u32 offsetib, offsetob; 630 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 631 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 632 633 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = 634 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 635 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = 636 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 637 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = 638 PM8001_EVENT_LOG_SIZE; 639 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; 640 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = 641 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 642 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = 643 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 644 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = 645 PM8001_EVENT_LOG_SIZE; 646 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; 647 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; 648 649 /* Disable end to end CRC checking */ 650 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); 651 652 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 653 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 654 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 655 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 656 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi; 657 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 658 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo; 659 pm8001_ha->inbnd_q_tbl[i].base_virt = 660 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr; 661 pm8001_ha->inbnd_q_tbl[i].total_length = 662 pm8001_ha->memoryMap.region[IB + i].total_len; 663 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 664 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi; 665 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 666 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo; 667 pm8001_ha->inbnd_q_tbl[i].ci_virt = 668 pm8001_ha->memoryMap.region[CI + i].virt_ptr; 669 offsetib = i * 0x20; 670 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 671 get_pci_bar_index(pm8001_mr32(addressib, 672 (offsetib + 0x14))); 673 pm8001_ha->inbnd_q_tbl[i].pi_offset = 674 pm8001_mr32(addressib, (offsetib + 0x18)); 675 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 676 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 677 678 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 679 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i, 680 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar, 681 pm8001_ha->inbnd_q_tbl[i].pi_offset)); 682 } 683 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 684 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 685 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 686 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 687 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi; 688 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 689 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo; 690 pm8001_ha->outbnd_q_tbl[i].base_virt = 691 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr; 692 pm8001_ha->outbnd_q_tbl[i].total_length = 693 pm8001_ha->memoryMap.region[OB + i].total_len; 694 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 695 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi; 696 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 697 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo; 698 /* interrupt vector based on oq */ 699 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); 700 pm8001_ha->outbnd_q_tbl[i].pi_virt = 701 pm8001_ha->memoryMap.region[PI + i].virt_ptr; 702 offsetob = i * 0x24; 703 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 704 get_pci_bar_index(pm8001_mr32(addressob, 705 offsetob + 0x14)); 706 pm8001_ha->outbnd_q_tbl[i].ci_offset = 707 pm8001_mr32(addressob, (offsetob + 0x18)); 708 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 709 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 710 711 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 712 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i, 713 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar, 714 pm8001_ha->outbnd_q_tbl[i].ci_offset)); 715 } 716 } 717 718 /** 719 * update_main_config_table - update the main default table to the HBA. 720 * @pm8001_ha: our hba card information 721 */ 722 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 723 { 724 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 725 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, 726 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); 727 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, 728 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); 729 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, 730 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); 731 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, 732 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); 733 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, 734 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); 735 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, 736 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); 737 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, 738 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); 739 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, 740 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); 741 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, 742 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); 743 /* Update Fatal error interrupt vector */ 744 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 745 ((pm8001_ha->number_of_intr - 1) << 8); 746 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, 747 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); 748 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 749 "Updated Fatal error interrupt vector 0x%x\n", 750 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT))); 751 752 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, 753 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); 754 755 /* SPCv specific */ 756 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; 757 /* Set GPIOLED to 0x2 for LED indicator */ 758 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; 759 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, 760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); 761 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 762 "Programming DW 0x21 in main cfg table with 0x%x\n", 763 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET))); 764 765 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 766 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 767 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, 768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); 769 770 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000; 771 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 772 PORT_RECOVERY_TIMEOUT; 773 if (pm8001_ha->chip_id == chip_8006) { 774 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 775 0x0000ffff; 776 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 777 CHIP_8006_PORT_RECOVERY_TIMEOUT; 778 } 779 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 780 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 781 } 782 783 /** 784 * update_inbnd_queue_table - update the inbound queue table to the HBA. 785 * @pm8001_ha: our hba card information 786 */ 787 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 788 int number) 789 { 790 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 791 u16 offset = number * 0x20; 792 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, 793 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 794 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, 795 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 796 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, 797 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 798 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, 799 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 800 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, 801 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 802 803 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 804 "IQ %d: Element pri size 0x%x\n", 805 number, 806 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt)); 807 808 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 809 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n", 810 pm8001_ha->inbnd_q_tbl[number].upper_base_addr, 811 pm8001_ha->inbnd_q_tbl[number].lower_base_addr)); 812 813 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 814 "CI upper base addr 0x%x CI lower base addr 0x%x\n", 815 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr, 816 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr)); 817 } 818 819 /** 820 * update_outbnd_queue_table - update the outbound queue table to the HBA. 821 * @pm8001_ha: our hba card information 822 */ 823 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 824 int number) 825 { 826 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 827 u16 offset = number * 0x24; 828 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, 829 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 830 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, 831 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 832 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, 833 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 834 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, 835 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 836 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, 837 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 838 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, 839 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 840 841 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 842 "OQ %d: Element pri size 0x%x\n", 843 number, 844 pm8001_ha->outbnd_q_tbl[number].element_size_cnt)); 845 846 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 847 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n", 848 pm8001_ha->outbnd_q_tbl[number].upper_base_addr, 849 pm8001_ha->outbnd_q_tbl[number].lower_base_addr)); 850 851 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 852 "PI upper base addr 0x%x PI lower base addr 0x%x\n", 853 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr, 854 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr)); 855 } 856 857 /** 858 * mpi_init_check - check firmware initialization status. 859 * @pm8001_ha: our hba card information 860 */ 861 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 862 { 863 u32 max_wait_count; 864 u32 value; 865 u32 gst_len_mpistate; 866 867 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 868 table is updated */ 869 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); 870 /* wait until Inbound DoorBell Clear Register toggled */ 871 if (IS_SPCV_12G(pm8001_ha->pdev)) { 872 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 873 } else { 874 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 875 } 876 do { 877 udelay(1); 878 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 879 value &= SPCv_MSGU_CFG_TABLE_UPDATE; 880 } while ((value != 0) && (--max_wait_count)); 881 882 if (!max_wait_count) 883 return -1; 884 /* check the MPI-State for initialization upto 100ms*/ 885 max_wait_count = 100 * 1000;/* 100 msec */ 886 do { 887 udelay(1); 888 gst_len_mpistate = 889 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 890 GST_GSTLEN_MPIS_OFFSET); 891 } while ((GST_MPI_STATE_INIT != 892 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); 893 if (!max_wait_count) 894 return -1; 895 896 /* check MPI Initialization error */ 897 gst_len_mpistate = gst_len_mpistate >> 16; 898 if (0x0000 != gst_len_mpistate) 899 return -1; 900 901 return 0; 902 } 903 904 /** 905 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 906 * @pm8001_ha: our hba card information 907 */ 908 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 909 { 910 u32 value; 911 u32 max_wait_count; 912 u32 max_wait_time; 913 int ret = 0; 914 915 /* reset / PCIe ready */ 916 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */ 917 do { 918 udelay(1); 919 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 920 } while ((value == 0xFFFFFFFF) && (--max_wait_count)); 921 922 /* check ila status */ 923 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */ 924 do { 925 udelay(1); 926 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 927 } while (((value & SCRATCH_PAD_ILA_READY) != 928 SCRATCH_PAD_ILA_READY) && (--max_wait_count)); 929 if (!max_wait_count) 930 ret = -1; 931 else { 932 PM8001_MSG_DBG(pm8001_ha, 933 pm8001_printk(" ila ready status in %d millisec\n", 934 (max_wait_time - max_wait_count))); 935 } 936 937 /* check RAAE status */ 938 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */ 939 do { 940 udelay(1); 941 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 942 } while (((value & SCRATCH_PAD_RAAE_READY) != 943 SCRATCH_PAD_RAAE_READY) && (--max_wait_count)); 944 if (!max_wait_count) 945 ret = -1; 946 else { 947 PM8001_MSG_DBG(pm8001_ha, 948 pm8001_printk(" raae ready status in %d millisec\n", 949 (max_wait_time - max_wait_count))); 950 } 951 952 /* check iop0 status */ 953 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */ 954 do { 955 udelay(1); 956 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 957 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) && 958 (--max_wait_count)); 959 if (!max_wait_count) 960 ret = -1; 961 else { 962 PM8001_MSG_DBG(pm8001_ha, 963 pm8001_printk(" iop0 ready status in %d millisec\n", 964 (max_wait_time - max_wait_count))); 965 } 966 967 /* check iop1 status only for 16 port controllers */ 968 if ((pm8001_ha->chip_id != chip_8008) && 969 (pm8001_ha->chip_id != chip_8009)) { 970 /* 200 milli sec */ 971 max_wait_time = max_wait_count = 200 * 1000; 972 do { 973 udelay(1); 974 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 975 } while (((value & SCRATCH_PAD_IOP1_READY) != 976 SCRATCH_PAD_IOP1_READY) && (--max_wait_count)); 977 if (!max_wait_count) 978 ret = -1; 979 else { 980 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 981 "iop1 ready status in %d millisec\n", 982 (max_wait_time - max_wait_count))); 983 } 984 } 985 986 return ret; 987 } 988 989 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 990 { 991 void __iomem *base_addr; 992 u32 value; 993 u32 offset; 994 u32 pcibar; 995 u32 pcilogic; 996 997 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 998 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ 999 1000 PM8001_DEV_DBG(pm8001_ha, 1001 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n", 1002 offset, value)); 1003 pcilogic = (value & 0xFC000000) >> 26; 1004 pcibar = get_pci_bar_index(pcilogic); 1005 PM8001_INIT_DBG(pm8001_ha, 1006 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar)); 1007 pm8001_ha->main_cfg_tbl_addr = base_addr = 1008 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 1009 pm8001_ha->general_stat_tbl_addr = 1010 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 1011 0xFFFFFF); 1012 pm8001_ha->inbnd_q_tbl_addr = 1013 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & 1014 0xFFFFFF); 1015 pm8001_ha->outbnd_q_tbl_addr = 1016 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & 1017 0xFFFFFF); 1018 pm8001_ha->ivt_tbl_addr = 1019 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & 1020 0xFFFFFF); 1021 pm8001_ha->pspa_q_tbl_addr = 1022 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & 1023 0xFFFFFF); 1024 pm8001_ha->fatal_tbl_addr = 1025 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & 1026 0xFFFFFF); 1027 1028 PM8001_INIT_DBG(pm8001_ha, 1029 pm8001_printk("GST OFFSET 0x%x\n", 1030 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18))); 1031 PM8001_INIT_DBG(pm8001_ha, 1032 pm8001_printk("INBND OFFSET 0x%x\n", 1033 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C))); 1034 PM8001_INIT_DBG(pm8001_ha, 1035 pm8001_printk("OBND OFFSET 0x%x\n", 1036 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20))); 1037 PM8001_INIT_DBG(pm8001_ha, 1038 pm8001_printk("IVT OFFSET 0x%x\n", 1039 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C))); 1040 PM8001_INIT_DBG(pm8001_ha, 1041 pm8001_printk("PSPA OFFSET 0x%x\n", 1042 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90))); 1043 PM8001_INIT_DBG(pm8001_ha, 1044 pm8001_printk("addr - main cfg %p general status %p\n", 1045 pm8001_ha->main_cfg_tbl_addr, 1046 pm8001_ha->general_stat_tbl_addr)); 1047 PM8001_INIT_DBG(pm8001_ha, 1048 pm8001_printk("addr - inbnd %p obnd %p\n", 1049 pm8001_ha->inbnd_q_tbl_addr, 1050 pm8001_ha->outbnd_q_tbl_addr)); 1051 PM8001_INIT_DBG(pm8001_ha, 1052 pm8001_printk("addr - pspa %p ivt %p\n", 1053 pm8001_ha->pspa_q_tbl_addr, 1054 pm8001_ha->ivt_tbl_addr)); 1055 } 1056 1057 /** 1058 * pm80xx_set_thermal_config - support the thermal configuration 1059 * @pm8001_ha: our hba card information. 1060 */ 1061 int 1062 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) 1063 { 1064 struct set_ctrl_cfg_req payload; 1065 struct inbound_queue_table *circularQ; 1066 int rc; 1067 u32 tag; 1068 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1069 u32 page_code; 1070 1071 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1072 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1073 if (rc) 1074 return -1; 1075 1076 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1077 payload.tag = cpu_to_le32(tag); 1078 1079 if (IS_SPCV_12G(pm8001_ha->pdev)) 1080 page_code = THERMAL_PAGE_CODE_7H; 1081 else 1082 page_code = THERMAL_PAGE_CODE_8H; 1083 1084 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) | 1085 (THERMAL_ENABLE << 8) | page_code; 1086 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8); 1087 1088 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 1089 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n", 1090 payload.cfg_pg[0], payload.cfg_pg[1])); 1091 1092 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1093 sizeof(payload), 0); 1094 if (rc) 1095 pm8001_tag_free(pm8001_ha, tag); 1096 return rc; 1097 1098 } 1099 1100 /** 1101 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol 1102 * Timer configuration page 1103 * @pm8001_ha: our hba card information. 1104 */ 1105 static int 1106 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) 1107 { 1108 struct set_ctrl_cfg_req payload; 1109 struct inbound_queue_table *circularQ; 1110 SASProtocolTimerConfig_t SASConfigPage; 1111 int rc; 1112 u32 tag; 1113 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1114 1115 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1116 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); 1117 1118 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1119 1120 if (rc) 1121 return -1; 1122 1123 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1124 payload.tag = cpu_to_le32(tag); 1125 1126 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE; 1127 SASConfigPage.MST_MSI = 3 << 15; 1128 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO; 1129 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) | 1130 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER; 1131 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME; 1132 1133 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF) 1134 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF; 1135 1136 1137 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) | 1138 SAS_OPNRJT_RTRY_INTVL; 1139 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16) 1140 | SAS_COPNRJT_RTRY_TMO; 1141 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16) 1142 | SAS_COPNRJT_RTRY_THR; 1143 SASConfigPage.MAX_AIP = SAS_MAX_AIP; 1144 1145 PM8001_INIT_DBG(pm8001_ha, 1146 pm8001_printk("SASConfigPage.pageCode " 1147 "0x%08x\n", SASConfigPage.pageCode)); 1148 PM8001_INIT_DBG(pm8001_ha, 1149 pm8001_printk("SASConfigPage.MST_MSI " 1150 " 0x%08x\n", SASConfigPage.MST_MSI)); 1151 PM8001_INIT_DBG(pm8001_ha, 1152 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO " 1153 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO)); 1154 PM8001_INIT_DBG(pm8001_ha, 1155 pm8001_printk("SASConfigPage.STP_FRM_TMO " 1156 " 0x%08x\n", SASConfigPage.STP_FRM_TMO)); 1157 PM8001_INIT_DBG(pm8001_ha, 1158 pm8001_printk("SASConfigPage.STP_IDLE_TMO " 1159 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO)); 1160 PM8001_INIT_DBG(pm8001_ha, 1161 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL " 1162 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL)); 1163 PM8001_INIT_DBG(pm8001_ha, 1164 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO " 1165 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO)); 1166 PM8001_INIT_DBG(pm8001_ha, 1167 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR " 1168 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR)); 1169 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP " 1170 " 0x%08x\n", SASConfigPage.MAX_AIP)); 1171 1172 memcpy(&payload.cfg_pg, &SASConfigPage, 1173 sizeof(SASProtocolTimerConfig_t)); 1174 1175 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1176 sizeof(payload), 0); 1177 if (rc) 1178 pm8001_tag_free(pm8001_ha, tag); 1179 1180 return rc; 1181 } 1182 1183 /** 1184 * pm80xx_get_encrypt_info - Check for encryption 1185 * @pm8001_ha: our hba card information. 1186 */ 1187 static int 1188 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) 1189 { 1190 u32 scratch3_value; 1191 int ret = -1; 1192 1193 /* Read encryption status from SCRATCH PAD 3 */ 1194 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1195 1196 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1197 SCRATCH_PAD3_ENC_READY) { 1198 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1199 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1200 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1201 SCRATCH_PAD3_SMF_ENABLED) 1202 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1203 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1204 SCRATCH_PAD3_SMA_ENABLED) 1205 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1206 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1207 SCRATCH_PAD3_SMB_ENABLED) 1208 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1209 pm8001_ha->encrypt_info.status = 0; 1210 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1211 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X." 1212 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", 1213 scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 1214 pm8001_ha->encrypt_info.sec_mode, 1215 pm8001_ha->encrypt_info.status)); 1216 ret = 0; 1217 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == 1218 SCRATCH_PAD3_ENC_DISABLED) { 1219 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1220 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", 1221 scratch3_value)); 1222 pm8001_ha->encrypt_info.status = 0xFFFFFFFF; 1223 pm8001_ha->encrypt_info.cipher_mode = 0; 1224 pm8001_ha->encrypt_info.sec_mode = 0; 1225 ret = 0; 1226 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1227 SCRATCH_PAD3_ENC_DIS_ERR) { 1228 pm8001_ha->encrypt_info.status = 1229 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1230 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1231 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1232 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1233 SCRATCH_PAD3_SMF_ENABLED) 1234 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1235 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1236 SCRATCH_PAD3_SMA_ENABLED) 1237 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1238 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1239 SCRATCH_PAD3_SMB_ENABLED) 1240 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1241 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1242 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X." 1243 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1244 scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 1245 pm8001_ha->encrypt_info.sec_mode, 1246 pm8001_ha->encrypt_info.status)); 1247 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1248 SCRATCH_PAD3_ENC_ENA_ERR) { 1249 1250 pm8001_ha->encrypt_info.status = 1251 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1252 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1253 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1254 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1255 SCRATCH_PAD3_SMF_ENABLED) 1256 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1257 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1258 SCRATCH_PAD3_SMA_ENABLED) 1259 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1260 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1261 SCRATCH_PAD3_SMB_ENABLED) 1262 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1263 1264 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1265 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X." 1266 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1267 scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 1268 pm8001_ha->encrypt_info.sec_mode, 1269 pm8001_ha->encrypt_info.status)); 1270 } 1271 return ret; 1272 } 1273 1274 /** 1275 * pm80xx_encrypt_update - update flash with encryption informtion 1276 * @pm8001_ha: our hba card information. 1277 */ 1278 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) 1279 { 1280 struct kek_mgmt_req payload; 1281 struct inbound_queue_table *circularQ; 1282 int rc; 1283 u32 tag; 1284 u32 opc = OPC_INB_KEK_MANAGEMENT; 1285 1286 memset(&payload, 0, sizeof(struct kek_mgmt_req)); 1287 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1288 if (rc) 1289 return -1; 1290 1291 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1292 payload.tag = cpu_to_le32(tag); 1293 /* Currently only one key is used. New KEK index is 1. 1294 * Current KEK index is 1. Store KEK to NVRAM is 1. 1295 */ 1296 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) | 1297 KEK_MGMT_SUBOP_KEYCARDUPDATE); 1298 1299 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 1300 "Saving Encryption info to flash. payload 0x%x\n", 1301 payload.new_curidx_ksop)); 1302 1303 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1304 sizeof(payload), 0); 1305 if (rc) 1306 pm8001_tag_free(pm8001_ha, tag); 1307 1308 return rc; 1309 } 1310 1311 /** 1312 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 1313 * @pm8001_ha: our hba card information 1314 */ 1315 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) 1316 { 1317 int ret; 1318 u8 i = 0; 1319 1320 /* check the firmware status */ 1321 if (-1 == check_fw_ready(pm8001_ha)) { 1322 PM8001_FAIL_DBG(pm8001_ha, 1323 pm8001_printk("Firmware is not ready!\n")); 1324 return -EBUSY; 1325 } 1326 1327 /* Initialize the controller fatal error flag */ 1328 pm8001_ha->controller_fatal_error = false; 1329 1330 /* Initialize pci space address eg: mpi offset */ 1331 init_pci_device_addresses(pm8001_ha); 1332 init_default_table_values(pm8001_ha); 1333 read_main_config_table(pm8001_ha); 1334 read_general_status_table(pm8001_ha); 1335 read_inbnd_queue_table(pm8001_ha); 1336 read_outbnd_queue_table(pm8001_ha); 1337 read_phy_attr_table(pm8001_ha); 1338 1339 /* update main config table ,inbound table and outbound table */ 1340 update_main_config_table(pm8001_ha); 1341 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) 1342 update_inbnd_queue_table(pm8001_ha, i); 1343 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) 1344 update_outbnd_queue_table(pm8001_ha, i); 1345 1346 /* notify firmware update finished and check initialization status */ 1347 if (0 == mpi_init_check(pm8001_ha)) { 1348 PM8001_INIT_DBG(pm8001_ha, 1349 pm8001_printk("MPI initialize successful!\n")); 1350 } else 1351 return -EBUSY; 1352 1353 /* send SAS protocol timer configuration page to FW */ 1354 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha); 1355 1356 /* Check for encryption */ 1357 if (pm8001_ha->chip->encrypt) { 1358 PM8001_INIT_DBG(pm8001_ha, 1359 pm8001_printk("Checking for encryption\n")); 1360 ret = pm80xx_get_encrypt_info(pm8001_ha); 1361 if (ret == -1) { 1362 PM8001_INIT_DBG(pm8001_ha, 1363 pm8001_printk("Encryption error !!\n")); 1364 if (pm8001_ha->encrypt_info.status == 0x81) { 1365 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 1366 "Encryption enabled with error." 1367 "Saving encryption key to flash\n")); 1368 pm80xx_encrypt_update(pm8001_ha); 1369 } 1370 } 1371 } 1372 return 0; 1373 } 1374 1375 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 1376 { 1377 u32 max_wait_count; 1378 u32 value; 1379 u32 gst_len_mpistate; 1380 init_pci_device_addresses(pm8001_ha); 1381 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 1382 table is stop */ 1383 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); 1384 1385 /* wait until Inbound DoorBell Clear Register toggled */ 1386 if (IS_SPCV_12G(pm8001_ha->pdev)) { 1387 max_wait_count = 4 * 1000 * 1000;/* 4 sec */ 1388 } else { 1389 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1390 } 1391 do { 1392 udelay(1); 1393 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1394 value &= SPCv_MSGU_CFG_TABLE_RESET; 1395 } while ((value != 0) && (--max_wait_count)); 1396 1397 if (!max_wait_count) { 1398 PM8001_FAIL_DBG(pm8001_ha, 1399 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value)); 1400 return -1; 1401 } 1402 1403 /* check the MPI-State for termination in progress */ 1404 /* wait until Inbound DoorBell Clear Register toggled */ 1405 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */ 1406 do { 1407 udelay(1); 1408 gst_len_mpistate = 1409 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1410 GST_GSTLEN_MPIS_OFFSET); 1411 if (GST_MPI_STATE_UNINIT == 1412 (gst_len_mpistate & GST_MPI_STATE_MASK)) 1413 break; 1414 } while (--max_wait_count); 1415 if (!max_wait_count) { 1416 PM8001_FAIL_DBG(pm8001_ha, 1417 pm8001_printk(" TIME OUT MPI State = 0x%x\n", 1418 gst_len_mpistate & GST_MPI_STATE_MASK)); 1419 return -1; 1420 } 1421 1422 return 0; 1423 } 1424 1425 /** 1426 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 1427 * the FW register status to the originated status. 1428 * @pm8001_ha: our hba card information 1429 */ 1430 1431 static int 1432 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 1433 { 1434 u32 regval; 1435 u32 bootloader_state; 1436 u32 ibutton0, ibutton1; 1437 1438 /* Process MPI table uninitialization only if FW is ready */ 1439 if (!pm8001_ha->controller_fatal_error) { 1440 /* Check if MPI is in ready state to reset */ 1441 if (mpi_uninit_check(pm8001_ha) != 0) { 1442 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1443 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1444 "MPI state is not ready scratch1 :0x%x\n", 1445 regval)); 1446 return -1; 1447 } 1448 } 1449 /* checked for reset register normal state; 0x0 */ 1450 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1451 PM8001_INIT_DBG(pm8001_ha, 1452 pm8001_printk("reset register before write : 0x%x\n", regval)); 1453 1454 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); 1455 msleep(500); 1456 1457 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1458 PM8001_INIT_DBG(pm8001_ha, 1459 pm8001_printk("reset register after write 0x%x\n", regval)); 1460 1461 if ((regval & SPCv_SOFT_RESET_READ_MASK) == 1462 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { 1463 PM8001_MSG_DBG(pm8001_ha, 1464 pm8001_printk(" soft reset successful [regval: 0x%x]\n", 1465 regval)); 1466 } else { 1467 PM8001_MSG_DBG(pm8001_ha, 1468 pm8001_printk(" soft reset failed [regval: 0x%x]\n", 1469 regval)); 1470 1471 /* check bootloader is successfully executed or in HDA mode */ 1472 bootloader_state = 1473 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1474 SCRATCH_PAD1_BOOTSTATE_MASK; 1475 1476 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { 1477 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1478 "Bootloader state - HDA mode SEEPROM\n")); 1479 } else if (bootloader_state == 1480 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { 1481 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1482 "Bootloader state - HDA mode Bootstrap Pin\n")); 1483 } else if (bootloader_state == 1484 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { 1485 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1486 "Bootloader state - HDA mode soft reset\n")); 1487 } else if (bootloader_state == 1488 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { 1489 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1490 "Bootloader state-HDA mode critical error\n")); 1491 } 1492 return -EBUSY; 1493 } 1494 1495 /* check the firmware status after reset */ 1496 if (-1 == check_fw_ready(pm8001_ha)) { 1497 PM8001_FAIL_DBG(pm8001_ha, 1498 pm8001_printk("Firmware is not ready!\n")); 1499 /* check iButton feature support for motherboard controller */ 1500 if (pm8001_ha->pdev->subsystem_vendor != 1501 PCI_VENDOR_ID_ADAPTEC2 && 1502 pm8001_ha->pdev->subsystem_vendor != 1503 PCI_VENDOR_ID_ATTO && 1504 pm8001_ha->pdev->subsystem_vendor != 0) { 1505 ibutton0 = pm8001_cr32(pm8001_ha, 0, 1506 MSGU_HOST_SCRATCH_PAD_6); 1507 ibutton1 = pm8001_cr32(pm8001_ha, 0, 1508 MSGU_HOST_SCRATCH_PAD_7); 1509 if (!ibutton0 && !ibutton1) { 1510 PM8001_FAIL_DBG(pm8001_ha, 1511 pm8001_printk("iButton Feature is" 1512 " not Available!!!\n")); 1513 return -EBUSY; 1514 } 1515 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { 1516 PM8001_FAIL_DBG(pm8001_ha, 1517 pm8001_printk("CRC Check for iButton" 1518 " Feature Failed!!!\n")); 1519 return -EBUSY; 1520 } 1521 } 1522 } 1523 PM8001_INIT_DBG(pm8001_ha, 1524 pm8001_printk("SPCv soft reset Complete\n")); 1525 return 0; 1526 } 1527 1528 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1529 { 1530 u32 i; 1531 1532 PM8001_INIT_DBG(pm8001_ha, 1533 pm8001_printk("chip reset start\n")); 1534 1535 /* do SPCv chip reset. */ 1536 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); 1537 PM8001_INIT_DBG(pm8001_ha, 1538 pm8001_printk("SPC soft reset Complete\n")); 1539 1540 /* Check this ..whether delay is required or no */ 1541 /* delay 10 usec */ 1542 udelay(10); 1543 1544 /* wait for 20 msec until the firmware gets reloaded */ 1545 i = 20; 1546 do { 1547 mdelay(1); 1548 } while ((--i) != 0); 1549 1550 PM8001_INIT_DBG(pm8001_ha, 1551 pm8001_printk("chip reset finished\n")); 1552 } 1553 1554 /** 1555 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1556 * @pm8001_ha: our hba card information 1557 */ 1558 static void 1559 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1560 { 1561 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1562 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1563 } 1564 1565 /** 1566 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1567 * @pm8001_ha: our hba card information 1568 */ 1569 static void 1570 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1571 { 1572 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); 1573 } 1574 1575 /** 1576 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1577 * @pm8001_ha: our hba card information 1578 */ 1579 static void 1580 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1581 { 1582 #ifdef PM8001_USE_MSIX 1583 u32 mask; 1584 mask = (u32)(1 << vec); 1585 1586 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); 1587 return; 1588 #endif 1589 pm80xx_chip_intx_interrupt_enable(pm8001_ha); 1590 1591 } 1592 1593 /** 1594 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt 1595 * @pm8001_ha: our hba card information 1596 */ 1597 static void 1598 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1599 { 1600 #ifdef PM8001_USE_MSIX 1601 u32 mask; 1602 if (vec == 0xFF) 1603 mask = 0xFFFFFFFF; 1604 else 1605 mask = (u32)(1 << vec); 1606 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); 1607 return; 1608 #endif 1609 pm80xx_chip_intx_interrupt_disable(pm8001_ha); 1610 } 1611 1612 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1613 struct pm8001_device *pm8001_ha_dev) 1614 { 1615 int res; 1616 u32 ccb_tag; 1617 struct pm8001_ccb_info *ccb; 1618 struct sas_task *task = NULL; 1619 struct task_abort_req task_abort; 1620 struct inbound_queue_table *circularQ; 1621 u32 opc = OPC_INB_SATA_ABORT; 1622 int ret; 1623 1624 if (!pm8001_ha_dev) { 1625 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n")); 1626 return; 1627 } 1628 1629 task = sas_alloc_slow_task(GFP_ATOMIC); 1630 1631 if (!task) { 1632 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot " 1633 "allocate task\n")); 1634 return; 1635 } 1636 1637 task->task_done = pm8001_task_done; 1638 1639 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1640 if (res) { 1641 sas_free_task(task); 1642 return; 1643 } 1644 1645 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1646 ccb->device = pm8001_ha_dev; 1647 ccb->ccb_tag = ccb_tag; 1648 ccb->task = task; 1649 1650 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1651 1652 memset(&task_abort, 0, sizeof(task_abort)); 1653 task_abort.abort_all = cpu_to_le32(1); 1654 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1655 task_abort.tag = cpu_to_le32(ccb_tag); 1656 1657 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 1658 sizeof(task_abort), 0); 1659 PM8001_FAIL_DBG(pm8001_ha, 1660 pm8001_printk("Executing abort task end\n")); 1661 if (ret) { 1662 sas_free_task(task); 1663 pm8001_tag_free(pm8001_ha, ccb_tag); 1664 } 1665 } 1666 1667 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha, 1668 struct pm8001_device *pm8001_ha_dev) 1669 { 1670 struct sata_start_req sata_cmd; 1671 int res; 1672 u32 ccb_tag; 1673 struct pm8001_ccb_info *ccb; 1674 struct sas_task *task = NULL; 1675 struct host_to_dev_fis fis; 1676 struct domain_device *dev; 1677 struct inbound_queue_table *circularQ; 1678 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1679 1680 task = sas_alloc_slow_task(GFP_ATOMIC); 1681 1682 if (!task) { 1683 PM8001_FAIL_DBG(pm8001_ha, 1684 pm8001_printk("cannot allocate task !!!\n")); 1685 return; 1686 } 1687 task->task_done = pm8001_task_done; 1688 1689 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1690 if (res) { 1691 sas_free_task(task); 1692 PM8001_FAIL_DBG(pm8001_ha, 1693 pm8001_printk("cannot allocate tag !!!\n")); 1694 return; 1695 } 1696 1697 /* allocate domain device by ourselves as libsas 1698 * is not going to provide any 1699 */ 1700 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1701 if (!dev) { 1702 sas_free_task(task); 1703 pm8001_tag_free(pm8001_ha, ccb_tag); 1704 PM8001_FAIL_DBG(pm8001_ha, 1705 pm8001_printk("Domain device cannot be allocated\n")); 1706 return; 1707 } 1708 1709 task->dev = dev; 1710 task->dev->lldd_dev = pm8001_ha_dev; 1711 1712 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1713 ccb->device = pm8001_ha_dev; 1714 ccb->ccb_tag = ccb_tag; 1715 ccb->task = task; 1716 ccb->n_elem = 0; 1717 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1718 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1719 1720 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1721 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1722 1723 /* construct read log FIS */ 1724 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1725 fis.fis_type = 0x27; 1726 fis.flags = 0x80; 1727 fis.command = ATA_CMD_READ_LOG_EXT; 1728 fis.lbal = 0x10; 1729 fis.sector_count = 0x1; 1730 1731 sata_cmd.tag = cpu_to_le32(ccb_tag); 1732 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1733 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9)); 1734 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1735 1736 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 1737 sizeof(sata_cmd), 0); 1738 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Executing read log end\n")); 1739 if (res) { 1740 sas_free_task(task); 1741 pm8001_tag_free(pm8001_ha, ccb_tag); 1742 kfree(dev); 1743 } 1744 } 1745 1746 /** 1747 * mpi_ssp_completion- process the event that FW response to the SSP request. 1748 * @pm8001_ha: our hba card information 1749 * @piomb: the message contents of this outbound message. 1750 * 1751 * When FW has completed a ssp request for example a IO request, after it has 1752 * filled the SG data with the data, it will trigger this event represent 1753 * that he has finished the job,please check the coresponding buffer. 1754 * So we will tell the caller who maybe waiting the result to tell upper layer 1755 * that the task has been finished. 1756 */ 1757 static void 1758 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1759 { 1760 struct sas_task *t; 1761 struct pm8001_ccb_info *ccb; 1762 unsigned long flags; 1763 u32 status; 1764 u32 param; 1765 u32 tag; 1766 struct ssp_completion_resp *psspPayload; 1767 struct task_status_struct *ts; 1768 struct ssp_response_iu *iu; 1769 struct pm8001_device *pm8001_dev; 1770 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1771 status = le32_to_cpu(psspPayload->status); 1772 tag = le32_to_cpu(psspPayload->tag); 1773 ccb = &pm8001_ha->ccb_info[tag]; 1774 if ((status == IO_ABORTED) && ccb->open_retry) { 1775 /* Being completed by another */ 1776 ccb->open_retry = 0; 1777 return; 1778 } 1779 pm8001_dev = ccb->device; 1780 param = le32_to_cpu(psspPayload->param); 1781 t = ccb->task; 1782 1783 if (status && status != IO_UNDERFLOW) 1784 PM8001_FAIL_DBG(pm8001_ha, 1785 pm8001_printk("sas IO status 0x%x\n", status)); 1786 if (unlikely(!t || !t->lldd_task || !t->dev)) 1787 return; 1788 ts = &t->task_status; 1789 1790 PM8001_DEV_DBG(pm8001_ha, pm8001_printk( 1791 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t)); 1792 1793 /* Print sas address of IO failed device */ 1794 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1795 (status != IO_UNDERFLOW)) 1796 PM8001_FAIL_DBG(pm8001_ha, 1797 pm8001_printk("SAS Address of IO Failure Drive" 1798 ":%016llx", SAS_ADDR(t->dev->sas_addr))); 1799 1800 switch (status) { 1801 case IO_SUCCESS: 1802 PM8001_IO_DBG(pm8001_ha, 1803 pm8001_printk("IO_SUCCESS ,param = 0x%x\n", 1804 param)); 1805 if (param == 0) { 1806 ts->resp = SAS_TASK_COMPLETE; 1807 ts->stat = SAM_STAT_GOOD; 1808 } else { 1809 ts->resp = SAS_TASK_COMPLETE; 1810 ts->stat = SAS_PROTO_RESPONSE; 1811 ts->residual = param; 1812 iu = &psspPayload->ssp_resp_iu; 1813 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1814 } 1815 if (pm8001_dev) 1816 pm8001_dev->running_req--; 1817 break; 1818 case IO_ABORTED: 1819 PM8001_IO_DBG(pm8001_ha, 1820 pm8001_printk("IO_ABORTED IOMB Tag\n")); 1821 ts->resp = SAS_TASK_COMPLETE; 1822 ts->stat = SAS_ABORTED_TASK; 1823 break; 1824 case IO_UNDERFLOW: 1825 /* SSP Completion with error */ 1826 PM8001_IO_DBG(pm8001_ha, 1827 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n", 1828 param)); 1829 ts->resp = SAS_TASK_COMPLETE; 1830 ts->stat = SAS_DATA_UNDERRUN; 1831 ts->residual = param; 1832 if (pm8001_dev) 1833 pm8001_dev->running_req--; 1834 break; 1835 case IO_NO_DEVICE: 1836 PM8001_IO_DBG(pm8001_ha, 1837 pm8001_printk("IO_NO_DEVICE\n")); 1838 ts->resp = SAS_TASK_UNDELIVERED; 1839 ts->stat = SAS_PHY_DOWN; 1840 break; 1841 case IO_XFER_ERROR_BREAK: 1842 PM8001_IO_DBG(pm8001_ha, 1843 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1844 ts->resp = SAS_TASK_COMPLETE; 1845 ts->stat = SAS_OPEN_REJECT; 1846 /* Force the midlayer to retry */ 1847 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1848 break; 1849 case IO_XFER_ERROR_PHY_NOT_READY: 1850 PM8001_IO_DBG(pm8001_ha, 1851 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1852 ts->resp = SAS_TASK_COMPLETE; 1853 ts->stat = SAS_OPEN_REJECT; 1854 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1855 break; 1856 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME: 1857 PM8001_IO_DBG(pm8001_ha, 1858 pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n")); 1859 ts->resp = SAS_TASK_COMPLETE; 1860 ts->stat = SAS_OPEN_REJECT; 1861 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1862 break; 1863 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1864 PM8001_IO_DBG(pm8001_ha, 1865 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1866 ts->resp = SAS_TASK_COMPLETE; 1867 ts->stat = SAS_OPEN_REJECT; 1868 ts->open_rej_reason = SAS_OREJ_EPROTO; 1869 break; 1870 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1871 PM8001_IO_DBG(pm8001_ha, 1872 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1873 ts->resp = SAS_TASK_COMPLETE; 1874 ts->stat = SAS_OPEN_REJECT; 1875 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1876 break; 1877 case IO_OPEN_CNX_ERROR_BREAK: 1878 PM8001_IO_DBG(pm8001_ha, 1879 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1880 ts->resp = SAS_TASK_COMPLETE; 1881 ts->stat = SAS_OPEN_REJECT; 1882 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1883 break; 1884 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1885 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 1886 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 1887 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 1888 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 1889 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 1890 PM8001_IO_DBG(pm8001_ha, 1891 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1892 ts->resp = SAS_TASK_COMPLETE; 1893 ts->stat = SAS_OPEN_REJECT; 1894 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1895 if (!t->uldd_task) 1896 pm8001_handle_event(pm8001_ha, 1897 pm8001_dev, 1898 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1899 break; 1900 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1901 PM8001_IO_DBG(pm8001_ha, 1902 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1903 ts->resp = SAS_TASK_COMPLETE; 1904 ts->stat = SAS_OPEN_REJECT; 1905 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1906 break; 1907 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1908 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1909 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 1910 ts->resp = SAS_TASK_COMPLETE; 1911 ts->stat = SAS_OPEN_REJECT; 1912 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1913 break; 1914 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1915 PM8001_IO_DBG(pm8001_ha, 1916 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1917 ts->resp = SAS_TASK_UNDELIVERED; 1918 ts->stat = SAS_OPEN_REJECT; 1919 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1920 break; 1921 case IO_XFER_ERROR_NAK_RECEIVED: 1922 PM8001_IO_DBG(pm8001_ha, 1923 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 1924 ts->resp = SAS_TASK_COMPLETE; 1925 ts->stat = SAS_OPEN_REJECT; 1926 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1927 break; 1928 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1929 PM8001_IO_DBG(pm8001_ha, 1930 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 1931 ts->resp = SAS_TASK_COMPLETE; 1932 ts->stat = SAS_NAK_R_ERR; 1933 break; 1934 case IO_XFER_ERROR_DMA: 1935 PM8001_IO_DBG(pm8001_ha, 1936 pm8001_printk("IO_XFER_ERROR_DMA\n")); 1937 ts->resp = SAS_TASK_COMPLETE; 1938 ts->stat = SAS_OPEN_REJECT; 1939 break; 1940 case IO_XFER_OPEN_RETRY_TIMEOUT: 1941 PM8001_IO_DBG(pm8001_ha, 1942 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1943 ts->resp = SAS_TASK_COMPLETE; 1944 ts->stat = SAS_OPEN_REJECT; 1945 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1946 break; 1947 case IO_XFER_ERROR_OFFSET_MISMATCH: 1948 PM8001_IO_DBG(pm8001_ha, 1949 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 1950 ts->resp = SAS_TASK_COMPLETE; 1951 ts->stat = SAS_OPEN_REJECT; 1952 break; 1953 case IO_PORT_IN_RESET: 1954 PM8001_IO_DBG(pm8001_ha, 1955 pm8001_printk("IO_PORT_IN_RESET\n")); 1956 ts->resp = SAS_TASK_COMPLETE; 1957 ts->stat = SAS_OPEN_REJECT; 1958 break; 1959 case IO_DS_NON_OPERATIONAL: 1960 PM8001_IO_DBG(pm8001_ha, 1961 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 1962 ts->resp = SAS_TASK_COMPLETE; 1963 ts->stat = SAS_OPEN_REJECT; 1964 if (!t->uldd_task) 1965 pm8001_handle_event(pm8001_ha, 1966 pm8001_dev, 1967 IO_DS_NON_OPERATIONAL); 1968 break; 1969 case IO_DS_IN_RECOVERY: 1970 PM8001_IO_DBG(pm8001_ha, 1971 pm8001_printk("IO_DS_IN_RECOVERY\n")); 1972 ts->resp = SAS_TASK_COMPLETE; 1973 ts->stat = SAS_OPEN_REJECT; 1974 break; 1975 case IO_TM_TAG_NOT_FOUND: 1976 PM8001_IO_DBG(pm8001_ha, 1977 pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); 1978 ts->resp = SAS_TASK_COMPLETE; 1979 ts->stat = SAS_OPEN_REJECT; 1980 break; 1981 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 1982 PM8001_IO_DBG(pm8001_ha, 1983 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); 1984 ts->resp = SAS_TASK_COMPLETE; 1985 ts->stat = SAS_OPEN_REJECT; 1986 break; 1987 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 1988 PM8001_IO_DBG(pm8001_ha, 1989 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 1990 ts->resp = SAS_TASK_COMPLETE; 1991 ts->stat = SAS_OPEN_REJECT; 1992 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1993 break; 1994 default: 1995 PM8001_DEVIO_DBG(pm8001_ha, 1996 pm8001_printk("Unknown status 0x%x\n", status)); 1997 /* not allowed case. Therefore, return failed status */ 1998 ts->resp = SAS_TASK_COMPLETE; 1999 ts->stat = SAS_OPEN_REJECT; 2000 break; 2001 } 2002 PM8001_IO_DBG(pm8001_ha, 2003 pm8001_printk("scsi_status = 0x%x\n ", 2004 psspPayload->ssp_resp_iu.status)); 2005 spin_lock_irqsave(&t->task_state_lock, flags); 2006 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2007 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2008 t->task_state_flags |= SAS_TASK_STATE_DONE; 2009 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2010 spin_unlock_irqrestore(&t->task_state_lock, flags); 2011 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 2012 "task 0x%p done with io_status 0x%x resp 0x%x " 2013 "stat 0x%x but aborted by upper layer!\n", 2014 t, status, ts->resp, ts->stat)); 2015 if (t->slow_task) 2016 complete(&t->slow_task->completion); 2017 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2018 } else { 2019 spin_unlock_irqrestore(&t->task_state_lock, flags); 2020 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2021 mb();/* in order to force CPU ordering */ 2022 t->task_done(t); 2023 } 2024 } 2025 2026 /*See the comments for mpi_ssp_completion */ 2027 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2028 { 2029 struct sas_task *t; 2030 unsigned long flags; 2031 struct task_status_struct *ts; 2032 struct pm8001_ccb_info *ccb; 2033 struct pm8001_device *pm8001_dev; 2034 struct ssp_event_resp *psspPayload = 2035 (struct ssp_event_resp *)(piomb + 4); 2036 u32 event = le32_to_cpu(psspPayload->event); 2037 u32 tag = le32_to_cpu(psspPayload->tag); 2038 u32 port_id = le32_to_cpu(psspPayload->port_id); 2039 2040 ccb = &pm8001_ha->ccb_info[tag]; 2041 t = ccb->task; 2042 pm8001_dev = ccb->device; 2043 if (event) 2044 PM8001_FAIL_DBG(pm8001_ha, 2045 pm8001_printk("sas IO status 0x%x\n", event)); 2046 if (unlikely(!t || !t->lldd_task || !t->dev)) 2047 return; 2048 ts = &t->task_status; 2049 PM8001_IOERR_DBG(pm8001_ha, 2050 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n", 2051 port_id, tag, event)); 2052 switch (event) { 2053 case IO_OVERFLOW: 2054 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) 2055 ts->resp = SAS_TASK_COMPLETE; 2056 ts->stat = SAS_DATA_OVERRUN; 2057 ts->residual = 0; 2058 if (pm8001_dev) 2059 pm8001_dev->running_req--; 2060 break; 2061 case IO_XFER_ERROR_BREAK: 2062 PM8001_IO_DBG(pm8001_ha, 2063 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2064 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2065 return; 2066 case IO_XFER_ERROR_PHY_NOT_READY: 2067 PM8001_IO_DBG(pm8001_ha, 2068 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2069 ts->resp = SAS_TASK_COMPLETE; 2070 ts->stat = SAS_OPEN_REJECT; 2071 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2072 break; 2073 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2074 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2075 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2076 ts->resp = SAS_TASK_COMPLETE; 2077 ts->stat = SAS_OPEN_REJECT; 2078 ts->open_rej_reason = SAS_OREJ_EPROTO; 2079 break; 2080 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2081 PM8001_IO_DBG(pm8001_ha, 2082 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2083 ts->resp = SAS_TASK_COMPLETE; 2084 ts->stat = SAS_OPEN_REJECT; 2085 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2086 break; 2087 case IO_OPEN_CNX_ERROR_BREAK: 2088 PM8001_IO_DBG(pm8001_ha, 2089 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2090 ts->resp = SAS_TASK_COMPLETE; 2091 ts->stat = SAS_OPEN_REJECT; 2092 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2093 break; 2094 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2095 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2096 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2097 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2098 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2099 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2100 PM8001_IO_DBG(pm8001_ha, 2101 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2102 ts->resp = SAS_TASK_COMPLETE; 2103 ts->stat = SAS_OPEN_REJECT; 2104 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2105 if (!t->uldd_task) 2106 pm8001_handle_event(pm8001_ha, 2107 pm8001_dev, 2108 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2109 break; 2110 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2111 PM8001_IO_DBG(pm8001_ha, 2112 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2113 ts->resp = SAS_TASK_COMPLETE; 2114 ts->stat = SAS_OPEN_REJECT; 2115 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2116 break; 2117 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2118 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2119 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2120 ts->resp = SAS_TASK_COMPLETE; 2121 ts->stat = SAS_OPEN_REJECT; 2122 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2123 break; 2124 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2125 PM8001_IO_DBG(pm8001_ha, 2126 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2127 ts->resp = SAS_TASK_COMPLETE; 2128 ts->stat = SAS_OPEN_REJECT; 2129 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2130 break; 2131 case IO_XFER_ERROR_NAK_RECEIVED: 2132 PM8001_IO_DBG(pm8001_ha, 2133 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2134 ts->resp = SAS_TASK_COMPLETE; 2135 ts->stat = SAS_OPEN_REJECT; 2136 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2137 break; 2138 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2139 PM8001_IO_DBG(pm8001_ha, 2140 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2141 ts->resp = SAS_TASK_COMPLETE; 2142 ts->stat = SAS_NAK_R_ERR; 2143 break; 2144 case IO_XFER_OPEN_RETRY_TIMEOUT: 2145 PM8001_IO_DBG(pm8001_ha, 2146 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2147 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2148 return; 2149 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2150 PM8001_IO_DBG(pm8001_ha, 2151 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2152 ts->resp = SAS_TASK_COMPLETE; 2153 ts->stat = SAS_DATA_OVERRUN; 2154 break; 2155 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2156 PM8001_IO_DBG(pm8001_ha, 2157 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2158 ts->resp = SAS_TASK_COMPLETE; 2159 ts->stat = SAS_DATA_OVERRUN; 2160 break; 2161 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2162 PM8001_IO_DBG(pm8001_ha, 2163 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2164 ts->resp = SAS_TASK_COMPLETE; 2165 ts->stat = SAS_DATA_OVERRUN; 2166 break; 2167 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2168 PM8001_IO_DBG(pm8001_ha, 2169 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); 2170 ts->resp = SAS_TASK_COMPLETE; 2171 ts->stat = SAS_DATA_OVERRUN; 2172 break; 2173 case IO_XFER_ERROR_OFFSET_MISMATCH: 2174 PM8001_IO_DBG(pm8001_ha, 2175 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2176 ts->resp = SAS_TASK_COMPLETE; 2177 ts->stat = SAS_DATA_OVERRUN; 2178 break; 2179 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2180 PM8001_IO_DBG(pm8001_ha, 2181 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2182 ts->resp = SAS_TASK_COMPLETE; 2183 ts->stat = SAS_DATA_OVERRUN; 2184 break; 2185 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2186 PM8001_IOERR_DBG(pm8001_ha, 2187 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n")); 2188 /* TBC: used default set values */ 2189 ts->resp = SAS_TASK_COMPLETE; 2190 ts->stat = SAS_DATA_OVERRUN; 2191 break; 2192 case IO_XFER_CMD_FRAME_ISSUED: 2193 PM8001_IO_DBG(pm8001_ha, 2194 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 2195 return; 2196 default: 2197 PM8001_DEVIO_DBG(pm8001_ha, 2198 pm8001_printk("Unknown status 0x%x\n", event)); 2199 /* not allowed case. Therefore, return failed status */ 2200 ts->resp = SAS_TASK_COMPLETE; 2201 ts->stat = SAS_DATA_OVERRUN; 2202 break; 2203 } 2204 spin_lock_irqsave(&t->task_state_lock, flags); 2205 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2206 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2207 t->task_state_flags |= SAS_TASK_STATE_DONE; 2208 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2209 spin_unlock_irqrestore(&t->task_state_lock, flags); 2210 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 2211 "task 0x%p done with event 0x%x resp 0x%x " 2212 "stat 0x%x but aborted by upper layer!\n", 2213 t, event, ts->resp, ts->stat)); 2214 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2215 } else { 2216 spin_unlock_irqrestore(&t->task_state_lock, flags); 2217 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2218 mb();/* in order to force CPU ordering */ 2219 t->task_done(t); 2220 } 2221 } 2222 2223 /*See the comments for mpi_ssp_completion */ 2224 static void 2225 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2226 { 2227 struct sas_task *t; 2228 struct pm8001_ccb_info *ccb; 2229 u32 param; 2230 u32 status; 2231 u32 tag; 2232 int i, j; 2233 u8 sata_addr_low[4]; 2234 u32 temp_sata_addr_low, temp_sata_addr_hi; 2235 u8 sata_addr_hi[4]; 2236 struct sata_completion_resp *psataPayload; 2237 struct task_status_struct *ts; 2238 struct ata_task_resp *resp ; 2239 u32 *sata_resp; 2240 struct pm8001_device *pm8001_dev; 2241 unsigned long flags; 2242 2243 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2244 status = le32_to_cpu(psataPayload->status); 2245 tag = le32_to_cpu(psataPayload->tag); 2246 2247 if (!tag) { 2248 PM8001_FAIL_DBG(pm8001_ha, 2249 pm8001_printk("tag null\n")); 2250 return; 2251 } 2252 ccb = &pm8001_ha->ccb_info[tag]; 2253 param = le32_to_cpu(psataPayload->param); 2254 if (ccb) { 2255 t = ccb->task; 2256 pm8001_dev = ccb->device; 2257 } else { 2258 PM8001_FAIL_DBG(pm8001_ha, 2259 pm8001_printk("ccb null\n")); 2260 return; 2261 } 2262 2263 if (t) { 2264 if (t->dev && (t->dev->lldd_dev)) 2265 pm8001_dev = t->dev->lldd_dev; 2266 } else { 2267 PM8001_FAIL_DBG(pm8001_ha, 2268 pm8001_printk("task null\n")); 2269 return; 2270 } 2271 2272 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2273 && unlikely(!t || !t->lldd_task || !t->dev)) { 2274 PM8001_FAIL_DBG(pm8001_ha, 2275 pm8001_printk("task or dev null\n")); 2276 return; 2277 } 2278 2279 ts = &t->task_status; 2280 if (!ts) { 2281 PM8001_FAIL_DBG(pm8001_ha, 2282 pm8001_printk("ts null\n")); 2283 return; 2284 } 2285 2286 if (unlikely(status)) 2287 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk( 2288 "status:0x%x, tag:0x%x, task::0x%p\n", 2289 status, tag, t)); 2290 2291 /* Print sas address of IO failed device */ 2292 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2293 (status != IO_UNDERFLOW)) { 2294 if (!((t->dev->parent) && 2295 (dev_is_expander(t->dev->parent->dev_type)))) { 2296 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++) 2297 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2298 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++) 2299 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2300 memcpy(&temp_sata_addr_low, sata_addr_low, 2301 sizeof(sata_addr_low)); 2302 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2303 sizeof(sata_addr_hi)); 2304 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2305 |((temp_sata_addr_hi << 8) & 2306 0xff0000) | 2307 ((temp_sata_addr_hi >> 8) 2308 & 0xff00) | 2309 ((temp_sata_addr_hi << 24) & 2310 0xff000000)); 2311 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2312 & 0xff) | 2313 ((temp_sata_addr_low << 8) 2314 & 0xff0000) | 2315 ((temp_sata_addr_low >> 8) 2316 & 0xff00) | 2317 ((temp_sata_addr_low << 24) 2318 & 0xff000000)) + 2319 pm8001_dev->attached_phy + 2320 0x10); 2321 PM8001_FAIL_DBG(pm8001_ha, 2322 pm8001_printk("SAS Address of IO Failure Drive:" 2323 "%08x%08x", temp_sata_addr_hi, 2324 temp_sata_addr_low)); 2325 2326 } else { 2327 PM8001_FAIL_DBG(pm8001_ha, 2328 pm8001_printk("SAS Address of IO Failure Drive:" 2329 "%016llx", SAS_ADDR(t->dev->sas_addr))); 2330 } 2331 } 2332 switch (status) { 2333 case IO_SUCCESS: 2334 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2335 if (param == 0) { 2336 ts->resp = SAS_TASK_COMPLETE; 2337 ts->stat = SAM_STAT_GOOD; 2338 /* check if response is for SEND READ LOG */ 2339 if (pm8001_dev && 2340 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2341 /* set new bit for abort_all */ 2342 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2343 /* clear bit for read log */ 2344 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2345 pm80xx_send_abort_all(pm8001_ha, pm8001_dev); 2346 /* Free the tag */ 2347 pm8001_tag_free(pm8001_ha, tag); 2348 sas_free_task(t); 2349 return; 2350 } 2351 } else { 2352 u8 len; 2353 ts->resp = SAS_TASK_COMPLETE; 2354 ts->stat = SAS_PROTO_RESPONSE; 2355 ts->residual = param; 2356 PM8001_IO_DBG(pm8001_ha, 2357 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", 2358 param)); 2359 sata_resp = &psataPayload->sata_resp[0]; 2360 resp = (struct ata_task_resp *)ts->buf; 2361 if (t->ata_task.dma_xfer == 0 && 2362 t->data_dir == DMA_FROM_DEVICE) { 2363 len = sizeof(struct pio_setup_fis); 2364 PM8001_IO_DBG(pm8001_ha, 2365 pm8001_printk("PIO read len = %d\n", len)); 2366 } else if (t->ata_task.use_ncq) { 2367 len = sizeof(struct set_dev_bits_fis); 2368 PM8001_IO_DBG(pm8001_ha, 2369 pm8001_printk("FPDMA len = %d\n", len)); 2370 } else { 2371 len = sizeof(struct dev_to_host_fis); 2372 PM8001_IO_DBG(pm8001_ha, 2373 pm8001_printk("other len = %d\n", len)); 2374 } 2375 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2376 resp->frame_len = len; 2377 memcpy(&resp->ending_fis[0], sata_resp, len); 2378 ts->buf_valid_size = sizeof(*resp); 2379 } else 2380 PM8001_IO_DBG(pm8001_ha, 2381 pm8001_printk("response to large\n")); 2382 } 2383 if (pm8001_dev) 2384 pm8001_dev->running_req--; 2385 break; 2386 case IO_ABORTED: 2387 PM8001_IO_DBG(pm8001_ha, 2388 pm8001_printk("IO_ABORTED IOMB Tag\n")); 2389 ts->resp = SAS_TASK_COMPLETE; 2390 ts->stat = SAS_ABORTED_TASK; 2391 if (pm8001_dev) 2392 pm8001_dev->running_req--; 2393 break; 2394 /* following cases are to do cases */ 2395 case IO_UNDERFLOW: 2396 /* SATA Completion with error */ 2397 PM8001_IO_DBG(pm8001_ha, 2398 pm8001_printk("IO_UNDERFLOW param = %d\n", param)); 2399 ts->resp = SAS_TASK_COMPLETE; 2400 ts->stat = SAS_DATA_UNDERRUN; 2401 ts->residual = param; 2402 if (pm8001_dev) 2403 pm8001_dev->running_req--; 2404 break; 2405 case IO_NO_DEVICE: 2406 PM8001_IO_DBG(pm8001_ha, 2407 pm8001_printk("IO_NO_DEVICE\n")); 2408 ts->resp = SAS_TASK_UNDELIVERED; 2409 ts->stat = SAS_PHY_DOWN; 2410 break; 2411 case IO_XFER_ERROR_BREAK: 2412 PM8001_IO_DBG(pm8001_ha, 2413 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2414 ts->resp = SAS_TASK_COMPLETE; 2415 ts->stat = SAS_INTERRUPTED; 2416 break; 2417 case IO_XFER_ERROR_PHY_NOT_READY: 2418 PM8001_IO_DBG(pm8001_ha, 2419 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2420 ts->resp = SAS_TASK_COMPLETE; 2421 ts->stat = SAS_OPEN_REJECT; 2422 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2423 break; 2424 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2425 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2426 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2427 ts->resp = SAS_TASK_COMPLETE; 2428 ts->stat = SAS_OPEN_REJECT; 2429 ts->open_rej_reason = SAS_OREJ_EPROTO; 2430 break; 2431 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2432 PM8001_IO_DBG(pm8001_ha, 2433 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2434 ts->resp = SAS_TASK_COMPLETE; 2435 ts->stat = SAS_OPEN_REJECT; 2436 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2437 break; 2438 case IO_OPEN_CNX_ERROR_BREAK: 2439 PM8001_IO_DBG(pm8001_ha, 2440 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2441 ts->resp = SAS_TASK_COMPLETE; 2442 ts->stat = SAS_OPEN_REJECT; 2443 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2444 break; 2445 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2446 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2447 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2448 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2449 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2450 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2451 PM8001_IO_DBG(pm8001_ha, 2452 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2453 ts->resp = SAS_TASK_COMPLETE; 2454 ts->stat = SAS_DEV_NO_RESPONSE; 2455 if (!t->uldd_task) { 2456 pm8001_handle_event(pm8001_ha, 2457 pm8001_dev, 2458 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2459 ts->resp = SAS_TASK_UNDELIVERED; 2460 ts->stat = SAS_QUEUE_FULL; 2461 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2462 return; 2463 } 2464 break; 2465 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2466 PM8001_IO_DBG(pm8001_ha, 2467 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2468 ts->resp = SAS_TASK_UNDELIVERED; 2469 ts->stat = SAS_OPEN_REJECT; 2470 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2471 if (!t->uldd_task) { 2472 pm8001_handle_event(pm8001_ha, 2473 pm8001_dev, 2474 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2475 ts->resp = SAS_TASK_UNDELIVERED; 2476 ts->stat = SAS_QUEUE_FULL; 2477 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2478 return; 2479 } 2480 break; 2481 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2482 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2483 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2484 ts->resp = SAS_TASK_COMPLETE; 2485 ts->stat = SAS_OPEN_REJECT; 2486 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2487 break; 2488 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2489 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2490 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n")); 2491 ts->resp = SAS_TASK_COMPLETE; 2492 ts->stat = SAS_DEV_NO_RESPONSE; 2493 if (!t->uldd_task) { 2494 pm8001_handle_event(pm8001_ha, 2495 pm8001_dev, 2496 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2497 ts->resp = SAS_TASK_UNDELIVERED; 2498 ts->stat = SAS_QUEUE_FULL; 2499 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2500 return; 2501 } 2502 break; 2503 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2504 PM8001_IO_DBG(pm8001_ha, 2505 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2506 ts->resp = SAS_TASK_COMPLETE; 2507 ts->stat = SAS_OPEN_REJECT; 2508 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2509 break; 2510 case IO_XFER_ERROR_NAK_RECEIVED: 2511 PM8001_IO_DBG(pm8001_ha, 2512 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2513 ts->resp = SAS_TASK_COMPLETE; 2514 ts->stat = SAS_NAK_R_ERR; 2515 break; 2516 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2517 PM8001_IO_DBG(pm8001_ha, 2518 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2519 ts->resp = SAS_TASK_COMPLETE; 2520 ts->stat = SAS_NAK_R_ERR; 2521 break; 2522 case IO_XFER_ERROR_DMA: 2523 PM8001_IO_DBG(pm8001_ha, 2524 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2525 ts->resp = SAS_TASK_COMPLETE; 2526 ts->stat = SAS_ABORTED_TASK; 2527 break; 2528 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2529 PM8001_IO_DBG(pm8001_ha, 2530 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); 2531 ts->resp = SAS_TASK_UNDELIVERED; 2532 ts->stat = SAS_DEV_NO_RESPONSE; 2533 break; 2534 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2535 PM8001_IO_DBG(pm8001_ha, 2536 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2537 ts->resp = SAS_TASK_COMPLETE; 2538 ts->stat = SAS_DATA_UNDERRUN; 2539 break; 2540 case IO_XFER_OPEN_RETRY_TIMEOUT: 2541 PM8001_IO_DBG(pm8001_ha, 2542 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2543 ts->resp = SAS_TASK_COMPLETE; 2544 ts->stat = SAS_OPEN_TO; 2545 break; 2546 case IO_PORT_IN_RESET: 2547 PM8001_IO_DBG(pm8001_ha, 2548 pm8001_printk("IO_PORT_IN_RESET\n")); 2549 ts->resp = SAS_TASK_COMPLETE; 2550 ts->stat = SAS_DEV_NO_RESPONSE; 2551 break; 2552 case IO_DS_NON_OPERATIONAL: 2553 PM8001_IO_DBG(pm8001_ha, 2554 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2555 ts->resp = SAS_TASK_COMPLETE; 2556 ts->stat = SAS_DEV_NO_RESPONSE; 2557 if (!t->uldd_task) { 2558 pm8001_handle_event(pm8001_ha, pm8001_dev, 2559 IO_DS_NON_OPERATIONAL); 2560 ts->resp = SAS_TASK_UNDELIVERED; 2561 ts->stat = SAS_QUEUE_FULL; 2562 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2563 return; 2564 } 2565 break; 2566 case IO_DS_IN_RECOVERY: 2567 PM8001_IO_DBG(pm8001_ha, 2568 pm8001_printk("IO_DS_IN_RECOVERY\n")); 2569 ts->resp = SAS_TASK_COMPLETE; 2570 ts->stat = SAS_DEV_NO_RESPONSE; 2571 break; 2572 case IO_DS_IN_ERROR: 2573 PM8001_IO_DBG(pm8001_ha, 2574 pm8001_printk("IO_DS_IN_ERROR\n")); 2575 ts->resp = SAS_TASK_COMPLETE; 2576 ts->stat = SAS_DEV_NO_RESPONSE; 2577 if (!t->uldd_task) { 2578 pm8001_handle_event(pm8001_ha, pm8001_dev, 2579 IO_DS_IN_ERROR); 2580 ts->resp = SAS_TASK_UNDELIVERED; 2581 ts->stat = SAS_QUEUE_FULL; 2582 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2583 return; 2584 } 2585 break; 2586 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2587 PM8001_IO_DBG(pm8001_ha, 2588 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2589 ts->resp = SAS_TASK_COMPLETE; 2590 ts->stat = SAS_OPEN_REJECT; 2591 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2592 break; 2593 default: 2594 PM8001_DEVIO_DBG(pm8001_ha, 2595 pm8001_printk("Unknown status 0x%x\n", status)); 2596 /* not allowed case. Therefore, return failed status */ 2597 ts->resp = SAS_TASK_COMPLETE; 2598 ts->stat = SAS_DEV_NO_RESPONSE; 2599 break; 2600 } 2601 spin_lock_irqsave(&t->task_state_lock, flags); 2602 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2603 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2604 t->task_state_flags |= SAS_TASK_STATE_DONE; 2605 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2606 spin_unlock_irqrestore(&t->task_state_lock, flags); 2607 PM8001_FAIL_DBG(pm8001_ha, 2608 pm8001_printk("task 0x%p done with io_status 0x%x" 2609 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2610 t, status, ts->resp, ts->stat)); 2611 if (t->slow_task) 2612 complete(&t->slow_task->completion); 2613 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2614 } else { 2615 spin_unlock_irqrestore(&t->task_state_lock, flags); 2616 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2617 } 2618 } 2619 2620 /*See the comments for mpi_ssp_completion */ 2621 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2622 { 2623 struct sas_task *t; 2624 struct task_status_struct *ts; 2625 struct pm8001_ccb_info *ccb; 2626 struct pm8001_device *pm8001_dev; 2627 struct sata_event_resp *psataPayload = 2628 (struct sata_event_resp *)(piomb + 4); 2629 u32 event = le32_to_cpu(psataPayload->event); 2630 u32 tag = le32_to_cpu(psataPayload->tag); 2631 u32 port_id = le32_to_cpu(psataPayload->port_id); 2632 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2633 unsigned long flags; 2634 2635 ccb = &pm8001_ha->ccb_info[tag]; 2636 2637 if (ccb) { 2638 t = ccb->task; 2639 pm8001_dev = ccb->device; 2640 } else { 2641 PM8001_FAIL_DBG(pm8001_ha, 2642 pm8001_printk("No CCB !!!. returning\n")); 2643 return; 2644 } 2645 if (event) 2646 PM8001_FAIL_DBG(pm8001_ha, 2647 pm8001_printk("SATA EVENT 0x%x\n", event)); 2648 2649 /* Check if this is NCQ error */ 2650 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2651 /* find device using device id */ 2652 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2653 /* send read log extension */ 2654 if (pm8001_dev) 2655 pm80xx_send_read_log(pm8001_ha, pm8001_dev); 2656 return; 2657 } 2658 2659 if (unlikely(!t || !t->lldd_task || !t->dev)) { 2660 PM8001_FAIL_DBG(pm8001_ha, 2661 pm8001_printk("task or dev null\n")); 2662 return; 2663 } 2664 2665 ts = &t->task_status; 2666 PM8001_IOERR_DBG(pm8001_ha, 2667 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n", 2668 port_id, tag, event)); 2669 switch (event) { 2670 case IO_OVERFLOW: 2671 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2672 ts->resp = SAS_TASK_COMPLETE; 2673 ts->stat = SAS_DATA_OVERRUN; 2674 ts->residual = 0; 2675 if (pm8001_dev) 2676 pm8001_dev->running_req--; 2677 break; 2678 case IO_XFER_ERROR_BREAK: 2679 PM8001_IO_DBG(pm8001_ha, 2680 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2681 ts->resp = SAS_TASK_COMPLETE; 2682 ts->stat = SAS_INTERRUPTED; 2683 break; 2684 case IO_XFER_ERROR_PHY_NOT_READY: 2685 PM8001_IO_DBG(pm8001_ha, 2686 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2687 ts->resp = SAS_TASK_COMPLETE; 2688 ts->stat = SAS_OPEN_REJECT; 2689 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2690 break; 2691 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2692 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2693 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2694 ts->resp = SAS_TASK_COMPLETE; 2695 ts->stat = SAS_OPEN_REJECT; 2696 ts->open_rej_reason = SAS_OREJ_EPROTO; 2697 break; 2698 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2699 PM8001_IO_DBG(pm8001_ha, 2700 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2701 ts->resp = SAS_TASK_COMPLETE; 2702 ts->stat = SAS_OPEN_REJECT; 2703 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2704 break; 2705 case IO_OPEN_CNX_ERROR_BREAK: 2706 PM8001_IO_DBG(pm8001_ha, 2707 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2708 ts->resp = SAS_TASK_COMPLETE; 2709 ts->stat = SAS_OPEN_REJECT; 2710 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2711 break; 2712 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2713 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2714 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2715 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2716 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2717 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2718 PM8001_FAIL_DBG(pm8001_ha, 2719 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2720 ts->resp = SAS_TASK_UNDELIVERED; 2721 ts->stat = SAS_DEV_NO_RESPONSE; 2722 if (!t->uldd_task) { 2723 pm8001_handle_event(pm8001_ha, 2724 pm8001_dev, 2725 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2726 ts->resp = SAS_TASK_COMPLETE; 2727 ts->stat = SAS_QUEUE_FULL; 2728 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2729 return; 2730 } 2731 break; 2732 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2733 PM8001_IO_DBG(pm8001_ha, 2734 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2735 ts->resp = SAS_TASK_UNDELIVERED; 2736 ts->stat = SAS_OPEN_REJECT; 2737 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2738 break; 2739 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2740 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2741 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2742 ts->resp = SAS_TASK_COMPLETE; 2743 ts->stat = SAS_OPEN_REJECT; 2744 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2745 break; 2746 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2747 PM8001_IO_DBG(pm8001_ha, 2748 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2749 ts->resp = SAS_TASK_COMPLETE; 2750 ts->stat = SAS_OPEN_REJECT; 2751 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2752 break; 2753 case IO_XFER_ERROR_NAK_RECEIVED: 2754 PM8001_IO_DBG(pm8001_ha, 2755 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2756 ts->resp = SAS_TASK_COMPLETE; 2757 ts->stat = SAS_NAK_R_ERR; 2758 break; 2759 case IO_XFER_ERROR_PEER_ABORTED: 2760 PM8001_IO_DBG(pm8001_ha, 2761 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); 2762 ts->resp = SAS_TASK_COMPLETE; 2763 ts->stat = SAS_NAK_R_ERR; 2764 break; 2765 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2766 PM8001_IO_DBG(pm8001_ha, 2767 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2768 ts->resp = SAS_TASK_COMPLETE; 2769 ts->stat = SAS_DATA_UNDERRUN; 2770 break; 2771 case IO_XFER_OPEN_RETRY_TIMEOUT: 2772 PM8001_IO_DBG(pm8001_ha, 2773 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2774 ts->resp = SAS_TASK_COMPLETE; 2775 ts->stat = SAS_OPEN_TO; 2776 break; 2777 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2778 PM8001_IO_DBG(pm8001_ha, 2779 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2780 ts->resp = SAS_TASK_COMPLETE; 2781 ts->stat = SAS_OPEN_TO; 2782 break; 2783 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2784 PM8001_IO_DBG(pm8001_ha, 2785 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2786 ts->resp = SAS_TASK_COMPLETE; 2787 ts->stat = SAS_OPEN_TO; 2788 break; 2789 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2790 PM8001_IO_DBG(pm8001_ha, 2791 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2792 ts->resp = SAS_TASK_COMPLETE; 2793 ts->stat = SAS_OPEN_TO; 2794 break; 2795 case IO_XFER_ERROR_OFFSET_MISMATCH: 2796 PM8001_IO_DBG(pm8001_ha, 2797 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2798 ts->resp = SAS_TASK_COMPLETE; 2799 ts->stat = SAS_OPEN_TO; 2800 break; 2801 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2802 PM8001_IO_DBG(pm8001_ha, 2803 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2804 ts->resp = SAS_TASK_COMPLETE; 2805 ts->stat = SAS_OPEN_TO; 2806 break; 2807 case IO_XFER_CMD_FRAME_ISSUED: 2808 PM8001_IO_DBG(pm8001_ha, 2809 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 2810 break; 2811 case IO_XFER_PIO_SETUP_ERROR: 2812 PM8001_IO_DBG(pm8001_ha, 2813 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); 2814 ts->resp = SAS_TASK_COMPLETE; 2815 ts->stat = SAS_OPEN_TO; 2816 break; 2817 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2818 PM8001_FAIL_DBG(pm8001_ha, 2819 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n")); 2820 /* TBC: used default set values */ 2821 ts->resp = SAS_TASK_COMPLETE; 2822 ts->stat = SAS_OPEN_TO; 2823 break; 2824 case IO_XFER_DMA_ACTIVATE_TIMEOUT: 2825 PM8001_FAIL_DBG(pm8001_ha, 2826 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n")); 2827 /* TBC: used default set values */ 2828 ts->resp = SAS_TASK_COMPLETE; 2829 ts->stat = SAS_OPEN_TO; 2830 break; 2831 default: 2832 PM8001_IO_DBG(pm8001_ha, 2833 pm8001_printk("Unknown status 0x%x\n", event)); 2834 /* not allowed case. Therefore, return failed status */ 2835 ts->resp = SAS_TASK_COMPLETE; 2836 ts->stat = SAS_OPEN_TO; 2837 break; 2838 } 2839 spin_lock_irqsave(&t->task_state_lock, flags); 2840 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2841 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2842 t->task_state_flags |= SAS_TASK_STATE_DONE; 2843 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2844 spin_unlock_irqrestore(&t->task_state_lock, flags); 2845 PM8001_FAIL_DBG(pm8001_ha, 2846 pm8001_printk("task 0x%p done with io_status 0x%x" 2847 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2848 t, event, ts->resp, ts->stat)); 2849 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2850 } else { 2851 spin_unlock_irqrestore(&t->task_state_lock, flags); 2852 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2853 } 2854 } 2855 2856 /*See the comments for mpi_ssp_completion */ 2857 static void 2858 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2859 { 2860 u32 param, i; 2861 struct sas_task *t; 2862 struct pm8001_ccb_info *ccb; 2863 unsigned long flags; 2864 u32 status; 2865 u32 tag; 2866 struct smp_completion_resp *psmpPayload; 2867 struct task_status_struct *ts; 2868 struct pm8001_device *pm8001_dev; 2869 char *pdma_respaddr = NULL; 2870 2871 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2872 status = le32_to_cpu(psmpPayload->status); 2873 tag = le32_to_cpu(psmpPayload->tag); 2874 2875 ccb = &pm8001_ha->ccb_info[tag]; 2876 param = le32_to_cpu(psmpPayload->param); 2877 t = ccb->task; 2878 ts = &t->task_status; 2879 pm8001_dev = ccb->device; 2880 if (status) 2881 PM8001_FAIL_DBG(pm8001_ha, 2882 pm8001_printk("smp IO status 0x%x\n", status)); 2883 if (unlikely(!t || !t->lldd_task || !t->dev)) 2884 return; 2885 2886 PM8001_DEV_DBG(pm8001_ha, 2887 pm8001_printk("tag::0x%x status::0x%x\n", tag, status)); 2888 2889 switch (status) { 2890 2891 case IO_SUCCESS: 2892 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2893 ts->resp = SAS_TASK_COMPLETE; 2894 ts->stat = SAM_STAT_GOOD; 2895 if (pm8001_dev) 2896 pm8001_dev->running_req--; 2897 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 2898 PM8001_IO_DBG(pm8001_ha, 2899 pm8001_printk("DIRECT RESPONSE Length:%d\n", 2900 param)); 2901 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64 2902 ((u64)sg_dma_address 2903 (&t->smp_task.smp_resp)))); 2904 for (i = 0; i < param; i++) { 2905 *(pdma_respaddr+i) = psmpPayload->_r_a[i]; 2906 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2907 "SMP Byte%d DMA data 0x%x psmp 0x%x\n", 2908 i, *(pdma_respaddr+i), 2909 psmpPayload->_r_a[i])); 2910 } 2911 } 2912 break; 2913 case IO_ABORTED: 2914 PM8001_IO_DBG(pm8001_ha, 2915 pm8001_printk("IO_ABORTED IOMB\n")); 2916 ts->resp = SAS_TASK_COMPLETE; 2917 ts->stat = SAS_ABORTED_TASK; 2918 if (pm8001_dev) 2919 pm8001_dev->running_req--; 2920 break; 2921 case IO_OVERFLOW: 2922 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2923 ts->resp = SAS_TASK_COMPLETE; 2924 ts->stat = SAS_DATA_OVERRUN; 2925 ts->residual = 0; 2926 if (pm8001_dev) 2927 pm8001_dev->running_req--; 2928 break; 2929 case IO_NO_DEVICE: 2930 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); 2931 ts->resp = SAS_TASK_COMPLETE; 2932 ts->stat = SAS_PHY_DOWN; 2933 break; 2934 case IO_ERROR_HW_TIMEOUT: 2935 PM8001_IO_DBG(pm8001_ha, 2936 pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); 2937 ts->resp = SAS_TASK_COMPLETE; 2938 ts->stat = SAM_STAT_BUSY; 2939 break; 2940 case IO_XFER_ERROR_BREAK: 2941 PM8001_IO_DBG(pm8001_ha, 2942 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2943 ts->resp = SAS_TASK_COMPLETE; 2944 ts->stat = SAM_STAT_BUSY; 2945 break; 2946 case IO_XFER_ERROR_PHY_NOT_READY: 2947 PM8001_IO_DBG(pm8001_ha, 2948 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2949 ts->resp = SAS_TASK_COMPLETE; 2950 ts->stat = SAM_STAT_BUSY; 2951 break; 2952 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2953 PM8001_IO_DBG(pm8001_ha, 2954 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2955 ts->resp = SAS_TASK_COMPLETE; 2956 ts->stat = SAS_OPEN_REJECT; 2957 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2958 break; 2959 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2960 PM8001_IO_DBG(pm8001_ha, 2961 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2962 ts->resp = SAS_TASK_COMPLETE; 2963 ts->stat = SAS_OPEN_REJECT; 2964 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2965 break; 2966 case IO_OPEN_CNX_ERROR_BREAK: 2967 PM8001_IO_DBG(pm8001_ha, 2968 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2969 ts->resp = SAS_TASK_COMPLETE; 2970 ts->stat = SAS_OPEN_REJECT; 2971 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2972 break; 2973 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2974 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2975 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2976 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2977 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2978 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2979 PM8001_IO_DBG(pm8001_ha, 2980 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2981 ts->resp = SAS_TASK_COMPLETE; 2982 ts->stat = SAS_OPEN_REJECT; 2983 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2984 pm8001_handle_event(pm8001_ha, 2985 pm8001_dev, 2986 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2987 break; 2988 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2989 PM8001_IO_DBG(pm8001_ha, 2990 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2991 ts->resp = SAS_TASK_COMPLETE; 2992 ts->stat = SAS_OPEN_REJECT; 2993 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2994 break; 2995 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2996 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\ 2997 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2998 ts->resp = SAS_TASK_COMPLETE; 2999 ts->stat = SAS_OPEN_REJECT; 3000 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 3001 break; 3002 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3003 PM8001_IO_DBG(pm8001_ha, 3004 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 3005 ts->resp = SAS_TASK_COMPLETE; 3006 ts->stat = SAS_OPEN_REJECT; 3007 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 3008 break; 3009 case IO_XFER_ERROR_RX_FRAME: 3010 PM8001_IO_DBG(pm8001_ha, 3011 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); 3012 ts->resp = SAS_TASK_COMPLETE; 3013 ts->stat = SAS_DEV_NO_RESPONSE; 3014 break; 3015 case IO_XFER_OPEN_RETRY_TIMEOUT: 3016 PM8001_IO_DBG(pm8001_ha, 3017 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 3018 ts->resp = SAS_TASK_COMPLETE; 3019 ts->stat = SAS_OPEN_REJECT; 3020 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3021 break; 3022 case IO_ERROR_INTERNAL_SMP_RESOURCE: 3023 PM8001_IO_DBG(pm8001_ha, 3024 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); 3025 ts->resp = SAS_TASK_COMPLETE; 3026 ts->stat = SAS_QUEUE_FULL; 3027 break; 3028 case IO_PORT_IN_RESET: 3029 PM8001_IO_DBG(pm8001_ha, 3030 pm8001_printk("IO_PORT_IN_RESET\n")); 3031 ts->resp = SAS_TASK_COMPLETE; 3032 ts->stat = SAS_OPEN_REJECT; 3033 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3034 break; 3035 case IO_DS_NON_OPERATIONAL: 3036 PM8001_IO_DBG(pm8001_ha, 3037 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 3038 ts->resp = SAS_TASK_COMPLETE; 3039 ts->stat = SAS_DEV_NO_RESPONSE; 3040 break; 3041 case IO_DS_IN_RECOVERY: 3042 PM8001_IO_DBG(pm8001_ha, 3043 pm8001_printk("IO_DS_IN_RECOVERY\n")); 3044 ts->resp = SAS_TASK_COMPLETE; 3045 ts->stat = SAS_OPEN_REJECT; 3046 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3047 break; 3048 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3049 PM8001_IO_DBG(pm8001_ha, 3050 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 3051 ts->resp = SAS_TASK_COMPLETE; 3052 ts->stat = SAS_OPEN_REJECT; 3053 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3054 break; 3055 default: 3056 PM8001_DEVIO_DBG(pm8001_ha, 3057 pm8001_printk("Unknown status 0x%x\n", status)); 3058 ts->resp = SAS_TASK_COMPLETE; 3059 ts->stat = SAS_DEV_NO_RESPONSE; 3060 /* not allowed case. Therefore, return failed status */ 3061 break; 3062 } 3063 spin_lock_irqsave(&t->task_state_lock, flags); 3064 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3065 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3066 t->task_state_flags |= SAS_TASK_STATE_DONE; 3067 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3068 spin_unlock_irqrestore(&t->task_state_lock, flags); 3069 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 3070 "task 0x%p done with io_status 0x%x resp 0x%x" 3071 "stat 0x%x but aborted by upper layer!\n", 3072 t, status, ts->resp, ts->stat)); 3073 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3074 } else { 3075 spin_unlock_irqrestore(&t->task_state_lock, flags); 3076 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3077 mb();/* in order to force CPU ordering */ 3078 t->task_done(t); 3079 } 3080 } 3081 3082 /** 3083 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3084 * @pm8001_ha: our hba card information 3085 * @Qnum: the outbound queue message number. 3086 * @SEA: source of event to ack 3087 * @port_id: port id. 3088 * @phyId: phy id. 3089 * @param0: parameter 0. 3090 * @param1: parameter 1. 3091 */ 3092 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3093 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3094 { 3095 struct hw_event_ack_req payload; 3096 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3097 3098 struct inbound_queue_table *circularQ; 3099 3100 memset((u8 *)&payload, 0, sizeof(payload)); 3101 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 3102 payload.tag = cpu_to_le32(1); 3103 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3104 ((phyId & 0xFF) << 24) | (port_id & 0xFF)); 3105 payload.param0 = cpu_to_le32(param0); 3106 payload.param1 = cpu_to_le32(param1); 3107 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 3108 sizeof(payload), 0); 3109 } 3110 3111 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3112 u32 phyId, u32 phy_op); 3113 3114 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha, 3115 void *piomb) 3116 { 3117 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4); 3118 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3119 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3120 u32 lr_status_evt_portid = 3121 le32_to_cpu(pPayload->lr_status_evt_portid); 3122 u8 deviceType = pPayload->sas_identify.dev_type; 3123 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3124 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3125 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3126 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3127 3128 if (deviceType == SAS_END_DEVICE) { 3129 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3130 PHY_NOTIFY_ENABLE_SPINUP); 3131 } 3132 3133 port->wide_port_phymap |= (1U << phy_id); 3134 pm8001_get_lrate_mode(phy, link_rate); 3135 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3136 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3137 phy->phy_attached = 1; 3138 } 3139 3140 /** 3141 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3142 * @pm8001_ha: our hba card information 3143 * @piomb: IO message buffer 3144 */ 3145 static void 3146 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3147 { 3148 struct hw_event_resp *pPayload = 3149 (struct hw_event_resp *)(piomb + 4); 3150 u32 lr_status_evt_portid = 3151 le32_to_cpu(pPayload->lr_status_evt_portid); 3152 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3153 3154 u8 link_rate = 3155 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3156 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3157 u8 phy_id = 3158 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3159 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3160 3161 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3162 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3163 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3164 unsigned long flags; 3165 u8 deviceType = pPayload->sas_identify.dev_type; 3166 port->port_state = portstate; 3167 port->wide_port_phymap |= (1U << phy_id); 3168 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3169 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3170 "portid:%d; phyid:%d; linkrate:%d; " 3171 "portstate:%x; devicetype:%x\n", 3172 port_id, phy_id, link_rate, portstate, deviceType)); 3173 3174 switch (deviceType) { 3175 case SAS_PHY_UNUSED: 3176 PM8001_MSG_DBG(pm8001_ha, 3177 pm8001_printk("device type no device.\n")); 3178 break; 3179 case SAS_END_DEVICE: 3180 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); 3181 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3182 PHY_NOTIFY_ENABLE_SPINUP); 3183 port->port_attached = 1; 3184 pm8001_get_lrate_mode(phy, link_rate); 3185 break; 3186 case SAS_EDGE_EXPANDER_DEVICE: 3187 PM8001_MSG_DBG(pm8001_ha, 3188 pm8001_printk("expander device.\n")); 3189 port->port_attached = 1; 3190 pm8001_get_lrate_mode(phy, link_rate); 3191 break; 3192 case SAS_FANOUT_EXPANDER_DEVICE: 3193 PM8001_MSG_DBG(pm8001_ha, 3194 pm8001_printk("fanout expander device.\n")); 3195 port->port_attached = 1; 3196 pm8001_get_lrate_mode(phy, link_rate); 3197 break; 3198 default: 3199 PM8001_DEVIO_DBG(pm8001_ha, 3200 pm8001_printk("unknown device type(%x)\n", deviceType)); 3201 break; 3202 } 3203 phy->phy_type |= PORT_TYPE_SAS; 3204 phy->identify.device_type = deviceType; 3205 phy->phy_attached = 1; 3206 if (phy->identify.device_type == SAS_END_DEVICE) 3207 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3208 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3209 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3210 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3211 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3212 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3213 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3214 sizeof(struct sas_identify_frame)-4); 3215 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3216 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3217 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3218 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3219 msleep(200);/*delay a moment to wait disk to spinup*/ 3220 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3221 } 3222 3223 /** 3224 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3225 * @pm8001_ha: our hba card information 3226 * @piomb: IO message buffer 3227 */ 3228 static void 3229 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3230 { 3231 struct hw_event_resp *pPayload = 3232 (struct hw_event_resp *)(piomb + 4); 3233 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3234 u32 lr_status_evt_portid = 3235 le32_to_cpu(pPayload->lr_status_evt_portid); 3236 u8 link_rate = 3237 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3238 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3239 u8 phy_id = 3240 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3241 3242 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3243 3244 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3245 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3246 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3247 unsigned long flags; 3248 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 3249 "port id %d, phy id %d link_rate %d portstate 0x%x\n", 3250 port_id, phy_id, link_rate, portstate)); 3251 3252 port->port_state = portstate; 3253 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3254 port->port_attached = 1; 3255 pm8001_get_lrate_mode(phy, link_rate); 3256 phy->phy_type |= PORT_TYPE_SATA; 3257 phy->phy_attached = 1; 3258 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3259 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3260 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3261 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3262 sizeof(struct dev_to_host_fis)); 3263 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3264 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3265 phy->identify.device_type = SAS_SATA_DEV; 3266 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3267 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3268 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3269 } 3270 3271 /** 3272 * hw_event_phy_down -we should notify the libsas the phy is down. 3273 * @pm8001_ha: our hba card information 3274 * @piomb: IO message buffer 3275 */ 3276 static void 3277 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3278 { 3279 struct hw_event_resp *pPayload = 3280 (struct hw_event_resp *)(piomb + 4); 3281 3282 u32 lr_status_evt_portid = 3283 le32_to_cpu(pPayload->lr_status_evt_portid); 3284 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3285 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3286 u8 phy_id = 3287 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3288 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3289 3290 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3291 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3292 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA); 3293 port->port_state = portstate; 3294 phy->identify.device_type = 0; 3295 phy->phy_attached = 0; 3296 switch (portstate) { 3297 case PORT_VALID: 3298 break; 3299 case PORT_INVALID: 3300 PM8001_MSG_DBG(pm8001_ha, 3301 pm8001_printk(" PortInvalid portID %d\n", port_id)); 3302 PM8001_MSG_DBG(pm8001_ha, 3303 pm8001_printk(" Last phy Down and port invalid\n")); 3304 if (port_sata) { 3305 phy->phy_type = 0; 3306 port->port_attached = 0; 3307 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3308 port_id, phy_id, 0, 0); 3309 } 3310 sas_phy_disconnected(&phy->sas_phy); 3311 break; 3312 case PORT_IN_RESET: 3313 PM8001_MSG_DBG(pm8001_ha, 3314 pm8001_printk(" Port In Reset portID %d\n", port_id)); 3315 break; 3316 case PORT_NOT_ESTABLISHED: 3317 PM8001_MSG_DBG(pm8001_ha, 3318 pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n")); 3319 port->port_attached = 0; 3320 break; 3321 case PORT_LOSTCOMM: 3322 PM8001_MSG_DBG(pm8001_ha, 3323 pm8001_printk(" Phy Down and PORT_LOSTCOMM\n")); 3324 PM8001_MSG_DBG(pm8001_ha, 3325 pm8001_printk(" Last phy Down and port invalid\n")); 3326 if (port_sata) { 3327 port->port_attached = 0; 3328 phy->phy_type = 0; 3329 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3330 port_id, phy_id, 0, 0); 3331 } 3332 sas_phy_disconnected(&phy->sas_phy); 3333 break; 3334 default: 3335 port->port_attached = 0; 3336 PM8001_DEVIO_DBG(pm8001_ha, 3337 pm8001_printk(" Phy Down and(default) = 0x%x\n", 3338 portstate)); 3339 break; 3340 3341 } 3342 if (port_sata && (portstate != PORT_IN_RESET)) { 3343 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3344 3345 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); 3346 } 3347 } 3348 3349 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3350 { 3351 struct phy_start_resp *pPayload = 3352 (struct phy_start_resp *)(piomb + 4); 3353 u32 status = 3354 le32_to_cpu(pPayload->status); 3355 u32 phy_id = 3356 le32_to_cpu(pPayload->phyid); 3357 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3358 3359 PM8001_INIT_DBG(pm8001_ha, 3360 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n", 3361 status, phy_id)); 3362 if (status == 0) { 3363 phy->phy_state = PHY_LINK_DOWN; 3364 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3365 phy->enable_completion != NULL) { 3366 complete(phy->enable_completion); 3367 phy->enable_completion = NULL; 3368 } 3369 } 3370 return 0; 3371 3372 } 3373 3374 /** 3375 * mpi_thermal_hw_event -The hw event has come. 3376 * @pm8001_ha: our hba card information 3377 * @piomb: IO message buffer 3378 */ 3379 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3380 { 3381 struct thermal_hw_event *pPayload = 3382 (struct thermal_hw_event *)(piomb + 4); 3383 3384 u32 thermal_event = le32_to_cpu(pPayload->thermal_event); 3385 u32 rht_lht = le32_to_cpu(pPayload->rht_lht); 3386 3387 if (thermal_event & 0x40) { 3388 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3389 "Thermal Event: Local high temperature violated!\n")); 3390 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3391 "Thermal Event: Measured local high temperature %d\n", 3392 ((rht_lht & 0xFF00) >> 8))); 3393 } 3394 if (thermal_event & 0x10) { 3395 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3396 "Thermal Event: Remote high temperature violated!\n")); 3397 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3398 "Thermal Event: Measured remote high temperature %d\n", 3399 ((rht_lht & 0xFF000000) >> 24))); 3400 } 3401 return 0; 3402 } 3403 3404 /** 3405 * mpi_hw_event -The hw event has come. 3406 * @pm8001_ha: our hba card information 3407 * @piomb: IO message buffer 3408 */ 3409 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3410 { 3411 unsigned long flags, i; 3412 struct hw_event_resp *pPayload = 3413 (struct hw_event_resp *)(piomb + 4); 3414 u32 lr_status_evt_portid = 3415 le32_to_cpu(pPayload->lr_status_evt_portid); 3416 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3417 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3418 u8 phy_id = 3419 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3420 u16 eventType = 3421 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); 3422 u8 status = 3423 (u8)((lr_status_evt_portid & 0x0F000000) >> 24); 3424 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3425 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3426 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3427 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3428 PM8001_DEV_DBG(pm8001_ha, 3429 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n", 3430 port_id, phy_id, eventType, status)); 3431 3432 switch (eventType) { 3433 3434 case HW_EVENT_SAS_PHY_UP: 3435 PM8001_MSG_DBG(pm8001_ha, 3436 pm8001_printk("HW_EVENT_PHY_START_STATUS\n")); 3437 hw_event_sas_phy_up(pm8001_ha, piomb); 3438 break; 3439 case HW_EVENT_SATA_PHY_UP: 3440 PM8001_MSG_DBG(pm8001_ha, 3441 pm8001_printk("HW_EVENT_SATA_PHY_UP\n")); 3442 hw_event_sata_phy_up(pm8001_ha, piomb); 3443 break; 3444 case HW_EVENT_SATA_SPINUP_HOLD: 3445 PM8001_MSG_DBG(pm8001_ha, 3446 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n")); 3447 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 3448 break; 3449 case HW_EVENT_PHY_DOWN: 3450 PM8001_MSG_DBG(pm8001_ha, 3451 pm8001_printk("HW_EVENT_PHY_DOWN\n")); 3452 hw_event_phy_down(pm8001_ha, piomb); 3453 if (pm8001_ha->reset_in_progress) { 3454 PM8001_MSG_DBG(pm8001_ha, 3455 pm8001_printk("Reset in progress\n")); 3456 return 0; 3457 } 3458 phy->phy_attached = 0; 3459 phy->phy_state = PHY_LINK_DISABLE; 3460 break; 3461 case HW_EVENT_PORT_INVALID: 3462 PM8001_MSG_DBG(pm8001_ha, 3463 pm8001_printk("HW_EVENT_PORT_INVALID\n")); 3464 sas_phy_disconnected(sas_phy); 3465 phy->phy_attached = 0; 3466 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3467 break; 3468 /* the broadcast change primitive received, tell the LIBSAS this event 3469 to revalidate the sas domain*/ 3470 case HW_EVENT_BROADCAST_CHANGE: 3471 PM8001_MSG_DBG(pm8001_ha, 3472 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); 3473 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3474 port_id, phy_id, 1, 0); 3475 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3476 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3477 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3478 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3479 break; 3480 case HW_EVENT_PHY_ERROR: 3481 PM8001_MSG_DBG(pm8001_ha, 3482 pm8001_printk("HW_EVENT_PHY_ERROR\n")); 3483 sas_phy_disconnected(&phy->sas_phy); 3484 phy->phy_attached = 0; 3485 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 3486 break; 3487 case HW_EVENT_BROADCAST_EXP: 3488 PM8001_MSG_DBG(pm8001_ha, 3489 pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); 3490 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3491 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3492 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3493 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3494 break; 3495 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3496 PM8001_MSG_DBG(pm8001_ha, 3497 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); 3498 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3499 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3500 break; 3501 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3502 PM8001_MSG_DBG(pm8001_ha, 3503 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); 3504 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3505 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3506 port_id, phy_id, 0, 0); 3507 break; 3508 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3509 PM8001_MSG_DBG(pm8001_ha, 3510 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); 3511 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3512 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3513 port_id, phy_id, 0, 0); 3514 break; 3515 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3516 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3517 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); 3518 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3519 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3520 port_id, phy_id, 0, 0); 3521 break; 3522 case HW_EVENT_MALFUNCTION: 3523 PM8001_MSG_DBG(pm8001_ha, 3524 pm8001_printk("HW_EVENT_MALFUNCTION\n")); 3525 break; 3526 case HW_EVENT_BROADCAST_SES: 3527 PM8001_MSG_DBG(pm8001_ha, 3528 pm8001_printk("HW_EVENT_BROADCAST_SES\n")); 3529 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3530 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3531 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3532 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3533 break; 3534 case HW_EVENT_INBOUND_CRC_ERROR: 3535 PM8001_MSG_DBG(pm8001_ha, 3536 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); 3537 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3538 HW_EVENT_INBOUND_CRC_ERROR, 3539 port_id, phy_id, 0, 0); 3540 break; 3541 case HW_EVENT_HARD_RESET_RECEIVED: 3542 PM8001_MSG_DBG(pm8001_ha, 3543 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); 3544 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3545 break; 3546 case HW_EVENT_ID_FRAME_TIMEOUT: 3547 PM8001_MSG_DBG(pm8001_ha, 3548 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); 3549 sas_phy_disconnected(sas_phy); 3550 phy->phy_attached = 0; 3551 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3552 break; 3553 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3554 PM8001_MSG_DBG(pm8001_ha, 3555 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n")); 3556 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3557 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3558 port_id, phy_id, 0, 0); 3559 sas_phy_disconnected(sas_phy); 3560 phy->phy_attached = 0; 3561 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3562 break; 3563 case HW_EVENT_PORT_RESET_TIMER_TMO: 3564 PM8001_MSG_DBG(pm8001_ha, 3565 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n")); 3566 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3567 port_id, phy_id, 0, 0); 3568 sas_phy_disconnected(sas_phy); 3569 phy->phy_attached = 0; 3570 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3571 if (pm8001_ha->phy[phy_id].reset_completion) { 3572 pm8001_ha->phy[phy_id].port_reset_status = 3573 PORT_RESET_TMO; 3574 complete(pm8001_ha->phy[phy_id].reset_completion); 3575 pm8001_ha->phy[phy_id].reset_completion = NULL; 3576 } 3577 break; 3578 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3579 PM8001_MSG_DBG(pm8001_ha, 3580 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n")); 3581 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3582 HW_EVENT_PORT_RECOVERY_TIMER_TMO, 3583 port_id, phy_id, 0, 0); 3584 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 3585 if (port->wide_port_phymap & (1 << i)) { 3586 phy = &pm8001_ha->phy[i]; 3587 sas_ha->notify_phy_event(&phy->sas_phy, 3588 PHYE_LOSS_OF_SIGNAL); 3589 port->wide_port_phymap &= ~(1 << i); 3590 } 3591 } 3592 break; 3593 case HW_EVENT_PORT_RECOVER: 3594 PM8001_MSG_DBG(pm8001_ha, 3595 pm8001_printk("HW_EVENT_PORT_RECOVER\n")); 3596 hw_event_port_recover(pm8001_ha, piomb); 3597 break; 3598 case HW_EVENT_PORT_RESET_COMPLETE: 3599 PM8001_MSG_DBG(pm8001_ha, 3600 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n")); 3601 if (pm8001_ha->phy[phy_id].reset_completion) { 3602 pm8001_ha->phy[phy_id].port_reset_status = 3603 PORT_RESET_SUCCESS; 3604 complete(pm8001_ha->phy[phy_id].reset_completion); 3605 pm8001_ha->phy[phy_id].reset_completion = NULL; 3606 } 3607 break; 3608 case EVENT_BROADCAST_ASYNCH_EVENT: 3609 PM8001_MSG_DBG(pm8001_ha, 3610 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); 3611 break; 3612 default: 3613 PM8001_DEVIO_DBG(pm8001_ha, 3614 pm8001_printk("Unknown event type 0x%x\n", eventType)); 3615 break; 3616 } 3617 return 0; 3618 } 3619 3620 /** 3621 * mpi_phy_stop_resp - SPCv specific 3622 * @pm8001_ha: our hba card information 3623 * @piomb: IO message buffer 3624 */ 3625 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3626 { 3627 struct phy_stop_resp *pPayload = 3628 (struct phy_stop_resp *)(piomb + 4); 3629 u32 status = 3630 le32_to_cpu(pPayload->status); 3631 u32 phyid = 3632 le32_to_cpu(pPayload->phyid) & 0xFF; 3633 struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; 3634 PM8001_MSG_DBG(pm8001_ha, 3635 pm8001_printk("phy:0x%x status:0x%x\n", 3636 phyid, status)); 3637 if (status == PHY_STOP_SUCCESS || 3638 status == PHY_STOP_ERR_DEVICE_ATTACHED) 3639 phy->phy_state = PHY_LINK_DISABLE; 3640 return 0; 3641 } 3642 3643 /** 3644 * mpi_set_controller_config_resp - SPCv specific 3645 * @pm8001_ha: our hba card information 3646 * @piomb: IO message buffer 3647 */ 3648 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3649 void *piomb) 3650 { 3651 struct set_ctrl_cfg_resp *pPayload = 3652 (struct set_ctrl_cfg_resp *)(piomb + 4); 3653 u32 status = le32_to_cpu(pPayload->status); 3654 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); 3655 3656 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3657 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", 3658 status, err_qlfr_pgcd)); 3659 3660 return 0; 3661 } 3662 3663 /** 3664 * mpi_get_controller_config_resp - SPCv specific 3665 * @pm8001_ha: our hba card information 3666 * @piomb: IO message buffer 3667 */ 3668 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3669 void *piomb) 3670 { 3671 PM8001_MSG_DBG(pm8001_ha, 3672 pm8001_printk(" pm80xx_addition_functionality\n")); 3673 3674 return 0; 3675 } 3676 3677 /** 3678 * mpi_get_phy_profile_resp - SPCv specific 3679 * @pm8001_ha: our hba card information 3680 * @piomb: IO message buffer 3681 */ 3682 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3683 void *piomb) 3684 { 3685 PM8001_MSG_DBG(pm8001_ha, 3686 pm8001_printk(" pm80xx_addition_functionality\n")); 3687 3688 return 0; 3689 } 3690 3691 /** 3692 * mpi_flash_op_ext_resp - SPCv specific 3693 * @pm8001_ha: our hba card information 3694 * @piomb: IO message buffer 3695 */ 3696 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3697 { 3698 PM8001_MSG_DBG(pm8001_ha, 3699 pm8001_printk(" pm80xx_addition_functionality\n")); 3700 3701 return 0; 3702 } 3703 3704 /** 3705 * mpi_set_phy_profile_resp - SPCv specific 3706 * @pm8001_ha: our hba card information 3707 * @piomb: IO message buffer 3708 */ 3709 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3710 void *piomb) 3711 { 3712 u8 page_code; 3713 struct set_phy_profile_resp *pPayload = 3714 (struct set_phy_profile_resp *)(piomb + 4); 3715 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); 3716 u32 status = le32_to_cpu(pPayload->status); 3717 3718 page_code = (u8)((ppc_phyid & 0xFF00) >> 8); 3719 if (status) { 3720 /* status is FAILED */ 3721 PM8001_FAIL_DBG(pm8001_ha, 3722 pm8001_printk("PhyProfile command failed with status " 3723 "0x%08X \n", status)); 3724 return -1; 3725 } else { 3726 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) { 3727 PM8001_FAIL_DBG(pm8001_ha, 3728 pm8001_printk("Invalid page code 0x%X\n", 3729 page_code)); 3730 return -1; 3731 } 3732 } 3733 return 0; 3734 } 3735 3736 /** 3737 * mpi_kek_management_resp - SPCv specific 3738 * @pm8001_ha: our hba card information 3739 * @piomb: IO message buffer 3740 */ 3741 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, 3742 void *piomb) 3743 { 3744 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); 3745 3746 u32 status = le32_to_cpu(pPayload->status); 3747 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); 3748 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); 3749 3750 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3751 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", 3752 status, kidx_new_curr_ksop, err_qlfr)); 3753 3754 return 0; 3755 } 3756 3757 /** 3758 * mpi_dek_management_resp - SPCv specific 3759 * @pm8001_ha: our hba card information 3760 * @piomb: IO message buffer 3761 */ 3762 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, 3763 void *piomb) 3764 { 3765 PM8001_MSG_DBG(pm8001_ha, 3766 pm8001_printk(" pm80xx_addition_functionality\n")); 3767 3768 return 0; 3769 } 3770 3771 /** 3772 * ssp_coalesced_comp_resp - SPCv specific 3773 * @pm8001_ha: our hba card information 3774 * @piomb: IO message buffer 3775 */ 3776 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, 3777 void *piomb) 3778 { 3779 PM8001_MSG_DBG(pm8001_ha, 3780 pm8001_printk(" pm80xx_addition_functionality\n")); 3781 3782 return 0; 3783 } 3784 3785 /** 3786 * process_one_iomb - process one outbound Queue memory block 3787 * @pm8001_ha: our hba card information 3788 * @piomb: IO message buffer 3789 */ 3790 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3791 { 3792 __le32 pHeader = *(__le32 *)piomb; 3793 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); 3794 3795 switch (opc) { 3796 case OPC_OUB_ECHO: 3797 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n")); 3798 break; 3799 case OPC_OUB_HW_EVENT: 3800 PM8001_MSG_DBG(pm8001_ha, 3801 pm8001_printk("OPC_OUB_HW_EVENT\n")); 3802 mpi_hw_event(pm8001_ha, piomb); 3803 break; 3804 case OPC_OUB_THERM_HW_EVENT: 3805 PM8001_MSG_DBG(pm8001_ha, 3806 pm8001_printk("OPC_OUB_THERMAL_EVENT\n")); 3807 mpi_thermal_hw_event(pm8001_ha, piomb); 3808 break; 3809 case OPC_OUB_SSP_COMP: 3810 PM8001_MSG_DBG(pm8001_ha, 3811 pm8001_printk("OPC_OUB_SSP_COMP\n")); 3812 mpi_ssp_completion(pm8001_ha, piomb); 3813 break; 3814 case OPC_OUB_SMP_COMP: 3815 PM8001_MSG_DBG(pm8001_ha, 3816 pm8001_printk("OPC_OUB_SMP_COMP\n")); 3817 mpi_smp_completion(pm8001_ha, piomb); 3818 break; 3819 case OPC_OUB_LOCAL_PHY_CNTRL: 3820 PM8001_MSG_DBG(pm8001_ha, 3821 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); 3822 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3823 break; 3824 case OPC_OUB_DEV_REGIST: 3825 PM8001_MSG_DBG(pm8001_ha, 3826 pm8001_printk("OPC_OUB_DEV_REGIST\n")); 3827 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3828 break; 3829 case OPC_OUB_DEREG_DEV: 3830 PM8001_MSG_DBG(pm8001_ha, 3831 pm8001_printk("unregister the device\n")); 3832 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3833 break; 3834 case OPC_OUB_GET_DEV_HANDLE: 3835 PM8001_MSG_DBG(pm8001_ha, 3836 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n")); 3837 break; 3838 case OPC_OUB_SATA_COMP: 3839 PM8001_MSG_DBG(pm8001_ha, 3840 pm8001_printk("OPC_OUB_SATA_COMP\n")); 3841 mpi_sata_completion(pm8001_ha, piomb); 3842 break; 3843 case OPC_OUB_SATA_EVENT: 3844 PM8001_MSG_DBG(pm8001_ha, 3845 pm8001_printk("OPC_OUB_SATA_EVENT\n")); 3846 mpi_sata_event(pm8001_ha, piomb); 3847 break; 3848 case OPC_OUB_SSP_EVENT: 3849 PM8001_MSG_DBG(pm8001_ha, 3850 pm8001_printk("OPC_OUB_SSP_EVENT\n")); 3851 mpi_ssp_event(pm8001_ha, piomb); 3852 break; 3853 case OPC_OUB_DEV_HANDLE_ARRIV: 3854 PM8001_MSG_DBG(pm8001_ha, 3855 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); 3856 /*This is for target*/ 3857 break; 3858 case OPC_OUB_SSP_RECV_EVENT: 3859 PM8001_MSG_DBG(pm8001_ha, 3860 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); 3861 /*This is for target*/ 3862 break; 3863 case OPC_OUB_FW_FLASH_UPDATE: 3864 PM8001_MSG_DBG(pm8001_ha, 3865 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); 3866 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3867 break; 3868 case OPC_OUB_GPIO_RESPONSE: 3869 PM8001_MSG_DBG(pm8001_ha, 3870 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); 3871 break; 3872 case OPC_OUB_GPIO_EVENT: 3873 PM8001_MSG_DBG(pm8001_ha, 3874 pm8001_printk("OPC_OUB_GPIO_EVENT\n")); 3875 break; 3876 case OPC_OUB_GENERAL_EVENT: 3877 PM8001_MSG_DBG(pm8001_ha, 3878 pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); 3879 pm8001_mpi_general_event(pm8001_ha, piomb); 3880 break; 3881 case OPC_OUB_SSP_ABORT_RSP: 3882 PM8001_MSG_DBG(pm8001_ha, 3883 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); 3884 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3885 break; 3886 case OPC_OUB_SATA_ABORT_RSP: 3887 PM8001_MSG_DBG(pm8001_ha, 3888 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); 3889 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3890 break; 3891 case OPC_OUB_SAS_DIAG_MODE_START_END: 3892 PM8001_MSG_DBG(pm8001_ha, 3893 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); 3894 break; 3895 case OPC_OUB_SAS_DIAG_EXECUTE: 3896 PM8001_MSG_DBG(pm8001_ha, 3897 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); 3898 break; 3899 case OPC_OUB_GET_TIME_STAMP: 3900 PM8001_MSG_DBG(pm8001_ha, 3901 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); 3902 break; 3903 case OPC_OUB_SAS_HW_EVENT_ACK: 3904 PM8001_MSG_DBG(pm8001_ha, 3905 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); 3906 break; 3907 case OPC_OUB_PORT_CONTROL: 3908 PM8001_MSG_DBG(pm8001_ha, 3909 pm8001_printk("OPC_OUB_PORT_CONTROL\n")); 3910 break; 3911 case OPC_OUB_SMP_ABORT_RSP: 3912 PM8001_MSG_DBG(pm8001_ha, 3913 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); 3914 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3915 break; 3916 case OPC_OUB_GET_NVMD_DATA: 3917 PM8001_MSG_DBG(pm8001_ha, 3918 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); 3919 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 3920 break; 3921 case OPC_OUB_SET_NVMD_DATA: 3922 PM8001_MSG_DBG(pm8001_ha, 3923 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); 3924 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 3925 break; 3926 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3927 PM8001_MSG_DBG(pm8001_ha, 3928 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); 3929 break; 3930 case OPC_OUB_SET_DEVICE_STATE: 3931 PM8001_MSG_DBG(pm8001_ha, 3932 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); 3933 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 3934 break; 3935 case OPC_OUB_GET_DEVICE_STATE: 3936 PM8001_MSG_DBG(pm8001_ha, 3937 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); 3938 break; 3939 case OPC_OUB_SET_DEV_INFO: 3940 PM8001_MSG_DBG(pm8001_ha, 3941 pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); 3942 break; 3943 /* spcv specifc commands */ 3944 case OPC_OUB_PHY_START_RESP: 3945 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3946 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc)); 3947 mpi_phy_start_resp(pm8001_ha, piomb); 3948 break; 3949 case OPC_OUB_PHY_STOP_RESP: 3950 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3951 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc)); 3952 mpi_phy_stop_resp(pm8001_ha, piomb); 3953 break; 3954 case OPC_OUB_SET_CONTROLLER_CONFIG: 3955 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3956 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc)); 3957 mpi_set_controller_config_resp(pm8001_ha, piomb); 3958 break; 3959 case OPC_OUB_GET_CONTROLLER_CONFIG: 3960 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3961 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc)); 3962 mpi_get_controller_config_resp(pm8001_ha, piomb); 3963 break; 3964 case OPC_OUB_GET_PHY_PROFILE: 3965 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3966 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc)); 3967 mpi_get_phy_profile_resp(pm8001_ha, piomb); 3968 break; 3969 case OPC_OUB_FLASH_OP_EXT: 3970 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3971 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc)); 3972 mpi_flash_op_ext_resp(pm8001_ha, piomb); 3973 break; 3974 case OPC_OUB_SET_PHY_PROFILE: 3975 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3976 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc)); 3977 mpi_set_phy_profile_resp(pm8001_ha, piomb); 3978 break; 3979 case OPC_OUB_KEK_MANAGEMENT_RESP: 3980 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3981 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc)); 3982 mpi_kek_management_resp(pm8001_ha, piomb); 3983 break; 3984 case OPC_OUB_DEK_MANAGEMENT_RESP: 3985 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3986 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc)); 3987 mpi_dek_management_resp(pm8001_ha, piomb); 3988 break; 3989 case OPC_OUB_SSP_COALESCED_COMP_RESP: 3990 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3991 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc)); 3992 ssp_coalesced_comp_resp(pm8001_ha, piomb); 3993 break; 3994 default: 3995 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 3996 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc)); 3997 break; 3998 } 3999 } 4000 4001 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha) 4002 { 4003 PM8001_FAIL_DBG(pm8001_ha, 4004 pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n", 4005 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0))); 4006 PM8001_FAIL_DBG(pm8001_ha, 4007 pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n", 4008 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1))); 4009 PM8001_FAIL_DBG(pm8001_ha, 4010 pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n", 4011 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2))); 4012 PM8001_FAIL_DBG(pm8001_ha, 4013 pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n", 4014 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3))); 4015 PM8001_FAIL_DBG(pm8001_ha, 4016 pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n", 4017 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0))); 4018 PM8001_FAIL_DBG(pm8001_ha, 4019 pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n", 4020 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1))); 4021 PM8001_FAIL_DBG(pm8001_ha, 4022 pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n", 4023 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2))); 4024 PM8001_FAIL_DBG(pm8001_ha, 4025 pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n", 4026 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3))); 4027 PM8001_FAIL_DBG(pm8001_ha, 4028 pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n", 4029 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4))); 4030 PM8001_FAIL_DBG(pm8001_ha, 4031 pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n", 4032 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5))); 4033 PM8001_FAIL_DBG(pm8001_ha, 4034 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n", 4035 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6))); 4036 PM8001_FAIL_DBG(pm8001_ha, 4037 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n", 4038 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7))); 4039 } 4040 4041 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4042 { 4043 struct outbound_queue_table *circularQ; 4044 void *pMsg1 = NULL; 4045 u8 uninitialized_var(bc); 4046 u32 ret = MPI_IO_STATUS_FAIL; 4047 unsigned long flags; 4048 u32 regval; 4049 4050 if (vec == (pm8001_ha->number_of_intr - 1)) { 4051 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 4052 if ((regval & SCRATCH_PAD_MIPSALL_READY) != 4053 SCRATCH_PAD_MIPSALL_READY) { 4054 pm8001_ha->controller_fatal_error = true; 4055 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 4056 "Firmware Fatal error! Regval:0x%x\n", regval)); 4057 print_scratchpad_registers(pm8001_ha); 4058 return ret; 4059 } 4060 } 4061 spin_lock_irqsave(&pm8001_ha->lock, flags); 4062 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4063 do { 4064 /* spurious interrupt during setup if kexec-ing and 4065 * driver doing a doorbell access w/ the pre-kexec oq 4066 * interrupt setup. 4067 */ 4068 if (!circularQ->pi_virt) 4069 break; 4070 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4071 if (MPI_IO_STATUS_SUCCESS == ret) { 4072 /* process the outbound message */ 4073 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 4074 /* free the message from the outbound circular buffer */ 4075 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4076 circularQ, bc); 4077 } 4078 if (MPI_IO_STATUS_BUSY == ret) { 4079 /* Update the producer index from SPC */ 4080 circularQ->producer_index = 4081 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4082 if (le32_to_cpu(circularQ->producer_index) == 4083 circularQ->consumer_idx) 4084 /* OQ is empty */ 4085 break; 4086 } 4087 } while (1); 4088 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 4089 return ret; 4090 } 4091 4092 /* DMA_... to our direction translation. */ 4093 static const u8 data_dir_flags[] = { 4094 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4095 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4096 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4097 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4098 }; 4099 4100 static void build_smp_cmd(u32 deviceID, __le32 hTag, 4101 struct smp_req *psmp_cmd, int mode, int length) 4102 { 4103 psmp_cmd->tag = hTag; 4104 psmp_cmd->device_id = cpu_to_le32(deviceID); 4105 if (mode == SMP_DIRECT) { 4106 length = length - 4; /* subtract crc */ 4107 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); 4108 } else { 4109 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4110 } 4111 } 4112 4113 /** 4114 * pm8001_chip_smp_req - send a SMP task to FW 4115 * @pm8001_ha: our hba card information. 4116 * @ccb: the ccb information this request used. 4117 */ 4118 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4119 struct pm8001_ccb_info *ccb) 4120 { 4121 int elem, rc; 4122 struct sas_task *task = ccb->task; 4123 struct domain_device *dev = task->dev; 4124 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4125 struct scatterlist *sg_req, *sg_resp; 4126 u32 req_len, resp_len; 4127 struct smp_req smp_cmd; 4128 u32 opc; 4129 struct inbound_queue_table *circularQ; 4130 char *preq_dma_addr = NULL; 4131 __le64 tmp_addr; 4132 u32 i, length; 4133 4134 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4135 /* 4136 * DMA-map SMP request, response buffers 4137 */ 4138 sg_req = &task->smp_task.smp_req; 4139 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4140 if (!elem) 4141 return -ENOMEM; 4142 req_len = sg_dma_len(sg_req); 4143 4144 sg_resp = &task->smp_task.smp_resp; 4145 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4146 if (!elem) { 4147 rc = -ENOMEM; 4148 goto err_out; 4149 } 4150 resp_len = sg_dma_len(sg_resp); 4151 /* must be in dwords */ 4152 if ((req_len & 0x3) || (resp_len & 0x3)) { 4153 rc = -EINVAL; 4154 goto err_out_2; 4155 } 4156 4157 opc = OPC_INB_SMP_REQUEST; 4158 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4159 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4160 4161 length = sg_req->length; 4162 PM8001_IO_DBG(pm8001_ha, 4163 pm8001_printk("SMP Frame Length %d\n", sg_req->length)); 4164 if (!(length - 8)) 4165 pm8001_ha->smp_exp_mode = SMP_DIRECT; 4166 else 4167 pm8001_ha->smp_exp_mode = SMP_INDIRECT; 4168 4169 4170 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 4171 preq_dma_addr = (char *)phys_to_virt(tmp_addr); 4172 4173 /* INDIRECT MODE command settings. Use DMA */ 4174 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { 4175 PM8001_IO_DBG(pm8001_ha, 4176 pm8001_printk("SMP REQUEST INDIRECT MODE\n")); 4177 /* for SPCv indirect mode. Place the top 4 bytes of 4178 * SMP Request header here. */ 4179 for (i = 0; i < 4; i++) 4180 smp_cmd.smp_req16[i] = *(preq_dma_addr + i); 4181 /* exclude top 4 bytes for SMP req header */ 4182 smp_cmd.long_smp_req.long_req_addr = 4183 cpu_to_le64((u64)sg_dma_address 4184 (&task->smp_task.smp_req) + 4); 4185 /* exclude 4 bytes for SMP req header and CRC */ 4186 smp_cmd.long_smp_req.long_req_size = 4187 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); 4188 smp_cmd.long_smp_req.long_resp_addr = 4189 cpu_to_le64((u64)sg_dma_address 4190 (&task->smp_task.smp_resp)); 4191 smp_cmd.long_smp_req.long_resp_size = 4192 cpu_to_le32((u32)sg_dma_len 4193 (&task->smp_task.smp_resp)-4); 4194 } else { /* DIRECT MODE */ 4195 smp_cmd.long_smp_req.long_req_addr = 4196 cpu_to_le64((u64)sg_dma_address 4197 (&task->smp_task.smp_req)); 4198 smp_cmd.long_smp_req.long_req_size = 4199 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4200 smp_cmd.long_smp_req.long_resp_addr = 4201 cpu_to_le64((u64)sg_dma_address 4202 (&task->smp_task.smp_resp)); 4203 smp_cmd.long_smp_req.long_resp_size = 4204 cpu_to_le32 4205 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4206 } 4207 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 4208 PM8001_IO_DBG(pm8001_ha, 4209 pm8001_printk("SMP REQUEST DIRECT MODE\n")); 4210 for (i = 0; i < length; i++) 4211 if (i < 16) { 4212 smp_cmd.smp_req16[i] = *(preq_dma_addr+i); 4213 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4214 "Byte[%d]:%x (DMA data:%x)\n", 4215 i, smp_cmd.smp_req16[i], 4216 *(preq_dma_addr))); 4217 } else { 4218 smp_cmd.smp_req[i] = *(preq_dma_addr+i); 4219 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4220 "Byte[%d]:%x (DMA data:%x)\n", 4221 i, smp_cmd.smp_req[i], 4222 *(preq_dma_addr))); 4223 } 4224 } 4225 4226 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, 4227 &smp_cmd, pm8001_ha->smp_exp_mode, length); 4228 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd, 4229 sizeof(smp_cmd), 0); 4230 if (rc) 4231 goto err_out_2; 4232 return 0; 4233 4234 err_out_2: 4235 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4236 DMA_FROM_DEVICE); 4237 err_out: 4238 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4239 DMA_TO_DEVICE); 4240 return rc; 4241 } 4242 4243 static int check_enc_sas_cmd(struct sas_task *task) 4244 { 4245 u8 cmd = task->ssp_task.cmd->cmnd[0]; 4246 4247 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) 4248 return 1; 4249 else 4250 return 0; 4251 } 4252 4253 static int check_enc_sat_cmd(struct sas_task *task) 4254 { 4255 int ret = 0; 4256 switch (task->ata_task.fis.command) { 4257 case ATA_CMD_FPDMA_READ: 4258 case ATA_CMD_READ_EXT: 4259 case ATA_CMD_READ: 4260 case ATA_CMD_FPDMA_WRITE: 4261 case ATA_CMD_WRITE_EXT: 4262 case ATA_CMD_WRITE: 4263 case ATA_CMD_PIO_READ: 4264 case ATA_CMD_PIO_READ_EXT: 4265 case ATA_CMD_PIO_WRITE: 4266 case ATA_CMD_PIO_WRITE_EXT: 4267 ret = 1; 4268 break; 4269 default: 4270 ret = 0; 4271 break; 4272 } 4273 return ret; 4274 } 4275 4276 /** 4277 * pm80xx_chip_ssp_io_req - send a SSP task to FW 4278 * @pm8001_ha: our hba card information. 4279 * @ccb: the ccb information this request used. 4280 */ 4281 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4282 struct pm8001_ccb_info *ccb) 4283 { 4284 struct sas_task *task = ccb->task; 4285 struct domain_device *dev = task->dev; 4286 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4287 struct ssp_ini_io_start_req ssp_cmd; 4288 u32 tag = ccb->ccb_tag; 4289 int ret; 4290 u64 phys_addr, start_addr, end_addr; 4291 u32 end_addr_high, end_addr_low; 4292 struct inbound_queue_table *circularQ; 4293 u32 q_index; 4294 u32 opc = OPC_INB_SSPINIIOSTART; 4295 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4296 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4297 /* data address domain added for spcv; set to 0 by host, 4298 * used internally by controller 4299 * 0 for SAS 1.1 and SAS 2.0 compatible TLR 4300 */ 4301 ssp_cmd.dad_dir_m_tlr = 4302 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); 4303 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4304 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4305 ssp_cmd.tag = cpu_to_le32(tag); 4306 if (task->ssp_task.enable_first_burst) 4307 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4308 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4309 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4310 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4311 task->ssp_task.cmd->cmd_len); 4312 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM; 4313 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4314 4315 /* Check if encryption is set */ 4316 if (pm8001_ha->chip->encrypt && 4317 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { 4318 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4319 "Encryption enabled.Sending Encrypt SAS command 0x%x\n", 4320 task->ssp_task.cmd->cmnd[0])); 4321 opc = OPC_INB_SSP_INI_DIF_ENC_IO; 4322 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ 4323 ssp_cmd.dad_dir_m_tlr = cpu_to_le32 4324 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); 4325 4326 /* fill in PRD (scatter/gather) table, if any */ 4327 if (task->num_scatter > 1) { 4328 pm8001_chip_make_sg(task->scatter, 4329 ccb->n_elem, ccb->buf_prd); 4330 phys_addr = ccb->ccb_dma_handle + 4331 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4332 ssp_cmd.enc_addr_low = 4333 cpu_to_le32(lower_32_bits(phys_addr)); 4334 ssp_cmd.enc_addr_high = 4335 cpu_to_le32(upper_32_bits(phys_addr)); 4336 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4337 } else if (task->num_scatter == 1) { 4338 u64 dma_addr = sg_dma_address(task->scatter); 4339 ssp_cmd.enc_addr_low = 4340 cpu_to_le32(lower_32_bits(dma_addr)); 4341 ssp_cmd.enc_addr_high = 4342 cpu_to_le32(upper_32_bits(dma_addr)); 4343 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4344 ssp_cmd.enc_esgl = 0; 4345 /* Check 4G Boundary */ 4346 start_addr = cpu_to_le64(dma_addr); 4347 end_addr = (start_addr + ssp_cmd.enc_len) - 1; 4348 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4349 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4350 if (end_addr_high != ssp_cmd.enc_addr_high) { 4351 PM8001_FAIL_DBG(pm8001_ha, 4352 pm8001_printk("The sg list address " 4353 "start_addr=0x%016llx data_len=0x%x " 4354 "end_addr_high=0x%08x end_addr_low=" 4355 "0x%08x has crossed 4G boundary\n", 4356 start_addr, ssp_cmd.enc_len, 4357 end_addr_high, end_addr_low)); 4358 pm8001_chip_make_sg(task->scatter, 1, 4359 ccb->buf_prd); 4360 phys_addr = ccb->ccb_dma_handle + 4361 offsetof(struct pm8001_ccb_info, 4362 buf_prd[0]); 4363 ssp_cmd.enc_addr_low = 4364 cpu_to_le32(lower_32_bits(phys_addr)); 4365 ssp_cmd.enc_addr_high = 4366 cpu_to_le32(upper_32_bits(phys_addr)); 4367 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4368 } 4369 } else if (task->num_scatter == 0) { 4370 ssp_cmd.enc_addr_low = 0; 4371 ssp_cmd.enc_addr_high = 0; 4372 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4373 ssp_cmd.enc_esgl = 0; 4374 } 4375 /* XTS mode. All other fields are 0 */ 4376 ssp_cmd.key_cmode = 0x6 << 4; 4377 /* set tweak values. Should be the start lba */ 4378 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | 4379 (task->ssp_task.cmd->cmnd[3] << 16) | 4380 (task->ssp_task.cmd->cmnd[4] << 8) | 4381 (task->ssp_task.cmd->cmnd[5])); 4382 } else { 4383 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4384 "Sending Normal SAS command 0x%x inb q %x\n", 4385 task->ssp_task.cmd->cmnd[0], q_index)); 4386 /* fill in PRD (scatter/gather) table, if any */ 4387 if (task->num_scatter > 1) { 4388 pm8001_chip_make_sg(task->scatter, ccb->n_elem, 4389 ccb->buf_prd); 4390 phys_addr = ccb->ccb_dma_handle + 4391 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4392 ssp_cmd.addr_low = 4393 cpu_to_le32(lower_32_bits(phys_addr)); 4394 ssp_cmd.addr_high = 4395 cpu_to_le32(upper_32_bits(phys_addr)); 4396 ssp_cmd.esgl = cpu_to_le32(1<<31); 4397 } else if (task->num_scatter == 1) { 4398 u64 dma_addr = sg_dma_address(task->scatter); 4399 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4400 ssp_cmd.addr_high = 4401 cpu_to_le32(upper_32_bits(dma_addr)); 4402 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4403 ssp_cmd.esgl = 0; 4404 /* Check 4G Boundary */ 4405 start_addr = cpu_to_le64(dma_addr); 4406 end_addr = (start_addr + ssp_cmd.len) - 1; 4407 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4408 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4409 if (end_addr_high != ssp_cmd.addr_high) { 4410 PM8001_FAIL_DBG(pm8001_ha, 4411 pm8001_printk("The sg list address " 4412 "start_addr=0x%016llx data_len=0x%x " 4413 "end_addr_high=0x%08x end_addr_low=" 4414 "0x%08x has crossed 4G boundary\n", 4415 start_addr, ssp_cmd.len, 4416 end_addr_high, end_addr_low)); 4417 pm8001_chip_make_sg(task->scatter, 1, 4418 ccb->buf_prd); 4419 phys_addr = ccb->ccb_dma_handle + 4420 offsetof(struct pm8001_ccb_info, 4421 buf_prd[0]); 4422 ssp_cmd.addr_low = 4423 cpu_to_le32(lower_32_bits(phys_addr)); 4424 ssp_cmd.addr_high = 4425 cpu_to_le32(upper_32_bits(phys_addr)); 4426 ssp_cmd.esgl = cpu_to_le32(1<<31); 4427 } 4428 } else if (task->num_scatter == 0) { 4429 ssp_cmd.addr_low = 0; 4430 ssp_cmd.addr_high = 0; 4431 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4432 ssp_cmd.esgl = 0; 4433 } 4434 } 4435 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM; 4436 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4437 &ssp_cmd, sizeof(ssp_cmd), q_index); 4438 return ret; 4439 } 4440 4441 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4442 struct pm8001_ccb_info *ccb) 4443 { 4444 struct sas_task *task = ccb->task; 4445 struct domain_device *dev = task->dev; 4446 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4447 u32 tag = ccb->ccb_tag; 4448 int ret; 4449 u32 q_index; 4450 struct sata_start_req sata_cmd; 4451 u32 hdr_tag, ncg_tag = 0; 4452 u64 phys_addr, start_addr, end_addr; 4453 u32 end_addr_high, end_addr_low; 4454 u32 ATAP = 0x0; 4455 u32 dir; 4456 struct inbound_queue_table *circularQ; 4457 unsigned long flags; 4458 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4459 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4460 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM; 4461 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4462 4463 if (task->data_dir == DMA_NONE) { 4464 ATAP = 0x04; /* no data*/ 4465 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n")); 4466 } else if (likely(!task->ata_task.device_control_reg_update)) { 4467 if (task->ata_task.dma_xfer) { 4468 ATAP = 0x06; /* DMA */ 4469 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n")); 4470 } else { 4471 ATAP = 0x05; /* PIO*/ 4472 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n")); 4473 } 4474 if (task->ata_task.use_ncq && 4475 dev->sata_dev.class != ATA_DEV_ATAPI) { 4476 ATAP = 0x07; /* FPDMA */ 4477 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n")); 4478 } 4479 } 4480 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4481 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4482 ncg_tag = hdr_tag; 4483 } 4484 dir = data_dir_flags[task->data_dir] << 8; 4485 sata_cmd.tag = cpu_to_le32(tag); 4486 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4487 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4488 4489 sata_cmd.sata_fis = task->ata_task.fis; 4490 if (likely(!task->ata_task.device_control_reg_update)) 4491 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4492 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4493 4494 /* Check if encryption is set */ 4495 if (pm8001_ha->chip->encrypt && 4496 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { 4497 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4498 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", 4499 sata_cmd.sata_fis.command)); 4500 opc = OPC_INB_SATA_DIF_ENC_IO; 4501 4502 /* set encryption bit */ 4503 sata_cmd.ncqtag_atap_dir_m_dad = 4504 cpu_to_le32(((ncg_tag & 0xff)<<16)| 4505 ((ATAP & 0x3f) << 10) | 0x20 | dir); 4506 /* dad (bit 0-1) is 0 */ 4507 /* fill in PRD (scatter/gather) table, if any */ 4508 if (task->num_scatter > 1) { 4509 pm8001_chip_make_sg(task->scatter, 4510 ccb->n_elem, ccb->buf_prd); 4511 phys_addr = ccb->ccb_dma_handle + 4512 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4513 sata_cmd.enc_addr_low = lower_32_bits(phys_addr); 4514 sata_cmd.enc_addr_high = upper_32_bits(phys_addr); 4515 sata_cmd.enc_esgl = cpu_to_le32(1 << 31); 4516 } else if (task->num_scatter == 1) { 4517 u64 dma_addr = sg_dma_address(task->scatter); 4518 sata_cmd.enc_addr_low = lower_32_bits(dma_addr); 4519 sata_cmd.enc_addr_high = upper_32_bits(dma_addr); 4520 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4521 sata_cmd.enc_esgl = 0; 4522 /* Check 4G Boundary */ 4523 start_addr = cpu_to_le64(dma_addr); 4524 end_addr = (start_addr + sata_cmd.enc_len) - 1; 4525 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4526 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4527 if (end_addr_high != sata_cmd.enc_addr_high) { 4528 PM8001_FAIL_DBG(pm8001_ha, 4529 pm8001_printk("The sg list address " 4530 "start_addr=0x%016llx data_len=0x%x " 4531 "end_addr_high=0x%08x end_addr_low" 4532 "=0x%08x has crossed 4G boundary\n", 4533 start_addr, sata_cmd.enc_len, 4534 end_addr_high, end_addr_low)); 4535 pm8001_chip_make_sg(task->scatter, 1, 4536 ccb->buf_prd); 4537 phys_addr = ccb->ccb_dma_handle + 4538 offsetof(struct pm8001_ccb_info, 4539 buf_prd[0]); 4540 sata_cmd.enc_addr_low = 4541 lower_32_bits(phys_addr); 4542 sata_cmd.enc_addr_high = 4543 upper_32_bits(phys_addr); 4544 sata_cmd.enc_esgl = 4545 cpu_to_le32(1 << 31); 4546 } 4547 } else if (task->num_scatter == 0) { 4548 sata_cmd.enc_addr_low = 0; 4549 sata_cmd.enc_addr_high = 0; 4550 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4551 sata_cmd.enc_esgl = 0; 4552 } 4553 /* XTS mode. All other fields are 0 */ 4554 sata_cmd.key_index_mode = 0x6 << 4; 4555 /* set tweak values. Should be the start lba */ 4556 sata_cmd.twk_val0 = 4557 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | 4558 (sata_cmd.sata_fis.lbah << 16) | 4559 (sata_cmd.sata_fis.lbam << 8) | 4560 (sata_cmd.sata_fis.lbal)); 4561 sata_cmd.twk_val1 = 4562 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | 4563 (sata_cmd.sata_fis.lbam_exp)); 4564 } else { 4565 PM8001_IO_DBG(pm8001_ha, pm8001_printk( 4566 "Sending Normal SATA command 0x%x inb %x\n", 4567 sata_cmd.sata_fis.command, q_index)); 4568 /* dad (bit 0-1) is 0 */ 4569 sata_cmd.ncqtag_atap_dir_m_dad = 4570 cpu_to_le32(((ncg_tag & 0xff)<<16) | 4571 ((ATAP & 0x3f) << 10) | dir); 4572 4573 /* fill in PRD (scatter/gather) table, if any */ 4574 if (task->num_scatter > 1) { 4575 pm8001_chip_make_sg(task->scatter, 4576 ccb->n_elem, ccb->buf_prd); 4577 phys_addr = ccb->ccb_dma_handle + 4578 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4579 sata_cmd.addr_low = lower_32_bits(phys_addr); 4580 sata_cmd.addr_high = upper_32_bits(phys_addr); 4581 sata_cmd.esgl = cpu_to_le32(1 << 31); 4582 } else if (task->num_scatter == 1) { 4583 u64 dma_addr = sg_dma_address(task->scatter); 4584 sata_cmd.addr_low = lower_32_bits(dma_addr); 4585 sata_cmd.addr_high = upper_32_bits(dma_addr); 4586 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4587 sata_cmd.esgl = 0; 4588 /* Check 4G Boundary */ 4589 start_addr = cpu_to_le64(dma_addr); 4590 end_addr = (start_addr + sata_cmd.len) - 1; 4591 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4592 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4593 if (end_addr_high != sata_cmd.addr_high) { 4594 PM8001_FAIL_DBG(pm8001_ha, 4595 pm8001_printk("The sg list address " 4596 "start_addr=0x%016llx data_len=0x%x" 4597 "end_addr_high=0x%08x end_addr_low=" 4598 "0x%08x has crossed 4G boundary\n", 4599 start_addr, sata_cmd.len, 4600 end_addr_high, end_addr_low)); 4601 pm8001_chip_make_sg(task->scatter, 1, 4602 ccb->buf_prd); 4603 phys_addr = ccb->ccb_dma_handle + 4604 offsetof(struct pm8001_ccb_info, 4605 buf_prd[0]); 4606 sata_cmd.addr_low = 4607 lower_32_bits(phys_addr); 4608 sata_cmd.addr_high = 4609 upper_32_bits(phys_addr); 4610 sata_cmd.esgl = cpu_to_le32(1 << 31); 4611 } 4612 } else if (task->num_scatter == 0) { 4613 sata_cmd.addr_low = 0; 4614 sata_cmd.addr_high = 0; 4615 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4616 sata_cmd.esgl = 0; 4617 } 4618 /* scsi cdb */ 4619 sata_cmd.atapi_scsi_cdb[0] = 4620 cpu_to_le32(((task->ata_task.atapi_packet[0]) | 4621 (task->ata_task.atapi_packet[1] << 8) | 4622 (task->ata_task.atapi_packet[2] << 16) | 4623 (task->ata_task.atapi_packet[3] << 24))); 4624 sata_cmd.atapi_scsi_cdb[1] = 4625 cpu_to_le32(((task->ata_task.atapi_packet[4]) | 4626 (task->ata_task.atapi_packet[5] << 8) | 4627 (task->ata_task.atapi_packet[6] << 16) | 4628 (task->ata_task.atapi_packet[7] << 24))); 4629 sata_cmd.atapi_scsi_cdb[2] = 4630 cpu_to_le32(((task->ata_task.atapi_packet[8]) | 4631 (task->ata_task.atapi_packet[9] << 8) | 4632 (task->ata_task.atapi_packet[10] << 16) | 4633 (task->ata_task.atapi_packet[11] << 24))); 4634 sata_cmd.atapi_scsi_cdb[3] = 4635 cpu_to_le32(((task->ata_task.atapi_packet[12]) | 4636 (task->ata_task.atapi_packet[13] << 8) | 4637 (task->ata_task.atapi_packet[14] << 16) | 4638 (task->ata_task.atapi_packet[15] << 24))); 4639 } 4640 4641 /* Check for read log for failed drive and return */ 4642 if (sata_cmd.sata_fis.command == 0x2f) { 4643 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4644 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4645 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4646 struct task_status_struct *ts; 4647 4648 pm8001_ha_dev->id &= 0xDFFFFFFF; 4649 ts = &task->task_status; 4650 4651 spin_lock_irqsave(&task->task_state_lock, flags); 4652 ts->resp = SAS_TASK_COMPLETE; 4653 ts->stat = SAM_STAT_GOOD; 4654 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4655 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4656 task->task_state_flags |= SAS_TASK_STATE_DONE; 4657 if (unlikely((task->task_state_flags & 4658 SAS_TASK_STATE_ABORTED))) { 4659 spin_unlock_irqrestore(&task->task_state_lock, 4660 flags); 4661 PM8001_FAIL_DBG(pm8001_ha, 4662 pm8001_printk("task 0x%p resp 0x%x " 4663 " stat 0x%x but aborted by upper layer " 4664 "\n", task, ts->resp, ts->stat)); 4665 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4666 return 0; 4667 } else { 4668 spin_unlock_irqrestore(&task->task_state_lock, 4669 flags); 4670 pm8001_ccb_task_free_done(pm8001_ha, task, 4671 ccb, tag); 4672 return 0; 4673 } 4674 } 4675 } 4676 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM; 4677 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4678 &sata_cmd, sizeof(sata_cmd), q_index); 4679 return ret; 4680 } 4681 4682 /** 4683 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND 4684 * @pm8001_ha: our hba card information. 4685 * @num: the inbound queue number 4686 * @phy_id: the phy id which we wanted to start up. 4687 */ 4688 static int 4689 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4690 { 4691 struct phy_start_req payload; 4692 struct inbound_queue_table *circularQ; 4693 int ret; 4694 u32 tag = 0x01; 4695 u32 opcode = OPC_INB_PHYSTART; 4696 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4697 memset(&payload, 0, sizeof(payload)); 4698 payload.tag = cpu_to_le32(tag); 4699 4700 PM8001_INIT_DBG(pm8001_ha, 4701 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id)); 4702 4703 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4704 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id); 4705 /* SSC Disable and SAS Analog ST configuration */ 4706 /** 4707 payload.ase_sh_lm_slr_phyid = 4708 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | 4709 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | 4710 phy_id); 4711 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need 4712 **/ 4713 4714 payload.sas_identify.dev_type = SAS_END_DEVICE; 4715 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4716 memcpy(payload.sas_identify.sas_addr, 4717 &pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4718 payload.sas_identify.phy_id = phy_id; 4719 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4720 sizeof(payload), 0); 4721 return ret; 4722 } 4723 4724 /** 4725 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4726 * @pm8001_ha: our hba card information. 4727 * @num: the inbound queue number 4728 * @phy_id: the phy id which we wanted to start up. 4729 */ 4730 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4731 u8 phy_id) 4732 { 4733 struct phy_stop_req payload; 4734 struct inbound_queue_table *circularQ; 4735 int ret; 4736 u32 tag = 0x01; 4737 u32 opcode = OPC_INB_PHYSTOP; 4738 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4739 memset(&payload, 0, sizeof(payload)); 4740 payload.tag = cpu_to_le32(tag); 4741 payload.phy_id = cpu_to_le32(phy_id); 4742 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4743 sizeof(payload), 0); 4744 return ret; 4745 } 4746 4747 /** 4748 * see comments on pm8001_mpi_reg_resp. 4749 */ 4750 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4751 struct pm8001_device *pm8001_dev, u32 flag) 4752 { 4753 struct reg_dev_req payload; 4754 u32 opc; 4755 u32 stp_sspsmp_sata = 0x4; 4756 struct inbound_queue_table *circularQ; 4757 u32 linkrate, phy_id; 4758 int rc, tag = 0xdeadbeef; 4759 struct pm8001_ccb_info *ccb; 4760 u8 retryFlag = 0x1; 4761 u16 firstBurstSize = 0; 4762 u16 ITNT = 2000; 4763 struct domain_device *dev = pm8001_dev->sas_device; 4764 struct domain_device *parent_dev = dev->parent; 4765 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4766 4767 memset(&payload, 0, sizeof(payload)); 4768 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4769 if (rc) 4770 return rc; 4771 ccb = &pm8001_ha->ccb_info[tag]; 4772 ccb->device = pm8001_dev; 4773 ccb->ccb_tag = tag; 4774 payload.tag = cpu_to_le32(tag); 4775 4776 if (flag == 1) { 4777 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4778 } else { 4779 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4780 stp_sspsmp_sata = 0x00; /* stp*/ 4781 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4782 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4783 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4784 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4785 } 4786 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4787 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4788 else 4789 phy_id = pm8001_dev->attached_phy; 4790 4791 opc = OPC_INB_REG_DEV; 4792 4793 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4794 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4795 4796 payload.phyid_portid = 4797 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) | 4798 ((phy_id & 0xFF) << 8)); 4799 4800 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | 4801 ((linkrate & 0x0F) << 24) | 4802 ((stp_sspsmp_sata & 0x03) << 28)); 4803 payload.firstburstsize_ITNexustimeout = 4804 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4805 4806 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4807 SAS_ADDR_SIZE); 4808 4809 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4810 sizeof(payload), 0); 4811 if (rc) 4812 pm8001_tag_free(pm8001_ha, tag); 4813 4814 return rc; 4815 } 4816 4817 /** 4818 * pm80xx_chip_phy_ctl_req - support the local phy operation 4819 * @pm8001_ha: our hba card information. 4820 * @num: the inbound queue number 4821 * @phy_id: the phy id which we wanted to operate 4822 * @phy_op: 4823 */ 4824 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4825 u32 phyId, u32 phy_op) 4826 { 4827 u32 tag; 4828 int rc; 4829 struct local_phy_ctl_req payload; 4830 struct inbound_queue_table *circularQ; 4831 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4832 memset(&payload, 0, sizeof(payload)); 4833 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4834 if (rc) 4835 return rc; 4836 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4837 payload.tag = cpu_to_le32(tag); 4838 payload.phyop_phyid = 4839 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); 4840 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4841 sizeof(payload), 0); 4842 } 4843 4844 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4845 { 4846 #ifdef PM8001_USE_MSIX 4847 return 1; 4848 #else 4849 u32 value; 4850 4851 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4852 if (value) 4853 return 1; 4854 return 0; 4855 #endif 4856 } 4857 4858 /** 4859 * pm8001_chip_isr - PM8001 isr handler. 4860 * @pm8001_ha: our hba card information. 4861 * @irq: irq number. 4862 * @stat: stat. 4863 */ 4864 static irqreturn_t 4865 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4866 { 4867 pm80xx_chip_interrupt_disable(pm8001_ha, vec); 4868 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk( 4869 "irq vec %d, ODMR:0x%x\n", 4870 vec, pm8001_cr32(pm8001_ha, 0, 0x30))); 4871 process_oq(pm8001_ha, vec); 4872 pm80xx_chip_interrupt_enable(pm8001_ha, vec); 4873 return IRQ_HANDLED; 4874 } 4875 4876 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha, 4877 u32 operation, u32 phyid, u32 length, u32 *buf) 4878 { 4879 u32 tag , i, j = 0; 4880 int rc; 4881 struct set_phy_profile_req payload; 4882 struct inbound_queue_table *circularQ; 4883 u32 opc = OPC_INB_SET_PHY_PROFILE; 4884 4885 memset(&payload, 0, sizeof(payload)); 4886 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4887 if (rc) 4888 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n")); 4889 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4890 payload.tag = cpu_to_le32(tag); 4891 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF)); 4892 PM8001_INIT_DBG(pm8001_ha, 4893 pm8001_printk(" phy profile command for phy %x ,length is %d\n", 4894 payload.ppc_phyid, length)); 4895 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { 4896 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i)); 4897 j++; 4898 } 4899 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4900 sizeof(payload), 0); 4901 if (rc) 4902 pm8001_tag_free(pm8001_ha, tag); 4903 } 4904 4905 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 4906 u32 length, u8 *buf) 4907 { 4908 u32 i; 4909 4910 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 4911 mpi_set_phy_profile_req(pm8001_ha, 4912 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf); 4913 length = length + PHY_DWORD_LENGTH; 4914 } 4915 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n")); 4916 } 4917 4918 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, 4919 u32 phy, u32 length, u32 *buf) 4920 { 4921 u32 tag, opc; 4922 int rc, i; 4923 struct set_phy_profile_req payload; 4924 struct inbound_queue_table *circularQ; 4925 4926 memset(&payload, 0, sizeof(payload)); 4927 4928 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4929 if (rc) 4930 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag")); 4931 4932 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4933 opc = OPC_INB_SET_PHY_PROFILE; 4934 4935 payload.tag = cpu_to_le32(tag); 4936 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8) 4937 | (phy & 0xFF)); 4938 4939 for (i = 0; i < length; i++) 4940 payload.reserved[i] = cpu_to_le32(*(buf + i)); 4941 4942 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4943 sizeof(payload), 0); 4944 if (rc) 4945 pm8001_tag_free(pm8001_ha, tag); 4946 4947 PM8001_INIT_DBG(pm8001_ha, 4948 pm8001_printk("PHY %d settings applied", phy)); 4949 } 4950 const struct pm8001_dispatch pm8001_80xx_dispatch = { 4951 .name = "pmc80xx", 4952 .chip_init = pm80xx_chip_init, 4953 .chip_soft_rst = pm80xx_chip_soft_rst, 4954 .chip_rst = pm80xx_hw_chip_rst, 4955 .chip_iounmap = pm8001_chip_iounmap, 4956 .isr = pm80xx_chip_isr, 4957 .is_our_interrupt = pm80xx_chip_is_our_interrupt, 4958 .isr_process_oq = process_oq, 4959 .interrupt_enable = pm80xx_chip_interrupt_enable, 4960 .interrupt_disable = pm80xx_chip_interrupt_disable, 4961 .make_prd = pm8001_chip_make_sg, 4962 .smp_req = pm80xx_chip_smp_req, 4963 .ssp_io_req = pm80xx_chip_ssp_io_req, 4964 .sata_req = pm80xx_chip_sata_req, 4965 .phy_start_req = pm80xx_chip_phy_start_req, 4966 .phy_stop_req = pm80xx_chip_phy_stop_req, 4967 .reg_dev_req = pm80xx_chip_reg_dev_req, 4968 .dereg_dev_req = pm8001_chip_dereg_dev_req, 4969 .phy_ctl_req = pm80xx_chip_phy_ctl_req, 4970 .task_abort = pm8001_chip_abort_task, 4971 .ssp_tm_req = pm8001_chip_ssp_tm_req, 4972 .get_nvmd_req = pm8001_chip_get_nvmd_req, 4973 .set_nvmd_req = pm8001_chip_set_nvmd_req, 4974 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4975 .set_dev_state_req = pm8001_chip_set_dev_state_req, 4976 }; 4977