1 /* 2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 PMC-Sierra, Inc., 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm80xx_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 #define SMP_DIRECT 1 47 #define SMP_INDIRECT 2 48 49 50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value) 51 { 52 u32 reg_val; 53 unsigned long start; 54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); 55 /* confirm the setting is written */ 56 start = jiffies + HZ; /* 1 sec */ 57 do { 58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); 59 } while ((reg_val != shift_value) && time_before(jiffies, start)); 60 if (reg_val != shift_value) { 61 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n", 62 reg_val); 63 return -1; 64 } 65 return 0; 66 } 67 68 static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset, 69 const void *destination, 70 u32 dw_count, u32 bus_base_number) 71 { 72 u32 index, value, offset; 73 u32 *destination1; 74 destination1 = (u32 *)destination; 75 76 for (index = 0; index < dw_count; index += 4, destination1++) { 77 offset = (soffset + index); 78 if (offset < (64 * 1024)) { 79 value = pm8001_cr32(pm8001_ha, bus_base_number, offset); 80 *destination1 = cpu_to_le32(value); 81 } 82 } 83 return; 84 } 85 86 ssize_t pm80xx_get_fatal_dump(struct device *cdev, 87 struct device_attribute *attr, char *buf) 88 { 89 struct Scsi_Host *shost = class_to_shost(cdev); 90 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 91 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 92 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; 93 u32 accum_len, reg_val, index, *temp; 94 u32 status = 1; 95 unsigned long start; 96 u8 *direct_data; 97 char *fatal_error_data = buf; 98 u32 length_to_read; 99 u32 offset; 100 101 pm8001_ha->forensic_info.data_buf.direct_data = buf; 102 if (pm8001_ha->chip_id == chip_8001) { 103 pm8001_ha->forensic_info.data_buf.direct_data += 104 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 105 "Not supported for SPC controller"); 106 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 107 (char *)buf; 108 } 109 /* initialize variables for very first call from host application */ 110 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 111 pm8001_dbg(pm8001_ha, IO, 112 "forensic_info TYPE_NON_FATAL..............\n"); 113 direct_data = (u8 *)fatal_error_data; 114 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; 115 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; 116 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 117 pm8001_ha->forensic_info.data_buf.read_len = 0; 118 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 119 120 /* Write signature to fatal dump table */ 121 pm8001_mw32(fatal_table_address, 122 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd); 123 124 pm8001_ha->forensic_info.data_buf.direct_data = direct_data; 125 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status); 126 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n", 127 pm8001_ha->forensic_info.data_buf.read_len); 128 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n", 129 pm8001_ha->forensic_info.data_buf.direct_len); 130 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n", 131 pm8001_ha->forensic_info.data_buf.direct_offset); 132 } 133 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 134 /* start to get data */ 135 /* Program the MEMBASE II Shifting Register with 0x00.*/ 136 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 137 pm8001_ha->fatal_forensic_shift_offset); 138 pm8001_ha->forensic_last_offset = 0; 139 pm8001_ha->forensic_fatal_step = 0; 140 pm8001_ha->fatal_bar_loc = 0; 141 } 142 143 /* Read until accum_len is retrived */ 144 accum_len = pm8001_mr32(fatal_table_address, 145 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 146 /* Determine length of data between previously stored transfer length 147 * and current accumulated transfer length 148 */ 149 length_to_read = 150 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer; 151 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n", 152 accum_len); 153 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n", 154 length_to_read); 155 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n", 156 pm8001_ha->forensic_last_offset); 157 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n", 158 pm8001_ha->forensic_info.data_buf.read_len); 159 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n", 160 pm8001_ha->forensic_info.data_buf.direct_len); 161 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n", 162 pm8001_ha->forensic_info.data_buf.direct_offset); 163 164 /* If accumulated length failed to read correctly fail the attempt.*/ 165 if (accum_len == 0xFFFFFFFF) { 166 pm8001_dbg(pm8001_ha, IO, 167 "Possible PCI issue 0x%x not expected\n", 168 accum_len); 169 return status; 170 } 171 /* If accumulated length is zero fail the attempt */ 172 if (accum_len == 0) { 173 pm8001_ha->forensic_info.data_buf.direct_data += 174 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 175 "%08x ", 0xFFFFFFFF); 176 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 177 (char *)buf; 178 } 179 /* Accumulated length is good so start capturing the first data */ 180 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 181 if (pm8001_ha->forensic_fatal_step == 0) { 182 moreData: 183 /* If data to read is less than SYSFS_OFFSET then reduce the 184 * length of dataLen 185 */ 186 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET 187 > length_to_read) { 188 pm8001_ha->forensic_info.data_buf.direct_len = 189 length_to_read - 190 pm8001_ha->forensic_last_offset; 191 } else { 192 pm8001_ha->forensic_info.data_buf.direct_len = 193 SYSFS_OFFSET; 194 } 195 if (pm8001_ha->forensic_info.data_buf.direct_data) { 196 /* Data is in bar, copy to host memory */ 197 pm80xx_pci_mem_copy(pm8001_ha, 198 pm8001_ha->fatal_bar_loc, 199 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, 200 pm8001_ha->forensic_info.data_buf.direct_len, 1); 201 } 202 pm8001_ha->fatal_bar_loc += 203 pm8001_ha->forensic_info.data_buf.direct_len; 204 pm8001_ha->forensic_info.data_buf.direct_offset += 205 pm8001_ha->forensic_info.data_buf.direct_len; 206 pm8001_ha->forensic_last_offset += 207 pm8001_ha->forensic_info.data_buf.direct_len; 208 pm8001_ha->forensic_info.data_buf.read_len = 209 pm8001_ha->forensic_info.data_buf.direct_len; 210 211 if (pm8001_ha->forensic_last_offset >= length_to_read) { 212 pm8001_ha->forensic_info.data_buf.direct_data += 213 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 214 "%08x ", 3); 215 for (index = 0; index < 216 (pm8001_ha->forensic_info.data_buf.direct_len 217 / 4); index++) { 218 pm8001_ha->forensic_info.data_buf.direct_data += 219 sprintf( 220 pm8001_ha->forensic_info.data_buf.direct_data, 221 "%08x ", *(temp + index)); 222 } 223 224 pm8001_ha->fatal_bar_loc = 0; 225 pm8001_ha->forensic_fatal_step = 1; 226 pm8001_ha->fatal_forensic_shift_offset = 0; 227 pm8001_ha->forensic_last_offset = 0; 228 status = 0; 229 offset = (int) 230 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 231 - (char *)buf); 232 pm8001_dbg(pm8001_ha, IO, 233 "get_fatal_spcv:return1 0x%x\n", offset); 234 return (char *)pm8001_ha-> 235 forensic_info.data_buf.direct_data - 236 (char *)buf; 237 } 238 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { 239 pm8001_ha->forensic_info.data_buf.direct_data += 240 sprintf(pm8001_ha-> 241 forensic_info.data_buf.direct_data, 242 "%08x ", 2); 243 for (index = 0; index < 244 (pm8001_ha->forensic_info.data_buf.direct_len 245 / 4); index++) { 246 pm8001_ha->forensic_info.data_buf.direct_data 247 += sprintf(pm8001_ha-> 248 forensic_info.data_buf.direct_data, 249 "%08x ", *(temp + index)); 250 } 251 status = 0; 252 offset = (int) 253 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 254 - (char *)buf); 255 pm8001_dbg(pm8001_ha, IO, 256 "get_fatal_spcv:return2 0x%x\n", offset); 257 return (char *)pm8001_ha-> 258 forensic_info.data_buf.direct_data - 259 (char *)buf; 260 } 261 262 /* Increment the MEMBASE II Shifting Register value by 0x100.*/ 263 pm8001_ha->forensic_info.data_buf.direct_data += 264 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 265 "%08x ", 2); 266 for (index = 0; index < 267 (pm8001_ha->forensic_info.data_buf.direct_len 268 / 4) ; index++) { 269 pm8001_ha->forensic_info.data_buf.direct_data += 270 sprintf(pm8001_ha-> 271 forensic_info.data_buf.direct_data, 272 "%08x ", *(temp + index)); 273 } 274 pm8001_ha->fatal_forensic_shift_offset += 0x100; 275 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 276 pm8001_ha->fatal_forensic_shift_offset); 277 pm8001_ha->fatal_bar_loc = 0; 278 status = 0; 279 offset = (int) 280 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 281 - (char *)buf); 282 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n", 283 offset); 284 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 285 (char *)buf; 286 } 287 if (pm8001_ha->forensic_fatal_step == 1) { 288 /* store previous accumulated length before triggering next 289 * accumulated length update 290 */ 291 pm8001_ha->forensic_preserved_accumulated_transfer = 292 pm8001_mr32(fatal_table_address, 293 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 294 295 /* continue capturing the fatal log until Dump status is 0x3 */ 296 if (pm8001_mr32(fatal_table_address, 297 MPI_FATAL_EDUMP_TABLE_STATUS) < 298 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) { 299 300 /* reset fddstat bit by writing to zero*/ 301 pm8001_mw32(fatal_table_address, 302 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0); 303 304 /* set dump control value to '1' so that new data will 305 * be transferred to shared memory 306 */ 307 pm8001_mw32(fatal_table_address, 308 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 309 MPI_FATAL_EDUMP_HANDSHAKE_RDY); 310 311 /*Poll FDDHSHK until clear */ 312 start = jiffies + (2 * HZ); /* 2 sec */ 313 314 do { 315 reg_val = pm8001_mr32(fatal_table_address, 316 MPI_FATAL_EDUMP_TABLE_HANDSHAKE); 317 } while ((reg_val) && time_before(jiffies, start)); 318 319 if (reg_val != 0) { 320 pm8001_dbg(pm8001_ha, FAIL, 321 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n", 322 reg_val); 323 /* Fail the dump if a timeout occurs */ 324 pm8001_ha->forensic_info.data_buf.direct_data += 325 sprintf( 326 pm8001_ha->forensic_info.data_buf.direct_data, 327 "%08x ", 0xFFFFFFFF); 328 return((char *) 329 pm8001_ha->forensic_info.data_buf.direct_data 330 - (char *)buf); 331 } 332 /* Poll status register until set to 2 or 333 * 3 for up to 2 seconds 334 */ 335 start = jiffies + (2 * HZ); /* 2 sec */ 336 337 do { 338 reg_val = pm8001_mr32(fatal_table_address, 339 MPI_FATAL_EDUMP_TABLE_STATUS); 340 } while (((reg_val != 2) && (reg_val != 3)) && 341 time_before(jiffies, start)); 342 343 if (reg_val < 2) { 344 pm8001_dbg(pm8001_ha, FAIL, 345 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n", 346 reg_val); 347 /* Fail the dump if a timeout occurs */ 348 pm8001_ha->forensic_info.data_buf.direct_data += 349 sprintf( 350 pm8001_ha->forensic_info.data_buf.direct_data, 351 "%08x ", 0xFFFFFFFF); 352 return((char *)pm8001_ha->forensic_info.data_buf.direct_data - 353 (char *)buf); 354 } 355 /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */ 356 pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */ 357 pm8001_cw32(pm8001_ha, 0, 358 MEMBASE_II_SHIFT_REGISTER, 359 pm8001_ha->fatal_forensic_shift_offset); 360 } 361 /* Read the next block of the debug data.*/ 362 length_to_read = pm8001_mr32(fatal_table_address, 363 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) - 364 pm8001_ha->forensic_preserved_accumulated_transfer; 365 if (length_to_read != 0x0) { 366 pm8001_ha->forensic_fatal_step = 0; 367 goto moreData; 368 } else { 369 pm8001_ha->forensic_info.data_buf.direct_data += 370 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 371 "%08x ", 4); 372 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF; 373 pm8001_ha->forensic_info.data_buf.direct_len = 0; 374 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 375 pm8001_ha->forensic_info.data_buf.read_len = 0; 376 } 377 } 378 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data 379 - (char *)buf); 380 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset); 381 return ((char *)pm8001_ha->forensic_info.data_buf.direct_data - 382 (char *)buf); 383 } 384 385 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma 386 * location by the firmware. 387 */ 388 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev, 389 struct device_attribute *attr, char *buf) 390 { 391 struct Scsi_Host *shost = class_to_shost(cdev); 392 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 393 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 394 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr; 395 u32 accum_len = 0; 396 u32 total_len = 0; 397 u32 reg_val = 0; 398 u32 *temp = NULL; 399 u32 index = 0; 400 u32 output_length; 401 unsigned long start = 0; 402 char *buf_copy = buf; 403 404 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 405 if (++pm8001_ha->non_fatal_count == 1) { 406 if (pm8001_ha->chip_id == chip_8001) { 407 snprintf(pm8001_ha->forensic_info.data_buf.direct_data, 408 PAGE_SIZE, "Not supported for SPC controller"); 409 return 0; 410 } 411 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n"); 412 /* 413 * Step 1: Write the host buffer parameters in the MPI Fatal and 414 * Non-Fatal Error Dump Capture Table.This is the buffer 415 * where debug data will be DMAed to. 416 */ 417 pm8001_mw32(nonfatal_table_address, 418 MPI_FATAL_EDUMP_TABLE_LO_OFFSET, 419 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo); 420 421 pm8001_mw32(nonfatal_table_address, 422 MPI_FATAL_EDUMP_TABLE_HI_OFFSET, 423 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi); 424 425 pm8001_mw32(nonfatal_table_address, 426 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET); 427 428 /* Optionally, set the DUMPCTRL bit to 1 if the host 429 * keeps sending active I/Os while capturing the non-fatal 430 * debug data. Otherwise, leave this bit set to zero 431 */ 432 pm8001_mw32(nonfatal_table_address, 433 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY); 434 435 /* 436 * Step 2: Clear Accumulative Length of Debug Data Transferred 437 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump 438 * Capture Table to zero. 439 */ 440 pm8001_mw32(nonfatal_table_address, 441 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0); 442 443 /* initiallize previous accumulated length to 0 */ 444 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 445 pm8001_ha->non_fatal_read_length = 0; 446 } 447 448 total_len = pm8001_mr32(nonfatal_table_address, 449 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN); 450 /* 451 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT] 452 * field and then request that the SPCv controller transfer the debug 453 * data by setting bit 7 of the Inbound Doorbell Set Register. 454 */ 455 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0); 456 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, 457 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP); 458 459 /* 460 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for 461 * 2 seconds) until register bit 7 is cleared. 462 * This step only indicates the request is accepted by the controller. 463 */ 464 start = jiffies + (2 * HZ); /* 2 sec */ 465 do { 466 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) & 467 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP; 468 } while ((reg_val != 0) && time_before(jiffies, start)); 469 470 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non 471 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in 472 * the MPI Fatal and Non-Fatal Error Dump Capture Table. 473 */ 474 start = jiffies + (2 * HZ); /* 2 sec */ 475 do { 476 reg_val = pm8001_mr32(nonfatal_table_address, 477 MPI_FATAL_EDUMP_TABLE_STATUS); 478 } while ((!reg_val) && time_before(jiffies, start)); 479 480 if ((reg_val == 0x00) || 481 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) || 482 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) { 483 pm8001_ha->non_fatal_read_length = 0; 484 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF); 485 pm8001_ha->non_fatal_count = 0; 486 return (buf_copy - buf); 487 } else if (reg_val == 488 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) { 489 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2); 490 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) || 491 (pm8001_ha->non_fatal_read_length >= total_len)) { 492 pm8001_ha->non_fatal_read_length = 0; 493 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4); 494 pm8001_ha->non_fatal_count = 0; 495 } 496 accum_len = pm8001_mr32(nonfatal_table_address, 497 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 498 output_length = accum_len - 499 pm8001_ha->forensic_preserved_accumulated_transfer; 500 501 for (index = 0; index < output_length/4; index++) 502 buf_copy += snprintf(buf_copy, PAGE_SIZE, 503 "%08x ", *(temp+index)); 504 505 pm8001_ha->non_fatal_read_length += output_length; 506 507 /* store current accumulated length to use in next iteration as 508 * the previous accumulated length 509 */ 510 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len; 511 return (buf_copy - buf); 512 } 513 514 /** 515 * read_main_config_table - read the configure table and save it. 516 * @pm8001_ha: our hba card information 517 */ 518 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 519 { 520 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 521 522 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = 523 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); 524 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = 525 pm8001_mr32(address, MAIN_INTERFACE_REVISION); 526 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = 527 pm8001_mr32(address, MAIN_FW_REVISION); 528 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = 529 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); 530 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = 531 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); 532 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = 533 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); 534 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = 535 pm8001_mr32(address, MAIN_GST_OFFSET); 536 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = 537 pm8001_mr32(address, MAIN_IBQ_OFFSET); 538 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = 539 pm8001_mr32(address, MAIN_OBQ_OFFSET); 540 541 /* read Error Dump Offset and Length */ 542 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = 543 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 544 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = 545 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 546 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = 547 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 548 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = 549 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 550 551 /* read GPIO LED settings from the configuration table */ 552 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = 553 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); 554 555 /* read analog Setting offset from the configuration table */ 556 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = 557 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 558 559 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = 560 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); 561 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = 562 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); 563 /* read port recover and reset timeout */ 564 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer = 565 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER); 566 /* read ILA and inactive firmware version */ 567 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version = 568 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE); 569 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version = 570 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION); 571 572 pm8001_dbg(pm8001_ha, DEV, 573 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n", 574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature, 575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev, 576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev); 577 578 pm8001_dbg(pm8001_ha, DEV, 579 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n", 580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset, 581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset, 582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset, 583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset, 584 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset); 585 586 pm8001_dbg(pm8001_ha, DEV, 587 "Main cfg table; ila rev:%x Inactive fw rev:%x\n", 588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version, 589 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version); 590 } 591 592 /** 593 * read_general_status_table - read the general status table and save it. 594 * @pm8001_ha: our hba card information 595 */ 596 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 597 { 598 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 599 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = 600 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); 601 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = 602 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); 603 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = 604 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); 605 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = 606 pm8001_mr32(address, GST_MSGUTCNT_OFFSET); 607 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = 608 pm8001_mr32(address, GST_IOPTCNT_OFFSET); 609 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = 610 pm8001_mr32(address, GST_GPIO_INPUT_VAL); 611 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = 612 pm8001_mr32(address, GST_RERRINFO_OFFSET0); 613 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = 614 pm8001_mr32(address, GST_RERRINFO_OFFSET1); 615 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = 616 pm8001_mr32(address, GST_RERRINFO_OFFSET2); 617 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = 618 pm8001_mr32(address, GST_RERRINFO_OFFSET3); 619 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = 620 pm8001_mr32(address, GST_RERRINFO_OFFSET4); 621 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = 622 pm8001_mr32(address, GST_RERRINFO_OFFSET5); 623 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = 624 pm8001_mr32(address, GST_RERRINFO_OFFSET6); 625 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = 626 pm8001_mr32(address, GST_RERRINFO_OFFSET7); 627 } 628 /** 629 * read_phy_attr_table - read the phy attribute table and save it. 630 * @pm8001_ha: our hba card information 631 */ 632 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) 633 { 634 void __iomem *address = pm8001_ha->pspa_q_tbl_addr; 635 pm8001_ha->phy_attr_table.phystart1_16[0] = 636 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); 637 pm8001_ha->phy_attr_table.phystart1_16[1] = 638 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); 639 pm8001_ha->phy_attr_table.phystart1_16[2] = 640 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); 641 pm8001_ha->phy_attr_table.phystart1_16[3] = 642 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); 643 pm8001_ha->phy_attr_table.phystart1_16[4] = 644 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); 645 pm8001_ha->phy_attr_table.phystart1_16[5] = 646 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); 647 pm8001_ha->phy_attr_table.phystart1_16[6] = 648 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); 649 pm8001_ha->phy_attr_table.phystart1_16[7] = 650 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); 651 pm8001_ha->phy_attr_table.phystart1_16[8] = 652 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); 653 pm8001_ha->phy_attr_table.phystart1_16[9] = 654 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); 655 pm8001_ha->phy_attr_table.phystart1_16[10] = 656 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); 657 pm8001_ha->phy_attr_table.phystart1_16[11] = 658 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); 659 pm8001_ha->phy_attr_table.phystart1_16[12] = 660 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); 661 pm8001_ha->phy_attr_table.phystart1_16[13] = 662 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); 663 pm8001_ha->phy_attr_table.phystart1_16[14] = 664 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); 665 pm8001_ha->phy_attr_table.phystart1_16[15] = 666 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); 667 668 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = 669 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); 670 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = 671 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); 672 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = 673 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); 674 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = 675 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); 676 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = 677 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); 678 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = 679 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); 680 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = 681 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); 682 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = 683 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); 684 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = 685 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); 686 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = 687 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); 688 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = 689 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); 690 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = 691 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); 692 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = 693 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); 694 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = 695 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); 696 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = 697 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); 698 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = 699 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); 700 701 } 702 703 /** 704 * read_inbnd_queue_table - read the inbound queue table and save it. 705 * @pm8001_ha: our hba card information 706 */ 707 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 708 { 709 int i; 710 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 711 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 712 u32 offset = i * 0x20; 713 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 714 get_pci_bar_index(pm8001_mr32(address, 715 (offset + IB_PIPCI_BAR))); 716 pm8001_ha->inbnd_q_tbl[i].pi_offset = 717 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); 718 } 719 } 720 721 /** 722 * read_outbnd_queue_table - read the outbound queue table and save it. 723 * @pm8001_ha: our hba card information 724 */ 725 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 726 { 727 int i; 728 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 729 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 730 u32 offset = i * 0x24; 731 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 732 get_pci_bar_index(pm8001_mr32(address, 733 (offset + OB_CIPCI_BAR))); 734 pm8001_ha->outbnd_q_tbl[i].ci_offset = 735 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); 736 } 737 } 738 739 /** 740 * init_default_table_values - init the default table. 741 * @pm8001_ha: our hba card information 742 */ 743 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 744 { 745 int i; 746 u32 offsetib, offsetob; 747 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 748 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 749 u32 ib_offset = pm8001_ha->ib_offset; 750 u32 ob_offset = pm8001_ha->ob_offset; 751 u32 ci_offset = pm8001_ha->ci_offset; 752 u32 pi_offset = pm8001_ha->pi_offset; 753 754 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = 755 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 756 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = 757 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 758 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = 759 PM8001_EVENT_LOG_SIZE; 760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; 761 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = 762 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 763 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = 764 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 765 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = 766 PM8001_EVENT_LOG_SIZE; 767 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; 768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; 769 770 /* Disable end to end CRC checking */ 771 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); 772 773 for (i = 0; i < pm8001_ha->max_q_num; i++) { 774 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 775 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 776 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 777 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; 778 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 779 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; 780 pm8001_ha->inbnd_q_tbl[i].base_virt = 781 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; 782 pm8001_ha->inbnd_q_tbl[i].total_length = 783 pm8001_ha->memoryMap.region[ib_offset + i].total_len; 784 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 785 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; 786 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 787 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; 788 pm8001_ha->inbnd_q_tbl[i].ci_virt = 789 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; 790 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0); 791 offsetib = i * 0x20; 792 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 793 get_pci_bar_index(pm8001_mr32(addressib, 794 (offsetib + 0x14))); 795 pm8001_ha->inbnd_q_tbl[i].pi_offset = 796 pm8001_mr32(addressib, (offsetib + 0x18)); 797 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 798 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 799 800 pm8001_dbg(pm8001_ha, DEV, 801 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i, 802 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar, 803 pm8001_ha->inbnd_q_tbl[i].pi_offset); 804 } 805 for (i = 0; i < pm8001_ha->max_q_num; i++) { 806 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 807 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 808 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 809 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; 810 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 811 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; 812 pm8001_ha->outbnd_q_tbl[i].base_virt = 813 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; 814 pm8001_ha->outbnd_q_tbl[i].total_length = 815 pm8001_ha->memoryMap.region[ob_offset + i].total_len; 816 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 817 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; 818 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 819 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; 820 /* interrupt vector based on oq */ 821 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); 822 pm8001_ha->outbnd_q_tbl[i].pi_virt = 823 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; 824 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0); 825 offsetob = i * 0x24; 826 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 827 get_pci_bar_index(pm8001_mr32(addressob, 828 offsetob + 0x14)); 829 pm8001_ha->outbnd_q_tbl[i].ci_offset = 830 pm8001_mr32(addressob, (offsetob + 0x18)); 831 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 832 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 833 834 pm8001_dbg(pm8001_ha, DEV, 835 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i, 836 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar, 837 pm8001_ha->outbnd_q_tbl[i].ci_offset); 838 } 839 } 840 841 /** 842 * update_main_config_table - update the main default table to the HBA. 843 * @pm8001_ha: our hba card information 844 */ 845 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 846 { 847 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 848 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, 849 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); 850 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, 851 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); 852 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, 853 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); 854 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, 855 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); 856 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, 857 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); 858 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, 859 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); 860 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, 861 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); 862 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, 863 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); 864 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, 865 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); 866 /* Update Fatal error interrupt vector */ 867 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 868 ((pm8001_ha->max_q_num - 1) << 8); 869 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, 870 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); 871 pm8001_dbg(pm8001_ha, DEV, 872 "Updated Fatal error interrupt vector 0x%x\n", 873 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)); 874 875 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, 876 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); 877 878 /* SPCv specific */ 879 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; 880 /* Set GPIOLED to 0x2 for LED indicator */ 881 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; 882 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, 883 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); 884 pm8001_dbg(pm8001_ha, DEV, 885 "Programming DW 0x21 in main cfg table with 0x%x\n", 886 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)); 887 888 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 889 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 890 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, 891 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); 892 893 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000; 894 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 895 PORT_RECOVERY_TIMEOUT; 896 if (pm8001_ha->chip_id == chip_8006) { 897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 898 0x0000ffff; 899 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 900 CHIP_8006_PORT_RECOVERY_TIMEOUT; 901 } 902 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 903 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 904 } 905 906 /** 907 * update_inbnd_queue_table - update the inbound queue table to the HBA. 908 * @pm8001_ha: our hba card information 909 * @number: entry in the queue 910 */ 911 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 912 int number) 913 { 914 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 915 u16 offset = number * 0x20; 916 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, 917 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 918 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, 919 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 920 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, 921 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 922 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, 923 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 924 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, 925 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 926 927 pm8001_dbg(pm8001_ha, DEV, 928 "IQ %d: Element pri size 0x%x\n", 929 number, 930 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 931 932 pm8001_dbg(pm8001_ha, DEV, 933 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n", 934 pm8001_ha->inbnd_q_tbl[number].upper_base_addr, 935 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 936 937 pm8001_dbg(pm8001_ha, DEV, 938 "CI upper base addr 0x%x CI lower base addr 0x%x\n", 939 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr, 940 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 941 } 942 943 /** 944 * update_outbnd_queue_table - update the outbound queue table to the HBA. 945 * @pm8001_ha: our hba card information 946 * @number: entry in the queue 947 */ 948 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 949 int number) 950 { 951 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 952 u16 offset = number * 0x24; 953 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, 954 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 955 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, 956 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 957 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, 958 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 959 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, 960 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 961 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, 962 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 963 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, 964 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 965 966 pm8001_dbg(pm8001_ha, DEV, 967 "OQ %d: Element pri size 0x%x\n", 968 number, 969 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 970 971 pm8001_dbg(pm8001_ha, DEV, 972 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n", 973 pm8001_ha->outbnd_q_tbl[number].upper_base_addr, 974 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 975 976 pm8001_dbg(pm8001_ha, DEV, 977 "PI upper base addr 0x%x PI lower base addr 0x%x\n", 978 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr, 979 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 980 } 981 982 /** 983 * mpi_init_check - check firmware initialization status. 984 * @pm8001_ha: our hba card information 985 */ 986 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 987 { 988 u32 max_wait_count; 989 u32 value; 990 u32 gst_len_mpistate; 991 992 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 993 table is updated */ 994 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); 995 /* wait until Inbound DoorBell Clear Register toggled */ 996 if (IS_SPCV_12G(pm8001_ha->pdev)) { 997 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 998 } else { 999 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 1000 } 1001 do { 1002 msleep(FW_READY_INTERVAL); 1003 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1004 value &= SPCv_MSGU_CFG_TABLE_UPDATE; 1005 } while ((value != 0) && (--max_wait_count)); 1006 1007 if (!max_wait_count) { 1008 /* additional check */ 1009 pm8001_dbg(pm8001_ha, FAIL, 1010 "Inb doorbell clear not toggled[value:%x]\n", 1011 value); 1012 return -EBUSY; 1013 } 1014 /* check the MPI-State for initialization upto 100ms*/ 1015 max_wait_count = 5;/* 100 msec */ 1016 do { 1017 msleep(FW_READY_INTERVAL); 1018 gst_len_mpistate = 1019 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1020 GST_GSTLEN_MPIS_OFFSET); 1021 } while ((GST_MPI_STATE_INIT != 1022 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); 1023 if (!max_wait_count) 1024 return -EBUSY; 1025 1026 /* check MPI Initialization error */ 1027 gst_len_mpistate = gst_len_mpistate >> 16; 1028 if (0x0000 != gst_len_mpistate) 1029 return -EBUSY; 1030 1031 return 0; 1032 } 1033 1034 /** 1035 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 1036 * This function sleeps hence it must not be used in atomic context. 1037 * @pm8001_ha: our hba card information 1038 */ 1039 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 1040 { 1041 u32 value; 1042 u32 max_wait_count; 1043 u32 max_wait_time; 1044 u32 expected_mask; 1045 int ret = 0; 1046 1047 /* reset / PCIe ready */ 1048 max_wait_time = max_wait_count = 5; /* 100 milli sec */ 1049 do { 1050 msleep(FW_READY_INTERVAL); 1051 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1052 } while ((value == 0xFFFFFFFF) && (--max_wait_count)); 1053 1054 /* check ila, RAAE and iops status */ 1055 if ((pm8001_ha->chip_id != chip_8008) && 1056 (pm8001_ha->chip_id != chip_8009)) { 1057 max_wait_time = max_wait_count = 180; /* 3600 milli sec */ 1058 expected_mask = SCRATCH_PAD_ILA_READY | 1059 SCRATCH_PAD_RAAE_READY | 1060 SCRATCH_PAD_IOP0_READY | 1061 SCRATCH_PAD_IOP1_READY; 1062 } else { 1063 max_wait_time = max_wait_count = 170; /* 3400 milli sec */ 1064 expected_mask = SCRATCH_PAD_ILA_READY | 1065 SCRATCH_PAD_RAAE_READY | 1066 SCRATCH_PAD_IOP0_READY; 1067 } 1068 do { 1069 msleep(FW_READY_INTERVAL); 1070 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1071 } while (((value & expected_mask) != 1072 expected_mask) && (--max_wait_count)); 1073 if (!max_wait_count) { 1074 pm8001_dbg(pm8001_ha, INIT, 1075 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n", 1076 max_wait_time * FW_READY_INTERVAL, value); 1077 ret = -1; 1078 } else { 1079 pm8001_dbg(pm8001_ha, MSG, 1080 "All FW components ready by %d ms\n", 1081 (max_wait_time - max_wait_count) * FW_READY_INTERVAL); 1082 } 1083 return ret; 1084 } 1085 1086 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 1087 { 1088 void __iomem *base_addr; 1089 u32 value; 1090 u32 offset; 1091 u32 pcibar; 1092 u32 pcilogic; 1093 1094 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1095 1096 /** 1097 * lower 26 bits of SCRATCHPAD0 register describes offset within the 1098 * PCIe BAR where the MPI configuration table is present 1099 */ 1100 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ 1101 1102 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n", 1103 offset, value); 1104 /** 1105 * Upper 6 bits describe the offset within PCI config space where BAR 1106 * is located. 1107 */ 1108 pcilogic = (value & 0xFC000000) >> 26; 1109 pcibar = get_pci_bar_index(pcilogic); 1110 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); 1111 1112 /** 1113 * Make sure the offset falls inside the ioremapped PCI BAR 1114 */ 1115 if (offset > pm8001_ha->io_mem[pcibar].memsize) { 1116 pm8001_dbg(pm8001_ha, FAIL, 1117 "Main cfg tbl offset outside %u > %u\n", 1118 offset, pm8001_ha->io_mem[pcibar].memsize); 1119 return -EBUSY; 1120 } 1121 pm8001_ha->main_cfg_tbl_addr = base_addr = 1122 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 1123 1124 /** 1125 * Validate main configuration table address: first DWord should read 1126 * "PMCS" 1127 */ 1128 value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0); 1129 if (memcmp(&value, "PMCS", 4) != 0) { 1130 pm8001_dbg(pm8001_ha, FAIL, 1131 "BAD main config signature 0x%x\n", 1132 value); 1133 return -EBUSY; 1134 } 1135 pm8001_dbg(pm8001_ha, INIT, 1136 "VALID main config signature 0x%x\n", value); 1137 pm8001_ha->general_stat_tbl_addr = 1138 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 1139 0xFFFFFF); 1140 pm8001_ha->inbnd_q_tbl_addr = 1141 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & 1142 0xFFFFFF); 1143 pm8001_ha->outbnd_q_tbl_addr = 1144 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & 1145 0xFFFFFF); 1146 pm8001_ha->ivt_tbl_addr = 1147 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & 1148 0xFFFFFF); 1149 pm8001_ha->pspa_q_tbl_addr = 1150 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & 1151 0xFFFFFF); 1152 pm8001_ha->fatal_tbl_addr = 1153 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & 1154 0xFFFFFF); 1155 1156 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n", 1157 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)); 1158 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n", 1159 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)); 1160 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n", 1161 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)); 1162 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n", 1163 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)); 1164 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n", 1165 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)); 1166 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n", 1167 pm8001_ha->main_cfg_tbl_addr, 1168 pm8001_ha->general_stat_tbl_addr); 1169 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n", 1170 pm8001_ha->inbnd_q_tbl_addr, 1171 pm8001_ha->outbnd_q_tbl_addr); 1172 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n", 1173 pm8001_ha->pspa_q_tbl_addr, 1174 pm8001_ha->ivt_tbl_addr); 1175 return 0; 1176 } 1177 1178 /** 1179 * pm80xx_set_thermal_config - support the thermal configuration 1180 * @pm8001_ha: our hba card information. 1181 */ 1182 int 1183 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) 1184 { 1185 struct set_ctrl_cfg_req payload; 1186 struct inbound_queue_table *circularQ; 1187 int rc; 1188 u32 tag; 1189 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1190 u32 page_code; 1191 1192 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1193 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1194 if (rc) 1195 return -1; 1196 1197 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1198 payload.tag = cpu_to_le32(tag); 1199 1200 if (IS_SPCV_12G(pm8001_ha->pdev)) 1201 page_code = THERMAL_PAGE_CODE_7H; 1202 else 1203 page_code = THERMAL_PAGE_CODE_8H; 1204 1205 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) | 1206 (THERMAL_ENABLE << 8) | page_code; 1207 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8); 1208 1209 pm8001_dbg(pm8001_ha, DEV, 1210 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n", 1211 payload.cfg_pg[0], payload.cfg_pg[1]); 1212 1213 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1214 sizeof(payload), 0); 1215 if (rc) 1216 pm8001_tag_free(pm8001_ha, tag); 1217 return rc; 1218 1219 } 1220 1221 /** 1222 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol 1223 * Timer configuration page 1224 * @pm8001_ha: our hba card information. 1225 */ 1226 static int 1227 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) 1228 { 1229 struct set_ctrl_cfg_req payload; 1230 struct inbound_queue_table *circularQ; 1231 SASProtocolTimerConfig_t SASConfigPage; 1232 int rc; 1233 u32 tag; 1234 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1235 1236 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1237 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); 1238 1239 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1240 1241 if (rc) 1242 return -1; 1243 1244 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1245 payload.tag = cpu_to_le32(tag); 1246 1247 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE; 1248 SASConfigPage.MST_MSI = 3 << 15; 1249 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO; 1250 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) | 1251 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER; 1252 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME; 1253 1254 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF) 1255 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF; 1256 1257 1258 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) | 1259 SAS_OPNRJT_RTRY_INTVL; 1260 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16) 1261 | SAS_COPNRJT_RTRY_TMO; 1262 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16) 1263 | SAS_COPNRJT_RTRY_THR; 1264 SASConfigPage.MAX_AIP = SAS_MAX_AIP; 1265 1266 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n", 1267 SASConfigPage.pageCode); 1268 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n", 1269 SASConfigPage.MST_MSI); 1270 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n", 1271 SASConfigPage.STP_SSP_MCT_TMO); 1272 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n", 1273 SASConfigPage.STP_FRM_TMO); 1274 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n", 1275 SASConfigPage.STP_IDLE_TMO); 1276 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n", 1277 SASConfigPage.OPNRJT_RTRY_INTVL); 1278 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n", 1279 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO); 1280 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n", 1281 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR); 1282 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n", 1283 SASConfigPage.MAX_AIP); 1284 1285 memcpy(&payload.cfg_pg, &SASConfigPage, 1286 sizeof(SASProtocolTimerConfig_t)); 1287 1288 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1289 sizeof(payload), 0); 1290 if (rc) 1291 pm8001_tag_free(pm8001_ha, tag); 1292 1293 return rc; 1294 } 1295 1296 /** 1297 * pm80xx_get_encrypt_info - Check for encryption 1298 * @pm8001_ha: our hba card information. 1299 */ 1300 static int 1301 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) 1302 { 1303 u32 scratch3_value; 1304 int ret = -1; 1305 1306 /* Read encryption status from SCRATCH PAD 3 */ 1307 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1308 1309 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1310 SCRATCH_PAD3_ENC_READY) { 1311 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1312 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1313 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1314 SCRATCH_PAD3_SMF_ENABLED) 1315 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1316 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1317 SCRATCH_PAD3_SMA_ENABLED) 1318 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1319 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1320 SCRATCH_PAD3_SMB_ENABLED) 1321 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1322 pm8001_ha->encrypt_info.status = 0; 1323 pm8001_dbg(pm8001_ha, INIT, 1324 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", 1325 scratch3_value, 1326 pm8001_ha->encrypt_info.cipher_mode, 1327 pm8001_ha->encrypt_info.sec_mode, 1328 pm8001_ha->encrypt_info.status); 1329 ret = 0; 1330 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == 1331 SCRATCH_PAD3_ENC_DISABLED) { 1332 pm8001_dbg(pm8001_ha, INIT, 1333 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", 1334 scratch3_value); 1335 pm8001_ha->encrypt_info.status = 0xFFFFFFFF; 1336 pm8001_ha->encrypt_info.cipher_mode = 0; 1337 pm8001_ha->encrypt_info.sec_mode = 0; 1338 ret = 0; 1339 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1340 SCRATCH_PAD3_ENC_DIS_ERR) { 1341 pm8001_ha->encrypt_info.status = 1342 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1343 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1344 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1345 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1346 SCRATCH_PAD3_SMF_ENABLED) 1347 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1348 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1349 SCRATCH_PAD3_SMA_ENABLED) 1350 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1351 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1352 SCRATCH_PAD3_SMB_ENABLED) 1353 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1354 pm8001_dbg(pm8001_ha, INIT, 1355 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1356 scratch3_value, 1357 pm8001_ha->encrypt_info.cipher_mode, 1358 pm8001_ha->encrypt_info.sec_mode, 1359 pm8001_ha->encrypt_info.status); 1360 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1361 SCRATCH_PAD3_ENC_ENA_ERR) { 1362 1363 pm8001_ha->encrypt_info.status = 1364 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1365 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1366 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1367 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1368 SCRATCH_PAD3_SMF_ENABLED) 1369 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1370 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1371 SCRATCH_PAD3_SMA_ENABLED) 1372 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1373 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1374 SCRATCH_PAD3_SMB_ENABLED) 1375 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1376 1377 pm8001_dbg(pm8001_ha, INIT, 1378 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1379 scratch3_value, 1380 pm8001_ha->encrypt_info.cipher_mode, 1381 pm8001_ha->encrypt_info.sec_mode, 1382 pm8001_ha->encrypt_info.status); 1383 } 1384 return ret; 1385 } 1386 1387 /** 1388 * pm80xx_encrypt_update - update flash with encryption informtion 1389 * @pm8001_ha: our hba card information. 1390 */ 1391 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) 1392 { 1393 struct kek_mgmt_req payload; 1394 struct inbound_queue_table *circularQ; 1395 int rc; 1396 u32 tag; 1397 u32 opc = OPC_INB_KEK_MANAGEMENT; 1398 1399 memset(&payload, 0, sizeof(struct kek_mgmt_req)); 1400 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1401 if (rc) 1402 return -1; 1403 1404 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1405 payload.tag = cpu_to_le32(tag); 1406 /* Currently only one key is used. New KEK index is 1. 1407 * Current KEK index is 1. Store KEK to NVRAM is 1. 1408 */ 1409 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) | 1410 KEK_MGMT_SUBOP_KEYCARDUPDATE); 1411 1412 pm8001_dbg(pm8001_ha, DEV, 1413 "Saving Encryption info to flash. payload 0x%x\n", 1414 payload.new_curidx_ksop); 1415 1416 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1417 sizeof(payload), 0); 1418 if (rc) 1419 pm8001_tag_free(pm8001_ha, tag); 1420 1421 return rc; 1422 } 1423 1424 /** 1425 * pm80xx_chip_init - the main init function that initialize whole PM8001 chip. 1426 * @pm8001_ha: our hba card information 1427 */ 1428 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) 1429 { 1430 int ret; 1431 u8 i = 0; 1432 1433 /* check the firmware status */ 1434 if (-1 == check_fw_ready(pm8001_ha)) { 1435 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1436 return -EBUSY; 1437 } 1438 1439 /* Initialize the controller fatal error flag */ 1440 pm8001_ha->controller_fatal_error = false; 1441 1442 /* Initialize pci space address eg: mpi offset */ 1443 ret = init_pci_device_addresses(pm8001_ha); 1444 if (ret) { 1445 pm8001_dbg(pm8001_ha, FAIL, 1446 "Failed to init pci addresses"); 1447 return ret; 1448 } 1449 init_default_table_values(pm8001_ha); 1450 read_main_config_table(pm8001_ha); 1451 read_general_status_table(pm8001_ha); 1452 read_inbnd_queue_table(pm8001_ha); 1453 read_outbnd_queue_table(pm8001_ha); 1454 read_phy_attr_table(pm8001_ha); 1455 1456 /* update main config table ,inbound table and outbound table */ 1457 update_main_config_table(pm8001_ha); 1458 for (i = 0; i < pm8001_ha->max_q_num; i++) { 1459 update_inbnd_queue_table(pm8001_ha, i); 1460 update_outbnd_queue_table(pm8001_ha, i); 1461 } 1462 /* notify firmware update finished and check initialization status */ 1463 if (0 == mpi_init_check(pm8001_ha)) { 1464 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n"); 1465 } else 1466 return -EBUSY; 1467 1468 /* send SAS protocol timer configuration page to FW */ 1469 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha); 1470 1471 /* Check for encryption */ 1472 if (pm8001_ha->chip->encrypt) { 1473 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n"); 1474 ret = pm80xx_get_encrypt_info(pm8001_ha); 1475 if (ret == -1) { 1476 pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n"); 1477 if (pm8001_ha->encrypt_info.status == 0x81) { 1478 pm8001_dbg(pm8001_ha, INIT, 1479 "Encryption enabled with error.Saving encryption key to flash\n"); 1480 pm80xx_encrypt_update(pm8001_ha); 1481 } 1482 } 1483 } 1484 return 0; 1485 } 1486 1487 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 1488 { 1489 u32 max_wait_count; 1490 u32 value; 1491 u32 gst_len_mpistate; 1492 int ret; 1493 1494 ret = init_pci_device_addresses(pm8001_ha); 1495 if (ret) { 1496 pm8001_dbg(pm8001_ha, FAIL, 1497 "Failed to init pci addresses"); 1498 return ret; 1499 } 1500 1501 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 1502 table is stop */ 1503 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); 1504 1505 /* wait until Inbound DoorBell Clear Register toggled */ 1506 if (IS_SPCV_12G(pm8001_ha->pdev)) { 1507 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 1508 } else { 1509 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 1510 } 1511 do { 1512 msleep(FW_READY_INTERVAL); 1513 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1514 value &= SPCv_MSGU_CFG_TABLE_RESET; 1515 } while ((value != 0) && (--max_wait_count)); 1516 1517 if (!max_wait_count) { 1518 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value); 1519 return -1; 1520 } 1521 1522 /* check the MPI-State for termination in progress */ 1523 /* wait until Inbound DoorBell Clear Register toggled */ 1524 max_wait_count = 100; /* 2 sec for spcv/ve */ 1525 do { 1526 msleep(FW_READY_INTERVAL); 1527 gst_len_mpistate = 1528 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1529 GST_GSTLEN_MPIS_OFFSET); 1530 if (GST_MPI_STATE_UNINIT == 1531 (gst_len_mpistate & GST_MPI_STATE_MASK)) 1532 break; 1533 } while (--max_wait_count); 1534 if (!max_wait_count) { 1535 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", 1536 gst_len_mpistate & GST_MPI_STATE_MASK); 1537 return -1; 1538 } 1539 1540 return 0; 1541 } 1542 1543 /** 1544 * pm80xx_fatal_errors - returns non zero *ONLY* when fatal errors 1545 * @pm8001_ha: our hba card information 1546 * 1547 * Fatal errors are recoverable only after a host reboot. 1548 */ 1549 int 1550 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha) 1551 { 1552 int ret = 0; 1553 u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0, 1554 MSGU_HOST_SCRATCH_PAD_6); 1555 u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0, 1556 MSGU_HOST_SCRATCH_PAD_7); 1557 u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1558 u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1559 u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1560 1561 if (pm8001_ha->chip_id != chip_8006 && 1562 pm8001_ha->chip_id != chip_8074 && 1563 pm8001_ha->chip_id != chip_8076) { 1564 return 0; 1565 } 1566 1567 if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) { 1568 pm8001_dbg(pm8001_ha, FAIL, 1569 "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n", 1570 scratch_pad1, scratch_pad2, scratch_pad3, 1571 scratch_pad_rsvd0, scratch_pad_rsvd1); 1572 ret = 1; 1573 } 1574 1575 return ret; 1576 } 1577 1578 /** 1579 * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 1580 * the FW register status to the originated status. 1581 * @pm8001_ha: our hba card information 1582 */ 1583 1584 static int 1585 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 1586 { 1587 u32 regval; 1588 u32 bootloader_state; 1589 u32 ibutton0, ibutton1; 1590 1591 /* Process MPI table uninitialization only if FW is ready */ 1592 if (!pm8001_ha->controller_fatal_error) { 1593 /* Check if MPI is in ready state to reset */ 1594 if (mpi_uninit_check(pm8001_ha) != 0) { 1595 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1596 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1597 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1598 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1599 pm8001_dbg(pm8001_ha, FAIL, 1600 "MPI state is not ready scratch: %x:%x:%x:%x\n", 1601 r0, r1, r2, r3); 1602 /* if things aren't ready but the bootloader is ok then 1603 * try the reset anyway. 1604 */ 1605 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK) 1606 return -1; 1607 } 1608 } 1609 /* checked for reset register normal state; 0x0 */ 1610 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1611 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n", 1612 regval); 1613 1614 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); 1615 msleep(500); 1616 1617 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1618 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n", 1619 regval); 1620 1621 if ((regval & SPCv_SOFT_RESET_READ_MASK) == 1622 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { 1623 pm8001_dbg(pm8001_ha, MSG, 1624 " soft reset successful [regval: 0x%x]\n", 1625 regval); 1626 } else { 1627 pm8001_dbg(pm8001_ha, MSG, 1628 " soft reset failed [regval: 0x%x]\n", 1629 regval); 1630 1631 /* check bootloader is successfully executed or in HDA mode */ 1632 bootloader_state = 1633 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1634 SCRATCH_PAD1_BOOTSTATE_MASK; 1635 1636 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { 1637 pm8001_dbg(pm8001_ha, MSG, 1638 "Bootloader state - HDA mode SEEPROM\n"); 1639 } else if (bootloader_state == 1640 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { 1641 pm8001_dbg(pm8001_ha, MSG, 1642 "Bootloader state - HDA mode Bootstrap Pin\n"); 1643 } else if (bootloader_state == 1644 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { 1645 pm8001_dbg(pm8001_ha, MSG, 1646 "Bootloader state - HDA mode soft reset\n"); 1647 } else if (bootloader_state == 1648 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { 1649 pm8001_dbg(pm8001_ha, MSG, 1650 "Bootloader state-HDA mode critical error\n"); 1651 } 1652 return -EBUSY; 1653 } 1654 1655 /* check the firmware status after reset */ 1656 if (-1 == check_fw_ready(pm8001_ha)) { 1657 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1658 /* check iButton feature support for motherboard controller */ 1659 if (pm8001_ha->pdev->subsystem_vendor != 1660 PCI_VENDOR_ID_ADAPTEC2 && 1661 pm8001_ha->pdev->subsystem_vendor != 1662 PCI_VENDOR_ID_ATTO && 1663 pm8001_ha->pdev->subsystem_vendor != 0) { 1664 ibutton0 = pm8001_cr32(pm8001_ha, 0, 1665 MSGU_HOST_SCRATCH_PAD_6); 1666 ibutton1 = pm8001_cr32(pm8001_ha, 0, 1667 MSGU_HOST_SCRATCH_PAD_7); 1668 if (!ibutton0 && !ibutton1) { 1669 pm8001_dbg(pm8001_ha, FAIL, 1670 "iButton Feature is not Available!!!\n"); 1671 return -EBUSY; 1672 } 1673 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { 1674 pm8001_dbg(pm8001_ha, FAIL, 1675 "CRC Check for iButton Feature Failed!!!\n"); 1676 return -EBUSY; 1677 } 1678 } 1679 } 1680 pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n"); 1681 return 0; 1682 } 1683 1684 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1685 { 1686 u32 i; 1687 1688 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n"); 1689 1690 /* do SPCv chip reset. */ 1691 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); 1692 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n"); 1693 1694 /* Check this ..whether delay is required or no */ 1695 /* delay 10 usec */ 1696 udelay(10); 1697 1698 /* wait for 20 msec until the firmware gets reloaded */ 1699 i = 20; 1700 do { 1701 mdelay(1); 1702 } while ((--i) != 0); 1703 1704 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); 1705 } 1706 1707 /** 1708 * pm80xx_chip_intx_interrupt_enable - enable PM8001 chip interrupt 1709 * @pm8001_ha: our hba card information 1710 */ 1711 static void 1712 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1713 { 1714 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1715 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1716 } 1717 1718 /** 1719 * pm80xx_chip_intx_interrupt_disable - disable PM8001 chip interrupt 1720 * @pm8001_ha: our hba card information 1721 */ 1722 static void 1723 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1724 { 1725 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); 1726 } 1727 1728 /** 1729 * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt 1730 * @pm8001_ha: our hba card information 1731 * @vec: interrupt number to enable 1732 */ 1733 static void 1734 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1735 { 1736 #ifdef PM8001_USE_MSIX 1737 u32 mask; 1738 mask = (u32)(1 << vec); 1739 1740 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); 1741 return; 1742 #endif 1743 pm80xx_chip_intx_interrupt_enable(pm8001_ha); 1744 1745 } 1746 1747 /** 1748 * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt 1749 * @pm8001_ha: our hba card information 1750 * @vec: interrupt number to disable 1751 */ 1752 static void 1753 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1754 { 1755 #ifdef PM8001_USE_MSIX 1756 u32 mask; 1757 if (vec == 0xFF) 1758 mask = 0xFFFFFFFF; 1759 else 1760 mask = (u32)(1 << vec); 1761 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); 1762 return; 1763 #endif 1764 pm80xx_chip_intx_interrupt_disable(pm8001_ha); 1765 } 1766 1767 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1768 struct pm8001_device *pm8001_ha_dev) 1769 { 1770 int res; 1771 u32 ccb_tag; 1772 struct pm8001_ccb_info *ccb; 1773 struct sas_task *task = NULL; 1774 struct task_abort_req task_abort; 1775 struct inbound_queue_table *circularQ; 1776 u32 opc = OPC_INB_SATA_ABORT; 1777 int ret; 1778 1779 if (!pm8001_ha_dev) { 1780 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n"); 1781 return; 1782 } 1783 1784 task = sas_alloc_slow_task(GFP_ATOMIC); 1785 1786 if (!task) { 1787 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n"); 1788 return; 1789 } 1790 1791 task->task_done = pm8001_task_done; 1792 1793 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1794 if (res) { 1795 sas_free_task(task); 1796 return; 1797 } 1798 1799 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1800 ccb->device = pm8001_ha_dev; 1801 ccb->ccb_tag = ccb_tag; 1802 ccb->task = task; 1803 1804 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1805 1806 memset(&task_abort, 0, sizeof(task_abort)); 1807 task_abort.abort_all = cpu_to_le32(1); 1808 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1809 task_abort.tag = cpu_to_le32(ccb_tag); 1810 1811 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 1812 sizeof(task_abort), 0); 1813 pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n"); 1814 if (ret) { 1815 sas_free_task(task); 1816 pm8001_tag_free(pm8001_ha, ccb_tag); 1817 } 1818 } 1819 1820 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha, 1821 struct pm8001_device *pm8001_ha_dev) 1822 { 1823 struct sata_start_req sata_cmd; 1824 int res; 1825 u32 ccb_tag; 1826 struct pm8001_ccb_info *ccb; 1827 struct sas_task *task = NULL; 1828 struct host_to_dev_fis fis; 1829 struct domain_device *dev; 1830 struct inbound_queue_table *circularQ; 1831 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1832 1833 task = sas_alloc_slow_task(GFP_ATOMIC); 1834 1835 if (!task) { 1836 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n"); 1837 return; 1838 } 1839 task->task_done = pm8001_task_done; 1840 1841 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1842 if (res) { 1843 sas_free_task(task); 1844 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n"); 1845 return; 1846 } 1847 1848 /* allocate domain device by ourselves as libsas 1849 * is not going to provide any 1850 */ 1851 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1852 if (!dev) { 1853 sas_free_task(task); 1854 pm8001_tag_free(pm8001_ha, ccb_tag); 1855 pm8001_dbg(pm8001_ha, FAIL, 1856 "Domain device cannot be allocated\n"); 1857 return; 1858 } 1859 1860 task->dev = dev; 1861 task->dev->lldd_dev = pm8001_ha_dev; 1862 1863 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1864 ccb->device = pm8001_ha_dev; 1865 ccb->ccb_tag = ccb_tag; 1866 ccb->task = task; 1867 ccb->n_elem = 0; 1868 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1869 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1870 1871 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1872 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1873 1874 /* construct read log FIS */ 1875 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1876 fis.fis_type = 0x27; 1877 fis.flags = 0x80; 1878 fis.command = ATA_CMD_READ_LOG_EXT; 1879 fis.lbal = 0x10; 1880 fis.sector_count = 0x1; 1881 1882 sata_cmd.tag = cpu_to_le32(ccb_tag); 1883 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1884 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9)); 1885 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1886 1887 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 1888 sizeof(sata_cmd), 0); 1889 pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n"); 1890 if (res) { 1891 sas_free_task(task); 1892 pm8001_tag_free(pm8001_ha, ccb_tag); 1893 kfree(dev); 1894 } 1895 } 1896 1897 /** 1898 * mpi_ssp_completion- process the event that FW response to the SSP request. 1899 * @pm8001_ha: our hba card information 1900 * @piomb: the message contents of this outbound message. 1901 * 1902 * When FW has completed a ssp request for example a IO request, after it has 1903 * filled the SG data with the data, it will trigger this event represent 1904 * that he has finished the job,please check the coresponding buffer. 1905 * So we will tell the caller who maybe waiting the result to tell upper layer 1906 * that the task has been finished. 1907 */ 1908 static void 1909 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 1910 { 1911 struct sas_task *t; 1912 struct pm8001_ccb_info *ccb; 1913 unsigned long flags; 1914 u32 status; 1915 u32 param; 1916 u32 tag; 1917 struct ssp_completion_resp *psspPayload; 1918 struct task_status_struct *ts; 1919 struct ssp_response_iu *iu; 1920 struct pm8001_device *pm8001_dev; 1921 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1922 status = le32_to_cpu(psspPayload->status); 1923 tag = le32_to_cpu(psspPayload->tag); 1924 ccb = &pm8001_ha->ccb_info[tag]; 1925 if ((status == IO_ABORTED) && ccb->open_retry) { 1926 /* Being completed by another */ 1927 ccb->open_retry = 0; 1928 return; 1929 } 1930 pm8001_dev = ccb->device; 1931 param = le32_to_cpu(psspPayload->param); 1932 t = ccb->task; 1933 1934 if (status && status != IO_UNDERFLOW) 1935 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); 1936 if (unlikely(!t || !t->lldd_task || !t->dev)) 1937 return; 1938 ts = &t->task_status; 1939 1940 pm8001_dbg(pm8001_ha, DEV, 1941 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t); 1942 1943 /* Print sas address of IO failed device */ 1944 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1945 (status != IO_UNDERFLOW)) 1946 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n", 1947 SAS_ADDR(t->dev->sas_addr)); 1948 1949 switch (status) { 1950 case IO_SUCCESS: 1951 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n", 1952 param); 1953 if (param == 0) { 1954 ts->resp = SAS_TASK_COMPLETE; 1955 ts->stat = SAM_STAT_GOOD; 1956 } else { 1957 ts->resp = SAS_TASK_COMPLETE; 1958 ts->stat = SAS_PROTO_RESPONSE; 1959 ts->residual = param; 1960 iu = &psspPayload->ssp_resp_iu; 1961 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1962 } 1963 if (pm8001_dev) 1964 atomic_dec(&pm8001_dev->running_req); 1965 break; 1966 case IO_ABORTED: 1967 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 1968 ts->resp = SAS_TASK_COMPLETE; 1969 ts->stat = SAS_ABORTED_TASK; 1970 if (pm8001_dev) 1971 atomic_dec(&pm8001_dev->running_req); 1972 break; 1973 case IO_UNDERFLOW: 1974 /* SSP Completion with error */ 1975 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n", 1976 param); 1977 ts->resp = SAS_TASK_COMPLETE; 1978 ts->stat = SAS_DATA_UNDERRUN; 1979 ts->residual = param; 1980 if (pm8001_dev) 1981 atomic_dec(&pm8001_dev->running_req); 1982 break; 1983 case IO_NO_DEVICE: 1984 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 1985 ts->resp = SAS_TASK_UNDELIVERED; 1986 ts->stat = SAS_PHY_DOWN; 1987 if (pm8001_dev) 1988 atomic_dec(&pm8001_dev->running_req); 1989 break; 1990 case IO_XFER_ERROR_BREAK: 1991 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 1992 ts->resp = SAS_TASK_COMPLETE; 1993 ts->stat = SAS_OPEN_REJECT; 1994 /* Force the midlayer to retry */ 1995 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1996 if (pm8001_dev) 1997 atomic_dec(&pm8001_dev->running_req); 1998 break; 1999 case IO_XFER_ERROR_PHY_NOT_READY: 2000 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2001 ts->resp = SAS_TASK_COMPLETE; 2002 ts->stat = SAS_OPEN_REJECT; 2003 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2004 if (pm8001_dev) 2005 atomic_dec(&pm8001_dev->running_req); 2006 break; 2007 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME: 2008 pm8001_dbg(pm8001_ha, IO, 2009 "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"); 2010 ts->resp = SAS_TASK_COMPLETE; 2011 ts->stat = SAS_OPEN_REJECT; 2012 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2013 if (pm8001_dev) 2014 atomic_dec(&pm8001_dev->running_req); 2015 break; 2016 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2017 pm8001_dbg(pm8001_ha, IO, 2018 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2019 ts->resp = SAS_TASK_COMPLETE; 2020 ts->stat = SAS_OPEN_REJECT; 2021 ts->open_rej_reason = SAS_OREJ_EPROTO; 2022 if (pm8001_dev) 2023 atomic_dec(&pm8001_dev->running_req); 2024 break; 2025 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2026 pm8001_dbg(pm8001_ha, IO, 2027 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2028 ts->resp = SAS_TASK_COMPLETE; 2029 ts->stat = SAS_OPEN_REJECT; 2030 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2031 if (pm8001_dev) 2032 atomic_dec(&pm8001_dev->running_req); 2033 break; 2034 case IO_OPEN_CNX_ERROR_BREAK: 2035 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2036 ts->resp = SAS_TASK_COMPLETE; 2037 ts->stat = SAS_OPEN_REJECT; 2038 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2039 if (pm8001_dev) 2040 atomic_dec(&pm8001_dev->running_req); 2041 break; 2042 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2043 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2044 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2045 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2046 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2047 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2048 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2049 ts->resp = SAS_TASK_COMPLETE; 2050 ts->stat = SAS_OPEN_REJECT; 2051 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2052 if (!t->uldd_task) 2053 pm8001_handle_event(pm8001_ha, 2054 pm8001_dev, 2055 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2056 break; 2057 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2058 pm8001_dbg(pm8001_ha, IO, 2059 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2060 ts->resp = SAS_TASK_COMPLETE; 2061 ts->stat = SAS_OPEN_REJECT; 2062 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2063 if (pm8001_dev) 2064 atomic_dec(&pm8001_dev->running_req); 2065 break; 2066 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2067 pm8001_dbg(pm8001_ha, IO, 2068 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2069 ts->resp = SAS_TASK_COMPLETE; 2070 ts->stat = SAS_OPEN_REJECT; 2071 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2072 if (pm8001_dev) 2073 atomic_dec(&pm8001_dev->running_req); 2074 break; 2075 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2076 pm8001_dbg(pm8001_ha, IO, 2077 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2078 ts->resp = SAS_TASK_UNDELIVERED; 2079 ts->stat = SAS_OPEN_REJECT; 2080 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2081 if (pm8001_dev) 2082 atomic_dec(&pm8001_dev->running_req); 2083 break; 2084 case IO_XFER_ERROR_NAK_RECEIVED: 2085 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2086 ts->resp = SAS_TASK_COMPLETE; 2087 ts->stat = SAS_OPEN_REJECT; 2088 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2089 if (pm8001_dev) 2090 atomic_dec(&pm8001_dev->running_req); 2091 break; 2092 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2093 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2094 ts->resp = SAS_TASK_COMPLETE; 2095 ts->stat = SAS_NAK_R_ERR; 2096 if (pm8001_dev) 2097 atomic_dec(&pm8001_dev->running_req); 2098 break; 2099 case IO_XFER_ERROR_DMA: 2100 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2101 ts->resp = SAS_TASK_COMPLETE; 2102 ts->stat = SAS_OPEN_REJECT; 2103 if (pm8001_dev) 2104 atomic_dec(&pm8001_dev->running_req); 2105 break; 2106 case IO_XFER_OPEN_RETRY_TIMEOUT: 2107 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2108 ts->resp = SAS_TASK_COMPLETE; 2109 ts->stat = SAS_OPEN_REJECT; 2110 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2111 if (pm8001_dev) 2112 atomic_dec(&pm8001_dev->running_req); 2113 break; 2114 case IO_XFER_ERROR_OFFSET_MISMATCH: 2115 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2116 ts->resp = SAS_TASK_COMPLETE; 2117 ts->stat = SAS_OPEN_REJECT; 2118 if (pm8001_dev) 2119 atomic_dec(&pm8001_dev->running_req); 2120 break; 2121 case IO_PORT_IN_RESET: 2122 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2123 ts->resp = SAS_TASK_COMPLETE; 2124 ts->stat = SAS_OPEN_REJECT; 2125 if (pm8001_dev) 2126 atomic_dec(&pm8001_dev->running_req); 2127 break; 2128 case IO_DS_NON_OPERATIONAL: 2129 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2130 ts->resp = SAS_TASK_COMPLETE; 2131 ts->stat = SAS_OPEN_REJECT; 2132 if (!t->uldd_task) 2133 pm8001_handle_event(pm8001_ha, 2134 pm8001_dev, 2135 IO_DS_NON_OPERATIONAL); 2136 break; 2137 case IO_DS_IN_RECOVERY: 2138 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2139 ts->resp = SAS_TASK_COMPLETE; 2140 ts->stat = SAS_OPEN_REJECT; 2141 if (pm8001_dev) 2142 atomic_dec(&pm8001_dev->running_req); 2143 break; 2144 case IO_TM_TAG_NOT_FOUND: 2145 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n"); 2146 ts->resp = SAS_TASK_COMPLETE; 2147 ts->stat = SAS_OPEN_REJECT; 2148 if (pm8001_dev) 2149 atomic_dec(&pm8001_dev->running_req); 2150 break; 2151 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 2152 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"); 2153 ts->resp = SAS_TASK_COMPLETE; 2154 ts->stat = SAS_OPEN_REJECT; 2155 if (pm8001_dev) 2156 atomic_dec(&pm8001_dev->running_req); 2157 break; 2158 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2159 pm8001_dbg(pm8001_ha, IO, 2160 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2161 ts->resp = SAS_TASK_COMPLETE; 2162 ts->stat = SAS_OPEN_REJECT; 2163 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2164 if (pm8001_dev) 2165 atomic_dec(&pm8001_dev->running_req); 2166 break; 2167 default: 2168 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2169 /* not allowed case. Therefore, return failed status */ 2170 ts->resp = SAS_TASK_COMPLETE; 2171 ts->stat = SAS_OPEN_REJECT; 2172 if (pm8001_dev) 2173 atomic_dec(&pm8001_dev->running_req); 2174 break; 2175 } 2176 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ", 2177 psspPayload->ssp_resp_iu.status); 2178 spin_lock_irqsave(&t->task_state_lock, flags); 2179 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2180 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2181 t->task_state_flags |= SAS_TASK_STATE_DONE; 2182 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2183 spin_unlock_irqrestore(&t->task_state_lock, flags); 2184 pm8001_dbg(pm8001_ha, FAIL, 2185 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2186 t, status, ts->resp, ts->stat); 2187 if (t->slow_task) 2188 complete(&t->slow_task->completion); 2189 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2190 } else { 2191 spin_unlock_irqrestore(&t->task_state_lock, flags); 2192 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2193 mb();/* in order to force CPU ordering */ 2194 t->task_done(t); 2195 } 2196 } 2197 2198 /*See the comments for mpi_ssp_completion */ 2199 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 2200 { 2201 struct sas_task *t; 2202 unsigned long flags; 2203 struct task_status_struct *ts; 2204 struct pm8001_ccb_info *ccb; 2205 struct pm8001_device *pm8001_dev; 2206 struct ssp_event_resp *psspPayload = 2207 (struct ssp_event_resp *)(piomb + 4); 2208 u32 event = le32_to_cpu(psspPayload->event); 2209 u32 tag = le32_to_cpu(psspPayload->tag); 2210 u32 port_id = le32_to_cpu(psspPayload->port_id); 2211 2212 ccb = &pm8001_ha->ccb_info[tag]; 2213 t = ccb->task; 2214 pm8001_dev = ccb->device; 2215 if (event) 2216 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); 2217 if (unlikely(!t || !t->lldd_task || !t->dev)) 2218 return; 2219 ts = &t->task_status; 2220 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2221 port_id, tag, event); 2222 switch (event) { 2223 case IO_OVERFLOW: 2224 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2225 ts->resp = SAS_TASK_COMPLETE; 2226 ts->stat = SAS_DATA_OVERRUN; 2227 ts->residual = 0; 2228 if (pm8001_dev) 2229 atomic_dec(&pm8001_dev->running_req); 2230 break; 2231 case IO_XFER_ERROR_BREAK: 2232 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2233 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2234 return; 2235 case IO_XFER_ERROR_PHY_NOT_READY: 2236 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2237 ts->resp = SAS_TASK_COMPLETE; 2238 ts->stat = SAS_OPEN_REJECT; 2239 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2240 break; 2241 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2242 pm8001_dbg(pm8001_ha, IO, 2243 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2244 ts->resp = SAS_TASK_COMPLETE; 2245 ts->stat = SAS_OPEN_REJECT; 2246 ts->open_rej_reason = SAS_OREJ_EPROTO; 2247 break; 2248 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2249 pm8001_dbg(pm8001_ha, IO, 2250 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2251 ts->resp = SAS_TASK_COMPLETE; 2252 ts->stat = SAS_OPEN_REJECT; 2253 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2254 break; 2255 case IO_OPEN_CNX_ERROR_BREAK: 2256 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2257 ts->resp = SAS_TASK_COMPLETE; 2258 ts->stat = SAS_OPEN_REJECT; 2259 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2260 break; 2261 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2262 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2263 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2264 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2265 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2266 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2267 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2268 ts->resp = SAS_TASK_COMPLETE; 2269 ts->stat = SAS_OPEN_REJECT; 2270 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2271 if (!t->uldd_task) 2272 pm8001_handle_event(pm8001_ha, 2273 pm8001_dev, 2274 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2275 break; 2276 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2277 pm8001_dbg(pm8001_ha, IO, 2278 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2279 ts->resp = SAS_TASK_COMPLETE; 2280 ts->stat = SAS_OPEN_REJECT; 2281 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2282 break; 2283 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2284 pm8001_dbg(pm8001_ha, IO, 2285 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2286 ts->resp = SAS_TASK_COMPLETE; 2287 ts->stat = SAS_OPEN_REJECT; 2288 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2289 break; 2290 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2291 pm8001_dbg(pm8001_ha, IO, 2292 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2293 ts->resp = SAS_TASK_COMPLETE; 2294 ts->stat = SAS_OPEN_REJECT; 2295 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2296 break; 2297 case IO_XFER_ERROR_NAK_RECEIVED: 2298 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2299 ts->resp = SAS_TASK_COMPLETE; 2300 ts->stat = SAS_OPEN_REJECT; 2301 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2302 break; 2303 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2304 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2305 ts->resp = SAS_TASK_COMPLETE; 2306 ts->stat = SAS_NAK_R_ERR; 2307 break; 2308 case IO_XFER_OPEN_RETRY_TIMEOUT: 2309 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2310 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2311 return; 2312 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2313 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2314 ts->resp = SAS_TASK_COMPLETE; 2315 ts->stat = SAS_DATA_OVERRUN; 2316 break; 2317 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2318 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2319 ts->resp = SAS_TASK_COMPLETE; 2320 ts->stat = SAS_DATA_OVERRUN; 2321 break; 2322 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2323 pm8001_dbg(pm8001_ha, IO, 2324 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2325 ts->resp = SAS_TASK_COMPLETE; 2326 ts->stat = SAS_DATA_OVERRUN; 2327 break; 2328 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2329 pm8001_dbg(pm8001_ha, IO, 2330 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"); 2331 ts->resp = SAS_TASK_COMPLETE; 2332 ts->stat = SAS_DATA_OVERRUN; 2333 break; 2334 case IO_XFER_ERROR_OFFSET_MISMATCH: 2335 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2336 ts->resp = SAS_TASK_COMPLETE; 2337 ts->stat = SAS_DATA_OVERRUN; 2338 break; 2339 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2340 pm8001_dbg(pm8001_ha, IO, 2341 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2342 ts->resp = SAS_TASK_COMPLETE; 2343 ts->stat = SAS_DATA_OVERRUN; 2344 break; 2345 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2346 pm8001_dbg(pm8001_ha, IOERR, 2347 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2348 /* TBC: used default set values */ 2349 ts->resp = SAS_TASK_COMPLETE; 2350 ts->stat = SAS_DATA_OVERRUN; 2351 break; 2352 case IO_XFER_CMD_FRAME_ISSUED: 2353 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2354 return; 2355 default: 2356 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2357 /* not allowed case. Therefore, return failed status */ 2358 ts->resp = SAS_TASK_COMPLETE; 2359 ts->stat = SAS_DATA_OVERRUN; 2360 break; 2361 } 2362 spin_lock_irqsave(&t->task_state_lock, flags); 2363 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2364 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2365 t->task_state_flags |= SAS_TASK_STATE_DONE; 2366 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2367 spin_unlock_irqrestore(&t->task_state_lock, flags); 2368 pm8001_dbg(pm8001_ha, FAIL, 2369 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2370 t, event, ts->resp, ts->stat); 2371 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2372 } else { 2373 spin_unlock_irqrestore(&t->task_state_lock, flags); 2374 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2375 mb();/* in order to force CPU ordering */ 2376 t->task_done(t); 2377 } 2378 } 2379 2380 /*See the comments for mpi_ssp_completion */ 2381 static void 2382 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2383 { 2384 struct sas_task *t; 2385 struct pm8001_ccb_info *ccb; 2386 u32 param; 2387 u32 status; 2388 u32 tag; 2389 int i, j; 2390 u8 sata_addr_low[4]; 2391 u32 temp_sata_addr_low, temp_sata_addr_hi; 2392 u8 sata_addr_hi[4]; 2393 struct sata_completion_resp *psataPayload; 2394 struct task_status_struct *ts; 2395 struct ata_task_resp *resp ; 2396 u32 *sata_resp; 2397 struct pm8001_device *pm8001_dev; 2398 unsigned long flags; 2399 2400 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2401 status = le32_to_cpu(psataPayload->status); 2402 tag = le32_to_cpu(psataPayload->tag); 2403 2404 if (!tag) { 2405 pm8001_dbg(pm8001_ha, FAIL, "tag null\n"); 2406 return; 2407 } 2408 ccb = &pm8001_ha->ccb_info[tag]; 2409 param = le32_to_cpu(psataPayload->param); 2410 if (ccb) { 2411 t = ccb->task; 2412 pm8001_dev = ccb->device; 2413 } else { 2414 pm8001_dbg(pm8001_ha, FAIL, "ccb null\n"); 2415 return; 2416 } 2417 2418 if (t) { 2419 if (t->dev && (t->dev->lldd_dev)) 2420 pm8001_dev = t->dev->lldd_dev; 2421 } else { 2422 pm8001_dbg(pm8001_ha, FAIL, "task null\n"); 2423 return; 2424 } 2425 2426 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2427 && unlikely(!t || !t->lldd_task || !t->dev)) { 2428 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2429 return; 2430 } 2431 2432 ts = &t->task_status; 2433 if (!ts) { 2434 pm8001_dbg(pm8001_ha, FAIL, "ts null\n"); 2435 return; 2436 } 2437 2438 if (status != IO_SUCCESS) { 2439 pm8001_dbg(pm8001_ha, FAIL, 2440 "IO failed device_id %u status 0x%x tag %d\n", 2441 pm8001_dev->device_id, status, tag); 2442 } 2443 2444 /* Print sas address of IO failed device */ 2445 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2446 (status != IO_UNDERFLOW)) { 2447 if (!((t->dev->parent) && 2448 (dev_is_expander(t->dev->parent->dev_type)))) { 2449 for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++) 2450 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2451 for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++) 2452 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2453 memcpy(&temp_sata_addr_low, sata_addr_low, 2454 sizeof(sata_addr_low)); 2455 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2456 sizeof(sata_addr_hi)); 2457 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2458 |((temp_sata_addr_hi << 8) & 2459 0xff0000) | 2460 ((temp_sata_addr_hi >> 8) 2461 & 0xff00) | 2462 ((temp_sata_addr_hi << 24) & 2463 0xff000000)); 2464 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2465 & 0xff) | 2466 ((temp_sata_addr_low << 8) 2467 & 0xff0000) | 2468 ((temp_sata_addr_low >> 8) 2469 & 0xff00) | 2470 ((temp_sata_addr_low << 24) 2471 & 0xff000000)) + 2472 pm8001_dev->attached_phy + 2473 0x10); 2474 pm8001_dbg(pm8001_ha, FAIL, 2475 "SAS Address of IO Failure Drive:%08x%08x\n", 2476 temp_sata_addr_hi, 2477 temp_sata_addr_low); 2478 2479 } else { 2480 pm8001_dbg(pm8001_ha, FAIL, 2481 "SAS Address of IO Failure Drive:%016llx\n", 2482 SAS_ADDR(t->dev->sas_addr)); 2483 } 2484 } 2485 switch (status) { 2486 case IO_SUCCESS: 2487 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2488 if (param == 0) { 2489 ts->resp = SAS_TASK_COMPLETE; 2490 ts->stat = SAM_STAT_GOOD; 2491 /* check if response is for SEND READ LOG */ 2492 if (pm8001_dev && 2493 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2494 /* set new bit for abort_all */ 2495 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2496 /* clear bit for read log */ 2497 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2498 pm80xx_send_abort_all(pm8001_ha, pm8001_dev); 2499 /* Free the tag */ 2500 pm8001_tag_free(pm8001_ha, tag); 2501 sas_free_task(t); 2502 return; 2503 } 2504 } else { 2505 u8 len; 2506 ts->resp = SAS_TASK_COMPLETE; 2507 ts->stat = SAS_PROTO_RESPONSE; 2508 ts->residual = param; 2509 pm8001_dbg(pm8001_ha, IO, 2510 "SAS_PROTO_RESPONSE len = %d\n", 2511 param); 2512 sata_resp = &psataPayload->sata_resp[0]; 2513 resp = (struct ata_task_resp *)ts->buf; 2514 if (t->ata_task.dma_xfer == 0 && 2515 t->data_dir == DMA_FROM_DEVICE) { 2516 len = sizeof(struct pio_setup_fis); 2517 pm8001_dbg(pm8001_ha, IO, 2518 "PIO read len = %d\n", len); 2519 } else if (t->ata_task.use_ncq) { 2520 len = sizeof(struct set_dev_bits_fis); 2521 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n", 2522 len); 2523 } else { 2524 len = sizeof(struct dev_to_host_fis); 2525 pm8001_dbg(pm8001_ha, IO, "other len = %d\n", 2526 len); 2527 } 2528 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2529 resp->frame_len = len; 2530 memcpy(&resp->ending_fis[0], sata_resp, len); 2531 ts->buf_valid_size = sizeof(*resp); 2532 } else 2533 pm8001_dbg(pm8001_ha, IO, 2534 "response too large\n"); 2535 } 2536 if (pm8001_dev) 2537 atomic_dec(&pm8001_dev->running_req); 2538 break; 2539 case IO_ABORTED: 2540 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 2541 ts->resp = SAS_TASK_COMPLETE; 2542 ts->stat = SAS_ABORTED_TASK; 2543 if (pm8001_dev) 2544 atomic_dec(&pm8001_dev->running_req); 2545 break; 2546 /* following cases are to do cases */ 2547 case IO_UNDERFLOW: 2548 /* SATA Completion with error */ 2549 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param); 2550 ts->resp = SAS_TASK_COMPLETE; 2551 ts->stat = SAS_DATA_UNDERRUN; 2552 ts->residual = param; 2553 if (pm8001_dev) 2554 atomic_dec(&pm8001_dev->running_req); 2555 break; 2556 case IO_NO_DEVICE: 2557 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2558 ts->resp = SAS_TASK_UNDELIVERED; 2559 ts->stat = SAS_PHY_DOWN; 2560 if (pm8001_dev) 2561 atomic_dec(&pm8001_dev->running_req); 2562 break; 2563 case IO_XFER_ERROR_BREAK: 2564 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2565 ts->resp = SAS_TASK_COMPLETE; 2566 ts->stat = SAS_INTERRUPTED; 2567 if (pm8001_dev) 2568 atomic_dec(&pm8001_dev->running_req); 2569 break; 2570 case IO_XFER_ERROR_PHY_NOT_READY: 2571 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2572 ts->resp = SAS_TASK_COMPLETE; 2573 ts->stat = SAS_OPEN_REJECT; 2574 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2575 if (pm8001_dev) 2576 atomic_dec(&pm8001_dev->running_req); 2577 break; 2578 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2579 pm8001_dbg(pm8001_ha, IO, 2580 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2581 ts->resp = SAS_TASK_COMPLETE; 2582 ts->stat = SAS_OPEN_REJECT; 2583 ts->open_rej_reason = SAS_OREJ_EPROTO; 2584 if (pm8001_dev) 2585 atomic_dec(&pm8001_dev->running_req); 2586 break; 2587 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2588 pm8001_dbg(pm8001_ha, IO, 2589 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2590 ts->resp = SAS_TASK_COMPLETE; 2591 ts->stat = SAS_OPEN_REJECT; 2592 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2593 if (pm8001_dev) 2594 atomic_dec(&pm8001_dev->running_req); 2595 break; 2596 case IO_OPEN_CNX_ERROR_BREAK: 2597 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2598 ts->resp = SAS_TASK_COMPLETE; 2599 ts->stat = SAS_OPEN_REJECT; 2600 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2601 if (pm8001_dev) 2602 atomic_dec(&pm8001_dev->running_req); 2603 break; 2604 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2605 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2606 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2607 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2608 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2609 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2610 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2611 ts->resp = SAS_TASK_COMPLETE; 2612 ts->stat = SAS_DEV_NO_RESPONSE; 2613 if (!t->uldd_task) { 2614 pm8001_handle_event(pm8001_ha, 2615 pm8001_dev, 2616 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2617 ts->resp = SAS_TASK_UNDELIVERED; 2618 ts->stat = SAS_QUEUE_FULL; 2619 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2620 return; 2621 } 2622 break; 2623 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2624 pm8001_dbg(pm8001_ha, IO, 2625 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2626 ts->resp = SAS_TASK_UNDELIVERED; 2627 ts->stat = SAS_OPEN_REJECT; 2628 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2629 if (!t->uldd_task) { 2630 pm8001_handle_event(pm8001_ha, 2631 pm8001_dev, 2632 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2633 ts->resp = SAS_TASK_UNDELIVERED; 2634 ts->stat = SAS_QUEUE_FULL; 2635 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2636 return; 2637 } 2638 break; 2639 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2640 pm8001_dbg(pm8001_ha, IO, 2641 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2642 ts->resp = SAS_TASK_COMPLETE; 2643 ts->stat = SAS_OPEN_REJECT; 2644 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2645 if (pm8001_dev) 2646 atomic_dec(&pm8001_dev->running_req); 2647 break; 2648 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2649 pm8001_dbg(pm8001_ha, IO, 2650 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"); 2651 ts->resp = SAS_TASK_COMPLETE; 2652 ts->stat = SAS_DEV_NO_RESPONSE; 2653 if (!t->uldd_task) { 2654 pm8001_handle_event(pm8001_ha, 2655 pm8001_dev, 2656 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2657 ts->resp = SAS_TASK_UNDELIVERED; 2658 ts->stat = SAS_QUEUE_FULL; 2659 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2660 return; 2661 } 2662 break; 2663 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2664 pm8001_dbg(pm8001_ha, IO, 2665 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2666 ts->resp = SAS_TASK_COMPLETE; 2667 ts->stat = SAS_OPEN_REJECT; 2668 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2669 if (pm8001_dev) 2670 atomic_dec(&pm8001_dev->running_req); 2671 break; 2672 case IO_XFER_ERROR_NAK_RECEIVED: 2673 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2674 ts->resp = SAS_TASK_COMPLETE; 2675 ts->stat = SAS_NAK_R_ERR; 2676 if (pm8001_dev) 2677 atomic_dec(&pm8001_dev->running_req); 2678 break; 2679 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2680 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2681 ts->resp = SAS_TASK_COMPLETE; 2682 ts->stat = SAS_NAK_R_ERR; 2683 if (pm8001_dev) 2684 atomic_dec(&pm8001_dev->running_req); 2685 break; 2686 case IO_XFER_ERROR_DMA: 2687 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2688 ts->resp = SAS_TASK_COMPLETE; 2689 ts->stat = SAS_ABORTED_TASK; 2690 if (pm8001_dev) 2691 atomic_dec(&pm8001_dev->running_req); 2692 break; 2693 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2694 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"); 2695 ts->resp = SAS_TASK_UNDELIVERED; 2696 ts->stat = SAS_DEV_NO_RESPONSE; 2697 if (pm8001_dev) 2698 atomic_dec(&pm8001_dev->running_req); 2699 break; 2700 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2701 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2702 ts->resp = SAS_TASK_COMPLETE; 2703 ts->stat = SAS_DATA_UNDERRUN; 2704 if (pm8001_dev) 2705 atomic_dec(&pm8001_dev->running_req); 2706 break; 2707 case IO_XFER_OPEN_RETRY_TIMEOUT: 2708 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2709 ts->resp = SAS_TASK_COMPLETE; 2710 ts->stat = SAS_OPEN_TO; 2711 if (pm8001_dev) 2712 atomic_dec(&pm8001_dev->running_req); 2713 break; 2714 case IO_PORT_IN_RESET: 2715 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2716 ts->resp = SAS_TASK_COMPLETE; 2717 ts->stat = SAS_DEV_NO_RESPONSE; 2718 if (pm8001_dev) 2719 atomic_dec(&pm8001_dev->running_req); 2720 break; 2721 case IO_DS_NON_OPERATIONAL: 2722 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2723 ts->resp = SAS_TASK_COMPLETE; 2724 ts->stat = SAS_DEV_NO_RESPONSE; 2725 if (!t->uldd_task) { 2726 pm8001_handle_event(pm8001_ha, pm8001_dev, 2727 IO_DS_NON_OPERATIONAL); 2728 ts->resp = SAS_TASK_UNDELIVERED; 2729 ts->stat = SAS_QUEUE_FULL; 2730 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2731 return; 2732 } 2733 break; 2734 case IO_DS_IN_RECOVERY: 2735 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2736 ts->resp = SAS_TASK_COMPLETE; 2737 ts->stat = SAS_DEV_NO_RESPONSE; 2738 if (pm8001_dev) 2739 atomic_dec(&pm8001_dev->running_req); 2740 break; 2741 case IO_DS_IN_ERROR: 2742 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n"); 2743 ts->resp = SAS_TASK_COMPLETE; 2744 ts->stat = SAS_DEV_NO_RESPONSE; 2745 if (!t->uldd_task) { 2746 pm8001_handle_event(pm8001_ha, pm8001_dev, 2747 IO_DS_IN_ERROR); 2748 ts->resp = SAS_TASK_UNDELIVERED; 2749 ts->stat = SAS_QUEUE_FULL; 2750 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2751 return; 2752 } 2753 break; 2754 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2755 pm8001_dbg(pm8001_ha, IO, 2756 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2757 ts->resp = SAS_TASK_COMPLETE; 2758 ts->stat = SAS_OPEN_REJECT; 2759 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2760 if (pm8001_dev) 2761 atomic_dec(&pm8001_dev->running_req); 2762 break; 2763 default: 2764 pm8001_dbg(pm8001_ha, DEVIO, 2765 "Unknown status device_id %u status 0x%x tag %d\n", 2766 pm8001_dev->device_id, status, tag); 2767 /* not allowed case. Therefore, return failed status */ 2768 ts->resp = SAS_TASK_COMPLETE; 2769 ts->stat = SAS_DEV_NO_RESPONSE; 2770 if (pm8001_dev) 2771 atomic_dec(&pm8001_dev->running_req); 2772 break; 2773 } 2774 spin_lock_irqsave(&t->task_state_lock, flags); 2775 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2776 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2777 t->task_state_flags |= SAS_TASK_STATE_DONE; 2778 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2779 spin_unlock_irqrestore(&t->task_state_lock, flags); 2780 pm8001_dbg(pm8001_ha, FAIL, 2781 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2782 t, status, ts->resp, ts->stat); 2783 if (t->slow_task) 2784 complete(&t->slow_task->completion); 2785 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2786 } else { 2787 spin_unlock_irqrestore(&t->task_state_lock, flags); 2788 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2789 } 2790 } 2791 2792 /*See the comments for mpi_ssp_completion */ 2793 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 2794 { 2795 struct sas_task *t; 2796 struct task_status_struct *ts; 2797 struct pm8001_ccb_info *ccb; 2798 struct pm8001_device *pm8001_dev; 2799 struct sata_event_resp *psataPayload = 2800 (struct sata_event_resp *)(piomb + 4); 2801 u32 event = le32_to_cpu(psataPayload->event); 2802 u32 tag = le32_to_cpu(psataPayload->tag); 2803 u32 port_id = le32_to_cpu(psataPayload->port_id); 2804 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2805 unsigned long flags; 2806 2807 ccb = &pm8001_ha->ccb_info[tag]; 2808 2809 if (ccb) { 2810 t = ccb->task; 2811 pm8001_dev = ccb->device; 2812 } else { 2813 pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n"); 2814 return; 2815 } 2816 if (event) 2817 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); 2818 2819 /* Check if this is NCQ error */ 2820 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2821 /* find device using device id */ 2822 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2823 /* send read log extension */ 2824 if (pm8001_dev) 2825 pm80xx_send_read_log(pm8001_ha, pm8001_dev); 2826 return; 2827 } 2828 2829 if (unlikely(!t || !t->lldd_task || !t->dev)) { 2830 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2831 return; 2832 } 2833 2834 ts = &t->task_status; 2835 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2836 port_id, tag, event); 2837 switch (event) { 2838 case IO_OVERFLOW: 2839 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2840 ts->resp = SAS_TASK_COMPLETE; 2841 ts->stat = SAS_DATA_OVERRUN; 2842 ts->residual = 0; 2843 if (pm8001_dev) 2844 atomic_dec(&pm8001_dev->running_req); 2845 break; 2846 case IO_XFER_ERROR_BREAK: 2847 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2848 ts->resp = SAS_TASK_COMPLETE; 2849 ts->stat = SAS_INTERRUPTED; 2850 break; 2851 case IO_XFER_ERROR_PHY_NOT_READY: 2852 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2853 ts->resp = SAS_TASK_COMPLETE; 2854 ts->stat = SAS_OPEN_REJECT; 2855 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2856 break; 2857 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2858 pm8001_dbg(pm8001_ha, IO, 2859 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2860 ts->resp = SAS_TASK_COMPLETE; 2861 ts->stat = SAS_OPEN_REJECT; 2862 ts->open_rej_reason = SAS_OREJ_EPROTO; 2863 break; 2864 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2865 pm8001_dbg(pm8001_ha, IO, 2866 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2867 ts->resp = SAS_TASK_COMPLETE; 2868 ts->stat = SAS_OPEN_REJECT; 2869 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2870 break; 2871 case IO_OPEN_CNX_ERROR_BREAK: 2872 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2873 ts->resp = SAS_TASK_COMPLETE; 2874 ts->stat = SAS_OPEN_REJECT; 2875 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2876 break; 2877 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2878 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2879 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2880 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2881 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2882 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2883 pm8001_dbg(pm8001_ha, FAIL, 2884 "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2885 ts->resp = SAS_TASK_UNDELIVERED; 2886 ts->stat = SAS_DEV_NO_RESPONSE; 2887 if (!t->uldd_task) { 2888 pm8001_handle_event(pm8001_ha, 2889 pm8001_dev, 2890 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2891 ts->resp = SAS_TASK_COMPLETE; 2892 ts->stat = SAS_QUEUE_FULL; 2893 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2894 return; 2895 } 2896 break; 2897 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2898 pm8001_dbg(pm8001_ha, IO, 2899 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2900 ts->resp = SAS_TASK_UNDELIVERED; 2901 ts->stat = SAS_OPEN_REJECT; 2902 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2903 break; 2904 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2905 pm8001_dbg(pm8001_ha, IO, 2906 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2907 ts->resp = SAS_TASK_COMPLETE; 2908 ts->stat = SAS_OPEN_REJECT; 2909 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2910 break; 2911 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2912 pm8001_dbg(pm8001_ha, IO, 2913 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2914 ts->resp = SAS_TASK_COMPLETE; 2915 ts->stat = SAS_OPEN_REJECT; 2916 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2917 break; 2918 case IO_XFER_ERROR_NAK_RECEIVED: 2919 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2920 ts->resp = SAS_TASK_COMPLETE; 2921 ts->stat = SAS_NAK_R_ERR; 2922 break; 2923 case IO_XFER_ERROR_PEER_ABORTED: 2924 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n"); 2925 ts->resp = SAS_TASK_COMPLETE; 2926 ts->stat = SAS_NAK_R_ERR; 2927 break; 2928 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2929 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2930 ts->resp = SAS_TASK_COMPLETE; 2931 ts->stat = SAS_DATA_UNDERRUN; 2932 break; 2933 case IO_XFER_OPEN_RETRY_TIMEOUT: 2934 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2935 ts->resp = SAS_TASK_COMPLETE; 2936 ts->stat = SAS_OPEN_TO; 2937 break; 2938 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2939 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2940 ts->resp = SAS_TASK_COMPLETE; 2941 ts->stat = SAS_OPEN_TO; 2942 break; 2943 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2944 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2945 ts->resp = SAS_TASK_COMPLETE; 2946 ts->stat = SAS_OPEN_TO; 2947 break; 2948 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2949 pm8001_dbg(pm8001_ha, IO, 2950 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2951 ts->resp = SAS_TASK_COMPLETE; 2952 ts->stat = SAS_OPEN_TO; 2953 break; 2954 case IO_XFER_ERROR_OFFSET_MISMATCH: 2955 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2956 ts->resp = SAS_TASK_COMPLETE; 2957 ts->stat = SAS_OPEN_TO; 2958 break; 2959 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2960 pm8001_dbg(pm8001_ha, IO, 2961 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2962 ts->resp = SAS_TASK_COMPLETE; 2963 ts->stat = SAS_OPEN_TO; 2964 break; 2965 case IO_XFER_CMD_FRAME_ISSUED: 2966 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2967 break; 2968 case IO_XFER_PIO_SETUP_ERROR: 2969 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n"); 2970 ts->resp = SAS_TASK_COMPLETE; 2971 ts->stat = SAS_OPEN_TO; 2972 break; 2973 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2974 pm8001_dbg(pm8001_ha, FAIL, 2975 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2976 /* TBC: used default set values */ 2977 ts->resp = SAS_TASK_COMPLETE; 2978 ts->stat = SAS_OPEN_TO; 2979 break; 2980 case IO_XFER_DMA_ACTIVATE_TIMEOUT: 2981 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n"); 2982 /* TBC: used default set values */ 2983 ts->resp = SAS_TASK_COMPLETE; 2984 ts->stat = SAS_OPEN_TO; 2985 break; 2986 default: 2987 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event); 2988 /* not allowed case. Therefore, return failed status */ 2989 ts->resp = SAS_TASK_COMPLETE; 2990 ts->stat = SAS_OPEN_TO; 2991 break; 2992 } 2993 spin_lock_irqsave(&t->task_state_lock, flags); 2994 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2995 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2996 t->task_state_flags |= SAS_TASK_STATE_DONE; 2997 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2998 spin_unlock_irqrestore(&t->task_state_lock, flags); 2999 pm8001_dbg(pm8001_ha, FAIL, 3000 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 3001 t, event, ts->resp, ts->stat); 3002 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3003 } else { 3004 spin_unlock_irqrestore(&t->task_state_lock, flags); 3005 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 3006 } 3007 } 3008 3009 /*See the comments for mpi_ssp_completion */ 3010 static void 3011 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 3012 { 3013 u32 param, i; 3014 struct sas_task *t; 3015 struct pm8001_ccb_info *ccb; 3016 unsigned long flags; 3017 u32 status; 3018 u32 tag; 3019 struct smp_completion_resp *psmpPayload; 3020 struct task_status_struct *ts; 3021 struct pm8001_device *pm8001_dev; 3022 char *pdma_respaddr = NULL; 3023 3024 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 3025 status = le32_to_cpu(psmpPayload->status); 3026 tag = le32_to_cpu(psmpPayload->tag); 3027 3028 ccb = &pm8001_ha->ccb_info[tag]; 3029 param = le32_to_cpu(psmpPayload->param); 3030 t = ccb->task; 3031 ts = &t->task_status; 3032 pm8001_dev = ccb->device; 3033 if (status) 3034 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); 3035 if (unlikely(!t || !t->lldd_task || !t->dev)) 3036 return; 3037 3038 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status); 3039 3040 switch (status) { 3041 3042 case IO_SUCCESS: 3043 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 3044 ts->resp = SAS_TASK_COMPLETE; 3045 ts->stat = SAM_STAT_GOOD; 3046 if (pm8001_dev) 3047 atomic_dec(&pm8001_dev->running_req); 3048 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 3049 pm8001_dbg(pm8001_ha, IO, 3050 "DIRECT RESPONSE Length:%d\n", 3051 param); 3052 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64 3053 ((u64)sg_dma_address 3054 (&t->smp_task.smp_resp)))); 3055 for (i = 0; i < param; i++) { 3056 *(pdma_respaddr+i) = psmpPayload->_r_a[i]; 3057 pm8001_dbg(pm8001_ha, IO, 3058 "SMP Byte%d DMA data 0x%x psmp 0x%x\n", 3059 i, *(pdma_respaddr + i), 3060 psmpPayload->_r_a[i]); 3061 } 3062 } 3063 break; 3064 case IO_ABORTED: 3065 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n"); 3066 ts->resp = SAS_TASK_COMPLETE; 3067 ts->stat = SAS_ABORTED_TASK; 3068 if (pm8001_dev) 3069 atomic_dec(&pm8001_dev->running_req); 3070 break; 3071 case IO_OVERFLOW: 3072 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 3073 ts->resp = SAS_TASK_COMPLETE; 3074 ts->stat = SAS_DATA_OVERRUN; 3075 ts->residual = 0; 3076 if (pm8001_dev) 3077 atomic_dec(&pm8001_dev->running_req); 3078 break; 3079 case IO_NO_DEVICE: 3080 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 3081 ts->resp = SAS_TASK_COMPLETE; 3082 ts->stat = SAS_PHY_DOWN; 3083 break; 3084 case IO_ERROR_HW_TIMEOUT: 3085 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n"); 3086 ts->resp = SAS_TASK_COMPLETE; 3087 ts->stat = SAM_STAT_BUSY; 3088 break; 3089 case IO_XFER_ERROR_BREAK: 3090 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 3091 ts->resp = SAS_TASK_COMPLETE; 3092 ts->stat = SAM_STAT_BUSY; 3093 break; 3094 case IO_XFER_ERROR_PHY_NOT_READY: 3095 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 3096 ts->resp = SAS_TASK_COMPLETE; 3097 ts->stat = SAM_STAT_BUSY; 3098 break; 3099 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3100 pm8001_dbg(pm8001_ha, IO, 3101 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 3102 ts->resp = SAS_TASK_COMPLETE; 3103 ts->stat = SAS_OPEN_REJECT; 3104 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3105 break; 3106 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3107 pm8001_dbg(pm8001_ha, IO, 3108 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 3109 ts->resp = SAS_TASK_COMPLETE; 3110 ts->stat = SAS_OPEN_REJECT; 3111 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3112 break; 3113 case IO_OPEN_CNX_ERROR_BREAK: 3114 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 3115 ts->resp = SAS_TASK_COMPLETE; 3116 ts->stat = SAS_OPEN_REJECT; 3117 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 3118 break; 3119 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3120 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 3121 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 3122 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 3123 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 3124 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 3125 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 3126 ts->resp = SAS_TASK_COMPLETE; 3127 ts->stat = SAS_OPEN_REJECT; 3128 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3129 pm8001_handle_event(pm8001_ha, 3130 pm8001_dev, 3131 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 3132 break; 3133 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3134 pm8001_dbg(pm8001_ha, IO, 3135 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 3136 ts->resp = SAS_TASK_COMPLETE; 3137 ts->stat = SAS_OPEN_REJECT; 3138 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 3139 break; 3140 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3141 pm8001_dbg(pm8001_ha, IO, 3142 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 3143 ts->resp = SAS_TASK_COMPLETE; 3144 ts->stat = SAS_OPEN_REJECT; 3145 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 3146 break; 3147 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3148 pm8001_dbg(pm8001_ha, IO, 3149 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 3150 ts->resp = SAS_TASK_COMPLETE; 3151 ts->stat = SAS_OPEN_REJECT; 3152 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 3153 break; 3154 case IO_XFER_ERROR_RX_FRAME: 3155 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n"); 3156 ts->resp = SAS_TASK_COMPLETE; 3157 ts->stat = SAS_DEV_NO_RESPONSE; 3158 break; 3159 case IO_XFER_OPEN_RETRY_TIMEOUT: 3160 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 3161 ts->resp = SAS_TASK_COMPLETE; 3162 ts->stat = SAS_OPEN_REJECT; 3163 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3164 break; 3165 case IO_ERROR_INTERNAL_SMP_RESOURCE: 3166 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n"); 3167 ts->resp = SAS_TASK_COMPLETE; 3168 ts->stat = SAS_QUEUE_FULL; 3169 break; 3170 case IO_PORT_IN_RESET: 3171 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 3172 ts->resp = SAS_TASK_COMPLETE; 3173 ts->stat = SAS_OPEN_REJECT; 3174 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3175 break; 3176 case IO_DS_NON_OPERATIONAL: 3177 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 3178 ts->resp = SAS_TASK_COMPLETE; 3179 ts->stat = SAS_DEV_NO_RESPONSE; 3180 break; 3181 case IO_DS_IN_RECOVERY: 3182 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 3183 ts->resp = SAS_TASK_COMPLETE; 3184 ts->stat = SAS_OPEN_REJECT; 3185 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3186 break; 3187 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3188 pm8001_dbg(pm8001_ha, IO, 3189 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 3190 ts->resp = SAS_TASK_COMPLETE; 3191 ts->stat = SAS_OPEN_REJECT; 3192 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3193 break; 3194 default: 3195 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 3196 ts->resp = SAS_TASK_COMPLETE; 3197 ts->stat = SAS_DEV_NO_RESPONSE; 3198 /* not allowed case. Therefore, return failed status */ 3199 break; 3200 } 3201 spin_lock_irqsave(&t->task_state_lock, flags); 3202 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3203 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3204 t->task_state_flags |= SAS_TASK_STATE_DONE; 3205 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3206 spin_unlock_irqrestore(&t->task_state_lock, flags); 3207 pm8001_dbg(pm8001_ha, FAIL, 3208 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n", 3209 t, status, ts->resp, ts->stat); 3210 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3211 } else { 3212 spin_unlock_irqrestore(&t->task_state_lock, flags); 3213 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3214 mb();/* in order to force CPU ordering */ 3215 t->task_done(t); 3216 } 3217 } 3218 3219 /** 3220 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3221 * @pm8001_ha: our hba card information 3222 * @Qnum: the outbound queue message number. 3223 * @SEA: source of event to ack 3224 * @port_id: port id. 3225 * @phyId: phy id. 3226 * @param0: parameter 0. 3227 * @param1: parameter 1. 3228 */ 3229 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3230 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3231 { 3232 struct hw_event_ack_req payload; 3233 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3234 3235 struct inbound_queue_table *circularQ; 3236 3237 memset((u8 *)&payload, 0, sizeof(payload)); 3238 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 3239 payload.tag = cpu_to_le32(1); 3240 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3241 ((phyId & 0xFF) << 24) | (port_id & 0xFF)); 3242 payload.param0 = cpu_to_le32(param0); 3243 payload.param1 = cpu_to_le32(param1); 3244 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 3245 sizeof(payload), 0); 3246 } 3247 3248 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3249 u32 phyId, u32 phy_op); 3250 3251 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha, 3252 void *piomb) 3253 { 3254 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4); 3255 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3256 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3257 u32 lr_status_evt_portid = 3258 le32_to_cpu(pPayload->lr_status_evt_portid); 3259 u8 deviceType = pPayload->sas_identify.dev_type; 3260 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3261 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3262 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3263 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3264 3265 if (deviceType == SAS_END_DEVICE) { 3266 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3267 PHY_NOTIFY_ENABLE_SPINUP); 3268 } 3269 3270 port->wide_port_phymap |= (1U << phy_id); 3271 pm8001_get_lrate_mode(phy, link_rate); 3272 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3273 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3274 phy->phy_attached = 1; 3275 } 3276 3277 /** 3278 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3279 * @pm8001_ha: our hba card information 3280 * @piomb: IO message buffer 3281 */ 3282 static void 3283 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3284 { 3285 struct hw_event_resp *pPayload = 3286 (struct hw_event_resp *)(piomb + 4); 3287 u32 lr_status_evt_portid = 3288 le32_to_cpu(pPayload->lr_status_evt_portid); 3289 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3290 3291 u8 link_rate = 3292 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3293 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3294 u8 phy_id = 3295 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3296 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3297 3298 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3299 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3300 unsigned long flags; 3301 u8 deviceType = pPayload->sas_identify.dev_type; 3302 port->port_state = portstate; 3303 port->wide_port_phymap |= (1U << phy_id); 3304 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3305 pm8001_dbg(pm8001_ha, MSG, 3306 "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n", 3307 port_id, phy_id, link_rate, portstate, deviceType); 3308 3309 switch (deviceType) { 3310 case SAS_PHY_UNUSED: 3311 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n"); 3312 break; 3313 case SAS_END_DEVICE: 3314 pm8001_dbg(pm8001_ha, MSG, "end device.\n"); 3315 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3316 PHY_NOTIFY_ENABLE_SPINUP); 3317 port->port_attached = 1; 3318 pm8001_get_lrate_mode(phy, link_rate); 3319 break; 3320 case SAS_EDGE_EXPANDER_DEVICE: 3321 pm8001_dbg(pm8001_ha, MSG, "expander device.\n"); 3322 port->port_attached = 1; 3323 pm8001_get_lrate_mode(phy, link_rate); 3324 break; 3325 case SAS_FANOUT_EXPANDER_DEVICE: 3326 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n"); 3327 port->port_attached = 1; 3328 pm8001_get_lrate_mode(phy, link_rate); 3329 break; 3330 default: 3331 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n", 3332 deviceType); 3333 break; 3334 } 3335 phy->phy_type |= PORT_TYPE_SAS; 3336 phy->identify.device_type = deviceType; 3337 phy->phy_attached = 1; 3338 if (phy->identify.device_type == SAS_END_DEVICE) 3339 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3340 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3341 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3342 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3343 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3344 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3345 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3346 sizeof(struct sas_identify_frame)-4); 3347 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3348 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3349 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3350 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3351 mdelay(200); /* delay a moment to wait for disk to spin up */ 3352 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3353 } 3354 3355 /** 3356 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3357 * @pm8001_ha: our hba card information 3358 * @piomb: IO message buffer 3359 */ 3360 static void 3361 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3362 { 3363 struct hw_event_resp *pPayload = 3364 (struct hw_event_resp *)(piomb + 4); 3365 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3366 u32 lr_status_evt_portid = 3367 le32_to_cpu(pPayload->lr_status_evt_portid); 3368 u8 link_rate = 3369 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3370 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3371 u8 phy_id = 3372 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3373 3374 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3375 3376 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3377 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3378 unsigned long flags; 3379 pm8001_dbg(pm8001_ha, DEVIO, 3380 "port id %d, phy id %d link_rate %d portstate 0x%x\n", 3381 port_id, phy_id, link_rate, portstate); 3382 3383 port->port_state = portstate; 3384 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3385 port->port_attached = 1; 3386 pm8001_get_lrate_mode(phy, link_rate); 3387 phy->phy_type |= PORT_TYPE_SATA; 3388 phy->phy_attached = 1; 3389 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3390 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3391 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3392 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3393 sizeof(struct dev_to_host_fis)); 3394 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3395 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3396 phy->identify.device_type = SAS_SATA_DEV; 3397 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3398 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3399 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3400 } 3401 3402 /** 3403 * hw_event_phy_down -we should notify the libsas the phy is down. 3404 * @pm8001_ha: our hba card information 3405 * @piomb: IO message buffer 3406 */ 3407 static void 3408 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3409 { 3410 struct hw_event_resp *pPayload = 3411 (struct hw_event_resp *)(piomb + 4); 3412 3413 u32 lr_status_evt_portid = 3414 le32_to_cpu(pPayload->lr_status_evt_portid); 3415 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3416 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3417 u8 phy_id = 3418 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3419 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3420 3421 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3422 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3423 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA); 3424 port->port_state = portstate; 3425 phy->identify.device_type = 0; 3426 phy->phy_attached = 0; 3427 switch (portstate) { 3428 case PORT_VALID: 3429 break; 3430 case PORT_INVALID: 3431 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n", 3432 port_id); 3433 pm8001_dbg(pm8001_ha, MSG, 3434 " Last phy Down and port invalid\n"); 3435 if (port_sata) { 3436 phy->phy_type = 0; 3437 port->port_attached = 0; 3438 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3439 port_id, phy_id, 0, 0); 3440 } 3441 sas_phy_disconnected(&phy->sas_phy); 3442 break; 3443 case PORT_IN_RESET: 3444 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n", 3445 port_id); 3446 break; 3447 case PORT_NOT_ESTABLISHED: 3448 pm8001_dbg(pm8001_ha, MSG, 3449 " Phy Down and PORT_NOT_ESTABLISHED\n"); 3450 port->port_attached = 0; 3451 break; 3452 case PORT_LOSTCOMM: 3453 pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n"); 3454 pm8001_dbg(pm8001_ha, MSG, 3455 " Last phy Down and port invalid\n"); 3456 if (port_sata) { 3457 port->port_attached = 0; 3458 phy->phy_type = 0; 3459 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3460 port_id, phy_id, 0, 0); 3461 } 3462 sas_phy_disconnected(&phy->sas_phy); 3463 break; 3464 default: 3465 port->port_attached = 0; 3466 pm8001_dbg(pm8001_ha, DEVIO, 3467 " Phy Down and(default) = 0x%x\n", 3468 portstate); 3469 break; 3470 3471 } 3472 if (port_sata && (portstate != PORT_IN_RESET)) 3473 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL, 3474 GFP_ATOMIC); 3475 } 3476 3477 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3478 { 3479 struct phy_start_resp *pPayload = 3480 (struct phy_start_resp *)(piomb + 4); 3481 u32 status = 3482 le32_to_cpu(pPayload->status); 3483 u32 phy_id = 3484 le32_to_cpu(pPayload->phyid); 3485 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3486 3487 pm8001_dbg(pm8001_ha, INIT, 3488 "phy start resp status:0x%x, phyid:0x%x\n", 3489 status, phy_id); 3490 if (status == 0) 3491 phy->phy_state = PHY_LINK_DOWN; 3492 3493 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3494 phy->enable_completion != NULL) { 3495 complete(phy->enable_completion); 3496 phy->enable_completion = NULL; 3497 } 3498 return 0; 3499 3500 } 3501 3502 /** 3503 * mpi_thermal_hw_event -The hw event has come. 3504 * @pm8001_ha: our hba card information 3505 * @piomb: IO message buffer 3506 */ 3507 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3508 { 3509 struct thermal_hw_event *pPayload = 3510 (struct thermal_hw_event *)(piomb + 4); 3511 3512 u32 thermal_event = le32_to_cpu(pPayload->thermal_event); 3513 u32 rht_lht = le32_to_cpu(pPayload->rht_lht); 3514 3515 if (thermal_event & 0x40) { 3516 pm8001_dbg(pm8001_ha, IO, 3517 "Thermal Event: Local high temperature violated!\n"); 3518 pm8001_dbg(pm8001_ha, IO, 3519 "Thermal Event: Measured local high temperature %d\n", 3520 ((rht_lht & 0xFF00) >> 8)); 3521 } 3522 if (thermal_event & 0x10) { 3523 pm8001_dbg(pm8001_ha, IO, 3524 "Thermal Event: Remote high temperature violated!\n"); 3525 pm8001_dbg(pm8001_ha, IO, 3526 "Thermal Event: Measured remote high temperature %d\n", 3527 ((rht_lht & 0xFF000000) >> 24)); 3528 } 3529 return 0; 3530 } 3531 3532 /** 3533 * mpi_hw_event -The hw event has come. 3534 * @pm8001_ha: our hba card information 3535 * @piomb: IO message buffer 3536 */ 3537 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3538 { 3539 unsigned long flags, i; 3540 struct hw_event_resp *pPayload = 3541 (struct hw_event_resp *)(piomb + 4); 3542 u32 lr_status_evt_portid = 3543 le32_to_cpu(pPayload->lr_status_evt_portid); 3544 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3545 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3546 u8 phy_id = 3547 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3548 u16 eventType = 3549 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); 3550 u8 status = 3551 (u8)((lr_status_evt_portid & 0x0F000000) >> 24); 3552 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3553 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3554 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3555 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3556 pm8001_dbg(pm8001_ha, DEV, 3557 "portid:%d phyid:%d event:0x%x status:0x%x\n", 3558 port_id, phy_id, eventType, status); 3559 3560 switch (eventType) { 3561 3562 case HW_EVENT_SAS_PHY_UP: 3563 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n"); 3564 hw_event_sas_phy_up(pm8001_ha, piomb); 3565 break; 3566 case HW_EVENT_SATA_PHY_UP: 3567 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n"); 3568 hw_event_sata_phy_up(pm8001_ha, piomb); 3569 break; 3570 case HW_EVENT_SATA_SPINUP_HOLD: 3571 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n"); 3572 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD, 3573 GFP_ATOMIC); 3574 break; 3575 case HW_EVENT_PHY_DOWN: 3576 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n"); 3577 hw_event_phy_down(pm8001_ha, piomb); 3578 if (pm8001_ha->reset_in_progress) { 3579 pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n"); 3580 return 0; 3581 } 3582 phy->phy_attached = 0; 3583 phy->phy_state = PHY_LINK_DISABLE; 3584 break; 3585 case HW_EVENT_PORT_INVALID: 3586 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n"); 3587 sas_phy_disconnected(sas_phy); 3588 phy->phy_attached = 0; 3589 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3590 GFP_ATOMIC); 3591 break; 3592 /* the broadcast change primitive received, tell the LIBSAS this event 3593 to revalidate the sas domain*/ 3594 case HW_EVENT_BROADCAST_CHANGE: 3595 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n"); 3596 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3597 port_id, phy_id, 1, 0); 3598 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3599 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3600 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3601 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3602 GFP_ATOMIC); 3603 break; 3604 case HW_EVENT_PHY_ERROR: 3605 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n"); 3606 sas_phy_disconnected(&phy->sas_phy); 3607 phy->phy_attached = 0; 3608 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC); 3609 break; 3610 case HW_EVENT_BROADCAST_EXP: 3611 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n"); 3612 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3613 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3614 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3615 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3616 GFP_ATOMIC); 3617 break; 3618 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3619 pm8001_dbg(pm8001_ha, MSG, 3620 "HW_EVENT_LINK_ERR_INVALID_DWORD\n"); 3621 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3622 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3623 break; 3624 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3625 pm8001_dbg(pm8001_ha, MSG, 3626 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"); 3627 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3628 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3629 port_id, phy_id, 0, 0); 3630 break; 3631 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3632 pm8001_dbg(pm8001_ha, MSG, 3633 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n"); 3634 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3635 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3636 port_id, phy_id, 0, 0); 3637 break; 3638 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3639 pm8001_dbg(pm8001_ha, MSG, 3640 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"); 3641 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3642 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3643 port_id, phy_id, 0, 0); 3644 break; 3645 case HW_EVENT_MALFUNCTION: 3646 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n"); 3647 break; 3648 case HW_EVENT_BROADCAST_SES: 3649 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n"); 3650 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3651 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3652 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3653 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3654 GFP_ATOMIC); 3655 break; 3656 case HW_EVENT_INBOUND_CRC_ERROR: 3657 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n"); 3658 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3659 HW_EVENT_INBOUND_CRC_ERROR, 3660 port_id, phy_id, 0, 0); 3661 break; 3662 case HW_EVENT_HARD_RESET_RECEIVED: 3663 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n"); 3664 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC); 3665 break; 3666 case HW_EVENT_ID_FRAME_TIMEOUT: 3667 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n"); 3668 sas_phy_disconnected(sas_phy); 3669 phy->phy_attached = 0; 3670 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3671 GFP_ATOMIC); 3672 break; 3673 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3674 pm8001_dbg(pm8001_ha, MSG, 3675 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"); 3676 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3677 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3678 port_id, phy_id, 0, 0); 3679 sas_phy_disconnected(sas_phy); 3680 phy->phy_attached = 0; 3681 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3682 GFP_ATOMIC); 3683 break; 3684 case HW_EVENT_PORT_RESET_TIMER_TMO: 3685 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n"); 3686 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3687 port_id, phy_id, 0, 0); 3688 sas_phy_disconnected(sas_phy); 3689 phy->phy_attached = 0; 3690 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3691 GFP_ATOMIC); 3692 if (pm8001_ha->phy[phy_id].reset_completion) { 3693 pm8001_ha->phy[phy_id].port_reset_status = 3694 PORT_RESET_TMO; 3695 complete(pm8001_ha->phy[phy_id].reset_completion); 3696 pm8001_ha->phy[phy_id].reset_completion = NULL; 3697 } 3698 break; 3699 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3700 pm8001_dbg(pm8001_ha, MSG, 3701 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"); 3702 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3703 HW_EVENT_PORT_RECOVERY_TIMER_TMO, 3704 port_id, phy_id, 0, 0); 3705 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 3706 if (port->wide_port_phymap & (1 << i)) { 3707 phy = &pm8001_ha->phy[i]; 3708 sas_notify_phy_event(&phy->sas_phy, 3709 PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC); 3710 port->wide_port_phymap &= ~(1 << i); 3711 } 3712 } 3713 break; 3714 case HW_EVENT_PORT_RECOVER: 3715 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n"); 3716 hw_event_port_recover(pm8001_ha, piomb); 3717 break; 3718 case HW_EVENT_PORT_RESET_COMPLETE: 3719 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n"); 3720 if (pm8001_ha->phy[phy_id].reset_completion) { 3721 pm8001_ha->phy[phy_id].port_reset_status = 3722 PORT_RESET_SUCCESS; 3723 complete(pm8001_ha->phy[phy_id].reset_completion); 3724 pm8001_ha->phy[phy_id].reset_completion = NULL; 3725 } 3726 break; 3727 case EVENT_BROADCAST_ASYNCH_EVENT: 3728 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n"); 3729 break; 3730 default: 3731 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n", 3732 eventType); 3733 break; 3734 } 3735 return 0; 3736 } 3737 3738 /** 3739 * mpi_phy_stop_resp - SPCv specific 3740 * @pm8001_ha: our hba card information 3741 * @piomb: IO message buffer 3742 */ 3743 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3744 { 3745 struct phy_stop_resp *pPayload = 3746 (struct phy_stop_resp *)(piomb + 4); 3747 u32 status = 3748 le32_to_cpu(pPayload->status); 3749 u32 phyid = 3750 le32_to_cpu(pPayload->phyid) & 0xFF; 3751 struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; 3752 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n", 3753 phyid, status); 3754 if (status == PHY_STOP_SUCCESS || 3755 status == PHY_STOP_ERR_DEVICE_ATTACHED) 3756 phy->phy_state = PHY_LINK_DISABLE; 3757 return 0; 3758 } 3759 3760 /** 3761 * mpi_set_controller_config_resp - SPCv specific 3762 * @pm8001_ha: our hba card information 3763 * @piomb: IO message buffer 3764 */ 3765 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3766 void *piomb) 3767 { 3768 struct set_ctrl_cfg_resp *pPayload = 3769 (struct set_ctrl_cfg_resp *)(piomb + 4); 3770 u32 status = le32_to_cpu(pPayload->status); 3771 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); 3772 3773 pm8001_dbg(pm8001_ha, MSG, 3774 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", 3775 status, err_qlfr_pgcd); 3776 3777 return 0; 3778 } 3779 3780 /** 3781 * mpi_get_controller_config_resp - SPCv specific 3782 * @pm8001_ha: our hba card information 3783 * @piomb: IO message buffer 3784 */ 3785 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3786 void *piomb) 3787 { 3788 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3789 3790 return 0; 3791 } 3792 3793 /** 3794 * mpi_get_phy_profile_resp - SPCv specific 3795 * @pm8001_ha: our hba card information 3796 * @piomb: IO message buffer 3797 */ 3798 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3799 void *piomb) 3800 { 3801 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3802 3803 return 0; 3804 } 3805 3806 /** 3807 * mpi_flash_op_ext_resp - SPCv specific 3808 * @pm8001_ha: our hba card information 3809 * @piomb: IO message buffer 3810 */ 3811 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3812 { 3813 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3814 3815 return 0; 3816 } 3817 3818 /** 3819 * mpi_set_phy_profile_resp - SPCv specific 3820 * @pm8001_ha: our hba card information 3821 * @piomb: IO message buffer 3822 */ 3823 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3824 void *piomb) 3825 { 3826 u32 tag; 3827 u8 page_code; 3828 int rc = 0; 3829 struct set_phy_profile_resp *pPayload = 3830 (struct set_phy_profile_resp *)(piomb + 4); 3831 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); 3832 u32 status = le32_to_cpu(pPayload->status); 3833 3834 tag = le32_to_cpu(pPayload->tag); 3835 page_code = (u8)((ppc_phyid & 0xFF00) >> 8); 3836 if (status) { 3837 /* status is FAILED */ 3838 pm8001_dbg(pm8001_ha, FAIL, 3839 "PhyProfile command failed with status 0x%08X\n", 3840 status); 3841 rc = -1; 3842 } else { 3843 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) { 3844 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n", 3845 page_code); 3846 rc = -1; 3847 } 3848 } 3849 pm8001_tag_free(pm8001_ha, tag); 3850 return rc; 3851 } 3852 3853 /** 3854 * mpi_kek_management_resp - SPCv specific 3855 * @pm8001_ha: our hba card information 3856 * @piomb: IO message buffer 3857 */ 3858 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, 3859 void *piomb) 3860 { 3861 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); 3862 3863 u32 status = le32_to_cpu(pPayload->status); 3864 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); 3865 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); 3866 3867 pm8001_dbg(pm8001_ha, MSG, 3868 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", 3869 status, kidx_new_curr_ksop, err_qlfr); 3870 3871 return 0; 3872 } 3873 3874 /** 3875 * mpi_dek_management_resp - SPCv specific 3876 * @pm8001_ha: our hba card information 3877 * @piomb: IO message buffer 3878 */ 3879 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, 3880 void *piomb) 3881 { 3882 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3883 3884 return 0; 3885 } 3886 3887 /** 3888 * ssp_coalesced_comp_resp - SPCv specific 3889 * @pm8001_ha: our hba card information 3890 * @piomb: IO message buffer 3891 */ 3892 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, 3893 void *piomb) 3894 { 3895 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3896 3897 return 0; 3898 } 3899 3900 /** 3901 * process_one_iomb - process one outbound Queue memory block 3902 * @pm8001_ha: our hba card information 3903 * @piomb: IO message buffer 3904 */ 3905 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3906 { 3907 __le32 pHeader = *(__le32 *)piomb; 3908 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); 3909 3910 switch (opc) { 3911 case OPC_OUB_ECHO: 3912 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n"); 3913 break; 3914 case OPC_OUB_HW_EVENT: 3915 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n"); 3916 mpi_hw_event(pm8001_ha, piomb); 3917 break; 3918 case OPC_OUB_THERM_HW_EVENT: 3919 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n"); 3920 mpi_thermal_hw_event(pm8001_ha, piomb); 3921 break; 3922 case OPC_OUB_SSP_COMP: 3923 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n"); 3924 mpi_ssp_completion(pm8001_ha, piomb); 3925 break; 3926 case OPC_OUB_SMP_COMP: 3927 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n"); 3928 mpi_smp_completion(pm8001_ha, piomb); 3929 break; 3930 case OPC_OUB_LOCAL_PHY_CNTRL: 3931 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n"); 3932 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3933 break; 3934 case OPC_OUB_DEV_REGIST: 3935 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n"); 3936 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3937 break; 3938 case OPC_OUB_DEREG_DEV: 3939 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n"); 3940 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3941 break; 3942 case OPC_OUB_GET_DEV_HANDLE: 3943 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n"); 3944 break; 3945 case OPC_OUB_SATA_COMP: 3946 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n"); 3947 mpi_sata_completion(pm8001_ha, piomb); 3948 break; 3949 case OPC_OUB_SATA_EVENT: 3950 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n"); 3951 mpi_sata_event(pm8001_ha, piomb); 3952 break; 3953 case OPC_OUB_SSP_EVENT: 3954 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n"); 3955 mpi_ssp_event(pm8001_ha, piomb); 3956 break; 3957 case OPC_OUB_DEV_HANDLE_ARRIV: 3958 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n"); 3959 /*This is for target*/ 3960 break; 3961 case OPC_OUB_SSP_RECV_EVENT: 3962 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n"); 3963 /*This is for target*/ 3964 break; 3965 case OPC_OUB_FW_FLASH_UPDATE: 3966 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n"); 3967 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3968 break; 3969 case OPC_OUB_GPIO_RESPONSE: 3970 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n"); 3971 break; 3972 case OPC_OUB_GPIO_EVENT: 3973 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n"); 3974 break; 3975 case OPC_OUB_GENERAL_EVENT: 3976 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n"); 3977 pm8001_mpi_general_event(pm8001_ha, piomb); 3978 break; 3979 case OPC_OUB_SSP_ABORT_RSP: 3980 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n"); 3981 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3982 break; 3983 case OPC_OUB_SATA_ABORT_RSP: 3984 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n"); 3985 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3986 break; 3987 case OPC_OUB_SAS_DIAG_MODE_START_END: 3988 pm8001_dbg(pm8001_ha, MSG, 3989 "OPC_OUB_SAS_DIAG_MODE_START_END\n"); 3990 break; 3991 case OPC_OUB_SAS_DIAG_EXECUTE: 3992 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n"); 3993 break; 3994 case OPC_OUB_GET_TIME_STAMP: 3995 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n"); 3996 break; 3997 case OPC_OUB_SAS_HW_EVENT_ACK: 3998 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n"); 3999 break; 4000 case OPC_OUB_PORT_CONTROL: 4001 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n"); 4002 break; 4003 case OPC_OUB_SMP_ABORT_RSP: 4004 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n"); 4005 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 4006 break; 4007 case OPC_OUB_GET_NVMD_DATA: 4008 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n"); 4009 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 4010 break; 4011 case OPC_OUB_SET_NVMD_DATA: 4012 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n"); 4013 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 4014 break; 4015 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 4016 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n"); 4017 break; 4018 case OPC_OUB_SET_DEVICE_STATE: 4019 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n"); 4020 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 4021 break; 4022 case OPC_OUB_GET_DEVICE_STATE: 4023 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n"); 4024 break; 4025 case OPC_OUB_SET_DEV_INFO: 4026 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n"); 4027 break; 4028 /* spcv specifc commands */ 4029 case OPC_OUB_PHY_START_RESP: 4030 pm8001_dbg(pm8001_ha, MSG, 4031 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc); 4032 mpi_phy_start_resp(pm8001_ha, piomb); 4033 break; 4034 case OPC_OUB_PHY_STOP_RESP: 4035 pm8001_dbg(pm8001_ha, MSG, 4036 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc); 4037 mpi_phy_stop_resp(pm8001_ha, piomb); 4038 break; 4039 case OPC_OUB_SET_CONTROLLER_CONFIG: 4040 pm8001_dbg(pm8001_ha, MSG, 4041 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc); 4042 mpi_set_controller_config_resp(pm8001_ha, piomb); 4043 break; 4044 case OPC_OUB_GET_CONTROLLER_CONFIG: 4045 pm8001_dbg(pm8001_ha, MSG, 4046 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc); 4047 mpi_get_controller_config_resp(pm8001_ha, piomb); 4048 break; 4049 case OPC_OUB_GET_PHY_PROFILE: 4050 pm8001_dbg(pm8001_ha, MSG, 4051 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc); 4052 mpi_get_phy_profile_resp(pm8001_ha, piomb); 4053 break; 4054 case OPC_OUB_FLASH_OP_EXT: 4055 pm8001_dbg(pm8001_ha, MSG, 4056 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc); 4057 mpi_flash_op_ext_resp(pm8001_ha, piomb); 4058 break; 4059 case OPC_OUB_SET_PHY_PROFILE: 4060 pm8001_dbg(pm8001_ha, MSG, 4061 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc); 4062 mpi_set_phy_profile_resp(pm8001_ha, piomb); 4063 break; 4064 case OPC_OUB_KEK_MANAGEMENT_RESP: 4065 pm8001_dbg(pm8001_ha, MSG, 4066 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc); 4067 mpi_kek_management_resp(pm8001_ha, piomb); 4068 break; 4069 case OPC_OUB_DEK_MANAGEMENT_RESP: 4070 pm8001_dbg(pm8001_ha, MSG, 4071 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc); 4072 mpi_dek_management_resp(pm8001_ha, piomb); 4073 break; 4074 case OPC_OUB_SSP_COALESCED_COMP_RESP: 4075 pm8001_dbg(pm8001_ha, MSG, 4076 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc); 4077 ssp_coalesced_comp_resp(pm8001_ha, piomb); 4078 break; 4079 default: 4080 pm8001_dbg(pm8001_ha, DEVIO, 4081 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc); 4082 break; 4083 } 4084 } 4085 4086 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha) 4087 { 4088 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n", 4089 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); 4090 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n", 4091 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)); 4092 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n", 4093 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)); 4094 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n", 4095 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); 4096 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n", 4097 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)); 4098 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n", 4099 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)); 4100 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n", 4101 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)); 4102 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n", 4103 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)); 4104 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n", 4105 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)); 4106 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n", 4107 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)); 4108 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n", 4109 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)); 4110 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n", 4111 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)); 4112 } 4113 4114 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4115 { 4116 struct outbound_queue_table *circularQ; 4117 void *pMsg1 = NULL; 4118 u8 bc; 4119 u32 ret = MPI_IO_STATUS_FAIL; 4120 unsigned long flags; 4121 u32 regval; 4122 4123 if (vec == (pm8001_ha->max_q_num - 1)) { 4124 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 4125 if ((regval & SCRATCH_PAD_MIPSALL_READY) != 4126 SCRATCH_PAD_MIPSALL_READY) { 4127 pm8001_ha->controller_fatal_error = true; 4128 pm8001_dbg(pm8001_ha, FAIL, 4129 "Firmware Fatal error! Regval:0x%x\n", 4130 regval); 4131 pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR); 4132 print_scratchpad_registers(pm8001_ha); 4133 return ret; 4134 } 4135 } 4136 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4137 spin_lock_irqsave(&circularQ->oq_lock, flags); 4138 do { 4139 /* spurious interrupt during setup if kexec-ing and 4140 * driver doing a doorbell access w/ the pre-kexec oq 4141 * interrupt setup. 4142 */ 4143 if (!circularQ->pi_virt) 4144 break; 4145 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4146 if (MPI_IO_STATUS_SUCCESS == ret) { 4147 /* process the outbound message */ 4148 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 4149 /* free the message from the outbound circular buffer */ 4150 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4151 circularQ, bc); 4152 } 4153 if (MPI_IO_STATUS_BUSY == ret) { 4154 /* Update the producer index from SPC */ 4155 circularQ->producer_index = 4156 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4157 if (le32_to_cpu(circularQ->producer_index) == 4158 circularQ->consumer_idx) 4159 /* OQ is empty */ 4160 break; 4161 } 4162 } while (1); 4163 spin_unlock_irqrestore(&circularQ->oq_lock, flags); 4164 return ret; 4165 } 4166 4167 /* DMA_... to our direction translation. */ 4168 static const u8 data_dir_flags[] = { 4169 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4170 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4171 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4172 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4173 }; 4174 4175 static void build_smp_cmd(u32 deviceID, __le32 hTag, 4176 struct smp_req *psmp_cmd, int mode, int length) 4177 { 4178 psmp_cmd->tag = hTag; 4179 psmp_cmd->device_id = cpu_to_le32(deviceID); 4180 if (mode == SMP_DIRECT) { 4181 length = length - 4; /* subtract crc */ 4182 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); 4183 } else { 4184 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4185 } 4186 } 4187 4188 /** 4189 * pm80xx_chip_smp_req - send a SMP task to FW 4190 * @pm8001_ha: our hba card information. 4191 * @ccb: the ccb information this request used. 4192 */ 4193 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4194 struct pm8001_ccb_info *ccb) 4195 { 4196 int elem, rc; 4197 struct sas_task *task = ccb->task; 4198 struct domain_device *dev = task->dev; 4199 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4200 struct scatterlist *sg_req, *sg_resp; 4201 u32 req_len, resp_len; 4202 struct smp_req smp_cmd; 4203 u32 opc; 4204 struct inbound_queue_table *circularQ; 4205 char *preq_dma_addr = NULL; 4206 __le64 tmp_addr; 4207 u32 i, length; 4208 4209 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4210 /* 4211 * DMA-map SMP request, response buffers 4212 */ 4213 sg_req = &task->smp_task.smp_req; 4214 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4215 if (!elem) 4216 return -ENOMEM; 4217 req_len = sg_dma_len(sg_req); 4218 4219 sg_resp = &task->smp_task.smp_resp; 4220 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4221 if (!elem) { 4222 rc = -ENOMEM; 4223 goto err_out; 4224 } 4225 resp_len = sg_dma_len(sg_resp); 4226 /* must be in dwords */ 4227 if ((req_len & 0x3) || (resp_len & 0x3)) { 4228 rc = -EINVAL; 4229 goto err_out_2; 4230 } 4231 4232 opc = OPC_INB_SMP_REQUEST; 4233 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4234 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4235 4236 length = sg_req->length; 4237 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length); 4238 if (!(length - 8)) 4239 pm8001_ha->smp_exp_mode = SMP_DIRECT; 4240 else 4241 pm8001_ha->smp_exp_mode = SMP_INDIRECT; 4242 4243 4244 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 4245 preq_dma_addr = (char *)phys_to_virt(tmp_addr); 4246 4247 /* INDIRECT MODE command settings. Use DMA */ 4248 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { 4249 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n"); 4250 /* for SPCv indirect mode. Place the top 4 bytes of 4251 * SMP Request header here. */ 4252 for (i = 0; i < 4; i++) 4253 smp_cmd.smp_req16[i] = *(preq_dma_addr + i); 4254 /* exclude top 4 bytes for SMP req header */ 4255 smp_cmd.long_smp_req.long_req_addr = 4256 cpu_to_le64((u64)sg_dma_address 4257 (&task->smp_task.smp_req) + 4); 4258 /* exclude 4 bytes for SMP req header and CRC */ 4259 smp_cmd.long_smp_req.long_req_size = 4260 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); 4261 smp_cmd.long_smp_req.long_resp_addr = 4262 cpu_to_le64((u64)sg_dma_address 4263 (&task->smp_task.smp_resp)); 4264 smp_cmd.long_smp_req.long_resp_size = 4265 cpu_to_le32((u32)sg_dma_len 4266 (&task->smp_task.smp_resp)-4); 4267 } else { /* DIRECT MODE */ 4268 smp_cmd.long_smp_req.long_req_addr = 4269 cpu_to_le64((u64)sg_dma_address 4270 (&task->smp_task.smp_req)); 4271 smp_cmd.long_smp_req.long_req_size = 4272 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4273 smp_cmd.long_smp_req.long_resp_addr = 4274 cpu_to_le64((u64)sg_dma_address 4275 (&task->smp_task.smp_resp)); 4276 smp_cmd.long_smp_req.long_resp_size = 4277 cpu_to_le32 4278 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4279 } 4280 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 4281 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n"); 4282 for (i = 0; i < length; i++) 4283 if (i < 16) { 4284 smp_cmd.smp_req16[i] = *(preq_dma_addr+i); 4285 pm8001_dbg(pm8001_ha, IO, 4286 "Byte[%d]:%x (DMA data:%x)\n", 4287 i, smp_cmd.smp_req16[i], 4288 *(preq_dma_addr)); 4289 } else { 4290 smp_cmd.smp_req[i] = *(preq_dma_addr+i); 4291 pm8001_dbg(pm8001_ha, IO, 4292 "Byte[%d]:%x (DMA data:%x)\n", 4293 i, smp_cmd.smp_req[i], 4294 *(preq_dma_addr)); 4295 } 4296 } 4297 4298 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, 4299 &smp_cmd, pm8001_ha->smp_exp_mode, length); 4300 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd, 4301 sizeof(smp_cmd), 0); 4302 if (rc) 4303 goto err_out_2; 4304 return 0; 4305 4306 err_out_2: 4307 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4308 DMA_FROM_DEVICE); 4309 err_out: 4310 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4311 DMA_TO_DEVICE); 4312 return rc; 4313 } 4314 4315 static int check_enc_sas_cmd(struct sas_task *task) 4316 { 4317 u8 cmd = task->ssp_task.cmd->cmnd[0]; 4318 4319 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) 4320 return 1; 4321 else 4322 return 0; 4323 } 4324 4325 static int check_enc_sat_cmd(struct sas_task *task) 4326 { 4327 int ret = 0; 4328 switch (task->ata_task.fis.command) { 4329 case ATA_CMD_FPDMA_READ: 4330 case ATA_CMD_READ_EXT: 4331 case ATA_CMD_READ: 4332 case ATA_CMD_FPDMA_WRITE: 4333 case ATA_CMD_WRITE_EXT: 4334 case ATA_CMD_WRITE: 4335 case ATA_CMD_PIO_READ: 4336 case ATA_CMD_PIO_READ_EXT: 4337 case ATA_CMD_PIO_WRITE: 4338 case ATA_CMD_PIO_WRITE_EXT: 4339 ret = 1; 4340 break; 4341 default: 4342 ret = 0; 4343 break; 4344 } 4345 return ret; 4346 } 4347 4348 /** 4349 * pm80xx_chip_ssp_io_req - send a SSP task to FW 4350 * @pm8001_ha: our hba card information. 4351 * @ccb: the ccb information this request used. 4352 */ 4353 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4354 struct pm8001_ccb_info *ccb) 4355 { 4356 struct sas_task *task = ccb->task; 4357 struct domain_device *dev = task->dev; 4358 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4359 struct ssp_ini_io_start_req ssp_cmd; 4360 u32 tag = ccb->ccb_tag; 4361 int ret; 4362 u64 phys_addr, start_addr, end_addr; 4363 u32 end_addr_high, end_addr_low; 4364 struct inbound_queue_table *circularQ; 4365 u32 q_index, cpu_id; 4366 u32 opc = OPC_INB_SSPINIIOSTART; 4367 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4368 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4369 /* data address domain added for spcv; set to 0 by host, 4370 * used internally by controller 4371 * 0 for SAS 1.1 and SAS 2.0 compatible TLR 4372 */ 4373 ssp_cmd.dad_dir_m_tlr = 4374 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); 4375 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4376 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4377 ssp_cmd.tag = cpu_to_le32(tag); 4378 if (task->ssp_task.enable_first_burst) 4379 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4380 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4381 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4382 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4383 task->ssp_task.cmd->cmd_len); 4384 cpu_id = smp_processor_id(); 4385 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num); 4386 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4387 4388 /* Check if encryption is set */ 4389 if (pm8001_ha->chip->encrypt && 4390 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { 4391 pm8001_dbg(pm8001_ha, IO, 4392 "Encryption enabled.Sending Encrypt SAS command 0x%x\n", 4393 task->ssp_task.cmd->cmnd[0]); 4394 opc = OPC_INB_SSP_INI_DIF_ENC_IO; 4395 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ 4396 ssp_cmd.dad_dir_m_tlr = cpu_to_le32 4397 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); 4398 4399 /* fill in PRD (scatter/gather) table, if any */ 4400 if (task->num_scatter > 1) { 4401 pm8001_chip_make_sg(task->scatter, 4402 ccb->n_elem, ccb->buf_prd); 4403 phys_addr = ccb->ccb_dma_handle; 4404 ssp_cmd.enc_addr_low = 4405 cpu_to_le32(lower_32_bits(phys_addr)); 4406 ssp_cmd.enc_addr_high = 4407 cpu_to_le32(upper_32_bits(phys_addr)); 4408 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4409 } else if (task->num_scatter == 1) { 4410 u64 dma_addr = sg_dma_address(task->scatter); 4411 ssp_cmd.enc_addr_low = 4412 cpu_to_le32(lower_32_bits(dma_addr)); 4413 ssp_cmd.enc_addr_high = 4414 cpu_to_le32(upper_32_bits(dma_addr)); 4415 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4416 ssp_cmd.enc_esgl = 0; 4417 /* Check 4G Boundary */ 4418 start_addr = cpu_to_le64(dma_addr); 4419 end_addr = (start_addr + ssp_cmd.enc_len) - 1; 4420 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4421 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4422 if (end_addr_high != ssp_cmd.enc_addr_high) { 4423 pm8001_dbg(pm8001_ha, FAIL, 4424 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4425 start_addr, ssp_cmd.enc_len, 4426 end_addr_high, end_addr_low); 4427 pm8001_chip_make_sg(task->scatter, 1, 4428 ccb->buf_prd); 4429 phys_addr = ccb->ccb_dma_handle; 4430 ssp_cmd.enc_addr_low = 4431 cpu_to_le32(lower_32_bits(phys_addr)); 4432 ssp_cmd.enc_addr_high = 4433 cpu_to_le32(upper_32_bits(phys_addr)); 4434 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4435 } 4436 } else if (task->num_scatter == 0) { 4437 ssp_cmd.enc_addr_low = 0; 4438 ssp_cmd.enc_addr_high = 0; 4439 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4440 ssp_cmd.enc_esgl = 0; 4441 } 4442 /* XTS mode. All other fields are 0 */ 4443 ssp_cmd.key_cmode = 0x6 << 4; 4444 /* set tweak values. Should be the start lba */ 4445 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | 4446 (task->ssp_task.cmd->cmnd[3] << 16) | 4447 (task->ssp_task.cmd->cmnd[4] << 8) | 4448 (task->ssp_task.cmd->cmnd[5])); 4449 } else { 4450 pm8001_dbg(pm8001_ha, IO, 4451 "Sending Normal SAS command 0x%x inb q %x\n", 4452 task->ssp_task.cmd->cmnd[0], q_index); 4453 /* fill in PRD (scatter/gather) table, if any */ 4454 if (task->num_scatter > 1) { 4455 pm8001_chip_make_sg(task->scatter, ccb->n_elem, 4456 ccb->buf_prd); 4457 phys_addr = ccb->ccb_dma_handle; 4458 ssp_cmd.addr_low = 4459 cpu_to_le32(lower_32_bits(phys_addr)); 4460 ssp_cmd.addr_high = 4461 cpu_to_le32(upper_32_bits(phys_addr)); 4462 ssp_cmd.esgl = cpu_to_le32(1<<31); 4463 } else if (task->num_scatter == 1) { 4464 u64 dma_addr = sg_dma_address(task->scatter); 4465 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4466 ssp_cmd.addr_high = 4467 cpu_to_le32(upper_32_bits(dma_addr)); 4468 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4469 ssp_cmd.esgl = 0; 4470 /* Check 4G Boundary */ 4471 start_addr = cpu_to_le64(dma_addr); 4472 end_addr = (start_addr + ssp_cmd.len) - 1; 4473 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4474 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4475 if (end_addr_high != ssp_cmd.addr_high) { 4476 pm8001_dbg(pm8001_ha, FAIL, 4477 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4478 start_addr, ssp_cmd.len, 4479 end_addr_high, end_addr_low); 4480 pm8001_chip_make_sg(task->scatter, 1, 4481 ccb->buf_prd); 4482 phys_addr = ccb->ccb_dma_handle; 4483 ssp_cmd.addr_low = 4484 cpu_to_le32(lower_32_bits(phys_addr)); 4485 ssp_cmd.addr_high = 4486 cpu_to_le32(upper_32_bits(phys_addr)); 4487 ssp_cmd.esgl = cpu_to_le32(1<<31); 4488 } 4489 } else if (task->num_scatter == 0) { 4490 ssp_cmd.addr_low = 0; 4491 ssp_cmd.addr_high = 0; 4492 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4493 ssp_cmd.esgl = 0; 4494 } 4495 } 4496 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4497 &ssp_cmd, sizeof(ssp_cmd), q_index); 4498 return ret; 4499 } 4500 4501 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4502 struct pm8001_ccb_info *ccb) 4503 { 4504 struct sas_task *task = ccb->task; 4505 struct domain_device *dev = task->dev; 4506 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4507 u32 tag = ccb->ccb_tag; 4508 int ret; 4509 u32 q_index, cpu_id; 4510 struct sata_start_req sata_cmd; 4511 u32 hdr_tag, ncg_tag = 0; 4512 u64 phys_addr, start_addr, end_addr; 4513 u32 end_addr_high, end_addr_low; 4514 u32 ATAP = 0x0; 4515 u32 dir; 4516 struct inbound_queue_table *circularQ; 4517 unsigned long flags; 4518 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4519 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4520 cpu_id = smp_processor_id(); 4521 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num); 4522 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4523 4524 if (task->data_dir == DMA_NONE) { 4525 ATAP = 0x04; /* no data*/ 4526 pm8001_dbg(pm8001_ha, IO, "no data\n"); 4527 } else if (likely(!task->ata_task.device_control_reg_update)) { 4528 if (task->ata_task.dma_xfer) { 4529 ATAP = 0x06; /* DMA */ 4530 pm8001_dbg(pm8001_ha, IO, "DMA\n"); 4531 } else { 4532 ATAP = 0x05; /* PIO*/ 4533 pm8001_dbg(pm8001_ha, IO, "PIO\n"); 4534 } 4535 if (task->ata_task.use_ncq && 4536 dev->sata_dev.class != ATA_DEV_ATAPI) { 4537 ATAP = 0x07; /* FPDMA */ 4538 pm8001_dbg(pm8001_ha, IO, "FPDMA\n"); 4539 } 4540 } 4541 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4542 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4543 ncg_tag = hdr_tag; 4544 } 4545 dir = data_dir_flags[task->data_dir] << 8; 4546 sata_cmd.tag = cpu_to_le32(tag); 4547 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4548 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4549 4550 sata_cmd.sata_fis = task->ata_task.fis; 4551 if (likely(!task->ata_task.device_control_reg_update)) 4552 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4553 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4554 4555 /* Check if encryption is set */ 4556 if (pm8001_ha->chip->encrypt && 4557 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { 4558 pm8001_dbg(pm8001_ha, IO, 4559 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", 4560 sata_cmd.sata_fis.command); 4561 opc = OPC_INB_SATA_DIF_ENC_IO; 4562 4563 /* set encryption bit */ 4564 sata_cmd.ncqtag_atap_dir_m_dad = 4565 cpu_to_le32(((ncg_tag & 0xff)<<16)| 4566 ((ATAP & 0x3f) << 10) | 0x20 | dir); 4567 /* dad (bit 0-1) is 0 */ 4568 /* fill in PRD (scatter/gather) table, if any */ 4569 if (task->num_scatter > 1) { 4570 pm8001_chip_make_sg(task->scatter, 4571 ccb->n_elem, ccb->buf_prd); 4572 phys_addr = ccb->ccb_dma_handle; 4573 sata_cmd.enc_addr_low = lower_32_bits(phys_addr); 4574 sata_cmd.enc_addr_high = upper_32_bits(phys_addr); 4575 sata_cmd.enc_esgl = cpu_to_le32(1 << 31); 4576 } else if (task->num_scatter == 1) { 4577 u64 dma_addr = sg_dma_address(task->scatter); 4578 sata_cmd.enc_addr_low = lower_32_bits(dma_addr); 4579 sata_cmd.enc_addr_high = upper_32_bits(dma_addr); 4580 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4581 sata_cmd.enc_esgl = 0; 4582 /* Check 4G Boundary */ 4583 start_addr = cpu_to_le64(dma_addr); 4584 end_addr = (start_addr + sata_cmd.enc_len) - 1; 4585 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4586 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4587 if (end_addr_high != sata_cmd.enc_addr_high) { 4588 pm8001_dbg(pm8001_ha, FAIL, 4589 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4590 start_addr, sata_cmd.enc_len, 4591 end_addr_high, end_addr_low); 4592 pm8001_chip_make_sg(task->scatter, 1, 4593 ccb->buf_prd); 4594 phys_addr = ccb->ccb_dma_handle; 4595 sata_cmd.enc_addr_low = 4596 lower_32_bits(phys_addr); 4597 sata_cmd.enc_addr_high = 4598 upper_32_bits(phys_addr); 4599 sata_cmd.enc_esgl = 4600 cpu_to_le32(1 << 31); 4601 } 4602 } else if (task->num_scatter == 0) { 4603 sata_cmd.enc_addr_low = 0; 4604 sata_cmd.enc_addr_high = 0; 4605 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4606 sata_cmd.enc_esgl = 0; 4607 } 4608 /* XTS mode. All other fields are 0 */ 4609 sata_cmd.key_index_mode = 0x6 << 4; 4610 /* set tweak values. Should be the start lba */ 4611 sata_cmd.twk_val0 = 4612 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | 4613 (sata_cmd.sata_fis.lbah << 16) | 4614 (sata_cmd.sata_fis.lbam << 8) | 4615 (sata_cmd.sata_fis.lbal)); 4616 sata_cmd.twk_val1 = 4617 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | 4618 (sata_cmd.sata_fis.lbam_exp)); 4619 } else { 4620 pm8001_dbg(pm8001_ha, IO, 4621 "Sending Normal SATA command 0x%x inb %x\n", 4622 sata_cmd.sata_fis.command, q_index); 4623 /* dad (bit 0-1) is 0 */ 4624 sata_cmd.ncqtag_atap_dir_m_dad = 4625 cpu_to_le32(((ncg_tag & 0xff)<<16) | 4626 ((ATAP & 0x3f) << 10) | dir); 4627 4628 /* fill in PRD (scatter/gather) table, if any */ 4629 if (task->num_scatter > 1) { 4630 pm8001_chip_make_sg(task->scatter, 4631 ccb->n_elem, ccb->buf_prd); 4632 phys_addr = ccb->ccb_dma_handle; 4633 sata_cmd.addr_low = lower_32_bits(phys_addr); 4634 sata_cmd.addr_high = upper_32_bits(phys_addr); 4635 sata_cmd.esgl = cpu_to_le32(1 << 31); 4636 } else if (task->num_scatter == 1) { 4637 u64 dma_addr = sg_dma_address(task->scatter); 4638 sata_cmd.addr_low = lower_32_bits(dma_addr); 4639 sata_cmd.addr_high = upper_32_bits(dma_addr); 4640 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4641 sata_cmd.esgl = 0; 4642 /* Check 4G Boundary */ 4643 start_addr = cpu_to_le64(dma_addr); 4644 end_addr = (start_addr + sata_cmd.len) - 1; 4645 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4646 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4647 if (end_addr_high != sata_cmd.addr_high) { 4648 pm8001_dbg(pm8001_ha, FAIL, 4649 "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4650 start_addr, sata_cmd.len, 4651 end_addr_high, end_addr_low); 4652 pm8001_chip_make_sg(task->scatter, 1, 4653 ccb->buf_prd); 4654 phys_addr = ccb->ccb_dma_handle; 4655 sata_cmd.addr_low = 4656 lower_32_bits(phys_addr); 4657 sata_cmd.addr_high = 4658 upper_32_bits(phys_addr); 4659 sata_cmd.esgl = cpu_to_le32(1 << 31); 4660 } 4661 } else if (task->num_scatter == 0) { 4662 sata_cmd.addr_low = 0; 4663 sata_cmd.addr_high = 0; 4664 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4665 sata_cmd.esgl = 0; 4666 } 4667 /* scsi cdb */ 4668 sata_cmd.atapi_scsi_cdb[0] = 4669 cpu_to_le32(((task->ata_task.atapi_packet[0]) | 4670 (task->ata_task.atapi_packet[1] << 8) | 4671 (task->ata_task.atapi_packet[2] << 16) | 4672 (task->ata_task.atapi_packet[3] << 24))); 4673 sata_cmd.atapi_scsi_cdb[1] = 4674 cpu_to_le32(((task->ata_task.atapi_packet[4]) | 4675 (task->ata_task.atapi_packet[5] << 8) | 4676 (task->ata_task.atapi_packet[6] << 16) | 4677 (task->ata_task.atapi_packet[7] << 24))); 4678 sata_cmd.atapi_scsi_cdb[2] = 4679 cpu_to_le32(((task->ata_task.atapi_packet[8]) | 4680 (task->ata_task.atapi_packet[9] << 8) | 4681 (task->ata_task.atapi_packet[10] << 16) | 4682 (task->ata_task.atapi_packet[11] << 24))); 4683 sata_cmd.atapi_scsi_cdb[3] = 4684 cpu_to_le32(((task->ata_task.atapi_packet[12]) | 4685 (task->ata_task.atapi_packet[13] << 8) | 4686 (task->ata_task.atapi_packet[14] << 16) | 4687 (task->ata_task.atapi_packet[15] << 24))); 4688 } 4689 4690 /* Check for read log for failed drive and return */ 4691 if (sata_cmd.sata_fis.command == 0x2f) { 4692 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4693 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4694 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4695 struct task_status_struct *ts; 4696 4697 pm8001_ha_dev->id &= 0xDFFFFFFF; 4698 ts = &task->task_status; 4699 4700 spin_lock_irqsave(&task->task_state_lock, flags); 4701 ts->resp = SAS_TASK_COMPLETE; 4702 ts->stat = SAM_STAT_GOOD; 4703 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4704 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4705 task->task_state_flags |= SAS_TASK_STATE_DONE; 4706 if (unlikely((task->task_state_flags & 4707 SAS_TASK_STATE_ABORTED))) { 4708 spin_unlock_irqrestore(&task->task_state_lock, 4709 flags); 4710 pm8001_dbg(pm8001_ha, FAIL, 4711 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n", 4712 task, ts->resp, 4713 ts->stat); 4714 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4715 return 0; 4716 } else { 4717 spin_unlock_irqrestore(&task->task_state_lock, 4718 flags); 4719 pm8001_ccb_task_free_done(pm8001_ha, task, 4720 ccb, tag); 4721 atomic_dec(&pm8001_ha_dev->running_req); 4722 return 0; 4723 } 4724 } 4725 } 4726 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4727 &sata_cmd, sizeof(sata_cmd), q_index); 4728 return ret; 4729 } 4730 4731 /** 4732 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND 4733 * @pm8001_ha: our hba card information. 4734 * @phy_id: the phy id which we wanted to start up. 4735 */ 4736 static int 4737 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4738 { 4739 struct phy_start_req payload; 4740 struct inbound_queue_table *circularQ; 4741 int ret; 4742 u32 tag = 0x01; 4743 u32 opcode = OPC_INB_PHYSTART; 4744 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4745 memset(&payload, 0, sizeof(payload)); 4746 payload.tag = cpu_to_le32(tag); 4747 4748 pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id); 4749 4750 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4751 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id); 4752 /* SSC Disable and SAS Analog ST configuration */ 4753 /** 4754 payload.ase_sh_lm_slr_phyid = 4755 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | 4756 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | 4757 phy_id); 4758 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need 4759 **/ 4760 4761 payload.sas_identify.dev_type = SAS_END_DEVICE; 4762 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4763 memcpy(payload.sas_identify.sas_addr, 4764 &pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4765 payload.sas_identify.phy_id = phy_id; 4766 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4767 sizeof(payload), 0); 4768 return ret; 4769 } 4770 4771 /** 4772 * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4773 * @pm8001_ha: our hba card information. 4774 * @phy_id: the phy id which we wanted to start up. 4775 */ 4776 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4777 u8 phy_id) 4778 { 4779 struct phy_stop_req payload; 4780 struct inbound_queue_table *circularQ; 4781 int ret; 4782 u32 tag = 0x01; 4783 u32 opcode = OPC_INB_PHYSTOP; 4784 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4785 memset(&payload, 0, sizeof(payload)); 4786 payload.tag = cpu_to_le32(tag); 4787 payload.phy_id = cpu_to_le32(phy_id); 4788 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4789 sizeof(payload), 0); 4790 return ret; 4791 } 4792 4793 /* 4794 * see comments on pm8001_mpi_reg_resp. 4795 */ 4796 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4797 struct pm8001_device *pm8001_dev, u32 flag) 4798 { 4799 struct reg_dev_req payload; 4800 u32 opc; 4801 u32 stp_sspsmp_sata = 0x4; 4802 struct inbound_queue_table *circularQ; 4803 u32 linkrate, phy_id; 4804 int rc, tag = 0xdeadbeef; 4805 struct pm8001_ccb_info *ccb; 4806 u8 retryFlag = 0x1; 4807 u16 firstBurstSize = 0; 4808 u16 ITNT = 2000; 4809 struct domain_device *dev = pm8001_dev->sas_device; 4810 struct domain_device *parent_dev = dev->parent; 4811 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4812 4813 memset(&payload, 0, sizeof(payload)); 4814 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4815 if (rc) 4816 return rc; 4817 ccb = &pm8001_ha->ccb_info[tag]; 4818 ccb->device = pm8001_dev; 4819 ccb->ccb_tag = tag; 4820 payload.tag = cpu_to_le32(tag); 4821 4822 if (flag == 1) { 4823 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4824 } else { 4825 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4826 stp_sspsmp_sata = 0x00; /* stp*/ 4827 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4828 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4829 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4830 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4831 } 4832 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4833 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4834 else 4835 phy_id = pm8001_dev->attached_phy; 4836 4837 opc = OPC_INB_REG_DEV; 4838 4839 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4840 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4841 4842 payload.phyid_portid = 4843 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) | 4844 ((phy_id & 0xFF) << 8)); 4845 4846 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | 4847 ((linkrate & 0x0F) << 24) | 4848 ((stp_sspsmp_sata & 0x03) << 28)); 4849 payload.firstburstsize_ITNexustimeout = 4850 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4851 4852 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4853 SAS_ADDR_SIZE); 4854 4855 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4856 sizeof(payload), 0); 4857 if (rc) 4858 pm8001_tag_free(pm8001_ha, tag); 4859 4860 return rc; 4861 } 4862 4863 /** 4864 * pm80xx_chip_phy_ctl_req - support the local phy operation 4865 * @pm8001_ha: our hba card information. 4866 * @phyId: the phy id which we wanted to operate 4867 * @phy_op: phy operation to request 4868 */ 4869 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4870 u32 phyId, u32 phy_op) 4871 { 4872 u32 tag; 4873 int rc; 4874 struct local_phy_ctl_req payload; 4875 struct inbound_queue_table *circularQ; 4876 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4877 memset(&payload, 0, sizeof(payload)); 4878 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4879 if (rc) 4880 return rc; 4881 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4882 payload.tag = cpu_to_le32(tag); 4883 payload.phyop_phyid = 4884 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); 4885 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4886 sizeof(payload), 0); 4887 } 4888 4889 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4890 { 4891 #ifdef PM8001_USE_MSIX 4892 return 1; 4893 #else 4894 u32 value; 4895 4896 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4897 if (value) 4898 return 1; 4899 return 0; 4900 #endif 4901 } 4902 4903 /** 4904 * pm80xx_chip_isr - PM8001 isr handler. 4905 * @pm8001_ha: our hba card information. 4906 * @vec: irq number. 4907 */ 4908 static irqreturn_t 4909 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4910 { 4911 pm80xx_chip_interrupt_disable(pm8001_ha, vec); 4912 pm8001_dbg(pm8001_ha, DEVIO, 4913 "irq vec %d, ODMR:0x%x\n", 4914 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); 4915 process_oq(pm8001_ha, vec); 4916 pm80xx_chip_interrupt_enable(pm8001_ha, vec); 4917 return IRQ_HANDLED; 4918 } 4919 4920 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha, 4921 u32 operation, u32 phyid, 4922 u32 length, u32 *buf) 4923 { 4924 u32 tag, i, j = 0; 4925 int rc; 4926 struct set_phy_profile_req payload; 4927 struct inbound_queue_table *circularQ; 4928 u32 opc = OPC_INB_SET_PHY_PROFILE; 4929 4930 memset(&payload, 0, sizeof(payload)); 4931 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4932 if (rc) 4933 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n"); 4934 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4935 payload.tag = cpu_to_le32(tag); 4936 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF)); 4937 pm8001_dbg(pm8001_ha, INIT, 4938 " phy profile command for phy %x ,length is %d\n", 4939 payload.ppc_phyid, length); 4940 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { 4941 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i)); 4942 j++; 4943 } 4944 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4945 sizeof(payload), 0); 4946 if (rc) 4947 pm8001_tag_free(pm8001_ha, tag); 4948 } 4949 4950 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 4951 u32 length, u8 *buf) 4952 { 4953 u32 i; 4954 4955 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 4956 mpi_set_phy_profile_req(pm8001_ha, 4957 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf); 4958 length = length + PHY_DWORD_LENGTH; 4959 } 4960 pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n"); 4961 } 4962 4963 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, 4964 u32 phy, u32 length, u32 *buf) 4965 { 4966 u32 tag, opc; 4967 int rc, i; 4968 struct set_phy_profile_req payload; 4969 struct inbound_queue_table *circularQ; 4970 4971 memset(&payload, 0, sizeof(payload)); 4972 4973 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4974 if (rc) 4975 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n"); 4976 4977 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4978 opc = OPC_INB_SET_PHY_PROFILE; 4979 4980 payload.tag = cpu_to_le32(tag); 4981 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8) 4982 | (phy & 0xFF)); 4983 4984 for (i = 0; i < length; i++) 4985 payload.reserved[i] = cpu_to_le32(*(buf + i)); 4986 4987 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4988 sizeof(payload), 0); 4989 if (rc) 4990 pm8001_tag_free(pm8001_ha, tag); 4991 4992 pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy); 4993 } 4994 const struct pm8001_dispatch pm8001_80xx_dispatch = { 4995 .name = "pmc80xx", 4996 .chip_init = pm80xx_chip_init, 4997 .chip_soft_rst = pm80xx_chip_soft_rst, 4998 .chip_rst = pm80xx_hw_chip_rst, 4999 .chip_iounmap = pm8001_chip_iounmap, 5000 .isr = pm80xx_chip_isr, 5001 .is_our_interrupt = pm80xx_chip_is_our_interrupt, 5002 .isr_process_oq = process_oq, 5003 .interrupt_enable = pm80xx_chip_interrupt_enable, 5004 .interrupt_disable = pm80xx_chip_interrupt_disable, 5005 .make_prd = pm8001_chip_make_sg, 5006 .smp_req = pm80xx_chip_smp_req, 5007 .ssp_io_req = pm80xx_chip_ssp_io_req, 5008 .sata_req = pm80xx_chip_sata_req, 5009 .phy_start_req = pm80xx_chip_phy_start_req, 5010 .phy_stop_req = pm80xx_chip_phy_stop_req, 5011 .reg_dev_req = pm80xx_chip_reg_dev_req, 5012 .dereg_dev_req = pm8001_chip_dereg_dev_req, 5013 .phy_ctl_req = pm80xx_chip_phy_ctl_req, 5014 .task_abort = pm8001_chip_abort_task, 5015 .ssp_tm_req = pm8001_chip_ssp_tm_req, 5016 .get_nvmd_req = pm8001_chip_get_nvmd_req, 5017 .set_nvmd_req = pm8001_chip_set_nvmd_req, 5018 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 5019 .set_dev_state_req = pm8001_chip_set_dev_state_req, 5020 .fatal_errors = pm80xx_fatal_errors, 5021 }; 5022