1 /* 2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 PMC-Sierra, Inc., 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm80xx_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46 #define SMP_DIRECT 1 47 #define SMP_INDIRECT 2 48 49 50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value) 51 { 52 u32 reg_val; 53 unsigned long start; 54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); 55 /* confirm the setting is written */ 56 start = jiffies + HZ; /* 1 sec */ 57 do { 58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); 59 } while ((reg_val != shift_value) && time_before(jiffies, start)); 60 if (reg_val != shift_value) { 61 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n", 62 reg_val); 63 return -1; 64 } 65 return 0; 66 } 67 68 static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset, 69 const void *destination, 70 u32 dw_count, u32 bus_base_number) 71 { 72 u32 index, value, offset; 73 u32 *destination1; 74 destination1 = (u32 *)destination; 75 76 for (index = 0; index < dw_count; index += 4, destination1++) { 77 offset = (soffset + index); 78 if (offset < (64 * 1024)) { 79 value = pm8001_cr32(pm8001_ha, bus_base_number, offset); 80 *destination1 = cpu_to_le32(value); 81 } 82 } 83 return; 84 } 85 86 ssize_t pm80xx_get_fatal_dump(struct device *cdev, 87 struct device_attribute *attr, char *buf) 88 { 89 struct Scsi_Host *shost = class_to_shost(cdev); 90 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 91 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 92 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; 93 u32 accum_len , reg_val, index, *temp; 94 u32 status = 1; 95 unsigned long start; 96 u8 *direct_data; 97 char *fatal_error_data = buf; 98 u32 length_to_read; 99 u32 offset; 100 101 pm8001_ha->forensic_info.data_buf.direct_data = buf; 102 if (pm8001_ha->chip_id == chip_8001) { 103 pm8001_ha->forensic_info.data_buf.direct_data += 104 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 105 "Not supported for SPC controller"); 106 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 107 (char *)buf; 108 } 109 /* initialize variables for very first call from host application */ 110 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 111 pm8001_dbg(pm8001_ha, IO, 112 "forensic_info TYPE_NON_FATAL..............\n"); 113 direct_data = (u8 *)fatal_error_data; 114 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; 115 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; 116 pm8001_ha->forensic_info.data_buf.direct_offset = 0; 117 pm8001_ha->forensic_info.data_buf.read_len = 0; 118 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 119 120 /* Write signature to fatal dump table */ 121 pm8001_mw32(fatal_table_address, 122 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd); 123 124 pm8001_ha->forensic_info.data_buf.direct_data = direct_data; 125 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status); 126 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n", 127 pm8001_ha->forensic_info.data_buf.read_len); 128 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n", 129 pm8001_ha->forensic_info.data_buf.direct_len); 130 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n", 131 pm8001_ha->forensic_info.data_buf.direct_offset); 132 } 133 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 134 /* start to get data */ 135 /* Program the MEMBASE II Shifting Register with 0x00.*/ 136 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 137 pm8001_ha->fatal_forensic_shift_offset); 138 pm8001_ha->forensic_last_offset = 0; 139 pm8001_ha->forensic_fatal_step = 0; 140 pm8001_ha->fatal_bar_loc = 0; 141 } 142 143 /* Read until accum_len is retrived */ 144 accum_len = pm8001_mr32(fatal_table_address, 145 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 146 /* Determine length of data between previously stored transfer length 147 * and current accumulated transfer length 148 */ 149 length_to_read = 150 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer; 151 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n", 152 accum_len); 153 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n", 154 length_to_read); 155 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n", 156 pm8001_ha->forensic_last_offset); 157 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n", 158 pm8001_ha->forensic_info.data_buf.read_len); 159 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n", 160 pm8001_ha->forensic_info.data_buf.direct_len); 161 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n", 162 pm8001_ha->forensic_info.data_buf.direct_offset); 163 164 /* If accumulated length failed to read correctly fail the attempt.*/ 165 if (accum_len == 0xFFFFFFFF) { 166 pm8001_dbg(pm8001_ha, IO, 167 "Possible PCI issue 0x%x not expected\n", 168 accum_len); 169 return status; 170 } 171 /* If accumulated length is zero fail the attempt */ 172 if (accum_len == 0) { 173 pm8001_ha->forensic_info.data_buf.direct_data += 174 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 175 "%08x ", 0xFFFFFFFF); 176 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 177 (char *)buf; 178 } 179 /* Accumulated length is good so start capturing the first data */ 180 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 181 if (pm8001_ha->forensic_fatal_step == 0) { 182 moreData: 183 /* If data to read is less than SYSFS_OFFSET then reduce the 184 * length of dataLen 185 */ 186 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET 187 > length_to_read) { 188 pm8001_ha->forensic_info.data_buf.direct_len = 189 length_to_read - 190 pm8001_ha->forensic_last_offset; 191 } else { 192 pm8001_ha->forensic_info.data_buf.direct_len = 193 SYSFS_OFFSET; 194 } 195 if (pm8001_ha->forensic_info.data_buf.direct_data) { 196 /* Data is in bar, copy to host memory */ 197 pm80xx_pci_mem_copy(pm8001_ha, 198 pm8001_ha->fatal_bar_loc, 199 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, 200 pm8001_ha->forensic_info.data_buf.direct_len, 1); 201 } 202 pm8001_ha->fatal_bar_loc += 203 pm8001_ha->forensic_info.data_buf.direct_len; 204 pm8001_ha->forensic_info.data_buf.direct_offset += 205 pm8001_ha->forensic_info.data_buf.direct_len; 206 pm8001_ha->forensic_last_offset += 207 pm8001_ha->forensic_info.data_buf.direct_len; 208 pm8001_ha->forensic_info.data_buf.read_len = 209 pm8001_ha->forensic_info.data_buf.direct_len; 210 211 if (pm8001_ha->forensic_last_offset >= length_to_read) { 212 pm8001_ha->forensic_info.data_buf.direct_data += 213 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 214 "%08x ", 3); 215 for (index = 0; index < 216 (pm8001_ha->forensic_info.data_buf.direct_len 217 / 4); index++) { 218 pm8001_ha->forensic_info.data_buf.direct_data += 219 sprintf( 220 pm8001_ha->forensic_info.data_buf.direct_data, 221 "%08x ", *(temp + index)); 222 } 223 224 pm8001_ha->fatal_bar_loc = 0; 225 pm8001_ha->forensic_fatal_step = 1; 226 pm8001_ha->fatal_forensic_shift_offset = 0; 227 pm8001_ha->forensic_last_offset = 0; 228 status = 0; 229 offset = (int) 230 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 231 - (char *)buf); 232 pm8001_dbg(pm8001_ha, IO, 233 "get_fatal_spcv:return1 0x%x\n", offset); 234 return (char *)pm8001_ha-> 235 forensic_info.data_buf.direct_data - 236 (char *)buf; 237 } 238 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { 239 pm8001_ha->forensic_info.data_buf.direct_data += 240 sprintf(pm8001_ha-> 241 forensic_info.data_buf.direct_data, 242 "%08x ", 2); 243 for (index = 0; index < 244 (pm8001_ha->forensic_info.data_buf.direct_len 245 / 4); index++) { 246 pm8001_ha->forensic_info.data_buf.direct_data 247 += sprintf(pm8001_ha-> 248 forensic_info.data_buf.direct_data, 249 "%08x ", *(temp + index)); 250 } 251 status = 0; 252 offset = (int) 253 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 254 - (char *)buf); 255 pm8001_dbg(pm8001_ha, IO, 256 "get_fatal_spcv:return2 0x%x\n", offset); 257 return (char *)pm8001_ha-> 258 forensic_info.data_buf.direct_data - 259 (char *)buf; 260 } 261 262 /* Increment the MEMBASE II Shifting Register value by 0x100.*/ 263 pm8001_ha->forensic_info.data_buf.direct_data += 264 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 265 "%08x ", 2); 266 for (index = 0; index < 267 (pm8001_ha->forensic_info.data_buf.direct_len 268 / 4) ; index++) { 269 pm8001_ha->forensic_info.data_buf.direct_data += 270 sprintf(pm8001_ha-> 271 forensic_info.data_buf.direct_data, 272 "%08x ", *(temp + index)); 273 } 274 pm8001_ha->fatal_forensic_shift_offset += 0x100; 275 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 276 pm8001_ha->fatal_forensic_shift_offset); 277 pm8001_ha->fatal_bar_loc = 0; 278 status = 0; 279 offset = (int) 280 ((char *)pm8001_ha->forensic_info.data_buf.direct_data 281 - (char *)buf); 282 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n", 283 offset); 284 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 285 (char *)buf; 286 } 287 if (pm8001_ha->forensic_fatal_step == 1) { 288 /* store previous accumulated length before triggering next 289 * accumulated length update 290 */ 291 pm8001_ha->forensic_preserved_accumulated_transfer = 292 pm8001_mr32(fatal_table_address, 293 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 294 295 /* continue capturing the fatal log until Dump status is 0x3 */ 296 if (pm8001_mr32(fatal_table_address, 297 MPI_FATAL_EDUMP_TABLE_STATUS) < 298 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) { 299 300 /* reset fddstat bit by writing to zero*/ 301 pm8001_mw32(fatal_table_address, 302 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0); 303 304 /* set dump control value to '1' so that new data will 305 * be transferred to shared memory 306 */ 307 pm8001_mw32(fatal_table_address, 308 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 309 MPI_FATAL_EDUMP_HANDSHAKE_RDY); 310 311 /*Poll FDDHSHK until clear */ 312 start = jiffies + (2 * HZ); /* 2 sec */ 313 314 do { 315 reg_val = pm8001_mr32(fatal_table_address, 316 MPI_FATAL_EDUMP_TABLE_HANDSHAKE); 317 } while ((reg_val) && time_before(jiffies, start)); 318 319 if (reg_val != 0) { 320 pm8001_dbg(pm8001_ha, FAIL, 321 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n", 322 reg_val); 323 /* Fail the dump if a timeout occurs */ 324 pm8001_ha->forensic_info.data_buf.direct_data += 325 sprintf( 326 pm8001_ha->forensic_info.data_buf.direct_data, 327 "%08x ", 0xFFFFFFFF); 328 return((char *) 329 pm8001_ha->forensic_info.data_buf.direct_data 330 - (char *)buf); 331 } 332 /* Poll status register until set to 2 or 333 * 3 for up to 2 seconds 334 */ 335 start = jiffies + (2 * HZ); /* 2 sec */ 336 337 do { 338 reg_val = pm8001_mr32(fatal_table_address, 339 MPI_FATAL_EDUMP_TABLE_STATUS); 340 } while (((reg_val != 2) && (reg_val != 3)) && 341 time_before(jiffies, start)); 342 343 if (reg_val < 2) { 344 pm8001_dbg(pm8001_ha, FAIL, 345 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n", 346 reg_val); 347 /* Fail the dump if a timeout occurs */ 348 pm8001_ha->forensic_info.data_buf.direct_data += 349 sprintf( 350 pm8001_ha->forensic_info.data_buf.direct_data, 351 "%08x ", 0xFFFFFFFF); 352 pm8001_cw32(pm8001_ha, 0, 353 MEMBASE_II_SHIFT_REGISTER, 354 pm8001_ha->fatal_forensic_shift_offset); 355 } 356 /* Read the next block of the debug data.*/ 357 length_to_read = pm8001_mr32(fatal_table_address, 358 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) - 359 pm8001_ha->forensic_preserved_accumulated_transfer; 360 if (length_to_read != 0x0) { 361 pm8001_ha->forensic_fatal_step = 0; 362 goto moreData; 363 } else { 364 pm8001_ha->forensic_info.data_buf.direct_data += 365 sprintf( 366 pm8001_ha->forensic_info.data_buf.direct_data, 367 "%08x ", 4); 368 pm8001_ha->forensic_info.data_buf.read_len 369 = 0xFFFFFFFF; 370 pm8001_ha->forensic_info.data_buf.direct_len 371 = 0; 372 pm8001_ha->forensic_info.data_buf.direct_offset 373 = 0; 374 pm8001_ha->forensic_info.data_buf.read_len = 0; 375 } 376 } 377 } 378 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data 379 - (char *)buf); 380 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset); 381 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 382 (char *)buf; 383 } 384 385 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma 386 * location by the firmware. 387 */ 388 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev, 389 struct device_attribute *attr, char *buf) 390 { 391 struct Scsi_Host *shost = class_to_shost(cdev); 392 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 393 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 394 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr; 395 u32 accum_len = 0; 396 u32 total_len = 0; 397 u32 reg_val = 0; 398 u32 *temp = NULL; 399 u32 index = 0; 400 u32 output_length; 401 unsigned long start = 0; 402 char *buf_copy = buf; 403 404 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 405 if (++pm8001_ha->non_fatal_count == 1) { 406 if (pm8001_ha->chip_id == chip_8001) { 407 snprintf(pm8001_ha->forensic_info.data_buf.direct_data, 408 PAGE_SIZE, "Not supported for SPC controller"); 409 return 0; 410 } 411 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n"); 412 /* 413 * Step 1: Write the host buffer parameters in the MPI Fatal and 414 * Non-Fatal Error Dump Capture Table.This is the buffer 415 * where debug data will be DMAed to. 416 */ 417 pm8001_mw32(nonfatal_table_address, 418 MPI_FATAL_EDUMP_TABLE_LO_OFFSET, 419 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo); 420 421 pm8001_mw32(nonfatal_table_address, 422 MPI_FATAL_EDUMP_TABLE_HI_OFFSET, 423 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi); 424 425 pm8001_mw32(nonfatal_table_address, 426 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET); 427 428 /* Optionally, set the DUMPCTRL bit to 1 if the host 429 * keeps sending active I/Os while capturing the non-fatal 430 * debug data. Otherwise, leave this bit set to zero 431 */ 432 pm8001_mw32(nonfatal_table_address, 433 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY); 434 435 /* 436 * Step 2: Clear Accumulative Length of Debug Data Transferred 437 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump 438 * Capture Table to zero. 439 */ 440 pm8001_mw32(nonfatal_table_address, 441 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0); 442 443 /* initiallize previous accumulated length to 0 */ 444 pm8001_ha->forensic_preserved_accumulated_transfer = 0; 445 pm8001_ha->non_fatal_read_length = 0; 446 } 447 448 total_len = pm8001_mr32(nonfatal_table_address, 449 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN); 450 /* 451 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT] 452 * field and then request that the SPCv controller transfer the debug 453 * data by setting bit 7 of the Inbound Doorbell Set Register. 454 */ 455 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0); 456 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, 457 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP); 458 459 /* 460 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for 461 * 2 seconds) until register bit 7 is cleared. 462 * This step only indicates the request is accepted by the controller. 463 */ 464 start = jiffies + (2 * HZ); /* 2 sec */ 465 do { 466 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) & 467 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP; 468 } while ((reg_val != 0) && time_before(jiffies, start)); 469 470 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non 471 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in 472 * the MPI Fatal and Non-Fatal Error Dump Capture Table. 473 */ 474 start = jiffies + (2 * HZ); /* 2 sec */ 475 do { 476 reg_val = pm8001_mr32(nonfatal_table_address, 477 MPI_FATAL_EDUMP_TABLE_STATUS); 478 } while ((!reg_val) && time_before(jiffies, start)); 479 480 if ((reg_val == 0x00) || 481 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) || 482 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) { 483 pm8001_ha->non_fatal_read_length = 0; 484 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF); 485 pm8001_ha->non_fatal_count = 0; 486 return (buf_copy - buf); 487 } else if (reg_val == 488 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) { 489 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2); 490 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) || 491 (pm8001_ha->non_fatal_read_length >= total_len)) { 492 pm8001_ha->non_fatal_read_length = 0; 493 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4); 494 pm8001_ha->non_fatal_count = 0; 495 } 496 accum_len = pm8001_mr32(nonfatal_table_address, 497 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 498 output_length = accum_len - 499 pm8001_ha->forensic_preserved_accumulated_transfer; 500 501 for (index = 0; index < output_length/4; index++) 502 buf_copy += snprintf(buf_copy, PAGE_SIZE, 503 "%08x ", *(temp+index)); 504 505 pm8001_ha->non_fatal_read_length += output_length; 506 507 /* store current accumulated length to use in next iteration as 508 * the previous accumulated length 509 */ 510 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len; 511 return (buf_copy - buf); 512 } 513 514 /** 515 * read_main_config_table - read the configure table and save it. 516 * @pm8001_ha: our hba card information 517 */ 518 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 519 { 520 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 521 522 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = 523 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); 524 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = 525 pm8001_mr32(address, MAIN_INTERFACE_REVISION); 526 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = 527 pm8001_mr32(address, MAIN_FW_REVISION); 528 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = 529 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); 530 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = 531 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); 532 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = 533 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); 534 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = 535 pm8001_mr32(address, MAIN_GST_OFFSET); 536 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = 537 pm8001_mr32(address, MAIN_IBQ_OFFSET); 538 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = 539 pm8001_mr32(address, MAIN_OBQ_OFFSET); 540 541 /* read Error Dump Offset and Length */ 542 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = 543 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 544 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = 545 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 546 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = 547 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 548 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = 549 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 550 551 /* read GPIO LED settings from the configuration table */ 552 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = 553 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); 554 555 /* read analog Setting offset from the configuration table */ 556 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = 557 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 558 559 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = 560 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); 561 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = 562 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); 563 /* read port recover and reset timeout */ 564 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer = 565 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER); 566 /* read ILA and inactive firmware version */ 567 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version = 568 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE); 569 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version = 570 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION); 571 572 pm8001_dbg(pm8001_ha, DEV, 573 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n", 574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature, 575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev, 576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev); 577 578 pm8001_dbg(pm8001_ha, DEV, 579 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n", 580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset, 581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset, 582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset, 583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset, 584 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset); 585 586 pm8001_dbg(pm8001_ha, DEV, 587 "Main cfg table; ila rev:%x Inactive fw rev:%x\n", 588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version, 589 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version); 590 } 591 592 /** 593 * read_general_status_table - read the general status table and save it. 594 * @pm8001_ha: our hba card information 595 */ 596 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 597 { 598 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 599 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = 600 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); 601 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = 602 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); 603 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = 604 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); 605 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = 606 pm8001_mr32(address, GST_MSGUTCNT_OFFSET); 607 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = 608 pm8001_mr32(address, GST_IOPTCNT_OFFSET); 609 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = 610 pm8001_mr32(address, GST_GPIO_INPUT_VAL); 611 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = 612 pm8001_mr32(address, GST_RERRINFO_OFFSET0); 613 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = 614 pm8001_mr32(address, GST_RERRINFO_OFFSET1); 615 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = 616 pm8001_mr32(address, GST_RERRINFO_OFFSET2); 617 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = 618 pm8001_mr32(address, GST_RERRINFO_OFFSET3); 619 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = 620 pm8001_mr32(address, GST_RERRINFO_OFFSET4); 621 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = 622 pm8001_mr32(address, GST_RERRINFO_OFFSET5); 623 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = 624 pm8001_mr32(address, GST_RERRINFO_OFFSET6); 625 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = 626 pm8001_mr32(address, GST_RERRINFO_OFFSET7); 627 } 628 /** 629 * read_phy_attr_table - read the phy attribute table and save it. 630 * @pm8001_ha: our hba card information 631 */ 632 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) 633 { 634 void __iomem *address = pm8001_ha->pspa_q_tbl_addr; 635 pm8001_ha->phy_attr_table.phystart1_16[0] = 636 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); 637 pm8001_ha->phy_attr_table.phystart1_16[1] = 638 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); 639 pm8001_ha->phy_attr_table.phystart1_16[2] = 640 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); 641 pm8001_ha->phy_attr_table.phystart1_16[3] = 642 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); 643 pm8001_ha->phy_attr_table.phystart1_16[4] = 644 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); 645 pm8001_ha->phy_attr_table.phystart1_16[5] = 646 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); 647 pm8001_ha->phy_attr_table.phystart1_16[6] = 648 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); 649 pm8001_ha->phy_attr_table.phystart1_16[7] = 650 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); 651 pm8001_ha->phy_attr_table.phystart1_16[8] = 652 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); 653 pm8001_ha->phy_attr_table.phystart1_16[9] = 654 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); 655 pm8001_ha->phy_attr_table.phystart1_16[10] = 656 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); 657 pm8001_ha->phy_attr_table.phystart1_16[11] = 658 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); 659 pm8001_ha->phy_attr_table.phystart1_16[12] = 660 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); 661 pm8001_ha->phy_attr_table.phystart1_16[13] = 662 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); 663 pm8001_ha->phy_attr_table.phystart1_16[14] = 664 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); 665 pm8001_ha->phy_attr_table.phystart1_16[15] = 666 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); 667 668 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = 669 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); 670 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = 671 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); 672 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = 673 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); 674 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = 675 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); 676 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = 677 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); 678 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = 679 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); 680 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = 681 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); 682 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = 683 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); 684 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = 685 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); 686 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = 687 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); 688 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = 689 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); 690 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = 691 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); 692 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = 693 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); 694 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = 695 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); 696 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = 697 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); 698 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = 699 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); 700 701 } 702 703 /** 704 * read_inbnd_queue_table - read the inbound queue table and save it. 705 * @pm8001_ha: our hba card information 706 */ 707 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 708 { 709 int i; 710 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 711 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 712 u32 offset = i * 0x20; 713 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 714 get_pci_bar_index(pm8001_mr32(address, 715 (offset + IB_PIPCI_BAR))); 716 pm8001_ha->inbnd_q_tbl[i].pi_offset = 717 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); 718 } 719 } 720 721 /** 722 * read_outbnd_queue_table - read the outbound queue table and save it. 723 * @pm8001_ha: our hba card information 724 */ 725 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 726 { 727 int i; 728 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 729 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 730 u32 offset = i * 0x24; 731 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 732 get_pci_bar_index(pm8001_mr32(address, 733 (offset + OB_CIPCI_BAR))); 734 pm8001_ha->outbnd_q_tbl[i].ci_offset = 735 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); 736 } 737 } 738 739 /** 740 * init_default_table_values - init the default table. 741 * @pm8001_ha: our hba card information 742 */ 743 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 744 { 745 int i; 746 u32 offsetib, offsetob; 747 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 748 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 749 u32 ib_offset = pm8001_ha->ib_offset; 750 u32 ob_offset = pm8001_ha->ob_offset; 751 u32 ci_offset = pm8001_ha->ci_offset; 752 u32 pi_offset = pm8001_ha->pi_offset; 753 754 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = 755 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 756 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = 757 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 758 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = 759 PM8001_EVENT_LOG_SIZE; 760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; 761 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = 762 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 763 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = 764 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 765 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = 766 PM8001_EVENT_LOG_SIZE; 767 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; 768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; 769 770 /* Disable end to end CRC checking */ 771 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); 772 773 for (i = 0; i < pm8001_ha->max_q_num; i++) { 774 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 775 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 776 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 777 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; 778 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 779 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; 780 pm8001_ha->inbnd_q_tbl[i].base_virt = 781 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; 782 pm8001_ha->inbnd_q_tbl[i].total_length = 783 pm8001_ha->memoryMap.region[ib_offset + i].total_len; 784 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 785 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; 786 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 787 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; 788 pm8001_ha->inbnd_q_tbl[i].ci_virt = 789 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; 790 offsetib = i * 0x20; 791 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 792 get_pci_bar_index(pm8001_mr32(addressib, 793 (offsetib + 0x14))); 794 pm8001_ha->inbnd_q_tbl[i].pi_offset = 795 pm8001_mr32(addressib, (offsetib + 0x18)); 796 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 797 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 798 799 pm8001_dbg(pm8001_ha, DEV, 800 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i, 801 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar, 802 pm8001_ha->inbnd_q_tbl[i].pi_offset); 803 } 804 for (i = 0; i < pm8001_ha->max_q_num; i++) { 805 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 806 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 807 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 808 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; 809 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 810 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; 811 pm8001_ha->outbnd_q_tbl[i].base_virt = 812 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; 813 pm8001_ha->outbnd_q_tbl[i].total_length = 814 pm8001_ha->memoryMap.region[ob_offset + i].total_len; 815 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 816 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; 817 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 818 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; 819 /* interrupt vector based on oq */ 820 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); 821 pm8001_ha->outbnd_q_tbl[i].pi_virt = 822 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; 823 offsetob = i * 0x24; 824 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 825 get_pci_bar_index(pm8001_mr32(addressob, 826 offsetob + 0x14)); 827 pm8001_ha->outbnd_q_tbl[i].ci_offset = 828 pm8001_mr32(addressob, (offsetob + 0x18)); 829 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 830 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 831 832 pm8001_dbg(pm8001_ha, DEV, 833 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i, 834 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar, 835 pm8001_ha->outbnd_q_tbl[i].ci_offset); 836 } 837 } 838 839 /** 840 * update_main_config_table - update the main default table to the HBA. 841 * @pm8001_ha: our hba card information 842 */ 843 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 844 { 845 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 846 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, 847 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); 848 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, 849 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); 850 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, 851 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); 852 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, 853 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); 854 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, 855 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); 856 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, 857 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); 858 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, 859 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); 860 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, 861 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); 862 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, 863 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); 864 /* Update Fatal error interrupt vector */ 865 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 866 ((pm8001_ha->max_q_num - 1) << 8); 867 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, 868 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); 869 pm8001_dbg(pm8001_ha, DEV, 870 "Updated Fatal error interrupt vector 0x%x\n", 871 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)); 872 873 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, 874 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); 875 876 /* SPCv specific */ 877 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; 878 /* Set GPIOLED to 0x2 for LED indicator */ 879 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; 880 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, 881 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); 882 pm8001_dbg(pm8001_ha, DEV, 883 "Programming DW 0x21 in main cfg table with 0x%x\n", 884 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)); 885 886 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 887 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 888 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, 889 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); 890 891 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000; 892 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 893 PORT_RECOVERY_TIMEOUT; 894 if (pm8001_ha->chip_id == chip_8006) { 895 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 896 0x0000ffff; 897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 898 CHIP_8006_PORT_RECOVERY_TIMEOUT; 899 } 900 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 901 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 902 } 903 904 /** 905 * update_inbnd_queue_table - update the inbound queue table to the HBA. 906 * @pm8001_ha: our hba card information 907 * @number: entry in the queue 908 */ 909 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 910 int number) 911 { 912 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 913 u16 offset = number * 0x20; 914 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, 915 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 916 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, 917 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 918 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, 919 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 920 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, 921 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 922 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, 923 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 924 925 pm8001_dbg(pm8001_ha, DEV, 926 "IQ %d: Element pri size 0x%x\n", 927 number, 928 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 929 930 pm8001_dbg(pm8001_ha, DEV, 931 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n", 932 pm8001_ha->inbnd_q_tbl[number].upper_base_addr, 933 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 934 935 pm8001_dbg(pm8001_ha, DEV, 936 "CI upper base addr 0x%x CI lower base addr 0x%x\n", 937 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr, 938 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 939 } 940 941 /** 942 * update_outbnd_queue_table - update the outbound queue table to the HBA. 943 * @pm8001_ha: our hba card information 944 * @number: entry in the queue 945 */ 946 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 947 int number) 948 { 949 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 950 u16 offset = number * 0x24; 951 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, 952 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 953 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, 954 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 955 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, 956 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 957 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, 958 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 959 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, 960 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 961 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, 962 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 963 964 pm8001_dbg(pm8001_ha, DEV, 965 "OQ %d: Element pri size 0x%x\n", 966 number, 967 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 968 969 pm8001_dbg(pm8001_ha, DEV, 970 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n", 971 pm8001_ha->outbnd_q_tbl[number].upper_base_addr, 972 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 973 974 pm8001_dbg(pm8001_ha, DEV, 975 "PI upper base addr 0x%x PI lower base addr 0x%x\n", 976 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr, 977 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 978 } 979 980 /** 981 * mpi_init_check - check firmware initialization status. 982 * @pm8001_ha: our hba card information 983 */ 984 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 985 { 986 u32 max_wait_count; 987 u32 value; 988 u32 gst_len_mpistate; 989 990 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 991 table is updated */ 992 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); 993 /* wait until Inbound DoorBell Clear Register toggled */ 994 if (IS_SPCV_12G(pm8001_ha->pdev)) { 995 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 996 } else { 997 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 998 } 999 do { 1000 udelay(1); 1001 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1002 value &= SPCv_MSGU_CFG_TABLE_UPDATE; 1003 } while ((value != 0) && (--max_wait_count)); 1004 1005 if (!max_wait_count) { 1006 /* additional check */ 1007 pm8001_dbg(pm8001_ha, FAIL, 1008 "Inb doorbell clear not toggled[value:%x]\n", 1009 value); 1010 return -EBUSY; 1011 } 1012 /* check the MPI-State for initialization upto 100ms*/ 1013 max_wait_count = 100 * 1000;/* 100 msec */ 1014 do { 1015 udelay(1); 1016 gst_len_mpistate = 1017 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1018 GST_GSTLEN_MPIS_OFFSET); 1019 } while ((GST_MPI_STATE_INIT != 1020 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); 1021 if (!max_wait_count) 1022 return -EBUSY; 1023 1024 /* check MPI Initialization error */ 1025 gst_len_mpistate = gst_len_mpistate >> 16; 1026 if (0x0000 != gst_len_mpistate) 1027 return -EBUSY; 1028 1029 return 0; 1030 } 1031 1032 /** 1033 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 1034 * This function sleeps hence it must not be used in atomic context. 1035 * @pm8001_ha: our hba card information 1036 */ 1037 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 1038 { 1039 u32 value; 1040 u32 max_wait_count; 1041 u32 max_wait_time; 1042 int ret = 0; 1043 1044 /* reset / PCIe ready */ 1045 max_wait_time = max_wait_count = 5; /* 100 milli sec */ 1046 do { 1047 msleep(FW_READY_INTERVAL); 1048 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1049 } while ((value == 0xFFFFFFFF) && (--max_wait_count)); 1050 1051 /* check ila status */ 1052 max_wait_time = max_wait_count = 50; /* 1000 milli sec */ 1053 do { 1054 msleep(FW_READY_INTERVAL); 1055 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1056 } while (((value & SCRATCH_PAD_ILA_READY) != 1057 SCRATCH_PAD_ILA_READY) && (--max_wait_count)); 1058 if (!max_wait_count) 1059 ret = -1; 1060 else { 1061 pm8001_dbg(pm8001_ha, MSG, 1062 " ila ready status in %d millisec\n", 1063 (max_wait_time - max_wait_count)); 1064 } 1065 1066 /* check RAAE status */ 1067 max_wait_time = max_wait_count = 90; /* 1800 milli sec */ 1068 do { 1069 msleep(FW_READY_INTERVAL); 1070 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1071 } while (((value & SCRATCH_PAD_RAAE_READY) != 1072 SCRATCH_PAD_RAAE_READY) && (--max_wait_count)); 1073 if (!max_wait_count) 1074 ret = -1; 1075 else { 1076 pm8001_dbg(pm8001_ha, MSG, 1077 " raae ready status in %d millisec\n", 1078 (max_wait_time - max_wait_count)); 1079 } 1080 1081 /* check iop0 status */ 1082 max_wait_time = max_wait_count = 30; /* 600 milli sec */ 1083 do { 1084 msleep(FW_READY_INTERVAL); 1085 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1086 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) && 1087 (--max_wait_count)); 1088 if (!max_wait_count) 1089 ret = -1; 1090 else { 1091 pm8001_dbg(pm8001_ha, MSG, 1092 " iop0 ready status in %d millisec\n", 1093 (max_wait_time - max_wait_count)); 1094 } 1095 1096 /* check iop1 status only for 16 port controllers */ 1097 if ((pm8001_ha->chip_id != chip_8008) && 1098 (pm8001_ha->chip_id != chip_8009)) { 1099 /* 200 milli sec */ 1100 max_wait_time = max_wait_count = 10; 1101 do { 1102 msleep(FW_READY_INTERVAL); 1103 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1104 } while (((value & SCRATCH_PAD_IOP1_READY) != 1105 SCRATCH_PAD_IOP1_READY) && (--max_wait_count)); 1106 if (!max_wait_count) 1107 ret = -1; 1108 else { 1109 pm8001_dbg(pm8001_ha, MSG, 1110 "iop1 ready status in %d millisec\n", 1111 (max_wait_time - max_wait_count)); 1112 } 1113 } 1114 1115 return ret; 1116 } 1117 1118 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 1119 { 1120 void __iomem *base_addr; 1121 u32 value; 1122 u32 offset; 1123 u32 pcibar; 1124 u32 pcilogic; 1125 1126 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1127 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ 1128 1129 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n", 1130 offset, value); 1131 pcilogic = (value & 0xFC000000) >> 26; 1132 pcibar = get_pci_bar_index(pcilogic); 1133 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); 1134 pm8001_ha->main_cfg_tbl_addr = base_addr = 1135 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 1136 pm8001_ha->general_stat_tbl_addr = 1137 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 1138 0xFFFFFF); 1139 pm8001_ha->inbnd_q_tbl_addr = 1140 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & 1141 0xFFFFFF); 1142 pm8001_ha->outbnd_q_tbl_addr = 1143 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & 1144 0xFFFFFF); 1145 pm8001_ha->ivt_tbl_addr = 1146 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & 1147 0xFFFFFF); 1148 pm8001_ha->pspa_q_tbl_addr = 1149 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & 1150 0xFFFFFF); 1151 pm8001_ha->fatal_tbl_addr = 1152 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & 1153 0xFFFFFF); 1154 1155 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n", 1156 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)); 1157 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n", 1158 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)); 1159 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n", 1160 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)); 1161 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n", 1162 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)); 1163 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n", 1164 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)); 1165 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n", 1166 pm8001_ha->main_cfg_tbl_addr, 1167 pm8001_ha->general_stat_tbl_addr); 1168 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n", 1169 pm8001_ha->inbnd_q_tbl_addr, 1170 pm8001_ha->outbnd_q_tbl_addr); 1171 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n", 1172 pm8001_ha->pspa_q_tbl_addr, 1173 pm8001_ha->ivt_tbl_addr); 1174 } 1175 1176 /** 1177 * pm80xx_set_thermal_config - support the thermal configuration 1178 * @pm8001_ha: our hba card information. 1179 */ 1180 int 1181 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) 1182 { 1183 struct set_ctrl_cfg_req payload; 1184 struct inbound_queue_table *circularQ; 1185 int rc; 1186 u32 tag; 1187 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1188 u32 page_code; 1189 1190 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1191 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1192 if (rc) 1193 return -1; 1194 1195 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1196 payload.tag = cpu_to_le32(tag); 1197 1198 if (IS_SPCV_12G(pm8001_ha->pdev)) 1199 page_code = THERMAL_PAGE_CODE_7H; 1200 else 1201 page_code = THERMAL_PAGE_CODE_8H; 1202 1203 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) | 1204 (THERMAL_ENABLE << 8) | page_code; 1205 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8); 1206 1207 pm8001_dbg(pm8001_ha, DEV, 1208 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n", 1209 payload.cfg_pg[0], payload.cfg_pg[1]); 1210 1211 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1212 sizeof(payload), 0); 1213 if (rc) 1214 pm8001_tag_free(pm8001_ha, tag); 1215 return rc; 1216 1217 } 1218 1219 /** 1220 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol 1221 * Timer configuration page 1222 * @pm8001_ha: our hba card information. 1223 */ 1224 static int 1225 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) 1226 { 1227 struct set_ctrl_cfg_req payload; 1228 struct inbound_queue_table *circularQ; 1229 SASProtocolTimerConfig_t SASConfigPage; 1230 int rc; 1231 u32 tag; 1232 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1233 1234 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1235 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); 1236 1237 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1238 1239 if (rc) 1240 return -1; 1241 1242 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1243 payload.tag = cpu_to_le32(tag); 1244 1245 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE; 1246 SASConfigPage.MST_MSI = 3 << 15; 1247 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO; 1248 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) | 1249 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER; 1250 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME; 1251 1252 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF) 1253 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF; 1254 1255 1256 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) | 1257 SAS_OPNRJT_RTRY_INTVL; 1258 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16) 1259 | SAS_COPNRJT_RTRY_TMO; 1260 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16) 1261 | SAS_COPNRJT_RTRY_THR; 1262 SASConfigPage.MAX_AIP = SAS_MAX_AIP; 1263 1264 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n", 1265 SASConfigPage.pageCode); 1266 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n", 1267 SASConfigPage.MST_MSI); 1268 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n", 1269 SASConfigPage.STP_SSP_MCT_TMO); 1270 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n", 1271 SASConfigPage.STP_FRM_TMO); 1272 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n", 1273 SASConfigPage.STP_IDLE_TMO); 1274 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n", 1275 SASConfigPage.OPNRJT_RTRY_INTVL); 1276 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n", 1277 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO); 1278 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n", 1279 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR); 1280 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n", 1281 SASConfigPage.MAX_AIP); 1282 1283 memcpy(&payload.cfg_pg, &SASConfigPage, 1284 sizeof(SASProtocolTimerConfig_t)); 1285 1286 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1287 sizeof(payload), 0); 1288 if (rc) 1289 pm8001_tag_free(pm8001_ha, tag); 1290 1291 return rc; 1292 } 1293 1294 /** 1295 * pm80xx_get_encrypt_info - Check for encryption 1296 * @pm8001_ha: our hba card information. 1297 */ 1298 static int 1299 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) 1300 { 1301 u32 scratch3_value; 1302 int ret = -1; 1303 1304 /* Read encryption status from SCRATCH PAD 3 */ 1305 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1306 1307 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1308 SCRATCH_PAD3_ENC_READY) { 1309 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1310 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1311 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1312 SCRATCH_PAD3_SMF_ENABLED) 1313 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1314 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1315 SCRATCH_PAD3_SMA_ENABLED) 1316 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1317 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1318 SCRATCH_PAD3_SMB_ENABLED) 1319 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1320 pm8001_ha->encrypt_info.status = 0; 1321 pm8001_dbg(pm8001_ha, INIT, 1322 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", 1323 scratch3_value, 1324 pm8001_ha->encrypt_info.cipher_mode, 1325 pm8001_ha->encrypt_info.sec_mode, 1326 pm8001_ha->encrypt_info.status); 1327 ret = 0; 1328 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == 1329 SCRATCH_PAD3_ENC_DISABLED) { 1330 pm8001_dbg(pm8001_ha, INIT, 1331 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", 1332 scratch3_value); 1333 pm8001_ha->encrypt_info.status = 0xFFFFFFFF; 1334 pm8001_ha->encrypt_info.cipher_mode = 0; 1335 pm8001_ha->encrypt_info.sec_mode = 0; 1336 ret = 0; 1337 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1338 SCRATCH_PAD3_ENC_DIS_ERR) { 1339 pm8001_ha->encrypt_info.status = 1340 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1341 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1342 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1343 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1344 SCRATCH_PAD3_SMF_ENABLED) 1345 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1346 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1347 SCRATCH_PAD3_SMA_ENABLED) 1348 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1349 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1350 SCRATCH_PAD3_SMB_ENABLED) 1351 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1352 pm8001_dbg(pm8001_ha, INIT, 1353 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1354 scratch3_value, 1355 pm8001_ha->encrypt_info.cipher_mode, 1356 pm8001_ha->encrypt_info.sec_mode, 1357 pm8001_ha->encrypt_info.status); 1358 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1359 SCRATCH_PAD3_ENC_ENA_ERR) { 1360 1361 pm8001_ha->encrypt_info.status = 1362 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1363 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1364 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1365 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1366 SCRATCH_PAD3_SMF_ENABLED) 1367 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1368 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1369 SCRATCH_PAD3_SMA_ENABLED) 1370 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1371 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1372 SCRATCH_PAD3_SMB_ENABLED) 1373 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1374 1375 pm8001_dbg(pm8001_ha, INIT, 1376 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 1377 scratch3_value, 1378 pm8001_ha->encrypt_info.cipher_mode, 1379 pm8001_ha->encrypt_info.sec_mode, 1380 pm8001_ha->encrypt_info.status); 1381 } 1382 return ret; 1383 } 1384 1385 /** 1386 * pm80xx_encrypt_update - update flash with encryption informtion 1387 * @pm8001_ha: our hba card information. 1388 */ 1389 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) 1390 { 1391 struct kek_mgmt_req payload; 1392 struct inbound_queue_table *circularQ; 1393 int rc; 1394 u32 tag; 1395 u32 opc = OPC_INB_KEK_MANAGEMENT; 1396 1397 memset(&payload, 0, sizeof(struct kek_mgmt_req)); 1398 rc = pm8001_tag_alloc(pm8001_ha, &tag); 1399 if (rc) 1400 return -1; 1401 1402 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1403 payload.tag = cpu_to_le32(tag); 1404 /* Currently only one key is used. New KEK index is 1. 1405 * Current KEK index is 1. Store KEK to NVRAM is 1. 1406 */ 1407 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) | 1408 KEK_MGMT_SUBOP_KEYCARDUPDATE); 1409 1410 pm8001_dbg(pm8001_ha, DEV, 1411 "Saving Encryption info to flash. payload 0x%x\n", 1412 payload.new_curidx_ksop); 1413 1414 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 1415 sizeof(payload), 0); 1416 if (rc) 1417 pm8001_tag_free(pm8001_ha, tag); 1418 1419 return rc; 1420 } 1421 1422 /** 1423 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 1424 * @pm8001_ha: our hba card information 1425 */ 1426 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) 1427 { 1428 int ret; 1429 u8 i = 0; 1430 1431 /* check the firmware status */ 1432 if (-1 == check_fw_ready(pm8001_ha)) { 1433 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1434 return -EBUSY; 1435 } 1436 1437 /* Initialize the controller fatal error flag */ 1438 pm8001_ha->controller_fatal_error = false; 1439 1440 /* Initialize pci space address eg: mpi offset */ 1441 init_pci_device_addresses(pm8001_ha); 1442 init_default_table_values(pm8001_ha); 1443 read_main_config_table(pm8001_ha); 1444 read_general_status_table(pm8001_ha); 1445 read_inbnd_queue_table(pm8001_ha); 1446 read_outbnd_queue_table(pm8001_ha); 1447 read_phy_attr_table(pm8001_ha); 1448 1449 /* update main config table ,inbound table and outbound table */ 1450 update_main_config_table(pm8001_ha); 1451 for (i = 0; i < pm8001_ha->max_q_num; i++) { 1452 update_inbnd_queue_table(pm8001_ha, i); 1453 update_outbnd_queue_table(pm8001_ha, i); 1454 } 1455 /* notify firmware update finished and check initialization status */ 1456 if (0 == mpi_init_check(pm8001_ha)) { 1457 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n"); 1458 } else 1459 return -EBUSY; 1460 1461 /* send SAS protocol timer configuration page to FW */ 1462 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha); 1463 1464 /* Check for encryption */ 1465 if (pm8001_ha->chip->encrypt) { 1466 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n"); 1467 ret = pm80xx_get_encrypt_info(pm8001_ha); 1468 if (ret == -1) { 1469 pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n"); 1470 if (pm8001_ha->encrypt_info.status == 0x81) { 1471 pm8001_dbg(pm8001_ha, INIT, 1472 "Encryption enabled with error.Saving encryption key to flash\n"); 1473 pm80xx_encrypt_update(pm8001_ha); 1474 } 1475 } 1476 } 1477 return 0; 1478 } 1479 1480 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 1481 { 1482 u32 max_wait_count; 1483 u32 value; 1484 u32 gst_len_mpistate; 1485 init_pci_device_addresses(pm8001_ha); 1486 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 1487 table is stop */ 1488 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); 1489 1490 /* wait until Inbound DoorBell Clear Register toggled */ 1491 if (IS_SPCV_12G(pm8001_ha->pdev)) { 1492 max_wait_count = 4 * 1000 * 1000;/* 4 sec */ 1493 } else { 1494 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1495 } 1496 do { 1497 udelay(1); 1498 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1499 value &= SPCv_MSGU_CFG_TABLE_RESET; 1500 } while ((value != 0) && (--max_wait_count)); 1501 1502 if (!max_wait_count) { 1503 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value); 1504 return -1; 1505 } 1506 1507 /* check the MPI-State for termination in progress */ 1508 /* wait until Inbound DoorBell Clear Register toggled */ 1509 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */ 1510 do { 1511 udelay(1); 1512 gst_len_mpistate = 1513 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1514 GST_GSTLEN_MPIS_OFFSET); 1515 if (GST_MPI_STATE_UNINIT == 1516 (gst_len_mpistate & GST_MPI_STATE_MASK)) 1517 break; 1518 } while (--max_wait_count); 1519 if (!max_wait_count) { 1520 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", 1521 gst_len_mpistate & GST_MPI_STATE_MASK); 1522 return -1; 1523 } 1524 1525 return 0; 1526 } 1527 1528 /** 1529 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 1530 * the FW register status to the originated status. 1531 * @pm8001_ha: our hba card information 1532 */ 1533 1534 static int 1535 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 1536 { 1537 u32 regval; 1538 u32 bootloader_state; 1539 u32 ibutton0, ibutton1; 1540 1541 /* Process MPI table uninitialization only if FW is ready */ 1542 if (!pm8001_ha->controller_fatal_error) { 1543 /* Check if MPI is in ready state to reset */ 1544 if (mpi_uninit_check(pm8001_ha) != 0) { 1545 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1546 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1547 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1548 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1549 pm8001_dbg(pm8001_ha, FAIL, 1550 "MPI state is not ready scratch: %x:%x:%x:%x\n", 1551 r0, r1, r2, r3); 1552 /* if things aren't ready but the bootloader is ok then 1553 * try the reset anyway. 1554 */ 1555 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK) 1556 return -1; 1557 } 1558 } 1559 /* checked for reset register normal state; 0x0 */ 1560 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1561 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n", 1562 regval); 1563 1564 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); 1565 msleep(500); 1566 1567 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 1568 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n", 1569 regval); 1570 1571 if ((regval & SPCv_SOFT_RESET_READ_MASK) == 1572 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { 1573 pm8001_dbg(pm8001_ha, MSG, 1574 " soft reset successful [regval: 0x%x]\n", 1575 regval); 1576 } else { 1577 pm8001_dbg(pm8001_ha, MSG, 1578 " soft reset failed [regval: 0x%x]\n", 1579 regval); 1580 1581 /* check bootloader is successfully executed or in HDA mode */ 1582 bootloader_state = 1583 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1584 SCRATCH_PAD1_BOOTSTATE_MASK; 1585 1586 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { 1587 pm8001_dbg(pm8001_ha, MSG, 1588 "Bootloader state - HDA mode SEEPROM\n"); 1589 } else if (bootloader_state == 1590 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { 1591 pm8001_dbg(pm8001_ha, MSG, 1592 "Bootloader state - HDA mode Bootstrap Pin\n"); 1593 } else if (bootloader_state == 1594 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { 1595 pm8001_dbg(pm8001_ha, MSG, 1596 "Bootloader state - HDA mode soft reset\n"); 1597 } else if (bootloader_state == 1598 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { 1599 pm8001_dbg(pm8001_ha, MSG, 1600 "Bootloader state-HDA mode critical error\n"); 1601 } 1602 return -EBUSY; 1603 } 1604 1605 /* check the firmware status after reset */ 1606 if (-1 == check_fw_ready(pm8001_ha)) { 1607 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1608 /* check iButton feature support for motherboard controller */ 1609 if (pm8001_ha->pdev->subsystem_vendor != 1610 PCI_VENDOR_ID_ADAPTEC2 && 1611 pm8001_ha->pdev->subsystem_vendor != 1612 PCI_VENDOR_ID_ATTO && 1613 pm8001_ha->pdev->subsystem_vendor != 0) { 1614 ibutton0 = pm8001_cr32(pm8001_ha, 0, 1615 MSGU_HOST_SCRATCH_PAD_6); 1616 ibutton1 = pm8001_cr32(pm8001_ha, 0, 1617 MSGU_HOST_SCRATCH_PAD_7); 1618 if (!ibutton0 && !ibutton1) { 1619 pm8001_dbg(pm8001_ha, FAIL, 1620 "iButton Feature is not Available!!!\n"); 1621 return -EBUSY; 1622 } 1623 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { 1624 pm8001_dbg(pm8001_ha, FAIL, 1625 "CRC Check for iButton Feature Failed!!!\n"); 1626 return -EBUSY; 1627 } 1628 } 1629 } 1630 pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n"); 1631 return 0; 1632 } 1633 1634 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1635 { 1636 u32 i; 1637 1638 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n"); 1639 1640 /* do SPCv chip reset. */ 1641 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); 1642 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n"); 1643 1644 /* Check this ..whether delay is required or no */ 1645 /* delay 10 usec */ 1646 udelay(10); 1647 1648 /* wait for 20 msec until the firmware gets reloaded */ 1649 i = 20; 1650 do { 1651 mdelay(1); 1652 } while ((--i) != 0); 1653 1654 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); 1655 } 1656 1657 /** 1658 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1659 * @pm8001_ha: our hba card information 1660 */ 1661 static void 1662 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1663 { 1664 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1665 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1666 } 1667 1668 /** 1669 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1670 * @pm8001_ha: our hba card information 1671 */ 1672 static void 1673 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1674 { 1675 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); 1676 } 1677 1678 /** 1679 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1680 * @pm8001_ha: our hba card information 1681 * @vec: interrupt number to enable 1682 */ 1683 static void 1684 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1685 { 1686 #ifdef PM8001_USE_MSIX 1687 u32 mask; 1688 mask = (u32)(1 << vec); 1689 1690 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); 1691 return; 1692 #endif 1693 pm80xx_chip_intx_interrupt_enable(pm8001_ha); 1694 1695 } 1696 1697 /** 1698 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt 1699 * @pm8001_ha: our hba card information 1700 * @vec: interrupt number to disable 1701 */ 1702 static void 1703 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1704 { 1705 #ifdef PM8001_USE_MSIX 1706 u32 mask; 1707 if (vec == 0xFF) 1708 mask = 0xFFFFFFFF; 1709 else 1710 mask = (u32)(1 << vec); 1711 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); 1712 return; 1713 #endif 1714 pm80xx_chip_intx_interrupt_disable(pm8001_ha); 1715 } 1716 1717 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1718 struct pm8001_device *pm8001_ha_dev) 1719 { 1720 int res; 1721 u32 ccb_tag; 1722 struct pm8001_ccb_info *ccb; 1723 struct sas_task *task = NULL; 1724 struct task_abort_req task_abort; 1725 struct inbound_queue_table *circularQ; 1726 u32 opc = OPC_INB_SATA_ABORT; 1727 int ret; 1728 1729 if (!pm8001_ha_dev) { 1730 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n"); 1731 return; 1732 } 1733 1734 task = sas_alloc_slow_task(GFP_ATOMIC); 1735 1736 if (!task) { 1737 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n"); 1738 return; 1739 } 1740 1741 task->task_done = pm8001_task_done; 1742 1743 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1744 if (res) { 1745 sas_free_task(task); 1746 return; 1747 } 1748 1749 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1750 ccb->device = pm8001_ha_dev; 1751 ccb->ccb_tag = ccb_tag; 1752 ccb->task = task; 1753 1754 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1755 1756 memset(&task_abort, 0, sizeof(task_abort)); 1757 task_abort.abort_all = cpu_to_le32(1); 1758 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1759 task_abort.tag = cpu_to_le32(ccb_tag); 1760 1761 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 1762 sizeof(task_abort), 0); 1763 pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n"); 1764 if (ret) { 1765 sas_free_task(task); 1766 pm8001_tag_free(pm8001_ha, ccb_tag); 1767 } 1768 } 1769 1770 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha, 1771 struct pm8001_device *pm8001_ha_dev) 1772 { 1773 struct sata_start_req sata_cmd; 1774 int res; 1775 u32 ccb_tag; 1776 struct pm8001_ccb_info *ccb; 1777 struct sas_task *task = NULL; 1778 struct host_to_dev_fis fis; 1779 struct domain_device *dev; 1780 struct inbound_queue_table *circularQ; 1781 u32 opc = OPC_INB_SATA_HOST_OPSTART; 1782 1783 task = sas_alloc_slow_task(GFP_ATOMIC); 1784 1785 if (!task) { 1786 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n"); 1787 return; 1788 } 1789 task->task_done = pm8001_task_done; 1790 1791 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1792 if (res) { 1793 sas_free_task(task); 1794 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n"); 1795 return; 1796 } 1797 1798 /* allocate domain device by ourselves as libsas 1799 * is not going to provide any 1800 */ 1801 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1802 if (!dev) { 1803 sas_free_task(task); 1804 pm8001_tag_free(pm8001_ha, ccb_tag); 1805 pm8001_dbg(pm8001_ha, FAIL, 1806 "Domain device cannot be allocated\n"); 1807 return; 1808 } 1809 1810 task->dev = dev; 1811 task->dev->lldd_dev = pm8001_ha_dev; 1812 1813 ccb = &pm8001_ha->ccb_info[ccb_tag]; 1814 ccb->device = pm8001_ha_dev; 1815 ccb->ccb_tag = ccb_tag; 1816 ccb->task = task; 1817 ccb->n_elem = 0; 1818 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1819 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1820 1821 memset(&sata_cmd, 0, sizeof(sata_cmd)); 1822 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1823 1824 /* construct read log FIS */ 1825 memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1826 fis.fis_type = 0x27; 1827 fis.flags = 0x80; 1828 fis.command = ATA_CMD_READ_LOG_EXT; 1829 fis.lbal = 0x10; 1830 fis.sector_count = 0x1; 1831 1832 sata_cmd.tag = cpu_to_le32(ccb_tag); 1833 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1834 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9)); 1835 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1836 1837 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 1838 sizeof(sata_cmd), 0); 1839 pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n"); 1840 if (res) { 1841 sas_free_task(task); 1842 pm8001_tag_free(pm8001_ha, ccb_tag); 1843 kfree(dev); 1844 } 1845 } 1846 1847 /** 1848 * mpi_ssp_completion- process the event that FW response to the SSP request. 1849 * @pm8001_ha: our hba card information 1850 * @piomb: the message contents of this outbound message. 1851 * 1852 * When FW has completed a ssp request for example a IO request, after it has 1853 * filled the SG data with the data, it will trigger this event represent 1854 * that he has finished the job,please check the coresponding buffer. 1855 * So we will tell the caller who maybe waiting the result to tell upper layer 1856 * that the task has been finished. 1857 */ 1858 static void 1859 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1860 { 1861 struct sas_task *t; 1862 struct pm8001_ccb_info *ccb; 1863 unsigned long flags; 1864 u32 status; 1865 u32 param; 1866 u32 tag; 1867 struct ssp_completion_resp *psspPayload; 1868 struct task_status_struct *ts; 1869 struct ssp_response_iu *iu; 1870 struct pm8001_device *pm8001_dev; 1871 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1872 status = le32_to_cpu(psspPayload->status); 1873 tag = le32_to_cpu(psspPayload->tag); 1874 ccb = &pm8001_ha->ccb_info[tag]; 1875 if ((status == IO_ABORTED) && ccb->open_retry) { 1876 /* Being completed by another */ 1877 ccb->open_retry = 0; 1878 return; 1879 } 1880 pm8001_dev = ccb->device; 1881 param = le32_to_cpu(psspPayload->param); 1882 t = ccb->task; 1883 1884 if (status && status != IO_UNDERFLOW) 1885 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); 1886 if (unlikely(!t || !t->lldd_task || !t->dev)) 1887 return; 1888 ts = &t->task_status; 1889 1890 pm8001_dbg(pm8001_ha, DEV, 1891 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t); 1892 1893 /* Print sas address of IO failed device */ 1894 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1895 (status != IO_UNDERFLOW)) 1896 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n", 1897 SAS_ADDR(t->dev->sas_addr)); 1898 1899 switch (status) { 1900 case IO_SUCCESS: 1901 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n", 1902 param); 1903 if (param == 0) { 1904 ts->resp = SAS_TASK_COMPLETE; 1905 ts->stat = SAM_STAT_GOOD; 1906 } else { 1907 ts->resp = SAS_TASK_COMPLETE; 1908 ts->stat = SAS_PROTO_RESPONSE; 1909 ts->residual = param; 1910 iu = &psspPayload->ssp_resp_iu; 1911 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1912 } 1913 if (pm8001_dev) 1914 atomic_dec(&pm8001_dev->running_req); 1915 break; 1916 case IO_ABORTED: 1917 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 1918 ts->resp = SAS_TASK_COMPLETE; 1919 ts->stat = SAS_ABORTED_TASK; 1920 if (pm8001_dev) 1921 atomic_dec(&pm8001_dev->running_req); 1922 break; 1923 case IO_UNDERFLOW: 1924 /* SSP Completion with error */ 1925 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n", 1926 param); 1927 ts->resp = SAS_TASK_COMPLETE; 1928 ts->stat = SAS_DATA_UNDERRUN; 1929 ts->residual = param; 1930 if (pm8001_dev) 1931 atomic_dec(&pm8001_dev->running_req); 1932 break; 1933 case IO_NO_DEVICE: 1934 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 1935 ts->resp = SAS_TASK_UNDELIVERED; 1936 ts->stat = SAS_PHY_DOWN; 1937 if (pm8001_dev) 1938 atomic_dec(&pm8001_dev->running_req); 1939 break; 1940 case IO_XFER_ERROR_BREAK: 1941 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 1942 ts->resp = SAS_TASK_COMPLETE; 1943 ts->stat = SAS_OPEN_REJECT; 1944 /* Force the midlayer to retry */ 1945 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1946 if (pm8001_dev) 1947 atomic_dec(&pm8001_dev->running_req); 1948 break; 1949 case IO_XFER_ERROR_PHY_NOT_READY: 1950 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 1951 ts->resp = SAS_TASK_COMPLETE; 1952 ts->stat = SAS_OPEN_REJECT; 1953 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1954 if (pm8001_dev) 1955 atomic_dec(&pm8001_dev->running_req); 1956 break; 1957 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME: 1958 pm8001_dbg(pm8001_ha, IO, 1959 "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"); 1960 ts->resp = SAS_TASK_COMPLETE; 1961 ts->stat = SAS_OPEN_REJECT; 1962 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1963 if (pm8001_dev) 1964 atomic_dec(&pm8001_dev->running_req); 1965 break; 1966 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1967 pm8001_dbg(pm8001_ha, IO, 1968 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 1969 ts->resp = SAS_TASK_COMPLETE; 1970 ts->stat = SAS_OPEN_REJECT; 1971 ts->open_rej_reason = SAS_OREJ_EPROTO; 1972 if (pm8001_dev) 1973 atomic_dec(&pm8001_dev->running_req); 1974 break; 1975 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1976 pm8001_dbg(pm8001_ha, IO, 1977 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 1978 ts->resp = SAS_TASK_COMPLETE; 1979 ts->stat = SAS_OPEN_REJECT; 1980 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1981 if (pm8001_dev) 1982 atomic_dec(&pm8001_dev->running_req); 1983 break; 1984 case IO_OPEN_CNX_ERROR_BREAK: 1985 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 1986 ts->resp = SAS_TASK_COMPLETE; 1987 ts->stat = SAS_OPEN_REJECT; 1988 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1989 if (pm8001_dev) 1990 atomic_dec(&pm8001_dev->running_req); 1991 break; 1992 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1993 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 1994 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 1995 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 1996 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 1997 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 1998 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 1999 ts->resp = SAS_TASK_COMPLETE; 2000 ts->stat = SAS_OPEN_REJECT; 2001 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2002 if (!t->uldd_task) 2003 pm8001_handle_event(pm8001_ha, 2004 pm8001_dev, 2005 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2006 break; 2007 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2008 pm8001_dbg(pm8001_ha, IO, 2009 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2010 ts->resp = SAS_TASK_COMPLETE; 2011 ts->stat = SAS_OPEN_REJECT; 2012 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2013 if (pm8001_dev) 2014 atomic_dec(&pm8001_dev->running_req); 2015 break; 2016 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2017 pm8001_dbg(pm8001_ha, IO, 2018 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2019 ts->resp = SAS_TASK_COMPLETE; 2020 ts->stat = SAS_OPEN_REJECT; 2021 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2022 if (pm8001_dev) 2023 atomic_dec(&pm8001_dev->running_req); 2024 break; 2025 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2026 pm8001_dbg(pm8001_ha, IO, 2027 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2028 ts->resp = SAS_TASK_UNDELIVERED; 2029 ts->stat = SAS_OPEN_REJECT; 2030 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2031 if (pm8001_dev) 2032 atomic_dec(&pm8001_dev->running_req); 2033 break; 2034 case IO_XFER_ERROR_NAK_RECEIVED: 2035 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2036 ts->resp = SAS_TASK_COMPLETE; 2037 ts->stat = SAS_OPEN_REJECT; 2038 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2039 if (pm8001_dev) 2040 atomic_dec(&pm8001_dev->running_req); 2041 break; 2042 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2043 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2044 ts->resp = SAS_TASK_COMPLETE; 2045 ts->stat = SAS_NAK_R_ERR; 2046 if (pm8001_dev) 2047 atomic_dec(&pm8001_dev->running_req); 2048 break; 2049 case IO_XFER_ERROR_DMA: 2050 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2051 ts->resp = SAS_TASK_COMPLETE; 2052 ts->stat = SAS_OPEN_REJECT; 2053 if (pm8001_dev) 2054 atomic_dec(&pm8001_dev->running_req); 2055 break; 2056 case IO_XFER_OPEN_RETRY_TIMEOUT: 2057 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2058 ts->resp = SAS_TASK_COMPLETE; 2059 ts->stat = SAS_OPEN_REJECT; 2060 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2061 if (pm8001_dev) 2062 atomic_dec(&pm8001_dev->running_req); 2063 break; 2064 case IO_XFER_ERROR_OFFSET_MISMATCH: 2065 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2066 ts->resp = SAS_TASK_COMPLETE; 2067 ts->stat = SAS_OPEN_REJECT; 2068 if (pm8001_dev) 2069 atomic_dec(&pm8001_dev->running_req); 2070 break; 2071 case IO_PORT_IN_RESET: 2072 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2073 ts->resp = SAS_TASK_COMPLETE; 2074 ts->stat = SAS_OPEN_REJECT; 2075 if (pm8001_dev) 2076 atomic_dec(&pm8001_dev->running_req); 2077 break; 2078 case IO_DS_NON_OPERATIONAL: 2079 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2080 ts->resp = SAS_TASK_COMPLETE; 2081 ts->stat = SAS_OPEN_REJECT; 2082 if (!t->uldd_task) 2083 pm8001_handle_event(pm8001_ha, 2084 pm8001_dev, 2085 IO_DS_NON_OPERATIONAL); 2086 break; 2087 case IO_DS_IN_RECOVERY: 2088 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2089 ts->resp = SAS_TASK_COMPLETE; 2090 ts->stat = SAS_OPEN_REJECT; 2091 if (pm8001_dev) 2092 atomic_dec(&pm8001_dev->running_req); 2093 break; 2094 case IO_TM_TAG_NOT_FOUND: 2095 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n"); 2096 ts->resp = SAS_TASK_COMPLETE; 2097 ts->stat = SAS_OPEN_REJECT; 2098 if (pm8001_dev) 2099 atomic_dec(&pm8001_dev->running_req); 2100 break; 2101 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 2102 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"); 2103 ts->resp = SAS_TASK_COMPLETE; 2104 ts->stat = SAS_OPEN_REJECT; 2105 if (pm8001_dev) 2106 atomic_dec(&pm8001_dev->running_req); 2107 break; 2108 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2109 pm8001_dbg(pm8001_ha, IO, 2110 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2111 ts->resp = SAS_TASK_COMPLETE; 2112 ts->stat = SAS_OPEN_REJECT; 2113 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2114 if (pm8001_dev) 2115 atomic_dec(&pm8001_dev->running_req); 2116 break; 2117 default: 2118 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2119 /* not allowed case. Therefore, return failed status */ 2120 ts->resp = SAS_TASK_COMPLETE; 2121 ts->stat = SAS_OPEN_REJECT; 2122 if (pm8001_dev) 2123 atomic_dec(&pm8001_dev->running_req); 2124 break; 2125 } 2126 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ", 2127 psspPayload->ssp_resp_iu.status); 2128 spin_lock_irqsave(&t->task_state_lock, flags); 2129 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2130 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2131 t->task_state_flags |= SAS_TASK_STATE_DONE; 2132 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2133 spin_unlock_irqrestore(&t->task_state_lock, flags); 2134 pm8001_dbg(pm8001_ha, FAIL, 2135 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2136 t, status, ts->resp, ts->stat); 2137 if (t->slow_task) 2138 complete(&t->slow_task->completion); 2139 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2140 } else { 2141 spin_unlock_irqrestore(&t->task_state_lock, flags); 2142 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2143 mb();/* in order to force CPU ordering */ 2144 t->task_done(t); 2145 } 2146 } 2147 2148 /*See the comments for mpi_ssp_completion */ 2149 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2150 { 2151 struct sas_task *t; 2152 unsigned long flags; 2153 struct task_status_struct *ts; 2154 struct pm8001_ccb_info *ccb; 2155 struct pm8001_device *pm8001_dev; 2156 struct ssp_event_resp *psspPayload = 2157 (struct ssp_event_resp *)(piomb + 4); 2158 u32 event = le32_to_cpu(psspPayload->event); 2159 u32 tag = le32_to_cpu(psspPayload->tag); 2160 u32 port_id = le32_to_cpu(psspPayload->port_id); 2161 2162 ccb = &pm8001_ha->ccb_info[tag]; 2163 t = ccb->task; 2164 pm8001_dev = ccb->device; 2165 if (event) 2166 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); 2167 if (unlikely(!t || !t->lldd_task || !t->dev)) 2168 return; 2169 ts = &t->task_status; 2170 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2171 port_id, tag, event); 2172 switch (event) { 2173 case IO_OVERFLOW: 2174 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2175 ts->resp = SAS_TASK_COMPLETE; 2176 ts->stat = SAS_DATA_OVERRUN; 2177 ts->residual = 0; 2178 if (pm8001_dev) 2179 atomic_dec(&pm8001_dev->running_req); 2180 break; 2181 case IO_XFER_ERROR_BREAK: 2182 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2183 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2184 return; 2185 case IO_XFER_ERROR_PHY_NOT_READY: 2186 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2187 ts->resp = SAS_TASK_COMPLETE; 2188 ts->stat = SAS_OPEN_REJECT; 2189 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2190 break; 2191 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2192 pm8001_dbg(pm8001_ha, IO, 2193 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2194 ts->resp = SAS_TASK_COMPLETE; 2195 ts->stat = SAS_OPEN_REJECT; 2196 ts->open_rej_reason = SAS_OREJ_EPROTO; 2197 break; 2198 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2199 pm8001_dbg(pm8001_ha, IO, 2200 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2201 ts->resp = SAS_TASK_COMPLETE; 2202 ts->stat = SAS_OPEN_REJECT; 2203 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2204 break; 2205 case IO_OPEN_CNX_ERROR_BREAK: 2206 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2207 ts->resp = SAS_TASK_COMPLETE; 2208 ts->stat = SAS_OPEN_REJECT; 2209 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2210 break; 2211 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2212 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2213 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2214 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2215 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2216 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2217 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2218 ts->resp = SAS_TASK_COMPLETE; 2219 ts->stat = SAS_OPEN_REJECT; 2220 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2221 if (!t->uldd_task) 2222 pm8001_handle_event(pm8001_ha, 2223 pm8001_dev, 2224 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2225 break; 2226 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2227 pm8001_dbg(pm8001_ha, IO, 2228 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2229 ts->resp = SAS_TASK_COMPLETE; 2230 ts->stat = SAS_OPEN_REJECT; 2231 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2232 break; 2233 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2234 pm8001_dbg(pm8001_ha, IO, 2235 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2236 ts->resp = SAS_TASK_COMPLETE; 2237 ts->stat = SAS_OPEN_REJECT; 2238 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2239 break; 2240 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2241 pm8001_dbg(pm8001_ha, IO, 2242 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2243 ts->resp = SAS_TASK_COMPLETE; 2244 ts->stat = SAS_OPEN_REJECT; 2245 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2246 break; 2247 case IO_XFER_ERROR_NAK_RECEIVED: 2248 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2249 ts->resp = SAS_TASK_COMPLETE; 2250 ts->stat = SAS_OPEN_REJECT; 2251 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2252 break; 2253 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2254 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2255 ts->resp = SAS_TASK_COMPLETE; 2256 ts->stat = SAS_NAK_R_ERR; 2257 break; 2258 case IO_XFER_OPEN_RETRY_TIMEOUT: 2259 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2260 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2261 return; 2262 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2263 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2264 ts->resp = SAS_TASK_COMPLETE; 2265 ts->stat = SAS_DATA_OVERRUN; 2266 break; 2267 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2268 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2269 ts->resp = SAS_TASK_COMPLETE; 2270 ts->stat = SAS_DATA_OVERRUN; 2271 break; 2272 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2273 pm8001_dbg(pm8001_ha, IO, 2274 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2275 ts->resp = SAS_TASK_COMPLETE; 2276 ts->stat = SAS_DATA_OVERRUN; 2277 break; 2278 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2279 pm8001_dbg(pm8001_ha, IO, 2280 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"); 2281 ts->resp = SAS_TASK_COMPLETE; 2282 ts->stat = SAS_DATA_OVERRUN; 2283 break; 2284 case IO_XFER_ERROR_OFFSET_MISMATCH: 2285 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2286 ts->resp = SAS_TASK_COMPLETE; 2287 ts->stat = SAS_DATA_OVERRUN; 2288 break; 2289 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2290 pm8001_dbg(pm8001_ha, IO, 2291 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2292 ts->resp = SAS_TASK_COMPLETE; 2293 ts->stat = SAS_DATA_OVERRUN; 2294 break; 2295 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2296 pm8001_dbg(pm8001_ha, IOERR, 2297 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2298 /* TBC: used default set values */ 2299 ts->resp = SAS_TASK_COMPLETE; 2300 ts->stat = SAS_DATA_OVERRUN; 2301 break; 2302 case IO_XFER_CMD_FRAME_ISSUED: 2303 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2304 return; 2305 default: 2306 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2307 /* not allowed case. Therefore, return failed status */ 2308 ts->resp = SAS_TASK_COMPLETE; 2309 ts->stat = SAS_DATA_OVERRUN; 2310 break; 2311 } 2312 spin_lock_irqsave(&t->task_state_lock, flags); 2313 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2314 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2315 t->task_state_flags |= SAS_TASK_STATE_DONE; 2316 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2317 spin_unlock_irqrestore(&t->task_state_lock, flags); 2318 pm8001_dbg(pm8001_ha, FAIL, 2319 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2320 t, event, ts->resp, ts->stat); 2321 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2322 } else { 2323 spin_unlock_irqrestore(&t->task_state_lock, flags); 2324 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2325 mb();/* in order to force CPU ordering */ 2326 t->task_done(t); 2327 } 2328 } 2329 2330 /*See the comments for mpi_ssp_completion */ 2331 static void 2332 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2333 { 2334 struct sas_task *t; 2335 struct pm8001_ccb_info *ccb; 2336 u32 param; 2337 u32 status; 2338 u32 tag; 2339 int i, j; 2340 u8 sata_addr_low[4]; 2341 u32 temp_sata_addr_low, temp_sata_addr_hi; 2342 u8 sata_addr_hi[4]; 2343 struct sata_completion_resp *psataPayload; 2344 struct task_status_struct *ts; 2345 struct ata_task_resp *resp ; 2346 u32 *sata_resp; 2347 struct pm8001_device *pm8001_dev; 2348 unsigned long flags; 2349 2350 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2351 status = le32_to_cpu(psataPayload->status); 2352 tag = le32_to_cpu(psataPayload->tag); 2353 2354 if (!tag) { 2355 pm8001_dbg(pm8001_ha, FAIL, "tag null\n"); 2356 return; 2357 } 2358 ccb = &pm8001_ha->ccb_info[tag]; 2359 param = le32_to_cpu(psataPayload->param); 2360 if (ccb) { 2361 t = ccb->task; 2362 pm8001_dev = ccb->device; 2363 } else { 2364 pm8001_dbg(pm8001_ha, FAIL, "ccb null\n"); 2365 return; 2366 } 2367 2368 if (t) { 2369 if (t->dev && (t->dev->lldd_dev)) 2370 pm8001_dev = t->dev->lldd_dev; 2371 } else { 2372 pm8001_dbg(pm8001_ha, FAIL, "task null\n"); 2373 return; 2374 } 2375 2376 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2377 && unlikely(!t || !t->lldd_task || !t->dev)) { 2378 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2379 return; 2380 } 2381 2382 ts = &t->task_status; 2383 if (!ts) { 2384 pm8001_dbg(pm8001_ha, FAIL, "ts null\n"); 2385 return; 2386 } 2387 2388 if (unlikely(status)) 2389 pm8001_dbg(pm8001_ha, IOERR, 2390 "status:0x%x, tag:0x%x, task::0x%p\n", 2391 status, tag, t); 2392 2393 /* Print sas address of IO failed device */ 2394 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2395 (status != IO_UNDERFLOW)) { 2396 if (!((t->dev->parent) && 2397 (dev_is_expander(t->dev->parent->dev_type)))) { 2398 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++) 2399 sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2400 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++) 2401 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2402 memcpy(&temp_sata_addr_low, sata_addr_low, 2403 sizeof(sata_addr_low)); 2404 memcpy(&temp_sata_addr_hi, sata_addr_hi, 2405 sizeof(sata_addr_hi)); 2406 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2407 |((temp_sata_addr_hi << 8) & 2408 0xff0000) | 2409 ((temp_sata_addr_hi >> 8) 2410 & 0xff00) | 2411 ((temp_sata_addr_hi << 24) & 2412 0xff000000)); 2413 temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2414 & 0xff) | 2415 ((temp_sata_addr_low << 8) 2416 & 0xff0000) | 2417 ((temp_sata_addr_low >> 8) 2418 & 0xff00) | 2419 ((temp_sata_addr_low << 24) 2420 & 0xff000000)) + 2421 pm8001_dev->attached_phy + 2422 0x10); 2423 pm8001_dbg(pm8001_ha, FAIL, 2424 "SAS Address of IO Failure Drive:%08x%08x\n", 2425 temp_sata_addr_hi, 2426 temp_sata_addr_low); 2427 2428 } else { 2429 pm8001_dbg(pm8001_ha, FAIL, 2430 "SAS Address of IO Failure Drive:%016llx\n", 2431 SAS_ADDR(t->dev->sas_addr)); 2432 } 2433 } 2434 switch (status) { 2435 case IO_SUCCESS: 2436 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2437 if (param == 0) { 2438 ts->resp = SAS_TASK_COMPLETE; 2439 ts->stat = SAM_STAT_GOOD; 2440 /* check if response is for SEND READ LOG */ 2441 if (pm8001_dev && 2442 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2443 /* set new bit for abort_all */ 2444 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 2445 /* clear bit for read log */ 2446 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 2447 pm80xx_send_abort_all(pm8001_ha, pm8001_dev); 2448 /* Free the tag */ 2449 pm8001_tag_free(pm8001_ha, tag); 2450 sas_free_task(t); 2451 return; 2452 } 2453 } else { 2454 u8 len; 2455 ts->resp = SAS_TASK_COMPLETE; 2456 ts->stat = SAS_PROTO_RESPONSE; 2457 ts->residual = param; 2458 pm8001_dbg(pm8001_ha, IO, 2459 "SAS_PROTO_RESPONSE len = %d\n", 2460 param); 2461 sata_resp = &psataPayload->sata_resp[0]; 2462 resp = (struct ata_task_resp *)ts->buf; 2463 if (t->ata_task.dma_xfer == 0 && 2464 t->data_dir == DMA_FROM_DEVICE) { 2465 len = sizeof(struct pio_setup_fis); 2466 pm8001_dbg(pm8001_ha, IO, 2467 "PIO read len = %d\n", len); 2468 } else if (t->ata_task.use_ncq) { 2469 len = sizeof(struct set_dev_bits_fis); 2470 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n", 2471 len); 2472 } else { 2473 len = sizeof(struct dev_to_host_fis); 2474 pm8001_dbg(pm8001_ha, IO, "other len = %d\n", 2475 len); 2476 } 2477 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2478 resp->frame_len = len; 2479 memcpy(&resp->ending_fis[0], sata_resp, len); 2480 ts->buf_valid_size = sizeof(*resp); 2481 } else 2482 pm8001_dbg(pm8001_ha, IO, 2483 "response too large\n"); 2484 } 2485 if (pm8001_dev) 2486 atomic_dec(&pm8001_dev->running_req); 2487 break; 2488 case IO_ABORTED: 2489 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 2490 ts->resp = SAS_TASK_COMPLETE; 2491 ts->stat = SAS_ABORTED_TASK; 2492 if (pm8001_dev) 2493 atomic_dec(&pm8001_dev->running_req); 2494 break; 2495 /* following cases are to do cases */ 2496 case IO_UNDERFLOW: 2497 /* SATA Completion with error */ 2498 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param); 2499 ts->resp = SAS_TASK_COMPLETE; 2500 ts->stat = SAS_DATA_UNDERRUN; 2501 ts->residual = param; 2502 if (pm8001_dev) 2503 atomic_dec(&pm8001_dev->running_req); 2504 break; 2505 case IO_NO_DEVICE: 2506 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2507 ts->resp = SAS_TASK_UNDELIVERED; 2508 ts->stat = SAS_PHY_DOWN; 2509 if (pm8001_dev) 2510 atomic_dec(&pm8001_dev->running_req); 2511 break; 2512 case IO_XFER_ERROR_BREAK: 2513 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2514 ts->resp = SAS_TASK_COMPLETE; 2515 ts->stat = SAS_INTERRUPTED; 2516 if (pm8001_dev) 2517 atomic_dec(&pm8001_dev->running_req); 2518 break; 2519 case IO_XFER_ERROR_PHY_NOT_READY: 2520 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2521 ts->resp = SAS_TASK_COMPLETE; 2522 ts->stat = SAS_OPEN_REJECT; 2523 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2524 if (pm8001_dev) 2525 atomic_dec(&pm8001_dev->running_req); 2526 break; 2527 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2528 pm8001_dbg(pm8001_ha, IO, 2529 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2530 ts->resp = SAS_TASK_COMPLETE; 2531 ts->stat = SAS_OPEN_REJECT; 2532 ts->open_rej_reason = SAS_OREJ_EPROTO; 2533 if (pm8001_dev) 2534 atomic_dec(&pm8001_dev->running_req); 2535 break; 2536 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2537 pm8001_dbg(pm8001_ha, IO, 2538 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2539 ts->resp = SAS_TASK_COMPLETE; 2540 ts->stat = SAS_OPEN_REJECT; 2541 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2542 if (pm8001_dev) 2543 atomic_dec(&pm8001_dev->running_req); 2544 break; 2545 case IO_OPEN_CNX_ERROR_BREAK: 2546 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2547 ts->resp = SAS_TASK_COMPLETE; 2548 ts->stat = SAS_OPEN_REJECT; 2549 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2550 if (pm8001_dev) 2551 atomic_dec(&pm8001_dev->running_req); 2552 break; 2553 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2554 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2555 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2556 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2557 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2558 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2559 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2560 ts->resp = SAS_TASK_COMPLETE; 2561 ts->stat = SAS_DEV_NO_RESPONSE; 2562 if (!t->uldd_task) { 2563 pm8001_handle_event(pm8001_ha, 2564 pm8001_dev, 2565 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2566 ts->resp = SAS_TASK_UNDELIVERED; 2567 ts->stat = SAS_QUEUE_FULL; 2568 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2569 return; 2570 } 2571 break; 2572 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2573 pm8001_dbg(pm8001_ha, IO, 2574 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2575 ts->resp = SAS_TASK_UNDELIVERED; 2576 ts->stat = SAS_OPEN_REJECT; 2577 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2578 if (!t->uldd_task) { 2579 pm8001_handle_event(pm8001_ha, 2580 pm8001_dev, 2581 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2582 ts->resp = SAS_TASK_UNDELIVERED; 2583 ts->stat = SAS_QUEUE_FULL; 2584 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2585 return; 2586 } 2587 break; 2588 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2589 pm8001_dbg(pm8001_ha, IO, 2590 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2591 ts->resp = SAS_TASK_COMPLETE; 2592 ts->stat = SAS_OPEN_REJECT; 2593 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2594 if (pm8001_dev) 2595 atomic_dec(&pm8001_dev->running_req); 2596 break; 2597 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2598 pm8001_dbg(pm8001_ha, IO, 2599 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"); 2600 ts->resp = SAS_TASK_COMPLETE; 2601 ts->stat = SAS_DEV_NO_RESPONSE; 2602 if (!t->uldd_task) { 2603 pm8001_handle_event(pm8001_ha, 2604 pm8001_dev, 2605 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2606 ts->resp = SAS_TASK_UNDELIVERED; 2607 ts->stat = SAS_QUEUE_FULL; 2608 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2609 return; 2610 } 2611 break; 2612 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2613 pm8001_dbg(pm8001_ha, IO, 2614 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2615 ts->resp = SAS_TASK_COMPLETE; 2616 ts->stat = SAS_OPEN_REJECT; 2617 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2618 if (pm8001_dev) 2619 atomic_dec(&pm8001_dev->running_req); 2620 break; 2621 case IO_XFER_ERROR_NAK_RECEIVED: 2622 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2623 ts->resp = SAS_TASK_COMPLETE; 2624 ts->stat = SAS_NAK_R_ERR; 2625 if (pm8001_dev) 2626 atomic_dec(&pm8001_dev->running_req); 2627 break; 2628 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2629 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2630 ts->resp = SAS_TASK_COMPLETE; 2631 ts->stat = SAS_NAK_R_ERR; 2632 if (pm8001_dev) 2633 atomic_dec(&pm8001_dev->running_req); 2634 break; 2635 case IO_XFER_ERROR_DMA: 2636 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2637 ts->resp = SAS_TASK_COMPLETE; 2638 ts->stat = SAS_ABORTED_TASK; 2639 if (pm8001_dev) 2640 atomic_dec(&pm8001_dev->running_req); 2641 break; 2642 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2643 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"); 2644 ts->resp = SAS_TASK_UNDELIVERED; 2645 ts->stat = SAS_DEV_NO_RESPONSE; 2646 if (pm8001_dev) 2647 atomic_dec(&pm8001_dev->running_req); 2648 break; 2649 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2650 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2651 ts->resp = SAS_TASK_COMPLETE; 2652 ts->stat = SAS_DATA_UNDERRUN; 2653 if (pm8001_dev) 2654 atomic_dec(&pm8001_dev->running_req); 2655 break; 2656 case IO_XFER_OPEN_RETRY_TIMEOUT: 2657 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2658 ts->resp = SAS_TASK_COMPLETE; 2659 ts->stat = SAS_OPEN_TO; 2660 if (pm8001_dev) 2661 atomic_dec(&pm8001_dev->running_req); 2662 break; 2663 case IO_PORT_IN_RESET: 2664 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2665 ts->resp = SAS_TASK_COMPLETE; 2666 ts->stat = SAS_DEV_NO_RESPONSE; 2667 if (pm8001_dev) 2668 atomic_dec(&pm8001_dev->running_req); 2669 break; 2670 case IO_DS_NON_OPERATIONAL: 2671 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2672 ts->resp = SAS_TASK_COMPLETE; 2673 ts->stat = SAS_DEV_NO_RESPONSE; 2674 if (!t->uldd_task) { 2675 pm8001_handle_event(pm8001_ha, pm8001_dev, 2676 IO_DS_NON_OPERATIONAL); 2677 ts->resp = SAS_TASK_UNDELIVERED; 2678 ts->stat = SAS_QUEUE_FULL; 2679 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2680 return; 2681 } 2682 break; 2683 case IO_DS_IN_RECOVERY: 2684 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2685 ts->resp = SAS_TASK_COMPLETE; 2686 ts->stat = SAS_DEV_NO_RESPONSE; 2687 if (pm8001_dev) 2688 atomic_dec(&pm8001_dev->running_req); 2689 break; 2690 case IO_DS_IN_ERROR: 2691 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n"); 2692 ts->resp = SAS_TASK_COMPLETE; 2693 ts->stat = SAS_DEV_NO_RESPONSE; 2694 if (!t->uldd_task) { 2695 pm8001_handle_event(pm8001_ha, pm8001_dev, 2696 IO_DS_IN_ERROR); 2697 ts->resp = SAS_TASK_UNDELIVERED; 2698 ts->stat = SAS_QUEUE_FULL; 2699 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2700 return; 2701 } 2702 break; 2703 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2704 pm8001_dbg(pm8001_ha, IO, 2705 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2706 ts->resp = SAS_TASK_COMPLETE; 2707 ts->stat = SAS_OPEN_REJECT; 2708 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2709 if (pm8001_dev) 2710 atomic_dec(&pm8001_dev->running_req); 2711 break; 2712 default: 2713 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2714 /* not allowed case. Therefore, return failed status */ 2715 ts->resp = SAS_TASK_COMPLETE; 2716 ts->stat = SAS_DEV_NO_RESPONSE; 2717 if (pm8001_dev) 2718 atomic_dec(&pm8001_dev->running_req); 2719 break; 2720 } 2721 spin_lock_irqsave(&t->task_state_lock, flags); 2722 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2723 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2724 t->task_state_flags |= SAS_TASK_STATE_DONE; 2725 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2726 spin_unlock_irqrestore(&t->task_state_lock, flags); 2727 pm8001_dbg(pm8001_ha, FAIL, 2728 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2729 t, status, ts->resp, ts->stat); 2730 if (t->slow_task) 2731 complete(&t->slow_task->completion); 2732 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2733 } else { 2734 spin_unlock_irqrestore(&t->task_state_lock, flags); 2735 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2736 } 2737 } 2738 2739 /*See the comments for mpi_ssp_completion */ 2740 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2741 { 2742 struct sas_task *t; 2743 struct task_status_struct *ts; 2744 struct pm8001_ccb_info *ccb; 2745 struct pm8001_device *pm8001_dev; 2746 struct sata_event_resp *psataPayload = 2747 (struct sata_event_resp *)(piomb + 4); 2748 u32 event = le32_to_cpu(psataPayload->event); 2749 u32 tag = le32_to_cpu(psataPayload->tag); 2750 u32 port_id = le32_to_cpu(psataPayload->port_id); 2751 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2752 unsigned long flags; 2753 2754 ccb = &pm8001_ha->ccb_info[tag]; 2755 2756 if (ccb) { 2757 t = ccb->task; 2758 pm8001_dev = ccb->device; 2759 } else { 2760 pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n"); 2761 return; 2762 } 2763 if (event) 2764 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); 2765 2766 /* Check if this is NCQ error */ 2767 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2768 /* find device using device id */ 2769 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2770 /* send read log extension */ 2771 if (pm8001_dev) 2772 pm80xx_send_read_log(pm8001_ha, pm8001_dev); 2773 return; 2774 } 2775 2776 if (unlikely(!t || !t->lldd_task || !t->dev)) { 2777 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2778 return; 2779 } 2780 2781 ts = &t->task_status; 2782 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 2783 port_id, tag, event); 2784 switch (event) { 2785 case IO_OVERFLOW: 2786 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2787 ts->resp = SAS_TASK_COMPLETE; 2788 ts->stat = SAS_DATA_OVERRUN; 2789 ts->residual = 0; 2790 if (pm8001_dev) 2791 atomic_dec(&pm8001_dev->running_req); 2792 break; 2793 case IO_XFER_ERROR_BREAK: 2794 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2795 ts->resp = SAS_TASK_COMPLETE; 2796 ts->stat = SAS_INTERRUPTED; 2797 break; 2798 case IO_XFER_ERROR_PHY_NOT_READY: 2799 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2800 ts->resp = SAS_TASK_COMPLETE; 2801 ts->stat = SAS_OPEN_REJECT; 2802 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2803 break; 2804 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2805 pm8001_dbg(pm8001_ha, IO, 2806 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2807 ts->resp = SAS_TASK_COMPLETE; 2808 ts->stat = SAS_OPEN_REJECT; 2809 ts->open_rej_reason = SAS_OREJ_EPROTO; 2810 break; 2811 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2812 pm8001_dbg(pm8001_ha, IO, 2813 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2814 ts->resp = SAS_TASK_COMPLETE; 2815 ts->stat = SAS_OPEN_REJECT; 2816 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2817 break; 2818 case IO_OPEN_CNX_ERROR_BREAK: 2819 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2820 ts->resp = SAS_TASK_COMPLETE; 2821 ts->stat = SAS_OPEN_REJECT; 2822 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2823 break; 2824 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2825 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2826 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2827 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2828 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2829 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2830 pm8001_dbg(pm8001_ha, FAIL, 2831 "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2832 ts->resp = SAS_TASK_UNDELIVERED; 2833 ts->stat = SAS_DEV_NO_RESPONSE; 2834 if (!t->uldd_task) { 2835 pm8001_handle_event(pm8001_ha, 2836 pm8001_dev, 2837 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2838 ts->resp = SAS_TASK_COMPLETE; 2839 ts->stat = SAS_QUEUE_FULL; 2840 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2841 return; 2842 } 2843 break; 2844 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2845 pm8001_dbg(pm8001_ha, IO, 2846 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2847 ts->resp = SAS_TASK_UNDELIVERED; 2848 ts->stat = SAS_OPEN_REJECT; 2849 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2850 break; 2851 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2852 pm8001_dbg(pm8001_ha, IO, 2853 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2854 ts->resp = SAS_TASK_COMPLETE; 2855 ts->stat = SAS_OPEN_REJECT; 2856 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2857 break; 2858 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2859 pm8001_dbg(pm8001_ha, IO, 2860 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2861 ts->resp = SAS_TASK_COMPLETE; 2862 ts->stat = SAS_OPEN_REJECT; 2863 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2864 break; 2865 case IO_XFER_ERROR_NAK_RECEIVED: 2866 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2867 ts->resp = SAS_TASK_COMPLETE; 2868 ts->stat = SAS_NAK_R_ERR; 2869 break; 2870 case IO_XFER_ERROR_PEER_ABORTED: 2871 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n"); 2872 ts->resp = SAS_TASK_COMPLETE; 2873 ts->stat = SAS_NAK_R_ERR; 2874 break; 2875 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2876 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2877 ts->resp = SAS_TASK_COMPLETE; 2878 ts->stat = SAS_DATA_UNDERRUN; 2879 break; 2880 case IO_XFER_OPEN_RETRY_TIMEOUT: 2881 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2882 ts->resp = SAS_TASK_COMPLETE; 2883 ts->stat = SAS_OPEN_TO; 2884 break; 2885 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2886 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2887 ts->resp = SAS_TASK_COMPLETE; 2888 ts->stat = SAS_OPEN_TO; 2889 break; 2890 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2891 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2892 ts->resp = SAS_TASK_COMPLETE; 2893 ts->stat = SAS_OPEN_TO; 2894 break; 2895 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2896 pm8001_dbg(pm8001_ha, IO, 2897 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2898 ts->resp = SAS_TASK_COMPLETE; 2899 ts->stat = SAS_OPEN_TO; 2900 break; 2901 case IO_XFER_ERROR_OFFSET_MISMATCH: 2902 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2903 ts->resp = SAS_TASK_COMPLETE; 2904 ts->stat = SAS_OPEN_TO; 2905 break; 2906 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2907 pm8001_dbg(pm8001_ha, IO, 2908 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2909 ts->resp = SAS_TASK_COMPLETE; 2910 ts->stat = SAS_OPEN_TO; 2911 break; 2912 case IO_XFER_CMD_FRAME_ISSUED: 2913 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2914 break; 2915 case IO_XFER_PIO_SETUP_ERROR: 2916 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n"); 2917 ts->resp = SAS_TASK_COMPLETE; 2918 ts->stat = SAS_OPEN_TO; 2919 break; 2920 case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2921 pm8001_dbg(pm8001_ha, FAIL, 2922 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2923 /* TBC: used default set values */ 2924 ts->resp = SAS_TASK_COMPLETE; 2925 ts->stat = SAS_OPEN_TO; 2926 break; 2927 case IO_XFER_DMA_ACTIVATE_TIMEOUT: 2928 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n"); 2929 /* TBC: used default set values */ 2930 ts->resp = SAS_TASK_COMPLETE; 2931 ts->stat = SAS_OPEN_TO; 2932 break; 2933 default: 2934 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event); 2935 /* not allowed case. Therefore, return failed status */ 2936 ts->resp = SAS_TASK_COMPLETE; 2937 ts->stat = SAS_OPEN_TO; 2938 break; 2939 } 2940 spin_lock_irqsave(&t->task_state_lock, flags); 2941 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2942 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2943 t->task_state_flags |= SAS_TASK_STATE_DONE; 2944 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2945 spin_unlock_irqrestore(&t->task_state_lock, flags); 2946 pm8001_dbg(pm8001_ha, FAIL, 2947 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 2948 t, event, ts->resp, ts->stat); 2949 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2950 } else { 2951 spin_unlock_irqrestore(&t->task_state_lock, flags); 2952 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); 2953 } 2954 } 2955 2956 /*See the comments for mpi_ssp_completion */ 2957 static void 2958 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2959 { 2960 u32 param, i; 2961 struct sas_task *t; 2962 struct pm8001_ccb_info *ccb; 2963 unsigned long flags; 2964 u32 status; 2965 u32 tag; 2966 struct smp_completion_resp *psmpPayload; 2967 struct task_status_struct *ts; 2968 struct pm8001_device *pm8001_dev; 2969 char *pdma_respaddr = NULL; 2970 2971 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2972 status = le32_to_cpu(psmpPayload->status); 2973 tag = le32_to_cpu(psmpPayload->tag); 2974 2975 ccb = &pm8001_ha->ccb_info[tag]; 2976 param = le32_to_cpu(psmpPayload->param); 2977 t = ccb->task; 2978 ts = &t->task_status; 2979 pm8001_dev = ccb->device; 2980 if (status) 2981 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); 2982 if (unlikely(!t || !t->lldd_task || !t->dev)) 2983 return; 2984 2985 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status); 2986 2987 switch (status) { 2988 2989 case IO_SUCCESS: 2990 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2991 ts->resp = SAS_TASK_COMPLETE; 2992 ts->stat = SAM_STAT_GOOD; 2993 if (pm8001_dev) 2994 atomic_dec(&pm8001_dev->running_req); 2995 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 2996 pm8001_dbg(pm8001_ha, IO, 2997 "DIRECT RESPONSE Length:%d\n", 2998 param); 2999 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64 3000 ((u64)sg_dma_address 3001 (&t->smp_task.smp_resp)))); 3002 for (i = 0; i < param; i++) { 3003 *(pdma_respaddr+i) = psmpPayload->_r_a[i]; 3004 pm8001_dbg(pm8001_ha, IO, 3005 "SMP Byte%d DMA data 0x%x psmp 0x%x\n", 3006 i, *(pdma_respaddr + i), 3007 psmpPayload->_r_a[i]); 3008 } 3009 } 3010 break; 3011 case IO_ABORTED: 3012 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n"); 3013 ts->resp = SAS_TASK_COMPLETE; 3014 ts->stat = SAS_ABORTED_TASK; 3015 if (pm8001_dev) 3016 atomic_dec(&pm8001_dev->running_req); 3017 break; 3018 case IO_OVERFLOW: 3019 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 3020 ts->resp = SAS_TASK_COMPLETE; 3021 ts->stat = SAS_DATA_OVERRUN; 3022 ts->residual = 0; 3023 if (pm8001_dev) 3024 atomic_dec(&pm8001_dev->running_req); 3025 break; 3026 case IO_NO_DEVICE: 3027 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 3028 ts->resp = SAS_TASK_COMPLETE; 3029 ts->stat = SAS_PHY_DOWN; 3030 break; 3031 case IO_ERROR_HW_TIMEOUT: 3032 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n"); 3033 ts->resp = SAS_TASK_COMPLETE; 3034 ts->stat = SAM_STAT_BUSY; 3035 break; 3036 case IO_XFER_ERROR_BREAK: 3037 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 3038 ts->resp = SAS_TASK_COMPLETE; 3039 ts->stat = SAM_STAT_BUSY; 3040 break; 3041 case IO_XFER_ERROR_PHY_NOT_READY: 3042 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 3043 ts->resp = SAS_TASK_COMPLETE; 3044 ts->stat = SAM_STAT_BUSY; 3045 break; 3046 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3047 pm8001_dbg(pm8001_ha, IO, 3048 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 3049 ts->resp = SAS_TASK_COMPLETE; 3050 ts->stat = SAS_OPEN_REJECT; 3051 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3052 break; 3053 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3054 pm8001_dbg(pm8001_ha, IO, 3055 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 3056 ts->resp = SAS_TASK_COMPLETE; 3057 ts->stat = SAS_OPEN_REJECT; 3058 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3059 break; 3060 case IO_OPEN_CNX_ERROR_BREAK: 3061 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 3062 ts->resp = SAS_TASK_COMPLETE; 3063 ts->stat = SAS_OPEN_REJECT; 3064 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 3065 break; 3066 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3067 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 3068 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 3069 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 3070 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 3071 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 3072 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 3073 ts->resp = SAS_TASK_COMPLETE; 3074 ts->stat = SAS_OPEN_REJECT; 3075 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3076 pm8001_handle_event(pm8001_ha, 3077 pm8001_dev, 3078 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 3079 break; 3080 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3081 pm8001_dbg(pm8001_ha, IO, 3082 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 3083 ts->resp = SAS_TASK_COMPLETE; 3084 ts->stat = SAS_OPEN_REJECT; 3085 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 3086 break; 3087 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3088 pm8001_dbg(pm8001_ha, IO, 3089 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 3090 ts->resp = SAS_TASK_COMPLETE; 3091 ts->stat = SAS_OPEN_REJECT; 3092 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 3093 break; 3094 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3095 pm8001_dbg(pm8001_ha, IO, 3096 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 3097 ts->resp = SAS_TASK_COMPLETE; 3098 ts->stat = SAS_OPEN_REJECT; 3099 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 3100 break; 3101 case IO_XFER_ERROR_RX_FRAME: 3102 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n"); 3103 ts->resp = SAS_TASK_COMPLETE; 3104 ts->stat = SAS_DEV_NO_RESPONSE; 3105 break; 3106 case IO_XFER_OPEN_RETRY_TIMEOUT: 3107 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 3108 ts->resp = SAS_TASK_COMPLETE; 3109 ts->stat = SAS_OPEN_REJECT; 3110 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3111 break; 3112 case IO_ERROR_INTERNAL_SMP_RESOURCE: 3113 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n"); 3114 ts->resp = SAS_TASK_COMPLETE; 3115 ts->stat = SAS_QUEUE_FULL; 3116 break; 3117 case IO_PORT_IN_RESET: 3118 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 3119 ts->resp = SAS_TASK_COMPLETE; 3120 ts->stat = SAS_OPEN_REJECT; 3121 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3122 break; 3123 case IO_DS_NON_OPERATIONAL: 3124 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 3125 ts->resp = SAS_TASK_COMPLETE; 3126 ts->stat = SAS_DEV_NO_RESPONSE; 3127 break; 3128 case IO_DS_IN_RECOVERY: 3129 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 3130 ts->resp = SAS_TASK_COMPLETE; 3131 ts->stat = SAS_OPEN_REJECT; 3132 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3133 break; 3134 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3135 pm8001_dbg(pm8001_ha, IO, 3136 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 3137 ts->resp = SAS_TASK_COMPLETE; 3138 ts->stat = SAS_OPEN_REJECT; 3139 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3140 break; 3141 default: 3142 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 3143 ts->resp = SAS_TASK_COMPLETE; 3144 ts->stat = SAS_DEV_NO_RESPONSE; 3145 /* not allowed case. Therefore, return failed status */ 3146 break; 3147 } 3148 spin_lock_irqsave(&t->task_state_lock, flags); 3149 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3150 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3151 t->task_state_flags |= SAS_TASK_STATE_DONE; 3152 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3153 spin_unlock_irqrestore(&t->task_state_lock, flags); 3154 pm8001_dbg(pm8001_ha, FAIL, 3155 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n", 3156 t, status, ts->resp, ts->stat); 3157 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3158 } else { 3159 spin_unlock_irqrestore(&t->task_state_lock, flags); 3160 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3161 mb();/* in order to force CPU ordering */ 3162 t->task_done(t); 3163 } 3164 } 3165 3166 /** 3167 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3168 * @pm8001_ha: our hba card information 3169 * @Qnum: the outbound queue message number. 3170 * @SEA: source of event to ack 3171 * @port_id: port id. 3172 * @phyId: phy id. 3173 * @param0: parameter 0. 3174 * @param1: parameter 1. 3175 */ 3176 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3177 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3178 { 3179 struct hw_event_ack_req payload; 3180 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3181 3182 struct inbound_queue_table *circularQ; 3183 3184 memset((u8 *)&payload, 0, sizeof(payload)); 3185 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 3186 payload.tag = cpu_to_le32(1); 3187 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3188 ((phyId & 0xFF) << 24) | (port_id & 0xFF)); 3189 payload.param0 = cpu_to_le32(param0); 3190 payload.param1 = cpu_to_le32(param1); 3191 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 3192 sizeof(payload), 0); 3193 } 3194 3195 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3196 u32 phyId, u32 phy_op); 3197 3198 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha, 3199 void *piomb) 3200 { 3201 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4); 3202 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3203 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3204 u32 lr_status_evt_portid = 3205 le32_to_cpu(pPayload->lr_status_evt_portid); 3206 u8 deviceType = pPayload->sas_identify.dev_type; 3207 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3208 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3209 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3210 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3211 3212 if (deviceType == SAS_END_DEVICE) { 3213 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3214 PHY_NOTIFY_ENABLE_SPINUP); 3215 } 3216 3217 port->wide_port_phymap |= (1U << phy_id); 3218 pm8001_get_lrate_mode(phy, link_rate); 3219 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3220 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3221 phy->phy_attached = 1; 3222 } 3223 3224 /** 3225 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3226 * @pm8001_ha: our hba card information 3227 * @piomb: IO message buffer 3228 */ 3229 static void 3230 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3231 { 3232 struct hw_event_resp *pPayload = 3233 (struct hw_event_resp *)(piomb + 4); 3234 u32 lr_status_evt_portid = 3235 le32_to_cpu(pPayload->lr_status_evt_portid); 3236 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3237 3238 u8 link_rate = 3239 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3240 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3241 u8 phy_id = 3242 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3243 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3244 3245 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3246 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3247 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3248 unsigned long flags; 3249 u8 deviceType = pPayload->sas_identify.dev_type; 3250 port->port_state = portstate; 3251 port->wide_port_phymap |= (1U << phy_id); 3252 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3253 pm8001_dbg(pm8001_ha, MSG, 3254 "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n", 3255 port_id, phy_id, link_rate, portstate, deviceType); 3256 3257 switch (deviceType) { 3258 case SAS_PHY_UNUSED: 3259 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n"); 3260 break; 3261 case SAS_END_DEVICE: 3262 pm8001_dbg(pm8001_ha, MSG, "end device.\n"); 3263 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3264 PHY_NOTIFY_ENABLE_SPINUP); 3265 port->port_attached = 1; 3266 pm8001_get_lrate_mode(phy, link_rate); 3267 break; 3268 case SAS_EDGE_EXPANDER_DEVICE: 3269 pm8001_dbg(pm8001_ha, MSG, "expander device.\n"); 3270 port->port_attached = 1; 3271 pm8001_get_lrate_mode(phy, link_rate); 3272 break; 3273 case SAS_FANOUT_EXPANDER_DEVICE: 3274 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n"); 3275 port->port_attached = 1; 3276 pm8001_get_lrate_mode(phy, link_rate); 3277 break; 3278 default: 3279 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n", 3280 deviceType); 3281 break; 3282 } 3283 phy->phy_type |= PORT_TYPE_SAS; 3284 phy->identify.device_type = deviceType; 3285 phy->phy_attached = 1; 3286 if (phy->identify.device_type == SAS_END_DEVICE) 3287 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3288 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3289 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3290 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3291 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3292 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3293 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3294 sizeof(struct sas_identify_frame)-4); 3295 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3296 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3297 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3298 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3299 mdelay(200); /* delay a moment to wait for disk to spin up */ 3300 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3301 } 3302 3303 /** 3304 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3305 * @pm8001_ha: our hba card information 3306 * @piomb: IO message buffer 3307 */ 3308 static void 3309 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3310 { 3311 struct hw_event_resp *pPayload = 3312 (struct hw_event_resp *)(piomb + 4); 3313 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3314 u32 lr_status_evt_portid = 3315 le32_to_cpu(pPayload->lr_status_evt_portid); 3316 u8 link_rate = 3317 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3318 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3319 u8 phy_id = 3320 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3321 3322 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3323 3324 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3325 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3326 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3327 unsigned long flags; 3328 pm8001_dbg(pm8001_ha, DEVIO, 3329 "port id %d, phy id %d link_rate %d portstate 0x%x\n", 3330 port_id, phy_id, link_rate, portstate); 3331 3332 port->port_state = portstate; 3333 phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3334 port->port_attached = 1; 3335 pm8001_get_lrate_mode(phy, link_rate); 3336 phy->phy_type |= PORT_TYPE_SATA; 3337 phy->phy_attached = 1; 3338 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3339 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3340 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3341 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3342 sizeof(struct dev_to_host_fis)); 3343 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3344 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3345 phy->identify.device_type = SAS_SATA_DEV; 3346 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3347 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3348 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3349 } 3350 3351 /** 3352 * hw_event_phy_down -we should notify the libsas the phy is down. 3353 * @pm8001_ha: our hba card information 3354 * @piomb: IO message buffer 3355 */ 3356 static void 3357 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3358 { 3359 struct hw_event_resp *pPayload = 3360 (struct hw_event_resp *)(piomb + 4); 3361 3362 u32 lr_status_evt_portid = 3363 le32_to_cpu(pPayload->lr_status_evt_portid); 3364 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3365 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3366 u8 phy_id = 3367 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3368 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3369 3370 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3371 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3372 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA); 3373 port->port_state = portstate; 3374 phy->identify.device_type = 0; 3375 phy->phy_attached = 0; 3376 switch (portstate) { 3377 case PORT_VALID: 3378 break; 3379 case PORT_INVALID: 3380 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n", 3381 port_id); 3382 pm8001_dbg(pm8001_ha, MSG, 3383 " Last phy Down and port invalid\n"); 3384 if (port_sata) { 3385 phy->phy_type = 0; 3386 port->port_attached = 0; 3387 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3388 port_id, phy_id, 0, 0); 3389 } 3390 sas_phy_disconnected(&phy->sas_phy); 3391 break; 3392 case PORT_IN_RESET: 3393 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n", 3394 port_id); 3395 break; 3396 case PORT_NOT_ESTABLISHED: 3397 pm8001_dbg(pm8001_ha, MSG, 3398 " Phy Down and PORT_NOT_ESTABLISHED\n"); 3399 port->port_attached = 0; 3400 break; 3401 case PORT_LOSTCOMM: 3402 pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n"); 3403 pm8001_dbg(pm8001_ha, MSG, 3404 " Last phy Down and port invalid\n"); 3405 if (port_sata) { 3406 port->port_attached = 0; 3407 phy->phy_type = 0; 3408 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3409 port_id, phy_id, 0, 0); 3410 } 3411 sas_phy_disconnected(&phy->sas_phy); 3412 break; 3413 default: 3414 port->port_attached = 0; 3415 pm8001_dbg(pm8001_ha, DEVIO, 3416 " Phy Down and(default) = 0x%x\n", 3417 portstate); 3418 break; 3419 3420 } 3421 if (port_sata && (portstate != PORT_IN_RESET)) { 3422 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3423 3424 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); 3425 } 3426 } 3427 3428 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3429 { 3430 struct phy_start_resp *pPayload = 3431 (struct phy_start_resp *)(piomb + 4); 3432 u32 status = 3433 le32_to_cpu(pPayload->status); 3434 u32 phy_id = 3435 le32_to_cpu(pPayload->phyid); 3436 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3437 3438 pm8001_dbg(pm8001_ha, INIT, 3439 "phy start resp status:0x%x, phyid:0x%x\n", 3440 status, phy_id); 3441 if (status == 0) { 3442 phy->phy_state = PHY_LINK_DOWN; 3443 if (pm8001_ha->flags == PM8001F_RUN_TIME && 3444 phy->enable_completion != NULL) { 3445 complete(phy->enable_completion); 3446 phy->enable_completion = NULL; 3447 } 3448 } 3449 return 0; 3450 3451 } 3452 3453 /** 3454 * mpi_thermal_hw_event -The hw event has come. 3455 * @pm8001_ha: our hba card information 3456 * @piomb: IO message buffer 3457 */ 3458 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3459 { 3460 struct thermal_hw_event *pPayload = 3461 (struct thermal_hw_event *)(piomb + 4); 3462 3463 u32 thermal_event = le32_to_cpu(pPayload->thermal_event); 3464 u32 rht_lht = le32_to_cpu(pPayload->rht_lht); 3465 3466 if (thermal_event & 0x40) { 3467 pm8001_dbg(pm8001_ha, IO, 3468 "Thermal Event: Local high temperature violated!\n"); 3469 pm8001_dbg(pm8001_ha, IO, 3470 "Thermal Event: Measured local high temperature %d\n", 3471 ((rht_lht & 0xFF00) >> 8)); 3472 } 3473 if (thermal_event & 0x10) { 3474 pm8001_dbg(pm8001_ha, IO, 3475 "Thermal Event: Remote high temperature violated!\n"); 3476 pm8001_dbg(pm8001_ha, IO, 3477 "Thermal Event: Measured remote high temperature %d\n", 3478 ((rht_lht & 0xFF000000) >> 24)); 3479 } 3480 return 0; 3481 } 3482 3483 /** 3484 * mpi_hw_event -The hw event has come. 3485 * @pm8001_ha: our hba card information 3486 * @piomb: IO message buffer 3487 */ 3488 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3489 { 3490 unsigned long flags, i; 3491 struct hw_event_resp *pPayload = 3492 (struct hw_event_resp *)(piomb + 4); 3493 u32 lr_status_evt_portid = 3494 le32_to_cpu(pPayload->lr_status_evt_portid); 3495 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3496 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3497 u8 phy_id = 3498 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3499 u16 eventType = 3500 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); 3501 u8 status = 3502 (u8)((lr_status_evt_portid & 0x0F000000) >> 24); 3503 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3504 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3505 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3506 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3507 pm8001_dbg(pm8001_ha, DEV, 3508 "portid:%d phyid:%d event:0x%x status:0x%x\n", 3509 port_id, phy_id, eventType, status); 3510 3511 switch (eventType) { 3512 3513 case HW_EVENT_SAS_PHY_UP: 3514 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n"); 3515 hw_event_sas_phy_up(pm8001_ha, piomb); 3516 break; 3517 case HW_EVENT_SATA_PHY_UP: 3518 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n"); 3519 hw_event_sata_phy_up(pm8001_ha, piomb); 3520 break; 3521 case HW_EVENT_SATA_SPINUP_HOLD: 3522 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n"); 3523 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 3524 break; 3525 case HW_EVENT_PHY_DOWN: 3526 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n"); 3527 hw_event_phy_down(pm8001_ha, piomb); 3528 if (pm8001_ha->reset_in_progress) { 3529 pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n"); 3530 return 0; 3531 } 3532 phy->phy_attached = 0; 3533 phy->phy_state = PHY_LINK_DISABLE; 3534 break; 3535 case HW_EVENT_PORT_INVALID: 3536 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n"); 3537 sas_phy_disconnected(sas_phy); 3538 phy->phy_attached = 0; 3539 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3540 break; 3541 /* the broadcast change primitive received, tell the LIBSAS this event 3542 to revalidate the sas domain*/ 3543 case HW_EVENT_BROADCAST_CHANGE: 3544 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n"); 3545 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3546 port_id, phy_id, 1, 0); 3547 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3548 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3549 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3550 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3551 break; 3552 case HW_EVENT_PHY_ERROR: 3553 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n"); 3554 sas_phy_disconnected(&phy->sas_phy); 3555 phy->phy_attached = 0; 3556 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 3557 break; 3558 case HW_EVENT_BROADCAST_EXP: 3559 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n"); 3560 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3561 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3562 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3563 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3564 break; 3565 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3566 pm8001_dbg(pm8001_ha, MSG, 3567 "HW_EVENT_LINK_ERR_INVALID_DWORD\n"); 3568 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3569 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3570 break; 3571 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3572 pm8001_dbg(pm8001_ha, MSG, 3573 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"); 3574 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3575 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3576 port_id, phy_id, 0, 0); 3577 break; 3578 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3579 pm8001_dbg(pm8001_ha, MSG, 3580 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n"); 3581 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3582 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3583 port_id, phy_id, 0, 0); 3584 break; 3585 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3586 pm8001_dbg(pm8001_ha, MSG, 3587 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"); 3588 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3589 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3590 port_id, phy_id, 0, 0); 3591 break; 3592 case HW_EVENT_MALFUNCTION: 3593 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n"); 3594 break; 3595 case HW_EVENT_BROADCAST_SES: 3596 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n"); 3597 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3598 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3599 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3600 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3601 break; 3602 case HW_EVENT_INBOUND_CRC_ERROR: 3603 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n"); 3604 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3605 HW_EVENT_INBOUND_CRC_ERROR, 3606 port_id, phy_id, 0, 0); 3607 break; 3608 case HW_EVENT_HARD_RESET_RECEIVED: 3609 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n"); 3610 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3611 break; 3612 case HW_EVENT_ID_FRAME_TIMEOUT: 3613 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n"); 3614 sas_phy_disconnected(sas_phy); 3615 phy->phy_attached = 0; 3616 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3617 break; 3618 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3619 pm8001_dbg(pm8001_ha, MSG, 3620 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"); 3621 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3622 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3623 port_id, phy_id, 0, 0); 3624 sas_phy_disconnected(sas_phy); 3625 phy->phy_attached = 0; 3626 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3627 break; 3628 case HW_EVENT_PORT_RESET_TIMER_TMO: 3629 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n"); 3630 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3631 port_id, phy_id, 0, 0); 3632 sas_phy_disconnected(sas_phy); 3633 phy->phy_attached = 0; 3634 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3635 if (pm8001_ha->phy[phy_id].reset_completion) { 3636 pm8001_ha->phy[phy_id].port_reset_status = 3637 PORT_RESET_TMO; 3638 complete(pm8001_ha->phy[phy_id].reset_completion); 3639 pm8001_ha->phy[phy_id].reset_completion = NULL; 3640 } 3641 break; 3642 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3643 pm8001_dbg(pm8001_ha, MSG, 3644 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"); 3645 pm80xx_hw_event_ack_req(pm8001_ha, 0, 3646 HW_EVENT_PORT_RECOVERY_TIMER_TMO, 3647 port_id, phy_id, 0, 0); 3648 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 3649 if (port->wide_port_phymap & (1 << i)) { 3650 phy = &pm8001_ha->phy[i]; 3651 sas_ha->notify_phy_event(&phy->sas_phy, 3652 PHYE_LOSS_OF_SIGNAL); 3653 port->wide_port_phymap &= ~(1 << i); 3654 } 3655 } 3656 break; 3657 case HW_EVENT_PORT_RECOVER: 3658 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n"); 3659 hw_event_port_recover(pm8001_ha, piomb); 3660 break; 3661 case HW_EVENT_PORT_RESET_COMPLETE: 3662 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n"); 3663 if (pm8001_ha->phy[phy_id].reset_completion) { 3664 pm8001_ha->phy[phy_id].port_reset_status = 3665 PORT_RESET_SUCCESS; 3666 complete(pm8001_ha->phy[phy_id].reset_completion); 3667 pm8001_ha->phy[phy_id].reset_completion = NULL; 3668 } 3669 break; 3670 case EVENT_BROADCAST_ASYNCH_EVENT: 3671 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n"); 3672 break; 3673 default: 3674 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n", 3675 eventType); 3676 break; 3677 } 3678 return 0; 3679 } 3680 3681 /** 3682 * mpi_phy_stop_resp - SPCv specific 3683 * @pm8001_ha: our hba card information 3684 * @piomb: IO message buffer 3685 */ 3686 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3687 { 3688 struct phy_stop_resp *pPayload = 3689 (struct phy_stop_resp *)(piomb + 4); 3690 u32 status = 3691 le32_to_cpu(pPayload->status); 3692 u32 phyid = 3693 le32_to_cpu(pPayload->phyid) & 0xFF; 3694 struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; 3695 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n", 3696 phyid, status); 3697 if (status == PHY_STOP_SUCCESS || 3698 status == PHY_STOP_ERR_DEVICE_ATTACHED) 3699 phy->phy_state = PHY_LINK_DISABLE; 3700 return 0; 3701 } 3702 3703 /** 3704 * mpi_set_controller_config_resp - SPCv specific 3705 * @pm8001_ha: our hba card information 3706 * @piomb: IO message buffer 3707 */ 3708 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3709 void *piomb) 3710 { 3711 struct set_ctrl_cfg_resp *pPayload = 3712 (struct set_ctrl_cfg_resp *)(piomb + 4); 3713 u32 status = le32_to_cpu(pPayload->status); 3714 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); 3715 3716 pm8001_dbg(pm8001_ha, MSG, 3717 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", 3718 status, err_qlfr_pgcd); 3719 3720 return 0; 3721 } 3722 3723 /** 3724 * mpi_get_controller_config_resp - SPCv specific 3725 * @pm8001_ha: our hba card information 3726 * @piomb: IO message buffer 3727 */ 3728 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3729 void *piomb) 3730 { 3731 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3732 3733 return 0; 3734 } 3735 3736 /** 3737 * mpi_get_phy_profile_resp - SPCv specific 3738 * @pm8001_ha: our hba card information 3739 * @piomb: IO message buffer 3740 */ 3741 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3742 void *piomb) 3743 { 3744 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3745 3746 return 0; 3747 } 3748 3749 /** 3750 * mpi_flash_op_ext_resp - SPCv specific 3751 * @pm8001_ha: our hba card information 3752 * @piomb: IO message buffer 3753 */ 3754 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3755 { 3756 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3757 3758 return 0; 3759 } 3760 3761 /** 3762 * mpi_set_phy_profile_resp - SPCv specific 3763 * @pm8001_ha: our hba card information 3764 * @piomb: IO message buffer 3765 */ 3766 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3767 void *piomb) 3768 { 3769 u32 tag; 3770 u8 page_code; 3771 int rc = 0; 3772 struct set_phy_profile_resp *pPayload = 3773 (struct set_phy_profile_resp *)(piomb + 4); 3774 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); 3775 u32 status = le32_to_cpu(pPayload->status); 3776 3777 tag = le32_to_cpu(pPayload->tag); 3778 page_code = (u8)((ppc_phyid & 0xFF00) >> 8); 3779 if (status) { 3780 /* status is FAILED */ 3781 pm8001_dbg(pm8001_ha, FAIL, 3782 "PhyProfile command failed with status 0x%08X\n", 3783 status); 3784 rc = -1; 3785 } else { 3786 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) { 3787 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n", 3788 page_code); 3789 rc = -1; 3790 } 3791 } 3792 pm8001_tag_free(pm8001_ha, tag); 3793 return rc; 3794 } 3795 3796 /** 3797 * mpi_kek_management_resp - SPCv specific 3798 * @pm8001_ha: our hba card information 3799 * @piomb: IO message buffer 3800 */ 3801 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, 3802 void *piomb) 3803 { 3804 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); 3805 3806 u32 status = le32_to_cpu(pPayload->status); 3807 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); 3808 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); 3809 3810 pm8001_dbg(pm8001_ha, MSG, 3811 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", 3812 status, kidx_new_curr_ksop, err_qlfr); 3813 3814 return 0; 3815 } 3816 3817 /** 3818 * mpi_dek_management_resp - SPCv specific 3819 * @pm8001_ha: our hba card information 3820 * @piomb: IO message buffer 3821 */ 3822 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, 3823 void *piomb) 3824 { 3825 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3826 3827 return 0; 3828 } 3829 3830 /** 3831 * ssp_coalesced_comp_resp - SPCv specific 3832 * @pm8001_ha: our hba card information 3833 * @piomb: IO message buffer 3834 */ 3835 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, 3836 void *piomb) 3837 { 3838 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3839 3840 return 0; 3841 } 3842 3843 /** 3844 * process_one_iomb - process one outbound Queue memory block 3845 * @pm8001_ha: our hba card information 3846 * @piomb: IO message buffer 3847 */ 3848 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3849 { 3850 __le32 pHeader = *(__le32 *)piomb; 3851 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); 3852 3853 switch (opc) { 3854 case OPC_OUB_ECHO: 3855 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n"); 3856 break; 3857 case OPC_OUB_HW_EVENT: 3858 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n"); 3859 mpi_hw_event(pm8001_ha, piomb); 3860 break; 3861 case OPC_OUB_THERM_HW_EVENT: 3862 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n"); 3863 mpi_thermal_hw_event(pm8001_ha, piomb); 3864 break; 3865 case OPC_OUB_SSP_COMP: 3866 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n"); 3867 mpi_ssp_completion(pm8001_ha, piomb); 3868 break; 3869 case OPC_OUB_SMP_COMP: 3870 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n"); 3871 mpi_smp_completion(pm8001_ha, piomb); 3872 break; 3873 case OPC_OUB_LOCAL_PHY_CNTRL: 3874 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n"); 3875 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3876 break; 3877 case OPC_OUB_DEV_REGIST: 3878 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n"); 3879 pm8001_mpi_reg_resp(pm8001_ha, piomb); 3880 break; 3881 case OPC_OUB_DEREG_DEV: 3882 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n"); 3883 pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3884 break; 3885 case OPC_OUB_GET_DEV_HANDLE: 3886 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n"); 3887 break; 3888 case OPC_OUB_SATA_COMP: 3889 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n"); 3890 mpi_sata_completion(pm8001_ha, piomb); 3891 break; 3892 case OPC_OUB_SATA_EVENT: 3893 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n"); 3894 mpi_sata_event(pm8001_ha, piomb); 3895 break; 3896 case OPC_OUB_SSP_EVENT: 3897 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n"); 3898 mpi_ssp_event(pm8001_ha, piomb); 3899 break; 3900 case OPC_OUB_DEV_HANDLE_ARRIV: 3901 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n"); 3902 /*This is for target*/ 3903 break; 3904 case OPC_OUB_SSP_RECV_EVENT: 3905 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n"); 3906 /*This is for target*/ 3907 break; 3908 case OPC_OUB_FW_FLASH_UPDATE: 3909 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n"); 3910 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3911 break; 3912 case OPC_OUB_GPIO_RESPONSE: 3913 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n"); 3914 break; 3915 case OPC_OUB_GPIO_EVENT: 3916 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n"); 3917 break; 3918 case OPC_OUB_GENERAL_EVENT: 3919 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n"); 3920 pm8001_mpi_general_event(pm8001_ha, piomb); 3921 break; 3922 case OPC_OUB_SSP_ABORT_RSP: 3923 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n"); 3924 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3925 break; 3926 case OPC_OUB_SATA_ABORT_RSP: 3927 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n"); 3928 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3929 break; 3930 case OPC_OUB_SAS_DIAG_MODE_START_END: 3931 pm8001_dbg(pm8001_ha, MSG, 3932 "OPC_OUB_SAS_DIAG_MODE_START_END\n"); 3933 break; 3934 case OPC_OUB_SAS_DIAG_EXECUTE: 3935 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n"); 3936 break; 3937 case OPC_OUB_GET_TIME_STAMP: 3938 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n"); 3939 break; 3940 case OPC_OUB_SAS_HW_EVENT_ACK: 3941 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n"); 3942 break; 3943 case OPC_OUB_PORT_CONTROL: 3944 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n"); 3945 break; 3946 case OPC_OUB_SMP_ABORT_RSP: 3947 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n"); 3948 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3949 break; 3950 case OPC_OUB_GET_NVMD_DATA: 3951 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n"); 3952 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 3953 break; 3954 case OPC_OUB_SET_NVMD_DATA: 3955 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n"); 3956 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 3957 break; 3958 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3959 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n"); 3960 break; 3961 case OPC_OUB_SET_DEVICE_STATE: 3962 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n"); 3963 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 3964 break; 3965 case OPC_OUB_GET_DEVICE_STATE: 3966 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n"); 3967 break; 3968 case OPC_OUB_SET_DEV_INFO: 3969 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n"); 3970 break; 3971 /* spcv specifc commands */ 3972 case OPC_OUB_PHY_START_RESP: 3973 pm8001_dbg(pm8001_ha, MSG, 3974 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc); 3975 mpi_phy_start_resp(pm8001_ha, piomb); 3976 break; 3977 case OPC_OUB_PHY_STOP_RESP: 3978 pm8001_dbg(pm8001_ha, MSG, 3979 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc); 3980 mpi_phy_stop_resp(pm8001_ha, piomb); 3981 break; 3982 case OPC_OUB_SET_CONTROLLER_CONFIG: 3983 pm8001_dbg(pm8001_ha, MSG, 3984 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc); 3985 mpi_set_controller_config_resp(pm8001_ha, piomb); 3986 break; 3987 case OPC_OUB_GET_CONTROLLER_CONFIG: 3988 pm8001_dbg(pm8001_ha, MSG, 3989 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc); 3990 mpi_get_controller_config_resp(pm8001_ha, piomb); 3991 break; 3992 case OPC_OUB_GET_PHY_PROFILE: 3993 pm8001_dbg(pm8001_ha, MSG, 3994 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc); 3995 mpi_get_phy_profile_resp(pm8001_ha, piomb); 3996 break; 3997 case OPC_OUB_FLASH_OP_EXT: 3998 pm8001_dbg(pm8001_ha, MSG, 3999 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc); 4000 mpi_flash_op_ext_resp(pm8001_ha, piomb); 4001 break; 4002 case OPC_OUB_SET_PHY_PROFILE: 4003 pm8001_dbg(pm8001_ha, MSG, 4004 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc); 4005 mpi_set_phy_profile_resp(pm8001_ha, piomb); 4006 break; 4007 case OPC_OUB_KEK_MANAGEMENT_RESP: 4008 pm8001_dbg(pm8001_ha, MSG, 4009 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc); 4010 mpi_kek_management_resp(pm8001_ha, piomb); 4011 break; 4012 case OPC_OUB_DEK_MANAGEMENT_RESP: 4013 pm8001_dbg(pm8001_ha, MSG, 4014 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc); 4015 mpi_dek_management_resp(pm8001_ha, piomb); 4016 break; 4017 case OPC_OUB_SSP_COALESCED_COMP_RESP: 4018 pm8001_dbg(pm8001_ha, MSG, 4019 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc); 4020 ssp_coalesced_comp_resp(pm8001_ha, piomb); 4021 break; 4022 default: 4023 pm8001_dbg(pm8001_ha, DEVIO, 4024 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc); 4025 break; 4026 } 4027 } 4028 4029 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha) 4030 { 4031 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n", 4032 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); 4033 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n", 4034 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)); 4035 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n", 4036 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)); 4037 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n", 4038 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); 4039 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n", 4040 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)); 4041 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n", 4042 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)); 4043 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n", 4044 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)); 4045 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n", 4046 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)); 4047 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n", 4048 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)); 4049 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n", 4050 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)); 4051 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n", 4052 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)); 4053 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n", 4054 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)); 4055 } 4056 4057 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4058 { 4059 struct outbound_queue_table *circularQ; 4060 void *pMsg1 = NULL; 4061 u8 bc; 4062 u32 ret = MPI_IO_STATUS_FAIL; 4063 unsigned long flags; 4064 u32 regval; 4065 4066 if (vec == (pm8001_ha->max_q_num - 1)) { 4067 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 4068 if ((regval & SCRATCH_PAD_MIPSALL_READY) != 4069 SCRATCH_PAD_MIPSALL_READY) { 4070 pm8001_ha->controller_fatal_error = true; 4071 pm8001_dbg(pm8001_ha, FAIL, 4072 "Firmware Fatal error! Regval:0x%x\n", 4073 regval); 4074 print_scratchpad_registers(pm8001_ha); 4075 return ret; 4076 } 4077 } 4078 spin_lock_irqsave(&pm8001_ha->lock, flags); 4079 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4080 do { 4081 /* spurious interrupt during setup if kexec-ing and 4082 * driver doing a doorbell access w/ the pre-kexec oq 4083 * interrupt setup. 4084 */ 4085 if (!circularQ->pi_virt) 4086 break; 4087 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4088 if (MPI_IO_STATUS_SUCCESS == ret) { 4089 /* process the outbound message */ 4090 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 4091 /* free the message from the outbound circular buffer */ 4092 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4093 circularQ, bc); 4094 } 4095 if (MPI_IO_STATUS_BUSY == ret) { 4096 /* Update the producer index from SPC */ 4097 circularQ->producer_index = 4098 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4099 if (le32_to_cpu(circularQ->producer_index) == 4100 circularQ->consumer_idx) 4101 /* OQ is empty */ 4102 break; 4103 } 4104 } while (1); 4105 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 4106 return ret; 4107 } 4108 4109 /* DMA_... to our direction translation. */ 4110 static const u8 data_dir_flags[] = { 4111 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4112 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4113 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4114 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4115 }; 4116 4117 static void build_smp_cmd(u32 deviceID, __le32 hTag, 4118 struct smp_req *psmp_cmd, int mode, int length) 4119 { 4120 psmp_cmd->tag = hTag; 4121 psmp_cmd->device_id = cpu_to_le32(deviceID); 4122 if (mode == SMP_DIRECT) { 4123 length = length - 4; /* subtract crc */ 4124 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); 4125 } else { 4126 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4127 } 4128 } 4129 4130 /** 4131 * pm8001_chip_smp_req - send a SMP task to FW 4132 * @pm8001_ha: our hba card information. 4133 * @ccb: the ccb information this request used. 4134 */ 4135 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4136 struct pm8001_ccb_info *ccb) 4137 { 4138 int elem, rc; 4139 struct sas_task *task = ccb->task; 4140 struct domain_device *dev = task->dev; 4141 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4142 struct scatterlist *sg_req, *sg_resp; 4143 u32 req_len, resp_len; 4144 struct smp_req smp_cmd; 4145 u32 opc; 4146 struct inbound_queue_table *circularQ; 4147 char *preq_dma_addr = NULL; 4148 __le64 tmp_addr; 4149 u32 i, length; 4150 4151 memset(&smp_cmd, 0, sizeof(smp_cmd)); 4152 /* 4153 * DMA-map SMP request, response buffers 4154 */ 4155 sg_req = &task->smp_task.smp_req; 4156 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4157 if (!elem) 4158 return -ENOMEM; 4159 req_len = sg_dma_len(sg_req); 4160 4161 sg_resp = &task->smp_task.smp_resp; 4162 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4163 if (!elem) { 4164 rc = -ENOMEM; 4165 goto err_out; 4166 } 4167 resp_len = sg_dma_len(sg_resp); 4168 /* must be in dwords */ 4169 if ((req_len & 0x3) || (resp_len & 0x3)) { 4170 rc = -EINVAL; 4171 goto err_out_2; 4172 } 4173 4174 opc = OPC_INB_SMP_REQUEST; 4175 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4176 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4177 4178 length = sg_req->length; 4179 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length); 4180 if (!(length - 8)) 4181 pm8001_ha->smp_exp_mode = SMP_DIRECT; 4182 else 4183 pm8001_ha->smp_exp_mode = SMP_INDIRECT; 4184 4185 4186 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 4187 preq_dma_addr = (char *)phys_to_virt(tmp_addr); 4188 4189 /* INDIRECT MODE command settings. Use DMA */ 4190 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { 4191 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n"); 4192 /* for SPCv indirect mode. Place the top 4 bytes of 4193 * SMP Request header here. */ 4194 for (i = 0; i < 4; i++) 4195 smp_cmd.smp_req16[i] = *(preq_dma_addr + i); 4196 /* exclude top 4 bytes for SMP req header */ 4197 smp_cmd.long_smp_req.long_req_addr = 4198 cpu_to_le64((u64)sg_dma_address 4199 (&task->smp_task.smp_req) + 4); 4200 /* exclude 4 bytes for SMP req header and CRC */ 4201 smp_cmd.long_smp_req.long_req_size = 4202 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); 4203 smp_cmd.long_smp_req.long_resp_addr = 4204 cpu_to_le64((u64)sg_dma_address 4205 (&task->smp_task.smp_resp)); 4206 smp_cmd.long_smp_req.long_resp_size = 4207 cpu_to_le32((u32)sg_dma_len 4208 (&task->smp_task.smp_resp)-4); 4209 } else { /* DIRECT MODE */ 4210 smp_cmd.long_smp_req.long_req_addr = 4211 cpu_to_le64((u64)sg_dma_address 4212 (&task->smp_task.smp_req)); 4213 smp_cmd.long_smp_req.long_req_size = 4214 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4215 smp_cmd.long_smp_req.long_resp_addr = 4216 cpu_to_le64((u64)sg_dma_address 4217 (&task->smp_task.smp_resp)); 4218 smp_cmd.long_smp_req.long_resp_size = 4219 cpu_to_le32 4220 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4221 } 4222 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 4223 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n"); 4224 for (i = 0; i < length; i++) 4225 if (i < 16) { 4226 smp_cmd.smp_req16[i] = *(preq_dma_addr+i); 4227 pm8001_dbg(pm8001_ha, IO, 4228 "Byte[%d]:%x (DMA data:%x)\n", 4229 i, smp_cmd.smp_req16[i], 4230 *(preq_dma_addr)); 4231 } else { 4232 smp_cmd.smp_req[i] = *(preq_dma_addr+i); 4233 pm8001_dbg(pm8001_ha, IO, 4234 "Byte[%d]:%x (DMA data:%x)\n", 4235 i, smp_cmd.smp_req[i], 4236 *(preq_dma_addr)); 4237 } 4238 } 4239 4240 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, 4241 &smp_cmd, pm8001_ha->smp_exp_mode, length); 4242 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd, 4243 sizeof(smp_cmd), 0); 4244 if (rc) 4245 goto err_out_2; 4246 return 0; 4247 4248 err_out_2: 4249 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4250 DMA_FROM_DEVICE); 4251 err_out: 4252 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4253 DMA_TO_DEVICE); 4254 return rc; 4255 } 4256 4257 static int check_enc_sas_cmd(struct sas_task *task) 4258 { 4259 u8 cmd = task->ssp_task.cmd->cmnd[0]; 4260 4261 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) 4262 return 1; 4263 else 4264 return 0; 4265 } 4266 4267 static int check_enc_sat_cmd(struct sas_task *task) 4268 { 4269 int ret = 0; 4270 switch (task->ata_task.fis.command) { 4271 case ATA_CMD_FPDMA_READ: 4272 case ATA_CMD_READ_EXT: 4273 case ATA_CMD_READ: 4274 case ATA_CMD_FPDMA_WRITE: 4275 case ATA_CMD_WRITE_EXT: 4276 case ATA_CMD_WRITE: 4277 case ATA_CMD_PIO_READ: 4278 case ATA_CMD_PIO_READ_EXT: 4279 case ATA_CMD_PIO_WRITE: 4280 case ATA_CMD_PIO_WRITE_EXT: 4281 ret = 1; 4282 break; 4283 default: 4284 ret = 0; 4285 break; 4286 } 4287 return ret; 4288 } 4289 4290 /** 4291 * pm80xx_chip_ssp_io_req - send a SSP task to FW 4292 * @pm8001_ha: our hba card information. 4293 * @ccb: the ccb information this request used. 4294 */ 4295 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4296 struct pm8001_ccb_info *ccb) 4297 { 4298 struct sas_task *task = ccb->task; 4299 struct domain_device *dev = task->dev; 4300 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4301 struct ssp_ini_io_start_req ssp_cmd; 4302 u32 tag = ccb->ccb_tag; 4303 int ret; 4304 u64 phys_addr, start_addr, end_addr; 4305 u32 end_addr_high, end_addr_low; 4306 struct inbound_queue_table *circularQ; 4307 u32 q_index, cpu_id; 4308 u32 opc = OPC_INB_SSPINIIOSTART; 4309 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4310 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4311 /* data address domain added for spcv; set to 0 by host, 4312 * used internally by controller 4313 * 0 for SAS 1.1 and SAS 2.0 compatible TLR 4314 */ 4315 ssp_cmd.dad_dir_m_tlr = 4316 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); 4317 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4318 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4319 ssp_cmd.tag = cpu_to_le32(tag); 4320 if (task->ssp_task.enable_first_burst) 4321 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4322 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4323 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4324 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4325 task->ssp_task.cmd->cmd_len); 4326 cpu_id = smp_processor_id(); 4327 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num); 4328 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4329 4330 /* Check if encryption is set */ 4331 if (pm8001_ha->chip->encrypt && 4332 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { 4333 pm8001_dbg(pm8001_ha, IO, 4334 "Encryption enabled.Sending Encrypt SAS command 0x%x\n", 4335 task->ssp_task.cmd->cmnd[0]); 4336 opc = OPC_INB_SSP_INI_DIF_ENC_IO; 4337 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ 4338 ssp_cmd.dad_dir_m_tlr = cpu_to_le32 4339 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); 4340 4341 /* fill in PRD (scatter/gather) table, if any */ 4342 if (task->num_scatter > 1) { 4343 pm8001_chip_make_sg(task->scatter, 4344 ccb->n_elem, ccb->buf_prd); 4345 phys_addr = ccb->ccb_dma_handle; 4346 ssp_cmd.enc_addr_low = 4347 cpu_to_le32(lower_32_bits(phys_addr)); 4348 ssp_cmd.enc_addr_high = 4349 cpu_to_le32(upper_32_bits(phys_addr)); 4350 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4351 } else if (task->num_scatter == 1) { 4352 u64 dma_addr = sg_dma_address(task->scatter); 4353 ssp_cmd.enc_addr_low = 4354 cpu_to_le32(lower_32_bits(dma_addr)); 4355 ssp_cmd.enc_addr_high = 4356 cpu_to_le32(upper_32_bits(dma_addr)); 4357 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4358 ssp_cmd.enc_esgl = 0; 4359 /* Check 4G Boundary */ 4360 start_addr = cpu_to_le64(dma_addr); 4361 end_addr = (start_addr + ssp_cmd.enc_len) - 1; 4362 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4363 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4364 if (end_addr_high != ssp_cmd.enc_addr_high) { 4365 pm8001_dbg(pm8001_ha, FAIL, 4366 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4367 start_addr, ssp_cmd.enc_len, 4368 end_addr_high, end_addr_low); 4369 pm8001_chip_make_sg(task->scatter, 1, 4370 ccb->buf_prd); 4371 phys_addr = ccb->ccb_dma_handle; 4372 ssp_cmd.enc_addr_low = 4373 cpu_to_le32(lower_32_bits(phys_addr)); 4374 ssp_cmd.enc_addr_high = 4375 cpu_to_le32(upper_32_bits(phys_addr)); 4376 ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4377 } 4378 } else if (task->num_scatter == 0) { 4379 ssp_cmd.enc_addr_low = 0; 4380 ssp_cmd.enc_addr_high = 0; 4381 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4382 ssp_cmd.enc_esgl = 0; 4383 } 4384 /* XTS mode. All other fields are 0 */ 4385 ssp_cmd.key_cmode = 0x6 << 4; 4386 /* set tweak values. Should be the start lba */ 4387 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | 4388 (task->ssp_task.cmd->cmnd[3] << 16) | 4389 (task->ssp_task.cmd->cmnd[4] << 8) | 4390 (task->ssp_task.cmd->cmnd[5])); 4391 } else { 4392 pm8001_dbg(pm8001_ha, IO, 4393 "Sending Normal SAS command 0x%x inb q %x\n", 4394 task->ssp_task.cmd->cmnd[0], q_index); 4395 /* fill in PRD (scatter/gather) table, if any */ 4396 if (task->num_scatter > 1) { 4397 pm8001_chip_make_sg(task->scatter, ccb->n_elem, 4398 ccb->buf_prd); 4399 phys_addr = ccb->ccb_dma_handle; 4400 ssp_cmd.addr_low = 4401 cpu_to_le32(lower_32_bits(phys_addr)); 4402 ssp_cmd.addr_high = 4403 cpu_to_le32(upper_32_bits(phys_addr)); 4404 ssp_cmd.esgl = cpu_to_le32(1<<31); 4405 } else if (task->num_scatter == 1) { 4406 u64 dma_addr = sg_dma_address(task->scatter); 4407 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4408 ssp_cmd.addr_high = 4409 cpu_to_le32(upper_32_bits(dma_addr)); 4410 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4411 ssp_cmd.esgl = 0; 4412 /* Check 4G Boundary */ 4413 start_addr = cpu_to_le64(dma_addr); 4414 end_addr = (start_addr + ssp_cmd.len) - 1; 4415 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4416 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4417 if (end_addr_high != ssp_cmd.addr_high) { 4418 pm8001_dbg(pm8001_ha, FAIL, 4419 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4420 start_addr, ssp_cmd.len, 4421 end_addr_high, end_addr_low); 4422 pm8001_chip_make_sg(task->scatter, 1, 4423 ccb->buf_prd); 4424 phys_addr = ccb->ccb_dma_handle; 4425 ssp_cmd.addr_low = 4426 cpu_to_le32(lower_32_bits(phys_addr)); 4427 ssp_cmd.addr_high = 4428 cpu_to_le32(upper_32_bits(phys_addr)); 4429 ssp_cmd.esgl = cpu_to_le32(1<<31); 4430 } 4431 } else if (task->num_scatter == 0) { 4432 ssp_cmd.addr_low = 0; 4433 ssp_cmd.addr_high = 0; 4434 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4435 ssp_cmd.esgl = 0; 4436 } 4437 } 4438 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4439 &ssp_cmd, sizeof(ssp_cmd), q_index); 4440 return ret; 4441 } 4442 4443 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4444 struct pm8001_ccb_info *ccb) 4445 { 4446 struct sas_task *task = ccb->task; 4447 struct domain_device *dev = task->dev; 4448 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4449 u32 tag = ccb->ccb_tag; 4450 int ret; 4451 u32 q_index, cpu_id; 4452 struct sata_start_req sata_cmd; 4453 u32 hdr_tag, ncg_tag = 0; 4454 u64 phys_addr, start_addr, end_addr; 4455 u32 end_addr_high, end_addr_low; 4456 u32 ATAP = 0x0; 4457 u32 dir; 4458 struct inbound_queue_table *circularQ; 4459 unsigned long flags; 4460 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4461 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4462 cpu_id = smp_processor_id(); 4463 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num); 4464 circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 4465 4466 if (task->data_dir == DMA_NONE) { 4467 ATAP = 0x04; /* no data*/ 4468 pm8001_dbg(pm8001_ha, IO, "no data\n"); 4469 } else if (likely(!task->ata_task.device_control_reg_update)) { 4470 if (task->ata_task.dma_xfer) { 4471 ATAP = 0x06; /* DMA */ 4472 pm8001_dbg(pm8001_ha, IO, "DMA\n"); 4473 } else { 4474 ATAP = 0x05; /* PIO*/ 4475 pm8001_dbg(pm8001_ha, IO, "PIO\n"); 4476 } 4477 if (task->ata_task.use_ncq && 4478 dev->sata_dev.class != ATA_DEV_ATAPI) { 4479 ATAP = 0x07; /* FPDMA */ 4480 pm8001_dbg(pm8001_ha, IO, "FPDMA\n"); 4481 } 4482 } 4483 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4484 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4485 ncg_tag = hdr_tag; 4486 } 4487 dir = data_dir_flags[task->data_dir] << 8; 4488 sata_cmd.tag = cpu_to_le32(tag); 4489 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4490 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4491 4492 sata_cmd.sata_fis = task->ata_task.fis; 4493 if (likely(!task->ata_task.device_control_reg_update)) 4494 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4495 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4496 4497 /* Check if encryption is set */ 4498 if (pm8001_ha->chip->encrypt && 4499 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { 4500 pm8001_dbg(pm8001_ha, IO, 4501 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", 4502 sata_cmd.sata_fis.command); 4503 opc = OPC_INB_SATA_DIF_ENC_IO; 4504 4505 /* set encryption bit */ 4506 sata_cmd.ncqtag_atap_dir_m_dad = 4507 cpu_to_le32(((ncg_tag & 0xff)<<16)| 4508 ((ATAP & 0x3f) << 10) | 0x20 | dir); 4509 /* dad (bit 0-1) is 0 */ 4510 /* fill in PRD (scatter/gather) table, if any */ 4511 if (task->num_scatter > 1) { 4512 pm8001_chip_make_sg(task->scatter, 4513 ccb->n_elem, ccb->buf_prd); 4514 phys_addr = ccb->ccb_dma_handle; 4515 sata_cmd.enc_addr_low = lower_32_bits(phys_addr); 4516 sata_cmd.enc_addr_high = upper_32_bits(phys_addr); 4517 sata_cmd.enc_esgl = cpu_to_le32(1 << 31); 4518 } else if (task->num_scatter == 1) { 4519 u64 dma_addr = sg_dma_address(task->scatter); 4520 sata_cmd.enc_addr_low = lower_32_bits(dma_addr); 4521 sata_cmd.enc_addr_high = upper_32_bits(dma_addr); 4522 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4523 sata_cmd.enc_esgl = 0; 4524 /* Check 4G Boundary */ 4525 start_addr = cpu_to_le64(dma_addr); 4526 end_addr = (start_addr + sata_cmd.enc_len) - 1; 4527 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4528 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4529 if (end_addr_high != sata_cmd.enc_addr_high) { 4530 pm8001_dbg(pm8001_ha, FAIL, 4531 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4532 start_addr, sata_cmd.enc_len, 4533 end_addr_high, end_addr_low); 4534 pm8001_chip_make_sg(task->scatter, 1, 4535 ccb->buf_prd); 4536 phys_addr = ccb->ccb_dma_handle; 4537 sata_cmd.enc_addr_low = 4538 lower_32_bits(phys_addr); 4539 sata_cmd.enc_addr_high = 4540 upper_32_bits(phys_addr); 4541 sata_cmd.enc_esgl = 4542 cpu_to_le32(1 << 31); 4543 } 4544 } else if (task->num_scatter == 0) { 4545 sata_cmd.enc_addr_low = 0; 4546 sata_cmd.enc_addr_high = 0; 4547 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4548 sata_cmd.enc_esgl = 0; 4549 } 4550 /* XTS mode. All other fields are 0 */ 4551 sata_cmd.key_index_mode = 0x6 << 4; 4552 /* set tweak values. Should be the start lba */ 4553 sata_cmd.twk_val0 = 4554 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | 4555 (sata_cmd.sata_fis.lbah << 16) | 4556 (sata_cmd.sata_fis.lbam << 8) | 4557 (sata_cmd.sata_fis.lbal)); 4558 sata_cmd.twk_val1 = 4559 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | 4560 (sata_cmd.sata_fis.lbam_exp)); 4561 } else { 4562 pm8001_dbg(pm8001_ha, IO, 4563 "Sending Normal SATA command 0x%x inb %x\n", 4564 sata_cmd.sata_fis.command, q_index); 4565 /* dad (bit 0-1) is 0 */ 4566 sata_cmd.ncqtag_atap_dir_m_dad = 4567 cpu_to_le32(((ncg_tag & 0xff)<<16) | 4568 ((ATAP & 0x3f) << 10) | dir); 4569 4570 /* fill in PRD (scatter/gather) table, if any */ 4571 if (task->num_scatter > 1) { 4572 pm8001_chip_make_sg(task->scatter, 4573 ccb->n_elem, ccb->buf_prd); 4574 phys_addr = ccb->ccb_dma_handle; 4575 sata_cmd.addr_low = lower_32_bits(phys_addr); 4576 sata_cmd.addr_high = upper_32_bits(phys_addr); 4577 sata_cmd.esgl = cpu_to_le32(1 << 31); 4578 } else if (task->num_scatter == 1) { 4579 u64 dma_addr = sg_dma_address(task->scatter); 4580 sata_cmd.addr_low = lower_32_bits(dma_addr); 4581 sata_cmd.addr_high = upper_32_bits(dma_addr); 4582 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4583 sata_cmd.esgl = 0; 4584 /* Check 4G Boundary */ 4585 start_addr = cpu_to_le64(dma_addr); 4586 end_addr = (start_addr + sata_cmd.len) - 1; 4587 end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 4588 end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 4589 if (end_addr_high != sata_cmd.addr_high) { 4590 pm8001_dbg(pm8001_ha, FAIL, 4591 "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4592 start_addr, sata_cmd.len, 4593 end_addr_high, end_addr_low); 4594 pm8001_chip_make_sg(task->scatter, 1, 4595 ccb->buf_prd); 4596 phys_addr = ccb->ccb_dma_handle; 4597 sata_cmd.addr_low = 4598 lower_32_bits(phys_addr); 4599 sata_cmd.addr_high = 4600 upper_32_bits(phys_addr); 4601 sata_cmd.esgl = cpu_to_le32(1 << 31); 4602 } 4603 } else if (task->num_scatter == 0) { 4604 sata_cmd.addr_low = 0; 4605 sata_cmd.addr_high = 0; 4606 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4607 sata_cmd.esgl = 0; 4608 } 4609 /* scsi cdb */ 4610 sata_cmd.atapi_scsi_cdb[0] = 4611 cpu_to_le32(((task->ata_task.atapi_packet[0]) | 4612 (task->ata_task.atapi_packet[1] << 8) | 4613 (task->ata_task.atapi_packet[2] << 16) | 4614 (task->ata_task.atapi_packet[3] << 24))); 4615 sata_cmd.atapi_scsi_cdb[1] = 4616 cpu_to_le32(((task->ata_task.atapi_packet[4]) | 4617 (task->ata_task.atapi_packet[5] << 8) | 4618 (task->ata_task.atapi_packet[6] << 16) | 4619 (task->ata_task.atapi_packet[7] << 24))); 4620 sata_cmd.atapi_scsi_cdb[2] = 4621 cpu_to_le32(((task->ata_task.atapi_packet[8]) | 4622 (task->ata_task.atapi_packet[9] << 8) | 4623 (task->ata_task.atapi_packet[10] << 16) | 4624 (task->ata_task.atapi_packet[11] << 24))); 4625 sata_cmd.atapi_scsi_cdb[3] = 4626 cpu_to_le32(((task->ata_task.atapi_packet[12]) | 4627 (task->ata_task.atapi_packet[13] << 8) | 4628 (task->ata_task.atapi_packet[14] << 16) | 4629 (task->ata_task.atapi_packet[15] << 24))); 4630 } 4631 4632 /* Check for read log for failed drive and return */ 4633 if (sata_cmd.sata_fis.command == 0x2f) { 4634 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4635 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4636 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4637 struct task_status_struct *ts; 4638 4639 pm8001_ha_dev->id &= 0xDFFFFFFF; 4640 ts = &task->task_status; 4641 4642 spin_lock_irqsave(&task->task_state_lock, flags); 4643 ts->resp = SAS_TASK_COMPLETE; 4644 ts->stat = SAM_STAT_GOOD; 4645 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4646 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4647 task->task_state_flags |= SAS_TASK_STATE_DONE; 4648 if (unlikely((task->task_state_flags & 4649 SAS_TASK_STATE_ABORTED))) { 4650 spin_unlock_irqrestore(&task->task_state_lock, 4651 flags); 4652 pm8001_dbg(pm8001_ha, FAIL, 4653 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n", 4654 task, ts->resp, 4655 ts->stat); 4656 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4657 return 0; 4658 } else { 4659 spin_unlock_irqrestore(&task->task_state_lock, 4660 flags); 4661 pm8001_ccb_task_free_done(pm8001_ha, task, 4662 ccb, tag); 4663 atomic_dec(&pm8001_ha_dev->running_req); 4664 return 0; 4665 } 4666 } 4667 } 4668 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4669 &sata_cmd, sizeof(sata_cmd), q_index); 4670 return ret; 4671 } 4672 4673 /** 4674 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND 4675 * @pm8001_ha: our hba card information. 4676 * @phy_id: the phy id which we wanted to start up. 4677 */ 4678 static int 4679 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4680 { 4681 struct phy_start_req payload; 4682 struct inbound_queue_table *circularQ; 4683 int ret; 4684 u32 tag = 0x01; 4685 u32 opcode = OPC_INB_PHYSTART; 4686 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4687 memset(&payload, 0, sizeof(payload)); 4688 payload.tag = cpu_to_le32(tag); 4689 4690 pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id); 4691 4692 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4693 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id); 4694 /* SSC Disable and SAS Analog ST configuration */ 4695 /** 4696 payload.ase_sh_lm_slr_phyid = 4697 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | 4698 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | 4699 phy_id); 4700 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need 4701 **/ 4702 4703 payload.sas_identify.dev_type = SAS_END_DEVICE; 4704 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4705 memcpy(payload.sas_identify.sas_addr, 4706 &pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4707 payload.sas_identify.phy_id = phy_id; 4708 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4709 sizeof(payload), 0); 4710 return ret; 4711 } 4712 4713 /** 4714 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4715 * @pm8001_ha: our hba card information. 4716 * @phy_id: the phy id which we wanted to start up. 4717 */ 4718 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4719 u8 phy_id) 4720 { 4721 struct phy_stop_req payload; 4722 struct inbound_queue_table *circularQ; 4723 int ret; 4724 u32 tag = 0x01; 4725 u32 opcode = OPC_INB_PHYSTOP; 4726 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4727 memset(&payload, 0, sizeof(payload)); 4728 payload.tag = cpu_to_le32(tag); 4729 payload.phy_id = cpu_to_le32(phy_id); 4730 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 4731 sizeof(payload), 0); 4732 return ret; 4733 } 4734 4735 /* 4736 * see comments on pm8001_mpi_reg_resp. 4737 */ 4738 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4739 struct pm8001_device *pm8001_dev, u32 flag) 4740 { 4741 struct reg_dev_req payload; 4742 u32 opc; 4743 u32 stp_sspsmp_sata = 0x4; 4744 struct inbound_queue_table *circularQ; 4745 u32 linkrate, phy_id; 4746 int rc, tag = 0xdeadbeef; 4747 struct pm8001_ccb_info *ccb; 4748 u8 retryFlag = 0x1; 4749 u16 firstBurstSize = 0; 4750 u16 ITNT = 2000; 4751 struct domain_device *dev = pm8001_dev->sas_device; 4752 struct domain_device *parent_dev = dev->parent; 4753 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4754 4755 memset(&payload, 0, sizeof(payload)); 4756 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4757 if (rc) 4758 return rc; 4759 ccb = &pm8001_ha->ccb_info[tag]; 4760 ccb->device = pm8001_dev; 4761 ccb->ccb_tag = tag; 4762 payload.tag = cpu_to_le32(tag); 4763 4764 if (flag == 1) { 4765 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4766 } else { 4767 if (pm8001_dev->dev_type == SAS_SATA_DEV) 4768 stp_sspsmp_sata = 0x00; /* stp*/ 4769 else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4770 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4771 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4772 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4773 } 4774 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4775 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4776 else 4777 phy_id = pm8001_dev->attached_phy; 4778 4779 opc = OPC_INB_REG_DEV; 4780 4781 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4782 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4783 4784 payload.phyid_portid = 4785 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) | 4786 ((phy_id & 0xFF) << 8)); 4787 4788 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | 4789 ((linkrate & 0x0F) << 24) | 4790 ((stp_sspsmp_sata & 0x03) << 28)); 4791 payload.firstburstsize_ITNexustimeout = 4792 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4793 4794 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4795 SAS_ADDR_SIZE); 4796 4797 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4798 sizeof(payload), 0); 4799 if (rc) 4800 pm8001_tag_free(pm8001_ha, tag); 4801 4802 return rc; 4803 } 4804 4805 /** 4806 * pm80xx_chip_phy_ctl_req - support the local phy operation 4807 * @pm8001_ha: our hba card information. 4808 * @phyId: the phy id which we wanted to operate 4809 * @phy_op: phy operation to request 4810 */ 4811 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4812 u32 phyId, u32 phy_op) 4813 { 4814 u32 tag; 4815 int rc; 4816 struct local_phy_ctl_req payload; 4817 struct inbound_queue_table *circularQ; 4818 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4819 memset(&payload, 0, sizeof(payload)); 4820 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4821 if (rc) 4822 return rc; 4823 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4824 payload.tag = cpu_to_le32(tag); 4825 payload.phyop_phyid = 4826 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); 4827 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4828 sizeof(payload), 0); 4829 } 4830 4831 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4832 { 4833 #ifdef PM8001_USE_MSIX 4834 return 1; 4835 #else 4836 u32 value; 4837 4838 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4839 if (value) 4840 return 1; 4841 return 0; 4842 #endif 4843 } 4844 4845 /** 4846 * pm8001_chip_isr - PM8001 isr handler. 4847 * @pm8001_ha: our hba card information. 4848 * @vec: irq number. 4849 */ 4850 static irqreturn_t 4851 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4852 { 4853 pm80xx_chip_interrupt_disable(pm8001_ha, vec); 4854 pm8001_dbg(pm8001_ha, DEVIO, 4855 "irq vec %d, ODMR:0x%x\n", 4856 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); 4857 process_oq(pm8001_ha, vec); 4858 pm80xx_chip_interrupt_enable(pm8001_ha, vec); 4859 return IRQ_HANDLED; 4860 } 4861 4862 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha, 4863 u32 operation, u32 phyid, 4864 u32 length, u32 *buf) 4865 { 4866 u32 tag , i, j = 0; 4867 int rc; 4868 struct set_phy_profile_req payload; 4869 struct inbound_queue_table *circularQ; 4870 u32 opc = OPC_INB_SET_PHY_PROFILE; 4871 4872 memset(&payload, 0, sizeof(payload)); 4873 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4874 if (rc) 4875 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n"); 4876 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4877 payload.tag = cpu_to_le32(tag); 4878 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF)); 4879 pm8001_dbg(pm8001_ha, INIT, 4880 " phy profile command for phy %x ,length is %d\n", 4881 payload.ppc_phyid, length); 4882 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { 4883 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i)); 4884 j++; 4885 } 4886 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4887 sizeof(payload), 0); 4888 if (rc) 4889 pm8001_tag_free(pm8001_ha, tag); 4890 } 4891 4892 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 4893 u32 length, u8 *buf) 4894 { 4895 u32 i; 4896 4897 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 4898 mpi_set_phy_profile_req(pm8001_ha, 4899 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf); 4900 length = length + PHY_DWORD_LENGTH; 4901 } 4902 pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n"); 4903 } 4904 4905 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, 4906 u32 phy, u32 length, u32 *buf) 4907 { 4908 u32 tag, opc; 4909 int rc, i; 4910 struct set_phy_profile_req payload; 4911 struct inbound_queue_table *circularQ; 4912 4913 memset(&payload, 0, sizeof(payload)); 4914 4915 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4916 if (rc) 4917 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n"); 4918 4919 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4920 opc = OPC_INB_SET_PHY_PROFILE; 4921 4922 payload.tag = cpu_to_le32(tag); 4923 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8) 4924 | (phy & 0xFF)); 4925 4926 for (i = 0; i < length; i++) 4927 payload.reserved[i] = cpu_to_le32(*(buf + i)); 4928 4929 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 4930 sizeof(payload), 0); 4931 if (rc) 4932 pm8001_tag_free(pm8001_ha, tag); 4933 4934 pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy); 4935 } 4936 const struct pm8001_dispatch pm8001_80xx_dispatch = { 4937 .name = "pmc80xx", 4938 .chip_init = pm80xx_chip_init, 4939 .chip_soft_rst = pm80xx_chip_soft_rst, 4940 .chip_rst = pm80xx_hw_chip_rst, 4941 .chip_iounmap = pm8001_chip_iounmap, 4942 .isr = pm80xx_chip_isr, 4943 .is_our_interrupt = pm80xx_chip_is_our_interrupt, 4944 .isr_process_oq = process_oq, 4945 .interrupt_enable = pm80xx_chip_interrupt_enable, 4946 .interrupt_disable = pm80xx_chip_interrupt_disable, 4947 .make_prd = pm8001_chip_make_sg, 4948 .smp_req = pm80xx_chip_smp_req, 4949 .ssp_io_req = pm80xx_chip_ssp_io_req, 4950 .sata_req = pm80xx_chip_sata_req, 4951 .phy_start_req = pm80xx_chip_phy_start_req, 4952 .phy_stop_req = pm80xx_chip_phy_stop_req, 4953 .reg_dev_req = pm80xx_chip_reg_dev_req, 4954 .dereg_dev_req = pm8001_chip_dereg_dev_req, 4955 .phy_ctl_req = pm80xx_chip_phy_ctl_req, 4956 .task_abort = pm8001_chip_abort_task, 4957 .ssp_tm_req = pm8001_chip_ssp_tm_req, 4958 .get_nvmd_req = pm8001_chip_get_nvmd_req, 4959 .set_nvmd_req = pm8001_chip_set_nvmd_req, 4960 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4961 .set_dev_state_req = pm8001_chip_set_dev_state_req, 4962 }; 4963