1f5860992SSakthivel K /* 2f5860992SSakthivel K * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver 3f5860992SSakthivel K * 4f5860992SSakthivel K * Copyright (c) 2008-2009 PMC-Sierra, Inc., 5f5860992SSakthivel K * All rights reserved. 6f5860992SSakthivel K * 7f5860992SSakthivel K * Redistribution and use in source and binary forms, with or without 8f5860992SSakthivel K * modification, are permitted provided that the following conditions 9f5860992SSakthivel K * are met: 10f5860992SSakthivel K * 1. Redistributions of source code must retain the above copyright 11f5860992SSakthivel K * notice, this list of conditions, and the following disclaimer, 12f5860992SSakthivel K * without modification. 13f5860992SSakthivel K * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14f5860992SSakthivel K * substantially similar to the "NO WARRANTY" disclaimer below 15f5860992SSakthivel K * ("Disclaimer") and any redistribution must be conditioned upon 16f5860992SSakthivel K * including a substantially similar Disclaimer requirement for further 17f5860992SSakthivel K * binary redistribution. 18f5860992SSakthivel K * 3. Neither the names of the above-listed copyright holders nor the names 19f5860992SSakthivel K * of any contributors may be used to endorse or promote products derived 20f5860992SSakthivel K * from this software without specific prior written permission. 21f5860992SSakthivel K * 22f5860992SSakthivel K * Alternatively, this software may be distributed under the terms of the 23f5860992SSakthivel K * GNU General Public License ("GPL") version 2 as published by the Free 24f5860992SSakthivel K * Software Foundation. 25f5860992SSakthivel K * 26f5860992SSakthivel K * NO WARRANTY 27f5860992SSakthivel K * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28f5860992SSakthivel K * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29f5860992SSakthivel K * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30f5860992SSakthivel K * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31f5860992SSakthivel K * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32f5860992SSakthivel K * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33f5860992SSakthivel K * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34f5860992SSakthivel K * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35f5860992SSakthivel K * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36f5860992SSakthivel K * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37f5860992SSakthivel K * POSSIBILITY OF SUCH DAMAGES. 38f5860992SSakthivel K * 39f5860992SSakthivel K */ 40f5860992SSakthivel K #include <linux/slab.h> 41f5860992SSakthivel K #include "pm8001_sas.h" 42f5860992SSakthivel K #include "pm80xx_hwi.h" 43f5860992SSakthivel K #include "pm8001_chips.h" 44f5860992SSakthivel K #include "pm8001_ctl.h" 458ceddda3SChangyuan Lyu #include "pm80xx_tracepoints.h" 46f5860992SSakthivel K 47f5860992SSakthivel K #define SMP_DIRECT 1 48f5860992SSakthivel K #define SMP_INDIRECT 2 49d078b511SAnand Kumar Santhanam 50d078b511SAnand Kumar Santhanam 51d078b511SAnand Kumar Santhanam int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value) 52d078b511SAnand Kumar Santhanam { 53d078b511SAnand Kumar Santhanam u32 reg_val; 54d078b511SAnand Kumar Santhanam unsigned long start; 55d078b511SAnand Kumar Santhanam pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); 56d078b511SAnand Kumar Santhanam /* confirm the setting is written */ 57d078b511SAnand Kumar Santhanam start = jiffies + HZ; /* 1 sec */ 58d078b511SAnand Kumar Santhanam do { 59d078b511SAnand Kumar Santhanam reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); 60d078b511SAnand Kumar Santhanam } while ((reg_val != shift_value) && time_before(jiffies, start)); 61d078b511SAnand Kumar Santhanam if (reg_val != shift_value) { 621b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n", 631b5d2793SJoe Perches reg_val); 64d078b511SAnand Kumar Santhanam return -1; 65d078b511SAnand Kumar Santhanam } 66d078b511SAnand Kumar Santhanam return 0; 67d078b511SAnand Kumar Santhanam } 68d078b511SAnand Kumar Santhanam 69ea310f57SLee Jones static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset, 703762d8f6SDamien Le Moal __le32 *destination, 71d078b511SAnand Kumar Santhanam u32 dw_count, u32 bus_base_number) 72d078b511SAnand Kumar Santhanam { 73d078b511SAnand Kumar Santhanam u32 index, value, offset; 74d078b511SAnand Kumar Santhanam 753762d8f6SDamien Le Moal for (index = 0; index < dw_count; index += 4, destination++) { 76044f59deSDeepak Ukey offset = (soffset + index); 77d078b511SAnand Kumar Santhanam if (offset < (64 * 1024)) { 78d078b511SAnand Kumar Santhanam value = pm8001_cr32(pm8001_ha, bus_base_number, offset); 793762d8f6SDamien Le Moal *destination = cpu_to_le32(value); 80d078b511SAnand Kumar Santhanam } 81d078b511SAnand Kumar Santhanam } 82d078b511SAnand Kumar Santhanam return; 83d078b511SAnand Kumar Santhanam } 84d078b511SAnand Kumar Santhanam 85d078b511SAnand Kumar Santhanam ssize_t pm80xx_get_fatal_dump(struct device *cdev, 86d078b511SAnand Kumar Santhanam struct device_attribute *attr, char *buf) 87d078b511SAnand Kumar Santhanam { 88d078b511SAnand Kumar Santhanam struct Scsi_Host *shost = class_to_shost(cdev); 89d078b511SAnand Kumar Santhanam struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 90d078b511SAnand Kumar Santhanam struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 91d078b511SAnand Kumar Santhanam void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; 92d078b511SAnand Kumar Santhanam u32 accum_len, reg_val, index, *temp; 93044f59deSDeepak Ukey u32 status = 1; 94d078b511SAnand Kumar Santhanam unsigned long start; 95d078b511SAnand Kumar Santhanam u8 *direct_data; 96d078b511SAnand Kumar Santhanam char *fatal_error_data = buf; 97044f59deSDeepak Ukey u32 length_to_read; 98044f59deSDeepak Ukey u32 offset; 99d078b511SAnand Kumar Santhanam 100d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_data = buf; 101d078b511SAnand Kumar Santhanam if (pm8001_ha->chip_id == chip_8001) { 102d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_data += 103d078b511SAnand Kumar Santhanam sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 104d078b511SAnand Kumar Santhanam "Not supported for SPC controller"); 105d078b511SAnand Kumar Santhanam return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 106d078b511SAnand Kumar Santhanam (char *)buf; 107d078b511SAnand Kumar Santhanam } 108044f59deSDeepak Ukey /* initialize variables for very first call from host application */ 109d078b511SAnand Kumar Santhanam if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 1101b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 1111b5d2793SJoe Perches "forensic_info TYPE_NON_FATAL..............\n"); 112d078b511SAnand Kumar Santhanam direct_data = (u8 *)fatal_error_data; 113d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; 114d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; 115044f59deSDeepak Ukey pm8001_ha->forensic_info.data_buf.direct_offset = 0; 116d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.read_len = 0; 117044f59deSDeepak Ukey pm8001_ha->forensic_preserved_accumulated_transfer = 0; 118044f59deSDeepak Ukey 119044f59deSDeepak Ukey /* Write signature to fatal dump table */ 120044f59deSDeepak Ukey pm8001_mw32(fatal_table_address, 121044f59deSDeepak Ukey MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd); 122d078b511SAnand Kumar Santhanam 123d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_data = direct_data; 1241b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status); 1251b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n", 1261b5d2793SJoe Perches pm8001_ha->forensic_info.data_buf.read_len); 1271b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n", 1281b5d2793SJoe Perches pm8001_ha->forensic_info.data_buf.direct_len); 1291b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n", 1301b5d2793SJoe Perches pm8001_ha->forensic_info.data_buf.direct_offset); 131044f59deSDeepak Ukey } 132044f59deSDeepak Ukey if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { 133d078b511SAnand Kumar Santhanam /* start to get data */ 134d078b511SAnand Kumar Santhanam /* Program the MEMBASE II Shifting Register with 0x00.*/ 135d078b511SAnand Kumar Santhanam pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 136d078b511SAnand Kumar Santhanam pm8001_ha->fatal_forensic_shift_offset); 137d078b511SAnand Kumar Santhanam pm8001_ha->forensic_last_offset = 0; 138d078b511SAnand Kumar Santhanam pm8001_ha->forensic_fatal_step = 0; 139d078b511SAnand Kumar Santhanam pm8001_ha->fatal_bar_loc = 0; 140d078b511SAnand Kumar Santhanam } 141cf370066SViswas G 142bb6beabfSRandy Dunlap /* Read until accum_len is retrieved */ 143d078b511SAnand Kumar Santhanam accum_len = pm8001_mr32(fatal_table_address, 144d078b511SAnand Kumar Santhanam MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 145044f59deSDeepak Ukey /* Determine length of data between previously stored transfer length 146044f59deSDeepak Ukey * and current accumulated transfer length 147044f59deSDeepak Ukey */ 148044f59deSDeepak Ukey length_to_read = 149044f59deSDeepak Ukey accum_len - pm8001_ha->forensic_preserved_accumulated_transfer; 1501b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n", 1511b5d2793SJoe Perches accum_len); 1521b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n", 1531b5d2793SJoe Perches length_to_read); 1541b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n", 1551b5d2793SJoe Perches pm8001_ha->forensic_last_offset); 1561b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n", 1571b5d2793SJoe Perches pm8001_ha->forensic_info.data_buf.read_len); 1581b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n", 1591b5d2793SJoe Perches pm8001_ha->forensic_info.data_buf.direct_len); 1601b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n", 1611b5d2793SJoe Perches pm8001_ha->forensic_info.data_buf.direct_offset); 162044f59deSDeepak Ukey 163044f59deSDeepak Ukey /* If accumulated length failed to read correctly fail the attempt.*/ 164d078b511SAnand Kumar Santhanam if (accum_len == 0xFFFFFFFF) { 1651b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 1661b5d2793SJoe Perches "Possible PCI issue 0x%x not expected\n", 1671b5d2793SJoe Perches accum_len); 168044f59deSDeepak Ukey return status; 169d078b511SAnand Kumar Santhanam } 170044f59deSDeepak Ukey /* If accumulated length is zero fail the attempt */ 171044f59deSDeepak Ukey if (accum_len == 0) { 172d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_data += 173d078b511SAnand Kumar Santhanam sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 174d078b511SAnand Kumar Santhanam "%08x ", 0xFFFFFFFF); 175d078b511SAnand Kumar Santhanam return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 176d078b511SAnand Kumar Santhanam (char *)buf; 177d078b511SAnand Kumar Santhanam } 178044f59deSDeepak Ukey /* Accumulated length is good so start capturing the first data */ 179d078b511SAnand Kumar Santhanam temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 180d078b511SAnand Kumar Santhanam if (pm8001_ha->forensic_fatal_step == 0) { 181d078b511SAnand Kumar Santhanam moreData: 182044f59deSDeepak Ukey /* If data to read is less than SYSFS_OFFSET then reduce the 183044f59deSDeepak Ukey * length of dataLen 184044f59deSDeepak Ukey */ 185044f59deSDeepak Ukey if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET 186044f59deSDeepak Ukey > length_to_read) { 187044f59deSDeepak Ukey pm8001_ha->forensic_info.data_buf.direct_len = 188044f59deSDeepak Ukey length_to_read - 189044f59deSDeepak Ukey pm8001_ha->forensic_last_offset; 190044f59deSDeepak Ukey } else { 191044f59deSDeepak Ukey pm8001_ha->forensic_info.data_buf.direct_len = 192044f59deSDeepak Ukey SYSFS_OFFSET; 193044f59deSDeepak Ukey } 194d078b511SAnand Kumar Santhanam if (pm8001_ha->forensic_info.data_buf.direct_data) { 195d078b511SAnand Kumar Santhanam /* Data is in bar, copy to host memory */ 196044f59deSDeepak Ukey pm80xx_pci_mem_copy(pm8001_ha, 197044f59deSDeepak Ukey pm8001_ha->fatal_bar_loc, 198d078b511SAnand Kumar Santhanam pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, 199044f59deSDeepak Ukey pm8001_ha->forensic_info.data_buf.direct_len, 1); 200d078b511SAnand Kumar Santhanam } 201d078b511SAnand Kumar Santhanam pm8001_ha->fatal_bar_loc += 202d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_len; 203d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_offset += 204d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_len; 205d078b511SAnand Kumar Santhanam pm8001_ha->forensic_last_offset += 206d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_len; 207d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.read_len = 208d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_len; 209d078b511SAnand Kumar Santhanam 210044f59deSDeepak Ukey if (pm8001_ha->forensic_last_offset >= length_to_read) { 211d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_data += 212d078b511SAnand Kumar Santhanam sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 213d078b511SAnand Kumar Santhanam "%08x ", 3); 214044f59deSDeepak Ukey for (index = 0; index < 215044f59deSDeepak Ukey (pm8001_ha->forensic_info.data_buf.direct_len 216044f59deSDeepak Ukey / 4); index++) { 217d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_data += 218044f59deSDeepak Ukey sprintf( 219044f59deSDeepak Ukey pm8001_ha->forensic_info.data_buf.direct_data, 220d078b511SAnand Kumar Santhanam "%08x ", *(temp + index)); 221d078b511SAnand Kumar Santhanam } 222d078b511SAnand Kumar Santhanam 223d078b511SAnand Kumar Santhanam pm8001_ha->fatal_bar_loc = 0; 224d078b511SAnand Kumar Santhanam pm8001_ha->forensic_fatal_step = 1; 225d078b511SAnand Kumar Santhanam pm8001_ha->fatal_forensic_shift_offset = 0; 226d078b511SAnand Kumar Santhanam pm8001_ha->forensic_last_offset = 0; 227044f59deSDeepak Ukey status = 0; 228044f59deSDeepak Ukey offset = (int) 229044f59deSDeepak Ukey ((char *)pm8001_ha->forensic_info.data_buf.direct_data 230044f59deSDeepak Ukey - (char *)buf); 2311b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 2321b5d2793SJoe Perches "get_fatal_spcv:return1 0x%x\n", offset); 233d078b511SAnand Kumar Santhanam return (char *)pm8001_ha-> 234d078b511SAnand Kumar Santhanam forensic_info.data_buf.direct_data - 235d078b511SAnand Kumar Santhanam (char *)buf; 236d078b511SAnand Kumar Santhanam } 237d078b511SAnand Kumar Santhanam if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { 238d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_data += 239d078b511SAnand Kumar Santhanam sprintf(pm8001_ha-> 240d078b511SAnand Kumar Santhanam forensic_info.data_buf.direct_data, 241d078b511SAnand Kumar Santhanam "%08x ", 2); 242044f59deSDeepak Ukey for (index = 0; index < 243044f59deSDeepak Ukey (pm8001_ha->forensic_info.data_buf.direct_len 244044f59deSDeepak Ukey / 4); index++) { 245044f59deSDeepak Ukey pm8001_ha->forensic_info.data_buf.direct_data 246044f59deSDeepak Ukey += sprintf(pm8001_ha-> 247d078b511SAnand Kumar Santhanam forensic_info.data_buf.direct_data, 248d078b511SAnand Kumar Santhanam "%08x ", *(temp + index)); 249d078b511SAnand Kumar Santhanam } 250044f59deSDeepak Ukey status = 0; 251044f59deSDeepak Ukey offset = (int) 252044f59deSDeepak Ukey ((char *)pm8001_ha->forensic_info.data_buf.direct_data 253044f59deSDeepak Ukey - (char *)buf); 2541b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 2551b5d2793SJoe Perches "get_fatal_spcv:return2 0x%x\n", offset); 256d078b511SAnand Kumar Santhanam return (char *)pm8001_ha-> 257d078b511SAnand Kumar Santhanam forensic_info.data_buf.direct_data - 258d078b511SAnand Kumar Santhanam (char *)buf; 259d078b511SAnand Kumar Santhanam } 260d078b511SAnand Kumar Santhanam 261d078b511SAnand Kumar Santhanam /* Increment the MEMBASE II Shifting Register value by 0x100.*/ 262d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_data += 263d078b511SAnand Kumar Santhanam sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 264d078b511SAnand Kumar Santhanam "%08x ", 2); 265044f59deSDeepak Ukey for (index = 0; index < 266044f59deSDeepak Ukey (pm8001_ha->forensic_info.data_buf.direct_len 267044f59deSDeepak Ukey / 4) ; index++) { 268d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_data += 269d078b511SAnand Kumar Santhanam sprintf(pm8001_ha-> 270d078b511SAnand Kumar Santhanam forensic_info.data_buf.direct_data, 271d078b511SAnand Kumar Santhanam "%08x ", *(temp + index)); 272d078b511SAnand Kumar Santhanam } 273d078b511SAnand Kumar Santhanam pm8001_ha->fatal_forensic_shift_offset += 0x100; 274d078b511SAnand Kumar Santhanam pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, 275d078b511SAnand Kumar Santhanam pm8001_ha->fatal_forensic_shift_offset); 276d078b511SAnand Kumar Santhanam pm8001_ha->fatal_bar_loc = 0; 277044f59deSDeepak Ukey status = 0; 278044f59deSDeepak Ukey offset = (int) 279044f59deSDeepak Ukey ((char *)pm8001_ha->forensic_info.data_buf.direct_data 280044f59deSDeepak Ukey - (char *)buf); 2811b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n", 2821b5d2793SJoe Perches offset); 283d078b511SAnand Kumar Santhanam return (char *)pm8001_ha->forensic_info.data_buf.direct_data - 284d078b511SAnand Kumar Santhanam (char *)buf; 285d078b511SAnand Kumar Santhanam } 286d078b511SAnand Kumar Santhanam if (pm8001_ha->forensic_fatal_step == 1) { 287044f59deSDeepak Ukey /* store previous accumulated length before triggering next 288044f59deSDeepak Ukey * accumulated length update 289044f59deSDeepak Ukey */ 290044f59deSDeepak Ukey pm8001_ha->forensic_preserved_accumulated_transfer = 291044f59deSDeepak Ukey pm8001_mr32(fatal_table_address, 292044f59deSDeepak Ukey MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 293044f59deSDeepak Ukey 294044f59deSDeepak Ukey /* continue capturing the fatal log until Dump status is 0x3 */ 295044f59deSDeepak Ukey if (pm8001_mr32(fatal_table_address, 296044f59deSDeepak Ukey MPI_FATAL_EDUMP_TABLE_STATUS) < 297044f59deSDeepak Ukey MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) { 298044f59deSDeepak Ukey 299044f59deSDeepak Ukey /* reset fddstat bit by writing to zero*/ 300044f59deSDeepak Ukey pm8001_mw32(fatal_table_address, 301044f59deSDeepak Ukey MPI_FATAL_EDUMP_TABLE_STATUS, 0x0); 302044f59deSDeepak Ukey 303044f59deSDeepak Ukey /* set dump control value to '1' so that new data will 304044f59deSDeepak Ukey * be transferred to shared memory 305044f59deSDeepak Ukey */ 306d078b511SAnand Kumar Santhanam pm8001_mw32(fatal_table_address, 307d078b511SAnand Kumar Santhanam MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 308d078b511SAnand Kumar Santhanam MPI_FATAL_EDUMP_HANDSHAKE_RDY); 309d078b511SAnand Kumar Santhanam 310d078b511SAnand Kumar Santhanam /*Poll FDDHSHK until clear */ 311d078b511SAnand Kumar Santhanam start = jiffies + (2 * HZ); /* 2 sec */ 312d078b511SAnand Kumar Santhanam 313d078b511SAnand Kumar Santhanam do { 314d078b511SAnand Kumar Santhanam reg_val = pm8001_mr32(fatal_table_address, 315d078b511SAnand Kumar Santhanam MPI_FATAL_EDUMP_TABLE_HANDSHAKE); 316d078b511SAnand Kumar Santhanam } while ((reg_val) && time_before(jiffies, start)); 317d078b511SAnand Kumar Santhanam 318d078b511SAnand Kumar Santhanam if (reg_val != 0) { 3191b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 320044f59deSDeepak Ukey "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n", 3211b5d2793SJoe Perches reg_val); 322044f59deSDeepak Ukey /* Fail the dump if a timeout occurs */ 323044f59deSDeepak Ukey pm8001_ha->forensic_info.data_buf.direct_data += 324044f59deSDeepak Ukey sprintf( 325044f59deSDeepak Ukey pm8001_ha->forensic_info.data_buf.direct_data, 326044f59deSDeepak Ukey "%08x ", 0xFFFFFFFF); 327044f59deSDeepak Ukey return((char *) 328044f59deSDeepak Ukey pm8001_ha->forensic_info.data_buf.direct_data 329044f59deSDeepak Ukey - (char *)buf); 330d078b511SAnand Kumar Santhanam } 331044f59deSDeepak Ukey /* Poll status register until set to 2 or 332044f59deSDeepak Ukey * 3 for up to 2 seconds 333044f59deSDeepak Ukey */ 334044f59deSDeepak Ukey start = jiffies + (2 * HZ); /* 2 sec */ 335d078b511SAnand Kumar Santhanam 336044f59deSDeepak Ukey do { 337044f59deSDeepak Ukey reg_val = pm8001_mr32(fatal_table_address, 338044f59deSDeepak Ukey MPI_FATAL_EDUMP_TABLE_STATUS); 3390e7c353eSColin Ian King } while (((reg_val != 2) && (reg_val != 3)) && 340044f59deSDeepak Ukey time_before(jiffies, start)); 341044f59deSDeepak Ukey 342044f59deSDeepak Ukey if (reg_val < 2) { 3431b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 344044f59deSDeepak Ukey "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n", 3451b5d2793SJoe Perches reg_val); 346044f59deSDeepak Ukey /* Fail the dump if a timeout occurs */ 347044f59deSDeepak Ukey pm8001_ha->forensic_info.data_buf.direct_data += 348044f59deSDeepak Ukey sprintf( 349044f59deSDeepak Ukey pm8001_ha->forensic_info.data_buf.direct_data, 350044f59deSDeepak Ukey "%08x ", 0xFFFFFFFF); 351ec2e7e1aSViswas G return((char *)pm8001_ha->forensic_info.data_buf.direct_data - 352ec2e7e1aSViswas G (char *)buf); 353ec2e7e1aSViswas G } 354ec2e7e1aSViswas G /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */ 355ec2e7e1aSViswas G pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */ 356044f59deSDeepak Ukey pm8001_cw32(pm8001_ha, 0, 357044f59deSDeepak Ukey MEMBASE_II_SHIFT_REGISTER, 358044f59deSDeepak Ukey pm8001_ha->fatal_forensic_shift_offset); 359044f59deSDeepak Ukey } 360044f59deSDeepak Ukey /* Read the next block of the debug data.*/ 361044f59deSDeepak Ukey length_to_read = pm8001_mr32(fatal_table_address, 362044f59deSDeepak Ukey MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) - 363044f59deSDeepak Ukey pm8001_ha->forensic_preserved_accumulated_transfer; 364044f59deSDeepak Ukey if (length_to_read != 0x0) { 365d078b511SAnand Kumar Santhanam pm8001_ha->forensic_fatal_step = 0; 366d078b511SAnand Kumar Santhanam goto moreData; 367d078b511SAnand Kumar Santhanam } else { 368d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.direct_data += 3697b382122SColin Ian King sprintf(pm8001_ha->forensic_info.data_buf.direct_data, 370d078b511SAnand Kumar Santhanam "%08x ", 4); 3717b382122SColin Ian King pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF; 3727b382122SColin Ian King pm8001_ha->forensic_info.data_buf.direct_len = 0; 3737b382122SColin Ian King pm8001_ha->forensic_info.data_buf.direct_offset = 0; 374d078b511SAnand Kumar Santhanam pm8001_ha->forensic_info.data_buf.read_len = 0; 375d078b511SAnand Kumar Santhanam } 376d078b511SAnand Kumar Santhanam } 377044f59deSDeepak Ukey offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data 378044f59deSDeepak Ukey - (char *)buf); 3791b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset); 380ec2e7e1aSViswas G return ((char *)pm8001_ha->forensic_info.data_buf.direct_data - 381ec2e7e1aSViswas G (char *)buf); 382d078b511SAnand Kumar Santhanam } 383d078b511SAnand Kumar Santhanam 384dba2cc03SDeepak Ukey /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma 385dba2cc03SDeepak Ukey * location by the firmware. 386dba2cc03SDeepak Ukey */ 387dba2cc03SDeepak Ukey ssize_t pm80xx_get_non_fatal_dump(struct device *cdev, 388dba2cc03SDeepak Ukey struct device_attribute *attr, char *buf) 389dba2cc03SDeepak Ukey { 390dba2cc03SDeepak Ukey struct Scsi_Host *shost = class_to_shost(cdev); 391dba2cc03SDeepak Ukey struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 392dba2cc03SDeepak Ukey struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; 393dba2cc03SDeepak Ukey void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr; 394dba2cc03SDeepak Ukey u32 accum_len = 0; 395dba2cc03SDeepak Ukey u32 total_len = 0; 396dba2cc03SDeepak Ukey u32 reg_val = 0; 397dba2cc03SDeepak Ukey u32 *temp = NULL; 398dba2cc03SDeepak Ukey u32 index = 0; 399dba2cc03SDeepak Ukey u32 output_length; 400dba2cc03SDeepak Ukey unsigned long start = 0; 401dba2cc03SDeepak Ukey char *buf_copy = buf; 402dba2cc03SDeepak Ukey 403dba2cc03SDeepak Ukey temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; 404dba2cc03SDeepak Ukey if (++pm8001_ha->non_fatal_count == 1) { 405dba2cc03SDeepak Ukey if (pm8001_ha->chip_id == chip_8001) { 406dba2cc03SDeepak Ukey snprintf(pm8001_ha->forensic_info.data_buf.direct_data, 407dba2cc03SDeepak Ukey PAGE_SIZE, "Not supported for SPC controller"); 408dba2cc03SDeepak Ukey return 0; 409dba2cc03SDeepak Ukey } 4101b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n"); 411dba2cc03SDeepak Ukey /* 412dba2cc03SDeepak Ukey * Step 1: Write the host buffer parameters in the MPI Fatal and 413dba2cc03SDeepak Ukey * Non-Fatal Error Dump Capture Table.This is the buffer 414dba2cc03SDeepak Ukey * where debug data will be DMAed to. 415dba2cc03SDeepak Ukey */ 416dba2cc03SDeepak Ukey pm8001_mw32(nonfatal_table_address, 417dba2cc03SDeepak Ukey MPI_FATAL_EDUMP_TABLE_LO_OFFSET, 418dba2cc03SDeepak Ukey pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo); 419dba2cc03SDeepak Ukey 420dba2cc03SDeepak Ukey pm8001_mw32(nonfatal_table_address, 421dba2cc03SDeepak Ukey MPI_FATAL_EDUMP_TABLE_HI_OFFSET, 422dba2cc03SDeepak Ukey pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi); 423dba2cc03SDeepak Ukey 424dba2cc03SDeepak Ukey pm8001_mw32(nonfatal_table_address, 425dba2cc03SDeepak Ukey MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET); 426dba2cc03SDeepak Ukey 427dba2cc03SDeepak Ukey /* Optionally, set the DUMPCTRL bit to 1 if the host 428dba2cc03SDeepak Ukey * keeps sending active I/Os while capturing the non-fatal 429dba2cc03SDeepak Ukey * debug data. Otherwise, leave this bit set to zero 430dba2cc03SDeepak Ukey */ 431dba2cc03SDeepak Ukey pm8001_mw32(nonfatal_table_address, 432dba2cc03SDeepak Ukey MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY); 433dba2cc03SDeepak Ukey 434dba2cc03SDeepak Ukey /* 435dba2cc03SDeepak Ukey * Step 2: Clear Accumulative Length of Debug Data Transferred 436dba2cc03SDeepak Ukey * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump 437dba2cc03SDeepak Ukey * Capture Table to zero. 438dba2cc03SDeepak Ukey */ 439dba2cc03SDeepak Ukey pm8001_mw32(nonfatal_table_address, 440dba2cc03SDeepak Ukey MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0); 441dba2cc03SDeepak Ukey 442dba2cc03SDeepak Ukey /* initiallize previous accumulated length to 0 */ 443dba2cc03SDeepak Ukey pm8001_ha->forensic_preserved_accumulated_transfer = 0; 444dba2cc03SDeepak Ukey pm8001_ha->non_fatal_read_length = 0; 445dba2cc03SDeepak Ukey } 446dba2cc03SDeepak Ukey 447dba2cc03SDeepak Ukey total_len = pm8001_mr32(nonfatal_table_address, 448dba2cc03SDeepak Ukey MPI_FATAL_EDUMP_TABLE_TOTAL_LEN); 449dba2cc03SDeepak Ukey /* 450dba2cc03SDeepak Ukey * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT] 451dba2cc03SDeepak Ukey * field and then request that the SPCv controller transfer the debug 452dba2cc03SDeepak Ukey * data by setting bit 7 of the Inbound Doorbell Set Register. 453dba2cc03SDeepak Ukey */ 454dba2cc03SDeepak Ukey pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0); 455dba2cc03SDeepak Ukey pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, 456dba2cc03SDeepak Ukey SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP); 457dba2cc03SDeepak Ukey 458dba2cc03SDeepak Ukey /* 459dba2cc03SDeepak Ukey * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for 460dba2cc03SDeepak Ukey * 2 seconds) until register bit 7 is cleared. 461dba2cc03SDeepak Ukey * This step only indicates the request is accepted by the controller. 462dba2cc03SDeepak Ukey */ 463dba2cc03SDeepak Ukey start = jiffies + (2 * HZ); /* 2 sec */ 464dba2cc03SDeepak Ukey do { 465dba2cc03SDeepak Ukey reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) & 466dba2cc03SDeepak Ukey SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP; 467dba2cc03SDeepak Ukey } while ((reg_val != 0) && time_before(jiffies, start)); 468dba2cc03SDeepak Ukey 469dba2cc03SDeepak Ukey /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non 470dba2cc03SDeepak Ukey * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in 471dba2cc03SDeepak Ukey * the MPI Fatal and Non-Fatal Error Dump Capture Table. 472dba2cc03SDeepak Ukey */ 473dba2cc03SDeepak Ukey start = jiffies + (2 * HZ); /* 2 sec */ 474dba2cc03SDeepak Ukey do { 475dba2cc03SDeepak Ukey reg_val = pm8001_mr32(nonfatal_table_address, 476dba2cc03SDeepak Ukey MPI_FATAL_EDUMP_TABLE_STATUS); 477dba2cc03SDeepak Ukey } while ((!reg_val) && time_before(jiffies, start)); 478dba2cc03SDeepak Ukey 479dba2cc03SDeepak Ukey if ((reg_val == 0x00) || 480dba2cc03SDeepak Ukey (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) || 481dba2cc03SDeepak Ukey (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) { 482dba2cc03SDeepak Ukey pm8001_ha->non_fatal_read_length = 0; 483dba2cc03SDeepak Ukey buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF); 484dba2cc03SDeepak Ukey pm8001_ha->non_fatal_count = 0; 485dba2cc03SDeepak Ukey return (buf_copy - buf); 486dba2cc03SDeepak Ukey } else if (reg_val == 487dba2cc03SDeepak Ukey MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) { 488dba2cc03SDeepak Ukey buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2); 489dba2cc03SDeepak Ukey } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) || 490dba2cc03SDeepak Ukey (pm8001_ha->non_fatal_read_length >= total_len)) { 491dba2cc03SDeepak Ukey pm8001_ha->non_fatal_read_length = 0; 492dba2cc03SDeepak Ukey buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4); 493dba2cc03SDeepak Ukey pm8001_ha->non_fatal_count = 0; 494dba2cc03SDeepak Ukey } 495dba2cc03SDeepak Ukey accum_len = pm8001_mr32(nonfatal_table_address, 496dba2cc03SDeepak Ukey MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); 497dba2cc03SDeepak Ukey output_length = accum_len - 498dba2cc03SDeepak Ukey pm8001_ha->forensic_preserved_accumulated_transfer; 499dba2cc03SDeepak Ukey 500dba2cc03SDeepak Ukey for (index = 0; index < output_length/4; index++) 501dba2cc03SDeepak Ukey buf_copy += snprintf(buf_copy, PAGE_SIZE, 502dba2cc03SDeepak Ukey "%08x ", *(temp+index)); 503dba2cc03SDeepak Ukey 504dba2cc03SDeepak Ukey pm8001_ha->non_fatal_read_length += output_length; 505dba2cc03SDeepak Ukey 506dba2cc03SDeepak Ukey /* store current accumulated length to use in next iteration as 507dba2cc03SDeepak Ukey * the previous accumulated length 508dba2cc03SDeepak Ukey */ 509dba2cc03SDeepak Ukey pm8001_ha->forensic_preserved_accumulated_transfer = accum_len; 510dba2cc03SDeepak Ukey return (buf_copy - buf); 511dba2cc03SDeepak Ukey } 512dba2cc03SDeepak Ukey 513f5860992SSakthivel K /** 514f5860992SSakthivel K * read_main_config_table - read the configure table and save it. 515f5860992SSakthivel K * @pm8001_ha: our hba card information 516f5860992SSakthivel K */ 517f5860992SSakthivel K static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 518f5860992SSakthivel K { 519f5860992SSakthivel K void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 520f5860992SSakthivel K 521f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = 522f5860992SSakthivel K pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); 523f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = 524f5860992SSakthivel K pm8001_mr32(address, MAIN_INTERFACE_REVISION); 525f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = 526f5860992SSakthivel K pm8001_mr32(address, MAIN_FW_REVISION); 527f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = 528f5860992SSakthivel K pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); 529f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = 530f5860992SSakthivel K pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); 531f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = 532f5860992SSakthivel K pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); 533f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = 534f5860992SSakthivel K pm8001_mr32(address, MAIN_GST_OFFSET); 535f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = 536f5860992SSakthivel K pm8001_mr32(address, MAIN_IBQ_OFFSET); 537f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = 538f5860992SSakthivel K pm8001_mr32(address, MAIN_OBQ_OFFSET); 539f5860992SSakthivel K 540f5860992SSakthivel K /* read Error Dump Offset and Length */ 541f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = 542f5860992SSakthivel K pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 543f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = 544f5860992SSakthivel K pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 545f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = 546f5860992SSakthivel K pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 547f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = 548f5860992SSakthivel K pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 549f5860992SSakthivel K 550f5860992SSakthivel K /* read GPIO LED settings from the configuration table */ 551f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = 552f5860992SSakthivel K pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); 553f5860992SSakthivel K 554f5860992SSakthivel K /* read analog Setting offset from the configuration table */ 555f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = 556f5860992SSakthivel K pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 557f5860992SSakthivel K 558f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = 559f5860992SSakthivel K pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); 560f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = 561f5860992SSakthivel K pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); 5628414cd80SViswas G /* read port recover and reset timeout */ 5638414cd80SViswas G pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer = 5648414cd80SViswas G pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER); 56524fff017SViswas G /* read ILA and inactive firmware version */ 56624fff017SViswas G pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version = 56724fff017SViswas G pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE); 56824fff017SViswas G pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version = 56924fff017SViswas G pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION); 5707370672dSpeter chang 5711b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 5727370672dSpeter chang "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n", 5737370672dSpeter chang pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature, 5747370672dSpeter chang pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev, 5751b5d2793SJoe Perches pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev); 5767370672dSpeter chang 5771b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 5787370672dSpeter chang "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n", 5797370672dSpeter chang pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset, 5807370672dSpeter chang pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset, 5817370672dSpeter chang pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset, 5827370672dSpeter chang pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset, 5831b5d2793SJoe Perches pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset); 5847370672dSpeter chang 5851b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 5867370672dSpeter chang "Main cfg table; ila rev:%x Inactive fw rev:%x\n", 5877370672dSpeter chang pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version, 5881b5d2793SJoe Perches pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version); 589f5860992SSakthivel K } 590f5860992SSakthivel K 591f5860992SSakthivel K /** 592f5860992SSakthivel K * read_general_status_table - read the general status table and save it. 593f5860992SSakthivel K * @pm8001_ha: our hba card information 594f5860992SSakthivel K */ 595f5860992SSakthivel K static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 596f5860992SSakthivel K { 597f5860992SSakthivel K void __iomem *address = pm8001_ha->general_stat_tbl_addr; 598f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = 599f5860992SSakthivel K pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); 600f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = 601f5860992SSakthivel K pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); 602f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = 603f5860992SSakthivel K pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); 604f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = 605f5860992SSakthivel K pm8001_mr32(address, GST_MSGUTCNT_OFFSET); 606f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = 607f5860992SSakthivel K pm8001_mr32(address, GST_IOPTCNT_OFFSET); 608f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = 609f5860992SSakthivel K pm8001_mr32(address, GST_GPIO_INPUT_VAL); 610f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = 611f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET0); 612f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = 613f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET1); 614f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = 615f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET2); 616f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = 617f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET3); 618f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = 619f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET4); 620f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = 621f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET5); 622f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = 623f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET6); 624f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = 625f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET7); 626f5860992SSakthivel K } 627f5860992SSakthivel K /** 628f5860992SSakthivel K * read_phy_attr_table - read the phy attribute table and save it. 629f5860992SSakthivel K * @pm8001_ha: our hba card information 630f5860992SSakthivel K */ 631f5860992SSakthivel K static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) 632f5860992SSakthivel K { 633f5860992SSakthivel K void __iomem *address = pm8001_ha->pspa_q_tbl_addr; 634f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[0] = 635f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); 636f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[1] = 637f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); 638f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[2] = 639f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); 640f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[3] = 641f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); 642f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[4] = 643f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); 644f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[5] = 645f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); 646f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[6] = 647f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); 648f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[7] = 649f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); 650f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[8] = 651f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); 652f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[9] = 653f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); 654f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[10] = 655f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); 656f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[11] = 657f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); 658f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[12] = 659f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); 660f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[13] = 661f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); 662f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[14] = 663f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); 664f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[15] = 665f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); 666f5860992SSakthivel K 667f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = 668f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); 669f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = 670f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); 671f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = 672f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); 673f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = 674f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); 675f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = 676f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); 677f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = 678f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); 679f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = 680f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); 681f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = 682f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); 683f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = 684f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); 685f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = 686f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); 687f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = 688f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); 689f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = 690f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); 691f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = 692f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); 693f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = 694f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); 695f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = 696f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); 697f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = 698f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); 699f5860992SSakthivel K 700f5860992SSakthivel K } 701f5860992SSakthivel K 702f5860992SSakthivel K /** 703f5860992SSakthivel K * read_inbnd_queue_table - read the inbound queue table and save it. 704f5860992SSakthivel K * @pm8001_ha: our hba card information 705f5860992SSakthivel K */ 706f5860992SSakthivel K static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 707f5860992SSakthivel K { 708f5860992SSakthivel K int i; 709f5860992SSakthivel K void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 71005c6c029SViswas G for (i = 0; i < PM8001_MAX_INB_NUM; i++) { 711f5860992SSakthivel K u32 offset = i * 0x20; 712f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 713f5860992SSakthivel K get_pci_bar_index(pm8001_mr32(address, 714f5860992SSakthivel K (offset + IB_PIPCI_BAR))); 715f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].pi_offset = 716f5860992SSakthivel K pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); 717f5860992SSakthivel K } 718f5860992SSakthivel K } 719f5860992SSakthivel K 720f5860992SSakthivel K /** 721f5860992SSakthivel K * read_outbnd_queue_table - read the outbound queue table and save it. 722f5860992SSakthivel K * @pm8001_ha: our hba card information 723f5860992SSakthivel K */ 724f5860992SSakthivel K static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 725f5860992SSakthivel K { 726f5860992SSakthivel K int i; 727f5860992SSakthivel K void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 72805c6c029SViswas G for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { 729f5860992SSakthivel K u32 offset = i * 0x24; 730f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 731f5860992SSakthivel K get_pci_bar_index(pm8001_mr32(address, 732f5860992SSakthivel K (offset + OB_CIPCI_BAR))); 733f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].ci_offset = 734f5860992SSakthivel K pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); 735f5860992SSakthivel K } 736f5860992SSakthivel K } 737f5860992SSakthivel K 738f5860992SSakthivel K /** 739f5860992SSakthivel K * init_default_table_values - init the default table. 740f5860992SSakthivel K * @pm8001_ha: our hba card information 741f5860992SSakthivel K */ 742f5860992SSakthivel K static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 743f5860992SSakthivel K { 744f5860992SSakthivel K int i; 745f5860992SSakthivel K u32 offsetib, offsetob; 746f5860992SSakthivel K void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 747f5860992SSakthivel K void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 74805c6c029SViswas G u32 ib_offset = pm8001_ha->ib_offset; 74905c6c029SViswas G u32 ob_offset = pm8001_ha->ob_offset; 75005c6c029SViswas G u32 ci_offset = pm8001_ha->ci_offset; 75105c6c029SViswas G u32 pi_offset = pm8001_ha->pi_offset; 752f5860992SSakthivel K 753f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = 754f5860992SSakthivel K pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 755f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = 756f5860992SSakthivel K pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 757f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = 758f5860992SSakthivel K PM8001_EVENT_LOG_SIZE; 759f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; 760f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = 761f5860992SSakthivel K pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 762f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = 763f5860992SSakthivel K pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 764f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = 765f5860992SSakthivel K PM8001_EVENT_LOG_SIZE; 766f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; 767f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; 768f5860992SSakthivel K 769bcd8a452SAjish Koshy /* Enable higher IQs and OQs, 32 to 63, bit 16 */ 770bcd8a452SAjish Koshy if (pm8001_ha->max_q_num > 32) 771bcd8a452SAjish Koshy pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 772bcd8a452SAjish Koshy 1 << 16; 773c6b9ef57SSakthivel K /* Disable end to end CRC checking */ 774c6b9ef57SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); 775c6b9ef57SSakthivel K 77605c6c029SViswas G for (i = 0; i < pm8001_ha->max_q_num; i++) { 777f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 7789504a923SHans Verkuil PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 779f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 78005c6c029SViswas G pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; 781f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 78205c6c029SViswas G pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; 783f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].base_virt = 78405c6c029SViswas G (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; 785f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].total_length = 78605c6c029SViswas G pm8001_ha->memoryMap.region[ib_offset + i].total_len; 787f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 78805c6c029SViswas G pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; 789f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 79005c6c029SViswas G pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; 791f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].ci_virt = 79205c6c029SViswas G pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; 793b431472bSViswas G pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0); 794f5860992SSakthivel K offsetib = i * 0x20; 795f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 796f5860992SSakthivel K get_pci_bar_index(pm8001_mr32(addressib, 797f5860992SSakthivel K (offsetib + 0x14))); 798f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].pi_offset = 799f5860992SSakthivel K pm8001_mr32(addressib, (offsetib + 0x18)); 800f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 801f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 8027370672dSpeter chang 8031b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 8047370672dSpeter chang "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i, 8057370672dSpeter chang pm8001_ha->inbnd_q_tbl[i].pi_pci_bar, 8061b5d2793SJoe Perches pm8001_ha->inbnd_q_tbl[i].pi_offset); 807f5860992SSakthivel K } 80805c6c029SViswas G for (i = 0; i < pm8001_ha->max_q_num; i++) { 809f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 8109504a923SHans Verkuil PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 811f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 81205c6c029SViswas G pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; 813f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 81405c6c029SViswas G pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; 815f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].base_virt = 81605c6c029SViswas G (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; 817f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].total_length = 81805c6c029SViswas G pm8001_ha->memoryMap.region[ob_offset + i].total_len; 819f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 82005c6c029SViswas G pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; 821f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 82205c6c029SViswas G pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; 823f5860992SSakthivel K /* interrupt vector based on oq */ 824f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); 825f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].pi_virt = 82605c6c029SViswas G pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; 827b431472bSViswas G pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0); 828f5860992SSakthivel K offsetob = i * 0x24; 829f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 830f5860992SSakthivel K get_pci_bar_index(pm8001_mr32(addressob, 831f5860992SSakthivel K offsetob + 0x14)); 832f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].ci_offset = 833f5860992SSakthivel K pm8001_mr32(addressob, (offsetob + 0x18)); 834f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 835f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 8367370672dSpeter chang 8371b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 8387370672dSpeter chang "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i, 8397370672dSpeter chang pm8001_ha->outbnd_q_tbl[i].ci_pci_bar, 8401b5d2793SJoe Perches pm8001_ha->outbnd_q_tbl[i].ci_offset); 841f5860992SSakthivel K } 842f5860992SSakthivel K } 843f5860992SSakthivel K 844f5860992SSakthivel K /** 845f5860992SSakthivel K * update_main_config_table - update the main default table to the HBA. 846f5860992SSakthivel K * @pm8001_ha: our hba card information 847f5860992SSakthivel K */ 848f5860992SSakthivel K static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 849f5860992SSakthivel K { 850f5860992SSakthivel K void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 851f5860992SSakthivel K pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, 852f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); 853f5860992SSakthivel K pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, 854f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); 855f5860992SSakthivel K pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, 856f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); 857f5860992SSakthivel K pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, 858f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); 859f5860992SSakthivel K pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, 860f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); 861f5860992SSakthivel K pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, 862f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); 863f5860992SSakthivel K pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, 864f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); 865f5860992SSakthivel K pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, 866f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); 867f5860992SSakthivel K pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, 868f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); 86972349b62SDeepak Ukey /* Update Fatal error interrupt vector */ 87072349b62SDeepak Ukey pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= 87105c6c029SViswas G ((pm8001_ha->max_q_num - 1) << 8); 872f5860992SSakthivel K pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, 873f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); 8741b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 8757370672dSpeter chang "Updated Fatal error interrupt vector 0x%x\n", 8761b5d2793SJoe Perches pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)); 8777370672dSpeter chang 878c6b9ef57SSakthivel K pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, 879c6b9ef57SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); 880f5860992SSakthivel K 881f5860992SSakthivel K /* SPCv specific */ 882f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; 883f5860992SSakthivel K /* Set GPIOLED to 0x2 for LED indicator */ 884f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; 885f5860992SSakthivel K pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, 886f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); 8871b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 8887370672dSpeter chang "Programming DW 0x21 in main cfg table with 0x%x\n", 8891b5d2793SJoe Perches pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)); 890f5860992SSakthivel K 891f5860992SSakthivel K pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 892f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 893f5860992SSakthivel K pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, 894f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); 8958414cd80SViswas G 8968414cd80SViswas G pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000; 8978414cd80SViswas G pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 8988414cd80SViswas G PORT_RECOVERY_TIMEOUT; 89961daffdeSViswas G if (pm8001_ha->chip_id == chip_8006) { 90061daffdeSViswas G pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 90161daffdeSViswas G 0x0000ffff; 90261daffdeSViswas G pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= 903196ba662SDeepak Ukey CHIP_8006_PORT_RECOVERY_TIMEOUT; 90461daffdeSViswas G } 9058414cd80SViswas G pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 9068414cd80SViswas G pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 907f5860992SSakthivel K } 908f5860992SSakthivel K 909f5860992SSakthivel K /** 910f5860992SSakthivel K * update_inbnd_queue_table - update the inbound queue table to the HBA. 911f5860992SSakthivel K * @pm8001_ha: our hba card information 9126ad4a517SLee Jones * @number: entry in the queue 913f5860992SSakthivel K */ 914f5860992SSakthivel K static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 915f5860992SSakthivel K int number) 916f5860992SSakthivel K { 917f5860992SSakthivel K void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 918f5860992SSakthivel K u16 offset = number * 0x20; 919f5860992SSakthivel K pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, 920f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 921f5860992SSakthivel K pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, 922f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 923f5860992SSakthivel K pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, 924f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 925f5860992SSakthivel K pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, 926f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 927f5860992SSakthivel K pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, 928f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 9297370672dSpeter chang 9301b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 9317370672dSpeter chang "IQ %d: Element pri size 0x%x\n", 9327370672dSpeter chang number, 9331b5d2793SJoe Perches pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 9347370672dSpeter chang 9351b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 9367370672dSpeter chang "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n", 9377370672dSpeter chang pm8001_ha->inbnd_q_tbl[number].upper_base_addr, 9381b5d2793SJoe Perches pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 9397370672dSpeter chang 9401b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 9417370672dSpeter chang "CI upper base addr 0x%x CI lower base addr 0x%x\n", 9427370672dSpeter chang pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr, 9431b5d2793SJoe Perches pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 944f5860992SSakthivel K } 945f5860992SSakthivel K 946f5860992SSakthivel K /** 947f5860992SSakthivel K * update_outbnd_queue_table - update the outbound queue table to the HBA. 948f5860992SSakthivel K * @pm8001_ha: our hba card information 9496ad4a517SLee Jones * @number: entry in the queue 950f5860992SSakthivel K */ 951f5860992SSakthivel K static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 952f5860992SSakthivel K int number) 953f5860992SSakthivel K { 954f5860992SSakthivel K void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 955f5860992SSakthivel K u16 offset = number * 0x24; 956f5860992SSakthivel K pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, 957f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 958f5860992SSakthivel K pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, 959f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 960f5860992SSakthivel K pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, 961f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 962f5860992SSakthivel K pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, 963f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 964f5860992SSakthivel K pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, 965f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 966f5860992SSakthivel K pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, 967f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 9687370672dSpeter chang 9691b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 9707370672dSpeter chang "OQ %d: Element pri size 0x%x\n", 9717370672dSpeter chang number, 9721b5d2793SJoe Perches pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 9737370672dSpeter chang 9741b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 9757370672dSpeter chang "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n", 9767370672dSpeter chang pm8001_ha->outbnd_q_tbl[number].upper_base_addr, 9771b5d2793SJoe Perches pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 9787370672dSpeter chang 9791b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 9807370672dSpeter chang "PI upper base addr 0x%x PI lower base addr 0x%x\n", 9817370672dSpeter chang pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr, 9821b5d2793SJoe Perches pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 983f5860992SSakthivel K } 984f5860992SSakthivel K 985f5860992SSakthivel K /** 986f5860992SSakthivel K * mpi_init_check - check firmware initialization status. 987f5860992SSakthivel K * @pm8001_ha: our hba card information 988f5860992SSakthivel K */ 989f5860992SSakthivel K static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 990f5860992SSakthivel K { 991f5860992SSakthivel K u32 max_wait_count; 992f5860992SSakthivel K u32 value; 993f5860992SSakthivel K u32 gst_len_mpistate; 994f5860992SSakthivel K 995f5860992SSakthivel K /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 996f5860992SSakthivel K table is updated */ 997f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); 998f5860992SSakthivel K /* wait until Inbound DoorBell Clear Register toggled */ 999a9a923e5SAnand Kumar Santhanam if (IS_SPCV_12G(pm8001_ha->pdev)) { 1000e90e2362Sianyar max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 1001a9a923e5SAnand Kumar Santhanam } else { 1002e90e2362Sianyar max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 1003a9a923e5SAnand Kumar Santhanam } 1004f5860992SSakthivel K do { 1005d71023afSakshatzen msleep(FW_READY_INTERVAL); 1006f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1007f5860992SSakthivel K value &= SPCv_MSGU_CFG_TABLE_UPDATE; 1008f5860992SSakthivel K } while ((value != 0) && (--max_wait_count)); 1009f5860992SSakthivel K 101005c6c029SViswas G if (!max_wait_count) { 101105c6c029SViswas G /* additional check */ 10121b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 10131b5d2793SJoe Perches "Inb doorbell clear not toggled[value:%x]\n", 10141b5d2793SJoe Perches value); 101505c6c029SViswas G return -EBUSY; 101605c6c029SViswas G } 1017f5860992SSakthivel K /* check the MPI-State for initialization up to 100ms*/ 1018d71023afSakshatzen max_wait_count = 5;/* 100 msec */ 1019f5860992SSakthivel K do { 1020d71023afSakshatzen msleep(FW_READY_INTERVAL); 1021f5860992SSakthivel K gst_len_mpistate = 1022f5860992SSakthivel K pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1023f5860992SSakthivel K GST_GSTLEN_MPIS_OFFSET); 1024f5860992SSakthivel K } while ((GST_MPI_STATE_INIT != 1025f5860992SSakthivel K (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); 1026f5860992SSakthivel K if (!max_wait_count) 102705c6c029SViswas G return -EBUSY; 1028f5860992SSakthivel K 1029f5860992SSakthivel K /* check MPI Initialization error */ 1030f5860992SSakthivel K gst_len_mpistate = gst_len_mpistate >> 16; 1031f5860992SSakthivel K if (0x0000 != gst_len_mpistate) 103205c6c029SViswas G return -EBUSY; 1033f5860992SSakthivel K 1034bcd8a452SAjish Koshy /* 1035bcd8a452SAjish Koshy * As per controller datasheet, after successful MPI 1036bcd8a452SAjish Koshy * initialization minimum 500ms delay is required before 1037bcd8a452SAjish Koshy * issuing commands. 1038bcd8a452SAjish Koshy */ 1039bcd8a452SAjish Koshy msleep(500); 1040bcd8a452SAjish Koshy 1041f5860992SSakthivel K return 0; 1042f5860992SSakthivel K } 1043f5860992SSakthivel K 1044f5860992SSakthivel K /** 1045f5860992SSakthivel K * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 104648cd6b38Sakshatzen * This function sleeps hence it must not be used in atomic context. 1047f5860992SSakthivel K * @pm8001_ha: our hba card information 1048f5860992SSakthivel K */ 1049f5860992SSakthivel K static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 1050f5860992SSakthivel K { 1051f5860992SSakthivel K u32 value; 1052f5860992SSakthivel K u32 max_wait_count; 1053f5860992SSakthivel K u32 max_wait_time; 10546b2f2d05SBhavesh Jashnani u32 expected_mask; 1055f5860992SSakthivel K int ret = 0; 1056f5860992SSakthivel K 1057f5860992SSakthivel K /* reset / PCIe ready */ 105848cd6b38Sakshatzen max_wait_time = max_wait_count = 5; /* 100 milli sec */ 1059f5860992SSakthivel K do { 106048cd6b38Sakshatzen msleep(FW_READY_INTERVAL); 1061f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1062f5860992SSakthivel K } while ((value == 0xFFFFFFFF) && (--max_wait_count)); 1063f5860992SSakthivel K 10646b2f2d05SBhavesh Jashnani /* check ila, RAAE and iops status */ 1065f5860992SSakthivel K if ((pm8001_ha->chip_id != chip_8008) && 1066f5860992SSakthivel K (pm8001_ha->chip_id != chip_8009)) { 10676b2f2d05SBhavesh Jashnani max_wait_time = max_wait_count = 180; /* 3600 milli sec */ 10686b2f2d05SBhavesh Jashnani expected_mask = SCRATCH_PAD_ILA_READY | 10696b2f2d05SBhavesh Jashnani SCRATCH_PAD_RAAE_READY | 10706b2f2d05SBhavesh Jashnani SCRATCH_PAD_IOP0_READY | 10716b2f2d05SBhavesh Jashnani SCRATCH_PAD_IOP1_READY; 10726b2f2d05SBhavesh Jashnani } else { 10736b2f2d05SBhavesh Jashnani max_wait_time = max_wait_count = 170; /* 3400 milli sec */ 10746b2f2d05SBhavesh Jashnani expected_mask = SCRATCH_PAD_ILA_READY | 10756b2f2d05SBhavesh Jashnani SCRATCH_PAD_RAAE_READY | 10766b2f2d05SBhavesh Jashnani SCRATCH_PAD_IOP0_READY; 10776b2f2d05SBhavesh Jashnani } 1078f5860992SSakthivel K do { 107948cd6b38Sakshatzen msleep(FW_READY_INTERVAL); 1080f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 10816b2f2d05SBhavesh Jashnani } while (((value & expected_mask) != 10826b2f2d05SBhavesh Jashnani expected_mask) && (--max_wait_count)); 10836b2f2d05SBhavesh Jashnani if (!max_wait_count) { 10846b2f2d05SBhavesh Jashnani pm8001_dbg(pm8001_ha, INIT, 10856b2f2d05SBhavesh Jashnani "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n", 10866b2f2d05SBhavesh Jashnani max_wait_time * FW_READY_INTERVAL, value); 1087f5860992SSakthivel K ret = -1; 10886b2f2d05SBhavesh Jashnani } else { 10891b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 10906b2f2d05SBhavesh Jashnani "All FW components ready by %d ms\n", 10916b2f2d05SBhavesh Jashnani (max_wait_time - max_wait_count) * FW_READY_INTERVAL); 1092f5860992SSakthivel K } 1093f5860992SSakthivel K return ret; 1094f5860992SSakthivel K } 1095f5860992SSakthivel K 109695652f98Sakshatzen static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 1097f5860992SSakthivel K { 1098f5860992SSakthivel K void __iomem *base_addr; 1099f5860992SSakthivel K u32 value; 1100f5860992SSakthivel K u32 offset; 1101f5860992SSakthivel K u32 pcibar; 1102f5860992SSakthivel K u32 pcilogic; 1103f5860992SSakthivel K 1104f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 110595652f98Sakshatzen 1106bb6beabfSRandy Dunlap /* 110795652f98Sakshatzen * lower 26 bits of SCRATCHPAD0 register describes offset within the 110895652f98Sakshatzen * PCIe BAR where the MPI configuration table is present 110995652f98Sakshatzen */ 1110f5860992SSakthivel K offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ 1111f5860992SSakthivel K 11121b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n", 11131b5d2793SJoe Perches offset, value); 1114bb6beabfSRandy Dunlap /* 111595652f98Sakshatzen * Upper 6 bits describe the offset within PCI config space where BAR 111695652f98Sakshatzen * is located. 111795652f98Sakshatzen */ 1118f5860992SSakthivel K pcilogic = (value & 0xFC000000) >> 26; 1119f5860992SSakthivel K pcibar = get_pci_bar_index(pcilogic); 11201b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); 112195652f98Sakshatzen 1122bb6beabfSRandy Dunlap /* 112395652f98Sakshatzen * Make sure the offset falls inside the ioremapped PCI BAR 112495652f98Sakshatzen */ 112595652f98Sakshatzen if (offset > pm8001_ha->io_mem[pcibar].memsize) { 112695652f98Sakshatzen pm8001_dbg(pm8001_ha, FAIL, 112795652f98Sakshatzen "Main cfg tbl offset outside %u > %u\n", 112895652f98Sakshatzen offset, pm8001_ha->io_mem[pcibar].memsize); 112995652f98Sakshatzen return -EBUSY; 113095652f98Sakshatzen } 1131f5860992SSakthivel K pm8001_ha->main_cfg_tbl_addr = base_addr = 1132f5860992SSakthivel K pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 113395652f98Sakshatzen 1134bb6beabfSRandy Dunlap /* 113595652f98Sakshatzen * Validate main configuration table address: first DWord should read 113695652f98Sakshatzen * "PMCS" 113795652f98Sakshatzen */ 113895652f98Sakshatzen value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0); 113995652f98Sakshatzen if (memcmp(&value, "PMCS", 4) != 0) { 114095652f98Sakshatzen pm8001_dbg(pm8001_ha, FAIL, 114195652f98Sakshatzen "BAD main config signature 0x%x\n", 114295652f98Sakshatzen value); 114395652f98Sakshatzen return -EBUSY; 114495652f98Sakshatzen } 114595652f98Sakshatzen pm8001_dbg(pm8001_ha, INIT, 114695652f98Sakshatzen "VALID main config signature 0x%x\n", value); 1147f5860992SSakthivel K pm8001_ha->general_stat_tbl_addr = 1148f5860992SSakthivel K base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 1149f5860992SSakthivel K 0xFFFFFF); 1150f5860992SSakthivel K pm8001_ha->inbnd_q_tbl_addr = 1151f5860992SSakthivel K base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & 1152f5860992SSakthivel K 0xFFFFFF); 1153f5860992SSakthivel K pm8001_ha->outbnd_q_tbl_addr = 1154f5860992SSakthivel K base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & 1155f5860992SSakthivel K 0xFFFFFF); 1156f5860992SSakthivel K pm8001_ha->ivt_tbl_addr = 1157f5860992SSakthivel K base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & 1158f5860992SSakthivel K 0xFFFFFF); 1159f5860992SSakthivel K pm8001_ha->pspa_q_tbl_addr = 1160f5860992SSakthivel K base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & 1161f5860992SSakthivel K 0xFFFFFF); 1162d078b511SAnand Kumar Santhanam pm8001_ha->fatal_tbl_addr = 1163d078b511SAnand Kumar Santhanam base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & 1164d078b511SAnand Kumar Santhanam 0xFFFFFF); 1165f5860992SSakthivel K 11661b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n", 11671b5d2793SJoe Perches pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)); 11681b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n", 11691b5d2793SJoe Perches pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)); 11701b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n", 11711b5d2793SJoe Perches pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)); 11721b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n", 11731b5d2793SJoe Perches pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)); 11741b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n", 11751b5d2793SJoe Perches pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)); 11761b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n", 1177f5860992SSakthivel K pm8001_ha->main_cfg_tbl_addr, 11781b5d2793SJoe Perches pm8001_ha->general_stat_tbl_addr); 11791b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n", 1180f5860992SSakthivel K pm8001_ha->inbnd_q_tbl_addr, 11811b5d2793SJoe Perches pm8001_ha->outbnd_q_tbl_addr); 11821b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n", 1183f5860992SSakthivel K pm8001_ha->pspa_q_tbl_addr, 11841b5d2793SJoe Perches pm8001_ha->ivt_tbl_addr); 118595652f98Sakshatzen return 0; 1186f5860992SSakthivel K } 1187f5860992SSakthivel K 1188f5860992SSakthivel K /** 1189f5860992SSakthivel K * pm80xx_set_thermal_config - support the thermal configuration 1190f5860992SSakthivel K * @pm8001_ha: our hba card information. 1191f5860992SSakthivel K */ 1192a6cb3d01SSakthivel K int 1193f5860992SSakthivel K pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) 1194f5860992SSakthivel K { 1195f5860992SSakthivel K struct set_ctrl_cfg_req payload; 1196f5860992SSakthivel K int rc; 1197f5860992SSakthivel K u32 tag; 1198f5860992SSakthivel K u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1199842784e0SViswas G u32 page_code; 1200f5860992SSakthivel K 1201f5860992SSakthivel K memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1202f5860992SSakthivel K rc = pm8001_tag_alloc(pm8001_ha, &tag); 1203f5860992SSakthivel K if (rc) 1204f17c599aSDamien Le Moal return rc; 1205f5860992SSakthivel K 1206f5860992SSakthivel K payload.tag = cpu_to_le32(tag); 1207842784e0SViswas G 1208842784e0SViswas G if (IS_SPCV_12G(pm8001_ha->pdev)) 1209842784e0SViswas G page_code = THERMAL_PAGE_CODE_7H; 1210842784e0SViswas G else 1211842784e0SViswas G page_code = THERMAL_PAGE_CODE_8H; 1212842784e0SViswas G 1213bb225b12SDamien Le Moal payload.cfg_pg[0] = 1214bb225b12SDamien Le Moal cpu_to_le32((THERMAL_LOG_ENABLE << 9) | 1215bb225b12SDamien Le Moal (THERMAL_ENABLE << 8) | page_code); 1216bb225b12SDamien Le Moal payload.cfg_pg[1] = 1217bb225b12SDamien Le Moal cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8)); 1218f5860992SSakthivel K 12191b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 12207370672dSpeter chang "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n", 12211b5d2793SJoe Perches payload.cfg_pg[0], payload.cfg_pg[1]); 12227370672dSpeter chang 1223f91767a3SDamien Le Moal rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 122491a43fa6Speter chang sizeof(payload), 0); 12255533abcaSTomas Henzl if (rc) 12265533abcaSTomas Henzl pm8001_tag_free(pm8001_ha, tag); 1227f5860992SSakthivel K return rc; 1228f5860992SSakthivel K 1229f5860992SSakthivel K } 1230f5860992SSakthivel K 1231f5860992SSakthivel K /** 1232a6cb3d01SSakthivel K * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol 1233a6cb3d01SSakthivel K * Timer configuration page 1234a6cb3d01SSakthivel K * @pm8001_ha: our hba card information. 1235a6cb3d01SSakthivel K */ 1236a6cb3d01SSakthivel K static int 1237a6cb3d01SSakthivel K pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) 1238a6cb3d01SSakthivel K { 1239a6cb3d01SSakthivel K struct set_ctrl_cfg_req payload; 1240a6cb3d01SSakthivel K SASProtocolTimerConfig_t SASConfigPage; 1241a6cb3d01SSakthivel K int rc; 1242a6cb3d01SSakthivel K u32 tag; 1243a6cb3d01SSakthivel K u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 1244a6cb3d01SSakthivel K 1245a6cb3d01SSakthivel K memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 1246a6cb3d01SSakthivel K memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); 1247a6cb3d01SSakthivel K 1248a6cb3d01SSakthivel K rc = pm8001_tag_alloc(pm8001_ha, &tag); 1249a6cb3d01SSakthivel K if (rc) 1250f17c599aSDamien Le Moal return rc; 1251a6cb3d01SSakthivel K 1252a6cb3d01SSakthivel K payload.tag = cpu_to_le32(tag); 1253a6cb3d01SSakthivel K 1254ca374f5dSDamien Le Moal SASConfigPage.pageCode = cpu_to_le32(SAS_PROTOCOL_TIMER_CONFIG_PAGE); 1255ca374f5dSDamien Le Moal SASConfigPage.MST_MSI = cpu_to_le32(3 << 15); 1256ca374f5dSDamien Le Moal SASConfigPage.STP_SSP_MCT_TMO = 1257ca374f5dSDamien Le Moal cpu_to_le32((STP_MCT_TMO << 16) | SSP_MCT_TMO); 1258ca374f5dSDamien Le Moal SASConfigPage.STP_FRM_TMO = 1259ca374f5dSDamien Le Moal cpu_to_le32((SAS_MAX_OPEN_TIME << 24) | 1260ca374f5dSDamien Le Moal (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER); 1261ca374f5dSDamien Le Moal SASConfigPage.STP_IDLE_TMO = cpu_to_le32(STP_IDLE_TIME); 1262a6cb3d01SSakthivel K 1263ca374f5dSDamien Le Moal SASConfigPage.OPNRJT_RTRY_INTVL = 1264ca374f5dSDamien Le Moal cpu_to_le32((SAS_MFD << 16) | SAS_OPNRJT_RTRY_INTVL); 1265ca374f5dSDamien Le Moal SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = 1266ca374f5dSDamien Le Moal cpu_to_le32((SAS_DOPNRJT_RTRY_TMO << 16) | SAS_COPNRJT_RTRY_TMO); 1267ca374f5dSDamien Le Moal SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = 1268ca374f5dSDamien Le Moal cpu_to_le32((SAS_DOPNRJT_RTRY_THR << 16) | SAS_COPNRJT_RTRY_THR); 1269ca374f5dSDamien Le Moal SASConfigPage.MAX_AIP = cpu_to_le32(SAS_MAX_AIP); 1270a6cb3d01SSakthivel K 12711b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n", 1272ca374f5dSDamien Le Moal le32_to_cpu(SASConfigPage.pageCode)); 12731b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n", 1274ca374f5dSDamien Le Moal le32_to_cpu(SASConfigPage.MST_MSI)); 12751b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n", 1276ca374f5dSDamien Le Moal le32_to_cpu(SASConfigPage.STP_SSP_MCT_TMO)); 12771b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n", 1278ca374f5dSDamien Le Moal le32_to_cpu(SASConfigPage.STP_FRM_TMO)); 12791b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n", 1280ca374f5dSDamien Le Moal le32_to_cpu(SASConfigPage.STP_IDLE_TMO)); 12811b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n", 1282ca374f5dSDamien Le Moal le32_to_cpu(SASConfigPage.OPNRJT_RTRY_INTVL)); 12831b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n", 1284ca374f5dSDamien Le Moal le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO)); 12851b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n", 1286ca374f5dSDamien Le Moal le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR)); 12871b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n", 1288ca374f5dSDamien Le Moal le32_to_cpu(SASConfigPage.MAX_AIP)); 1289a6cb3d01SSakthivel K 1290a6cb3d01SSakthivel K memcpy(&payload.cfg_pg, &SASConfigPage, 1291a6cb3d01SSakthivel K sizeof(SASProtocolTimerConfig_t)); 1292a6cb3d01SSakthivel K 1293f91767a3SDamien Le Moal rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 129491a43fa6Speter chang sizeof(payload), 0); 12955533abcaSTomas Henzl if (rc) 12965533abcaSTomas Henzl pm8001_tag_free(pm8001_ha, tag); 1297a6cb3d01SSakthivel K 1298a6cb3d01SSakthivel K return rc; 1299a6cb3d01SSakthivel K } 1300a6cb3d01SSakthivel K 1301a6cb3d01SSakthivel K /** 1302f5860992SSakthivel K * pm80xx_get_encrypt_info - Check for encryption 1303f5860992SSakthivel K * @pm8001_ha: our hba card information. 1304f5860992SSakthivel K */ 1305f5860992SSakthivel K static int 1306f5860992SSakthivel K pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) 1307f5860992SSakthivel K { 1308f5860992SSakthivel K u32 scratch3_value; 1309da225498SRickard Strandqvist int ret = -1; 1310f5860992SSakthivel K 1311f5860992SSakthivel K /* Read encryption status from SCRATCH PAD 3 */ 1312f5860992SSakthivel K scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1313f5860992SSakthivel K 1314f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1315f5860992SSakthivel K SCRATCH_PAD3_ENC_READY) { 1316f5860992SSakthivel K if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1317f5860992SSakthivel K pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1318f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1319f5860992SSakthivel K SCRATCH_PAD3_SMF_ENABLED) 1320f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1321f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1322f5860992SSakthivel K SCRATCH_PAD3_SMA_ENABLED) 1323f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1324f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1325f5860992SSakthivel K SCRATCH_PAD3_SMB_ENABLED) 1326f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1327f5860992SSakthivel K pm8001_ha->encrypt_info.status = 0; 13281b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, 13291b5d2793SJoe Perches "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", 13301b5d2793SJoe Perches scratch3_value, 13311b5d2793SJoe Perches pm8001_ha->encrypt_info.cipher_mode, 1332f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode, 13331b5d2793SJoe Perches pm8001_ha->encrypt_info.status); 1334f5860992SSakthivel K ret = 0; 1335f5860992SSakthivel K } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == 1336f5860992SSakthivel K SCRATCH_PAD3_ENC_DISABLED) { 13371b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, 1338f5860992SSakthivel K "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", 13391b5d2793SJoe Perches scratch3_value); 1340f5860992SSakthivel K pm8001_ha->encrypt_info.status = 0xFFFFFFFF; 1341f5860992SSakthivel K pm8001_ha->encrypt_info.cipher_mode = 0; 1342f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = 0; 1343da225498SRickard Strandqvist ret = 0; 1344f5860992SSakthivel K } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1345f5860992SSakthivel K SCRATCH_PAD3_ENC_DIS_ERR) { 1346f5860992SSakthivel K pm8001_ha->encrypt_info.status = 1347f5860992SSakthivel K (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1348f5860992SSakthivel K if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1349f5860992SSakthivel K pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1350f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1351f5860992SSakthivel K SCRATCH_PAD3_SMF_ENABLED) 1352f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1353f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1354f5860992SSakthivel K SCRATCH_PAD3_SMA_ENABLED) 1355f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1356f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1357f5860992SSakthivel K SCRATCH_PAD3_SMB_ENABLED) 1358f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 13591b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, 13601b5d2793SJoe Perches "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 13611b5d2793SJoe Perches scratch3_value, 13621b5d2793SJoe Perches pm8001_ha->encrypt_info.cipher_mode, 1363f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode, 13641b5d2793SJoe Perches pm8001_ha->encrypt_info.status); 1365f5860992SSakthivel K } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 1366f5860992SSakthivel K SCRATCH_PAD3_ENC_ENA_ERR) { 1367f5860992SSakthivel K 1368f5860992SSakthivel K pm8001_ha->encrypt_info.status = 1369f5860992SSakthivel K (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 1370f5860992SSakthivel K if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 1371f5860992SSakthivel K pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 1372f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1373f5860992SSakthivel K SCRATCH_PAD3_SMF_ENABLED) 1374f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 1375f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1376f5860992SSakthivel K SCRATCH_PAD3_SMA_ENABLED) 1377f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 1378f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 1379f5860992SSakthivel K SCRATCH_PAD3_SMB_ENABLED) 1380f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 1381f5860992SSakthivel K 13821b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, 13831b5d2793SJoe Perches "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 13841b5d2793SJoe Perches scratch3_value, 13851b5d2793SJoe Perches pm8001_ha->encrypt_info.cipher_mode, 1386f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode, 13871b5d2793SJoe Perches pm8001_ha->encrypt_info.status); 1388f5860992SSakthivel K } 1389f5860992SSakthivel K return ret; 1390f5860992SSakthivel K } 1391f5860992SSakthivel K 1392f5860992SSakthivel K /** 1393bb6beabfSRandy Dunlap * pm80xx_encrypt_update - update flash with encryption information 1394f5860992SSakthivel K * @pm8001_ha: our hba card information. 1395f5860992SSakthivel K */ 1396f5860992SSakthivel K static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) 1397f5860992SSakthivel K { 1398f5860992SSakthivel K struct kek_mgmt_req payload; 1399f5860992SSakthivel K int rc; 1400f5860992SSakthivel K u32 tag; 1401f5860992SSakthivel K u32 opc = OPC_INB_KEK_MANAGEMENT; 1402f5860992SSakthivel K 1403f5860992SSakthivel K memset(&payload, 0, sizeof(struct kek_mgmt_req)); 1404f5860992SSakthivel K rc = pm8001_tag_alloc(pm8001_ha, &tag); 1405f5860992SSakthivel K if (rc) 1406f17c599aSDamien Le Moal return rc; 1407f5860992SSakthivel K 1408f5860992SSakthivel K payload.tag = cpu_to_le32(tag); 1409f5860992SSakthivel K /* Currently only one key is used. New KEK index is 1. 1410f5860992SSakthivel K * Current KEK index is 1. Store KEK to NVRAM is 1. 1411f5860992SSakthivel K */ 1412f8b12dfbSDamien Le Moal payload.new_curidx_ksop = 1413f8b12dfbSDamien Le Moal cpu_to_le32(((1 << 24) | (1 << 16) | (1 << 8) | 1414f8b12dfbSDamien Le Moal KEK_MGMT_SUBOP_KEYCARDUPDATE)); 1415f5860992SSakthivel K 14161b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 14177370672dSpeter chang "Saving Encryption info to flash. payload 0x%x\n", 1418f8b12dfbSDamien Le Moal le32_to_cpu(payload.new_curidx_ksop)); 14197370672dSpeter chang 1420f91767a3SDamien Le Moal rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 142191a43fa6Speter chang sizeof(payload), 0); 14225533abcaSTomas Henzl if (rc) 14235533abcaSTomas Henzl pm8001_tag_free(pm8001_ha, tag); 1424f5860992SSakthivel K 1425f5860992SSakthivel K return rc; 1426f5860992SSakthivel K } 1427f5860992SSakthivel K 1428f5860992SSakthivel K /** 1429bb6beabfSRandy Dunlap * pm80xx_chip_init - the main init function that initializes whole PM8001 chip. 1430f5860992SSakthivel K * @pm8001_ha: our hba card information 1431f5860992SSakthivel K */ 1432f5860992SSakthivel K static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) 1433f5860992SSakthivel K { 1434f5860992SSakthivel K int ret; 1435f5860992SSakthivel K u8 i = 0; 1436f5860992SSakthivel K 1437f5860992SSakthivel K /* check the firmware status */ 1438f5860992SSakthivel K if (-1 == check_fw_ready(pm8001_ha)) { 14391b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 1440f5860992SSakthivel K return -EBUSY; 1441f5860992SSakthivel K } 1442f5860992SSakthivel K 144372349b62SDeepak Ukey /* Initialize the controller fatal error flag */ 144472349b62SDeepak Ukey pm8001_ha->controller_fatal_error = false; 144572349b62SDeepak Ukey 1446f5860992SSakthivel K /* Initialize pci space address eg: mpi offset */ 144795652f98Sakshatzen ret = init_pci_device_addresses(pm8001_ha); 144895652f98Sakshatzen if (ret) { 144995652f98Sakshatzen pm8001_dbg(pm8001_ha, FAIL, 145095652f98Sakshatzen "Failed to init pci addresses"); 145195652f98Sakshatzen return ret; 145295652f98Sakshatzen } 1453f5860992SSakthivel K init_default_table_values(pm8001_ha); 1454f5860992SSakthivel K read_main_config_table(pm8001_ha); 1455f5860992SSakthivel K read_general_status_table(pm8001_ha); 1456f5860992SSakthivel K read_inbnd_queue_table(pm8001_ha); 1457f5860992SSakthivel K read_outbnd_queue_table(pm8001_ha); 1458f5860992SSakthivel K read_phy_attr_table(pm8001_ha); 1459f5860992SSakthivel K 1460f5860992SSakthivel K /* update main config table ,inbound table and outbound table */ 1461f5860992SSakthivel K update_main_config_table(pm8001_ha); 146205c6c029SViswas G for (i = 0; i < pm8001_ha->max_q_num; i++) { 1463f5860992SSakthivel K update_inbnd_queue_table(pm8001_ha, i); 1464f5860992SSakthivel K update_outbnd_queue_table(pm8001_ha, i); 146505c6c029SViswas G } 1466f5860992SSakthivel K /* notify firmware update finished and check initialization status */ 1467f5860992SSakthivel K if (0 == mpi_init_check(pm8001_ha)) { 14681b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n"); 1469f5860992SSakthivel K } else 1470f5860992SSakthivel K return -EBUSY; 1471f5860992SSakthivel K 147298132d84SJohn Garry return 0; 147398132d84SJohn Garry } 147498132d84SJohn Garry 147598132d84SJohn Garry static void pm80xx_chip_post_init(struct pm8001_hba_info *pm8001_ha) 147698132d84SJohn Garry { 1477a6cb3d01SSakthivel K /* send SAS protocol timer configuration page to FW */ 147898132d84SJohn Garry pm80xx_set_sas_protocol_timer_config(pm8001_ha); 1479f5860992SSakthivel K 1480f5860992SSakthivel K /* Check for encryption */ 1481f5860992SSakthivel K if (pm8001_ha->chip->encrypt) { 148298132d84SJohn Garry int ret; 148398132d84SJohn Garry 14841b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n"); 1485f5860992SSakthivel K ret = pm80xx_get_encrypt_info(pm8001_ha); 1486f5860992SSakthivel K if (ret == -1) { 14871b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n"); 1488f5860992SSakthivel K if (pm8001_ha->encrypt_info.status == 0x81) { 14891b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, 14901b5d2793SJoe Perches "Encryption enabled with error.Saving encryption key to flash\n"); 1491f5860992SSakthivel K pm80xx_encrypt_update(pm8001_ha); 1492f5860992SSakthivel K } 1493f5860992SSakthivel K } 1494f5860992SSakthivel K } 1495f5860992SSakthivel K } 1496f5860992SSakthivel K 1497f5860992SSakthivel K static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 1498f5860992SSakthivel K { 1499f5860992SSakthivel K u32 max_wait_count; 1500f5860992SSakthivel K u32 value; 1501f5860992SSakthivel K u32 gst_len_mpistate; 150295652f98Sakshatzen int ret; 150395652f98Sakshatzen 150495652f98Sakshatzen ret = init_pci_device_addresses(pm8001_ha); 150595652f98Sakshatzen if (ret) { 150695652f98Sakshatzen pm8001_dbg(pm8001_ha, FAIL, 150795652f98Sakshatzen "Failed to init pci addresses"); 150895652f98Sakshatzen return ret; 150995652f98Sakshatzen } 151095652f98Sakshatzen 1511f5860992SSakthivel K /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 1512f5860992SSakthivel K table is stop */ 1513f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); 1514f5860992SSakthivel K 1515f5860992SSakthivel K /* wait until Inbound DoorBell Clear Register toggled */ 1516a9a923e5SAnand Kumar Santhanam if (IS_SPCV_12G(pm8001_ha->pdev)) { 15176f305bf6SIgor Pylypiv max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT; 1518a9a923e5SAnand Kumar Santhanam } else { 15196f305bf6SIgor Pylypiv max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT; 1520a9a923e5SAnand Kumar Santhanam } 1521f5860992SSakthivel K do { 15226f305bf6SIgor Pylypiv msleep(FW_READY_INTERVAL); 1523f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 1524f5860992SSakthivel K value &= SPCv_MSGU_CFG_TABLE_RESET; 1525f5860992SSakthivel K } while ((value != 0) && (--max_wait_count)); 1526f5860992SSakthivel K 1527f5860992SSakthivel K if (!max_wait_count) { 15281b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value); 1529f5860992SSakthivel K return -1; 1530f5860992SSakthivel K } 1531f5860992SSakthivel K 1532f5860992SSakthivel K /* check the MPI-State for termination in progress */ 1533f5860992SSakthivel K /* wait until Inbound DoorBell Clear Register toggled */ 15346f305bf6SIgor Pylypiv max_wait_count = 100; /* 2 sec for spcv/ve */ 1535f5860992SSakthivel K do { 15366f305bf6SIgor Pylypiv msleep(FW_READY_INTERVAL); 1537f5860992SSakthivel K gst_len_mpistate = 1538f5860992SSakthivel K pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 1539f5860992SSakthivel K GST_GSTLEN_MPIS_OFFSET); 1540f5860992SSakthivel K if (GST_MPI_STATE_UNINIT == 1541f5860992SSakthivel K (gst_len_mpistate & GST_MPI_STATE_MASK)) 1542f5860992SSakthivel K break; 1543f5860992SSakthivel K } while (--max_wait_count); 1544f5860992SSakthivel K if (!max_wait_count) { 15451b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", 15461b5d2793SJoe Perches gst_len_mpistate & GST_MPI_STATE_MASK); 1547f5860992SSakthivel K return -1; 1548f5860992SSakthivel K } 1549f5860992SSakthivel K 1550f5860992SSakthivel K return 0; 1551f5860992SSakthivel K } 1552f5860992SSakthivel K 1553f5860992SSakthivel K /** 1554bb6beabfSRandy Dunlap * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors 1555a961ea0aSakshatzen * @pm8001_ha: our hba card information 1556a961ea0aSakshatzen * 1557a961ea0aSakshatzen * Fatal errors are recoverable only after a host reboot. 1558a961ea0aSakshatzen */ 1559a961ea0aSakshatzen int 1560a961ea0aSakshatzen pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha) 1561a961ea0aSakshatzen { 1562a961ea0aSakshatzen int ret = 0; 1563a961ea0aSakshatzen u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0, 156480cac47bSAjish Koshy MSGU_SCRATCH_PAD_RSVD_0); 1565a961ea0aSakshatzen u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0, 156680cac47bSAjish Koshy MSGU_SCRATCH_PAD_RSVD_1); 1567a961ea0aSakshatzen u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1568a961ea0aSakshatzen u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1569a961ea0aSakshatzen u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 1570a961ea0aSakshatzen 1571a961ea0aSakshatzen if (pm8001_ha->chip_id != chip_8006 && 1572a961ea0aSakshatzen pm8001_ha->chip_id != chip_8074 && 1573a961ea0aSakshatzen pm8001_ha->chip_id != chip_8076) { 1574a961ea0aSakshatzen return 0; 1575a961ea0aSakshatzen } 1576a961ea0aSakshatzen 1577a961ea0aSakshatzen if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) { 1578a961ea0aSakshatzen pm8001_dbg(pm8001_ha, FAIL, 1579a961ea0aSakshatzen "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n", 1580a961ea0aSakshatzen scratch_pad1, scratch_pad2, scratch_pad3, 1581a961ea0aSakshatzen scratch_pad_rsvd0, scratch_pad_rsvd1); 1582a961ea0aSakshatzen ret = 1; 1583a961ea0aSakshatzen } 1584a961ea0aSakshatzen 1585a961ea0aSakshatzen return ret; 1586a961ea0aSakshatzen } 1587a961ea0aSakshatzen 1588a961ea0aSakshatzen /** 1589bb6beabfSRandy Dunlap * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all 1590bb6beabfSRandy Dunlap * FW register status are reset to the originated status. 1591f5860992SSakthivel K * @pm8001_ha: our hba card information 1592f5860992SSakthivel K */ 1593f5860992SSakthivel K 1594f5860992SSakthivel K static int 1595f5860992SSakthivel K pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 1596f5860992SSakthivel K { 1597f5860992SSakthivel K u32 regval; 1598f5860992SSakthivel K u32 bootloader_state; 159906f12f22SAnand Kumar Santhanam u32 ibutton0, ibutton1; 1600f5860992SSakthivel K 160172349b62SDeepak Ukey /* Process MPI table uninitialization only if FW is ready */ 160272349b62SDeepak Ukey if (!pm8001_ha->controller_fatal_error) { 1603f5860992SSakthivel K /* Check if MPI is in ready state to reset */ 1604f5860992SSakthivel K if (mpi_uninit_check(pm8001_ha) != 0) { 1605d384be6eSVikram Auradkar u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 1606d384be6eSVikram Auradkar u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1607d384be6eSVikram Auradkar u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1608d384be6eSVikram Auradkar u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 16091b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 1610d384be6eSVikram Auradkar "MPI state is not ready scratch: %x:%x:%x:%x\n", 16111b5d2793SJoe Perches r0, r1, r2, r3); 1612d384be6eSVikram Auradkar /* if things aren't ready but the bootloader is ok then 1613d384be6eSVikram Auradkar * try the reset anyway. 1614d384be6eSVikram Auradkar */ 1615d384be6eSVikram Auradkar if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK) 1616f5860992SSakthivel K return -1; 1617f5860992SSakthivel K } 161872349b62SDeepak Ukey } 1619f5860992SSakthivel K /* checked for reset register normal state; 0x0 */ 1620f5860992SSakthivel K regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 16211b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n", 16221b5d2793SJoe Perches regval); 1623f5860992SSakthivel K 1624f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); 16254daf1ef3SVikram Auradkar msleep(500); 1626f5860992SSakthivel K 1627f5860992SSakthivel K regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 16281b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n", 16291b5d2793SJoe Perches regval); 1630f5860992SSakthivel K 1631f5860992SSakthivel K if ((regval & SPCv_SOFT_RESET_READ_MASK) == 1632f5860992SSakthivel K SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { 16331b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 16341b5d2793SJoe Perches " soft reset successful [regval: 0x%x]\n", 16351b5d2793SJoe Perches regval); 1636f5860992SSakthivel K } else { 16371b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 16381b5d2793SJoe Perches " soft reset failed [regval: 0x%x]\n", 16391b5d2793SJoe Perches regval); 1640f5860992SSakthivel K 1641f5860992SSakthivel K /* check bootloader is successfully executed or in HDA mode */ 1642f5860992SSakthivel K bootloader_state = 1643f5860992SSakthivel K pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1644f5860992SSakthivel K SCRATCH_PAD1_BOOTSTATE_MASK; 1645f5860992SSakthivel K 1646f5860992SSakthivel K if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { 16471b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 16481b5d2793SJoe Perches "Bootloader state - HDA mode SEEPROM\n"); 1649f5860992SSakthivel K } else if (bootloader_state == 1650f5860992SSakthivel K SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { 16511b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 16521b5d2793SJoe Perches "Bootloader state - HDA mode Bootstrap Pin\n"); 1653f5860992SSakthivel K } else if (bootloader_state == 1654f5860992SSakthivel K SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { 16551b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 16561b5d2793SJoe Perches "Bootloader state - HDA mode soft reset\n"); 1657f5860992SSakthivel K } else if (bootloader_state == 1658f5860992SSakthivel K SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { 16591b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 16601b5d2793SJoe Perches "Bootloader state-HDA mode critical error\n"); 1661f5860992SSakthivel K } 1662f5860992SSakthivel K return -EBUSY; 1663f5860992SSakthivel K } 1664f5860992SSakthivel K 1665f5860992SSakthivel K /* check the firmware status after reset */ 1666f5860992SSakthivel K if (-1 == check_fw_ready(pm8001_ha)) { 16671b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); 166806f12f22SAnand Kumar Santhanam /* check iButton feature support for motherboard controller */ 166906f12f22SAnand Kumar Santhanam if (pm8001_ha->pdev->subsystem_vendor != 167006f12f22SAnand Kumar Santhanam PCI_VENDOR_ID_ADAPTEC2 && 1671faf321b0SBenjamin Rood pm8001_ha->pdev->subsystem_vendor != 1672faf321b0SBenjamin Rood PCI_VENDOR_ID_ATTO && 167306f12f22SAnand Kumar Santhanam pm8001_ha->pdev->subsystem_vendor != 0) { 167406f12f22SAnand Kumar Santhanam ibutton0 = pm8001_cr32(pm8001_ha, 0, 167580cac47bSAjish Koshy MSGU_SCRATCH_PAD_RSVD_0); 167606f12f22SAnand Kumar Santhanam ibutton1 = pm8001_cr32(pm8001_ha, 0, 167780cac47bSAjish Koshy MSGU_SCRATCH_PAD_RSVD_1); 167806f12f22SAnand Kumar Santhanam if (!ibutton0 && !ibutton1) { 16791b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 16801b5d2793SJoe Perches "iButton Feature is not Available!!!\n"); 1681f5860992SSakthivel K return -EBUSY; 1682f5860992SSakthivel K } 168306f12f22SAnand Kumar Santhanam if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { 16841b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 16851b5d2793SJoe Perches "CRC Check for iButton Feature Failed!!!\n"); 168606f12f22SAnand Kumar Santhanam return -EBUSY; 168706f12f22SAnand Kumar Santhanam } 168806f12f22SAnand Kumar Santhanam } 168906f12f22SAnand Kumar Santhanam } 16901b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n"); 1691f5860992SSakthivel K return 0; 1692f5860992SSakthivel K } 1693f5860992SSakthivel K 1694f5860992SSakthivel K static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1695f5860992SSakthivel K { 1696f5860992SSakthivel K u32 i; 1697f5860992SSakthivel K 16981b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "chip reset start\n"); 1699f5860992SSakthivel K 1700f5860992SSakthivel K /* do SPCv chip reset. */ 1701f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); 17021b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n"); 1703f5860992SSakthivel K 1704f5860992SSakthivel K /* Check this ..whether delay is required or no */ 1705f5860992SSakthivel K /* delay 10 usec */ 1706f5860992SSakthivel K udelay(10); 1707f5860992SSakthivel K 1708f5860992SSakthivel K /* wait for 20 msec until the firmware gets reloaded */ 1709f5860992SSakthivel K i = 20; 1710f5860992SSakthivel K do { 1711f5860992SSakthivel K mdelay(1); 1712f5860992SSakthivel K } while ((--i) != 0); 1713f5860992SSakthivel K 17141b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); 1715f5860992SSakthivel K } 1716f5860992SSakthivel K 1717f5860992SSakthivel K /** 17187cdaf12eSLee Jones * pm80xx_chip_intx_interrupt_enable - enable PM8001 chip interrupt 1719f5860992SSakthivel K * @pm8001_ha: our hba card information 1720f5860992SSakthivel K */ 1721f5860992SSakthivel K static void 1722f5860992SSakthivel K pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1723f5860992SSakthivel K { 1724f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1725f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1726f5860992SSakthivel K } 1727f5860992SSakthivel K 1728f5860992SSakthivel K /** 17297cdaf12eSLee Jones * pm80xx_chip_intx_interrupt_disable - disable PM8001 chip interrupt 1730f5860992SSakthivel K * @pm8001_ha: our hba card information 1731f5860992SSakthivel K */ 1732f5860992SSakthivel K static void 1733f5860992SSakthivel K pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1734f5860992SSakthivel K { 1735f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); 1736f5860992SSakthivel K } 1737f5860992SSakthivel K 1738f5860992SSakthivel K /** 17397cdaf12eSLee Jones * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt 1740f5860992SSakthivel K * @pm8001_ha: our hba card information 17416ad4a517SLee Jones * @vec: interrupt number to enable 1742f5860992SSakthivel K */ 1743f5860992SSakthivel K static void 1744f5860992SSakthivel K pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1745f5860992SSakthivel K { 1746f5860992SSakthivel K #ifdef PM8001_USE_MSIX 1747294080eaSAjish Koshy if (vec < 32) 1748294080eaSAjish Koshy pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec); 1749294080eaSAjish Koshy else 1750294080eaSAjish Koshy pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, 1751294080eaSAjish Koshy 1U << (vec - 32)); 1752f5860992SSakthivel K return; 1753f5860992SSakthivel K #endif 1754f5860992SSakthivel K pm80xx_chip_intx_interrupt_enable(pm8001_ha); 1755f5860992SSakthivel K 1756f5860992SSakthivel K } 1757f5860992SSakthivel K 1758f5860992SSakthivel K /** 17597cdaf12eSLee Jones * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt 1760f5860992SSakthivel K * @pm8001_ha: our hba card information 17616ad4a517SLee Jones * @vec: interrupt number to disable 1762f5860992SSakthivel K */ 1763f5860992SSakthivel K static void 1764f5860992SSakthivel K pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1765f5860992SSakthivel K { 1766f5860992SSakthivel K #ifdef PM8001_USE_MSIX 1767294080eaSAjish Koshy if (vec == 0xFF) { 1768294080eaSAjish Koshy /* disable all vectors 0-31, 32-63 */ 1769294080eaSAjish Koshy pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF); 1770294080eaSAjish Koshy pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF); 1771294080eaSAjish Koshy } else if (vec < 32) 1772294080eaSAjish Koshy pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec); 1773f5860992SSakthivel K else 1774294080eaSAjish Koshy pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 1775294080eaSAjish Koshy 1U << (vec - 32)); 1776f5860992SSakthivel K return; 1777f5860992SSakthivel K #endif 1778f5860992SSakthivel K pm80xx_chip_intx_interrupt_disable(pm8001_ha); 1779f5860992SSakthivel K } 1780f5860992SSakthivel K 1781c6b9ef57SSakthivel K static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1782c6b9ef57SSakthivel K struct pm8001_device *pm8001_ha_dev) 1783c6b9ef57SSakthivel K { 1784c6b9ef57SSakthivel K struct pm8001_ccb_info *ccb; 1785ca44f98dSDamien Le Moal struct sas_task *task; 1786c6b9ef57SSakthivel K struct task_abort_req task_abort; 1787c6b9ef57SSakthivel K u32 opc = OPC_INB_SATA_ABORT; 1788c6b9ef57SSakthivel K int ret; 1789c6b9ef57SSakthivel K 1790ca44f98dSDamien Le Moal pm8001_ha_dev->id |= NCQ_ABORT_ALL_FLAG; 1791ca44f98dSDamien Le Moal pm8001_ha_dev->id &= ~NCQ_READ_LOG_FLAG; 1792c6b9ef57SSakthivel K 1793c6b9ef57SSakthivel K task = sas_alloc_slow_task(GFP_ATOMIC); 1794c6b9ef57SSakthivel K if (!task) { 17951b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n"); 1796c6b9ef57SSakthivel K return; 1797c6b9ef57SSakthivel K } 1798c6b9ef57SSakthivel K task->task_done = pm8001_task_done; 1799c6b9ef57SSakthivel K 180099df0edbSDamien Le Moal ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task); 180199df0edbSDamien Le Moal if (!ccb) { 18025533abcaSTomas Henzl sas_free_task(task); 1803c6b9ef57SSakthivel K return; 18045533abcaSTomas Henzl } 1805c6b9ef57SSakthivel K 1806c6b9ef57SSakthivel K memset(&task_abort, 0, sizeof(task_abort)); 1807c6b9ef57SSakthivel K task_abort.abort_all = cpu_to_le32(1); 1808c6b9ef57SSakthivel K task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 180999df0edbSDamien Le Moal task_abort.tag = cpu_to_le32(ccb->ccb_tag); 1810c6b9ef57SSakthivel K 1811f91767a3SDamien Le Moal ret = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort, 181291a43fa6Speter chang sizeof(task_abort), 0); 18131b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n"); 18145533abcaSTomas Henzl if (ret) { 18155533abcaSTomas Henzl sas_free_task(task); 181699df0edbSDamien Le Moal pm8001_ccb_free(pm8001_ha, ccb); 18175533abcaSTomas Henzl } 1818c6b9ef57SSakthivel K } 1819c6b9ef57SSakthivel K 1820c6b9ef57SSakthivel K static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha, 1821c6b9ef57SSakthivel K struct pm8001_device *pm8001_ha_dev) 1822c6b9ef57SSakthivel K { 1823c6b9ef57SSakthivel K struct sata_start_req sata_cmd; 1824c6b9ef57SSakthivel K int res; 1825c6b9ef57SSakthivel K struct pm8001_ccb_info *ccb; 1826c6b9ef57SSakthivel K struct sas_task *task = NULL; 1827c6b9ef57SSakthivel K struct host_to_dev_fis fis; 1828c6b9ef57SSakthivel K struct domain_device *dev; 1829c6b9ef57SSakthivel K u32 opc = OPC_INB_SATA_HOST_OPSTART; 1830c6b9ef57SSakthivel K 1831c6b9ef57SSakthivel K task = sas_alloc_slow_task(GFP_ATOMIC); 1832c6b9ef57SSakthivel K if (!task) { 18331b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n"); 1834c6b9ef57SSakthivel K return; 1835c6b9ef57SSakthivel K } 1836c6b9ef57SSakthivel K task->task_done = pm8001_task_done; 1837c6b9ef57SSakthivel K 183899df0edbSDamien Le Moal /* 183999df0edbSDamien Le Moal * Allocate domain device by ourselves as libsas is not going to 184099df0edbSDamien Le Moal * provide any. 1841c6b9ef57SSakthivel K */ 1842c6b9ef57SSakthivel K dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1843c6b9ef57SSakthivel K if (!dev) { 18445533abcaSTomas Henzl sas_free_task(task); 18451b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 18461b5d2793SJoe Perches "Domain device cannot be allocated\n"); 1847c6b9ef57SSakthivel K return; 18485533abcaSTomas Henzl } 18495533abcaSTomas Henzl 1850c6b9ef57SSakthivel K task->dev = dev; 1851c6b9ef57SSakthivel K task->dev->lldd_dev = pm8001_ha_dev; 1852c6b9ef57SSakthivel K 185399df0edbSDamien Le Moal ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task); 185499df0edbSDamien Le Moal if (!ccb) { 185599df0edbSDamien Le Moal sas_free_task(task); 185699df0edbSDamien Le Moal kfree(dev); 185799df0edbSDamien Le Moal return; 185899df0edbSDamien Le Moal } 185999df0edbSDamien Le Moal 1860c6b9ef57SSakthivel K pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1861c6b9ef57SSakthivel K pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1862c6b9ef57SSakthivel K 1863c6b9ef57SSakthivel K memset(&sata_cmd, 0, sizeof(sata_cmd)); 1864c6b9ef57SSakthivel K 1865c6b9ef57SSakthivel K /* construct read log FIS */ 1866c6b9ef57SSakthivel K memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1867c6b9ef57SSakthivel K fis.fis_type = 0x27; 1868c6b9ef57SSakthivel K fis.flags = 0x80; 1869c6b9ef57SSakthivel K fis.command = ATA_CMD_READ_LOG_EXT; 1870c6b9ef57SSakthivel K fis.lbal = 0x10; 1871c6b9ef57SSakthivel K fis.sector_count = 0x1; 1872c6b9ef57SSakthivel K 187399df0edbSDamien Le Moal sata_cmd.tag = cpu_to_le32(ccb->ccb_tag); 1874c6b9ef57SSakthivel K sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 18751a37b673SDamien Le Moal sata_cmd.ncqtag_atap_dir_m_dad = cpu_to_le32(((0x1 << 7) | (0x5 << 9))); 1876c6b9ef57SSakthivel K memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1877c6b9ef57SSakthivel K 1878f91767a3SDamien Le Moal res = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd, 187991a43fa6Speter chang sizeof(sata_cmd), 0); 18801b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n"); 18815533abcaSTomas Henzl if (res) { 18825533abcaSTomas Henzl sas_free_task(task); 188399df0edbSDamien Le Moal pm8001_ccb_free(pm8001_ha, ccb); 18845533abcaSTomas Henzl kfree(dev); 18855533abcaSTomas Henzl } 1886c6b9ef57SSakthivel K } 1887c6b9ef57SSakthivel K 1888f5860992SSakthivel K /** 1889f5860992SSakthivel K * mpi_ssp_completion - process the event that FW response to the SSP request. 1890f5860992SSakthivel K * @pm8001_ha: our hba card information 1891f5860992SSakthivel K * @piomb: the message contents of this outbound message. 1892f5860992SSakthivel K * 1893f5860992SSakthivel K * When FW has completed a ssp request for example a IO request, after it has 1894bb6beabfSRandy Dunlap * filled the SG data with the data, it will trigger this event representing 1895bb6beabfSRandy Dunlap * that he has finished the job; please check the corresponding buffer. 1896f5860992SSakthivel K * So we will tell the caller who maybe waiting the result to tell upper layer 1897f5860992SSakthivel K * that the task has been finished. 1898f5860992SSakthivel K */ 1899f5860992SSakthivel K static void 1900f5860992SSakthivel K mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 1901f5860992SSakthivel K { 1902f5860992SSakthivel K struct sas_task *t; 1903f5860992SSakthivel K struct pm8001_ccb_info *ccb; 1904f5860992SSakthivel K unsigned long flags; 1905f5860992SSakthivel K u32 status; 1906f5860992SSakthivel K u32 param; 1907f5860992SSakthivel K u32 tag; 1908f5860992SSakthivel K struct ssp_completion_resp *psspPayload; 1909f5860992SSakthivel K struct task_status_struct *ts; 1910f5860992SSakthivel K struct ssp_response_iu *iu; 1911f5860992SSakthivel K struct pm8001_device *pm8001_dev; 1912f5860992SSakthivel K psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1913f5860992SSakthivel K status = le32_to_cpu(psspPayload->status); 1914f5860992SSakthivel K tag = le32_to_cpu(psspPayload->tag); 1915f5860992SSakthivel K ccb = &pm8001_ha->ccb_info[tag]; 1916f5860992SSakthivel K if ((status == IO_ABORTED) && ccb->open_retry) { 1917f5860992SSakthivel K /* Being completed by another */ 1918f5860992SSakthivel K ccb->open_retry = 0; 1919f5860992SSakthivel K return; 1920f5860992SSakthivel K } 1921f5860992SSakthivel K pm8001_dev = ccb->device; 1922f5860992SSakthivel K param = le32_to_cpu(psspPayload->param); 1923f5860992SSakthivel K t = ccb->task; 1924f5860992SSakthivel K 1925f5860992SSakthivel K if (status && status != IO_UNDERFLOW) 19261b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); 1927f5860992SSakthivel K if (unlikely(!t || !t->lldd_task || !t->dev)) 1928f5860992SSakthivel K return; 1929f5860992SSakthivel K ts = &t->task_status; 19307370672dSpeter chang 19311b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 19321b5d2793SJoe Perches "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t); 19337370672dSpeter chang 1934cb269c26SAnand Kumar Santhanam /* Print sas address of IO failed device */ 1935cb269c26SAnand Kumar Santhanam if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1936cb269c26SAnand Kumar Santhanam (status != IO_UNDERFLOW)) 19371b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n", 19381b5d2793SJoe Perches SAS_ADDR(t->dev->sas_addr)); 1939cb269c26SAnand Kumar Santhanam 1940f5860992SSakthivel K switch (status) { 1941f5860992SSakthivel K case IO_SUCCESS: 19421b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n", 19431b5d2793SJoe Perches param); 1944f5860992SSakthivel K if (param == 0) { 1945f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1946d377f415SBart Van Assche ts->stat = SAS_SAM_STAT_GOOD; 1947f5860992SSakthivel K } else { 1948f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1949f5860992SSakthivel K ts->stat = SAS_PROTO_RESPONSE; 1950f5860992SSakthivel K ts->residual = param; 1951f5860992SSakthivel K iu = &psspPayload->ssp_resp_iu; 1952f5860992SSakthivel K sas_ssp_task_response(pm8001_ha->dev, t, iu); 1953f5860992SSakthivel K } 1954f5860992SSakthivel K if (pm8001_dev) 19554a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 1956f5860992SSakthivel K break; 1957f5860992SSakthivel K case IO_ABORTED: 19581b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 1959f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1960f5860992SSakthivel K ts->stat = SAS_ABORTED_TASK; 19614a2efd4bSViswas G if (pm8001_dev) 19624a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 1963f5860992SSakthivel K break; 1964f5860992SSakthivel K case IO_UNDERFLOW: 1965f5860992SSakthivel K /* SSP Completion with error */ 19661b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n", 19671b5d2793SJoe Perches param); 1968f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1969f5860992SSakthivel K ts->stat = SAS_DATA_UNDERRUN; 1970f5860992SSakthivel K ts->residual = param; 1971f5860992SSakthivel K if (pm8001_dev) 19724a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 1973f5860992SSakthivel K break; 1974f5860992SSakthivel K case IO_NO_DEVICE: 19751b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 1976f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 1977f5860992SSakthivel K ts->stat = SAS_PHY_DOWN; 19784a2efd4bSViswas G if (pm8001_dev) 19794a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 1980f5860992SSakthivel K break; 1981f5860992SSakthivel K case IO_XFER_ERROR_BREAK: 19821b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 1983f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1984f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1985f5860992SSakthivel K /* Force the midlayer to retry */ 1986f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 19874a2efd4bSViswas G if (pm8001_dev) 19884a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 1989f5860992SSakthivel K break; 1990f5860992SSakthivel K case IO_XFER_ERROR_PHY_NOT_READY: 19911b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 1992f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1993f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1994f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 19954a2efd4bSViswas G if (pm8001_dev) 19964a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 1997f5860992SSakthivel K break; 199827ecfa5eSViswas G case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME: 19991b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 20001b5d2793SJoe Perches "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"); 200127ecfa5eSViswas G ts->resp = SAS_TASK_COMPLETE; 200227ecfa5eSViswas G ts->stat = SAS_OPEN_REJECT; 200327ecfa5eSViswas G ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 20044a2efd4bSViswas G if (pm8001_dev) 20054a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 200627ecfa5eSViswas G break; 2007f5860992SSakthivel K case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 20081b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 20091b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2010f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2011f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2012f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_EPROTO; 20134a2efd4bSViswas G if (pm8001_dev) 20144a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2015f5860992SSakthivel K break; 2016f5860992SSakthivel K case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 20171b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 20181b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2019f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2020f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2021f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 20224a2efd4bSViswas G if (pm8001_dev) 20234a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2024f5860992SSakthivel K break; 2025f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BREAK: 20261b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2027f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2028f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2029f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 20304a2efd4bSViswas G if (pm8001_dev) 20314a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2032f5860992SSakthivel K break; 2033f5860992SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2034a6cb3d01SSakthivel K case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2035a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2036a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2037a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2038a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 20391b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2040f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2041f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2042f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2043f5860992SSakthivel K if (!t->uldd_task) 2044f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 2045f5860992SSakthivel K pm8001_dev, 2046f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2047f5860992SSakthivel K break; 2048f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 20491b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 20501b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2051f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2052f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2053f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_BAD_DEST; 20544a2efd4bSViswas G if (pm8001_dev) 20554a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2056f5860992SSakthivel K break; 2057f5860992SSakthivel K case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 20581b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 20591b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2060f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2061f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2062f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_CONN_RATE; 20634a2efd4bSViswas G if (pm8001_dev) 20644a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2065f5860992SSakthivel K break; 2066f5860992SSakthivel K case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 20671b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 20681b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2069f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2070f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2071f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 20724a2efd4bSViswas G if (pm8001_dev) 20734a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2074f5860992SSakthivel K break; 2075f5860992SSakthivel K case IO_XFER_ERROR_NAK_RECEIVED: 20761b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2077f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2078f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2079f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 20804a2efd4bSViswas G if (pm8001_dev) 20814a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2082f5860992SSakthivel K break; 2083f5860992SSakthivel K case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 20841b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2085f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2086f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 20874a2efd4bSViswas G if (pm8001_dev) 20884a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2089f5860992SSakthivel K break; 2090f5860992SSakthivel K case IO_XFER_ERROR_DMA: 20911b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2092f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2093f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 20944a2efd4bSViswas G if (pm8001_dev) 20954a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2096f5860992SSakthivel K break; 2097f5860992SSakthivel K case IO_XFER_OPEN_RETRY_TIMEOUT: 20981b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2099f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2100f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2101f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 21024a2efd4bSViswas G if (pm8001_dev) 21034a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2104f5860992SSakthivel K break; 2105f5860992SSakthivel K case IO_XFER_ERROR_OFFSET_MISMATCH: 21061b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2107f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2108f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 21094a2efd4bSViswas G if (pm8001_dev) 21104a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2111f5860992SSakthivel K break; 2112f5860992SSakthivel K case IO_PORT_IN_RESET: 21131b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2114f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2115f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 21164a2efd4bSViswas G if (pm8001_dev) 21174a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2118f5860992SSakthivel K break; 2119f5860992SSakthivel K case IO_DS_NON_OPERATIONAL: 21201b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2121f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2122f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2123f5860992SSakthivel K if (!t->uldd_task) 2124f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 2125f5860992SSakthivel K pm8001_dev, 2126f5860992SSakthivel K IO_DS_NON_OPERATIONAL); 2127f5860992SSakthivel K break; 2128f5860992SSakthivel K case IO_DS_IN_RECOVERY: 21291b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2130f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2131f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 21324a2efd4bSViswas G if (pm8001_dev) 21334a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2134f5860992SSakthivel K break; 2135f5860992SSakthivel K case IO_TM_TAG_NOT_FOUND: 21361b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n"); 2137f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2138f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 21394a2efd4bSViswas G if (pm8001_dev) 21404a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2141f5860992SSakthivel K break; 2142f5860992SSakthivel K case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 21431b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"); 2144f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2145f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 21464a2efd4bSViswas G if (pm8001_dev) 21474a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2148f5860992SSakthivel K break; 2149f5860992SSakthivel K case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 21501b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 21511b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2152f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2153f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2154f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 21554a2efd4bSViswas G if (pm8001_dev) 21564a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2157f5860992SSakthivel K break; 2158f5860992SSakthivel K default: 21591b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 2160f5860992SSakthivel K /* not allowed case. Therefore, return failed status */ 2161f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2162f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 21634a2efd4bSViswas G if (pm8001_dev) 21644a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2165f5860992SSakthivel K break; 2166f5860992SSakthivel K } 21671b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ", 21681b5d2793SJoe Perches psspPayload->ssp_resp_iu.status); 2169f5860992SSakthivel K spin_lock_irqsave(&t->task_state_lock, flags); 2170f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2171f5860992SSakthivel K t->task_state_flags |= SAS_TASK_STATE_DONE; 2172f5860992SSakthivel K if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2173f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 21741b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 21751b5d2793SJoe Perches "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 21761b5d2793SJoe Perches t, status, ts->resp, ts->stat); 2177304fe11bSDamien Le Moal pm8001_ccb_task_free(pm8001_ha, ccb); 2178869ddbdcSViswas G if (t->slow_task) 2179869ddbdcSViswas G complete(&t->slow_task->completion); 2180f5860992SSakthivel K } else { 2181f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 2182304fe11bSDamien Le Moal pm8001_ccb_task_free_done(pm8001_ha, ccb); 2183f5860992SSakthivel K } 2184f5860992SSakthivel K } 2185f5860992SSakthivel K 2186f5860992SSakthivel K /*See the comments for mpi_ssp_completion */ 2187f5860992SSakthivel K static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 2188f5860992SSakthivel K { 2189f5860992SSakthivel K struct sas_task *t; 2190f5860992SSakthivel K unsigned long flags; 2191f5860992SSakthivel K struct task_status_struct *ts; 2192f5860992SSakthivel K struct pm8001_ccb_info *ccb; 2193f5860992SSakthivel K struct pm8001_device *pm8001_dev; 2194f5860992SSakthivel K struct ssp_event_resp *psspPayload = 2195f5860992SSakthivel K (struct ssp_event_resp *)(piomb + 4); 2196f5860992SSakthivel K u32 event = le32_to_cpu(psspPayload->event); 2197f5860992SSakthivel K u32 tag = le32_to_cpu(psspPayload->tag); 2198f5860992SSakthivel K u32 port_id = le32_to_cpu(psspPayload->port_id); 2199f5860992SSakthivel K 2200f5860992SSakthivel K ccb = &pm8001_ha->ccb_info[tag]; 2201f5860992SSakthivel K t = ccb->task; 2202f5860992SSakthivel K pm8001_dev = ccb->device; 2203f5860992SSakthivel K if (event) 22041b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); 2205f5860992SSakthivel K if (unlikely(!t || !t->lldd_task || !t->dev)) 2206f5860992SSakthivel K return; 2207f5860992SSakthivel K ts = &t->task_status; 22081b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 22091b5d2793SJoe Perches port_id, tag, event); 2210f5860992SSakthivel K switch (event) { 2211f5860992SSakthivel K case IO_OVERFLOW: 22121b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2213f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2214f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2215f5860992SSakthivel K ts->residual = 0; 2216f5860992SSakthivel K if (pm8001_dev) 22174a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2218f5860992SSakthivel K break; 2219f5860992SSakthivel K case IO_XFER_ERROR_BREAK: 22201b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2221f5860992SSakthivel K pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 2222f5860992SSakthivel K return; 2223f5860992SSakthivel K case IO_XFER_ERROR_PHY_NOT_READY: 22241b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2225f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2226f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2227f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2228f5860992SSakthivel K break; 2229f5860992SSakthivel K case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 22301b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 22311b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2232f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2233f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2234f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_EPROTO; 2235f5860992SSakthivel K break; 2236f5860992SSakthivel K case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 22371b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 22381b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2239f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2240f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2241f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2242f5860992SSakthivel K break; 2243f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BREAK: 22441b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2245f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2246f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2247f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2248f5860992SSakthivel K break; 2249f5860992SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2250a6cb3d01SSakthivel K case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2251a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2252a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2253a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2254a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 22551b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2256f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2257f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2258f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2259f5860992SSakthivel K if (!t->uldd_task) 2260f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 2261f5860992SSakthivel K pm8001_dev, 2262f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2263f5860992SSakthivel K break; 2264f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 22651b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 22661b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2267f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2268f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2269f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2270f5860992SSakthivel K break; 2271f5860992SSakthivel K case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 22721b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 22731b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2274f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2275f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2276f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2277f5860992SSakthivel K break; 2278f5860992SSakthivel K case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 22791b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 22801b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2281f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2282f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2283f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2284f5860992SSakthivel K break; 2285f5860992SSakthivel K case IO_XFER_ERROR_NAK_RECEIVED: 22861b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2287f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2288f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2289f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2290f5860992SSakthivel K break; 2291f5860992SSakthivel K case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 22921b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2293f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2294f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 2295f5860992SSakthivel K break; 2296f5860992SSakthivel K case IO_XFER_OPEN_RETRY_TIMEOUT: 22971b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2298f5860992SSakthivel K pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2299f5860992SSakthivel K return; 2300f5860992SSakthivel K case IO_XFER_ERROR_UNEXPECTED_PHASE: 23011b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2302f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2303f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2304f5860992SSakthivel K break; 2305f5860992SSakthivel K case IO_XFER_ERROR_XFER_RDY_OVERRUN: 23061b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2307f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2308f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2309f5860992SSakthivel K break; 2310f5860992SSakthivel K case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 23111b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 23121b5d2793SJoe Perches "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2313f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2314f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2315f5860992SSakthivel K break; 2316f5860992SSakthivel K case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 23171b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 23181b5d2793SJoe Perches "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"); 2319f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2320f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2321f5860992SSakthivel K break; 2322f5860992SSakthivel K case IO_XFER_ERROR_OFFSET_MISMATCH: 23231b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2324f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2325f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2326f5860992SSakthivel K break; 2327f5860992SSakthivel K case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 23281b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 23291b5d2793SJoe Perches "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2330f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2331f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2332f5860992SSakthivel K break; 2333a6cb3d01SSakthivel K case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 23341b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IOERR, 23351b5d2793SJoe Perches "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2336a6cb3d01SSakthivel K /* TBC: used default set values */ 2337a6cb3d01SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2338a6cb3d01SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2339a6cb3d01SSakthivel K break; 2340f5860992SSakthivel K case IO_XFER_CMD_FRAME_ISSUED: 23411b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2342f5860992SSakthivel K return; 2343f5860992SSakthivel K default: 23441b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); 2345f5860992SSakthivel K /* not allowed case. Therefore, return failed status */ 2346f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2347f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2348f5860992SSakthivel K break; 2349f5860992SSakthivel K } 2350f5860992SSakthivel K spin_lock_irqsave(&t->task_state_lock, flags); 2351f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2352f5860992SSakthivel K t->task_state_flags |= SAS_TASK_STATE_DONE; 2353f5860992SSakthivel K if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2354f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 23551b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 23561b5d2793SJoe Perches "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 23571b5d2793SJoe Perches t, event, ts->resp, ts->stat); 2358304fe11bSDamien Le Moal pm8001_ccb_task_free(pm8001_ha, ccb); 2359f5860992SSakthivel K } else { 2360f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 2361304fe11bSDamien Le Moal pm8001_ccb_task_free_done(pm8001_ha, ccb); 2362f5860992SSakthivel K } 2363f5860992SSakthivel K } 2364f5860992SSakthivel K 2365f5860992SSakthivel K /*See the comments for mpi_ssp_completion */ 2366f5860992SSakthivel K static void 2367b27a4053SAjish Koshy mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, 2368b27a4053SAjish Koshy struct outbound_queue_table *circularQ, void *piomb) 2369f5860992SSakthivel K { 2370f5860992SSakthivel K struct sas_task *t; 2371f5860992SSakthivel K struct pm8001_ccb_info *ccb; 2372f5860992SSakthivel K u32 param; 2373f5860992SSakthivel K u32 status; 2374f5860992SSakthivel K u32 tag; 2375cb269c26SAnand Kumar Santhanam int i, j; 2376cb269c26SAnand Kumar Santhanam u8 sata_addr_low[4]; 2377cb269c26SAnand Kumar Santhanam u32 temp_sata_addr_low, temp_sata_addr_hi; 2378cb269c26SAnand Kumar Santhanam u8 sata_addr_hi[4]; 2379f5860992SSakthivel K struct sata_completion_resp *psataPayload; 2380f5860992SSakthivel K struct task_status_struct *ts; 2381f5860992SSakthivel K struct ata_task_resp *resp ; 2382f5860992SSakthivel K u32 *sata_resp; 2383f5860992SSakthivel K struct pm8001_device *pm8001_dev; 2384c6b9ef57SSakthivel K unsigned long flags; 2385f5860992SSakthivel K 2386f5860992SSakthivel K psataPayload = (struct sata_completion_resp *)(piomb + 4); 2387f5860992SSakthivel K status = le32_to_cpu(psataPayload->status); 238860de1a67SIgor Pylypiv param = le32_to_cpu(psataPayload->param); 2389f5860992SSakthivel K tag = le32_to_cpu(psataPayload->tag); 2390f5860992SSakthivel K 2391f5860992SSakthivel K ccb = &pm8001_ha->ccb_info[tag]; 2392f5860992SSakthivel K t = ccb->task; 2393f5860992SSakthivel K pm8001_dev = ccb->device; 2394c6b9ef57SSakthivel K 2395c6b9ef57SSakthivel K if (t) { 2396c6b9ef57SSakthivel K if (t->dev && (t->dev->lldd_dev)) 2397c6b9ef57SSakthivel K pm8001_dev = t->dev->lldd_dev; 2398c6b9ef57SSakthivel K } else { 23991b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "task null\n"); 2400c6b9ef57SSakthivel K return; 2401c6b9ef57SSakthivel K } 2402c6b9ef57SSakthivel K 2403c6b9ef57SSakthivel K if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 2404c6b9ef57SSakthivel K && unlikely(!t || !t->lldd_task || !t->dev)) { 24051b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2406c6b9ef57SSakthivel K return; 2407c6b9ef57SSakthivel K } 2408c6b9ef57SSakthivel K 2409c6b9ef57SSakthivel K ts = &t->task_status; 24107370672dSpeter chang 24114f608fbcSVishakha Channapattan if (status != IO_SUCCESS) { 24124f608fbcSVishakha Channapattan pm8001_dbg(pm8001_ha, FAIL, 24134f608fbcSVishakha Channapattan "IO failed device_id %u status 0x%x tag %d\n", 24144f608fbcSVishakha Channapattan pm8001_dev->device_id, status, tag); 24154f608fbcSVishakha Channapattan } 24167370672dSpeter chang 2417cb269c26SAnand Kumar Santhanam /* Print sas address of IO failed device */ 2418cb269c26SAnand Kumar Santhanam if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 2419cb269c26SAnand Kumar Santhanam (status != IO_UNDERFLOW)) { 2420cb269c26SAnand Kumar Santhanam if (!((t->dev->parent) && 2421924a3541SJohn Garry (dev_is_expander(t->dev->parent->dev_type)))) { 2422cb269c26SAnand Kumar Santhanam for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++) 2423cb269c26SAnand Kumar Santhanam sata_addr_low[i] = pm8001_ha->sas_addr[j]; 2424cb269c26SAnand Kumar Santhanam for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++) 2425cb269c26SAnand Kumar Santhanam sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 2426cb269c26SAnand Kumar Santhanam memcpy(&temp_sata_addr_low, sata_addr_low, 2427cb269c26SAnand Kumar Santhanam sizeof(sata_addr_low)); 2428cb269c26SAnand Kumar Santhanam memcpy(&temp_sata_addr_hi, sata_addr_hi, 2429cb269c26SAnand Kumar Santhanam sizeof(sata_addr_hi)); 2430cb269c26SAnand Kumar Santhanam temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 2431cb269c26SAnand Kumar Santhanam |((temp_sata_addr_hi << 8) & 2432cb269c26SAnand Kumar Santhanam 0xff0000) | 2433cb269c26SAnand Kumar Santhanam ((temp_sata_addr_hi >> 8) 2434cb269c26SAnand Kumar Santhanam & 0xff00) | 2435cb269c26SAnand Kumar Santhanam ((temp_sata_addr_hi << 24) & 2436cb269c26SAnand Kumar Santhanam 0xff000000)); 2437cb269c26SAnand Kumar Santhanam temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 2438cb269c26SAnand Kumar Santhanam & 0xff) | 2439cb269c26SAnand Kumar Santhanam ((temp_sata_addr_low << 8) 2440cb269c26SAnand Kumar Santhanam & 0xff0000) | 2441cb269c26SAnand Kumar Santhanam ((temp_sata_addr_low >> 8) 2442cb269c26SAnand Kumar Santhanam & 0xff00) | 2443cb269c26SAnand Kumar Santhanam ((temp_sata_addr_low << 24) 2444cb269c26SAnand Kumar Santhanam & 0xff000000)) + 2445cb269c26SAnand Kumar Santhanam pm8001_dev->attached_phy + 2446cb269c26SAnand Kumar Santhanam 0x10); 24471b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 24481b5d2793SJoe Perches "SAS Address of IO Failure Drive:%08x%08x\n", 24491b5d2793SJoe Perches temp_sata_addr_hi, 24501b5d2793SJoe Perches temp_sata_addr_low); 2451f5860992SSakthivel K 2452cb269c26SAnand Kumar Santhanam } else { 24531b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 24541b5d2793SJoe Perches "SAS Address of IO Failure Drive:%016llx\n", 24551b5d2793SJoe Perches SAS_ADDR(t->dev->sas_addr)); 2456cb269c26SAnand Kumar Santhanam } 2457cb269c26SAnand Kumar Santhanam } 2458f5860992SSakthivel K switch (status) { 2459f5860992SSakthivel K case IO_SUCCESS: 24601b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 2461f5860992SSakthivel K if (param == 0) { 2462f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2463d377f415SBart Van Assche ts->stat = SAS_SAM_STAT_GOOD; 2464c6b9ef57SSakthivel K /* check if response is for SEND READ LOG */ 2465c6b9ef57SSakthivel K if (pm8001_dev && 2466c6b9ef57SSakthivel K (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 2467c6b9ef57SSakthivel K pm80xx_send_abort_all(pm8001_ha, pm8001_dev); 2468c6b9ef57SSakthivel K /* Free the tag */ 2469c6b9ef57SSakthivel K pm8001_tag_free(pm8001_ha, tag); 2470c6b9ef57SSakthivel K sas_free_task(t); 2471c6b9ef57SSakthivel K return; 2472c6b9ef57SSakthivel K } 2473f5860992SSakthivel K } else { 2474f5860992SSakthivel K u8 len; 2475f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2476f5860992SSakthivel K ts->stat = SAS_PROTO_RESPONSE; 2477f5860992SSakthivel K ts->residual = param; 24781b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 24791b5d2793SJoe Perches "SAS_PROTO_RESPONSE len = %d\n", 24801b5d2793SJoe Perches param); 2481f5860992SSakthivel K sata_resp = &psataPayload->sata_resp[0]; 2482f5860992SSakthivel K resp = (struct ata_task_resp *)ts->buf; 2483f5860992SSakthivel K if (t->ata_task.dma_xfer == 0 && 2484f73bdebdSChristoph Hellwig t->data_dir == DMA_FROM_DEVICE) { 2485f5860992SSakthivel K len = sizeof(struct pio_setup_fis); 24861b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 24871b5d2793SJoe Perches "PIO read len = %d\n", len); 24881d6736c3SDamien Le Moal } else if (t->ata_task.use_ncq && 24891d6736c3SDamien Le Moal t->data_dir != DMA_NONE) { 2490f5860992SSakthivel K len = sizeof(struct set_dev_bits_fis); 24911b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n", 24921b5d2793SJoe Perches len); 2493f5860992SSakthivel K } else { 2494f5860992SSakthivel K len = sizeof(struct dev_to_host_fis); 24951b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "other len = %d\n", 24961b5d2793SJoe Perches len); 2497f5860992SSakthivel K } 2498f5860992SSakthivel K if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2499f5860992SSakthivel K resp->frame_len = len; 2500f5860992SSakthivel K memcpy(&resp->ending_fis[0], sata_resp, len); 2501f5860992SSakthivel K ts->buf_valid_size = sizeof(*resp); 2502f5860992SSakthivel K } else 25031b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 25041b5d2793SJoe Perches "response too large\n"); 2505f5860992SSakthivel K } 2506f5860992SSakthivel K if (pm8001_dev) 25074a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2508f5860992SSakthivel K break; 2509f5860992SSakthivel K case IO_ABORTED: 25101b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); 2511f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2512f5860992SSakthivel K ts->stat = SAS_ABORTED_TASK; 2513f5860992SSakthivel K if (pm8001_dev) 25144a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2515f5860992SSakthivel K break; 2516f5860992SSakthivel K /* following cases are to do cases */ 2517f5860992SSakthivel K case IO_UNDERFLOW: 2518f5860992SSakthivel K /* SATA Completion with error */ 25191b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param); 2520f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2521f5860992SSakthivel K ts->stat = SAS_DATA_UNDERRUN; 2522f5860992SSakthivel K ts->residual = param; 2523f5860992SSakthivel K if (pm8001_dev) 25244a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2525f5860992SSakthivel K break; 2526f5860992SSakthivel K case IO_NO_DEVICE: 25271b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 2528f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2529f5860992SSakthivel K ts->stat = SAS_PHY_DOWN; 25304a2efd4bSViswas G if (pm8001_dev) 25314a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2532f5860992SSakthivel K break; 2533f5860992SSakthivel K case IO_XFER_ERROR_BREAK: 25341b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2535f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2536f5860992SSakthivel K ts->stat = SAS_INTERRUPTED; 25374a2efd4bSViswas G if (pm8001_dev) 25384a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2539f5860992SSakthivel K break; 2540f5860992SSakthivel K case IO_XFER_ERROR_PHY_NOT_READY: 25411b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2542f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2543f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2544f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 25454a2efd4bSViswas G if (pm8001_dev) 25464a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2547f5860992SSakthivel K break; 2548f5860992SSakthivel K case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 25491b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 25501b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2551f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2552f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2553f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_EPROTO; 25544a2efd4bSViswas G if (pm8001_dev) 25554a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2556f5860992SSakthivel K break; 2557f5860992SSakthivel K case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 25581b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 25591b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2560f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2561f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2562f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 25634a2efd4bSViswas G if (pm8001_dev) 25644a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2565f5860992SSakthivel K break; 2566f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BREAK: 25671b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2568f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2569f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2570f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 25714a2efd4bSViswas G if (pm8001_dev) 25724a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2573f5860992SSakthivel K break; 2574f5860992SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2575a6cb3d01SSakthivel K case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2576a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2577a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2578a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2579a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 25801b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2581f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2582f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2583f5860992SSakthivel K if (!t->uldd_task) { 2584f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 2585f5860992SSakthivel K pm8001_dev, 2586f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2587f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2588f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 2589b27a4053SAjish Koshy spin_unlock_irqrestore(&circularQ->oq_lock, 2590b27a4053SAjish Koshy circularQ->lock_flags); 2591304fe11bSDamien Le Moal pm8001_ccb_task_free_done(pm8001_ha, ccb); 2592b27a4053SAjish Koshy spin_lock_irqsave(&circularQ->oq_lock, 2593b27a4053SAjish Koshy circularQ->lock_flags); 2594f5860992SSakthivel K return; 2595f5860992SSakthivel K } 2596f5860992SSakthivel K break; 2597f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 25981b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 25991b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2600f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2601f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2602f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2603f5860992SSakthivel K if (!t->uldd_task) { 2604f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 2605f5860992SSakthivel K pm8001_dev, 2606f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2607f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2608f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 2609b27a4053SAjish Koshy spin_unlock_irqrestore(&circularQ->oq_lock, 2610b27a4053SAjish Koshy circularQ->lock_flags); 2611304fe11bSDamien Le Moal pm8001_ccb_task_free_done(pm8001_ha, ccb); 2612b27a4053SAjish Koshy spin_lock_irqsave(&circularQ->oq_lock, 2613b27a4053SAjish Koshy circularQ->lock_flags); 2614f5860992SSakthivel K return; 2615f5860992SSakthivel K } 2616f5860992SSakthivel K break; 2617f5860992SSakthivel K case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 26181b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 26191b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2620f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2621f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2622f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_CONN_RATE; 26234a2efd4bSViswas G if (pm8001_dev) 26244a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2625f5860992SSakthivel K break; 2626f5860992SSakthivel K case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 26271b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 26281b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"); 2629f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2630f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2631f5860992SSakthivel K if (!t->uldd_task) { 2632f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 2633f5860992SSakthivel K pm8001_dev, 2634f5860992SSakthivel K IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2635f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2636f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 2637b27a4053SAjish Koshy spin_unlock_irqrestore(&circularQ->oq_lock, 2638b27a4053SAjish Koshy circularQ->lock_flags); 2639304fe11bSDamien Le Moal pm8001_ccb_task_free_done(pm8001_ha, ccb); 2640b27a4053SAjish Koshy spin_lock_irqsave(&circularQ->oq_lock, 2641b27a4053SAjish Koshy circularQ->lock_flags); 2642f5860992SSakthivel K return; 2643f5860992SSakthivel K } 2644f5860992SSakthivel K break; 2645f5860992SSakthivel K case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 26461b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 26471b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2648f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2649f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2650f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 26514a2efd4bSViswas G if (pm8001_dev) 26524a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2653f5860992SSakthivel K break; 2654f5860992SSakthivel K case IO_XFER_ERROR_NAK_RECEIVED: 26551b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2656f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2657f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 26584a2efd4bSViswas G if (pm8001_dev) 26594a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2660f5860992SSakthivel K break; 2661f5860992SSakthivel K case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 26621b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); 2663f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2664f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 26654a2efd4bSViswas G if (pm8001_dev) 26664a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2667f5860992SSakthivel K break; 2668f5860992SSakthivel K case IO_XFER_ERROR_DMA: 26691b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); 2670f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2671f5860992SSakthivel K ts->stat = SAS_ABORTED_TASK; 26724a2efd4bSViswas G if (pm8001_dev) 26734a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2674f5860992SSakthivel K break; 2675f5860992SSakthivel K case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 26761b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"); 2677f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2678f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 26794a2efd4bSViswas G if (pm8001_dev) 26804a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2681f5860992SSakthivel K break; 2682f5860992SSakthivel K case IO_XFER_ERROR_REJECTED_NCQ_MODE: 26831b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2684f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2685f5860992SSakthivel K ts->stat = SAS_DATA_UNDERRUN; 26864a2efd4bSViswas G if (pm8001_dev) 26874a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2688f5860992SSakthivel K break; 2689f5860992SSakthivel K case IO_XFER_OPEN_RETRY_TIMEOUT: 26901b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2691f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2692f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 26934a2efd4bSViswas G if (pm8001_dev) 26944a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2695f5860992SSakthivel K break; 2696f5860992SSakthivel K case IO_PORT_IN_RESET: 26971b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 2698f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2699f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 27004a2efd4bSViswas G if (pm8001_dev) 27014a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2702f5860992SSakthivel K break; 2703f5860992SSakthivel K case IO_DS_NON_OPERATIONAL: 27041b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 2705f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2706f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2707f5860992SSakthivel K if (!t->uldd_task) { 2708f5860992SSakthivel K pm8001_handle_event(pm8001_ha, pm8001_dev, 2709f5860992SSakthivel K IO_DS_NON_OPERATIONAL); 2710f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2711f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 2712b27a4053SAjish Koshy spin_unlock_irqrestore(&circularQ->oq_lock, 2713b27a4053SAjish Koshy circularQ->lock_flags); 2714304fe11bSDamien Le Moal pm8001_ccb_task_free_done(pm8001_ha, ccb); 2715b27a4053SAjish Koshy spin_lock_irqsave(&circularQ->oq_lock, 2716b27a4053SAjish Koshy circularQ->lock_flags); 2717f5860992SSakthivel K return; 2718f5860992SSakthivel K } 2719f5860992SSakthivel K break; 2720f5860992SSakthivel K case IO_DS_IN_RECOVERY: 27211b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 2722f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2723f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 27244a2efd4bSViswas G if (pm8001_dev) 27254a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2726f5860992SSakthivel K break; 2727f5860992SSakthivel K case IO_DS_IN_ERROR: 27281b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n"); 2729f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2730f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2731f5860992SSakthivel K if (!t->uldd_task) { 2732f5860992SSakthivel K pm8001_handle_event(pm8001_ha, pm8001_dev, 2733f5860992SSakthivel K IO_DS_IN_ERROR); 2734f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2735f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 2736b27a4053SAjish Koshy spin_unlock_irqrestore(&circularQ->oq_lock, 2737b27a4053SAjish Koshy circularQ->lock_flags); 2738304fe11bSDamien Le Moal pm8001_ccb_task_free_done(pm8001_ha, ccb); 2739b27a4053SAjish Koshy spin_lock_irqsave(&circularQ->oq_lock, 2740b27a4053SAjish Koshy circularQ->lock_flags); 2741f5860992SSakthivel K return; 2742f5860992SSakthivel K } 2743f5860992SSakthivel K break; 2744f5860992SSakthivel K case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 27451b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 27461b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 2747f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2748f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2749f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 27504a2efd4bSViswas G if (pm8001_dev) 27514a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 275250acde8eSJohannes Thumshirn break; 2753f5860992SSakthivel K default: 27544f608fbcSVishakha Channapattan pm8001_dbg(pm8001_ha, DEVIO, 27554f608fbcSVishakha Channapattan "Unknown status device_id %u status 0x%x tag %d\n", 27564f608fbcSVishakha Channapattan pm8001_dev->device_id, status, tag); 2757f5860992SSakthivel K /* not allowed case. Therefore, return failed status */ 2758f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2759f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 27604a2efd4bSViswas G if (pm8001_dev) 27614a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 2762f5860992SSakthivel K break; 2763f5860992SSakthivel K } 2764f5860992SSakthivel K spin_lock_irqsave(&t->task_state_lock, flags); 2765f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2766f5860992SSakthivel K t->task_state_flags |= SAS_TASK_STATE_DONE; 2767f5860992SSakthivel K if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2768f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 27691b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 27701b5d2793SJoe Perches "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", 27711b5d2793SJoe Perches t, status, ts->resp, ts->stat); 2772304fe11bSDamien Le Moal pm8001_ccb_task_free(pm8001_ha, ccb); 2773ce21c63eSpeter chang if (t->slow_task) 2774ce21c63eSpeter chang complete(&t->slow_task->completion); 27752b01d816SSuresh Thiagarajan } else { 2776f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 2777b27a4053SAjish Koshy spin_unlock_irqrestore(&circularQ->oq_lock, 2778b27a4053SAjish Koshy circularQ->lock_flags); 2779304fe11bSDamien Le Moal pm8001_ccb_task_free_done(pm8001_ha, ccb); 2780b27a4053SAjish Koshy spin_lock_irqsave(&circularQ->oq_lock, 2781b27a4053SAjish Koshy circularQ->lock_flags); 2782f5860992SSakthivel K } 2783f5860992SSakthivel K } 2784f5860992SSakthivel K 2785f5860992SSakthivel K /*See the comments for mpi_ssp_completion */ 2786b27a4053SAjish Koshy static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, 2787b27a4053SAjish Koshy struct outbound_queue_table *circularQ, void *piomb) 2788f5860992SSakthivel K { 2789f5860992SSakthivel K struct sas_task *t; 2790f5860992SSakthivel K struct task_status_struct *ts; 2791f5860992SSakthivel K struct pm8001_ccb_info *ccb; 2792f5860992SSakthivel K struct pm8001_device *pm8001_dev; 2793f5860992SSakthivel K struct sata_event_resp *psataPayload = 2794f5860992SSakthivel K (struct sata_event_resp *)(piomb + 4); 2795f5860992SSakthivel K u32 event = le32_to_cpu(psataPayload->event); 2796f5860992SSakthivel K u32 tag = le32_to_cpu(psataPayload->tag); 2797f5860992SSakthivel K u32 port_id = le32_to_cpu(psataPayload->port_id); 2798c6b9ef57SSakthivel K u32 dev_id = le32_to_cpu(psataPayload->device_id); 2799f5860992SSakthivel K 2800f5860992SSakthivel K if (event) 28011b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); 2802c6b9ef57SSakthivel K 2803c6b9ef57SSakthivel K /* Check if this is NCQ error */ 2804c6b9ef57SSakthivel K if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2805c6b9ef57SSakthivel K /* find device using device id */ 2806c6b9ef57SSakthivel K pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2807c6b9ef57SSakthivel K /* send read log extension */ 2808c6b9ef57SSakthivel K if (pm8001_dev) 2809c6b9ef57SSakthivel K pm80xx_send_read_log(pm8001_ha, pm8001_dev); 2810f5860992SSakthivel K return; 2811c6b9ef57SSakthivel K } 2812c6b9ef57SSakthivel K 281360de1a67SIgor Pylypiv ccb = &pm8001_ha->ccb_info[tag]; 281460de1a67SIgor Pylypiv t = ccb->task; 281560de1a67SIgor Pylypiv pm8001_dev = ccb->device; 281660de1a67SIgor Pylypiv 2817c6b9ef57SSakthivel K if (unlikely(!t || !t->lldd_task || !t->dev)) { 28181b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); 2819c6b9ef57SSakthivel K return; 2820c6b9ef57SSakthivel K } 2821c6b9ef57SSakthivel K 2822f5860992SSakthivel K ts = &t->task_status; 28231b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", 28241b5d2793SJoe Perches port_id, tag, event); 2825f5860992SSakthivel K switch (event) { 2826f5860992SSakthivel K case IO_OVERFLOW: 28271b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 2828f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2829f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2830f5860992SSakthivel K ts->residual = 0; 2831f5860992SSakthivel K break; 2832f5860992SSakthivel K case IO_XFER_ERROR_BREAK: 28331b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 2834f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2835f5860992SSakthivel K ts->stat = SAS_INTERRUPTED; 2836f5860992SSakthivel K break; 2837f5860992SSakthivel K case IO_XFER_ERROR_PHY_NOT_READY: 28381b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 2839f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2840f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2841f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2842f5860992SSakthivel K break; 2843f5860992SSakthivel K case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 28441b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 28451b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 2846f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2847f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2848f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_EPROTO; 2849f5860992SSakthivel K break; 2850f5860992SSakthivel K case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 28511b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 28521b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 2853f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2854f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2855f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2856f5860992SSakthivel K break; 2857f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BREAK: 28581b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 2859f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2860f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2861f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2862f5860992SSakthivel K break; 2863f5860992SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2864a6cb3d01SSakthivel K case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2865a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2866a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2867a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2868a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 28691b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 28701b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 2871f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2872f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2873f5860992SSakthivel K if (!t->uldd_task) { 2874f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 2875f5860992SSakthivel K pm8001_dev, 2876f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2877f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2878f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 2879f5860992SSakthivel K return; 2880f5860992SSakthivel K } 2881f5860992SSakthivel K break; 2882f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 28831b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 28841b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 2885f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2886f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2887f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2888f5860992SSakthivel K break; 2889f5860992SSakthivel K case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 28901b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 28911b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 2892f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2893f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2894f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2895f5860992SSakthivel K break; 2896f5860992SSakthivel K case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 28971b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 28981b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 2899f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2900f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2901f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2902f5860992SSakthivel K break; 2903f5860992SSakthivel K case IO_XFER_ERROR_NAK_RECEIVED: 29041b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); 2905f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2906f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 2907f5860992SSakthivel K break; 2908f5860992SSakthivel K case IO_XFER_ERROR_PEER_ABORTED: 29091b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n"); 2910f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2911f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 2912f5860992SSakthivel K break; 2913f5860992SSakthivel K case IO_XFER_ERROR_REJECTED_NCQ_MODE: 29141b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); 2915f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2916f5860992SSakthivel K ts->stat = SAS_DATA_UNDERRUN; 2917f5860992SSakthivel K break; 2918f5860992SSakthivel K case IO_XFER_OPEN_RETRY_TIMEOUT: 29191b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 2920f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2921f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2922f5860992SSakthivel K break; 2923f5860992SSakthivel K case IO_XFER_ERROR_UNEXPECTED_PHASE: 29241b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); 2925f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2926f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2927f5860992SSakthivel K break; 2928f5860992SSakthivel K case IO_XFER_ERROR_XFER_RDY_OVERRUN: 29291b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); 2930f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2931f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2932f5860992SSakthivel K break; 2933f5860992SSakthivel K case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 29341b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 29351b5d2793SJoe Perches "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"); 2936f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2937f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2938f5860992SSakthivel K break; 2939f5860992SSakthivel K case IO_XFER_ERROR_OFFSET_MISMATCH: 29401b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); 2941f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2942f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2943f5860992SSakthivel K break; 2944f5860992SSakthivel K case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 29451b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 29461b5d2793SJoe Perches "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"); 2947f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2948f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2949f5860992SSakthivel K break; 2950f5860992SSakthivel K case IO_XFER_CMD_FRAME_ISSUED: 29511b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); 2952f5860992SSakthivel K break; 2953f5860992SSakthivel K case IO_XFER_PIO_SETUP_ERROR: 29541b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n"); 2955f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2956f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2957f5860992SSakthivel K break; 2958a6cb3d01SSakthivel K case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 29591b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 29601b5d2793SJoe Perches "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"); 2961a6cb3d01SSakthivel K /* TBC: used default set values */ 2962a6cb3d01SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2963a6cb3d01SSakthivel K ts->stat = SAS_OPEN_TO; 2964a6cb3d01SSakthivel K break; 2965a6cb3d01SSakthivel K case IO_XFER_DMA_ACTIVATE_TIMEOUT: 29661b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n"); 2967a6cb3d01SSakthivel K /* TBC: used default set values */ 2968a6cb3d01SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2969a6cb3d01SSakthivel K ts->stat = SAS_OPEN_TO; 2970a6cb3d01SSakthivel K break; 2971f5860992SSakthivel K default: 29721b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event); 2973f5860992SSakthivel K /* not allowed case. Therefore, return failed status */ 2974f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2975f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2976f5860992SSakthivel K break; 2977f5860992SSakthivel K } 2978f5860992SSakthivel K } 2979f5860992SSakthivel K 2980f5860992SSakthivel K /*See the comments for mpi_ssp_completion */ 2981f5860992SSakthivel K static void 2982f5860992SSakthivel K mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2983f5860992SSakthivel K { 2984f5860992SSakthivel K u32 param, i; 2985f5860992SSakthivel K struct sas_task *t; 2986f5860992SSakthivel K struct pm8001_ccb_info *ccb; 2987f5860992SSakthivel K unsigned long flags; 2988f5860992SSakthivel K u32 status; 2989f5860992SSakthivel K u32 tag; 2990f5860992SSakthivel K struct smp_completion_resp *psmpPayload; 2991f5860992SSakthivel K struct task_status_struct *ts; 2992f5860992SSakthivel K struct pm8001_device *pm8001_dev; 2993f5860992SSakthivel K 2994f5860992SSakthivel K psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2995f5860992SSakthivel K status = le32_to_cpu(psmpPayload->status); 2996f5860992SSakthivel K tag = le32_to_cpu(psmpPayload->tag); 2997f5860992SSakthivel K 2998f5860992SSakthivel K ccb = &pm8001_ha->ccb_info[tag]; 2999f5860992SSakthivel K param = le32_to_cpu(psmpPayload->param); 3000f5860992SSakthivel K t = ccb->task; 3001f5860992SSakthivel K ts = &t->task_status; 3002f5860992SSakthivel K pm8001_dev = ccb->device; 3003f5860992SSakthivel K if (status) 30041b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); 3005f5860992SSakthivel K if (unlikely(!t || !t->lldd_task || !t->dev)) 3006f5860992SSakthivel K return; 3007f5860992SSakthivel K 30081b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status); 30097370672dSpeter chang 3010f5860992SSakthivel K switch (status) { 3011f5860992SSakthivel K 3012f5860992SSakthivel K case IO_SUCCESS: 30131b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); 3014f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3015d377f415SBart Van Assche ts->stat = SAS_SAM_STAT_GOOD; 3016f5860992SSakthivel K if (pm8001_dev) 30174a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 3018f5860992SSakthivel K if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 30192fe24343SJohn Garry struct scatterlist *sg_resp = &t->smp_task.smp_resp; 30202fe24343SJohn Garry u8 *payload; 30212fe24343SJohn Garry void *to; 30222fe24343SJohn Garry 30231b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 30241b5d2793SJoe Perches "DIRECT RESPONSE Length:%d\n", 30251b5d2793SJoe Perches param); 30262fe24343SJohn Garry to = kmap_atomic(sg_page(sg_resp)); 30272fe24343SJohn Garry payload = to + sg_resp->offset; 3028f5860992SSakthivel K for (i = 0; i < param; i++) { 30292fe24343SJohn Garry *(payload + i) = psmpPayload->_r_a[i]; 30301b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 3031f5860992SSakthivel K "SMP Byte%d DMA data 0x%x psmp 0x%x\n", 30322fe24343SJohn Garry i, *(payload + i), 30331b5d2793SJoe Perches psmpPayload->_r_a[i]); 3034f5860992SSakthivel K } 30352fe24343SJohn Garry kunmap_atomic(to); 3036f5860992SSakthivel K } 3037f5860992SSakthivel K break; 3038f5860992SSakthivel K case IO_ABORTED: 30391b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n"); 3040f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3041f5860992SSakthivel K ts->stat = SAS_ABORTED_TASK; 3042f5860992SSakthivel K if (pm8001_dev) 30434a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 3044f5860992SSakthivel K break; 3045f5860992SSakthivel K case IO_OVERFLOW: 30461b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); 3047f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3048f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 3049f5860992SSakthivel K ts->residual = 0; 3050f5860992SSakthivel K if (pm8001_dev) 30514a2efd4bSViswas G atomic_dec(&pm8001_dev->running_req); 3052f5860992SSakthivel K break; 3053f5860992SSakthivel K case IO_NO_DEVICE: 30541b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); 3055f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3056f5860992SSakthivel K ts->stat = SAS_PHY_DOWN; 3057f5860992SSakthivel K break; 3058f5860992SSakthivel K case IO_ERROR_HW_TIMEOUT: 30591b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n"); 3060f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3061d377f415SBart Van Assche ts->stat = SAS_SAM_STAT_BUSY; 3062f5860992SSakthivel K break; 3063f5860992SSakthivel K case IO_XFER_ERROR_BREAK: 30641b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); 3065f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3066d377f415SBart Van Assche ts->stat = SAS_SAM_STAT_BUSY; 3067f5860992SSakthivel K break; 3068f5860992SSakthivel K case IO_XFER_ERROR_PHY_NOT_READY: 30691b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); 3070f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3071d377f415SBart Van Assche ts->stat = SAS_SAM_STAT_BUSY; 3072f5860992SSakthivel K break; 3073f5860992SSakthivel K case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 30741b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 30751b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); 3076f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3077f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 3078f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3079f5860992SSakthivel K break; 3080f5860992SSakthivel K case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 30811b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 30821b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"); 3083f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3084f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 3085f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3086f5860992SSakthivel K break; 3087f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BREAK: 30881b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); 3089f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3090f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 3091f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 3092f5860992SSakthivel K break; 3093f5860992SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3094a6cb3d01SSakthivel K case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 3095a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 3096a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 3097a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 3098a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 30991b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); 3100f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3101f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 3102f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 3103f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 3104f5860992SSakthivel K pm8001_dev, 3105f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 3106f5860992SSakthivel K break; 3107f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 31081b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 31091b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"); 3110f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3111f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 3112f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_BAD_DEST; 3113f5860992SSakthivel K break; 3114f5860992SSakthivel K case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 31151b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 31161b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); 3117f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3118f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 3119f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_CONN_RATE; 3120f5860992SSakthivel K break; 3121f5860992SSakthivel K case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 31221b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 31231b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"); 3124f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3125f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 3126f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 3127f5860992SSakthivel K break; 3128f5860992SSakthivel K case IO_XFER_ERROR_RX_FRAME: 31291b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n"); 3130f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3131f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 3132f5860992SSakthivel K break; 3133f5860992SSakthivel K case IO_XFER_OPEN_RETRY_TIMEOUT: 31341b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); 3135f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3136f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 3137f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3138f5860992SSakthivel K break; 3139f5860992SSakthivel K case IO_ERROR_INTERNAL_SMP_RESOURCE: 31401b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n"); 3141f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3142f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 3143f5860992SSakthivel K break; 3144f5860992SSakthivel K case IO_PORT_IN_RESET: 31451b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); 3146f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3147f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 3148f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3149f5860992SSakthivel K break; 3150f5860992SSakthivel K case IO_DS_NON_OPERATIONAL: 31511b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); 3152f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3153f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 3154f5860992SSakthivel K break; 3155f5860992SSakthivel K case IO_DS_IN_RECOVERY: 31561b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); 3157f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3158f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 3159f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3160f5860992SSakthivel K break; 3161f5860992SSakthivel K case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 31621b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 31631b5d2793SJoe Perches "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"); 3164f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3165f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 3166f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 3167f5860992SSakthivel K break; 3168f5860992SSakthivel K default: 31691b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); 3170f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 3171f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 3172f5860992SSakthivel K /* not allowed case. Therefore, return failed status */ 3173f5860992SSakthivel K break; 3174f5860992SSakthivel K } 3175f5860992SSakthivel K spin_lock_irqsave(&t->task_state_lock, flags); 3176f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3177f5860992SSakthivel K t->task_state_flags |= SAS_TASK_STATE_DONE; 3178f5860992SSakthivel K if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 3179f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 31801b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 31811b5d2793SJoe Perches "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n", 31821b5d2793SJoe Perches t, status, ts->resp, ts->stat); 3183304fe11bSDamien Le Moal pm8001_ccb_task_free(pm8001_ha, ccb); 3184f5860992SSakthivel K } else { 3185f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 3186304fe11bSDamien Le Moal pm8001_ccb_task_free(pm8001_ha, ccb); 3187f5860992SSakthivel K mb();/* in order to force CPU ordering */ 3188f5860992SSakthivel K t->task_done(t); 3189f5860992SSakthivel K } 3190f5860992SSakthivel K } 3191f5860992SSakthivel K 3192f5860992SSakthivel K /** 3193bb6beabfSRandy Dunlap * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW. 3194f5860992SSakthivel K * @pm8001_ha: our hba card information 3195f5860992SSakthivel K * @Qnum: the outbound queue message number. 3196f5860992SSakthivel K * @SEA: source of event to ack 3197f5860992SSakthivel K * @port_id: port id. 3198f5860992SSakthivel K * @phyId: phy id. 3199f5860992SSakthivel K * @param0: parameter 0. 3200f5860992SSakthivel K * @param1: parameter 1. 3201f5860992SSakthivel K */ 3202f5860992SSakthivel K static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3203f5860992SSakthivel K u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3204f5860992SSakthivel K { 3205f5860992SSakthivel K struct hw_event_ack_req payload; 3206f5860992SSakthivel K u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3207f5860992SSakthivel K 3208f5860992SSakthivel K memset((u8 *)&payload, 0, sizeof(payload)); 3209f5860992SSakthivel K payload.tag = cpu_to_le32(1); 3210f5860992SSakthivel K payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3211f5860992SSakthivel K ((phyId & 0xFF) << 24) | (port_id & 0xFF)); 3212f5860992SSakthivel K payload.param0 = cpu_to_le32(param0); 3213f5860992SSakthivel K payload.param1 = cpu_to_le32(param1); 3214f91767a3SDamien Le Moal 3215f91767a3SDamien Le Moal pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload, 321691a43fa6Speter chang sizeof(payload), 0); 3217f5860992SSakthivel K } 3218f5860992SSakthivel K 3219f5860992SSakthivel K static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3220f5860992SSakthivel K u32 phyId, u32 phy_op); 3221f5860992SSakthivel K 32228414cd80SViswas G static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha, 32238414cd80SViswas G void *piomb) 32248414cd80SViswas G { 32258414cd80SViswas G struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4); 32268414cd80SViswas G u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 32278414cd80SViswas G u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 32288414cd80SViswas G u32 lr_status_evt_portid = 32298414cd80SViswas G le32_to_cpu(pPayload->lr_status_evt_portid); 32308414cd80SViswas G u8 deviceType = pPayload->sas_identify.dev_type; 32318414cd80SViswas G u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 32328414cd80SViswas G struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 32338414cd80SViswas G u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 32348414cd80SViswas G struct pm8001_port *port = &pm8001_ha->port[port_id]; 32358414cd80SViswas G 32368414cd80SViswas G if (deviceType == SAS_END_DEVICE) { 32378414cd80SViswas G pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 32388414cd80SViswas G PHY_NOTIFY_ENABLE_SPINUP); 32398414cd80SViswas G } 32408414cd80SViswas G 32418414cd80SViswas G port->wide_port_phymap |= (1U << phy_id); 32428414cd80SViswas G pm8001_get_lrate_mode(phy, link_rate); 32438414cd80SViswas G phy->sas_phy.oob_mode = SAS_OOB_MODE; 32448414cd80SViswas G phy->phy_state = PHY_STATE_LINK_UP_SPCV; 32458414cd80SViswas G phy->phy_attached = 1; 32468414cd80SViswas G } 32478414cd80SViswas G 3248f5860992SSakthivel K /** 3249f5860992SSakthivel K * hw_event_sas_phy_up - FW tells me a SAS phy up event. 3250f5860992SSakthivel K * @pm8001_ha: our hba card information 3251f5860992SSakthivel K * @piomb: IO message buffer 3252f5860992SSakthivel K */ 3253f5860992SSakthivel K static void 3254f5860992SSakthivel K hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3255f5860992SSakthivel K { 3256f5860992SSakthivel K struct hw_event_resp *pPayload = 3257f5860992SSakthivel K (struct hw_event_resp *)(piomb + 4); 3258f5860992SSakthivel K u32 lr_status_evt_portid = 3259f5860992SSakthivel K le32_to_cpu(pPayload->lr_status_evt_portid); 3260f5860992SSakthivel K u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3261f5860992SSakthivel K 3262f5860992SSakthivel K u8 link_rate = 3263f5860992SSakthivel K (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3264f5860992SSakthivel K u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3265f5860992SSakthivel K u8 phy_id = 3266f5860992SSakthivel K (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3267f5860992SSakthivel K u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3268f5860992SSakthivel K 3269f5860992SSakthivel K struct pm8001_port *port = &pm8001_ha->port[port_id]; 3270f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3271f5860992SSakthivel K unsigned long flags; 3272f5860992SSakthivel K u8 deviceType = pPayload->sas_identify.dev_type; 327308d0a992SAjish Koshy phy->port = port; 327408d0a992SAjish Koshy port->port_id = port_id; 3275f5860992SSakthivel K port->port_state = portstate; 32768414cd80SViswas G port->wide_port_phymap |= (1U << phy_id); 32777d029005SNikith Ganigarakoppal phy->phy_state = PHY_STATE_LINK_UP_SPCV; 32781b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 32791b5d2793SJoe Perches "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n", 32801b5d2793SJoe Perches port_id, phy_id, link_rate, portstate, deviceType); 3281f5860992SSakthivel K 3282f5860992SSakthivel K switch (deviceType) { 3283f5860992SSakthivel K case SAS_PHY_UNUSED: 32841b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "device type no device.\n"); 3285f5860992SSakthivel K break; 3286f5860992SSakthivel K case SAS_END_DEVICE: 32871b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "end device.\n"); 3288f5860992SSakthivel K pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 3289f5860992SSakthivel K PHY_NOTIFY_ENABLE_SPINUP); 3290f5860992SSakthivel K port->port_attached = 1; 3291f5860992SSakthivel K pm8001_get_lrate_mode(phy, link_rate); 3292f5860992SSakthivel K break; 3293f5860992SSakthivel K case SAS_EDGE_EXPANDER_DEVICE: 32941b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "expander device.\n"); 3295f5860992SSakthivel K port->port_attached = 1; 3296f5860992SSakthivel K pm8001_get_lrate_mode(phy, link_rate); 3297f5860992SSakthivel K break; 3298f5860992SSakthivel K case SAS_FANOUT_EXPANDER_DEVICE: 32991b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n"); 3300f5860992SSakthivel K port->port_attached = 1; 3301f5860992SSakthivel K pm8001_get_lrate_mode(phy, link_rate); 3302f5860992SSakthivel K break; 3303f5860992SSakthivel K default: 33041b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n", 33051b5d2793SJoe Perches deviceType); 3306f5860992SSakthivel K break; 3307f5860992SSakthivel K } 3308f5860992SSakthivel K phy->phy_type |= PORT_TYPE_SAS; 3309f5860992SSakthivel K phy->identify.device_type = deviceType; 3310f5860992SSakthivel K phy->phy_attached = 1; 3311f5860992SSakthivel K if (phy->identify.device_type == SAS_END_DEVICE) 3312f5860992SSakthivel K phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3313f5860992SSakthivel K else if (phy->identify.device_type != SAS_PHY_UNUSED) 3314f5860992SSakthivel K phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3315f5860992SSakthivel K phy->sas_phy.oob_mode = SAS_OOB_MODE; 3316de6d7547SAhmed S. Darwish sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3317f5860992SSakthivel K spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3318f5860992SSakthivel K memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3319f5860992SSakthivel K sizeof(struct sas_identify_frame)-4); 3320f5860992SSakthivel K phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3321f5860992SSakthivel K pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3322f5860992SSakthivel K spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3323f5860992SSakthivel K if (pm8001_ha->flags == PM8001F_RUN_TIME) 33244ba9e516SAhmed S. Darwish mdelay(200); /* delay a moment to wait for disk to spin up */ 3325f5860992SSakthivel K pm8001_bytes_dmaed(pm8001_ha, phy_id); 3326f5860992SSakthivel K } 3327f5860992SSakthivel K 3328f5860992SSakthivel K /** 3329f5860992SSakthivel K * hw_event_sata_phy_up - FW tells me a SATA phy up event. 3330f5860992SSakthivel K * @pm8001_ha: our hba card information 3331f5860992SSakthivel K * @piomb: IO message buffer 3332f5860992SSakthivel K */ 3333f5860992SSakthivel K static void 3334f5860992SSakthivel K hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3335f5860992SSakthivel K { 3336f5860992SSakthivel K struct hw_event_resp *pPayload = 3337f5860992SSakthivel K (struct hw_event_resp *)(piomb + 4); 3338f5860992SSakthivel K u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3339f5860992SSakthivel K u32 lr_status_evt_portid = 3340f5860992SSakthivel K le32_to_cpu(pPayload->lr_status_evt_portid); 3341f5860992SSakthivel K u8 link_rate = 3342f5860992SSakthivel K (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 3343f5860992SSakthivel K u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3344f5860992SSakthivel K u8 phy_id = 3345f5860992SSakthivel K (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3346f5860992SSakthivel K 3347f5860992SSakthivel K u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3348f5860992SSakthivel K 3349f5860992SSakthivel K struct pm8001_port *port = &pm8001_ha->port[port_id]; 3350f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3351f5860992SSakthivel K unsigned long flags; 33521b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEVIO, 3353f5860992SSakthivel K "port id %d, phy id %d link_rate %d portstate 0x%x\n", 33541b5d2793SJoe Perches port_id, phy_id, link_rate, portstate); 3355f5860992SSakthivel K 335608d0a992SAjish Koshy phy->port = port; 335708d0a992SAjish Koshy port->port_id = port_id; 3358f5860992SSakthivel K port->port_state = portstate; 33597d029005SNikith Ganigarakoppal phy->phy_state = PHY_STATE_LINK_UP_SPCV; 3360f5860992SSakthivel K port->port_attached = 1; 3361f5860992SSakthivel K pm8001_get_lrate_mode(phy, link_rate); 3362f5860992SSakthivel K phy->phy_type |= PORT_TYPE_SATA; 3363f5860992SSakthivel K phy->phy_attached = 1; 3364f5860992SSakthivel K phy->sas_phy.oob_mode = SATA_OOB_MODE; 3365de6d7547SAhmed S. Darwish sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); 3366f5860992SSakthivel K spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3367f5860992SSakthivel K memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3368f5860992SSakthivel K sizeof(struct dev_to_host_fis)); 3369f5860992SSakthivel K phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3370f5860992SSakthivel K phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3371aa9f8328SJames Bottomley phy->identify.device_type = SAS_SATA_DEV; 3372f5860992SSakthivel K pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3373f5860992SSakthivel K spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3374f5860992SSakthivel K pm8001_bytes_dmaed(pm8001_ha, phy_id); 3375f5860992SSakthivel K } 3376f5860992SSakthivel K 3377f5860992SSakthivel K /** 3378f5860992SSakthivel K * hw_event_phy_down - we should notify the libsas the phy is down. 3379f5860992SSakthivel K * @pm8001_ha: our hba card information 3380f5860992SSakthivel K * @piomb: IO message buffer 3381f5860992SSakthivel K */ 3382f5860992SSakthivel K static void 3383f5860992SSakthivel K hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3384f5860992SSakthivel K { 3385f5860992SSakthivel K struct hw_event_resp *pPayload = 3386f5860992SSakthivel K (struct hw_event_resp *)(piomb + 4); 3387f5860992SSakthivel K 3388f5860992SSakthivel K u32 lr_status_evt_portid = 3389f5860992SSakthivel K le32_to_cpu(pPayload->lr_status_evt_portid); 3390f5860992SSakthivel K u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3391f5860992SSakthivel K u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3392f5860992SSakthivel K u8 phy_id = 3393f5860992SSakthivel K (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3394f5860992SSakthivel K u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 3395f5860992SSakthivel K 3396f5860992SSakthivel K struct pm8001_port *port = &pm8001_ha->port[port_id]; 3397f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3398869ddbdcSViswas G u32 port_sata = (phy->phy_type & PORT_TYPE_SATA); 3399f5860992SSakthivel K port->port_state = portstate; 3400f5860992SSakthivel K phy->identify.device_type = 0; 3401f5860992SSakthivel K phy->phy_attached = 0; 3402f5860992SSakthivel K switch (portstate) { 3403f5860992SSakthivel K case PORT_VALID: 3404f5860992SSakthivel K break; 3405f5860992SSakthivel K case PORT_INVALID: 34061b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n", 34071b5d2793SJoe Perches port_id); 34081b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 34091b5d2793SJoe Perches " Last phy Down and port invalid\n"); 3410869ddbdcSViswas G if (port_sata) { 34118414cd80SViswas G phy->phy_type = 0; 3412f5860992SSakthivel K port->port_attached = 0; 3413f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3414f5860992SSakthivel K port_id, phy_id, 0, 0); 34158414cd80SViswas G } 34168414cd80SViswas G sas_phy_disconnected(&phy->sas_phy); 3417f5860992SSakthivel K break; 3418f5860992SSakthivel K case PORT_IN_RESET: 34191b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n", 34201b5d2793SJoe Perches port_id); 3421f5860992SSakthivel K break; 3422f5860992SSakthivel K case PORT_NOT_ESTABLISHED: 34231b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 34241b5d2793SJoe Perches " Phy Down and PORT_NOT_ESTABLISHED\n"); 3425f5860992SSakthivel K port->port_attached = 0; 3426f5860992SSakthivel K break; 3427f5860992SSakthivel K case PORT_LOSTCOMM: 34281b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n"); 34291b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 34301b5d2793SJoe Perches " Last phy Down and port invalid\n"); 3431869ddbdcSViswas G if (port_sata) { 3432f5860992SSakthivel K port->port_attached = 0; 34338414cd80SViswas G phy->phy_type = 0; 3434f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3435f5860992SSakthivel K port_id, phy_id, 0, 0); 34368414cd80SViswas G } 34378414cd80SViswas G sas_phy_disconnected(&phy->sas_phy); 3438f5860992SSakthivel K break; 3439f5860992SSakthivel K default: 3440f5860992SSakthivel K port->port_attached = 0; 34411b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEVIO, 34421b5d2793SJoe Perches " Phy Down and(default) = 0x%x\n", 34431b5d2793SJoe Perches portstate); 3444f5860992SSakthivel K break; 3445f5860992SSakthivel K 3446f5860992SSakthivel K } 3447121181f3SJohn Garry if (port_sata && (portstate != PORT_IN_RESET)) 3448de6d7547SAhmed S. Darwish sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL, 3449cd4e8176SAhmed S. Darwish GFP_ATOMIC); 3450f5860992SSakthivel K } 3451f5860992SSakthivel K 3452f5860992SSakthivel K static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3453f5860992SSakthivel K { 3454f5860992SSakthivel K struct phy_start_resp *pPayload = 3455f5860992SSakthivel K (struct phy_start_resp *)(piomb + 4); 3456f5860992SSakthivel K u32 status = 3457f5860992SSakthivel K le32_to_cpu(pPayload->status); 3458f5860992SSakthivel K u32 phy_id = 3459744798fcSIgor Pylypiv le32_to_cpu(pPayload->phyid) & 0xFF; 3460f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3461f5860992SSakthivel K 34621b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, 34631b5d2793SJoe Perches "phy start resp status:0x%x, phyid:0x%x\n", 34641b5d2793SJoe Perches status, phy_id); 3465d1acd81bSAjish Koshy if (status == 0) 3466cd135754SDeepak Ukey phy->phy_state = PHY_LINK_DOWN; 3467d1acd81bSAjish Koshy 3468cd135754SDeepak Ukey if (pm8001_ha->flags == PM8001F_RUN_TIME && 3469e703977bSpeter chang phy->enable_completion != NULL) { 3470f5860992SSakthivel K complete(phy->enable_completion); 3471e703977bSpeter chang phy->enable_completion = NULL; 3472e703977bSpeter chang } 3473f5860992SSakthivel K return 0; 3474f5860992SSakthivel K 3475f5860992SSakthivel K } 3476f5860992SSakthivel K 3477f5860992SSakthivel K /** 3478bb6beabfSRandy Dunlap * mpi_thermal_hw_event - a thermal hw event has come. 3479f5860992SSakthivel K * @pm8001_ha: our hba card information 3480f5860992SSakthivel K * @piomb: IO message buffer 3481f5860992SSakthivel K */ 3482f5860992SSakthivel K static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3483f5860992SSakthivel K { 3484f5860992SSakthivel K struct thermal_hw_event *pPayload = 3485f5860992SSakthivel K (struct thermal_hw_event *)(piomb + 4); 3486f5860992SSakthivel K 3487f5860992SSakthivel K u32 thermal_event = le32_to_cpu(pPayload->thermal_event); 3488f5860992SSakthivel K u32 rht_lht = le32_to_cpu(pPayload->rht_lht); 3489f5860992SSakthivel K 3490f5860992SSakthivel K if (thermal_event & 0x40) { 34911b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 34921b5d2793SJoe Perches "Thermal Event: Local high temperature violated!\n"); 34931b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 3494f5860992SSakthivel K "Thermal Event: Measured local high temperature %d\n", 34951b5d2793SJoe Perches ((rht_lht & 0xFF00) >> 8)); 3496f5860992SSakthivel K } 3497f5860992SSakthivel K if (thermal_event & 0x10) { 34981b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 34991b5d2793SJoe Perches "Thermal Event: Remote high temperature violated!\n"); 35001b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 3501f5860992SSakthivel K "Thermal Event: Measured remote high temperature %d\n", 35021b5d2793SJoe Perches ((rht_lht & 0xFF000000) >> 24)); 3503f5860992SSakthivel K } 3504f5860992SSakthivel K return 0; 3505f5860992SSakthivel K } 3506f5860992SSakthivel K 3507f5860992SSakthivel K /** 3508f5860992SSakthivel K * mpi_hw_event - The hw event has come. 3509f5860992SSakthivel K * @pm8001_ha: our hba card information 3510f5860992SSakthivel K * @piomb: IO message buffer 3511f5860992SSakthivel K */ 3512f5860992SSakthivel K static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 3513f5860992SSakthivel K { 35148414cd80SViswas G unsigned long flags, i; 3515f5860992SSakthivel K struct hw_event_resp *pPayload = 3516f5860992SSakthivel K (struct hw_event_resp *)(piomb + 4); 3517f5860992SSakthivel K u32 lr_status_evt_portid = 3518f5860992SSakthivel K le32_to_cpu(pPayload->lr_status_evt_portid); 3519f5860992SSakthivel K u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 3520f5860992SSakthivel K u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 3521f5860992SSakthivel K u8 phy_id = 3522f5860992SSakthivel K (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 3523f5860992SSakthivel K u16 eventType = 3524f5860992SSakthivel K (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); 3525f5860992SSakthivel K u8 status = 3526f5860992SSakthivel K (u8)((lr_status_evt_portid & 0x0F000000) >> 24); 3527f5860992SSakthivel K struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3528f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 35298414cd80SViswas G struct pm8001_port *port = &pm8001_ha->port[port_id]; 3530f5860992SSakthivel K struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 35311b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEV, 35321b5d2793SJoe Perches "portid:%d phyid:%d event:0x%x status:0x%x\n", 35331b5d2793SJoe Perches port_id, phy_id, eventType, status); 3534f5860992SSakthivel K 3535f5860992SSakthivel K switch (eventType) { 3536f5860992SSakthivel K 3537f5860992SSakthivel K case HW_EVENT_SAS_PHY_UP: 35381b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n"); 3539f5860992SSakthivel K hw_event_sas_phy_up(pm8001_ha, piomb); 3540f5860992SSakthivel K break; 3541f5860992SSakthivel K case HW_EVENT_SATA_PHY_UP: 35421b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n"); 3543f5860992SSakthivel K hw_event_sata_phy_up(pm8001_ha, piomb); 3544f5860992SSakthivel K break; 3545f5860992SSakthivel K case HW_EVENT_SATA_SPINUP_HOLD: 35461b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n"); 3547de6d7547SAhmed S. Darwish sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD, 3548cd4e8176SAhmed S. Darwish GFP_ATOMIC); 3549f5860992SSakthivel K break; 3550f5860992SSakthivel K case HW_EVENT_PHY_DOWN: 35511b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n"); 3552869ddbdcSViswas G hw_event_phy_down(pm8001_ha, piomb); 3553869ddbdcSViswas G if (pm8001_ha->reset_in_progress) { 35541b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n"); 3555869ddbdcSViswas G return 0; 3556869ddbdcSViswas G } 3557f5860992SSakthivel K phy->phy_attached = 0; 3558cd135754SDeepak Ukey phy->phy_state = PHY_LINK_DISABLE; 3559f5860992SSakthivel K break; 3560f5860992SSakthivel K case HW_EVENT_PORT_INVALID: 35611b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n"); 3562f5860992SSakthivel K sas_phy_disconnected(sas_phy); 3563f5860992SSakthivel K phy->phy_attached = 0; 3564de6d7547SAhmed S. Darwish sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3565cd4e8176SAhmed S. Darwish GFP_ATOMIC); 3566f5860992SSakthivel K break; 3567f5860992SSakthivel K /* the broadcast change primitive received, tell the LIBSAS this event 3568f5860992SSakthivel K to revalidate the sas domain*/ 3569f5860992SSakthivel K case HW_EVENT_BROADCAST_CHANGE: 35701b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n"); 3571f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3572f5860992SSakthivel K port_id, phy_id, 1, 0); 3573f5860992SSakthivel K spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3574f5860992SSakthivel K sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3575f5860992SSakthivel K spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3576de6d7547SAhmed S. Darwish sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3577cd4e8176SAhmed S. Darwish GFP_ATOMIC); 3578f5860992SSakthivel K break; 3579f5860992SSakthivel K case HW_EVENT_PHY_ERROR: 35801b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n"); 3581f5860992SSakthivel K sas_phy_disconnected(&phy->sas_phy); 3582f5860992SSakthivel K phy->phy_attached = 0; 3583de6d7547SAhmed S. Darwish sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC); 3584f5860992SSakthivel K break; 3585f5860992SSakthivel K case HW_EVENT_BROADCAST_EXP: 35861b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n"); 3587f5860992SSakthivel K spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3588f5860992SSakthivel K sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3589f5860992SSakthivel K spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3590de6d7547SAhmed S. Darwish sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3591cd4e8176SAhmed S. Darwish GFP_ATOMIC); 3592f5860992SSakthivel K break; 3593f5860992SSakthivel K case HW_EVENT_LINK_ERR_INVALID_DWORD: 35941b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 35951b5d2793SJoe Perches "HW_EVENT_LINK_ERR_INVALID_DWORD\n"); 3596f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3597f5860992SSakthivel K HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3598f5860992SSakthivel K break; 3599f5860992SSakthivel K case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 36001b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 36011b5d2793SJoe Perches "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"); 3602f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3603f5860992SSakthivel K HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3604f5860992SSakthivel K port_id, phy_id, 0, 0); 3605f5860992SSakthivel K break; 3606f5860992SSakthivel K case HW_EVENT_LINK_ERR_CODE_VIOLATION: 36071b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 36081b5d2793SJoe Perches "HW_EVENT_LINK_ERR_CODE_VIOLATION\n"); 3609f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3610f5860992SSakthivel K HW_EVENT_LINK_ERR_CODE_VIOLATION, 3611f5860992SSakthivel K port_id, phy_id, 0, 0); 3612f5860992SSakthivel K break; 3613f5860992SSakthivel K case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 36141b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 36151b5d2793SJoe Perches "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"); 3616f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3617f5860992SSakthivel K HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3618f5860992SSakthivel K port_id, phy_id, 0, 0); 3619f5860992SSakthivel K break; 3620f5860992SSakthivel K case HW_EVENT_MALFUNCTION: 36211b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n"); 3622f5860992SSakthivel K break; 3623f5860992SSakthivel K case HW_EVENT_BROADCAST_SES: 36241b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n"); 3625f5860992SSakthivel K spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3626f5860992SSakthivel K sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3627f5860992SSakthivel K spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3628de6d7547SAhmed S. Darwish sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, 3629cd4e8176SAhmed S. Darwish GFP_ATOMIC); 3630f5860992SSakthivel K break; 3631f5860992SSakthivel K case HW_EVENT_INBOUND_CRC_ERROR: 36321b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n"); 3633f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3634f5860992SSakthivel K HW_EVENT_INBOUND_CRC_ERROR, 3635f5860992SSakthivel K port_id, phy_id, 0, 0); 3636f5860992SSakthivel K break; 3637f5860992SSakthivel K case HW_EVENT_HARD_RESET_RECEIVED: 36381b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n"); 3639de6d7547SAhmed S. Darwish sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC); 3640f5860992SSakthivel K break; 3641f5860992SSakthivel K case HW_EVENT_ID_FRAME_TIMEOUT: 36421b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n"); 3643f5860992SSakthivel K sas_phy_disconnected(sas_phy); 3644f5860992SSakthivel K phy->phy_attached = 0; 3645de6d7547SAhmed S. Darwish sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3646cd4e8176SAhmed S. Darwish GFP_ATOMIC); 3647f5860992SSakthivel K break; 3648f5860992SSakthivel K case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 36491b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 36501b5d2793SJoe Perches "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"); 3651f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3652f5860992SSakthivel K HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3653f5860992SSakthivel K port_id, phy_id, 0, 0); 3654f5860992SSakthivel K sas_phy_disconnected(sas_phy); 3655f5860992SSakthivel K phy->phy_attached = 0; 3656de6d7547SAhmed S. Darwish sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3657cd4e8176SAhmed S. Darwish GFP_ATOMIC); 3658f5860992SSakthivel K break; 3659f5860992SSakthivel K case HW_EVENT_PORT_RESET_TIMER_TMO: 36601b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n"); 3661ee05cb71SAjish Koshy if (!pm8001_ha->phy[phy_id].reset_completion) { 3662869ddbdcSViswas G pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3663869ddbdcSViswas G port_id, phy_id, 0, 0); 3664ee05cb71SAjish Koshy } 3665f5860992SSakthivel K sas_phy_disconnected(sas_phy); 3666f5860992SSakthivel K phy->phy_attached = 0; 3667de6d7547SAhmed S. Darwish sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR, 3668cd4e8176SAhmed S. Darwish GFP_ATOMIC); 3669869ddbdcSViswas G if (pm8001_ha->phy[phy_id].reset_completion) { 3670869ddbdcSViswas G pm8001_ha->phy[phy_id].port_reset_status = 3671869ddbdcSViswas G PORT_RESET_TMO; 3672869ddbdcSViswas G complete(pm8001_ha->phy[phy_id].reset_completion); 3673869ddbdcSViswas G pm8001_ha->phy[phy_id].reset_completion = NULL; 3674869ddbdcSViswas G } 3675f5860992SSakthivel K break; 3676f5860992SSakthivel K case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 36771b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 36781b5d2793SJoe Perches "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"); 3679a6cb3d01SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3680a6cb3d01SSakthivel K HW_EVENT_PORT_RECOVERY_TIMER_TMO, 3681a6cb3d01SSakthivel K port_id, phy_id, 0, 0); 36828414cd80SViswas G for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 36838414cd80SViswas G if (port->wide_port_phymap & (1 << i)) { 36848414cd80SViswas G phy = &pm8001_ha->phy[i]; 3685de6d7547SAhmed S. Darwish sas_notify_phy_event(&phy->sas_phy, 3686cd4e8176SAhmed S. Darwish PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC); 36878414cd80SViswas G port->wide_port_phymap &= ~(1 << i); 36888414cd80SViswas G } 36898414cd80SViswas G } 3690f5860992SSakthivel K break; 3691f5860992SSakthivel K case HW_EVENT_PORT_RECOVER: 36921b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n"); 36938414cd80SViswas G hw_event_port_recover(pm8001_ha, piomb); 3694f5860992SSakthivel K break; 3695f5860992SSakthivel K case HW_EVENT_PORT_RESET_COMPLETE: 36961b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n"); 3697869ddbdcSViswas G if (pm8001_ha->phy[phy_id].reset_completion) { 3698869ddbdcSViswas G pm8001_ha->phy[phy_id].port_reset_status = 3699869ddbdcSViswas G PORT_RESET_SUCCESS; 3700869ddbdcSViswas G complete(pm8001_ha->phy[phy_id].reset_completion); 3701869ddbdcSViswas G pm8001_ha->phy[phy_id].reset_completion = NULL; 3702869ddbdcSViswas G } 3703f5860992SSakthivel K break; 3704f5860992SSakthivel K case EVENT_BROADCAST_ASYNCH_EVENT: 37051b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n"); 3706f5860992SSakthivel K break; 3707f5860992SSakthivel K default: 37081b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n", 37091b5d2793SJoe Perches eventType); 3710f5860992SSakthivel K break; 3711f5860992SSakthivel K } 3712f5860992SSakthivel K return 0; 3713f5860992SSakthivel K } 3714f5860992SSakthivel K 3715f5860992SSakthivel K /** 3716f5860992SSakthivel K * mpi_phy_stop_resp - SPCv specific 3717f5860992SSakthivel K * @pm8001_ha: our hba card information 3718f5860992SSakthivel K * @piomb: IO message buffer 3719f5860992SSakthivel K */ 3720f5860992SSakthivel K static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3721f5860992SSakthivel K { 3722f5860992SSakthivel K struct phy_stop_resp *pPayload = 3723f5860992SSakthivel K (struct phy_stop_resp *)(piomb + 4); 3724f5860992SSakthivel K u32 status = 3725f5860992SSakthivel K le32_to_cpu(pPayload->status); 3726f5860992SSakthivel K u32 phyid = 3727cd135754SDeepak Ukey le32_to_cpu(pPayload->phyid) & 0xFF; 3728f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; 37291b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n", 37301b5d2793SJoe Perches phyid, status); 3731cd135754SDeepak Ukey if (status == PHY_STOP_SUCCESS || 3732cd135754SDeepak Ukey status == PHY_STOP_ERR_DEVICE_ATTACHED) 3733cd135754SDeepak Ukey phy->phy_state = PHY_LINK_DISABLE; 3734f5860992SSakthivel K return 0; 3735f5860992SSakthivel K } 3736f5860992SSakthivel K 3737f5860992SSakthivel K /** 3738f5860992SSakthivel K * mpi_set_controller_config_resp - SPCv specific 3739f5860992SSakthivel K * @pm8001_ha: our hba card information 3740f5860992SSakthivel K * @piomb: IO message buffer 3741f5860992SSakthivel K */ 3742f5860992SSakthivel K static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3743f5860992SSakthivel K void *piomb) 3744f5860992SSakthivel K { 3745f5860992SSakthivel K struct set_ctrl_cfg_resp *pPayload = 3746f5860992SSakthivel K (struct set_ctrl_cfg_resp *)(piomb + 4); 3747f5860992SSakthivel K u32 status = le32_to_cpu(pPayload->status); 3748f5860992SSakthivel K u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); 3749f5860992SSakthivel K 37501b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 3751f5860992SSakthivel K "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", 37521b5d2793SJoe Perches status, err_qlfr_pgcd); 3753f5860992SSakthivel K 3754f5860992SSakthivel K return 0; 3755f5860992SSakthivel K } 3756f5860992SSakthivel K 3757f5860992SSakthivel K /** 3758f5860992SSakthivel K * mpi_get_controller_config_resp - SPCv specific 3759f5860992SSakthivel K * @pm8001_ha: our hba card information 3760f5860992SSakthivel K * @piomb: IO message buffer 3761f5860992SSakthivel K */ 3762f5860992SSakthivel K static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3763f5860992SSakthivel K void *piomb) 3764f5860992SSakthivel K { 37651b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3766f5860992SSakthivel K 3767f5860992SSakthivel K return 0; 3768f5860992SSakthivel K } 3769f5860992SSakthivel K 3770f5860992SSakthivel K /** 3771f5860992SSakthivel K * mpi_get_phy_profile_resp - SPCv specific 3772f5860992SSakthivel K * @pm8001_ha: our hba card information 3773f5860992SSakthivel K * @piomb: IO message buffer 3774f5860992SSakthivel K */ 3775f5860992SSakthivel K static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3776f5860992SSakthivel K void *piomb) 3777f5860992SSakthivel K { 37781b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3779f5860992SSakthivel K 3780f5860992SSakthivel K return 0; 3781f5860992SSakthivel K } 3782f5860992SSakthivel K 3783f5860992SSakthivel K /** 3784f5860992SSakthivel K * mpi_flash_op_ext_resp - SPCv specific 3785f5860992SSakthivel K * @pm8001_ha: our hba card information 3786f5860992SSakthivel K * @piomb: IO message buffer 3787f5860992SSakthivel K */ 3788f5860992SSakthivel K static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3789f5860992SSakthivel K { 37901b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3791f5860992SSakthivel K 3792f5860992SSakthivel K return 0; 3793f5860992SSakthivel K } 3794f5860992SSakthivel K 3795f5860992SSakthivel K /** 3796f5860992SSakthivel K * mpi_set_phy_profile_resp - SPCv specific 3797f5860992SSakthivel K * @pm8001_ha: our hba card information 3798f5860992SSakthivel K * @piomb: IO message buffer 3799f5860992SSakthivel K */ 3800f5860992SSakthivel K static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3801f5860992SSakthivel K void *piomb) 3802f5860992SSakthivel K { 38039d9c7c20Syuuzheng u32 tag; 380427909407SAnand Kumar Santhanam u8 page_code; 38059d9c7c20Syuuzheng int rc = 0; 380627909407SAnand Kumar Santhanam struct set_phy_profile_resp *pPayload = 380727909407SAnand Kumar Santhanam (struct set_phy_profile_resp *)(piomb + 4); 380827909407SAnand Kumar Santhanam u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); 380927909407SAnand Kumar Santhanam u32 status = le32_to_cpu(pPayload->status); 3810f5860992SSakthivel K 38119d9c7c20Syuuzheng tag = le32_to_cpu(pPayload->tag); 381227909407SAnand Kumar Santhanam page_code = (u8)((ppc_phyid & 0xFF00) >> 8); 381327909407SAnand Kumar Santhanam if (status) { 381427909407SAnand Kumar Santhanam /* status is FAILED */ 38151b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 38161b5d2793SJoe Perches "PhyProfile command failed with status 0x%08X\n", 38171b5d2793SJoe Perches status); 38189d9c7c20Syuuzheng rc = -1; 381927909407SAnand Kumar Santhanam } else { 382027909407SAnand Kumar Santhanam if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) { 38211b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n", 38221b5d2793SJoe Perches page_code); 38239d9c7c20Syuuzheng rc = -1; 382427909407SAnand Kumar Santhanam } 382527909407SAnand Kumar Santhanam } 38269d9c7c20Syuuzheng pm8001_tag_free(pm8001_ha, tag); 38279d9c7c20Syuuzheng return rc; 3828f5860992SSakthivel K } 3829f5860992SSakthivel K 3830f5860992SSakthivel K /** 3831f5860992SSakthivel K * mpi_kek_management_resp - SPCv specific 3832f5860992SSakthivel K * @pm8001_ha: our hba card information 3833f5860992SSakthivel K * @piomb: IO message buffer 3834f5860992SSakthivel K */ 3835f5860992SSakthivel K static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, 3836f5860992SSakthivel K void *piomb) 3837f5860992SSakthivel K { 3838f5860992SSakthivel K struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); 3839f5860992SSakthivel K 3840f5860992SSakthivel K u32 status = le32_to_cpu(pPayload->status); 3841f5860992SSakthivel K u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); 3842f5860992SSakthivel K u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); 3843f5860992SSakthivel K 38441b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 3845f5860992SSakthivel K "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", 38461b5d2793SJoe Perches status, kidx_new_curr_ksop, err_qlfr); 3847f5860992SSakthivel K 3848f5860992SSakthivel K return 0; 3849f5860992SSakthivel K } 3850f5860992SSakthivel K 3851f5860992SSakthivel K /** 3852f5860992SSakthivel K * mpi_dek_management_resp - SPCv specific 3853f5860992SSakthivel K * @pm8001_ha: our hba card information 3854f5860992SSakthivel K * @piomb: IO message buffer 3855f5860992SSakthivel K */ 3856f5860992SSakthivel K static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, 3857f5860992SSakthivel K void *piomb) 3858f5860992SSakthivel K { 38591b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3860f5860992SSakthivel K 3861f5860992SSakthivel K return 0; 3862f5860992SSakthivel K } 3863f5860992SSakthivel K 3864f5860992SSakthivel K /** 3865f5860992SSakthivel K * ssp_coalesced_comp_resp - SPCv specific 3866f5860992SSakthivel K * @pm8001_ha: our hba card information 3867f5860992SSakthivel K * @piomb: IO message buffer 3868f5860992SSakthivel K */ 3869f5860992SSakthivel K static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, 3870f5860992SSakthivel K void *piomb) 3871f5860992SSakthivel K { 38721b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n"); 3873f5860992SSakthivel K 3874f5860992SSakthivel K return 0; 3875f5860992SSakthivel K } 3876f5860992SSakthivel K 3877f5860992SSakthivel K /** 3878f5860992SSakthivel K * process_one_iomb - process one outbound Queue memory block 3879f5860992SSakthivel K * @pm8001_ha: our hba card information 38800aed75fdSJohn Garry * @circularQ: outbound circular queue 3881f5860992SSakthivel K * @piomb: IO message buffer 3882f5860992SSakthivel K */ 3883b27a4053SAjish Koshy static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, 3884b27a4053SAjish Koshy struct outbound_queue_table *circularQ, void *piomb) 3885f5860992SSakthivel K { 3886f5860992SSakthivel K __le32 pHeader = *(__le32 *)piomb; 3887f5860992SSakthivel K u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); 3888f5860992SSakthivel K 3889f5860992SSakthivel K switch (opc) { 3890f5860992SSakthivel K case OPC_OUB_ECHO: 38911b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n"); 3892f5860992SSakthivel K break; 3893f5860992SSakthivel K case OPC_OUB_HW_EVENT: 38941b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n"); 3895f5860992SSakthivel K mpi_hw_event(pm8001_ha, piomb); 3896f5860992SSakthivel K break; 3897f5860992SSakthivel K case OPC_OUB_THERM_HW_EVENT: 38981b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n"); 3899f5860992SSakthivel K mpi_thermal_hw_event(pm8001_ha, piomb); 3900f5860992SSakthivel K break; 3901f5860992SSakthivel K case OPC_OUB_SSP_COMP: 39021b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n"); 3903f5860992SSakthivel K mpi_ssp_completion(pm8001_ha, piomb); 3904f5860992SSakthivel K break; 3905f5860992SSakthivel K case OPC_OUB_SMP_COMP: 39061b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n"); 3907f5860992SSakthivel K mpi_smp_completion(pm8001_ha, piomb); 3908f5860992SSakthivel K break; 3909f5860992SSakthivel K case OPC_OUB_LOCAL_PHY_CNTRL: 39101b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n"); 3911f5860992SSakthivel K pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3912f5860992SSakthivel K break; 3913f5860992SSakthivel K case OPC_OUB_DEV_REGIST: 39141b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n"); 3915f5860992SSakthivel K pm8001_mpi_reg_resp(pm8001_ha, piomb); 3916f5860992SSakthivel K break; 3917f5860992SSakthivel K case OPC_OUB_DEREG_DEV: 39181b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "unregister the device\n"); 3919f5860992SSakthivel K pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3920f5860992SSakthivel K break; 3921f5860992SSakthivel K case OPC_OUB_GET_DEV_HANDLE: 39221b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n"); 3923f5860992SSakthivel K break; 3924f5860992SSakthivel K case OPC_OUB_SATA_COMP: 39251b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n"); 3926b27a4053SAjish Koshy mpi_sata_completion(pm8001_ha, circularQ, piomb); 3927f5860992SSakthivel K break; 3928f5860992SSakthivel K case OPC_OUB_SATA_EVENT: 39291b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n"); 3930b27a4053SAjish Koshy mpi_sata_event(pm8001_ha, circularQ, piomb); 3931f5860992SSakthivel K break; 3932f5860992SSakthivel K case OPC_OUB_SSP_EVENT: 39331b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n"); 3934f5860992SSakthivel K mpi_ssp_event(pm8001_ha, piomb); 3935f5860992SSakthivel K break; 3936f5860992SSakthivel K case OPC_OUB_DEV_HANDLE_ARRIV: 39371b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n"); 3938f5860992SSakthivel K /*This is for target*/ 3939f5860992SSakthivel K break; 3940f5860992SSakthivel K case OPC_OUB_SSP_RECV_EVENT: 39411b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n"); 3942f5860992SSakthivel K /*This is for target*/ 3943f5860992SSakthivel K break; 3944f5860992SSakthivel K case OPC_OUB_FW_FLASH_UPDATE: 39451b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n"); 3946f5860992SSakthivel K pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3947f5860992SSakthivel K break; 3948f5860992SSakthivel K case OPC_OUB_GPIO_RESPONSE: 39491b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n"); 3950f5860992SSakthivel K break; 3951f5860992SSakthivel K case OPC_OUB_GPIO_EVENT: 39521b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n"); 3953f5860992SSakthivel K break; 3954f5860992SSakthivel K case OPC_OUB_GENERAL_EVENT: 39551b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n"); 3956f5860992SSakthivel K pm8001_mpi_general_event(pm8001_ha, piomb); 3957f5860992SSakthivel K break; 3958f5860992SSakthivel K case OPC_OUB_SSP_ABORT_RSP: 39591b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n"); 3960f5860992SSakthivel K pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3961f5860992SSakthivel K break; 3962f5860992SSakthivel K case OPC_OUB_SATA_ABORT_RSP: 39631b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n"); 3964f5860992SSakthivel K pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3965f5860992SSakthivel K break; 3966f5860992SSakthivel K case OPC_OUB_SAS_DIAG_MODE_START_END: 39671b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 39681b5d2793SJoe Perches "OPC_OUB_SAS_DIAG_MODE_START_END\n"); 3969f5860992SSakthivel K break; 3970f5860992SSakthivel K case OPC_OUB_SAS_DIAG_EXECUTE: 39711b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n"); 3972f5860992SSakthivel K break; 3973f5860992SSakthivel K case OPC_OUB_GET_TIME_STAMP: 39741b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n"); 3975f5860992SSakthivel K break; 3976f5860992SSakthivel K case OPC_OUB_SAS_HW_EVENT_ACK: 39771b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n"); 3978f5860992SSakthivel K break; 3979f5860992SSakthivel K case OPC_OUB_PORT_CONTROL: 39801b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n"); 3981f5860992SSakthivel K break; 3982f5860992SSakthivel K case OPC_OUB_SMP_ABORT_RSP: 39831b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n"); 3984f5860992SSakthivel K pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3985f5860992SSakthivel K break; 3986f5860992SSakthivel K case OPC_OUB_GET_NVMD_DATA: 39871b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n"); 3988f5860992SSakthivel K pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 3989f5860992SSakthivel K break; 3990f5860992SSakthivel K case OPC_OUB_SET_NVMD_DATA: 39911b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n"); 3992f5860992SSakthivel K pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 3993f5860992SSakthivel K break; 3994f5860992SSakthivel K case OPC_OUB_DEVICE_HANDLE_REMOVAL: 39951b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n"); 3996f5860992SSakthivel K break; 3997f5860992SSakthivel K case OPC_OUB_SET_DEVICE_STATE: 39981b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n"); 3999f5860992SSakthivel K pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 4000f5860992SSakthivel K break; 4001f5860992SSakthivel K case OPC_OUB_GET_DEVICE_STATE: 40021b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n"); 4003f5860992SSakthivel K break; 4004f5860992SSakthivel K case OPC_OUB_SET_DEV_INFO: 40051b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n"); 4006f5860992SSakthivel K break; 4007bb6beabfSRandy Dunlap /* spcv specific commands */ 4008f5860992SSakthivel K case OPC_OUB_PHY_START_RESP: 40091b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 40101b5d2793SJoe Perches "OPC_OUB_PHY_START_RESP opcode:%x\n", opc); 4011f5860992SSakthivel K mpi_phy_start_resp(pm8001_ha, piomb); 4012f5860992SSakthivel K break; 4013f5860992SSakthivel K case OPC_OUB_PHY_STOP_RESP: 40141b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 40151b5d2793SJoe Perches "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc); 4016f5860992SSakthivel K mpi_phy_stop_resp(pm8001_ha, piomb); 4017f5860992SSakthivel K break; 4018f5860992SSakthivel K case OPC_OUB_SET_CONTROLLER_CONFIG: 40191b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 40201b5d2793SJoe Perches "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc); 4021f5860992SSakthivel K mpi_set_controller_config_resp(pm8001_ha, piomb); 4022f5860992SSakthivel K break; 4023f5860992SSakthivel K case OPC_OUB_GET_CONTROLLER_CONFIG: 40241b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 40251b5d2793SJoe Perches "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc); 4026f5860992SSakthivel K mpi_get_controller_config_resp(pm8001_ha, piomb); 4027f5860992SSakthivel K break; 4028f5860992SSakthivel K case OPC_OUB_GET_PHY_PROFILE: 40291b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 40301b5d2793SJoe Perches "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc); 4031f5860992SSakthivel K mpi_get_phy_profile_resp(pm8001_ha, piomb); 4032f5860992SSakthivel K break; 4033f5860992SSakthivel K case OPC_OUB_FLASH_OP_EXT: 40341b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 40351b5d2793SJoe Perches "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc); 4036f5860992SSakthivel K mpi_flash_op_ext_resp(pm8001_ha, piomb); 4037f5860992SSakthivel K break; 4038f5860992SSakthivel K case OPC_OUB_SET_PHY_PROFILE: 40391b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 40401b5d2793SJoe Perches "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc); 4041f5860992SSakthivel K mpi_set_phy_profile_resp(pm8001_ha, piomb); 4042f5860992SSakthivel K break; 4043f5860992SSakthivel K case OPC_OUB_KEK_MANAGEMENT_RESP: 40441b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 40451b5d2793SJoe Perches "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc); 4046f5860992SSakthivel K mpi_kek_management_resp(pm8001_ha, piomb); 4047f5860992SSakthivel K break; 4048f5860992SSakthivel K case OPC_OUB_DEK_MANAGEMENT_RESP: 40491b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 40501b5d2793SJoe Perches "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc); 4051f5860992SSakthivel K mpi_dek_management_resp(pm8001_ha, piomb); 4052f5860992SSakthivel K break; 4053f5860992SSakthivel K case OPC_OUB_SSP_COALESCED_COMP_RESP: 40541b5d2793SJoe Perches pm8001_dbg(pm8001_ha, MSG, 40551b5d2793SJoe Perches "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc); 4056f5860992SSakthivel K ssp_coalesced_comp_resp(pm8001_ha, piomb); 4057f5860992SSakthivel K break; 4058f5860992SSakthivel K default: 40591b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEVIO, 40601b5d2793SJoe Perches "Unknown outbound Queue IOMB OPC = 0x%x\n", opc); 4061f5860992SSakthivel K break; 4062f5860992SSakthivel K } 4063f5860992SSakthivel K } 4064f5860992SSakthivel K 406572349b62SDeepak Ukey static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha) 406672349b62SDeepak Ukey { 40671b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n", 40681b5d2793SJoe Perches pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); 40691b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n", 40701b5d2793SJoe Perches pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)); 40711b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n", 40721b5d2793SJoe Perches pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)); 40731b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n", 40741b5d2793SJoe Perches pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); 40751b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n", 40761b5d2793SJoe Perches pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)); 40771b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n", 40781b5d2793SJoe Perches pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)); 40791b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n", 40801b5d2793SJoe Perches pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)); 40811b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n", 40821b5d2793SJoe Perches pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)); 40831b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n", 40841b5d2793SJoe Perches pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)); 40851b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n", 40861b5d2793SJoe Perches pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)); 40871b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n", 408880cac47bSAjish Koshy pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_0)); 40891b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n", 409080cac47bSAjish Koshy pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_1)); 409172349b62SDeepak Ukey } 409272349b62SDeepak Ukey 4093f5860992SSakthivel K static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 4094f5860992SSakthivel K { 4095f5860992SSakthivel K struct outbound_queue_table *circularQ; 4096f5860992SSakthivel K void *pMsg1 = NULL; 40973f649ab7SKees Cook u8 bc; 4098f5860992SSakthivel K u32 ret = MPI_IO_STATUS_FAIL; 409972349b62SDeepak Ukey u32 regval; 4100f5860992SSakthivel K 410162afb379SJohn Garry /* 410262afb379SJohn Garry * Fatal errors are programmed to be signalled in irq vector 410362afb379SJohn Garry * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl. 410462afb379SJohn Garry * fatal_err_interrupt 410562afb379SJohn Garry */ 410605c6c029SViswas G if (vec == (pm8001_ha->max_q_num - 1)) { 410762afb379SJohn Garry u32 mipsall_ready; 410862afb379SJohn Garry 410962afb379SJohn Garry if (pm8001_ha->chip_id == chip_8008 || 411062afb379SJohn Garry pm8001_ha->chip_id == chip_8009) 411162afb379SJohn Garry mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT; 411262afb379SJohn Garry else 411362afb379SJohn Garry mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT; 411462afb379SJohn Garry 411572349b62SDeepak Ukey regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 411662afb379SJohn Garry if ((regval & mipsall_ready) != mipsall_ready) { 411772349b62SDeepak Ukey pm8001_ha->controller_fatal_error = true; 41181b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 41191b5d2793SJoe Perches "Firmware Fatal error! Regval:0x%x\n", 41201b5d2793SJoe Perches regval); 41214f5deeb4SRuksar Devadi pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR); 412272349b62SDeepak Ukey print_scratchpad_registers(pm8001_ha); 412372349b62SDeepak Ukey return ret; 412480cac47bSAjish Koshy } else { 412580cac47bSAjish Koshy /*read scratchpad rsvd 0 register*/ 412680cac47bSAjish Koshy regval = pm8001_cr32(pm8001_ha, 0, 412780cac47bSAjish Koshy MSGU_SCRATCH_PAD_RSVD_0); 412880cac47bSAjish Koshy switch (regval) { 412980cac47bSAjish Koshy case NON_FATAL_SPBC_LBUS_ECC_ERR: 413080cac47bSAjish Koshy case NON_FATAL_BDMA_ERR: 413180cac47bSAjish Koshy case NON_FATAL_THERM_OVERTEMP_ERR: 413280cac47bSAjish Koshy /*Clear the register*/ 413380cac47bSAjish Koshy pm8001_cw32(pm8001_ha, 0, 413480cac47bSAjish Koshy MSGU_SCRATCH_PAD_RSVD_0, 413580cac47bSAjish Koshy 0x00000000); 413680cac47bSAjish Koshy break; 413780cac47bSAjish Koshy default: 413880cac47bSAjish Koshy break; 413980cac47bSAjish Koshy } 414072349b62SDeepak Ukey } 414172349b62SDeepak Ukey } 4142f5860992SSakthivel K circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 4143b27a4053SAjish Koshy spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags); 4144f5860992SSakthivel K do { 414572349b62SDeepak Ukey /* spurious interrupt during setup if kexec-ing and 414672349b62SDeepak Ukey * driver doing a doorbell access w/ the pre-kexec oq 414772349b62SDeepak Ukey * interrupt setup. 414872349b62SDeepak Ukey */ 414972349b62SDeepak Ukey if (!circularQ->pi_virt) 415072349b62SDeepak Ukey break; 4151f5860992SSakthivel K ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 4152f5860992SSakthivel K if (MPI_IO_STATUS_SUCCESS == ret) { 4153f5860992SSakthivel K /* process the outbound message */ 4154b27a4053SAjish Koshy process_one_iomb(pm8001_ha, circularQ, 4155b27a4053SAjish Koshy (void *)(pMsg1 - 4)); 4156f5860992SSakthivel K /* free the message from the outbound circular buffer */ 4157f5860992SSakthivel K pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 4158f5860992SSakthivel K circularQ, bc); 4159f5860992SSakthivel K } 4160f5860992SSakthivel K if (MPI_IO_STATUS_BUSY == ret) { 4161f5860992SSakthivel K /* Update the producer index from SPC */ 4162f5860992SSakthivel K circularQ->producer_index = 4163f5860992SSakthivel K cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 4164f5860992SSakthivel K if (le32_to_cpu(circularQ->producer_index) == 4165f5860992SSakthivel K circularQ->consumer_idx) 4166f5860992SSakthivel K /* OQ is empty */ 4167f5860992SSakthivel K break; 4168f5860992SSakthivel K } 4169f5860992SSakthivel K } while (1); 4170b27a4053SAjish Koshy spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags); 4171f5860992SSakthivel K return ret; 4172f5860992SSakthivel K } 4173f5860992SSakthivel K 4174f73bdebdSChristoph Hellwig /* DMA_... to our direction translation. */ 4175f5860992SSakthivel K static const u8 data_dir_flags[] = { 4176f73bdebdSChristoph Hellwig [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */ 4177f73bdebdSChristoph Hellwig [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */ 4178f73bdebdSChristoph Hellwig [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */ 4179f73bdebdSChristoph Hellwig [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */ 4180f5860992SSakthivel K }; 4181f5860992SSakthivel K 4182f5860992SSakthivel K static void build_smp_cmd(u32 deviceID, __le32 hTag, 4183f5860992SSakthivel K struct smp_req *psmp_cmd, int mode, int length) 4184f5860992SSakthivel K { 4185f5860992SSakthivel K psmp_cmd->tag = hTag; 4186f5860992SSakthivel K psmp_cmd->device_id = cpu_to_le32(deviceID); 4187f5860992SSakthivel K if (mode == SMP_DIRECT) { 4188f5860992SSakthivel K length = length - 4; /* subtract crc */ 4189f5860992SSakthivel K psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); 4190f5860992SSakthivel K } else { 4191f5860992SSakthivel K psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 4192f5860992SSakthivel K } 4193f5860992SSakthivel K } 4194f5860992SSakthivel K 4195f5860992SSakthivel K /** 4196bb6beabfSRandy Dunlap * pm80xx_chip_smp_req - send an SMP task to FW 4197f5860992SSakthivel K * @pm8001_ha: our hba card information. 4198f5860992SSakthivel K * @ccb: the ccb information this request used. 4199f5860992SSakthivel K */ 4200f5860992SSakthivel K static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 4201f5860992SSakthivel K struct pm8001_ccb_info *ccb) 4202f5860992SSakthivel K { 4203f5860992SSakthivel K int elem, rc; 4204f5860992SSakthivel K struct sas_task *task = ccb->task; 4205f5860992SSakthivel K struct domain_device *dev = task->dev; 4206f5860992SSakthivel K struct pm8001_device *pm8001_dev = dev->lldd_dev; 42072fe24343SJohn Garry struct scatterlist *sg_req, *sg_resp, *smp_req; 4208f5860992SSakthivel K u32 req_len, resp_len; 4209f5860992SSakthivel K struct smp_req smp_cmd; 4210f5860992SSakthivel K u32 opc; 4211f5860992SSakthivel K u32 i, length; 42122fe24343SJohn Garry u8 *payload; 42132fe24343SJohn Garry u8 *to; 4214f5860992SSakthivel K 4215f5860992SSakthivel K memset(&smp_cmd, 0, sizeof(smp_cmd)); 4216f5860992SSakthivel K /* 4217f5860992SSakthivel K * DMA-map SMP request, response buffers 4218f5860992SSakthivel K */ 4219f5860992SSakthivel K sg_req = &task->smp_task.smp_req; 4220f73bdebdSChristoph Hellwig elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); 4221f5860992SSakthivel K if (!elem) 4222f5860992SSakthivel K return -ENOMEM; 4223f5860992SSakthivel K req_len = sg_dma_len(sg_req); 4224f5860992SSakthivel K 4225f5860992SSakthivel K sg_resp = &task->smp_task.smp_resp; 4226f73bdebdSChristoph Hellwig elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); 4227f5860992SSakthivel K if (!elem) { 4228f5860992SSakthivel K rc = -ENOMEM; 4229f5860992SSakthivel K goto err_out; 4230f5860992SSakthivel K } 4231f5860992SSakthivel K resp_len = sg_dma_len(sg_resp); 4232f5860992SSakthivel K /* must be in dwords */ 4233f5860992SSakthivel K if ((req_len & 0x3) || (resp_len & 0x3)) { 4234f5860992SSakthivel K rc = -EINVAL; 4235f5860992SSakthivel K goto err_out_2; 4236f5860992SSakthivel K } 4237f5860992SSakthivel K 4238f5860992SSakthivel K opc = OPC_INB_SMP_REQUEST; 4239f5860992SSakthivel K smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 4240f5860992SSakthivel K 4241f5860992SSakthivel K length = sg_req->length; 42421b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length); 4243f5860992SSakthivel K if (!(length - 8)) 4244f5860992SSakthivel K pm8001_ha->smp_exp_mode = SMP_DIRECT; 4245f5860992SSakthivel K else 4246f5860992SSakthivel K pm8001_ha->smp_exp_mode = SMP_INDIRECT; 4247f5860992SSakthivel K 4248f5860992SSakthivel K 42492fe24343SJohn Garry smp_req = &task->smp_task.smp_req; 42502fe24343SJohn Garry to = kmap_atomic(sg_page(smp_req)); 42512fe24343SJohn Garry payload = to + smp_req->offset; 4252f5860992SSakthivel K 4253f5860992SSakthivel K /* INDIRECT MODE command settings. Use DMA */ 4254f5860992SSakthivel K if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { 42551b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n"); 4256f5860992SSakthivel K /* for SPCv indirect mode. Place the top 4 bytes of 4257f5860992SSakthivel K * SMP Request header here. */ 4258f5860992SSakthivel K for (i = 0; i < 4; i++) 42592fe24343SJohn Garry smp_cmd.smp_req16[i] = *(payload + i); 4260f5860992SSakthivel K /* exclude top 4 bytes for SMP req header */ 4261f5860992SSakthivel K smp_cmd.long_smp_req.long_req_addr = 4262f5860992SSakthivel K cpu_to_le64((u64)sg_dma_address 4263cb993e5dSAnand Kumar Santhanam (&task->smp_task.smp_req) + 4); 4264f5860992SSakthivel K /* exclude 4 bytes for SMP req header and CRC */ 4265f5860992SSakthivel K smp_cmd.long_smp_req.long_req_size = 4266f5860992SSakthivel K cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); 4267f5860992SSakthivel K smp_cmd.long_smp_req.long_resp_addr = 4268f5860992SSakthivel K cpu_to_le64((u64)sg_dma_address 4269f5860992SSakthivel K (&task->smp_task.smp_resp)); 4270f5860992SSakthivel K smp_cmd.long_smp_req.long_resp_size = 4271f5860992SSakthivel K cpu_to_le32((u32)sg_dma_len 4272f5860992SSakthivel K (&task->smp_task.smp_resp)-4); 4273f5860992SSakthivel K } else { /* DIRECT MODE */ 4274f5860992SSakthivel K smp_cmd.long_smp_req.long_req_addr = 4275f5860992SSakthivel K cpu_to_le64((u64)sg_dma_address 4276f5860992SSakthivel K (&task->smp_task.smp_req)); 4277f5860992SSakthivel K smp_cmd.long_smp_req.long_req_size = 4278f5860992SSakthivel K cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 4279f5860992SSakthivel K smp_cmd.long_smp_req.long_resp_addr = 4280f5860992SSakthivel K cpu_to_le64((u64)sg_dma_address 4281f5860992SSakthivel K (&task->smp_task.smp_resp)); 4282f5860992SSakthivel K smp_cmd.long_smp_req.long_resp_size = 4283f5860992SSakthivel K cpu_to_le32 4284f5860992SSakthivel K ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 4285f5860992SSakthivel K } 4286f5860992SSakthivel K if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 42871b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n"); 4288f5860992SSakthivel K for (i = 0; i < length; i++) 4289f5860992SSakthivel K if (i < 16) { 42902fe24343SJohn Garry smp_cmd.smp_req16[i] = *(payload + i); 42911b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 4292f5860992SSakthivel K "Byte[%d]:%x (DMA data:%x)\n", 4293f5860992SSakthivel K i, smp_cmd.smp_req16[i], 42942fe24343SJohn Garry *(payload)); 4295f5860992SSakthivel K } else { 42962fe24343SJohn Garry smp_cmd.smp_req[i] = *(payload + i); 42971b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 4298f5860992SSakthivel K "Byte[%d]:%x (DMA data:%x)\n", 4299f5860992SSakthivel K i, smp_cmd.smp_req[i], 43002fe24343SJohn Garry *(payload)); 4301f5860992SSakthivel K } 4302f5860992SSakthivel K } 43032fe24343SJohn Garry kunmap_atomic(to); 4304f5860992SSakthivel K build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, 4305f5860992SSakthivel K &smp_cmd, pm8001_ha->smp_exp_mode, length); 4306f91767a3SDamien Le Moal rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &smp_cmd, 430791a43fa6Speter chang sizeof(smp_cmd), 0); 43085533abcaSTomas Henzl if (rc) 43095533abcaSTomas Henzl goto err_out_2; 4310f5860992SSakthivel K return 0; 4311f5860992SSakthivel K 4312f5860992SSakthivel K err_out_2: 4313f5860992SSakthivel K dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 4314f73bdebdSChristoph Hellwig DMA_FROM_DEVICE); 4315f5860992SSakthivel K err_out: 4316f5860992SSakthivel K dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 4317f73bdebdSChristoph Hellwig DMA_TO_DEVICE); 4318f5860992SSakthivel K return rc; 4319f5860992SSakthivel K } 4320f5860992SSakthivel K 4321f5860992SSakthivel K static int check_enc_sas_cmd(struct sas_task *task) 4322f5860992SSakthivel K { 4323e73823f7SJames Bottomley u8 cmd = task->ssp_task.cmd->cmnd[0]; 4324e73823f7SJames Bottomley 4325e73823f7SJames Bottomley if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) 4326f5860992SSakthivel K return 1; 4327f5860992SSakthivel K else 4328f5860992SSakthivel K return 0; 4329f5860992SSakthivel K } 4330f5860992SSakthivel K 4331f5860992SSakthivel K static int check_enc_sat_cmd(struct sas_task *task) 4332f5860992SSakthivel K { 4333f5860992SSakthivel K int ret = 0; 4334f5860992SSakthivel K switch (task->ata_task.fis.command) { 4335f5860992SSakthivel K case ATA_CMD_FPDMA_READ: 4336f5860992SSakthivel K case ATA_CMD_READ_EXT: 4337f5860992SSakthivel K case ATA_CMD_READ: 4338f5860992SSakthivel K case ATA_CMD_FPDMA_WRITE: 4339f5860992SSakthivel K case ATA_CMD_WRITE_EXT: 4340f5860992SSakthivel K case ATA_CMD_WRITE: 4341f5860992SSakthivel K case ATA_CMD_PIO_READ: 4342f5860992SSakthivel K case ATA_CMD_PIO_READ_EXT: 4343f5860992SSakthivel K case ATA_CMD_PIO_WRITE: 4344f5860992SSakthivel K case ATA_CMD_PIO_WRITE_EXT: 4345f5860992SSakthivel K ret = 1; 4346f5860992SSakthivel K break; 4347f5860992SSakthivel K default: 4348f5860992SSakthivel K ret = 0; 4349f5860992SSakthivel K break; 4350f5860992SSakthivel K } 4351f5860992SSakthivel K return ret; 4352f5860992SSakthivel K } 4353f5860992SSakthivel K 4354*42f22fe3SJohn Garry static u32 pm80xx_chip_get_q_index(struct sas_task *task) 4355*42f22fe3SJohn Garry { 4356*42f22fe3SJohn Garry struct scsi_cmnd *scmd = NULL; 4357*42f22fe3SJohn Garry u32 blk_tag; 4358*42f22fe3SJohn Garry 4359*42f22fe3SJohn Garry if (task->uldd_task) { 4360*42f22fe3SJohn Garry struct ata_queued_cmd *qc; 4361*42f22fe3SJohn Garry 4362*42f22fe3SJohn Garry if (dev_is_sata(task->dev)) { 4363*42f22fe3SJohn Garry qc = task->uldd_task; 4364*42f22fe3SJohn Garry scmd = qc->scsicmd; 4365*42f22fe3SJohn Garry } else { 4366*42f22fe3SJohn Garry scmd = task->uldd_task; 4367*42f22fe3SJohn Garry } 4368*42f22fe3SJohn Garry } 4369*42f22fe3SJohn Garry 4370*42f22fe3SJohn Garry if (!scmd) 4371*42f22fe3SJohn Garry return 0; 4372*42f22fe3SJohn Garry 4373*42f22fe3SJohn Garry blk_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd)); 4374*42f22fe3SJohn Garry return blk_mq_unique_tag_to_hwq(blk_tag); 4375*42f22fe3SJohn Garry } 4376*42f22fe3SJohn Garry 4377f5860992SSakthivel K /** 4378bb6beabfSRandy Dunlap * pm80xx_chip_ssp_io_req - send an SSP task to FW 4379f5860992SSakthivel K * @pm8001_ha: our hba card information. 4380f5860992SSakthivel K * @ccb: the ccb information this request used. 4381f5860992SSakthivel K */ 4382f5860992SSakthivel K static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4383f5860992SSakthivel K struct pm8001_ccb_info *ccb) 4384f5860992SSakthivel K { 4385f5860992SSakthivel K struct sas_task *task = ccb->task; 4386f5860992SSakthivel K struct domain_device *dev = task->dev; 4387f5860992SSakthivel K struct pm8001_device *pm8001_dev = dev->lldd_dev; 4388f5860992SSakthivel K struct ssp_ini_io_start_req ssp_cmd; 4389f5860992SSakthivel K u32 tag = ccb->ccb_tag; 4390970404ccSDamien Le Moal u64 phys_addr, end_addr; 43910ecdf00bSAnand Kumar Santhanam u32 end_addr_high, end_addr_low; 4392*42f22fe3SJohn Garry u32 q_index; 4393f5860992SSakthivel K u32 opc = OPC_INB_SSPINIIOSTART; 4394970404ccSDamien Le Moal 4395f5860992SSakthivel K memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4396f5860992SSakthivel K memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4397970404ccSDamien Le Moal 4398f5860992SSakthivel K /* data address domain added for spcv; set to 0 by host, 4399f5860992SSakthivel K * used internally by controller 4400f5860992SSakthivel K * 0 for SAS 1.1 and SAS 2.0 compatible TLR 4401f5860992SSakthivel K */ 4402f5860992SSakthivel K ssp_cmd.dad_dir_m_tlr = 4403f5860992SSakthivel K cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); 4404f5860992SSakthivel K ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4405f5860992SSakthivel K ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4406f5860992SSakthivel K ssp_cmd.tag = cpu_to_le32(tag); 4407f5860992SSakthivel K if (task->ssp_task.enable_first_burst) 4408970404ccSDamien Le Moal ssp_cmd.ssp_iu.efb_prio_attr = 0x80; 4409f5860992SSakthivel K ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4410f5860992SSakthivel K ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4411e73823f7SJames Bottomley memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 4412e73823f7SJames Bottomley task->ssp_task.cmd->cmd_len); 4413*42f22fe3SJohn Garry q_index = pm80xx_chip_get_q_index(task); 4414f5860992SSakthivel K 4415f5860992SSakthivel K /* Check if encryption is set */ 4416f5860992SSakthivel K if (pm8001_ha->chip->encrypt && 4417f5860992SSakthivel K !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { 44181b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 4419f5860992SSakthivel K "Encryption enabled.Sending Encrypt SAS command 0x%x\n", 44201b5d2793SJoe Perches task->ssp_task.cmd->cmnd[0]); 4421f5860992SSakthivel K opc = OPC_INB_SSP_INI_DIF_ENC_IO; 4422f5860992SSakthivel K /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ 4423f5860992SSakthivel K ssp_cmd.dad_dir_m_tlr = cpu_to_le32 4424f5860992SSakthivel K ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); 4425f5860992SSakthivel K 4426f5860992SSakthivel K /* fill in PRD (scatter/gather) table, if any */ 4427f5860992SSakthivel K if (task->num_scatter > 1) { 4428f5860992SSakthivel K pm8001_chip_make_sg(task->scatter, 4429f5860992SSakthivel K ccb->n_elem, ccb->buf_prd); 44305a141315SViswas G phys_addr = ccb->ccb_dma_handle; 4431f5860992SSakthivel K ssp_cmd.enc_addr_low = 4432f5860992SSakthivel K cpu_to_le32(lower_32_bits(phys_addr)); 4433f5860992SSakthivel K ssp_cmd.enc_addr_high = 4434f5860992SSakthivel K cpu_to_le32(upper_32_bits(phys_addr)); 4435f5860992SSakthivel K ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 4436f5860992SSakthivel K } else if (task->num_scatter == 1) { 4437f5860992SSakthivel K u64 dma_addr = sg_dma_address(task->scatter); 4438970404ccSDamien Le Moal 4439f5860992SSakthivel K ssp_cmd.enc_addr_low = 4440f5860992SSakthivel K cpu_to_le32(lower_32_bits(dma_addr)); 4441f5860992SSakthivel K ssp_cmd.enc_addr_high = 4442f5860992SSakthivel K cpu_to_le32(upper_32_bits(dma_addr)); 4443f5860992SSakthivel K ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4444f5860992SSakthivel K ssp_cmd.enc_esgl = 0; 4445970404ccSDamien Le Moal 44460ecdf00bSAnand Kumar Santhanam /* Check 4G Boundary */ 4447970404ccSDamien Le Moal end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1; 4448970404ccSDamien Le Moal end_addr_low = lower_32_bits(end_addr); 4449970404ccSDamien Le Moal end_addr_high = upper_32_bits(end_addr); 4450970404ccSDamien Le Moal 4451970404ccSDamien Le Moal if (end_addr_high != le32_to_cpu(ssp_cmd.enc_addr_high)) { 44521b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 44531b5d2793SJoe Perches "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4454970404ccSDamien Le Moal dma_addr, 4455970404ccSDamien Le Moal le32_to_cpu(ssp_cmd.enc_len), 44561b5d2793SJoe Perches end_addr_high, end_addr_low); 44570ecdf00bSAnand Kumar Santhanam pm8001_chip_make_sg(task->scatter, 1, 44580ecdf00bSAnand Kumar Santhanam ccb->buf_prd); 44595a141315SViswas G phys_addr = ccb->ccb_dma_handle; 44600ecdf00bSAnand Kumar Santhanam ssp_cmd.enc_addr_low = 44610ecdf00bSAnand Kumar Santhanam cpu_to_le32(lower_32_bits(phys_addr)); 44620ecdf00bSAnand Kumar Santhanam ssp_cmd.enc_addr_high = 44630ecdf00bSAnand Kumar Santhanam cpu_to_le32(upper_32_bits(phys_addr)); 4464970404ccSDamien Le Moal ssp_cmd.enc_esgl = cpu_to_le32(1U<<31); 44650ecdf00bSAnand Kumar Santhanam } 4466f5860992SSakthivel K } else if (task->num_scatter == 0) { 4467f5860992SSakthivel K ssp_cmd.enc_addr_low = 0; 4468f5860992SSakthivel K ssp_cmd.enc_addr_high = 0; 4469f5860992SSakthivel K ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4470f5860992SSakthivel K ssp_cmd.enc_esgl = 0; 4471f5860992SSakthivel K } 4472970404ccSDamien Le Moal 4473f5860992SSakthivel K /* XTS mode. All other fields are 0 */ 4474970404ccSDamien Le Moal ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4); 4475970404ccSDamien Le Moal 4476f5860992SSakthivel K /* set tweak values. Should be the start lba */ 4477e73823f7SJames Bottomley ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | 4478e73823f7SJames Bottomley (task->ssp_task.cmd->cmnd[3] << 16) | 4479e73823f7SJames Bottomley (task->ssp_task.cmd->cmnd[4] << 8) | 4480e73823f7SJames Bottomley (task->ssp_task.cmd->cmnd[5])); 4481f5860992SSakthivel K } else { 44821b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 4483f5860992SSakthivel K "Sending Normal SAS command 0x%x inb q %x\n", 44841b5d2793SJoe Perches task->ssp_task.cmd->cmnd[0], q_index); 4485f5860992SSakthivel K /* fill in PRD (scatter/gather) table, if any */ 4486f5860992SSakthivel K if (task->num_scatter > 1) { 4487f5860992SSakthivel K pm8001_chip_make_sg(task->scatter, ccb->n_elem, 4488f5860992SSakthivel K ccb->buf_prd); 44895a141315SViswas G phys_addr = ccb->ccb_dma_handle; 4490f5860992SSakthivel K ssp_cmd.addr_low = 4491f5860992SSakthivel K cpu_to_le32(lower_32_bits(phys_addr)); 4492f5860992SSakthivel K ssp_cmd.addr_high = 4493f5860992SSakthivel K cpu_to_le32(upper_32_bits(phys_addr)); 4494f5860992SSakthivel K ssp_cmd.esgl = cpu_to_le32(1<<31); 4495f5860992SSakthivel K } else if (task->num_scatter == 1) { 4496f5860992SSakthivel K u64 dma_addr = sg_dma_address(task->scatter); 4497970404ccSDamien Le Moal 4498f5860992SSakthivel K ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4499f5860992SSakthivel K ssp_cmd.addr_high = 4500f5860992SSakthivel K cpu_to_le32(upper_32_bits(dma_addr)); 4501f5860992SSakthivel K ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4502f5860992SSakthivel K ssp_cmd.esgl = 0; 4503970404ccSDamien Le Moal 45040ecdf00bSAnand Kumar Santhanam /* Check 4G Boundary */ 4505970404ccSDamien Le Moal end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1; 4506970404ccSDamien Le Moal end_addr_low = lower_32_bits(end_addr); 4507970404ccSDamien Le Moal end_addr_high = upper_32_bits(end_addr); 4508970404ccSDamien Le Moal if (end_addr_high != le32_to_cpu(ssp_cmd.addr_high)) { 45091b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 45101b5d2793SJoe Perches "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4511970404ccSDamien Le Moal dma_addr, 4512970404ccSDamien Le Moal le32_to_cpu(ssp_cmd.len), 45131b5d2793SJoe Perches end_addr_high, end_addr_low); 45140ecdf00bSAnand Kumar Santhanam pm8001_chip_make_sg(task->scatter, 1, 45150ecdf00bSAnand Kumar Santhanam ccb->buf_prd); 45165a141315SViswas G phys_addr = ccb->ccb_dma_handle; 45170ecdf00bSAnand Kumar Santhanam ssp_cmd.addr_low = 45180ecdf00bSAnand Kumar Santhanam cpu_to_le32(lower_32_bits(phys_addr)); 45190ecdf00bSAnand Kumar Santhanam ssp_cmd.addr_high = 45200ecdf00bSAnand Kumar Santhanam cpu_to_le32(upper_32_bits(phys_addr)); 45210ecdf00bSAnand Kumar Santhanam ssp_cmd.esgl = cpu_to_le32(1<<31); 45220ecdf00bSAnand Kumar Santhanam } 4523f5860992SSakthivel K } else if (task->num_scatter == 0) { 4524f5860992SSakthivel K ssp_cmd.addr_low = 0; 4525f5860992SSakthivel K ssp_cmd.addr_high = 0; 4526f5860992SSakthivel K ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4527f5860992SSakthivel K ssp_cmd.esgl = 0; 4528f5860992SSakthivel K } 4529f5860992SSakthivel K } 4530f91767a3SDamien Le Moal 4531f91767a3SDamien Le Moal return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &ssp_cmd, 4532f91767a3SDamien Le Moal sizeof(ssp_cmd), q_index); 4533f5860992SSakthivel K } 4534f5860992SSakthivel K 4535f5860992SSakthivel K static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4536f5860992SSakthivel K struct pm8001_ccb_info *ccb) 4537f5860992SSakthivel K { 4538f5860992SSakthivel K struct sas_task *task = ccb->task; 4539f5860992SSakthivel K struct domain_device *dev = task->dev; 4540f5860992SSakthivel K struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 45418ceddda3SChangyuan Lyu struct ata_queued_cmd *qc = task->uldd_task; 4542*42f22fe3SJohn Garry u32 tag = ccb->ccb_tag, q_index; 4543f5860992SSakthivel K struct sata_start_req sata_cmd; 4544f5860992SSakthivel K u32 hdr_tag, ncg_tag = 0; 4545fd6d0e37SDamien Le Moal u64 phys_addr, end_addr; 45460ecdf00bSAnand Kumar Santhanam u32 end_addr_high, end_addr_low; 4547f5860992SSakthivel K u32 ATAP = 0x0; 4548f5860992SSakthivel K u32 dir; 4549c6b9ef57SSakthivel K unsigned long flags; 4550f5860992SSakthivel K u32 opc = OPC_INB_SATA_HOST_OPSTART; 4551f5860992SSakthivel K memset(&sata_cmd, 0, sizeof(sata_cmd)); 4552*42f22fe3SJohn Garry 4553*42f22fe3SJohn Garry q_index = pm80xx_chip_get_q_index(task); 4554f5860992SSakthivel K 4555aa028141SDamien Le Moal if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) { 4556f5860992SSakthivel K ATAP = 0x04; /* no data*/ 45571b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "no data\n"); 4558f5860992SSakthivel K } else if (likely(!task->ata_task.device_control_reg_update)) { 4559aa028141SDamien Le Moal if (task->ata_task.use_ncq && 4560aa028141SDamien Le Moal dev->sata_dev.class != ATA_DEV_ATAPI) { 4561aa028141SDamien Le Moal ATAP = 0x07; /* FPDMA */ 4562aa028141SDamien Le Moal pm8001_dbg(pm8001_ha, IO, "FPDMA\n"); 4563aa028141SDamien Le Moal } else if (task->ata_task.dma_xfer) { 4564f5860992SSakthivel K ATAP = 0x06; /* DMA */ 45651b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "DMA\n"); 4566f5860992SSakthivel K } else { 4567f5860992SSakthivel K ATAP = 0x05; /* PIO*/ 45681b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, "PIO\n"); 4569f5860992SSakthivel K } 4570f5860992SSakthivel K } 4571c6b9ef57SSakthivel K if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 4572c6b9ef57SSakthivel K task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 4573f5860992SSakthivel K ncg_tag = hdr_tag; 4574c6b9ef57SSakthivel K } 4575f5860992SSakthivel K dir = data_dir_flags[task->data_dir] << 8; 4576f5860992SSakthivel K sata_cmd.tag = cpu_to_le32(tag); 4577f5860992SSakthivel K sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4578f5860992SSakthivel K sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4579f5860992SSakthivel K 4580f5860992SSakthivel K sata_cmd.sata_fis = task->ata_task.fis; 4581f5860992SSakthivel K if (likely(!task->ata_task.device_control_reg_update)) 4582f5860992SSakthivel K sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4583f5860992SSakthivel K sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4584f5860992SSakthivel K 4585f5860992SSakthivel K /* Check if encryption is set */ 4586f5860992SSakthivel K if (pm8001_ha->chip->encrypt && 4587f5860992SSakthivel K !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { 45881b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 4589f5860992SSakthivel K "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", 45901b5d2793SJoe Perches sata_cmd.sata_fis.command); 4591f5860992SSakthivel K opc = OPC_INB_SATA_DIF_ENC_IO; 4592f5860992SSakthivel K 4593f5860992SSakthivel K /* set encryption bit */ 4594f5860992SSakthivel K sata_cmd.ncqtag_atap_dir_m_dad = 4595f5860992SSakthivel K cpu_to_le32(((ncg_tag & 0xff)<<16)| 4596f5860992SSakthivel K ((ATAP & 0x3f) << 10) | 0x20 | dir); 4597f5860992SSakthivel K /* dad (bit 0-1) is 0 */ 4598f5860992SSakthivel K /* fill in PRD (scatter/gather) table, if any */ 4599f5860992SSakthivel K if (task->num_scatter > 1) { 4600f5860992SSakthivel K pm8001_chip_make_sg(task->scatter, 4601f5860992SSakthivel K ccb->n_elem, ccb->buf_prd); 46025a141315SViswas G phys_addr = ccb->ccb_dma_handle; 4603fd6d0e37SDamien Le Moal sata_cmd.enc_addr_low = 4604fd6d0e37SDamien Le Moal cpu_to_le32(lower_32_bits(phys_addr)); 4605fd6d0e37SDamien Le Moal sata_cmd.enc_addr_high = 4606fd6d0e37SDamien Le Moal cpu_to_le32(upper_32_bits(phys_addr)); 4607f5860992SSakthivel K sata_cmd.enc_esgl = cpu_to_le32(1 << 31); 4608f5860992SSakthivel K } else if (task->num_scatter == 1) { 4609f5860992SSakthivel K u64 dma_addr = sg_dma_address(task->scatter); 4610fd6d0e37SDamien Le Moal 4611fd6d0e37SDamien Le Moal sata_cmd.enc_addr_low = 4612fd6d0e37SDamien Le Moal cpu_to_le32(lower_32_bits(dma_addr)); 4613fd6d0e37SDamien Le Moal sata_cmd.enc_addr_high = 4614fd6d0e37SDamien Le Moal cpu_to_le32(upper_32_bits(dma_addr)); 4615f5860992SSakthivel K sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4616f5860992SSakthivel K sata_cmd.enc_esgl = 0; 4617fd6d0e37SDamien Le Moal 46180ecdf00bSAnand Kumar Santhanam /* Check 4G Boundary */ 4619fd6d0e37SDamien Le Moal end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1; 4620fd6d0e37SDamien Le Moal end_addr_low = lower_32_bits(end_addr); 4621fd6d0e37SDamien Le Moal end_addr_high = upper_32_bits(end_addr); 4622fd6d0e37SDamien Le Moal if (end_addr_high != le32_to_cpu(sata_cmd.enc_addr_high)) { 46231b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 46241b5d2793SJoe Perches "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4625fd6d0e37SDamien Le Moal dma_addr, 4626fd6d0e37SDamien Le Moal le32_to_cpu(sata_cmd.enc_len), 46271b5d2793SJoe Perches end_addr_high, end_addr_low); 46280ecdf00bSAnand Kumar Santhanam pm8001_chip_make_sg(task->scatter, 1, 46290ecdf00bSAnand Kumar Santhanam ccb->buf_prd); 46305a141315SViswas G phys_addr = ccb->ccb_dma_handle; 46310ecdf00bSAnand Kumar Santhanam sata_cmd.enc_addr_low = 4632fd6d0e37SDamien Le Moal cpu_to_le32(lower_32_bits(phys_addr)); 46330ecdf00bSAnand Kumar Santhanam sata_cmd.enc_addr_high = 4634fd6d0e37SDamien Le Moal cpu_to_le32(upper_32_bits(phys_addr)); 46350ecdf00bSAnand Kumar Santhanam sata_cmd.enc_esgl = 46360ecdf00bSAnand Kumar Santhanam cpu_to_le32(1 << 31); 46370ecdf00bSAnand Kumar Santhanam } 4638f5860992SSakthivel K } else if (task->num_scatter == 0) { 4639f5860992SSakthivel K sata_cmd.enc_addr_low = 0; 4640f5860992SSakthivel K sata_cmd.enc_addr_high = 0; 4641f5860992SSakthivel K sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 4642f5860992SSakthivel K sata_cmd.enc_esgl = 0; 4643f5860992SSakthivel K } 4644f5860992SSakthivel K /* XTS mode. All other fields are 0 */ 4645fd6d0e37SDamien Le Moal sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4); 4646fd6d0e37SDamien Le Moal 4647f5860992SSakthivel K /* set tweak values. Should be the start lba */ 4648f5860992SSakthivel K sata_cmd.twk_val0 = 4649f5860992SSakthivel K cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | 4650f5860992SSakthivel K (sata_cmd.sata_fis.lbah << 16) | 4651f5860992SSakthivel K (sata_cmd.sata_fis.lbam << 8) | 4652f5860992SSakthivel K (sata_cmd.sata_fis.lbal)); 4653f5860992SSakthivel K sata_cmd.twk_val1 = 4654f5860992SSakthivel K cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | 4655f5860992SSakthivel K (sata_cmd.sata_fis.lbam_exp)); 4656f5860992SSakthivel K } else { 46571b5d2793SJoe Perches pm8001_dbg(pm8001_ha, IO, 4658f5860992SSakthivel K "Sending Normal SATA command 0x%x inb %x\n", 46591b5d2793SJoe Perches sata_cmd.sata_fis.command, q_index); 4660f5860992SSakthivel K /* dad (bit 0-1) is 0 */ 4661f5860992SSakthivel K sata_cmd.ncqtag_atap_dir_m_dad = 4662f5860992SSakthivel K cpu_to_le32(((ncg_tag & 0xff)<<16) | 4663f5860992SSakthivel K ((ATAP & 0x3f) << 10) | dir); 4664f5860992SSakthivel K 4665f5860992SSakthivel K /* fill in PRD (scatter/gather) table, if any */ 4666f5860992SSakthivel K if (task->num_scatter > 1) { 4667f5860992SSakthivel K pm8001_chip_make_sg(task->scatter, 4668f5860992SSakthivel K ccb->n_elem, ccb->buf_prd); 46695a141315SViswas G phys_addr = ccb->ccb_dma_handle; 4670f5860992SSakthivel K sata_cmd.addr_low = lower_32_bits(phys_addr); 4671f5860992SSakthivel K sata_cmd.addr_high = upper_32_bits(phys_addr); 4672fd6d0e37SDamien Le Moal sata_cmd.esgl = cpu_to_le32(1U << 31); 4673f5860992SSakthivel K } else if (task->num_scatter == 1) { 4674f5860992SSakthivel K u64 dma_addr = sg_dma_address(task->scatter); 4675fd6d0e37SDamien Le Moal 4676f5860992SSakthivel K sata_cmd.addr_low = lower_32_bits(dma_addr); 4677f5860992SSakthivel K sata_cmd.addr_high = upper_32_bits(dma_addr); 4678f5860992SSakthivel K sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4679f5860992SSakthivel K sata_cmd.esgl = 0; 4680fd6d0e37SDamien Le Moal 46810ecdf00bSAnand Kumar Santhanam /* Check 4G Boundary */ 4682fd6d0e37SDamien Le Moal end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1; 4683fd6d0e37SDamien Le Moal end_addr_low = lower_32_bits(end_addr); 4684fd6d0e37SDamien Le Moal end_addr_high = upper_32_bits(end_addr); 46850ecdf00bSAnand Kumar Santhanam if (end_addr_high != sata_cmd.addr_high) { 46861b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 46871b5d2793SJoe Perches "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n", 4688fd6d0e37SDamien Le Moal dma_addr, 4689fd6d0e37SDamien Le Moal le32_to_cpu(sata_cmd.len), 46901b5d2793SJoe Perches end_addr_high, end_addr_low); 46910ecdf00bSAnand Kumar Santhanam pm8001_chip_make_sg(task->scatter, 1, 46920ecdf00bSAnand Kumar Santhanam ccb->buf_prd); 46935a141315SViswas G phys_addr = ccb->ccb_dma_handle; 4694fd6d0e37SDamien Le Moal sata_cmd.addr_low = lower_32_bits(phys_addr); 4695fd6d0e37SDamien Le Moal sata_cmd.addr_high = upper_32_bits(phys_addr); 4696fd6d0e37SDamien Le Moal sata_cmd.esgl = cpu_to_le32(1U << 31); 46970ecdf00bSAnand Kumar Santhanam } 4698f5860992SSakthivel K } else if (task->num_scatter == 0) { 4699f5860992SSakthivel K sata_cmd.addr_low = 0; 4700f5860992SSakthivel K sata_cmd.addr_high = 0; 4701f5860992SSakthivel K sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4702f5860992SSakthivel K sata_cmd.esgl = 0; 4703f5860992SSakthivel K } 4704fd6d0e37SDamien Le Moal 4705f5860992SSakthivel K /* scsi cdb */ 4706f5860992SSakthivel K sata_cmd.atapi_scsi_cdb[0] = 4707f5860992SSakthivel K cpu_to_le32(((task->ata_task.atapi_packet[0]) | 4708f5860992SSakthivel K (task->ata_task.atapi_packet[1] << 8) | 4709f5860992SSakthivel K (task->ata_task.atapi_packet[2] << 16) | 4710f5860992SSakthivel K (task->ata_task.atapi_packet[3] << 24))); 4711f5860992SSakthivel K sata_cmd.atapi_scsi_cdb[1] = 4712f5860992SSakthivel K cpu_to_le32(((task->ata_task.atapi_packet[4]) | 4713f5860992SSakthivel K (task->ata_task.atapi_packet[5] << 8) | 4714f5860992SSakthivel K (task->ata_task.atapi_packet[6] << 16) | 4715f5860992SSakthivel K (task->ata_task.atapi_packet[7] << 24))); 4716f5860992SSakthivel K sata_cmd.atapi_scsi_cdb[2] = 4717f5860992SSakthivel K cpu_to_le32(((task->ata_task.atapi_packet[8]) | 4718f5860992SSakthivel K (task->ata_task.atapi_packet[9] << 8) | 4719f5860992SSakthivel K (task->ata_task.atapi_packet[10] << 16) | 4720f5860992SSakthivel K (task->ata_task.atapi_packet[11] << 24))); 4721f5860992SSakthivel K sata_cmd.atapi_scsi_cdb[3] = 4722f5860992SSakthivel K cpu_to_le32(((task->ata_task.atapi_packet[12]) | 4723f5860992SSakthivel K (task->ata_task.atapi_packet[13] << 8) | 4724f5860992SSakthivel K (task->ata_task.atapi_packet[14] << 16) | 4725f5860992SSakthivel K (task->ata_task.atapi_packet[15] << 24))); 4726f5860992SSakthivel K } 4727c6b9ef57SSakthivel K 4728c6b9ef57SSakthivel K /* Check for read log for failed drive and return */ 4729c6b9ef57SSakthivel K if (sata_cmd.sata_fis.command == 0x2f) { 4730c6b9ef57SSakthivel K if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4731c6b9ef57SSakthivel K (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4732c6b9ef57SSakthivel K (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4733c6b9ef57SSakthivel K struct task_status_struct *ts; 4734c6b9ef57SSakthivel K 4735c6b9ef57SSakthivel K pm8001_ha_dev->id &= 0xDFFFFFFF; 4736c6b9ef57SSakthivel K ts = &task->task_status; 4737c6b9ef57SSakthivel K 4738c6b9ef57SSakthivel K spin_lock_irqsave(&task->task_state_lock, flags); 4739c6b9ef57SSakthivel K ts->resp = SAS_TASK_COMPLETE; 4740d377f415SBart Van Assche ts->stat = SAS_SAM_STAT_GOOD; 4741c6b9ef57SSakthivel K task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4742c6b9ef57SSakthivel K task->task_state_flags |= SAS_TASK_STATE_DONE; 4743c6b9ef57SSakthivel K if (unlikely((task->task_state_flags & 4744c6b9ef57SSakthivel K SAS_TASK_STATE_ABORTED))) { 4745c6b9ef57SSakthivel K spin_unlock_irqrestore(&task->task_state_lock, 4746c6b9ef57SSakthivel K flags); 47471b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, 47481b5d2793SJoe Perches "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n", 47491b5d2793SJoe Perches task, ts->resp, 47501b5d2793SJoe Perches ts->stat); 4751304fe11bSDamien Le Moal pm8001_ccb_task_free(pm8001_ha, ccb); 4752c6b9ef57SSakthivel K return 0; 47532b01d816SSuresh Thiagarajan } else { 4754c6b9ef57SSakthivel K spin_unlock_irqrestore(&task->task_state_lock, 4755c6b9ef57SSakthivel K flags); 4756304fe11bSDamien Le Moal pm8001_ccb_task_free_done(pm8001_ha, ccb); 47574a2efd4bSViswas G atomic_dec(&pm8001_ha_dev->running_req); 4758c6b9ef57SSakthivel K return 0; 4759c6b9ef57SSakthivel K } 4760c6b9ef57SSakthivel K } 4761c6b9ef57SSakthivel K } 47628ceddda3SChangyuan Lyu trace_pm80xx_request_issue(pm8001_ha->id, 47638ceddda3SChangyuan Lyu ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS, 47648ceddda3SChangyuan Lyu ccb->ccb_tag, opc, 47658ceddda3SChangyuan Lyu qc ? qc->tf.command : 0, // ata opcode 47668ceddda3SChangyuan Lyu ccb->device ? atomic_read(&ccb->device->running_req) : 0); 4767f91767a3SDamien Le Moal return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &sata_cmd, 4768f91767a3SDamien Le Moal sizeof(sata_cmd), q_index); 4769f5860992SSakthivel K } 4770f5860992SSakthivel K 4771f5860992SSakthivel K /** 4772f5860992SSakthivel K * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND 4773f5860992SSakthivel K * @pm8001_ha: our hba card information. 4774f5860992SSakthivel K * @phy_id: the phy id which we wanted to start up. 4775f5860992SSakthivel K */ 4776f5860992SSakthivel K static int 4777f5860992SSakthivel K pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4778f5860992SSakthivel K { 4779f5860992SSakthivel K struct phy_start_req payload; 4780f5860992SSakthivel K u32 tag = 0x01; 4781f5860992SSakthivel K u32 opcode = OPC_INB_PHYSTART; 4782f91767a3SDamien Le Moal 4783f5860992SSakthivel K memset(&payload, 0, sizeof(payload)); 4784f5860992SSakthivel K payload.tag = cpu_to_le32(tag); 4785f5860992SSakthivel K 47861b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id); 4787a9a923e5SAnand Kumar Santhanam 47883e253d96Speter chang payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 47893e253d96Speter chang LINKMODE_AUTO | pm8001_ha->link_rate | phy_id); 4790f5860992SSakthivel K /* SSC Disable and SAS Analog ST configuration */ 4791bb6beabfSRandy Dunlap /* 4792f5860992SSakthivel K payload.ase_sh_lm_slr_phyid = 4793f5860992SSakthivel K cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | 4794f5860992SSakthivel K LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | 4795f5860992SSakthivel K phy_id); 4796f5860992SSakthivel K Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need 4797bb6beabfSRandy Dunlap */ 4798f5860992SSakthivel K 4799aa9f8328SJames Bottomley payload.sas_identify.dev_type = SAS_END_DEVICE; 4800f5860992SSakthivel K payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4801f5860992SSakthivel K memcpy(payload.sas_identify.sas_addr, 48023e253d96Speter chang &pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4803f5860992SSakthivel K payload.sas_identify.phy_id = phy_id; 4804f91767a3SDamien Le Moal 4805f91767a3SDamien Le Moal return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, 480691a43fa6Speter chang sizeof(payload), 0); 4807f5860992SSakthivel K } 4808f5860992SSakthivel K 4809f5860992SSakthivel K /** 48107cdaf12eSLee Jones * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4811f5860992SSakthivel K * @pm8001_ha: our hba card information. 4812f5860992SSakthivel K * @phy_id: the phy id which we wanted to start up. 4813f5860992SSakthivel K */ 4814f5860992SSakthivel K static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4815f5860992SSakthivel K u8 phy_id) 4816f5860992SSakthivel K { 4817f5860992SSakthivel K struct phy_stop_req payload; 4818f5860992SSakthivel K u32 tag = 0x01; 4819f5860992SSakthivel K u32 opcode = OPC_INB_PHYSTOP; 4820f91767a3SDamien Le Moal 4821f5860992SSakthivel K memset(&payload, 0, sizeof(payload)); 4822f5860992SSakthivel K payload.tag = cpu_to_le32(tag); 4823f5860992SSakthivel K payload.phy_id = cpu_to_le32(phy_id); 4824f91767a3SDamien Le Moal 4825f91767a3SDamien Le Moal return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, 482691a43fa6Speter chang sizeof(payload), 0); 4827f5860992SSakthivel K } 4828f5860992SSakthivel K 48296ad4a517SLee Jones /* 4830f5860992SSakthivel K * see comments on pm8001_mpi_reg_resp. 4831f5860992SSakthivel K */ 4832f5860992SSakthivel K static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4833f5860992SSakthivel K struct pm8001_device *pm8001_dev, u32 flag) 4834f5860992SSakthivel K { 4835f5860992SSakthivel K struct reg_dev_req payload; 4836f5860992SSakthivel K u32 opc; 4837f5860992SSakthivel K u32 stp_sspsmp_sata = 0x4; 4838f5860992SSakthivel K u32 linkrate, phy_id; 483999df0edbSDamien Le Moal int rc; 4840f5860992SSakthivel K struct pm8001_ccb_info *ccb; 4841f5860992SSakthivel K u8 retryFlag = 0x1; 4842f5860992SSakthivel K u16 firstBurstSize = 0; 4843f5860992SSakthivel K u16 ITNT = 2000; 4844f5860992SSakthivel K struct domain_device *dev = pm8001_dev->sas_device; 4845f5860992SSakthivel K struct domain_device *parent_dev = dev->parent; 484608d0a992SAjish Koshy struct pm8001_port *port = dev->port->lldd_port; 4847f5860992SSakthivel K 4848f5860992SSakthivel K memset(&payload, 0, sizeof(payload)); 484999df0edbSDamien Le Moal ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL); 485099df0edbSDamien Le Moal if (!ccb) 485199df0edbSDamien Le Moal return -SAS_QUEUE_FULL; 485299df0edbSDamien Le Moal 485399df0edbSDamien Le Moal payload.tag = cpu_to_le32(ccb->ccb_tag); 4854f5860992SSakthivel K 4855f5860992SSakthivel K if (flag == 1) { 4856f5860992SSakthivel K stp_sspsmp_sata = 0x02; /*direct attached sata */ 4857f5860992SSakthivel K } else { 4858aa9f8328SJames Bottomley if (pm8001_dev->dev_type == SAS_SATA_DEV) 4859f5860992SSakthivel K stp_sspsmp_sata = 0x00; /* stp*/ 4860aa9f8328SJames Bottomley else if (pm8001_dev->dev_type == SAS_END_DEVICE || 48614f632918SIgor Pylypiv dev_is_expander(pm8001_dev->dev_type)) 4862f5860992SSakthivel K stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4863f5860992SSakthivel K } 4864924a3541SJohn Garry if (parent_dev && dev_is_expander(parent_dev->dev_type)) 4865f5860992SSakthivel K phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4866f5860992SSakthivel K else 4867f5860992SSakthivel K phy_id = pm8001_dev->attached_phy; 4868f5860992SSakthivel K 4869f5860992SSakthivel K opc = OPC_INB_REG_DEV; 4870f5860992SSakthivel K 4871f5860992SSakthivel K linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4872f5860992SSakthivel K pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4873f5860992SSakthivel K 4874f5860992SSakthivel K payload.phyid_portid = 487508d0a992SAjish Koshy cpu_to_le32(((port->port_id) & 0xFF) | 4876f5860992SSakthivel K ((phy_id & 0xFF) << 8)); 4877f5860992SSakthivel K 4878f5860992SSakthivel K payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | 4879f5860992SSakthivel K ((linkrate & 0x0F) << 24) | 4880f5860992SSakthivel K ((stp_sspsmp_sata & 0x03) << 28)); 4881f5860992SSakthivel K payload.firstburstsize_ITNexustimeout = 4882f5860992SSakthivel K cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4883f5860992SSakthivel K 4884f5860992SSakthivel K memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4885f5860992SSakthivel K SAS_ADDR_SIZE); 4886f5860992SSakthivel K 4887f91767a3SDamien Le Moal rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 488891a43fa6Speter chang sizeof(payload), 0); 48895533abcaSTomas Henzl if (rc) 489099df0edbSDamien Le Moal pm8001_ccb_free(pm8001_ha, ccb); 4891f5860992SSakthivel K 4892f5860992SSakthivel K return rc; 4893f5860992SSakthivel K } 4894f5860992SSakthivel K 4895f5860992SSakthivel K /** 4896f5860992SSakthivel K * pm80xx_chip_phy_ctl_req - support the local phy operation 4897f5860992SSakthivel K * @pm8001_ha: our hba card information. 48986ad4a517SLee Jones * @phyId: the phy id which we wanted to operate 48996ad4a517SLee Jones * @phy_op: phy operation to request 4900f5860992SSakthivel K */ 4901f5860992SSakthivel K static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4902f5860992SSakthivel K u32 phyId, u32 phy_op) 4903f5860992SSakthivel K { 490425c6edbdSViswas G u32 tag; 490525c6edbdSViswas G int rc; 4906f5860992SSakthivel K struct local_phy_ctl_req payload; 4907f5860992SSakthivel K u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4908f91767a3SDamien Le Moal 4909f5860992SSakthivel K memset(&payload, 0, sizeof(payload)); 491025c6edbdSViswas G rc = pm8001_tag_alloc(pm8001_ha, &tag); 491125c6edbdSViswas G if (rc) 491225c6edbdSViswas G return rc; 4913f91767a3SDamien Le Moal 491425c6edbdSViswas G payload.tag = cpu_to_le32(tag); 4915f5860992SSakthivel K payload.phyop_phyid = 4916f5860992SSakthivel K cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); 49174c8f04b1SDamien Le Moal 4918f91767a3SDamien Le Moal rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 491991a43fa6Speter chang sizeof(payload), 0); 49204c8f04b1SDamien Le Moal if (rc) 49214c8f04b1SDamien Le Moal pm8001_tag_free(pm8001_ha, tag); 49224c8f04b1SDamien Le Moal 49234c8f04b1SDamien Le Moal return rc; 4924f5860992SSakthivel K } 4925f5860992SSakthivel K 4926f310a4eaSColin Ian King static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) 4927f5860992SSakthivel K { 4928f5860992SSakthivel K #ifdef PM8001_USE_MSIX 4929f5860992SSakthivel K return 1; 4930292c04ccSColin Ian King #else 4931292c04ccSColin Ian King u32 value; 4932292c04ccSColin Ian King 4933f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4934f5860992SSakthivel K if (value) 4935f5860992SSakthivel K return 1; 4936f5860992SSakthivel K return 0; 4937292c04ccSColin Ian King #endif 4938f5860992SSakthivel K } 4939f5860992SSakthivel K 4940f5860992SSakthivel K /** 49417cdaf12eSLee Jones * pm80xx_chip_isr - PM8001 isr handler. 4942f5860992SSakthivel K * @pm8001_ha: our hba card information. 49436ad4a517SLee Jones * @vec: irq number. 4944f5860992SSakthivel K */ 4945f5860992SSakthivel K static irqreturn_t 4946f5860992SSakthivel K pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4947f5860992SSakthivel K { 4948f5860992SSakthivel K pm80xx_chip_interrupt_disable(pm8001_ha, vec); 49491b5d2793SJoe Perches pm8001_dbg(pm8001_ha, DEVIO, 49507370672dSpeter chang "irq vec %d, ODMR:0x%x\n", 49511b5d2793SJoe Perches vec, pm8001_cr32(pm8001_ha, 0, 0x30)); 4952f5860992SSakthivel K process_oq(pm8001_ha, vec); 4953f5860992SSakthivel K pm80xx_chip_interrupt_enable(pm8001_ha, vec); 4954f5860992SSakthivel K return IRQ_HANDLED; 4955f5860992SSakthivel K } 4956f5860992SSakthivel K 4957ea310f57SLee Jones static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha, 4958ea310f57SLee Jones u32 operation, u32 phyid, 4959ea310f57SLee Jones u32 length, u32 *buf) 496027909407SAnand Kumar Santhanam { 496127909407SAnand Kumar Santhanam u32 tag, i, j = 0; 496227909407SAnand Kumar Santhanam int rc; 496327909407SAnand Kumar Santhanam struct set_phy_profile_req payload; 496427909407SAnand Kumar Santhanam u32 opc = OPC_INB_SET_PHY_PROFILE; 496527909407SAnand Kumar Santhanam 496627909407SAnand Kumar Santhanam memset(&payload, 0, sizeof(payload)); 496727909407SAnand Kumar Santhanam rc = pm8001_tag_alloc(pm8001_ha, &tag); 4968f17c599aSDamien Le Moal if (rc) { 49691b5d2793SJoe Perches pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n"); 4970f17c599aSDamien Le Moal return; 4971f17c599aSDamien Le Moal } 4972f17c599aSDamien Le Moal 497327909407SAnand Kumar Santhanam payload.tag = cpu_to_le32(tag); 4974e5039a92SDamien Le Moal payload.ppc_phyid = 4975e5039a92SDamien Le Moal cpu_to_le32(((operation & 0xF) << 8) | (phyid & 0xFF)); 49761b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, 49771b5d2793SJoe Perches " phy profile command for phy %x ,length is %d\n", 4978e5039a92SDamien Le Moal le32_to_cpu(payload.ppc_phyid), length); 497927909407SAnand Kumar Santhanam for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { 498027909407SAnand Kumar Santhanam payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i)); 498127909407SAnand Kumar Santhanam j++; 498227909407SAnand Kumar Santhanam } 4983f91767a3SDamien Le Moal rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 498491a43fa6Speter chang sizeof(payload), 0); 49855533abcaSTomas Henzl if (rc) 49865533abcaSTomas Henzl pm8001_tag_free(pm8001_ha, tag); 498727909407SAnand Kumar Santhanam } 498827909407SAnand Kumar Santhanam 498927909407SAnand Kumar Santhanam void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, 499027909407SAnand Kumar Santhanam u32 length, u8 *buf) 499127909407SAnand Kumar Santhanam { 4992fdd0a66bSYueHaibing u32 i; 499327909407SAnand Kumar Santhanam 499427909407SAnand Kumar Santhanam for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 499527909407SAnand Kumar Santhanam mpi_set_phy_profile_req(pm8001_ha, 499627909407SAnand Kumar Santhanam SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf); 499727909407SAnand Kumar Santhanam length = length + PHY_DWORD_LENGTH; 499827909407SAnand Kumar Santhanam } 49991b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n"); 500027909407SAnand Kumar Santhanam } 5001c5614df7SBenjamin Rood 5002c5614df7SBenjamin Rood void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, 5003c5614df7SBenjamin Rood u32 phy, u32 length, u32 *buf) 5004c5614df7SBenjamin Rood { 5005c5614df7SBenjamin Rood u32 tag, opc; 5006c5614df7SBenjamin Rood int rc, i; 5007c5614df7SBenjamin Rood struct set_phy_profile_req payload; 5008c5614df7SBenjamin Rood 5009c5614df7SBenjamin Rood memset(&payload, 0, sizeof(payload)); 5010c5614df7SBenjamin Rood 5011c5614df7SBenjamin Rood rc = pm8001_tag_alloc(pm8001_ha, &tag); 5012f17c599aSDamien Le Moal if (rc) { 50131b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n"); 5014f17c599aSDamien Le Moal return; 5015f17c599aSDamien Le Moal } 5016c5614df7SBenjamin Rood 5017c5614df7SBenjamin Rood opc = OPC_INB_SET_PHY_PROFILE; 5018c5614df7SBenjamin Rood 5019c5614df7SBenjamin Rood payload.tag = cpu_to_le32(tag); 5020e5039a92SDamien Le Moal payload.ppc_phyid = 5021e5039a92SDamien Le Moal cpu_to_le32(((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8) 5022c5614df7SBenjamin Rood | (phy & 0xFF)); 5023c5614df7SBenjamin Rood 5024c5614df7SBenjamin Rood for (i = 0; i < length; i++) 5025c5614df7SBenjamin Rood payload.reserved[i] = cpu_to_le32(*(buf + i)); 5026c5614df7SBenjamin Rood 5027f91767a3SDamien Le Moal rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, 502891a43fa6Speter chang sizeof(payload), 0); 5029c5614df7SBenjamin Rood if (rc) 5030c5614df7SBenjamin Rood pm8001_tag_free(pm8001_ha, tag); 5031c5614df7SBenjamin Rood 50321b5d2793SJoe Perches pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy); 5033c5614df7SBenjamin Rood } 5034f5860992SSakthivel K const struct pm8001_dispatch pm8001_80xx_dispatch = { 5035f5860992SSakthivel K .name = "pmc80xx", 5036f5860992SSakthivel K .chip_init = pm80xx_chip_init, 503798132d84SJohn Garry .chip_post_init = pm80xx_chip_post_init, 5038f5860992SSakthivel K .chip_soft_rst = pm80xx_chip_soft_rst, 5039f5860992SSakthivel K .chip_rst = pm80xx_hw_chip_rst, 5040f5860992SSakthivel K .chip_iounmap = pm8001_chip_iounmap, 5041f5860992SSakthivel K .isr = pm80xx_chip_isr, 5042f310a4eaSColin Ian King .is_our_interrupt = pm80xx_chip_is_our_interrupt, 5043f5860992SSakthivel K .isr_process_oq = process_oq, 5044f5860992SSakthivel K .interrupt_enable = pm80xx_chip_interrupt_enable, 5045f5860992SSakthivel K .interrupt_disable = pm80xx_chip_interrupt_disable, 5046f5860992SSakthivel K .make_prd = pm8001_chip_make_sg, 5047f5860992SSakthivel K .smp_req = pm80xx_chip_smp_req, 5048f5860992SSakthivel K .ssp_io_req = pm80xx_chip_ssp_io_req, 5049f5860992SSakthivel K .sata_req = pm80xx_chip_sata_req, 5050f5860992SSakthivel K .phy_start_req = pm80xx_chip_phy_start_req, 5051f5860992SSakthivel K .phy_stop_req = pm80xx_chip_phy_stop_req, 5052f5860992SSakthivel K .reg_dev_req = pm80xx_chip_reg_dev_req, 5053f5860992SSakthivel K .dereg_dev_req = pm8001_chip_dereg_dev_req, 5054f5860992SSakthivel K .phy_ctl_req = pm80xx_chip_phy_ctl_req, 5055f5860992SSakthivel K .task_abort = pm8001_chip_abort_task, 5056f5860992SSakthivel K .ssp_tm_req = pm8001_chip_ssp_tm_req, 5057f5860992SSakthivel K .get_nvmd_req = pm8001_chip_get_nvmd_req, 5058f5860992SSakthivel K .set_nvmd_req = pm8001_chip_set_nvmd_req, 5059f5860992SSakthivel K .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 5060f5860992SSakthivel K .set_dev_state_req = pm8001_chip_set_dev_state_req, 5061a961ea0aSakshatzen .fatal_errors = pm80xx_fatal_errors, 5062ee05cb71SAjish Koshy .hw_event_ack_req = pm80xx_hw_event_ack_req, 5063f5860992SSakthivel K }; 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