1f5860992SSakthivel K /* 2f5860992SSakthivel K * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver 3f5860992SSakthivel K * 4f5860992SSakthivel K * Copyright (c) 2008-2009 PMC-Sierra, Inc., 5f5860992SSakthivel K * All rights reserved. 6f5860992SSakthivel K * 7f5860992SSakthivel K * Redistribution and use in source and binary forms, with or without 8f5860992SSakthivel K * modification, are permitted provided that the following conditions 9f5860992SSakthivel K * are met: 10f5860992SSakthivel K * 1. Redistributions of source code must retain the above copyright 11f5860992SSakthivel K * notice, this list of conditions, and the following disclaimer, 12f5860992SSakthivel K * without modification. 13f5860992SSakthivel K * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14f5860992SSakthivel K * substantially similar to the "NO WARRANTY" disclaimer below 15f5860992SSakthivel K * ("Disclaimer") and any redistribution must be conditioned upon 16f5860992SSakthivel K * including a substantially similar Disclaimer requirement for further 17f5860992SSakthivel K * binary redistribution. 18f5860992SSakthivel K * 3. Neither the names of the above-listed copyright holders nor the names 19f5860992SSakthivel K * of any contributors may be used to endorse or promote products derived 20f5860992SSakthivel K * from this software without specific prior written permission. 21f5860992SSakthivel K * 22f5860992SSakthivel K * Alternatively, this software may be distributed under the terms of the 23f5860992SSakthivel K * GNU General Public License ("GPL") version 2 as published by the Free 24f5860992SSakthivel K * Software Foundation. 25f5860992SSakthivel K * 26f5860992SSakthivel K * NO WARRANTY 27f5860992SSakthivel K * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28f5860992SSakthivel K * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29f5860992SSakthivel K * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30f5860992SSakthivel K * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31f5860992SSakthivel K * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32f5860992SSakthivel K * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33f5860992SSakthivel K * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34f5860992SSakthivel K * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35f5860992SSakthivel K * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36f5860992SSakthivel K * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37f5860992SSakthivel K * POSSIBILITY OF SUCH DAMAGES. 38f5860992SSakthivel K * 39f5860992SSakthivel K */ 40f5860992SSakthivel K #include <linux/slab.h> 41f5860992SSakthivel K #include "pm8001_sas.h" 42f5860992SSakthivel K #include "pm80xx_hwi.h" 43f5860992SSakthivel K #include "pm8001_chips.h" 44f5860992SSakthivel K #include "pm8001_ctl.h" 45f5860992SSakthivel K 46f5860992SSakthivel K #define SMP_DIRECT 1 47f5860992SSakthivel K #define SMP_INDIRECT 2 48f5860992SSakthivel K /** 49f5860992SSakthivel K * read_main_config_table - read the configure table and save it. 50f5860992SSakthivel K * @pm8001_ha: our hba card information 51f5860992SSakthivel K */ 52f5860992SSakthivel K static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) 53f5860992SSakthivel K { 54f5860992SSakthivel K void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 55f5860992SSakthivel K 56f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = 57f5860992SSakthivel K pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); 58f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = 59f5860992SSakthivel K pm8001_mr32(address, MAIN_INTERFACE_REVISION); 60f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = 61f5860992SSakthivel K pm8001_mr32(address, MAIN_FW_REVISION); 62f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = 63f5860992SSakthivel K pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); 64f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = 65f5860992SSakthivel K pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); 66f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = 67f5860992SSakthivel K pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); 68f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = 69f5860992SSakthivel K pm8001_mr32(address, MAIN_GST_OFFSET); 70f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = 71f5860992SSakthivel K pm8001_mr32(address, MAIN_IBQ_OFFSET); 72f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = 73f5860992SSakthivel K pm8001_mr32(address, MAIN_OBQ_OFFSET); 74f5860992SSakthivel K 75f5860992SSakthivel K /* read Error Dump Offset and Length */ 76f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = 77f5860992SSakthivel K pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 78f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = 79f5860992SSakthivel K pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 80f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = 81f5860992SSakthivel K pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 82f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = 83f5860992SSakthivel K pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 84f5860992SSakthivel K 85f5860992SSakthivel K /* read GPIO LED settings from the configuration table */ 86f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = 87f5860992SSakthivel K pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); 88f5860992SSakthivel K 89f5860992SSakthivel K /* read analog Setting offset from the configuration table */ 90f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = 91f5860992SSakthivel K pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 92f5860992SSakthivel K 93f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = 94f5860992SSakthivel K pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); 95f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = 96f5860992SSakthivel K pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); 97f5860992SSakthivel K } 98f5860992SSakthivel K 99f5860992SSakthivel K /** 100f5860992SSakthivel K * read_general_status_table - read the general status table and save it. 101f5860992SSakthivel K * @pm8001_ha: our hba card information 102f5860992SSakthivel K */ 103f5860992SSakthivel K static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) 104f5860992SSakthivel K { 105f5860992SSakthivel K void __iomem *address = pm8001_ha->general_stat_tbl_addr; 106f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = 107f5860992SSakthivel K pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); 108f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = 109f5860992SSakthivel K pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); 110f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = 111f5860992SSakthivel K pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); 112f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = 113f5860992SSakthivel K pm8001_mr32(address, GST_MSGUTCNT_OFFSET); 114f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = 115f5860992SSakthivel K pm8001_mr32(address, GST_IOPTCNT_OFFSET); 116f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = 117f5860992SSakthivel K pm8001_mr32(address, GST_GPIO_INPUT_VAL); 118f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = 119f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET0); 120f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = 121f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET1); 122f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = 123f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET2); 124f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = 125f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET3); 126f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = 127f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET4); 128f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = 129f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET5); 130f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = 131f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET6); 132f5860992SSakthivel K pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = 133f5860992SSakthivel K pm8001_mr32(address, GST_RERRINFO_OFFSET7); 134f5860992SSakthivel K } 135f5860992SSakthivel K /** 136f5860992SSakthivel K * read_phy_attr_table - read the phy attribute table and save it. 137f5860992SSakthivel K * @pm8001_ha: our hba card information 138f5860992SSakthivel K */ 139f5860992SSakthivel K static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) 140f5860992SSakthivel K { 141f5860992SSakthivel K void __iomem *address = pm8001_ha->pspa_q_tbl_addr; 142f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[0] = 143f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); 144f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[1] = 145f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); 146f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[2] = 147f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); 148f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[3] = 149f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); 150f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[4] = 151f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); 152f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[5] = 153f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); 154f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[6] = 155f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); 156f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[7] = 157f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); 158f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[8] = 159f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); 160f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[9] = 161f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); 162f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[10] = 163f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); 164f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[11] = 165f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); 166f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[12] = 167f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); 168f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[13] = 169f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); 170f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[14] = 171f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); 172f5860992SSakthivel K pm8001_ha->phy_attr_table.phystart1_16[15] = 173f5860992SSakthivel K pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); 174f5860992SSakthivel K 175f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = 176f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); 177f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = 178f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); 179f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = 180f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); 181f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = 182f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); 183f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = 184f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); 185f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = 186f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); 187f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = 188f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); 189f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = 190f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); 191f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = 192f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); 193f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = 194f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); 195f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = 196f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); 197f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = 198f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); 199f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = 200f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); 201f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = 202f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); 203f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = 204f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); 205f5860992SSakthivel K pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = 206f5860992SSakthivel K pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); 207f5860992SSakthivel K 208f5860992SSakthivel K } 209f5860992SSakthivel K 210f5860992SSakthivel K /** 211f5860992SSakthivel K * read_inbnd_queue_table - read the inbound queue table and save it. 212f5860992SSakthivel K * @pm8001_ha: our hba card information 213f5860992SSakthivel K */ 214f5860992SSakthivel K static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 215f5860992SSakthivel K { 216f5860992SSakthivel K int i; 217f5860992SSakthivel K void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 218f5860992SSakthivel K for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 219f5860992SSakthivel K u32 offset = i * 0x20; 220f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 221f5860992SSakthivel K get_pci_bar_index(pm8001_mr32(address, 222f5860992SSakthivel K (offset + IB_PIPCI_BAR))); 223f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].pi_offset = 224f5860992SSakthivel K pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); 225f5860992SSakthivel K } 226f5860992SSakthivel K } 227f5860992SSakthivel K 228f5860992SSakthivel K /** 229f5860992SSakthivel K * read_outbnd_queue_table - read the outbound queue table and save it. 230f5860992SSakthivel K * @pm8001_ha: our hba card information 231f5860992SSakthivel K */ 232f5860992SSakthivel K static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 233f5860992SSakthivel K { 234f5860992SSakthivel K int i; 235f5860992SSakthivel K void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 236f5860992SSakthivel K for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 237f5860992SSakthivel K u32 offset = i * 0x24; 238f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 239f5860992SSakthivel K get_pci_bar_index(pm8001_mr32(address, 240f5860992SSakthivel K (offset + OB_CIPCI_BAR))); 241f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].ci_offset = 242f5860992SSakthivel K pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); 243f5860992SSakthivel K } 244f5860992SSakthivel K } 245f5860992SSakthivel K 246f5860992SSakthivel K /** 247f5860992SSakthivel K * init_default_table_values - init the default table. 248f5860992SSakthivel K * @pm8001_ha: our hba card information 249f5860992SSakthivel K */ 250f5860992SSakthivel K static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) 251f5860992SSakthivel K { 252f5860992SSakthivel K int i; 253f5860992SSakthivel K u32 offsetib, offsetob; 254f5860992SSakthivel K void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 255f5860992SSakthivel K void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 256f5860992SSakthivel K 257f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = 258f5860992SSakthivel K pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 259f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = 260f5860992SSakthivel K pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 261f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = 262f5860992SSakthivel K PM8001_EVENT_LOG_SIZE; 263f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; 264f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = 265f5860992SSakthivel K pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 266f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = 267f5860992SSakthivel K pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 268f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = 269f5860992SSakthivel K PM8001_EVENT_LOG_SIZE; 270f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; 271f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; 272f5860992SSakthivel K 273c6b9ef57SSakthivel K /* Disable end to end CRC checking */ 274c6b9ef57SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); 275c6b9ef57SSakthivel K 276f5860992SSakthivel K for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 277f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 2789504a923SHans Verkuil PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); 279f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 280f5860992SSakthivel K pm8001_ha->memoryMap.region[IB + i].phys_addr_hi; 281f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 282f5860992SSakthivel K pm8001_ha->memoryMap.region[IB + i].phys_addr_lo; 283f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].base_virt = 284f5860992SSakthivel K (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr; 285f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].total_length = 286f5860992SSakthivel K pm8001_ha->memoryMap.region[IB + i].total_len; 287f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 288f5860992SSakthivel K pm8001_ha->memoryMap.region[CI + i].phys_addr_hi; 289f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 290f5860992SSakthivel K pm8001_ha->memoryMap.region[CI + i].phys_addr_lo; 291f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].ci_virt = 292f5860992SSakthivel K pm8001_ha->memoryMap.region[CI + i].virt_ptr; 293f5860992SSakthivel K offsetib = i * 0x20; 294f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 295f5860992SSakthivel K get_pci_bar_index(pm8001_mr32(addressib, 296f5860992SSakthivel K (offsetib + 0x14))); 297f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].pi_offset = 298f5860992SSakthivel K pm8001_mr32(addressib, (offsetib + 0x18)); 299f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 300f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 301f5860992SSakthivel K } 302f5860992SSakthivel K for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 303f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 3049504a923SHans Verkuil PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); 305f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 306f5860992SSakthivel K pm8001_ha->memoryMap.region[OB + i].phys_addr_hi; 307f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 308f5860992SSakthivel K pm8001_ha->memoryMap.region[OB + i].phys_addr_lo; 309f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].base_virt = 310f5860992SSakthivel K (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr; 311f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].total_length = 312f5860992SSakthivel K pm8001_ha->memoryMap.region[OB + i].total_len; 313f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 314f5860992SSakthivel K pm8001_ha->memoryMap.region[PI + i].phys_addr_hi; 315f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 316f5860992SSakthivel K pm8001_ha->memoryMap.region[PI + i].phys_addr_lo; 317f5860992SSakthivel K /* interrupt vector based on oq */ 318f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); 319f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].pi_virt = 320f5860992SSakthivel K pm8001_ha->memoryMap.region[PI + i].virt_ptr; 321f5860992SSakthivel K offsetob = i * 0x24; 322f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 323f5860992SSakthivel K get_pci_bar_index(pm8001_mr32(addressob, 324f5860992SSakthivel K offsetob + 0x14)); 325f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].ci_offset = 326f5860992SSakthivel K pm8001_mr32(addressob, (offsetob + 0x18)); 327f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 328f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 329f5860992SSakthivel K } 330f5860992SSakthivel K } 331f5860992SSakthivel K 332f5860992SSakthivel K /** 333f5860992SSakthivel K * update_main_config_table - update the main default table to the HBA. 334f5860992SSakthivel K * @pm8001_ha: our hba card information 335f5860992SSakthivel K */ 336f5860992SSakthivel K static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) 337f5860992SSakthivel K { 338f5860992SSakthivel K void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 339f5860992SSakthivel K pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, 340f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); 341f5860992SSakthivel K pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, 342f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); 343f5860992SSakthivel K pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, 344f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); 345f5860992SSakthivel K pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, 346f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); 347f5860992SSakthivel K pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, 348f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); 349f5860992SSakthivel K pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, 350f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); 351f5860992SSakthivel K pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, 352f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); 353f5860992SSakthivel K pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, 354f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); 355f5860992SSakthivel K pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, 356f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); 357f5860992SSakthivel K pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, 358f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); 359c6b9ef57SSakthivel K pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, 360c6b9ef57SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); 361f5860992SSakthivel K 362f5860992SSakthivel K /* SPCv specific */ 363f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; 364f5860992SSakthivel K /* Set GPIOLED to 0x2 for LED indicator */ 365f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; 366f5860992SSakthivel K pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, 367f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); 368f5860992SSakthivel K 369f5860992SSakthivel K pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, 370f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); 371f5860992SSakthivel K pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, 372f5860992SSakthivel K pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); 373f5860992SSakthivel K } 374f5860992SSakthivel K 375f5860992SSakthivel K /** 376f5860992SSakthivel K * update_inbnd_queue_table - update the inbound queue table to the HBA. 377f5860992SSakthivel K * @pm8001_ha: our hba card information 378f5860992SSakthivel K */ 379f5860992SSakthivel K static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 380f5860992SSakthivel K int number) 381f5860992SSakthivel K { 382f5860992SSakthivel K void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 383f5860992SSakthivel K u16 offset = number * 0x20; 384f5860992SSakthivel K pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, 385f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 386f5860992SSakthivel K pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, 387f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 388f5860992SSakthivel K pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, 389f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 390f5860992SSakthivel K pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, 391f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 392f5860992SSakthivel K pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, 393f5860992SSakthivel K pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 394f5860992SSakthivel K } 395f5860992SSakthivel K 396f5860992SSakthivel K /** 397f5860992SSakthivel K * update_outbnd_queue_table - update the outbound queue table to the HBA. 398f5860992SSakthivel K * @pm8001_ha: our hba card information 399f5860992SSakthivel K */ 400f5860992SSakthivel K static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, 401f5860992SSakthivel K int number) 402f5860992SSakthivel K { 403f5860992SSakthivel K void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 404f5860992SSakthivel K u16 offset = number * 0x24; 405f5860992SSakthivel K pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, 406f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 407f5860992SSakthivel K pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, 408f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 409f5860992SSakthivel K pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, 410f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 411f5860992SSakthivel K pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, 412f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 413f5860992SSakthivel K pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, 414f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 415f5860992SSakthivel K pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, 416f5860992SSakthivel K pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 417f5860992SSakthivel K } 418f5860992SSakthivel K 419f5860992SSakthivel K /** 420f5860992SSakthivel K * mpi_init_check - check firmware initialization status. 421f5860992SSakthivel K * @pm8001_ha: our hba card information 422f5860992SSakthivel K */ 423f5860992SSakthivel K static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 424f5860992SSakthivel K { 425f5860992SSakthivel K u32 max_wait_count; 426f5860992SSakthivel K u32 value; 427f5860992SSakthivel K u32 gst_len_mpistate; 428f5860992SSakthivel K 429f5860992SSakthivel K /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 430f5860992SSakthivel K table is updated */ 431f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); 432f5860992SSakthivel K /* wait until Inbound DoorBell Clear Register toggled */ 433a9a923e5SAnand Kumar Santhanam if (IS_SPCV_12G(pm8001_ha->pdev)) { 434a9a923e5SAnand Kumar Santhanam max_wait_count = 4 * 1000 * 1000;/* 4 sec */ 435a9a923e5SAnand Kumar Santhanam } else { 436a9a923e5SAnand Kumar Santhanam max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 437a9a923e5SAnand Kumar Santhanam } 438f5860992SSakthivel K do { 439f5860992SSakthivel K udelay(1); 440f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 441f5860992SSakthivel K value &= SPCv_MSGU_CFG_TABLE_UPDATE; 442f5860992SSakthivel K } while ((value != 0) && (--max_wait_count)); 443f5860992SSakthivel K 444f5860992SSakthivel K if (!max_wait_count) 445f5860992SSakthivel K return -1; 446f5860992SSakthivel K /* check the MPI-State for initialization upto 100ms*/ 447f5860992SSakthivel K max_wait_count = 100 * 1000;/* 100 msec */ 448f5860992SSakthivel K do { 449f5860992SSakthivel K udelay(1); 450f5860992SSakthivel K gst_len_mpistate = 451f5860992SSakthivel K pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 452f5860992SSakthivel K GST_GSTLEN_MPIS_OFFSET); 453f5860992SSakthivel K } while ((GST_MPI_STATE_INIT != 454f5860992SSakthivel K (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); 455f5860992SSakthivel K if (!max_wait_count) 456f5860992SSakthivel K return -1; 457f5860992SSakthivel K 458f5860992SSakthivel K /* check MPI Initialization error */ 459f5860992SSakthivel K gst_len_mpistate = gst_len_mpistate >> 16; 460f5860992SSakthivel K if (0x0000 != gst_len_mpistate) 461f5860992SSakthivel K return -1; 462f5860992SSakthivel K 463f5860992SSakthivel K return 0; 464f5860992SSakthivel K } 465f5860992SSakthivel K 466f5860992SSakthivel K /** 467f5860992SSakthivel K * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 468f5860992SSakthivel K * @pm8001_ha: our hba card information 469f5860992SSakthivel K */ 470f5860992SSakthivel K static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 471f5860992SSakthivel K { 472f5860992SSakthivel K u32 value; 473f5860992SSakthivel K u32 max_wait_count; 474f5860992SSakthivel K u32 max_wait_time; 475f5860992SSakthivel K int ret = 0; 476f5860992SSakthivel K 477f5860992SSakthivel K /* reset / PCIe ready */ 478f5860992SSakthivel K max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */ 479f5860992SSakthivel K do { 480f5860992SSakthivel K udelay(1); 481f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 482f5860992SSakthivel K } while ((value == 0xFFFFFFFF) && (--max_wait_count)); 483f5860992SSakthivel K 484f5860992SSakthivel K /* check ila status */ 485f5860992SSakthivel K max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */ 486f5860992SSakthivel K do { 487f5860992SSakthivel K udelay(1); 488f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 489f5860992SSakthivel K } while (((value & SCRATCH_PAD_ILA_READY) != 490f5860992SSakthivel K SCRATCH_PAD_ILA_READY) && (--max_wait_count)); 491f5860992SSakthivel K if (!max_wait_count) 492f5860992SSakthivel K ret = -1; 493f5860992SSakthivel K else { 494f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 495f5860992SSakthivel K pm8001_printk(" ila ready status in %d millisec\n", 496f5860992SSakthivel K (max_wait_time - max_wait_count))); 497f5860992SSakthivel K } 498f5860992SSakthivel K 499f5860992SSakthivel K /* check RAAE status */ 500f5860992SSakthivel K max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */ 501f5860992SSakthivel K do { 502f5860992SSakthivel K udelay(1); 503f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 504f5860992SSakthivel K } while (((value & SCRATCH_PAD_RAAE_READY) != 505f5860992SSakthivel K SCRATCH_PAD_RAAE_READY) && (--max_wait_count)); 506f5860992SSakthivel K if (!max_wait_count) 507f5860992SSakthivel K ret = -1; 508f5860992SSakthivel K else { 509f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 510f5860992SSakthivel K pm8001_printk(" raae ready status in %d millisec\n", 511f5860992SSakthivel K (max_wait_time - max_wait_count))); 512f5860992SSakthivel K } 513f5860992SSakthivel K 514f5860992SSakthivel K /* check iop0 status */ 515f5860992SSakthivel K max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */ 516f5860992SSakthivel K do { 517f5860992SSakthivel K udelay(1); 518f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 519f5860992SSakthivel K } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) && 520f5860992SSakthivel K (--max_wait_count)); 521f5860992SSakthivel K if (!max_wait_count) 522f5860992SSakthivel K ret = -1; 523f5860992SSakthivel K else { 524f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 525f5860992SSakthivel K pm8001_printk(" iop0 ready status in %d millisec\n", 526f5860992SSakthivel K (max_wait_time - max_wait_count))); 527f5860992SSakthivel K } 528f5860992SSakthivel K 529f5860992SSakthivel K /* check iop1 status only for 16 port controllers */ 530f5860992SSakthivel K if ((pm8001_ha->chip_id != chip_8008) && 531f5860992SSakthivel K (pm8001_ha->chip_id != chip_8009)) { 532f5860992SSakthivel K /* 200 milli sec */ 533f5860992SSakthivel K max_wait_time = max_wait_count = 200 * 1000; 534f5860992SSakthivel K do { 535f5860992SSakthivel K udelay(1); 536f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 537f5860992SSakthivel K } while (((value & SCRATCH_PAD_IOP1_READY) != 538f5860992SSakthivel K SCRATCH_PAD_IOP1_READY) && (--max_wait_count)); 539f5860992SSakthivel K if (!max_wait_count) 540f5860992SSakthivel K ret = -1; 541f5860992SSakthivel K else { 542f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 543f5860992SSakthivel K "iop1 ready status in %d millisec\n", 544f5860992SSakthivel K (max_wait_time - max_wait_count))); 545f5860992SSakthivel K } 546f5860992SSakthivel K } 547f5860992SSakthivel K 548f5860992SSakthivel K return ret; 549f5860992SSakthivel K } 550f5860992SSakthivel K 551f5860992SSakthivel K static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 552f5860992SSakthivel K { 553f5860992SSakthivel K void __iomem *base_addr; 554f5860992SSakthivel K u32 value; 555f5860992SSakthivel K u32 offset; 556f5860992SSakthivel K u32 pcibar; 557f5860992SSakthivel K u32 pcilogic; 558f5860992SSakthivel K 559f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 560f5860992SSakthivel K offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ 561f5860992SSakthivel K 562f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 563f5860992SSakthivel K pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n", 564f5860992SSakthivel K offset, value)); 565f5860992SSakthivel K pcilogic = (value & 0xFC000000) >> 26; 566f5860992SSakthivel K pcibar = get_pci_bar_index(pcilogic); 567f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 568f5860992SSakthivel K pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar)); 569f5860992SSakthivel K pm8001_ha->main_cfg_tbl_addr = base_addr = 570f5860992SSakthivel K pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 571f5860992SSakthivel K pm8001_ha->general_stat_tbl_addr = 572f5860992SSakthivel K base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & 573f5860992SSakthivel K 0xFFFFFF); 574f5860992SSakthivel K pm8001_ha->inbnd_q_tbl_addr = 575f5860992SSakthivel K base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & 576f5860992SSakthivel K 0xFFFFFF); 577f5860992SSakthivel K pm8001_ha->outbnd_q_tbl_addr = 578f5860992SSakthivel K base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & 579f5860992SSakthivel K 0xFFFFFF); 580f5860992SSakthivel K pm8001_ha->ivt_tbl_addr = 581f5860992SSakthivel K base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & 582f5860992SSakthivel K 0xFFFFFF); 583f5860992SSakthivel K pm8001_ha->pspa_q_tbl_addr = 584f5860992SSakthivel K base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & 585f5860992SSakthivel K 0xFFFFFF); 586f5860992SSakthivel K 587f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 588f5860992SSakthivel K pm8001_printk("GST OFFSET 0x%x\n", 589f5860992SSakthivel K pm8001_cr32(pm8001_ha, pcibar, offset + 0x18))); 590f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 591f5860992SSakthivel K pm8001_printk("INBND OFFSET 0x%x\n", 592f5860992SSakthivel K pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C))); 593f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 594f5860992SSakthivel K pm8001_printk("OBND OFFSET 0x%x\n", 595f5860992SSakthivel K pm8001_cr32(pm8001_ha, pcibar, offset + 0x20))); 596f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 597f5860992SSakthivel K pm8001_printk("IVT OFFSET 0x%x\n", 598f5860992SSakthivel K pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C))); 599f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 600f5860992SSakthivel K pm8001_printk("PSPA OFFSET 0x%x\n", 601f5860992SSakthivel K pm8001_cr32(pm8001_ha, pcibar, offset + 0x90))); 602f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 603f5860992SSakthivel K pm8001_printk("addr - main cfg %p general status %p\n", 604f5860992SSakthivel K pm8001_ha->main_cfg_tbl_addr, 605f5860992SSakthivel K pm8001_ha->general_stat_tbl_addr)); 606f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 607f5860992SSakthivel K pm8001_printk("addr - inbnd %p obnd %p\n", 608f5860992SSakthivel K pm8001_ha->inbnd_q_tbl_addr, 609f5860992SSakthivel K pm8001_ha->outbnd_q_tbl_addr)); 610f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 611f5860992SSakthivel K pm8001_printk("addr - pspa %p ivt %p\n", 612f5860992SSakthivel K pm8001_ha->pspa_q_tbl_addr, 613f5860992SSakthivel K pm8001_ha->ivt_tbl_addr)); 614f5860992SSakthivel K } 615f5860992SSakthivel K 616f5860992SSakthivel K /** 617f5860992SSakthivel K * pm80xx_set_thermal_config - support the thermal configuration 618f5860992SSakthivel K * @pm8001_ha: our hba card information. 619f5860992SSakthivel K */ 620a6cb3d01SSakthivel K int 621f5860992SSakthivel K pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) 622f5860992SSakthivel K { 623f5860992SSakthivel K struct set_ctrl_cfg_req payload; 624f5860992SSakthivel K struct inbound_queue_table *circularQ; 625f5860992SSakthivel K int rc; 626f5860992SSakthivel K u32 tag; 627f5860992SSakthivel K u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 628f5860992SSakthivel K 629f5860992SSakthivel K memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 630f5860992SSakthivel K rc = pm8001_tag_alloc(pm8001_ha, &tag); 631f5860992SSakthivel K if (rc) 632f5860992SSakthivel K return -1; 633f5860992SSakthivel K 634f5860992SSakthivel K circularQ = &pm8001_ha->inbnd_q_tbl[0]; 635f5860992SSakthivel K payload.tag = cpu_to_le32(tag); 636f5860992SSakthivel K payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) | 637f5860992SSakthivel K (THERMAL_ENABLE << 8) | THERMAL_OP_CODE; 638f5860992SSakthivel K payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8); 639f5860992SSakthivel K 640f5860992SSakthivel K rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 641f5860992SSakthivel K return rc; 642f5860992SSakthivel K 643f5860992SSakthivel K } 644f5860992SSakthivel K 645f5860992SSakthivel K /** 646a6cb3d01SSakthivel K * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol 647a6cb3d01SSakthivel K * Timer configuration page 648a6cb3d01SSakthivel K * @pm8001_ha: our hba card information. 649a6cb3d01SSakthivel K */ 650a6cb3d01SSakthivel K static int 651a6cb3d01SSakthivel K pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) 652a6cb3d01SSakthivel K { 653a6cb3d01SSakthivel K struct set_ctrl_cfg_req payload; 654a6cb3d01SSakthivel K struct inbound_queue_table *circularQ; 655a6cb3d01SSakthivel K SASProtocolTimerConfig_t SASConfigPage; 656a6cb3d01SSakthivel K int rc; 657a6cb3d01SSakthivel K u32 tag; 658a6cb3d01SSakthivel K u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; 659a6cb3d01SSakthivel K 660a6cb3d01SSakthivel K memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); 661a6cb3d01SSakthivel K memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); 662a6cb3d01SSakthivel K 663a6cb3d01SSakthivel K rc = pm8001_tag_alloc(pm8001_ha, &tag); 664a6cb3d01SSakthivel K 665a6cb3d01SSakthivel K if (rc) 666a6cb3d01SSakthivel K return -1; 667a6cb3d01SSakthivel K 668a6cb3d01SSakthivel K circularQ = &pm8001_ha->inbnd_q_tbl[0]; 669a6cb3d01SSakthivel K payload.tag = cpu_to_le32(tag); 670a6cb3d01SSakthivel K 671a6cb3d01SSakthivel K SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE; 672a6cb3d01SSakthivel K SASConfigPage.MST_MSI = 3 << 15; 673a6cb3d01SSakthivel K SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO; 674a6cb3d01SSakthivel K SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) | 675a6cb3d01SSakthivel K (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER; 676a6cb3d01SSakthivel K SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME; 677a6cb3d01SSakthivel K 678a6cb3d01SSakthivel K if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF) 679a6cb3d01SSakthivel K SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF; 680a6cb3d01SSakthivel K 681a6cb3d01SSakthivel K 682a6cb3d01SSakthivel K SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) | 683a6cb3d01SSakthivel K SAS_OPNRJT_RTRY_INTVL; 684a6cb3d01SSakthivel K SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16) 685a6cb3d01SSakthivel K | SAS_COPNRJT_RTRY_TMO; 686a6cb3d01SSakthivel K SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16) 687a6cb3d01SSakthivel K | SAS_COPNRJT_RTRY_THR; 688a6cb3d01SSakthivel K SASConfigPage.MAX_AIP = SAS_MAX_AIP; 689a6cb3d01SSakthivel K 690a6cb3d01SSakthivel K PM8001_INIT_DBG(pm8001_ha, 691a6cb3d01SSakthivel K pm8001_printk("SASConfigPage.pageCode " 692a6cb3d01SSakthivel K "0x%08x\n", SASConfigPage.pageCode)); 693a6cb3d01SSakthivel K PM8001_INIT_DBG(pm8001_ha, 694a6cb3d01SSakthivel K pm8001_printk("SASConfigPage.MST_MSI " 695a6cb3d01SSakthivel K " 0x%08x\n", SASConfigPage.MST_MSI)); 696a6cb3d01SSakthivel K PM8001_INIT_DBG(pm8001_ha, 697a6cb3d01SSakthivel K pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO " 698a6cb3d01SSakthivel K " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO)); 699a6cb3d01SSakthivel K PM8001_INIT_DBG(pm8001_ha, 700a6cb3d01SSakthivel K pm8001_printk("SASConfigPage.STP_FRM_TMO " 701a6cb3d01SSakthivel K " 0x%08x\n", SASConfigPage.STP_FRM_TMO)); 702a6cb3d01SSakthivel K PM8001_INIT_DBG(pm8001_ha, 703a6cb3d01SSakthivel K pm8001_printk("SASConfigPage.STP_IDLE_TMO " 704a6cb3d01SSakthivel K " 0x%08x\n", SASConfigPage.STP_IDLE_TMO)); 705a6cb3d01SSakthivel K PM8001_INIT_DBG(pm8001_ha, 706a6cb3d01SSakthivel K pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL " 707a6cb3d01SSakthivel K " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL)); 708a6cb3d01SSakthivel K PM8001_INIT_DBG(pm8001_ha, 709a6cb3d01SSakthivel K pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO " 710a6cb3d01SSakthivel K " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO)); 711a6cb3d01SSakthivel K PM8001_INIT_DBG(pm8001_ha, 712a6cb3d01SSakthivel K pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR " 713a6cb3d01SSakthivel K " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR)); 714a6cb3d01SSakthivel K PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP " 715a6cb3d01SSakthivel K " 0x%08x\n", SASConfigPage.MAX_AIP)); 716a6cb3d01SSakthivel K 717a6cb3d01SSakthivel K memcpy(&payload.cfg_pg, &SASConfigPage, 718a6cb3d01SSakthivel K sizeof(SASProtocolTimerConfig_t)); 719a6cb3d01SSakthivel K 720a6cb3d01SSakthivel K rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 721a6cb3d01SSakthivel K 722a6cb3d01SSakthivel K return rc; 723a6cb3d01SSakthivel K } 724a6cb3d01SSakthivel K 725a6cb3d01SSakthivel K /** 726f5860992SSakthivel K * pm80xx_get_encrypt_info - Check for encryption 727f5860992SSakthivel K * @pm8001_ha: our hba card information. 728f5860992SSakthivel K */ 729f5860992SSakthivel K static int 730f5860992SSakthivel K pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) 731f5860992SSakthivel K { 732f5860992SSakthivel K u32 scratch3_value; 733f5860992SSakthivel K int ret; 734f5860992SSakthivel K 735f5860992SSakthivel K /* Read encryption status from SCRATCH PAD 3 */ 736f5860992SSakthivel K scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 737f5860992SSakthivel K 738f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 739f5860992SSakthivel K SCRATCH_PAD3_ENC_READY) { 740f5860992SSakthivel K if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 741f5860992SSakthivel K pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 742f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 743f5860992SSakthivel K SCRATCH_PAD3_SMF_ENABLED) 744f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 745f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 746f5860992SSakthivel K SCRATCH_PAD3_SMA_ENABLED) 747f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 748f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 749f5860992SSakthivel K SCRATCH_PAD3_SMB_ENABLED) 750f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 751f5860992SSakthivel K pm8001_ha->encrypt_info.status = 0; 752f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 753f5860992SSakthivel K "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X." 754f5860992SSakthivel K "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", 755f5860992SSakthivel K scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 756f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode, 757f5860992SSakthivel K pm8001_ha->encrypt_info.status)); 758f5860992SSakthivel K ret = 0; 759f5860992SSakthivel K } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == 760f5860992SSakthivel K SCRATCH_PAD3_ENC_DISABLED) { 761f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 762f5860992SSakthivel K "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", 763f5860992SSakthivel K scratch3_value)); 764f5860992SSakthivel K pm8001_ha->encrypt_info.status = 0xFFFFFFFF; 765f5860992SSakthivel K pm8001_ha->encrypt_info.cipher_mode = 0; 766f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = 0; 767f5860992SSakthivel K return 0; 768f5860992SSakthivel K } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 769f5860992SSakthivel K SCRATCH_PAD3_ENC_DIS_ERR) { 770f5860992SSakthivel K pm8001_ha->encrypt_info.status = 771f5860992SSakthivel K (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 772f5860992SSakthivel K if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 773f5860992SSakthivel K pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 774f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 775f5860992SSakthivel K SCRATCH_PAD3_SMF_ENABLED) 776f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 777f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 778f5860992SSakthivel K SCRATCH_PAD3_SMA_ENABLED) 779f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 780f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 781f5860992SSakthivel K SCRATCH_PAD3_SMB_ENABLED) 782f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 783f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 784f5860992SSakthivel K "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X." 785f5860992SSakthivel K "Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 786f5860992SSakthivel K scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 787f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode, 788f5860992SSakthivel K pm8001_ha->encrypt_info.status)); 789f5860992SSakthivel K ret = -1; 790f5860992SSakthivel K } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == 791f5860992SSakthivel K SCRATCH_PAD3_ENC_ENA_ERR) { 792f5860992SSakthivel K 793f5860992SSakthivel K pm8001_ha->encrypt_info.status = 794f5860992SSakthivel K (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; 795f5860992SSakthivel K if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) 796f5860992SSakthivel K pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; 797f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 798f5860992SSakthivel K SCRATCH_PAD3_SMF_ENABLED) 799f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; 800f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 801f5860992SSakthivel K SCRATCH_PAD3_SMA_ENABLED) 802f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; 803f5860992SSakthivel K if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == 804f5860992SSakthivel K SCRATCH_PAD3_SMB_ENABLED) 805f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; 806f5860992SSakthivel K 807f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 808f5860992SSakthivel K "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X." 809f5860992SSakthivel K "Cipher mode 0x%x sec mode 0x%x status 0x%x\n", 810f5860992SSakthivel K scratch3_value, pm8001_ha->encrypt_info.cipher_mode, 811f5860992SSakthivel K pm8001_ha->encrypt_info.sec_mode, 812f5860992SSakthivel K pm8001_ha->encrypt_info.status)); 813f5860992SSakthivel K ret = -1; 814f5860992SSakthivel K } 815f5860992SSakthivel K return ret; 816f5860992SSakthivel K } 817f5860992SSakthivel K 818f5860992SSakthivel K /** 819f5860992SSakthivel K * pm80xx_encrypt_update - update flash with encryption informtion 820f5860992SSakthivel K * @pm8001_ha: our hba card information. 821f5860992SSakthivel K */ 822f5860992SSakthivel K static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) 823f5860992SSakthivel K { 824f5860992SSakthivel K struct kek_mgmt_req payload; 825f5860992SSakthivel K struct inbound_queue_table *circularQ; 826f5860992SSakthivel K int rc; 827f5860992SSakthivel K u32 tag; 828f5860992SSakthivel K u32 opc = OPC_INB_KEK_MANAGEMENT; 829f5860992SSakthivel K 830f5860992SSakthivel K memset(&payload, 0, sizeof(struct kek_mgmt_req)); 831f5860992SSakthivel K rc = pm8001_tag_alloc(pm8001_ha, &tag); 832f5860992SSakthivel K if (rc) 833f5860992SSakthivel K return -1; 834f5860992SSakthivel K 835f5860992SSakthivel K circularQ = &pm8001_ha->inbnd_q_tbl[0]; 836f5860992SSakthivel K payload.tag = cpu_to_le32(tag); 837f5860992SSakthivel K /* Currently only one key is used. New KEK index is 1. 838f5860992SSakthivel K * Current KEK index is 1. Store KEK to NVRAM is 1. 839f5860992SSakthivel K */ 840f5860992SSakthivel K payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) | 841f5860992SSakthivel K KEK_MGMT_SUBOP_KEYCARDUPDATE); 842f5860992SSakthivel K 843f5860992SSakthivel K rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 844f5860992SSakthivel K 845f5860992SSakthivel K return rc; 846f5860992SSakthivel K } 847f5860992SSakthivel K 848f5860992SSakthivel K /** 849f5860992SSakthivel K * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 850f5860992SSakthivel K * @pm8001_ha: our hba card information 851f5860992SSakthivel K */ 852f5860992SSakthivel K static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) 853f5860992SSakthivel K { 854f5860992SSakthivel K int ret; 855f5860992SSakthivel K u8 i = 0; 856f5860992SSakthivel K 857f5860992SSakthivel K /* check the firmware status */ 858f5860992SSakthivel K if (-1 == check_fw_ready(pm8001_ha)) { 859f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 860f5860992SSakthivel K pm8001_printk("Firmware is not ready!\n")); 861f5860992SSakthivel K return -EBUSY; 862f5860992SSakthivel K } 863f5860992SSakthivel K 864f5860992SSakthivel K /* Initialize pci space address eg: mpi offset */ 865f5860992SSakthivel K init_pci_device_addresses(pm8001_ha); 866f5860992SSakthivel K init_default_table_values(pm8001_ha); 867f5860992SSakthivel K read_main_config_table(pm8001_ha); 868f5860992SSakthivel K read_general_status_table(pm8001_ha); 869f5860992SSakthivel K read_inbnd_queue_table(pm8001_ha); 870f5860992SSakthivel K read_outbnd_queue_table(pm8001_ha); 871f5860992SSakthivel K read_phy_attr_table(pm8001_ha); 872f5860992SSakthivel K 873f5860992SSakthivel K /* update main config table ,inbound table and outbound table */ 874f5860992SSakthivel K update_main_config_table(pm8001_ha); 875f5860992SSakthivel K for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) 876f5860992SSakthivel K update_inbnd_queue_table(pm8001_ha, i); 877f5860992SSakthivel K for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) 878f5860992SSakthivel K update_outbnd_queue_table(pm8001_ha, i); 879f5860992SSakthivel K 880f5860992SSakthivel K /* notify firmware update finished and check initialization status */ 881f5860992SSakthivel K if (0 == mpi_init_check(pm8001_ha)) { 882f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 883f5860992SSakthivel K pm8001_printk("MPI initialize successful!\n")); 884f5860992SSakthivel K } else 885f5860992SSakthivel K return -EBUSY; 886f5860992SSakthivel K 887a6cb3d01SSakthivel K /* send SAS protocol timer configuration page to FW */ 888a6cb3d01SSakthivel K ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha); 889f5860992SSakthivel K 890f5860992SSakthivel K /* Check for encryption */ 891f5860992SSakthivel K if (pm8001_ha->chip->encrypt) { 892f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 893f5860992SSakthivel K pm8001_printk("Checking for encryption\n")); 894f5860992SSakthivel K ret = pm80xx_get_encrypt_info(pm8001_ha); 895f5860992SSakthivel K if (ret == -1) { 896f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 897f5860992SSakthivel K pm8001_printk("Encryption error !!\n")); 898f5860992SSakthivel K if (pm8001_ha->encrypt_info.status == 0x81) { 899f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 900f5860992SSakthivel K "Encryption enabled with error." 901f5860992SSakthivel K "Saving encryption key to flash\n")); 902f5860992SSakthivel K pm80xx_encrypt_update(pm8001_ha); 903f5860992SSakthivel K } 904f5860992SSakthivel K } 905f5860992SSakthivel K } 906f5860992SSakthivel K return 0; 907f5860992SSakthivel K } 908f5860992SSakthivel K 909f5860992SSakthivel K static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 910f5860992SSakthivel K { 911f5860992SSakthivel K u32 max_wait_count; 912f5860992SSakthivel K u32 value; 913f5860992SSakthivel K u32 gst_len_mpistate; 914f5860992SSakthivel K init_pci_device_addresses(pm8001_ha); 915f5860992SSakthivel K /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 916f5860992SSakthivel K table is stop */ 917f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); 918f5860992SSakthivel K 919f5860992SSakthivel K /* wait until Inbound DoorBell Clear Register toggled */ 920a9a923e5SAnand Kumar Santhanam if (IS_SPCV_12G(pm8001_ha->pdev)) { 921a9a923e5SAnand Kumar Santhanam max_wait_count = 4 * 1000 * 1000;/* 4 sec */ 922a9a923e5SAnand Kumar Santhanam } else { 923a9a923e5SAnand Kumar Santhanam max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 924a9a923e5SAnand Kumar Santhanam } 925f5860992SSakthivel K do { 926f5860992SSakthivel K udelay(1); 927f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 928f5860992SSakthivel K value &= SPCv_MSGU_CFG_TABLE_RESET; 929f5860992SSakthivel K } while ((value != 0) && (--max_wait_count)); 930f5860992SSakthivel K 931f5860992SSakthivel K if (!max_wait_count) { 932f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 933f5860992SSakthivel K pm8001_printk("TIMEOUT:IBDB value/=%x\n", value)); 934f5860992SSakthivel K return -1; 935f5860992SSakthivel K } 936f5860992SSakthivel K 937f5860992SSakthivel K /* check the MPI-State for termination in progress */ 938f5860992SSakthivel K /* wait until Inbound DoorBell Clear Register toggled */ 939f5860992SSakthivel K max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */ 940f5860992SSakthivel K do { 941f5860992SSakthivel K udelay(1); 942f5860992SSakthivel K gst_len_mpistate = 943f5860992SSakthivel K pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 944f5860992SSakthivel K GST_GSTLEN_MPIS_OFFSET); 945f5860992SSakthivel K if (GST_MPI_STATE_UNINIT == 946f5860992SSakthivel K (gst_len_mpistate & GST_MPI_STATE_MASK)) 947f5860992SSakthivel K break; 948f5860992SSakthivel K } while (--max_wait_count); 949f5860992SSakthivel K if (!max_wait_count) { 950f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 951f5860992SSakthivel K pm8001_printk(" TIME OUT MPI State = 0x%x\n", 952f5860992SSakthivel K gst_len_mpistate & GST_MPI_STATE_MASK)); 953f5860992SSakthivel K return -1; 954f5860992SSakthivel K } 955f5860992SSakthivel K 956f5860992SSakthivel K return 0; 957f5860992SSakthivel K } 958f5860992SSakthivel K 959f5860992SSakthivel K /** 960f5860992SSakthivel K * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 961f5860992SSakthivel K * the FW register status to the originated status. 962f5860992SSakthivel K * @pm8001_ha: our hba card information 963f5860992SSakthivel K */ 964f5860992SSakthivel K 965f5860992SSakthivel K static int 966f5860992SSakthivel K pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) 967f5860992SSakthivel K { 968f5860992SSakthivel K u32 regval; 969f5860992SSakthivel K u32 bootloader_state; 97006f12f22SAnand Kumar Santhanam u32 ibutton0, ibutton1; 971f5860992SSakthivel K 972f5860992SSakthivel K /* Check if MPI is in ready state to reset */ 973f5860992SSakthivel K if (mpi_uninit_check(pm8001_ha) != 0) { 974f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 975f5860992SSakthivel K pm8001_printk("MPI state is not ready\n")); 976f5860992SSakthivel K return -1; 977f5860992SSakthivel K } 978f5860992SSakthivel K 979f5860992SSakthivel K /* checked for reset register normal state; 0x0 */ 980f5860992SSakthivel K regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 981f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 982f5860992SSakthivel K pm8001_printk("reset register before write : 0x%x\n", regval)); 983f5860992SSakthivel K 984f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); 985f5860992SSakthivel K mdelay(500); 986f5860992SSakthivel K 987f5860992SSakthivel K regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); 988f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 989f5860992SSakthivel K pm8001_printk("reset register after write 0x%x\n", regval)); 990f5860992SSakthivel K 991f5860992SSakthivel K if ((regval & SPCv_SOFT_RESET_READ_MASK) == 992f5860992SSakthivel K SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { 993f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 994f5860992SSakthivel K pm8001_printk(" soft reset successful [regval: 0x%x]\n", 995f5860992SSakthivel K regval)); 996f5860992SSakthivel K } else { 997f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 998f5860992SSakthivel K pm8001_printk(" soft reset failed [regval: 0x%x]\n", 999f5860992SSakthivel K regval)); 1000f5860992SSakthivel K 1001f5860992SSakthivel K /* check bootloader is successfully executed or in HDA mode */ 1002f5860992SSakthivel K bootloader_state = 1003f5860992SSakthivel K pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1004f5860992SSakthivel K SCRATCH_PAD1_BOOTSTATE_MASK; 1005f5860992SSakthivel K 1006f5860992SSakthivel K if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { 1007f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1008f5860992SSakthivel K "Bootloader state - HDA mode SEEPROM\n")); 1009f5860992SSakthivel K } else if (bootloader_state == 1010f5860992SSakthivel K SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { 1011f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1012f5860992SSakthivel K "Bootloader state - HDA mode Bootstrap Pin\n")); 1013f5860992SSakthivel K } else if (bootloader_state == 1014f5860992SSakthivel K SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { 1015f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1016f5860992SSakthivel K "Bootloader state - HDA mode soft reset\n")); 1017f5860992SSakthivel K } else if (bootloader_state == 1018f5860992SSakthivel K SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { 1019f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 1020f5860992SSakthivel K "Bootloader state-HDA mode critical error\n")); 1021f5860992SSakthivel K } 1022f5860992SSakthivel K return -EBUSY; 1023f5860992SSakthivel K } 1024f5860992SSakthivel K 1025f5860992SSakthivel K /* check the firmware status after reset */ 1026f5860992SSakthivel K if (-1 == check_fw_ready(pm8001_ha)) { 1027f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 1028f5860992SSakthivel K pm8001_printk("Firmware is not ready!\n")); 102906f12f22SAnand Kumar Santhanam /* check iButton feature support for motherboard controller */ 103006f12f22SAnand Kumar Santhanam if (pm8001_ha->pdev->subsystem_vendor != 103106f12f22SAnand Kumar Santhanam PCI_VENDOR_ID_ADAPTEC2 && 103206f12f22SAnand Kumar Santhanam pm8001_ha->pdev->subsystem_vendor != 0) { 103306f12f22SAnand Kumar Santhanam ibutton0 = pm8001_cr32(pm8001_ha, 0, 103406f12f22SAnand Kumar Santhanam MSGU_HOST_SCRATCH_PAD_6); 103506f12f22SAnand Kumar Santhanam ibutton1 = pm8001_cr32(pm8001_ha, 0, 103606f12f22SAnand Kumar Santhanam MSGU_HOST_SCRATCH_PAD_7); 103706f12f22SAnand Kumar Santhanam if (!ibutton0 && !ibutton1) { 103806f12f22SAnand Kumar Santhanam PM8001_FAIL_DBG(pm8001_ha, 103906f12f22SAnand Kumar Santhanam pm8001_printk("iButton Feature is" 104006f12f22SAnand Kumar Santhanam " not Available!!!\n")); 1041f5860992SSakthivel K return -EBUSY; 1042f5860992SSakthivel K } 104306f12f22SAnand Kumar Santhanam if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { 104406f12f22SAnand Kumar Santhanam PM8001_FAIL_DBG(pm8001_ha, 104506f12f22SAnand Kumar Santhanam pm8001_printk("CRC Check for iButton" 104606f12f22SAnand Kumar Santhanam " Feature Failed!!!\n")); 104706f12f22SAnand Kumar Santhanam return -EBUSY; 104806f12f22SAnand Kumar Santhanam } 104906f12f22SAnand Kumar Santhanam } 105006f12f22SAnand Kumar Santhanam } 1051f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 1052f5860992SSakthivel K pm8001_printk("SPCv soft reset Complete\n")); 1053f5860992SSakthivel K return 0; 1054f5860992SSakthivel K } 1055f5860992SSakthivel K 1056f5860992SSakthivel K static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1057f5860992SSakthivel K { 1058f5860992SSakthivel K u32 i; 1059f5860992SSakthivel K 1060f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 1061f5860992SSakthivel K pm8001_printk("chip reset start\n")); 1062f5860992SSakthivel K 1063f5860992SSakthivel K /* do SPCv chip reset. */ 1064f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); 1065f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 1066f5860992SSakthivel K pm8001_printk("SPC soft reset Complete\n")); 1067f5860992SSakthivel K 1068f5860992SSakthivel K /* Check this ..whether delay is required or no */ 1069f5860992SSakthivel K /* delay 10 usec */ 1070f5860992SSakthivel K udelay(10); 1071f5860992SSakthivel K 1072f5860992SSakthivel K /* wait for 20 msec until the firmware gets reloaded */ 1073f5860992SSakthivel K i = 20; 1074f5860992SSakthivel K do { 1075f5860992SSakthivel K mdelay(1); 1076f5860992SSakthivel K } while ((--i) != 0); 1077f5860992SSakthivel K 1078f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 1079f5860992SSakthivel K pm8001_printk("chip reset finished\n")); 1080f5860992SSakthivel K } 1081f5860992SSakthivel K 1082f5860992SSakthivel K /** 1083f5860992SSakthivel K * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1084f5860992SSakthivel K * @pm8001_ha: our hba card information 1085f5860992SSakthivel K */ 1086f5860992SSakthivel K static void 1087f5860992SSakthivel K pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1088f5860992SSakthivel K { 1089f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1090f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1091f5860992SSakthivel K } 1092f5860992SSakthivel K 1093f5860992SSakthivel K /** 1094f5860992SSakthivel K * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1095f5860992SSakthivel K * @pm8001_ha: our hba card information 1096f5860992SSakthivel K */ 1097f5860992SSakthivel K static void 1098f5860992SSakthivel K pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1099f5860992SSakthivel K { 1100f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); 1101f5860992SSakthivel K } 1102f5860992SSakthivel K 1103f5860992SSakthivel K /** 1104f5860992SSakthivel K * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1105f5860992SSakthivel K * @pm8001_ha: our hba card information 1106f5860992SSakthivel K */ 1107f5860992SSakthivel K static void 1108f5860992SSakthivel K pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1109f5860992SSakthivel K { 1110f5860992SSakthivel K #ifdef PM8001_USE_MSIX 1111f5860992SSakthivel K u32 mask; 1112f5860992SSakthivel K mask = (u32)(1 << vec); 1113f5860992SSakthivel K 1114f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); 1115f5860992SSakthivel K return; 1116f5860992SSakthivel K #endif 1117f5860992SSakthivel K pm80xx_chip_intx_interrupt_enable(pm8001_ha); 1118f5860992SSakthivel K 1119f5860992SSakthivel K } 1120f5860992SSakthivel K 1121f5860992SSakthivel K /** 1122f5860992SSakthivel K * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt 1123f5860992SSakthivel K * @pm8001_ha: our hba card information 1124f5860992SSakthivel K */ 1125f5860992SSakthivel K static void 1126f5860992SSakthivel K pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) 1127f5860992SSakthivel K { 1128f5860992SSakthivel K #ifdef PM8001_USE_MSIX 1129f5860992SSakthivel K u32 mask; 1130f5860992SSakthivel K if (vec == 0xFF) 1131f5860992SSakthivel K mask = 0xFFFFFFFF; 1132f5860992SSakthivel K else 1133f5860992SSakthivel K mask = (u32)(1 << vec); 1134f5860992SSakthivel K pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); 1135f5860992SSakthivel K return; 1136f5860992SSakthivel K #endif 1137f5860992SSakthivel K pm80xx_chip_intx_interrupt_disable(pm8001_ha); 1138f5860992SSakthivel K } 1139f5860992SSakthivel K 1140c6b9ef57SSakthivel K static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha, 1141c6b9ef57SSakthivel K struct pm8001_device *pm8001_ha_dev) 1142c6b9ef57SSakthivel K { 1143c6b9ef57SSakthivel K int res; 1144c6b9ef57SSakthivel K u32 ccb_tag; 1145c6b9ef57SSakthivel K struct pm8001_ccb_info *ccb; 1146c6b9ef57SSakthivel K struct sas_task *task = NULL; 1147c6b9ef57SSakthivel K struct task_abort_req task_abort; 1148c6b9ef57SSakthivel K struct inbound_queue_table *circularQ; 1149c6b9ef57SSakthivel K u32 opc = OPC_INB_SATA_ABORT; 1150c6b9ef57SSakthivel K int ret; 1151c6b9ef57SSakthivel K 1152c6b9ef57SSakthivel K if (!pm8001_ha_dev) { 1153c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n")); 1154c6b9ef57SSakthivel K return; 1155c6b9ef57SSakthivel K } 1156c6b9ef57SSakthivel K 1157c6b9ef57SSakthivel K task = sas_alloc_slow_task(GFP_ATOMIC); 1158c6b9ef57SSakthivel K 1159c6b9ef57SSakthivel K if (!task) { 1160c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot " 1161c6b9ef57SSakthivel K "allocate task\n")); 1162c6b9ef57SSakthivel K return; 1163c6b9ef57SSakthivel K } 1164c6b9ef57SSakthivel K 1165c6b9ef57SSakthivel K task->task_done = pm8001_task_done; 1166c6b9ef57SSakthivel K 1167c6b9ef57SSakthivel K res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1168c6b9ef57SSakthivel K if (res) 1169c6b9ef57SSakthivel K return; 1170c6b9ef57SSakthivel K 1171c6b9ef57SSakthivel K ccb = &pm8001_ha->ccb_info[ccb_tag]; 1172c6b9ef57SSakthivel K ccb->device = pm8001_ha_dev; 1173c6b9ef57SSakthivel K ccb->ccb_tag = ccb_tag; 1174c6b9ef57SSakthivel K ccb->task = task; 1175c6b9ef57SSakthivel K 1176c6b9ef57SSakthivel K circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1177c6b9ef57SSakthivel K 1178c6b9ef57SSakthivel K memset(&task_abort, 0, sizeof(task_abort)); 1179c6b9ef57SSakthivel K task_abort.abort_all = cpu_to_le32(1); 1180c6b9ef57SSakthivel K task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1181c6b9ef57SSakthivel K task_abort.tag = cpu_to_le32(ccb_tag); 1182c6b9ef57SSakthivel K 1183c6b9ef57SSakthivel K ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0); 1184c6b9ef57SSakthivel K 1185c6b9ef57SSakthivel K } 1186c6b9ef57SSakthivel K 1187c6b9ef57SSakthivel K static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha, 1188c6b9ef57SSakthivel K struct pm8001_device *pm8001_ha_dev) 1189c6b9ef57SSakthivel K { 1190c6b9ef57SSakthivel K struct sata_start_req sata_cmd; 1191c6b9ef57SSakthivel K int res; 1192c6b9ef57SSakthivel K u32 ccb_tag; 1193c6b9ef57SSakthivel K struct pm8001_ccb_info *ccb; 1194c6b9ef57SSakthivel K struct sas_task *task = NULL; 1195c6b9ef57SSakthivel K struct host_to_dev_fis fis; 1196c6b9ef57SSakthivel K struct domain_device *dev; 1197c6b9ef57SSakthivel K struct inbound_queue_table *circularQ; 1198c6b9ef57SSakthivel K u32 opc = OPC_INB_SATA_HOST_OPSTART; 1199c6b9ef57SSakthivel K 1200c6b9ef57SSakthivel K task = sas_alloc_slow_task(GFP_ATOMIC); 1201c6b9ef57SSakthivel K 1202c6b9ef57SSakthivel K if (!task) { 1203c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 1204c6b9ef57SSakthivel K pm8001_printk("cannot allocate task !!!\n")); 1205c6b9ef57SSakthivel K return; 1206c6b9ef57SSakthivel K } 1207c6b9ef57SSakthivel K task->task_done = pm8001_task_done; 1208c6b9ef57SSakthivel K 1209c6b9ef57SSakthivel K res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); 1210c6b9ef57SSakthivel K if (res) { 1211c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 1212c6b9ef57SSakthivel K pm8001_printk("cannot allocate tag !!!\n")); 1213c6b9ef57SSakthivel K return; 1214c6b9ef57SSakthivel K } 1215c6b9ef57SSakthivel K 1216c6b9ef57SSakthivel K /* allocate domain device by ourselves as libsas 1217c6b9ef57SSakthivel K * is not going to provide any 1218c6b9ef57SSakthivel K */ 1219c6b9ef57SSakthivel K dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); 1220c6b9ef57SSakthivel K if (!dev) { 1221c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 1222c6b9ef57SSakthivel K pm8001_printk("Domain device cannot be allocated\n")); 1223c6b9ef57SSakthivel K sas_free_task(task); 1224c6b9ef57SSakthivel K return; 1225c6b9ef57SSakthivel K } else { 1226c6b9ef57SSakthivel K task->dev = dev; 1227c6b9ef57SSakthivel K task->dev->lldd_dev = pm8001_ha_dev; 1228c6b9ef57SSakthivel K } 1229c6b9ef57SSakthivel K 1230c6b9ef57SSakthivel K ccb = &pm8001_ha->ccb_info[ccb_tag]; 1231c6b9ef57SSakthivel K ccb->device = pm8001_ha_dev; 1232c6b9ef57SSakthivel K ccb->ccb_tag = ccb_tag; 1233c6b9ef57SSakthivel K ccb->task = task; 1234c6b9ef57SSakthivel K pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; 1235c6b9ef57SSakthivel K pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; 1236c6b9ef57SSakthivel K 1237c6b9ef57SSakthivel K memset(&sata_cmd, 0, sizeof(sata_cmd)); 1238c6b9ef57SSakthivel K circularQ = &pm8001_ha->inbnd_q_tbl[0]; 1239c6b9ef57SSakthivel K 1240c6b9ef57SSakthivel K /* construct read log FIS */ 1241c6b9ef57SSakthivel K memset(&fis, 0, sizeof(struct host_to_dev_fis)); 1242c6b9ef57SSakthivel K fis.fis_type = 0x27; 1243c6b9ef57SSakthivel K fis.flags = 0x80; 1244c6b9ef57SSakthivel K fis.command = ATA_CMD_READ_LOG_EXT; 1245c6b9ef57SSakthivel K fis.lbal = 0x10; 1246c6b9ef57SSakthivel K fis.sector_count = 0x1; 1247c6b9ef57SSakthivel K 1248c6b9ef57SSakthivel K sata_cmd.tag = cpu_to_le32(ccb_tag); 1249c6b9ef57SSakthivel K sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 1250c6b9ef57SSakthivel K sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9)); 1251c6b9ef57SSakthivel K memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); 1252c6b9ef57SSakthivel K 1253c6b9ef57SSakthivel K res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0); 1254c6b9ef57SSakthivel K 1255c6b9ef57SSakthivel K } 1256c6b9ef57SSakthivel K 1257f5860992SSakthivel K /** 1258f5860992SSakthivel K * mpi_ssp_completion- process the event that FW response to the SSP request. 1259f5860992SSakthivel K * @pm8001_ha: our hba card information 1260f5860992SSakthivel K * @piomb: the message contents of this outbound message. 1261f5860992SSakthivel K * 1262f5860992SSakthivel K * When FW has completed a ssp request for example a IO request, after it has 1263f5860992SSakthivel K * filled the SG data with the data, it will trigger this event represent 1264f5860992SSakthivel K * that he has finished the job,please check the coresponding buffer. 1265f5860992SSakthivel K * So we will tell the caller who maybe waiting the result to tell upper layer 1266f5860992SSakthivel K * that the task has been finished. 1267f5860992SSakthivel K */ 1268f5860992SSakthivel K static void 1269f5860992SSakthivel K mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1270f5860992SSakthivel K { 1271f5860992SSakthivel K struct sas_task *t; 1272f5860992SSakthivel K struct pm8001_ccb_info *ccb; 1273f5860992SSakthivel K unsigned long flags; 1274f5860992SSakthivel K u32 status; 1275f5860992SSakthivel K u32 param; 1276f5860992SSakthivel K u32 tag; 1277f5860992SSakthivel K struct ssp_completion_resp *psspPayload; 1278f5860992SSakthivel K struct task_status_struct *ts; 1279f5860992SSakthivel K struct ssp_response_iu *iu; 1280f5860992SSakthivel K struct pm8001_device *pm8001_dev; 1281f5860992SSakthivel K psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1282f5860992SSakthivel K status = le32_to_cpu(psspPayload->status); 1283f5860992SSakthivel K tag = le32_to_cpu(psspPayload->tag); 1284f5860992SSakthivel K ccb = &pm8001_ha->ccb_info[tag]; 1285f5860992SSakthivel K if ((status == IO_ABORTED) && ccb->open_retry) { 1286f5860992SSakthivel K /* Being completed by another */ 1287f5860992SSakthivel K ccb->open_retry = 0; 1288f5860992SSakthivel K return; 1289f5860992SSakthivel K } 1290f5860992SSakthivel K pm8001_dev = ccb->device; 1291f5860992SSakthivel K param = le32_to_cpu(psspPayload->param); 1292f5860992SSakthivel K t = ccb->task; 1293f5860992SSakthivel K 1294f5860992SSakthivel K if (status && status != IO_UNDERFLOW) 1295f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 1296f5860992SSakthivel K pm8001_printk("sas IO status 0x%x\n", status)); 1297f5860992SSakthivel K if (unlikely(!t || !t->lldd_task || !t->dev)) 1298f5860992SSakthivel K return; 1299f5860992SSakthivel K ts = &t->task_status; 1300cb269c26SAnand Kumar Santhanam /* Print sas address of IO failed device */ 1301cb269c26SAnand Kumar Santhanam if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1302cb269c26SAnand Kumar Santhanam (status != IO_UNDERFLOW)) 1303cb269c26SAnand Kumar Santhanam PM8001_FAIL_DBG(pm8001_ha, 1304cb269c26SAnand Kumar Santhanam pm8001_printk("SAS Address of IO Failure Drive" 1305cb269c26SAnand Kumar Santhanam ":%016llx", SAS_ADDR(t->dev->sas_addr))); 1306cb269c26SAnand Kumar Santhanam 1307f5860992SSakthivel K switch (status) { 1308f5860992SSakthivel K case IO_SUCCESS: 1309f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1310f5860992SSakthivel K pm8001_printk("IO_SUCCESS ,param = 0x%x\n", 1311f5860992SSakthivel K param)); 1312f5860992SSakthivel K if (param == 0) { 1313f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1314f5860992SSakthivel K ts->stat = SAM_STAT_GOOD; 1315f5860992SSakthivel K } else { 1316f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1317f5860992SSakthivel K ts->stat = SAS_PROTO_RESPONSE; 1318f5860992SSakthivel K ts->residual = param; 1319f5860992SSakthivel K iu = &psspPayload->ssp_resp_iu; 1320f5860992SSakthivel K sas_ssp_task_response(pm8001_ha->dev, t, iu); 1321f5860992SSakthivel K } 1322f5860992SSakthivel K if (pm8001_dev) 1323f5860992SSakthivel K pm8001_dev->running_req--; 1324f5860992SSakthivel K break; 1325f5860992SSakthivel K case IO_ABORTED: 1326f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1327f5860992SSakthivel K pm8001_printk("IO_ABORTED IOMB Tag\n")); 1328f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1329f5860992SSakthivel K ts->stat = SAS_ABORTED_TASK; 1330f5860992SSakthivel K break; 1331f5860992SSakthivel K case IO_UNDERFLOW: 1332f5860992SSakthivel K /* SSP Completion with error */ 1333f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1334f5860992SSakthivel K pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n", 1335f5860992SSakthivel K param)); 1336f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1337f5860992SSakthivel K ts->stat = SAS_DATA_UNDERRUN; 1338f5860992SSakthivel K ts->residual = param; 1339f5860992SSakthivel K if (pm8001_dev) 1340f5860992SSakthivel K pm8001_dev->running_req--; 1341f5860992SSakthivel K break; 1342f5860992SSakthivel K case IO_NO_DEVICE: 1343f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1344f5860992SSakthivel K pm8001_printk("IO_NO_DEVICE\n")); 1345f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 1346f5860992SSakthivel K ts->stat = SAS_PHY_DOWN; 1347f5860992SSakthivel K break; 1348f5860992SSakthivel K case IO_XFER_ERROR_BREAK: 1349f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1350f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1351f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1352f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1353f5860992SSakthivel K /* Force the midlayer to retry */ 1354f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1355f5860992SSakthivel K break; 1356f5860992SSakthivel K case IO_XFER_ERROR_PHY_NOT_READY: 1357f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1358f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1359f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1360f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1361f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1362f5860992SSakthivel K break; 1363f5860992SSakthivel K case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1364f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1365f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1366f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1367f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1368f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_EPROTO; 1369f5860992SSakthivel K break; 1370f5860992SSakthivel K case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1371f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1372f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1373f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1374f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1375f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1376f5860992SSakthivel K break; 1377f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BREAK: 1378f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1379f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1380f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1381f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1382f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1383f5860992SSakthivel K break; 1384f5860992SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1385a6cb3d01SSakthivel K case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 1386a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 1387a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 1388a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 1389a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 1390f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1391f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1392f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1393f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1394f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1395f5860992SSakthivel K if (!t->uldd_task) 1396f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 1397f5860992SSakthivel K pm8001_dev, 1398f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1399f5860992SSakthivel K break; 1400f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1401f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1402f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1403f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1404f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1405f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1406f5860992SSakthivel K break; 1407f5860992SSakthivel K case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1408f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1409f5860992SSakthivel K "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 1410f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1411f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1412f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1413f5860992SSakthivel K break; 1414f5860992SSakthivel K case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1415f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1416f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1417f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 1418f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1419f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1420f5860992SSakthivel K break; 1421f5860992SSakthivel K case IO_XFER_ERROR_NAK_RECEIVED: 1422f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1423f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 1424f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1425f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1426f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1427f5860992SSakthivel K break; 1428f5860992SSakthivel K case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1429f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1430f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 1431f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1432f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 1433f5860992SSakthivel K break; 1434f5860992SSakthivel K case IO_XFER_ERROR_DMA: 1435f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1436f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_DMA\n")); 1437f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1438f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1439f5860992SSakthivel K break; 1440f5860992SSakthivel K case IO_XFER_OPEN_RETRY_TIMEOUT: 1441f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1442f5860992SSakthivel K pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1443f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1444f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1445f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1446f5860992SSakthivel K break; 1447f5860992SSakthivel K case IO_XFER_ERROR_OFFSET_MISMATCH: 1448f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1449f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 1450f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1451f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1452f5860992SSakthivel K break; 1453f5860992SSakthivel K case IO_PORT_IN_RESET: 1454f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1455f5860992SSakthivel K pm8001_printk("IO_PORT_IN_RESET\n")); 1456f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1457f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1458f5860992SSakthivel K break; 1459f5860992SSakthivel K case IO_DS_NON_OPERATIONAL: 1460f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1461f5860992SSakthivel K pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 1462f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1463f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1464f5860992SSakthivel K if (!t->uldd_task) 1465f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 1466f5860992SSakthivel K pm8001_dev, 1467f5860992SSakthivel K IO_DS_NON_OPERATIONAL); 1468f5860992SSakthivel K break; 1469f5860992SSakthivel K case IO_DS_IN_RECOVERY: 1470f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1471f5860992SSakthivel K pm8001_printk("IO_DS_IN_RECOVERY\n")); 1472f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1473f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1474f5860992SSakthivel K break; 1475f5860992SSakthivel K case IO_TM_TAG_NOT_FOUND: 1476f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1477f5860992SSakthivel K pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); 1478f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1479f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1480f5860992SSakthivel K break; 1481f5860992SSakthivel K case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 1482f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1483f5860992SSakthivel K pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); 1484f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1485f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1486f5860992SSakthivel K break; 1487f5860992SSakthivel K case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 1488f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1489f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 1490f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1491f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1492f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1493f5860992SSakthivel K break; 1494f5860992SSakthivel K default: 1495f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1496f5860992SSakthivel K pm8001_printk("Unknown status 0x%x\n", status)); 1497f5860992SSakthivel K /* not allowed case. Therefore, return failed status */ 1498f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1499f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1500f5860992SSakthivel K break; 1501f5860992SSakthivel K } 1502f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1503f5860992SSakthivel K pm8001_printk("scsi_status = 0x%x\n ", 1504f5860992SSakthivel K psspPayload->ssp_resp_iu.status)); 1505f5860992SSakthivel K spin_lock_irqsave(&t->task_state_lock, flags); 1506f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1507f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1508f5860992SSakthivel K t->task_state_flags |= SAS_TASK_STATE_DONE; 1509f5860992SSakthivel K if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1510f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 1511f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1512f5860992SSakthivel K "task 0x%p done with io_status 0x%x resp 0x%x " 1513f5860992SSakthivel K "stat 0x%x but aborted by upper layer!\n", 1514f5860992SSakthivel K t, status, ts->resp, ts->stat)); 1515f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1516f5860992SSakthivel K } else { 1517f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 1518f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1519f5860992SSakthivel K mb();/* in order to force CPU ordering */ 1520f5860992SSakthivel K t->task_done(t); 1521f5860992SSakthivel K } 1522f5860992SSakthivel K } 1523f5860992SSakthivel K 1524f5860992SSakthivel K /*See the comments for mpi_ssp_completion */ 1525f5860992SSakthivel K static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 1526f5860992SSakthivel K { 1527f5860992SSakthivel K struct sas_task *t; 1528f5860992SSakthivel K unsigned long flags; 1529f5860992SSakthivel K struct task_status_struct *ts; 1530f5860992SSakthivel K struct pm8001_ccb_info *ccb; 1531f5860992SSakthivel K struct pm8001_device *pm8001_dev; 1532f5860992SSakthivel K struct ssp_event_resp *psspPayload = 1533f5860992SSakthivel K (struct ssp_event_resp *)(piomb + 4); 1534f5860992SSakthivel K u32 event = le32_to_cpu(psspPayload->event); 1535f5860992SSakthivel K u32 tag = le32_to_cpu(psspPayload->tag); 1536f5860992SSakthivel K u32 port_id = le32_to_cpu(psspPayload->port_id); 1537f5860992SSakthivel K 1538f5860992SSakthivel K ccb = &pm8001_ha->ccb_info[tag]; 1539f5860992SSakthivel K t = ccb->task; 1540f5860992SSakthivel K pm8001_dev = ccb->device; 1541f5860992SSakthivel K if (event) 1542f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 1543f5860992SSakthivel K pm8001_printk("sas IO status 0x%x\n", event)); 1544f5860992SSakthivel K if (unlikely(!t || !t->lldd_task || !t->dev)) 1545f5860992SSakthivel K return; 1546f5860992SSakthivel K ts = &t->task_status; 1547f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1548f5860992SSakthivel K pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n", 1549f5860992SSakthivel K port_id, tag, event)); 1550f5860992SSakthivel K switch (event) { 1551f5860992SSakthivel K case IO_OVERFLOW: 1552f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) 1553f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1554f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 1555f5860992SSakthivel K ts->residual = 0; 1556f5860992SSakthivel K if (pm8001_dev) 1557f5860992SSakthivel K pm8001_dev->running_req--; 1558f5860992SSakthivel K break; 1559f5860992SSakthivel K case IO_XFER_ERROR_BREAK: 1560f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1561f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1562f5860992SSakthivel K pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 1563f5860992SSakthivel K return; 1564f5860992SSakthivel K case IO_XFER_ERROR_PHY_NOT_READY: 1565f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1566f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1567f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1568f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1569f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1570f5860992SSakthivel K break; 1571f5860992SSakthivel K case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1572f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1573f5860992SSakthivel K "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1574f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1575f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1576f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_EPROTO; 1577f5860992SSakthivel K break; 1578f5860992SSakthivel K case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1579f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1580f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1581f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1582f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1583f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1584f5860992SSakthivel K break; 1585f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BREAK: 1586f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1587f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1588f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1589f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1590f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1591f5860992SSakthivel K break; 1592f5860992SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1593a6cb3d01SSakthivel K case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 1594a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 1595a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 1596a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 1597a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 1598f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1599f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1600f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1601f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1602f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1603f5860992SSakthivel K if (!t->uldd_task) 1604f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 1605f5860992SSakthivel K pm8001_dev, 1606f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1607f5860992SSakthivel K break; 1608f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1609f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1610f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1611f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1612f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1613f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1614f5860992SSakthivel K break; 1615f5860992SSakthivel K case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1616f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1617f5860992SSakthivel K "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 1618f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1619f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1620f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1621f5860992SSakthivel K break; 1622f5860992SSakthivel K case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1623f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1624f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1625f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1626f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1627f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1628f5860992SSakthivel K break; 1629f5860992SSakthivel K case IO_XFER_ERROR_NAK_RECEIVED: 1630f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1631f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 1632f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1633f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1634f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1635f5860992SSakthivel K break; 1636f5860992SSakthivel K case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1637f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1638f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 1639f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1640f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 1641f5860992SSakthivel K break; 1642f5860992SSakthivel K case IO_XFER_OPEN_RETRY_TIMEOUT: 1643f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1644f5860992SSakthivel K pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1645f5860992SSakthivel K pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 1646f5860992SSakthivel K return; 1647f5860992SSakthivel K case IO_XFER_ERROR_UNEXPECTED_PHASE: 1648f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1649f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 1650f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1651f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 1652f5860992SSakthivel K break; 1653f5860992SSakthivel K case IO_XFER_ERROR_XFER_RDY_OVERRUN: 1654f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1655f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 1656f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1657f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 1658f5860992SSakthivel K break; 1659f5860992SSakthivel K case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 1660f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1661f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 1662f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1663f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 1664f5860992SSakthivel K break; 1665f5860992SSakthivel K case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 1666f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1667f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); 1668f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1669f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 1670f5860992SSakthivel K break; 1671f5860992SSakthivel K case IO_XFER_ERROR_OFFSET_MISMATCH: 1672f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1673f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 1674f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1675f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 1676f5860992SSakthivel K break; 1677f5860992SSakthivel K case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 1678f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1679f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 1680f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1681f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 1682f5860992SSakthivel K break; 1683a6cb3d01SSakthivel K case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 1684a6cb3d01SSakthivel K PM8001_IO_DBG(pm8001_ha, 1685a6cb3d01SSakthivel K pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n")); 1686a6cb3d01SSakthivel K /* TBC: used default set values */ 1687a6cb3d01SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1688a6cb3d01SSakthivel K ts->stat = SAS_DATA_OVERRUN; 1689a6cb3d01SSakthivel K break; 1690f5860992SSakthivel K case IO_XFER_CMD_FRAME_ISSUED: 1691f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1692f5860992SSakthivel K pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 1693f5860992SSakthivel K return; 1694f5860992SSakthivel K default: 1695f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1696f5860992SSakthivel K pm8001_printk("Unknown status 0x%x\n", event)); 1697f5860992SSakthivel K /* not allowed case. Therefore, return failed status */ 1698f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1699f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 1700f5860992SSakthivel K break; 1701f5860992SSakthivel K } 1702f5860992SSakthivel K spin_lock_irqsave(&t->task_state_lock, flags); 1703f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1704f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1705f5860992SSakthivel K t->task_state_flags |= SAS_TASK_STATE_DONE; 1706f5860992SSakthivel K if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1707f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 1708f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1709f5860992SSakthivel K "task 0x%p done with event 0x%x resp 0x%x " 1710f5860992SSakthivel K "stat 0x%x but aborted by upper layer!\n", 1711f5860992SSakthivel K t, event, ts->resp, ts->stat)); 1712f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1713f5860992SSakthivel K } else { 1714f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 1715f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1716f5860992SSakthivel K mb();/* in order to force CPU ordering */ 1717f5860992SSakthivel K t->task_done(t); 1718f5860992SSakthivel K } 1719f5860992SSakthivel K } 1720f5860992SSakthivel K 1721f5860992SSakthivel K /*See the comments for mpi_ssp_completion */ 1722f5860992SSakthivel K static void 1723f5860992SSakthivel K mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 1724f5860992SSakthivel K { 1725f5860992SSakthivel K struct sas_task *t; 1726f5860992SSakthivel K struct pm8001_ccb_info *ccb; 1727f5860992SSakthivel K u32 param; 1728f5860992SSakthivel K u32 status; 1729f5860992SSakthivel K u32 tag; 1730cb269c26SAnand Kumar Santhanam int i, j; 1731cb269c26SAnand Kumar Santhanam u8 sata_addr_low[4]; 1732cb269c26SAnand Kumar Santhanam u32 temp_sata_addr_low, temp_sata_addr_hi; 1733cb269c26SAnand Kumar Santhanam u8 sata_addr_hi[4]; 1734f5860992SSakthivel K struct sata_completion_resp *psataPayload; 1735f5860992SSakthivel K struct task_status_struct *ts; 1736f5860992SSakthivel K struct ata_task_resp *resp ; 1737f5860992SSakthivel K u32 *sata_resp; 1738f5860992SSakthivel K struct pm8001_device *pm8001_dev; 1739c6b9ef57SSakthivel K unsigned long flags; 1740f5860992SSakthivel K 1741f5860992SSakthivel K psataPayload = (struct sata_completion_resp *)(piomb + 4); 1742f5860992SSakthivel K status = le32_to_cpu(psataPayload->status); 1743f5860992SSakthivel K tag = le32_to_cpu(psataPayload->tag); 1744f5860992SSakthivel K 1745c6b9ef57SSakthivel K if (!tag) { 1746c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 1747c6b9ef57SSakthivel K pm8001_printk("tag null\n")); 1748c6b9ef57SSakthivel K return; 1749c6b9ef57SSakthivel K } 1750f5860992SSakthivel K ccb = &pm8001_ha->ccb_info[tag]; 1751f5860992SSakthivel K param = le32_to_cpu(psataPayload->param); 1752c6b9ef57SSakthivel K if (ccb) { 1753f5860992SSakthivel K t = ccb->task; 1754f5860992SSakthivel K pm8001_dev = ccb->device; 1755c6b9ef57SSakthivel K } else { 1756f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 1757c6b9ef57SSakthivel K pm8001_printk("ccb null\n")); 1758f5860992SSakthivel K return; 1759c6b9ef57SSakthivel K } 1760c6b9ef57SSakthivel K 1761c6b9ef57SSakthivel K if (t) { 1762c6b9ef57SSakthivel K if (t->dev && (t->dev->lldd_dev)) 1763c6b9ef57SSakthivel K pm8001_dev = t->dev->lldd_dev; 1764c6b9ef57SSakthivel K } else { 1765c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 1766c6b9ef57SSakthivel K pm8001_printk("task null\n")); 1767c6b9ef57SSakthivel K return; 1768c6b9ef57SSakthivel K } 1769c6b9ef57SSakthivel K 1770c6b9ef57SSakthivel K if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) 1771c6b9ef57SSakthivel K && unlikely(!t || !t->lldd_task || !t->dev)) { 1772c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 1773c6b9ef57SSakthivel K pm8001_printk("task or dev null\n")); 1774c6b9ef57SSakthivel K return; 1775c6b9ef57SSakthivel K } 1776c6b9ef57SSakthivel K 1777c6b9ef57SSakthivel K ts = &t->task_status; 1778c6b9ef57SSakthivel K if (!ts) { 1779c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 1780c6b9ef57SSakthivel K pm8001_printk("ts null\n")); 1781c6b9ef57SSakthivel K return; 1782c6b9ef57SSakthivel K } 1783cb269c26SAnand Kumar Santhanam /* Print sas address of IO failed device */ 1784cb269c26SAnand Kumar Santhanam if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && 1785cb269c26SAnand Kumar Santhanam (status != IO_UNDERFLOW)) { 1786cb269c26SAnand Kumar Santhanam if (!((t->dev->parent) && 1787cb269c26SAnand Kumar Santhanam (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) { 1788cb269c26SAnand Kumar Santhanam for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++) 1789cb269c26SAnand Kumar Santhanam sata_addr_low[i] = pm8001_ha->sas_addr[j]; 1790cb269c26SAnand Kumar Santhanam for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++) 1791cb269c26SAnand Kumar Santhanam sata_addr_hi[i] = pm8001_ha->sas_addr[j]; 1792cb269c26SAnand Kumar Santhanam memcpy(&temp_sata_addr_low, sata_addr_low, 1793cb269c26SAnand Kumar Santhanam sizeof(sata_addr_low)); 1794cb269c26SAnand Kumar Santhanam memcpy(&temp_sata_addr_hi, sata_addr_hi, 1795cb269c26SAnand Kumar Santhanam sizeof(sata_addr_hi)); 1796cb269c26SAnand Kumar Santhanam temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) 1797cb269c26SAnand Kumar Santhanam |((temp_sata_addr_hi << 8) & 1798cb269c26SAnand Kumar Santhanam 0xff0000) | 1799cb269c26SAnand Kumar Santhanam ((temp_sata_addr_hi >> 8) 1800cb269c26SAnand Kumar Santhanam & 0xff00) | 1801cb269c26SAnand Kumar Santhanam ((temp_sata_addr_hi << 24) & 1802cb269c26SAnand Kumar Santhanam 0xff000000)); 1803cb269c26SAnand Kumar Santhanam temp_sata_addr_low = ((((temp_sata_addr_low >> 24) 1804cb269c26SAnand Kumar Santhanam & 0xff) | 1805cb269c26SAnand Kumar Santhanam ((temp_sata_addr_low << 8) 1806cb269c26SAnand Kumar Santhanam & 0xff0000) | 1807cb269c26SAnand Kumar Santhanam ((temp_sata_addr_low >> 8) 1808cb269c26SAnand Kumar Santhanam & 0xff00) | 1809cb269c26SAnand Kumar Santhanam ((temp_sata_addr_low << 24) 1810cb269c26SAnand Kumar Santhanam & 0xff000000)) + 1811cb269c26SAnand Kumar Santhanam pm8001_dev->attached_phy + 1812cb269c26SAnand Kumar Santhanam 0x10); 1813cb269c26SAnand Kumar Santhanam PM8001_FAIL_DBG(pm8001_ha, 1814cb269c26SAnand Kumar Santhanam pm8001_printk("SAS Address of IO Failure Drive:" 1815cb269c26SAnand Kumar Santhanam "%08x%08x", temp_sata_addr_hi, 1816cb269c26SAnand Kumar Santhanam temp_sata_addr_low)); 1817f5860992SSakthivel K 1818cb269c26SAnand Kumar Santhanam } else { 1819cb269c26SAnand Kumar Santhanam PM8001_FAIL_DBG(pm8001_ha, 1820cb269c26SAnand Kumar Santhanam pm8001_printk("SAS Address of IO Failure Drive:" 1821cb269c26SAnand Kumar Santhanam "%016llx", SAS_ADDR(t->dev->sas_addr))); 1822cb269c26SAnand Kumar Santhanam } 1823cb269c26SAnand Kumar Santhanam } 1824f5860992SSakthivel K switch (status) { 1825f5860992SSakthivel K case IO_SUCCESS: 1826f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 1827f5860992SSakthivel K if (param == 0) { 1828f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1829f5860992SSakthivel K ts->stat = SAM_STAT_GOOD; 1830c6b9ef57SSakthivel K /* check if response is for SEND READ LOG */ 1831c6b9ef57SSakthivel K if (pm8001_dev && 1832c6b9ef57SSakthivel K (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { 1833c6b9ef57SSakthivel K /* set new bit for abort_all */ 1834c6b9ef57SSakthivel K pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; 1835c6b9ef57SSakthivel K /* clear bit for read log */ 1836c6b9ef57SSakthivel K pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; 1837c6b9ef57SSakthivel K pm80xx_send_abort_all(pm8001_ha, pm8001_dev); 1838c6b9ef57SSakthivel K /* Free the tag */ 1839c6b9ef57SSakthivel K pm8001_tag_free(pm8001_ha, tag); 1840c6b9ef57SSakthivel K sas_free_task(t); 1841c6b9ef57SSakthivel K return; 1842c6b9ef57SSakthivel K } 1843f5860992SSakthivel K } else { 1844f5860992SSakthivel K u8 len; 1845f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1846f5860992SSakthivel K ts->stat = SAS_PROTO_RESPONSE; 1847f5860992SSakthivel K ts->residual = param; 1848f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1849f5860992SSakthivel K pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", 1850f5860992SSakthivel K param)); 1851f5860992SSakthivel K sata_resp = &psataPayload->sata_resp[0]; 1852f5860992SSakthivel K resp = (struct ata_task_resp *)ts->buf; 1853f5860992SSakthivel K if (t->ata_task.dma_xfer == 0 && 1854f5860992SSakthivel K t->data_dir == PCI_DMA_FROMDEVICE) { 1855f5860992SSakthivel K len = sizeof(struct pio_setup_fis); 1856f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1857f5860992SSakthivel K pm8001_printk("PIO read len = %d\n", len)); 1858f5860992SSakthivel K } else if (t->ata_task.use_ncq) { 1859f5860992SSakthivel K len = sizeof(struct set_dev_bits_fis); 1860f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1861f5860992SSakthivel K pm8001_printk("FPDMA len = %d\n", len)); 1862f5860992SSakthivel K } else { 1863f5860992SSakthivel K len = sizeof(struct dev_to_host_fis); 1864f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1865f5860992SSakthivel K pm8001_printk("other len = %d\n", len)); 1866f5860992SSakthivel K } 1867f5860992SSakthivel K if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 1868f5860992SSakthivel K resp->frame_len = len; 1869f5860992SSakthivel K memcpy(&resp->ending_fis[0], sata_resp, len); 1870f5860992SSakthivel K ts->buf_valid_size = sizeof(*resp); 1871f5860992SSakthivel K } else 1872f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1873f5860992SSakthivel K pm8001_printk("response to large\n")); 1874f5860992SSakthivel K } 1875f5860992SSakthivel K if (pm8001_dev) 1876f5860992SSakthivel K pm8001_dev->running_req--; 1877f5860992SSakthivel K break; 1878f5860992SSakthivel K case IO_ABORTED: 1879f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1880f5860992SSakthivel K pm8001_printk("IO_ABORTED IOMB Tag\n")); 1881f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1882f5860992SSakthivel K ts->stat = SAS_ABORTED_TASK; 1883f5860992SSakthivel K if (pm8001_dev) 1884f5860992SSakthivel K pm8001_dev->running_req--; 1885f5860992SSakthivel K break; 1886f5860992SSakthivel K /* following cases are to do cases */ 1887f5860992SSakthivel K case IO_UNDERFLOW: 1888f5860992SSakthivel K /* SATA Completion with error */ 1889f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1890f5860992SSakthivel K pm8001_printk("IO_UNDERFLOW param = %d\n", param)); 1891f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1892f5860992SSakthivel K ts->stat = SAS_DATA_UNDERRUN; 1893f5860992SSakthivel K ts->residual = param; 1894f5860992SSakthivel K if (pm8001_dev) 1895f5860992SSakthivel K pm8001_dev->running_req--; 1896f5860992SSakthivel K break; 1897f5860992SSakthivel K case IO_NO_DEVICE: 1898f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1899f5860992SSakthivel K pm8001_printk("IO_NO_DEVICE\n")); 1900f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 1901f5860992SSakthivel K ts->stat = SAS_PHY_DOWN; 1902f5860992SSakthivel K break; 1903f5860992SSakthivel K case IO_XFER_ERROR_BREAK: 1904f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1905f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1906f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1907f5860992SSakthivel K ts->stat = SAS_INTERRUPTED; 1908f5860992SSakthivel K break; 1909f5860992SSakthivel K case IO_XFER_ERROR_PHY_NOT_READY: 1910f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1911f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1912f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1913f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1914f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1915f5860992SSakthivel K break; 1916f5860992SSakthivel K case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1917f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1918f5860992SSakthivel K "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1919f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1920f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1921f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_EPROTO; 1922f5860992SSakthivel K break; 1923f5860992SSakthivel K case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1924f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1925f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1926f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1927f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1928f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1929f5860992SSakthivel K break; 1930f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BREAK: 1931f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1932f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1933f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1934f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1935f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 1936f5860992SSakthivel K break; 1937f5860992SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1938a6cb3d01SSakthivel K case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 1939a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 1940a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 1941a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 1942a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 1943f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1944f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1945f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1946f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 1947f5860992SSakthivel K if (!t->uldd_task) { 1948f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 1949f5860992SSakthivel K pm8001_dev, 1950f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1951f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 1952f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 1953f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1954f5860992SSakthivel K mb();/*in order to force CPU ordering*/ 1955f5860992SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 1956f5860992SSakthivel K t->task_done(t); 1957f5860992SSakthivel K spin_lock_irq(&pm8001_ha->lock); 1958f5860992SSakthivel K return; 1959f5860992SSakthivel K } 1960f5860992SSakthivel K break; 1961f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1962f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 1963f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1964f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 1965f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1966f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1967f5860992SSakthivel K if (!t->uldd_task) { 1968f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 1969f5860992SSakthivel K pm8001_dev, 1970f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1971f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 1972f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 1973f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1974f5860992SSakthivel K mb();/*ditto*/ 1975f5860992SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 1976f5860992SSakthivel K t->task_done(t); 1977f5860992SSakthivel K spin_lock_irq(&pm8001_ha->lock); 1978f5860992SSakthivel K return; 1979f5860992SSakthivel K } 1980f5860992SSakthivel K break; 1981f5860992SSakthivel K case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1982f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1983f5860992SSakthivel K "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 1984f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1985f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 1986f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1987f5860992SSakthivel K break; 1988f5860992SSakthivel K case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 1989f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 1990f5860992SSakthivel K "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n")); 1991f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 1992f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 1993f5860992SSakthivel K if (!t->uldd_task) { 1994f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 1995f5860992SSakthivel K pm8001_dev, 1996f5860992SSakthivel K IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 1997f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 1998f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 1999f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2000f5860992SSakthivel K mb();/* ditto*/ 2001f5860992SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 2002f5860992SSakthivel K t->task_done(t); 2003f5860992SSakthivel K spin_lock_irq(&pm8001_ha->lock); 2004f5860992SSakthivel K return; 2005f5860992SSakthivel K } 2006f5860992SSakthivel K break; 2007f5860992SSakthivel K case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2008f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2009f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2010f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2011f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2012f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2013f5860992SSakthivel K break; 2014f5860992SSakthivel K case IO_XFER_ERROR_NAK_RECEIVED: 2015f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2016f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2017f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2018f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 2019f5860992SSakthivel K break; 2020f5860992SSakthivel K case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2021f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2022f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2023f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2024f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 2025f5860992SSakthivel K break; 2026f5860992SSakthivel K case IO_XFER_ERROR_DMA: 2027f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2028f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_DMA\n")); 2029f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2030f5860992SSakthivel K ts->stat = SAS_ABORTED_TASK; 2031f5860992SSakthivel K break; 2032f5860992SSakthivel K case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2033f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2034f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); 2035f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2036f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2037f5860992SSakthivel K break; 2038f5860992SSakthivel K case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2039f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2040f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2041f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2042f5860992SSakthivel K ts->stat = SAS_DATA_UNDERRUN; 2043f5860992SSakthivel K break; 2044f5860992SSakthivel K case IO_XFER_OPEN_RETRY_TIMEOUT: 2045f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2046f5860992SSakthivel K pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2047f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2048f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2049f5860992SSakthivel K break; 2050f5860992SSakthivel K case IO_PORT_IN_RESET: 2051f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2052f5860992SSakthivel K pm8001_printk("IO_PORT_IN_RESET\n")); 2053f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2054f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2055f5860992SSakthivel K break; 2056f5860992SSakthivel K case IO_DS_NON_OPERATIONAL: 2057f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2058f5860992SSakthivel K pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2059f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2060f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2061f5860992SSakthivel K if (!t->uldd_task) { 2062f5860992SSakthivel K pm8001_handle_event(pm8001_ha, pm8001_dev, 2063f5860992SSakthivel K IO_DS_NON_OPERATIONAL); 2064f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2065f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 2066f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2067f5860992SSakthivel K mb();/*ditto*/ 2068f5860992SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 2069f5860992SSakthivel K t->task_done(t); 2070f5860992SSakthivel K spin_lock_irq(&pm8001_ha->lock); 2071f5860992SSakthivel K return; 2072f5860992SSakthivel K } 2073f5860992SSakthivel K break; 2074f5860992SSakthivel K case IO_DS_IN_RECOVERY: 2075f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2076f5860992SSakthivel K pm8001_printk("IO_DS_IN_RECOVERY\n")); 2077f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2078f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2079f5860992SSakthivel K break; 2080f5860992SSakthivel K case IO_DS_IN_ERROR: 2081f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2082f5860992SSakthivel K pm8001_printk("IO_DS_IN_ERROR\n")); 2083f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2084f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2085f5860992SSakthivel K if (!t->uldd_task) { 2086f5860992SSakthivel K pm8001_handle_event(pm8001_ha, pm8001_dev, 2087f5860992SSakthivel K IO_DS_IN_ERROR); 2088f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2089f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 2090f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2091f5860992SSakthivel K mb();/*ditto*/ 2092f5860992SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 2093f5860992SSakthivel K t->task_done(t); 2094f5860992SSakthivel K spin_lock_irq(&pm8001_ha->lock); 2095f5860992SSakthivel K return; 2096f5860992SSakthivel K } 2097f5860992SSakthivel K break; 2098f5860992SSakthivel K case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2099f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2100f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2101f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2102f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2103f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2104f5860992SSakthivel K default: 2105f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2106f5860992SSakthivel K pm8001_printk("Unknown status 0x%x\n", status)); 2107f5860992SSakthivel K /* not allowed case. Therefore, return failed status */ 2108f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2109f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2110f5860992SSakthivel K break; 2111f5860992SSakthivel K } 2112f5860992SSakthivel K spin_lock_irqsave(&t->task_state_lock, flags); 2113f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2114f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2115f5860992SSakthivel K t->task_state_flags |= SAS_TASK_STATE_DONE; 2116f5860992SSakthivel K if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2117f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 2118f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 2119f5860992SSakthivel K pm8001_printk("task 0x%p done with io_status 0x%x" 2120f5860992SSakthivel K " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2121f5860992SSakthivel K t, status, ts->resp, ts->stat)); 2122f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2123f5860992SSakthivel K } else if (t->uldd_task) { 2124f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 2125f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2126f5860992SSakthivel K mb();/* ditto */ 2127f5860992SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 2128f5860992SSakthivel K t->task_done(t); 2129f5860992SSakthivel K spin_lock_irq(&pm8001_ha->lock); 2130f5860992SSakthivel K } else if (!t->uldd_task) { 2131f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 2132f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2133f5860992SSakthivel K mb();/*ditto*/ 2134f5860992SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 2135f5860992SSakthivel K t->task_done(t); 2136f5860992SSakthivel K spin_lock_irq(&pm8001_ha->lock); 2137f5860992SSakthivel K } 2138f5860992SSakthivel K } 2139f5860992SSakthivel K 2140f5860992SSakthivel K /*See the comments for mpi_ssp_completion */ 2141f5860992SSakthivel K static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2142f5860992SSakthivel K { 2143f5860992SSakthivel K struct sas_task *t; 2144f5860992SSakthivel K struct task_status_struct *ts; 2145f5860992SSakthivel K struct pm8001_ccb_info *ccb; 2146f5860992SSakthivel K struct pm8001_device *pm8001_dev; 2147f5860992SSakthivel K struct sata_event_resp *psataPayload = 2148f5860992SSakthivel K (struct sata_event_resp *)(piomb + 4); 2149f5860992SSakthivel K u32 event = le32_to_cpu(psataPayload->event); 2150f5860992SSakthivel K u32 tag = le32_to_cpu(psataPayload->tag); 2151f5860992SSakthivel K u32 port_id = le32_to_cpu(psataPayload->port_id); 2152c6b9ef57SSakthivel K u32 dev_id = le32_to_cpu(psataPayload->device_id); 2153c6b9ef57SSakthivel K unsigned long flags; 2154f5860992SSakthivel K 2155f5860992SSakthivel K ccb = &pm8001_ha->ccb_info[tag]; 2156c6b9ef57SSakthivel K 2157c6b9ef57SSakthivel K if (ccb) { 2158f5860992SSakthivel K t = ccb->task; 2159f5860992SSakthivel K pm8001_dev = ccb->device; 2160c6b9ef57SSakthivel K } else { 2161c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 2162c6b9ef57SSakthivel K pm8001_printk("No CCB !!!. returning\n")); 2163c6b9ef57SSakthivel K return; 2164c6b9ef57SSakthivel K } 2165f5860992SSakthivel K if (event) 2166f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 2167c6b9ef57SSakthivel K pm8001_printk("SATA EVENT 0x%x\n", event)); 2168c6b9ef57SSakthivel K 2169c6b9ef57SSakthivel K /* Check if this is NCQ error */ 2170c6b9ef57SSakthivel K if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { 2171c6b9ef57SSakthivel K /* find device using device id */ 2172c6b9ef57SSakthivel K pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); 2173c6b9ef57SSakthivel K /* send read log extension */ 2174c6b9ef57SSakthivel K if (pm8001_dev) 2175c6b9ef57SSakthivel K pm80xx_send_read_log(pm8001_ha, pm8001_dev); 2176f5860992SSakthivel K return; 2177c6b9ef57SSakthivel K } 2178c6b9ef57SSakthivel K 2179c6b9ef57SSakthivel K if (unlikely(!t || !t->lldd_task || !t->dev)) { 2180c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 2181c6b9ef57SSakthivel K pm8001_printk("task or dev null\n")); 2182c6b9ef57SSakthivel K return; 2183c6b9ef57SSakthivel K } 2184c6b9ef57SSakthivel K 2185f5860992SSakthivel K ts = &t->task_status; 2186f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2187f5860992SSakthivel K pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n", 2188f5860992SSakthivel K port_id, tag, event)); 2189f5860992SSakthivel K switch (event) { 2190f5860992SSakthivel K case IO_OVERFLOW: 2191f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2192f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2193f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2194f5860992SSakthivel K ts->residual = 0; 2195f5860992SSakthivel K if (pm8001_dev) 2196f5860992SSakthivel K pm8001_dev->running_req--; 2197f5860992SSakthivel K break; 2198f5860992SSakthivel K case IO_XFER_ERROR_BREAK: 2199f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2200f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2201f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2202f5860992SSakthivel K ts->stat = SAS_INTERRUPTED; 2203f5860992SSakthivel K break; 2204f5860992SSakthivel K case IO_XFER_ERROR_PHY_NOT_READY: 2205f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2206f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2207f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2208f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2209f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2210f5860992SSakthivel K break; 2211f5860992SSakthivel K case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2212f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2213f5860992SSakthivel K "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2214f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2215f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2216f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_EPROTO; 2217f5860992SSakthivel K break; 2218f5860992SSakthivel K case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2219f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2220f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2221f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2222f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2223f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2224f5860992SSakthivel K break; 2225f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BREAK: 2226f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2227f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2228f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2229f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2230f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2231f5860992SSakthivel K break; 2232f5860992SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2233a6cb3d01SSakthivel K case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2234a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2235a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2236a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2237a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2238a6cb3d01SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 2239f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2240f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2241f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2242f5860992SSakthivel K if (!t->uldd_task) { 2243f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 2244f5860992SSakthivel K pm8001_dev, 2245f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2246f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2247f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 2248f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2249f5860992SSakthivel K mb();/*ditto*/ 2250f5860992SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 2251f5860992SSakthivel K t->task_done(t); 2252f5860992SSakthivel K spin_lock_irq(&pm8001_ha->lock); 2253f5860992SSakthivel K return; 2254f5860992SSakthivel K } 2255f5860992SSakthivel K break; 2256f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2257f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2258f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2259f5860992SSakthivel K ts->resp = SAS_TASK_UNDELIVERED; 2260f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2261f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2262f5860992SSakthivel K break; 2263f5860992SSakthivel K case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2264f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2265f5860992SSakthivel K "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2266f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2267f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2268f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2269f5860992SSakthivel K break; 2270f5860992SSakthivel K case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2271f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2272f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2273f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2274f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2275f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2276f5860992SSakthivel K break; 2277f5860992SSakthivel K case IO_XFER_ERROR_NAK_RECEIVED: 2278f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2279f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2280f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2281f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 2282f5860992SSakthivel K break; 2283f5860992SSakthivel K case IO_XFER_ERROR_PEER_ABORTED: 2284f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2285f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); 2286f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2287f5860992SSakthivel K ts->stat = SAS_NAK_R_ERR; 2288f5860992SSakthivel K break; 2289f5860992SSakthivel K case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2290f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2291f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2292f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2293f5860992SSakthivel K ts->stat = SAS_DATA_UNDERRUN; 2294f5860992SSakthivel K break; 2295f5860992SSakthivel K case IO_XFER_OPEN_RETRY_TIMEOUT: 2296f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2297f5860992SSakthivel K pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2298f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2299f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2300f5860992SSakthivel K break; 2301f5860992SSakthivel K case IO_XFER_ERROR_UNEXPECTED_PHASE: 2302f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2303f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2304f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2305f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2306f5860992SSakthivel K break; 2307f5860992SSakthivel K case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2308f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2309f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2310f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2311f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2312f5860992SSakthivel K break; 2313f5860992SSakthivel K case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2314f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2315f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2316f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2317f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2318f5860992SSakthivel K break; 2319f5860992SSakthivel K case IO_XFER_ERROR_OFFSET_MISMATCH: 2320f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2321f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2322f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2323f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2324f5860992SSakthivel K break; 2325f5860992SSakthivel K case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2326f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2327f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2328f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2329f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2330f5860992SSakthivel K break; 2331f5860992SSakthivel K case IO_XFER_CMD_FRAME_ISSUED: 2332f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2333f5860992SSakthivel K pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 2334f5860992SSakthivel K break; 2335f5860992SSakthivel K case IO_XFER_PIO_SETUP_ERROR: 2336f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2337f5860992SSakthivel K pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); 2338f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2339f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2340f5860992SSakthivel K break; 2341a6cb3d01SSakthivel K case IO_XFER_ERROR_INTERNAL_CRC_ERROR: 2342a6cb3d01SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 2343a6cb3d01SSakthivel K pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n")); 2344a6cb3d01SSakthivel K /* TBC: used default set values */ 2345a6cb3d01SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2346a6cb3d01SSakthivel K ts->stat = SAS_OPEN_TO; 2347a6cb3d01SSakthivel K break; 2348a6cb3d01SSakthivel K case IO_XFER_DMA_ACTIVATE_TIMEOUT: 2349a6cb3d01SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 2350a6cb3d01SSakthivel K pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n")); 2351a6cb3d01SSakthivel K /* TBC: used default set values */ 2352a6cb3d01SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2353a6cb3d01SSakthivel K ts->stat = SAS_OPEN_TO; 2354a6cb3d01SSakthivel K break; 2355f5860992SSakthivel K default: 2356f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2357f5860992SSakthivel K pm8001_printk("Unknown status 0x%x\n", event)); 2358f5860992SSakthivel K /* not allowed case. Therefore, return failed status */ 2359f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2360f5860992SSakthivel K ts->stat = SAS_OPEN_TO; 2361f5860992SSakthivel K break; 2362f5860992SSakthivel K } 2363f5860992SSakthivel K spin_lock_irqsave(&t->task_state_lock, flags); 2364f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2365f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2366f5860992SSakthivel K t->task_state_flags |= SAS_TASK_STATE_DONE; 2367f5860992SSakthivel K if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2368f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 2369f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 2370f5860992SSakthivel K pm8001_printk("task 0x%p done with io_status 0x%x" 2371f5860992SSakthivel K " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2372f5860992SSakthivel K t, event, ts->resp, ts->stat)); 2373f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2374f5860992SSakthivel K } else if (t->uldd_task) { 2375f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 2376f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2377f5860992SSakthivel K mb();/* ditto */ 2378f5860992SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 2379f5860992SSakthivel K t->task_done(t); 2380f5860992SSakthivel K spin_lock_irq(&pm8001_ha->lock); 2381f5860992SSakthivel K } else if (!t->uldd_task) { 2382f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 2383f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2384f5860992SSakthivel K mb();/*ditto*/ 2385f5860992SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 2386f5860992SSakthivel K t->task_done(t); 2387f5860992SSakthivel K spin_lock_irq(&pm8001_ha->lock); 2388f5860992SSakthivel K } 2389f5860992SSakthivel K } 2390f5860992SSakthivel K 2391f5860992SSakthivel K /*See the comments for mpi_ssp_completion */ 2392f5860992SSakthivel K static void 2393f5860992SSakthivel K mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2394f5860992SSakthivel K { 2395f5860992SSakthivel K u32 param, i; 2396f5860992SSakthivel K struct sas_task *t; 2397f5860992SSakthivel K struct pm8001_ccb_info *ccb; 2398f5860992SSakthivel K unsigned long flags; 2399f5860992SSakthivel K u32 status; 2400f5860992SSakthivel K u32 tag; 2401f5860992SSakthivel K struct smp_completion_resp *psmpPayload; 2402f5860992SSakthivel K struct task_status_struct *ts; 2403f5860992SSakthivel K struct pm8001_device *pm8001_dev; 2404f5860992SSakthivel K char *pdma_respaddr = NULL; 2405f5860992SSakthivel K 2406f5860992SSakthivel K psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2407f5860992SSakthivel K status = le32_to_cpu(psmpPayload->status); 2408f5860992SSakthivel K tag = le32_to_cpu(psmpPayload->tag); 2409f5860992SSakthivel K 2410f5860992SSakthivel K ccb = &pm8001_ha->ccb_info[tag]; 2411f5860992SSakthivel K param = le32_to_cpu(psmpPayload->param); 2412f5860992SSakthivel K t = ccb->task; 2413f5860992SSakthivel K ts = &t->task_status; 2414f5860992SSakthivel K pm8001_dev = ccb->device; 2415f5860992SSakthivel K if (status) 2416f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 2417f5860992SSakthivel K pm8001_printk("smp IO status 0x%x\n", status)); 2418f5860992SSakthivel K if (unlikely(!t || !t->lldd_task || !t->dev)) 2419f5860992SSakthivel K return; 2420f5860992SSakthivel K 2421f5860992SSakthivel K switch (status) { 2422f5860992SSakthivel K 2423f5860992SSakthivel K case IO_SUCCESS: 2424f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2425f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2426f5860992SSakthivel K ts->stat = SAM_STAT_GOOD; 2427f5860992SSakthivel K if (pm8001_dev) 2428f5860992SSakthivel K pm8001_dev->running_req--; 2429f5860992SSakthivel K if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 2430f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2431f5860992SSakthivel K pm8001_printk("DIRECT RESPONSE Length:%d\n", 2432f5860992SSakthivel K param)); 2433f5860992SSakthivel K pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64 2434f5860992SSakthivel K ((u64)sg_dma_address 2435f5860992SSakthivel K (&t->smp_task.smp_resp)))); 2436f5860992SSakthivel K for (i = 0; i < param; i++) { 2437f5860992SSakthivel K *(pdma_respaddr+i) = psmpPayload->_r_a[i]; 2438f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2439f5860992SSakthivel K "SMP Byte%d DMA data 0x%x psmp 0x%x\n", 2440f5860992SSakthivel K i, *(pdma_respaddr+i), 2441f5860992SSakthivel K psmpPayload->_r_a[i])); 2442f5860992SSakthivel K } 2443f5860992SSakthivel K } 2444f5860992SSakthivel K break; 2445f5860992SSakthivel K case IO_ABORTED: 2446f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2447f5860992SSakthivel K pm8001_printk("IO_ABORTED IOMB\n")); 2448f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2449f5860992SSakthivel K ts->stat = SAS_ABORTED_TASK; 2450f5860992SSakthivel K if (pm8001_dev) 2451f5860992SSakthivel K pm8001_dev->running_req--; 2452f5860992SSakthivel K break; 2453f5860992SSakthivel K case IO_OVERFLOW: 2454f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2455f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2456f5860992SSakthivel K ts->stat = SAS_DATA_OVERRUN; 2457f5860992SSakthivel K ts->residual = 0; 2458f5860992SSakthivel K if (pm8001_dev) 2459f5860992SSakthivel K pm8001_dev->running_req--; 2460f5860992SSakthivel K break; 2461f5860992SSakthivel K case IO_NO_DEVICE: 2462f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); 2463f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2464f5860992SSakthivel K ts->stat = SAS_PHY_DOWN; 2465f5860992SSakthivel K break; 2466f5860992SSakthivel K case IO_ERROR_HW_TIMEOUT: 2467f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2468f5860992SSakthivel K pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); 2469f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2470f5860992SSakthivel K ts->stat = SAM_STAT_BUSY; 2471f5860992SSakthivel K break; 2472f5860992SSakthivel K case IO_XFER_ERROR_BREAK: 2473f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2474f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2475f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2476f5860992SSakthivel K ts->stat = SAM_STAT_BUSY; 2477f5860992SSakthivel K break; 2478f5860992SSakthivel K case IO_XFER_ERROR_PHY_NOT_READY: 2479f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2480f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2481f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2482f5860992SSakthivel K ts->stat = SAM_STAT_BUSY; 2483f5860992SSakthivel K break; 2484f5860992SSakthivel K case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2485f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2486f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2487f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2488f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2489f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2490f5860992SSakthivel K break; 2491f5860992SSakthivel K case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2492f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2493f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2494f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2495f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2496f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2497f5860992SSakthivel K break; 2498f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BREAK: 2499f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2500f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2501f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2502f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2503f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2504f5860992SSakthivel K break; 2505f5860992SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2506a6cb3d01SSakthivel K case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 2507a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 2508a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 2509a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 2510a6cb3d01SSakthivel K case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 2511f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2512f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2513f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2514f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2515f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2516f5860992SSakthivel K pm8001_handle_event(pm8001_ha, 2517f5860992SSakthivel K pm8001_dev, 2518f5860992SSakthivel K IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2519f5860992SSakthivel K break; 2520f5860992SSakthivel K case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2521f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2522f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2523f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2524f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2525f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2526f5860992SSakthivel K break; 2527f5860992SSakthivel K case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2528f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk(\ 2529f5860992SSakthivel K "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); 2530f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2531f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2532f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2533f5860992SSakthivel K break; 2534f5860992SSakthivel K case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2535f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2536f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2537f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2538f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2539f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2540f5860992SSakthivel K break; 2541f5860992SSakthivel K case IO_XFER_ERROR_RX_FRAME: 2542f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2543f5860992SSakthivel K pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); 2544f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2545f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2546f5860992SSakthivel K break; 2547f5860992SSakthivel K case IO_XFER_OPEN_RETRY_TIMEOUT: 2548f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2549f5860992SSakthivel K pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2550f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2551f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2552f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2553f5860992SSakthivel K break; 2554f5860992SSakthivel K case IO_ERROR_INTERNAL_SMP_RESOURCE: 2555f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2556f5860992SSakthivel K pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); 2557f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2558f5860992SSakthivel K ts->stat = SAS_QUEUE_FULL; 2559f5860992SSakthivel K break; 2560f5860992SSakthivel K case IO_PORT_IN_RESET: 2561f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2562f5860992SSakthivel K pm8001_printk("IO_PORT_IN_RESET\n")); 2563f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2564f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2565f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2566f5860992SSakthivel K break; 2567f5860992SSakthivel K case IO_DS_NON_OPERATIONAL: 2568f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2569f5860992SSakthivel K pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2570f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2571f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2572f5860992SSakthivel K break; 2573f5860992SSakthivel K case IO_DS_IN_RECOVERY: 2574f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2575f5860992SSakthivel K pm8001_printk("IO_DS_IN_RECOVERY\n")); 2576f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2577f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2578f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2579f5860992SSakthivel K break; 2580f5860992SSakthivel K case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2581f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2582f5860992SSakthivel K pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2583f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2584f5860992SSakthivel K ts->stat = SAS_OPEN_REJECT; 2585f5860992SSakthivel K ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2586f5860992SSakthivel K break; 2587f5860992SSakthivel K default: 2588f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 2589f5860992SSakthivel K pm8001_printk("Unknown status 0x%x\n", status)); 2590f5860992SSakthivel K ts->resp = SAS_TASK_COMPLETE; 2591f5860992SSakthivel K ts->stat = SAS_DEV_NO_RESPONSE; 2592f5860992SSakthivel K /* not allowed case. Therefore, return failed status */ 2593f5860992SSakthivel K break; 2594f5860992SSakthivel K } 2595f5860992SSakthivel K spin_lock_irqsave(&t->task_state_lock, flags); 2596f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2597f5860992SSakthivel K t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2598f5860992SSakthivel K t->task_state_flags |= SAS_TASK_STATE_DONE; 2599f5860992SSakthivel K if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2600f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 2601f5860992SSakthivel K PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 2602f5860992SSakthivel K "task 0x%p done with io_status 0x%x resp 0x%x" 2603f5860992SSakthivel K "stat 0x%x but aborted by upper layer!\n", 2604f5860992SSakthivel K t, status, ts->resp, ts->stat)); 2605f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2606f5860992SSakthivel K } else { 2607f5860992SSakthivel K spin_unlock_irqrestore(&t->task_state_lock, flags); 2608f5860992SSakthivel K pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2609f5860992SSakthivel K mb();/* in order to force CPU ordering */ 2610f5860992SSakthivel K t->task_done(t); 2611f5860992SSakthivel K } 2612f5860992SSakthivel K } 2613f5860992SSakthivel K 2614f5860992SSakthivel K /** 2615f5860992SSakthivel K * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 2616f5860992SSakthivel K * @pm8001_ha: our hba card information 2617f5860992SSakthivel K * @Qnum: the outbound queue message number. 2618f5860992SSakthivel K * @SEA: source of event to ack 2619f5860992SSakthivel K * @port_id: port id. 2620f5860992SSakthivel K * @phyId: phy id. 2621f5860992SSakthivel K * @param0: parameter 0. 2622f5860992SSakthivel K * @param1: parameter 1. 2623f5860992SSakthivel K */ 2624f5860992SSakthivel K static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 2625f5860992SSakthivel K u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 2626f5860992SSakthivel K { 2627f5860992SSakthivel K struct hw_event_ack_req payload; 2628f5860992SSakthivel K u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 2629f5860992SSakthivel K 2630f5860992SSakthivel K struct inbound_queue_table *circularQ; 2631f5860992SSakthivel K 2632f5860992SSakthivel K memset((u8 *)&payload, 0, sizeof(payload)); 2633f5860992SSakthivel K circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 2634f5860992SSakthivel K payload.tag = cpu_to_le32(1); 2635f5860992SSakthivel K payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 2636f5860992SSakthivel K ((phyId & 0xFF) << 24) | (port_id & 0xFF)); 2637f5860992SSakthivel K payload.param0 = cpu_to_le32(param0); 2638f5860992SSakthivel K payload.param1 = cpu_to_le32(param1); 2639f5860992SSakthivel K pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 2640f5860992SSakthivel K } 2641f5860992SSakthivel K 2642f5860992SSakthivel K static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 2643f5860992SSakthivel K u32 phyId, u32 phy_op); 2644f5860992SSakthivel K 2645f5860992SSakthivel K /** 2646f5860992SSakthivel K * hw_event_sas_phy_up -FW tells me a SAS phy up event. 2647f5860992SSakthivel K * @pm8001_ha: our hba card information 2648f5860992SSakthivel K * @piomb: IO message buffer 2649f5860992SSakthivel K */ 2650f5860992SSakthivel K static void 2651f5860992SSakthivel K hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 2652f5860992SSakthivel K { 2653f5860992SSakthivel K struct hw_event_resp *pPayload = 2654f5860992SSakthivel K (struct hw_event_resp *)(piomb + 4); 2655f5860992SSakthivel K u32 lr_status_evt_portid = 2656f5860992SSakthivel K le32_to_cpu(pPayload->lr_status_evt_portid); 2657f5860992SSakthivel K u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 2658f5860992SSakthivel K 2659f5860992SSakthivel K u8 link_rate = 2660f5860992SSakthivel K (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 2661f5860992SSakthivel K u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 2662f5860992SSakthivel K u8 phy_id = 2663f5860992SSakthivel K (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 2664f5860992SSakthivel K u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 2665f5860992SSakthivel K 2666f5860992SSakthivel K struct pm8001_port *port = &pm8001_ha->port[port_id]; 2667f5860992SSakthivel K struct sas_ha_struct *sas_ha = pm8001_ha->sas; 2668f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2669f5860992SSakthivel K unsigned long flags; 2670f5860992SSakthivel K u8 deviceType = pPayload->sas_identify.dev_type; 2671f5860992SSakthivel K port->port_state = portstate; 2672f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 2673f5860992SSakthivel K "portid:%d; phyid:%d; linkrate:%d; " 2674f5860992SSakthivel K "portstate:%x; devicetype:%x\n", 2675f5860992SSakthivel K port_id, phy_id, link_rate, portstate, deviceType)); 2676f5860992SSakthivel K 2677f5860992SSakthivel K switch (deviceType) { 2678f5860992SSakthivel K case SAS_PHY_UNUSED: 2679f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2680f5860992SSakthivel K pm8001_printk("device type no device.\n")); 2681f5860992SSakthivel K break; 2682f5860992SSakthivel K case SAS_END_DEVICE: 2683f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); 2684f5860992SSakthivel K pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, 2685f5860992SSakthivel K PHY_NOTIFY_ENABLE_SPINUP); 2686f5860992SSakthivel K port->port_attached = 1; 2687f5860992SSakthivel K pm8001_get_lrate_mode(phy, link_rate); 2688f5860992SSakthivel K break; 2689f5860992SSakthivel K case SAS_EDGE_EXPANDER_DEVICE: 2690f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2691f5860992SSakthivel K pm8001_printk("expander device.\n")); 2692f5860992SSakthivel K port->port_attached = 1; 2693f5860992SSakthivel K pm8001_get_lrate_mode(phy, link_rate); 2694f5860992SSakthivel K break; 2695f5860992SSakthivel K case SAS_FANOUT_EXPANDER_DEVICE: 2696f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2697f5860992SSakthivel K pm8001_printk("fanout expander device.\n")); 2698f5860992SSakthivel K port->port_attached = 1; 2699f5860992SSakthivel K pm8001_get_lrate_mode(phy, link_rate); 2700f5860992SSakthivel K break; 2701f5860992SSakthivel K default: 2702f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2703f5860992SSakthivel K pm8001_printk("unknown device type(%x)\n", deviceType)); 2704f5860992SSakthivel K break; 2705f5860992SSakthivel K } 2706f5860992SSakthivel K phy->phy_type |= PORT_TYPE_SAS; 2707f5860992SSakthivel K phy->identify.device_type = deviceType; 2708f5860992SSakthivel K phy->phy_attached = 1; 2709f5860992SSakthivel K if (phy->identify.device_type == SAS_END_DEVICE) 2710f5860992SSakthivel K phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 2711f5860992SSakthivel K else if (phy->identify.device_type != SAS_PHY_UNUSED) 2712f5860992SSakthivel K phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 2713f5860992SSakthivel K phy->sas_phy.oob_mode = SAS_OOB_MODE; 2714f5860992SSakthivel K sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 2715f5860992SSakthivel K spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 2716f5860992SSakthivel K memcpy(phy->frame_rcvd, &pPayload->sas_identify, 2717f5860992SSakthivel K sizeof(struct sas_identify_frame)-4); 2718f5860992SSakthivel K phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 2719f5860992SSakthivel K pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 2720f5860992SSakthivel K spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 2721f5860992SSakthivel K if (pm8001_ha->flags == PM8001F_RUN_TIME) 2722f5860992SSakthivel K mdelay(200);/*delay a moment to wait disk to spinup*/ 2723f5860992SSakthivel K pm8001_bytes_dmaed(pm8001_ha, phy_id); 2724f5860992SSakthivel K } 2725f5860992SSakthivel K 2726f5860992SSakthivel K /** 2727f5860992SSakthivel K * hw_event_sata_phy_up -FW tells me a SATA phy up event. 2728f5860992SSakthivel K * @pm8001_ha: our hba card information 2729f5860992SSakthivel K * @piomb: IO message buffer 2730f5860992SSakthivel K */ 2731f5860992SSakthivel K static void 2732f5860992SSakthivel K hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 2733f5860992SSakthivel K { 2734f5860992SSakthivel K struct hw_event_resp *pPayload = 2735f5860992SSakthivel K (struct hw_event_resp *)(piomb + 4); 2736f5860992SSakthivel K u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 2737f5860992SSakthivel K u32 lr_status_evt_portid = 2738f5860992SSakthivel K le32_to_cpu(pPayload->lr_status_evt_portid); 2739f5860992SSakthivel K u8 link_rate = 2740f5860992SSakthivel K (u8)((lr_status_evt_portid & 0xF0000000) >> 28); 2741f5860992SSakthivel K u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 2742f5860992SSakthivel K u8 phy_id = 2743f5860992SSakthivel K (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 2744f5860992SSakthivel K 2745f5860992SSakthivel K u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 2746f5860992SSakthivel K 2747f5860992SSakthivel K struct pm8001_port *port = &pm8001_ha->port[port_id]; 2748f5860992SSakthivel K struct sas_ha_struct *sas_ha = pm8001_ha->sas; 2749f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2750f5860992SSakthivel K unsigned long flags; 2751f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 2752f5860992SSakthivel K "port id %d, phy id %d link_rate %d portstate 0x%x\n", 2753f5860992SSakthivel K port_id, phy_id, link_rate, portstate)); 2754f5860992SSakthivel K 2755f5860992SSakthivel K port->port_state = portstate; 2756f5860992SSakthivel K port->port_attached = 1; 2757f5860992SSakthivel K pm8001_get_lrate_mode(phy, link_rate); 2758f5860992SSakthivel K phy->phy_type |= PORT_TYPE_SATA; 2759f5860992SSakthivel K phy->phy_attached = 1; 2760f5860992SSakthivel K phy->sas_phy.oob_mode = SATA_OOB_MODE; 2761f5860992SSakthivel K sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 2762f5860992SSakthivel K spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 2763f5860992SSakthivel K memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 2764f5860992SSakthivel K sizeof(struct dev_to_host_fis)); 2765f5860992SSakthivel K phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 2766f5860992SSakthivel K phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 2767aa9f8328SJames Bottomley phy->identify.device_type = SAS_SATA_DEV; 2768f5860992SSakthivel K pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 2769f5860992SSakthivel K spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 2770f5860992SSakthivel K pm8001_bytes_dmaed(pm8001_ha, phy_id); 2771f5860992SSakthivel K } 2772f5860992SSakthivel K 2773f5860992SSakthivel K /** 2774f5860992SSakthivel K * hw_event_phy_down -we should notify the libsas the phy is down. 2775f5860992SSakthivel K * @pm8001_ha: our hba card information 2776f5860992SSakthivel K * @piomb: IO message buffer 2777f5860992SSakthivel K */ 2778f5860992SSakthivel K static void 2779f5860992SSakthivel K hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 2780f5860992SSakthivel K { 2781f5860992SSakthivel K struct hw_event_resp *pPayload = 2782f5860992SSakthivel K (struct hw_event_resp *)(piomb + 4); 2783f5860992SSakthivel K 2784f5860992SSakthivel K u32 lr_status_evt_portid = 2785f5860992SSakthivel K le32_to_cpu(pPayload->lr_status_evt_portid); 2786f5860992SSakthivel K u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 2787f5860992SSakthivel K u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 2788f5860992SSakthivel K u8 phy_id = 2789f5860992SSakthivel K (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 2790f5860992SSakthivel K u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); 2791f5860992SSakthivel K 2792f5860992SSakthivel K struct pm8001_port *port = &pm8001_ha->port[port_id]; 2793f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2794f5860992SSakthivel K port->port_state = portstate; 2795f5860992SSakthivel K phy->phy_type = 0; 2796f5860992SSakthivel K phy->identify.device_type = 0; 2797f5860992SSakthivel K phy->phy_attached = 0; 2798f5860992SSakthivel K memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); 2799f5860992SSakthivel K switch (portstate) { 2800f5860992SSakthivel K case PORT_VALID: 2801f5860992SSakthivel K break; 2802f5860992SSakthivel K case PORT_INVALID: 2803f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2804f5860992SSakthivel K pm8001_printk(" PortInvalid portID %d\n", port_id)); 2805f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2806f5860992SSakthivel K pm8001_printk(" Last phy Down and port invalid\n")); 2807f5860992SSakthivel K port->port_attached = 0; 2808f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 2809f5860992SSakthivel K port_id, phy_id, 0, 0); 2810f5860992SSakthivel K break; 2811f5860992SSakthivel K case PORT_IN_RESET: 2812f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2813f5860992SSakthivel K pm8001_printk(" Port In Reset portID %d\n", port_id)); 2814f5860992SSakthivel K break; 2815f5860992SSakthivel K case PORT_NOT_ESTABLISHED: 2816f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2817f5860992SSakthivel K pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n")); 2818f5860992SSakthivel K port->port_attached = 0; 2819f5860992SSakthivel K break; 2820f5860992SSakthivel K case PORT_LOSTCOMM: 2821f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2822f5860992SSakthivel K pm8001_printk(" phy Down and PORT_LOSTCOMM\n")); 2823f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2824f5860992SSakthivel K pm8001_printk(" Last phy Down and port invalid\n")); 2825f5860992SSakthivel K port->port_attached = 0; 2826f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 2827f5860992SSakthivel K port_id, phy_id, 0, 0); 2828f5860992SSakthivel K break; 2829f5860992SSakthivel K default: 2830f5860992SSakthivel K port->port_attached = 0; 2831f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2832f5860992SSakthivel K pm8001_printk(" phy Down and(default) = 0x%x\n", 2833f5860992SSakthivel K portstate)); 2834f5860992SSakthivel K break; 2835f5860992SSakthivel K 2836f5860992SSakthivel K } 2837f5860992SSakthivel K } 2838f5860992SSakthivel K 2839f5860992SSakthivel K static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 2840f5860992SSakthivel K { 2841f5860992SSakthivel K struct phy_start_resp *pPayload = 2842f5860992SSakthivel K (struct phy_start_resp *)(piomb + 4); 2843f5860992SSakthivel K u32 status = 2844f5860992SSakthivel K le32_to_cpu(pPayload->status); 2845f5860992SSakthivel K u32 phy_id = 2846f5860992SSakthivel K le32_to_cpu(pPayload->phyid); 2847f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2848f5860992SSakthivel K 2849f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 2850f5860992SSakthivel K pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n", 2851f5860992SSakthivel K status, phy_id)); 2852f5860992SSakthivel K if (status == 0) { 2853f5860992SSakthivel K phy->phy_state = 1; 2854f5860992SSakthivel K if (pm8001_ha->flags == PM8001F_RUN_TIME) 2855f5860992SSakthivel K complete(phy->enable_completion); 2856f5860992SSakthivel K } 2857f5860992SSakthivel K return 0; 2858f5860992SSakthivel K 2859f5860992SSakthivel K } 2860f5860992SSakthivel K 2861f5860992SSakthivel K /** 2862f5860992SSakthivel K * mpi_thermal_hw_event -The hw event has come. 2863f5860992SSakthivel K * @pm8001_ha: our hba card information 2864f5860992SSakthivel K * @piomb: IO message buffer 2865f5860992SSakthivel K */ 2866f5860992SSakthivel K static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 2867f5860992SSakthivel K { 2868f5860992SSakthivel K struct thermal_hw_event *pPayload = 2869f5860992SSakthivel K (struct thermal_hw_event *)(piomb + 4); 2870f5860992SSakthivel K 2871f5860992SSakthivel K u32 thermal_event = le32_to_cpu(pPayload->thermal_event); 2872f5860992SSakthivel K u32 rht_lht = le32_to_cpu(pPayload->rht_lht); 2873f5860992SSakthivel K 2874f5860992SSakthivel K if (thermal_event & 0x40) { 2875f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2876f5860992SSakthivel K "Thermal Event: Local high temperature violated!\n")); 2877f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2878f5860992SSakthivel K "Thermal Event: Measured local high temperature %d\n", 2879f5860992SSakthivel K ((rht_lht & 0xFF00) >> 8))); 2880f5860992SSakthivel K } 2881f5860992SSakthivel K if (thermal_event & 0x10) { 2882f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2883f5860992SSakthivel K "Thermal Event: Remote high temperature violated!\n")); 2884f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 2885f5860992SSakthivel K "Thermal Event: Measured remote high temperature %d\n", 2886f5860992SSakthivel K ((rht_lht & 0xFF000000) >> 24))); 2887f5860992SSakthivel K } 2888f5860992SSakthivel K return 0; 2889f5860992SSakthivel K } 2890f5860992SSakthivel K 2891f5860992SSakthivel K /** 2892f5860992SSakthivel K * mpi_hw_event -The hw event has come. 2893f5860992SSakthivel K * @pm8001_ha: our hba card information 2894f5860992SSakthivel K * @piomb: IO message buffer 2895f5860992SSakthivel K */ 2896f5860992SSakthivel K static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) 2897f5860992SSakthivel K { 2898f5860992SSakthivel K unsigned long flags; 2899f5860992SSakthivel K struct hw_event_resp *pPayload = 2900f5860992SSakthivel K (struct hw_event_resp *)(piomb + 4); 2901f5860992SSakthivel K u32 lr_status_evt_portid = 2902f5860992SSakthivel K le32_to_cpu(pPayload->lr_status_evt_portid); 2903f5860992SSakthivel K u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); 2904f5860992SSakthivel K u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); 2905f5860992SSakthivel K u8 phy_id = 2906f5860992SSakthivel K (u8)((phyid_npip_portstate & 0xFF0000) >> 16); 2907f5860992SSakthivel K u16 eventType = 2908f5860992SSakthivel K (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); 2909f5860992SSakthivel K u8 status = 2910f5860992SSakthivel K (u8)((lr_status_evt_portid & 0x0F000000) >> 24); 2911f5860992SSakthivel K 2912f5860992SSakthivel K struct sas_ha_struct *sas_ha = pm8001_ha->sas; 2913f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 2914f5860992SSakthivel K struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 2915f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2916f5860992SSakthivel K pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n", 2917f5860992SSakthivel K port_id, phy_id, eventType, status)); 2918f5860992SSakthivel K 2919f5860992SSakthivel K switch (eventType) { 2920f5860992SSakthivel K 2921f5860992SSakthivel K case HW_EVENT_SAS_PHY_UP: 2922f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2923f5860992SSakthivel K pm8001_printk("HW_EVENT_PHY_START_STATUS\n")); 2924f5860992SSakthivel K hw_event_sas_phy_up(pm8001_ha, piomb); 2925f5860992SSakthivel K break; 2926f5860992SSakthivel K case HW_EVENT_SATA_PHY_UP: 2927f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2928f5860992SSakthivel K pm8001_printk("HW_EVENT_SATA_PHY_UP\n")); 2929f5860992SSakthivel K hw_event_sata_phy_up(pm8001_ha, piomb); 2930f5860992SSakthivel K break; 2931f5860992SSakthivel K case HW_EVENT_SATA_SPINUP_HOLD: 2932f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2933f5860992SSakthivel K pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n")); 2934f5860992SSakthivel K sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 2935f5860992SSakthivel K break; 2936f5860992SSakthivel K case HW_EVENT_PHY_DOWN: 2937f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2938f5860992SSakthivel K pm8001_printk("HW_EVENT_PHY_DOWN\n")); 2939f5860992SSakthivel K sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); 2940f5860992SSakthivel K phy->phy_attached = 0; 2941f5860992SSakthivel K phy->phy_state = 0; 2942f5860992SSakthivel K hw_event_phy_down(pm8001_ha, piomb); 2943f5860992SSakthivel K break; 2944f5860992SSakthivel K case HW_EVENT_PORT_INVALID: 2945f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2946f5860992SSakthivel K pm8001_printk("HW_EVENT_PORT_INVALID\n")); 2947f5860992SSakthivel K sas_phy_disconnected(sas_phy); 2948f5860992SSakthivel K phy->phy_attached = 0; 2949f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 2950f5860992SSakthivel K break; 2951f5860992SSakthivel K /* the broadcast change primitive received, tell the LIBSAS this event 2952f5860992SSakthivel K to revalidate the sas domain*/ 2953f5860992SSakthivel K case HW_EVENT_BROADCAST_CHANGE: 2954f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2955f5860992SSakthivel K pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); 2956f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 2957f5860992SSakthivel K port_id, phy_id, 1, 0); 2958f5860992SSakthivel K spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 2959f5860992SSakthivel K sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 2960f5860992SSakthivel K spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 2961f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 2962f5860992SSakthivel K break; 2963f5860992SSakthivel K case HW_EVENT_PHY_ERROR: 2964f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2965f5860992SSakthivel K pm8001_printk("HW_EVENT_PHY_ERROR\n")); 2966f5860992SSakthivel K sas_phy_disconnected(&phy->sas_phy); 2967f5860992SSakthivel K phy->phy_attached = 0; 2968f5860992SSakthivel K sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 2969f5860992SSakthivel K break; 2970f5860992SSakthivel K case HW_EVENT_BROADCAST_EXP: 2971f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2972f5860992SSakthivel K pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); 2973f5860992SSakthivel K spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 2974f5860992SSakthivel K sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 2975f5860992SSakthivel K spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 2976f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 2977f5860992SSakthivel K break; 2978f5860992SSakthivel K case HW_EVENT_LINK_ERR_INVALID_DWORD: 2979f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2980f5860992SSakthivel K pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); 2981f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 2982f5860992SSakthivel K HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 2983f5860992SSakthivel K sas_phy_disconnected(sas_phy); 2984f5860992SSakthivel K phy->phy_attached = 0; 2985f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 2986f5860992SSakthivel K break; 2987f5860992SSakthivel K case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 2988f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2989f5860992SSakthivel K pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); 2990f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 2991f5860992SSakthivel K HW_EVENT_LINK_ERR_DISPARITY_ERROR, 2992f5860992SSakthivel K port_id, phy_id, 0, 0); 2993f5860992SSakthivel K sas_phy_disconnected(sas_phy); 2994f5860992SSakthivel K phy->phy_attached = 0; 2995f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 2996f5860992SSakthivel K break; 2997f5860992SSakthivel K case HW_EVENT_LINK_ERR_CODE_VIOLATION: 2998f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 2999f5860992SSakthivel K pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); 3000f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3001f5860992SSakthivel K HW_EVENT_LINK_ERR_CODE_VIOLATION, 3002f5860992SSakthivel K port_id, phy_id, 0, 0); 3003f5860992SSakthivel K sas_phy_disconnected(sas_phy); 3004f5860992SSakthivel K phy->phy_attached = 0; 3005f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3006f5860992SSakthivel K break; 3007f5860992SSakthivel K case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3008f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3009f5860992SSakthivel K "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); 3010f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3011f5860992SSakthivel K HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3012f5860992SSakthivel K port_id, phy_id, 0, 0); 3013f5860992SSakthivel K sas_phy_disconnected(sas_phy); 3014f5860992SSakthivel K phy->phy_attached = 0; 3015f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3016f5860992SSakthivel K break; 3017f5860992SSakthivel K case HW_EVENT_MALFUNCTION: 3018f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3019f5860992SSakthivel K pm8001_printk("HW_EVENT_MALFUNCTION\n")); 3020f5860992SSakthivel K break; 3021f5860992SSakthivel K case HW_EVENT_BROADCAST_SES: 3022f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3023f5860992SSakthivel K pm8001_printk("HW_EVENT_BROADCAST_SES\n")); 3024f5860992SSakthivel K spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3025f5860992SSakthivel K sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3026f5860992SSakthivel K spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3027f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3028f5860992SSakthivel K break; 3029f5860992SSakthivel K case HW_EVENT_INBOUND_CRC_ERROR: 3030f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3031f5860992SSakthivel K pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); 3032f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3033f5860992SSakthivel K HW_EVENT_INBOUND_CRC_ERROR, 3034f5860992SSakthivel K port_id, phy_id, 0, 0); 3035f5860992SSakthivel K break; 3036f5860992SSakthivel K case HW_EVENT_HARD_RESET_RECEIVED: 3037f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3038f5860992SSakthivel K pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); 3039f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3040f5860992SSakthivel K break; 3041f5860992SSakthivel K case HW_EVENT_ID_FRAME_TIMEOUT: 3042f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3043f5860992SSakthivel K pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); 3044f5860992SSakthivel K sas_phy_disconnected(sas_phy); 3045f5860992SSakthivel K phy->phy_attached = 0; 3046f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3047f5860992SSakthivel K break; 3048f5860992SSakthivel K case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3049f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3050f5860992SSakthivel K pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n")); 3051f5860992SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3052f5860992SSakthivel K HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3053f5860992SSakthivel K port_id, phy_id, 0, 0); 3054f5860992SSakthivel K sas_phy_disconnected(sas_phy); 3055f5860992SSakthivel K phy->phy_attached = 0; 3056f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3057f5860992SSakthivel K break; 3058f5860992SSakthivel K case HW_EVENT_PORT_RESET_TIMER_TMO: 3059f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3060f5860992SSakthivel K pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n")); 3061f5860992SSakthivel K sas_phy_disconnected(sas_phy); 3062f5860992SSakthivel K phy->phy_attached = 0; 3063f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3064f5860992SSakthivel K break; 3065f5860992SSakthivel K case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3066f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3067f5860992SSakthivel K pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n")); 3068a6cb3d01SSakthivel K pm80xx_hw_event_ack_req(pm8001_ha, 0, 3069a6cb3d01SSakthivel K HW_EVENT_PORT_RECOVERY_TIMER_TMO, 3070a6cb3d01SSakthivel K port_id, phy_id, 0, 0); 3071f5860992SSakthivel K sas_phy_disconnected(sas_phy); 3072f5860992SSakthivel K phy->phy_attached = 0; 3073f5860992SSakthivel K sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3074f5860992SSakthivel K break; 3075f5860992SSakthivel K case HW_EVENT_PORT_RECOVER: 3076f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3077f5860992SSakthivel K pm8001_printk("HW_EVENT_PORT_RECOVER\n")); 3078f5860992SSakthivel K break; 3079f5860992SSakthivel K case HW_EVENT_PORT_RESET_COMPLETE: 3080f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3081f5860992SSakthivel K pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n")); 3082f5860992SSakthivel K break; 3083f5860992SSakthivel K case EVENT_BROADCAST_ASYNCH_EVENT: 3084f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3085f5860992SSakthivel K pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); 3086f5860992SSakthivel K break; 3087f5860992SSakthivel K default: 3088f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3089f5860992SSakthivel K pm8001_printk("Unknown event type 0x%x\n", eventType)); 3090f5860992SSakthivel K break; 3091f5860992SSakthivel K } 3092f5860992SSakthivel K return 0; 3093f5860992SSakthivel K } 3094f5860992SSakthivel K 3095f5860992SSakthivel K /** 3096f5860992SSakthivel K * mpi_phy_stop_resp - SPCv specific 3097f5860992SSakthivel K * @pm8001_ha: our hba card information 3098f5860992SSakthivel K * @piomb: IO message buffer 3099f5860992SSakthivel K */ 3100f5860992SSakthivel K static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3101f5860992SSakthivel K { 3102f5860992SSakthivel K struct phy_stop_resp *pPayload = 3103f5860992SSakthivel K (struct phy_stop_resp *)(piomb + 4); 3104f5860992SSakthivel K u32 status = 3105f5860992SSakthivel K le32_to_cpu(pPayload->status); 3106f5860992SSakthivel K u32 phyid = 3107f5860992SSakthivel K le32_to_cpu(pPayload->phyid); 3108f5860992SSakthivel K struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; 3109f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3110f5860992SSakthivel K pm8001_printk("phy:0x%x status:0x%x\n", 3111f5860992SSakthivel K phyid, status)); 3112f5860992SSakthivel K if (status == 0) 3113f5860992SSakthivel K phy->phy_state = 0; 3114f5860992SSakthivel K return 0; 3115f5860992SSakthivel K } 3116f5860992SSakthivel K 3117f5860992SSakthivel K /** 3118f5860992SSakthivel K * mpi_set_controller_config_resp - SPCv specific 3119f5860992SSakthivel K * @pm8001_ha: our hba card information 3120f5860992SSakthivel K * @piomb: IO message buffer 3121f5860992SSakthivel K */ 3122f5860992SSakthivel K static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3123f5860992SSakthivel K void *piomb) 3124f5860992SSakthivel K { 3125f5860992SSakthivel K struct set_ctrl_cfg_resp *pPayload = 3126f5860992SSakthivel K (struct set_ctrl_cfg_resp *)(piomb + 4); 3127f5860992SSakthivel K u32 status = le32_to_cpu(pPayload->status); 3128f5860992SSakthivel K u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); 3129f5860992SSakthivel K 3130f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3131f5860992SSakthivel K "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", 3132f5860992SSakthivel K status, err_qlfr_pgcd)); 3133f5860992SSakthivel K 3134f5860992SSakthivel K return 0; 3135f5860992SSakthivel K } 3136f5860992SSakthivel K 3137f5860992SSakthivel K /** 3138f5860992SSakthivel K * mpi_get_controller_config_resp - SPCv specific 3139f5860992SSakthivel K * @pm8001_ha: our hba card information 3140f5860992SSakthivel K * @piomb: IO message buffer 3141f5860992SSakthivel K */ 3142f5860992SSakthivel K static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, 3143f5860992SSakthivel K void *piomb) 3144f5860992SSakthivel K { 3145f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3146f5860992SSakthivel K pm8001_printk(" pm80xx_addition_functionality\n")); 3147f5860992SSakthivel K 3148f5860992SSakthivel K return 0; 3149f5860992SSakthivel K } 3150f5860992SSakthivel K 3151f5860992SSakthivel K /** 3152f5860992SSakthivel K * mpi_get_phy_profile_resp - SPCv specific 3153f5860992SSakthivel K * @pm8001_ha: our hba card information 3154f5860992SSakthivel K * @piomb: IO message buffer 3155f5860992SSakthivel K */ 3156f5860992SSakthivel K static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3157f5860992SSakthivel K void *piomb) 3158f5860992SSakthivel K { 3159f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3160f5860992SSakthivel K pm8001_printk(" pm80xx_addition_functionality\n")); 3161f5860992SSakthivel K 3162f5860992SSakthivel K return 0; 3163f5860992SSakthivel K } 3164f5860992SSakthivel K 3165f5860992SSakthivel K /** 3166f5860992SSakthivel K * mpi_flash_op_ext_resp - SPCv specific 3167f5860992SSakthivel K * @pm8001_ha: our hba card information 3168f5860992SSakthivel K * @piomb: IO message buffer 3169f5860992SSakthivel K */ 3170f5860992SSakthivel K static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3171f5860992SSakthivel K { 3172f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3173f5860992SSakthivel K pm8001_printk(" pm80xx_addition_functionality\n")); 3174f5860992SSakthivel K 3175f5860992SSakthivel K return 0; 3176f5860992SSakthivel K } 3177f5860992SSakthivel K 3178f5860992SSakthivel K /** 3179f5860992SSakthivel K * mpi_set_phy_profile_resp - SPCv specific 3180f5860992SSakthivel K * @pm8001_ha: our hba card information 3181f5860992SSakthivel K * @piomb: IO message buffer 3182f5860992SSakthivel K */ 3183f5860992SSakthivel K static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, 3184f5860992SSakthivel K void *piomb) 3185f5860992SSakthivel K { 3186f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3187f5860992SSakthivel K pm8001_printk(" pm80xx_addition_functionality\n")); 3188f5860992SSakthivel K 3189f5860992SSakthivel K return 0; 3190f5860992SSakthivel K } 3191f5860992SSakthivel K 3192f5860992SSakthivel K /** 3193f5860992SSakthivel K * mpi_kek_management_resp - SPCv specific 3194f5860992SSakthivel K * @pm8001_ha: our hba card information 3195f5860992SSakthivel K * @piomb: IO message buffer 3196f5860992SSakthivel K */ 3197f5860992SSakthivel K static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, 3198f5860992SSakthivel K void *piomb) 3199f5860992SSakthivel K { 3200f5860992SSakthivel K struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); 3201f5860992SSakthivel K 3202f5860992SSakthivel K u32 status = le32_to_cpu(pPayload->status); 3203f5860992SSakthivel K u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); 3204f5860992SSakthivel K u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); 3205f5860992SSakthivel K 3206f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3207f5860992SSakthivel K "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", 3208f5860992SSakthivel K status, kidx_new_curr_ksop, err_qlfr)); 3209f5860992SSakthivel K 3210f5860992SSakthivel K return 0; 3211f5860992SSakthivel K } 3212f5860992SSakthivel K 3213f5860992SSakthivel K /** 3214f5860992SSakthivel K * mpi_dek_management_resp - SPCv specific 3215f5860992SSakthivel K * @pm8001_ha: our hba card information 3216f5860992SSakthivel K * @piomb: IO message buffer 3217f5860992SSakthivel K */ 3218f5860992SSakthivel K static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, 3219f5860992SSakthivel K void *piomb) 3220f5860992SSakthivel K { 3221f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3222f5860992SSakthivel K pm8001_printk(" pm80xx_addition_functionality\n")); 3223f5860992SSakthivel K 3224f5860992SSakthivel K return 0; 3225f5860992SSakthivel K } 3226f5860992SSakthivel K 3227f5860992SSakthivel K /** 3228f5860992SSakthivel K * ssp_coalesced_comp_resp - SPCv specific 3229f5860992SSakthivel K * @pm8001_ha: our hba card information 3230f5860992SSakthivel K * @piomb: IO message buffer 3231f5860992SSakthivel K */ 3232f5860992SSakthivel K static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, 3233f5860992SSakthivel K void *piomb) 3234f5860992SSakthivel K { 3235f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3236f5860992SSakthivel K pm8001_printk(" pm80xx_addition_functionality\n")); 3237f5860992SSakthivel K 3238f5860992SSakthivel K return 0; 3239f5860992SSakthivel K } 3240f5860992SSakthivel K 3241f5860992SSakthivel K /** 3242f5860992SSakthivel K * process_one_iomb - process one outbound Queue memory block 3243f5860992SSakthivel K * @pm8001_ha: our hba card information 3244f5860992SSakthivel K * @piomb: IO message buffer 3245f5860992SSakthivel K */ 3246f5860992SSakthivel K static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3247f5860992SSakthivel K { 3248f5860992SSakthivel K __le32 pHeader = *(__le32 *)piomb; 3249f5860992SSakthivel K u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); 3250f5860992SSakthivel K 3251f5860992SSakthivel K switch (opc) { 3252f5860992SSakthivel K case OPC_OUB_ECHO: 3253f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n")); 3254f5860992SSakthivel K break; 3255f5860992SSakthivel K case OPC_OUB_HW_EVENT: 3256f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3257f5860992SSakthivel K pm8001_printk("OPC_OUB_HW_EVENT\n")); 3258f5860992SSakthivel K mpi_hw_event(pm8001_ha, piomb); 3259f5860992SSakthivel K break; 3260f5860992SSakthivel K case OPC_OUB_THERM_HW_EVENT: 3261f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3262f5860992SSakthivel K pm8001_printk("OPC_OUB_THERMAL_EVENT\n")); 3263f5860992SSakthivel K mpi_thermal_hw_event(pm8001_ha, piomb); 3264f5860992SSakthivel K break; 3265f5860992SSakthivel K case OPC_OUB_SSP_COMP: 3266f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3267f5860992SSakthivel K pm8001_printk("OPC_OUB_SSP_COMP\n")); 3268f5860992SSakthivel K mpi_ssp_completion(pm8001_ha, piomb); 3269f5860992SSakthivel K break; 3270f5860992SSakthivel K case OPC_OUB_SMP_COMP: 3271f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3272f5860992SSakthivel K pm8001_printk("OPC_OUB_SMP_COMP\n")); 3273f5860992SSakthivel K mpi_smp_completion(pm8001_ha, piomb); 3274f5860992SSakthivel K break; 3275f5860992SSakthivel K case OPC_OUB_LOCAL_PHY_CNTRL: 3276f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3277f5860992SSakthivel K pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); 3278f5860992SSakthivel K pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); 3279f5860992SSakthivel K break; 3280f5860992SSakthivel K case OPC_OUB_DEV_REGIST: 3281f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3282f5860992SSakthivel K pm8001_printk("OPC_OUB_DEV_REGIST\n")); 3283f5860992SSakthivel K pm8001_mpi_reg_resp(pm8001_ha, piomb); 3284f5860992SSakthivel K break; 3285f5860992SSakthivel K case OPC_OUB_DEREG_DEV: 3286f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 32878b513d0cSMasanari Iida pm8001_printk("unregister the device\n")); 3288f5860992SSakthivel K pm8001_mpi_dereg_resp(pm8001_ha, piomb); 3289f5860992SSakthivel K break; 3290f5860992SSakthivel K case OPC_OUB_GET_DEV_HANDLE: 3291f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3292f5860992SSakthivel K pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n")); 3293f5860992SSakthivel K break; 3294f5860992SSakthivel K case OPC_OUB_SATA_COMP: 3295f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3296f5860992SSakthivel K pm8001_printk("OPC_OUB_SATA_COMP\n")); 3297f5860992SSakthivel K mpi_sata_completion(pm8001_ha, piomb); 3298f5860992SSakthivel K break; 3299f5860992SSakthivel K case OPC_OUB_SATA_EVENT: 3300f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3301f5860992SSakthivel K pm8001_printk("OPC_OUB_SATA_EVENT\n")); 3302f5860992SSakthivel K mpi_sata_event(pm8001_ha, piomb); 3303f5860992SSakthivel K break; 3304f5860992SSakthivel K case OPC_OUB_SSP_EVENT: 3305f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3306f5860992SSakthivel K pm8001_printk("OPC_OUB_SSP_EVENT\n")); 3307f5860992SSakthivel K mpi_ssp_event(pm8001_ha, piomb); 3308f5860992SSakthivel K break; 3309f5860992SSakthivel K case OPC_OUB_DEV_HANDLE_ARRIV: 3310f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3311f5860992SSakthivel K pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); 3312f5860992SSakthivel K /*This is for target*/ 3313f5860992SSakthivel K break; 3314f5860992SSakthivel K case OPC_OUB_SSP_RECV_EVENT: 3315f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3316f5860992SSakthivel K pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); 3317f5860992SSakthivel K /*This is for target*/ 3318f5860992SSakthivel K break; 3319f5860992SSakthivel K case OPC_OUB_FW_FLASH_UPDATE: 3320f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3321f5860992SSakthivel K pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); 3322f5860992SSakthivel K pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); 3323f5860992SSakthivel K break; 3324f5860992SSakthivel K case OPC_OUB_GPIO_RESPONSE: 3325f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3326f5860992SSakthivel K pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); 3327f5860992SSakthivel K break; 3328f5860992SSakthivel K case OPC_OUB_GPIO_EVENT: 3329f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3330f5860992SSakthivel K pm8001_printk("OPC_OUB_GPIO_EVENT\n")); 3331f5860992SSakthivel K break; 3332f5860992SSakthivel K case OPC_OUB_GENERAL_EVENT: 3333f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3334f5860992SSakthivel K pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); 3335f5860992SSakthivel K pm8001_mpi_general_event(pm8001_ha, piomb); 3336f5860992SSakthivel K break; 3337f5860992SSakthivel K case OPC_OUB_SSP_ABORT_RSP: 3338f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3339f5860992SSakthivel K pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); 3340f5860992SSakthivel K pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3341f5860992SSakthivel K break; 3342f5860992SSakthivel K case OPC_OUB_SATA_ABORT_RSP: 3343f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3344f5860992SSakthivel K pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); 3345f5860992SSakthivel K pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3346f5860992SSakthivel K break; 3347f5860992SSakthivel K case OPC_OUB_SAS_DIAG_MODE_START_END: 3348f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3349f5860992SSakthivel K pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); 3350f5860992SSakthivel K break; 3351f5860992SSakthivel K case OPC_OUB_SAS_DIAG_EXECUTE: 3352f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3353f5860992SSakthivel K pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); 3354f5860992SSakthivel K break; 3355f5860992SSakthivel K case OPC_OUB_GET_TIME_STAMP: 3356f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3357f5860992SSakthivel K pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); 3358f5860992SSakthivel K break; 3359f5860992SSakthivel K case OPC_OUB_SAS_HW_EVENT_ACK: 3360f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3361f5860992SSakthivel K pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); 3362f5860992SSakthivel K break; 3363f5860992SSakthivel K case OPC_OUB_PORT_CONTROL: 3364f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3365f5860992SSakthivel K pm8001_printk("OPC_OUB_PORT_CONTROL\n")); 3366f5860992SSakthivel K break; 3367f5860992SSakthivel K case OPC_OUB_SMP_ABORT_RSP: 3368f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3369f5860992SSakthivel K pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); 3370f5860992SSakthivel K pm8001_mpi_task_abort_resp(pm8001_ha, piomb); 3371f5860992SSakthivel K break; 3372f5860992SSakthivel K case OPC_OUB_GET_NVMD_DATA: 3373f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3374f5860992SSakthivel K pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); 3375f5860992SSakthivel K pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); 3376f5860992SSakthivel K break; 3377f5860992SSakthivel K case OPC_OUB_SET_NVMD_DATA: 3378f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3379f5860992SSakthivel K pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); 3380f5860992SSakthivel K pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); 3381f5860992SSakthivel K break; 3382f5860992SSakthivel K case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3383f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3384f5860992SSakthivel K pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); 3385f5860992SSakthivel K break; 3386f5860992SSakthivel K case OPC_OUB_SET_DEVICE_STATE: 3387f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3388f5860992SSakthivel K pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); 3389f5860992SSakthivel K pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); 3390f5860992SSakthivel K break; 3391f5860992SSakthivel K case OPC_OUB_GET_DEVICE_STATE: 3392f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3393f5860992SSakthivel K pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); 3394f5860992SSakthivel K break; 3395f5860992SSakthivel K case OPC_OUB_SET_DEV_INFO: 3396f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, 3397f5860992SSakthivel K pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); 3398f5860992SSakthivel K break; 3399f5860992SSakthivel K /* spcv specifc commands */ 3400f5860992SSakthivel K case OPC_OUB_PHY_START_RESP: 3401f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3402f5860992SSakthivel K "OPC_OUB_PHY_START_RESP opcode:%x\n", opc)); 3403f5860992SSakthivel K mpi_phy_start_resp(pm8001_ha, piomb); 3404f5860992SSakthivel K break; 3405f5860992SSakthivel K case OPC_OUB_PHY_STOP_RESP: 3406f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3407f5860992SSakthivel K "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc)); 3408f5860992SSakthivel K mpi_phy_stop_resp(pm8001_ha, piomb); 3409f5860992SSakthivel K break; 3410f5860992SSakthivel K case OPC_OUB_SET_CONTROLLER_CONFIG: 3411f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3412f5860992SSakthivel K "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc)); 3413f5860992SSakthivel K mpi_set_controller_config_resp(pm8001_ha, piomb); 3414f5860992SSakthivel K break; 3415f5860992SSakthivel K case OPC_OUB_GET_CONTROLLER_CONFIG: 3416f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3417f5860992SSakthivel K "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc)); 3418f5860992SSakthivel K mpi_get_controller_config_resp(pm8001_ha, piomb); 3419f5860992SSakthivel K break; 3420f5860992SSakthivel K case OPC_OUB_GET_PHY_PROFILE: 3421f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3422f5860992SSakthivel K "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc)); 3423f5860992SSakthivel K mpi_get_phy_profile_resp(pm8001_ha, piomb); 3424f5860992SSakthivel K break; 3425f5860992SSakthivel K case OPC_OUB_FLASH_OP_EXT: 3426f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3427f5860992SSakthivel K "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc)); 3428f5860992SSakthivel K mpi_flash_op_ext_resp(pm8001_ha, piomb); 3429f5860992SSakthivel K break; 3430f5860992SSakthivel K case OPC_OUB_SET_PHY_PROFILE: 3431f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3432f5860992SSakthivel K "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc)); 3433f5860992SSakthivel K mpi_set_phy_profile_resp(pm8001_ha, piomb); 3434f5860992SSakthivel K break; 3435f5860992SSakthivel K case OPC_OUB_KEK_MANAGEMENT_RESP: 3436f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3437f5860992SSakthivel K "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc)); 3438f5860992SSakthivel K mpi_kek_management_resp(pm8001_ha, piomb); 3439f5860992SSakthivel K break; 3440f5860992SSakthivel K case OPC_OUB_DEK_MANAGEMENT_RESP: 3441f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3442f5860992SSakthivel K "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc)); 3443f5860992SSakthivel K mpi_dek_management_resp(pm8001_ha, piomb); 3444f5860992SSakthivel K break; 3445f5860992SSakthivel K case OPC_OUB_SSP_COALESCED_COMP_RESP: 3446f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3447f5860992SSakthivel K "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc)); 3448f5860992SSakthivel K ssp_coalesced_comp_resp(pm8001_ha, piomb); 3449f5860992SSakthivel K break; 3450f5860992SSakthivel K default: 3451f5860992SSakthivel K PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 3452f5860992SSakthivel K "Unknown outbound Queue IOMB OPC = 0x%x\n", opc)); 3453f5860992SSakthivel K break; 3454f5860992SSakthivel K } 3455f5860992SSakthivel K } 3456f5860992SSakthivel K 3457f5860992SSakthivel K static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) 3458f5860992SSakthivel K { 3459f5860992SSakthivel K struct outbound_queue_table *circularQ; 3460f5860992SSakthivel K void *pMsg1 = NULL; 3461f5860992SSakthivel K u8 uninitialized_var(bc); 3462f5860992SSakthivel K u32 ret = MPI_IO_STATUS_FAIL; 3463f5860992SSakthivel K unsigned long flags; 3464f5860992SSakthivel K 3465f5860992SSakthivel K spin_lock_irqsave(&pm8001_ha->lock, flags); 3466f5860992SSakthivel K circularQ = &pm8001_ha->outbnd_q_tbl[vec]; 3467f5860992SSakthivel K do { 3468f5860992SSakthivel K ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 3469f5860992SSakthivel K if (MPI_IO_STATUS_SUCCESS == ret) { 3470f5860992SSakthivel K /* process the outbound message */ 3471f5860992SSakthivel K process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 3472f5860992SSakthivel K /* free the message from the outbound circular buffer */ 3473f5860992SSakthivel K pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, 3474f5860992SSakthivel K circularQ, bc); 3475f5860992SSakthivel K } 3476f5860992SSakthivel K if (MPI_IO_STATUS_BUSY == ret) { 3477f5860992SSakthivel K /* Update the producer index from SPC */ 3478f5860992SSakthivel K circularQ->producer_index = 3479f5860992SSakthivel K cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 3480f5860992SSakthivel K if (le32_to_cpu(circularQ->producer_index) == 3481f5860992SSakthivel K circularQ->consumer_idx) 3482f5860992SSakthivel K /* OQ is empty */ 3483f5860992SSakthivel K break; 3484f5860992SSakthivel K } 3485f5860992SSakthivel K } while (1); 3486f5860992SSakthivel K spin_unlock_irqrestore(&pm8001_ha->lock, flags); 3487f5860992SSakthivel K return ret; 3488f5860992SSakthivel K } 3489f5860992SSakthivel K 3490f5860992SSakthivel K /* PCI_DMA_... to our direction translation. */ 3491f5860992SSakthivel K static const u8 data_dir_flags[] = { 3492f5860992SSakthivel K [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */ 3493f5860992SSakthivel K [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */ 3494f5860992SSakthivel K [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */ 3495f5860992SSakthivel K [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */ 3496f5860992SSakthivel K }; 3497f5860992SSakthivel K 3498f5860992SSakthivel K static void build_smp_cmd(u32 deviceID, __le32 hTag, 3499f5860992SSakthivel K struct smp_req *psmp_cmd, int mode, int length) 3500f5860992SSakthivel K { 3501f5860992SSakthivel K psmp_cmd->tag = hTag; 3502f5860992SSakthivel K psmp_cmd->device_id = cpu_to_le32(deviceID); 3503f5860992SSakthivel K if (mode == SMP_DIRECT) { 3504f5860992SSakthivel K length = length - 4; /* subtract crc */ 3505f5860992SSakthivel K psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); 3506f5860992SSakthivel K } else { 3507f5860992SSakthivel K psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 3508f5860992SSakthivel K } 3509f5860992SSakthivel K } 3510f5860992SSakthivel K 3511f5860992SSakthivel K /** 3512f5860992SSakthivel K * pm8001_chip_smp_req - send a SMP task to FW 3513f5860992SSakthivel K * @pm8001_ha: our hba card information. 3514f5860992SSakthivel K * @ccb: the ccb information this request used. 3515f5860992SSakthivel K */ 3516f5860992SSakthivel K static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 3517f5860992SSakthivel K struct pm8001_ccb_info *ccb) 3518f5860992SSakthivel K { 3519f5860992SSakthivel K int elem, rc; 3520f5860992SSakthivel K struct sas_task *task = ccb->task; 3521f5860992SSakthivel K struct domain_device *dev = task->dev; 3522f5860992SSakthivel K struct pm8001_device *pm8001_dev = dev->lldd_dev; 3523f5860992SSakthivel K struct scatterlist *sg_req, *sg_resp; 3524f5860992SSakthivel K u32 req_len, resp_len; 3525f5860992SSakthivel K struct smp_req smp_cmd; 3526f5860992SSakthivel K u32 opc; 3527f5860992SSakthivel K struct inbound_queue_table *circularQ; 3528f5860992SSakthivel K char *preq_dma_addr = NULL; 3529f5860992SSakthivel K __le64 tmp_addr; 3530f5860992SSakthivel K u32 i, length; 3531f5860992SSakthivel K 3532f5860992SSakthivel K memset(&smp_cmd, 0, sizeof(smp_cmd)); 3533f5860992SSakthivel K /* 3534f5860992SSakthivel K * DMA-map SMP request, response buffers 3535f5860992SSakthivel K */ 3536f5860992SSakthivel K sg_req = &task->smp_task.smp_req; 3537f5860992SSakthivel K elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE); 3538f5860992SSakthivel K if (!elem) 3539f5860992SSakthivel K return -ENOMEM; 3540f5860992SSakthivel K req_len = sg_dma_len(sg_req); 3541f5860992SSakthivel K 3542f5860992SSakthivel K sg_resp = &task->smp_task.smp_resp; 3543f5860992SSakthivel K elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE); 3544f5860992SSakthivel K if (!elem) { 3545f5860992SSakthivel K rc = -ENOMEM; 3546f5860992SSakthivel K goto err_out; 3547f5860992SSakthivel K } 3548f5860992SSakthivel K resp_len = sg_dma_len(sg_resp); 3549f5860992SSakthivel K /* must be in dwords */ 3550f5860992SSakthivel K if ((req_len & 0x3) || (resp_len & 0x3)) { 3551f5860992SSakthivel K rc = -EINVAL; 3552f5860992SSakthivel K goto err_out_2; 3553f5860992SSakthivel K } 3554f5860992SSakthivel K 3555f5860992SSakthivel K opc = OPC_INB_SMP_REQUEST; 3556f5860992SSakthivel K circularQ = &pm8001_ha->inbnd_q_tbl[0]; 3557f5860992SSakthivel K smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 3558f5860992SSakthivel K 3559f5860992SSakthivel K length = sg_req->length; 3560f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 3561f5860992SSakthivel K pm8001_printk("SMP Frame Length %d\n", sg_req->length)); 3562f5860992SSakthivel K if (!(length - 8)) 3563f5860992SSakthivel K pm8001_ha->smp_exp_mode = SMP_DIRECT; 3564f5860992SSakthivel K else 3565f5860992SSakthivel K pm8001_ha->smp_exp_mode = SMP_INDIRECT; 3566f5860992SSakthivel K 3567f5860992SSakthivel K 3568f5860992SSakthivel K tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 3569f5860992SSakthivel K preq_dma_addr = (char *)phys_to_virt(tmp_addr); 3570f5860992SSakthivel K 3571f5860992SSakthivel K /* INDIRECT MODE command settings. Use DMA */ 3572f5860992SSakthivel K if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { 3573f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 3574f5860992SSakthivel K pm8001_printk("SMP REQUEST INDIRECT MODE\n")); 3575f5860992SSakthivel K /* for SPCv indirect mode. Place the top 4 bytes of 3576f5860992SSakthivel K * SMP Request header here. */ 3577f5860992SSakthivel K for (i = 0; i < 4; i++) 3578f5860992SSakthivel K smp_cmd.smp_req16[i] = *(preq_dma_addr + i); 3579f5860992SSakthivel K /* exclude top 4 bytes for SMP req header */ 3580f5860992SSakthivel K smp_cmd.long_smp_req.long_req_addr = 3581f5860992SSakthivel K cpu_to_le64((u64)sg_dma_address 3582cb993e5dSAnand Kumar Santhanam (&task->smp_task.smp_req) + 4); 3583f5860992SSakthivel K /* exclude 4 bytes for SMP req header and CRC */ 3584f5860992SSakthivel K smp_cmd.long_smp_req.long_req_size = 3585f5860992SSakthivel K cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); 3586f5860992SSakthivel K smp_cmd.long_smp_req.long_resp_addr = 3587f5860992SSakthivel K cpu_to_le64((u64)sg_dma_address 3588f5860992SSakthivel K (&task->smp_task.smp_resp)); 3589f5860992SSakthivel K smp_cmd.long_smp_req.long_resp_size = 3590f5860992SSakthivel K cpu_to_le32((u32)sg_dma_len 3591f5860992SSakthivel K (&task->smp_task.smp_resp)-4); 3592f5860992SSakthivel K } else { /* DIRECT MODE */ 3593f5860992SSakthivel K smp_cmd.long_smp_req.long_req_addr = 3594f5860992SSakthivel K cpu_to_le64((u64)sg_dma_address 3595f5860992SSakthivel K (&task->smp_task.smp_req)); 3596f5860992SSakthivel K smp_cmd.long_smp_req.long_req_size = 3597f5860992SSakthivel K cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 3598f5860992SSakthivel K smp_cmd.long_smp_req.long_resp_addr = 3599f5860992SSakthivel K cpu_to_le64((u64)sg_dma_address 3600f5860992SSakthivel K (&task->smp_task.smp_resp)); 3601f5860992SSakthivel K smp_cmd.long_smp_req.long_resp_size = 3602f5860992SSakthivel K cpu_to_le32 3603f5860992SSakthivel K ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 3604f5860992SSakthivel K } 3605f5860992SSakthivel K if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { 3606f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, 3607f5860992SSakthivel K pm8001_printk("SMP REQUEST DIRECT MODE\n")); 3608f5860992SSakthivel K for (i = 0; i < length; i++) 3609f5860992SSakthivel K if (i < 16) { 3610f5860992SSakthivel K smp_cmd.smp_req16[i] = *(preq_dma_addr+i); 3611f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3612f5860992SSakthivel K "Byte[%d]:%x (DMA data:%x)\n", 3613f5860992SSakthivel K i, smp_cmd.smp_req16[i], 3614f5860992SSakthivel K *(preq_dma_addr))); 3615f5860992SSakthivel K } else { 3616f5860992SSakthivel K smp_cmd.smp_req[i] = *(preq_dma_addr+i); 3617f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3618f5860992SSakthivel K "Byte[%d]:%x (DMA data:%x)\n", 3619f5860992SSakthivel K i, smp_cmd.smp_req[i], 3620f5860992SSakthivel K *(preq_dma_addr))); 3621f5860992SSakthivel K } 3622f5860992SSakthivel K } 3623f5860992SSakthivel K 3624f5860992SSakthivel K build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, 3625f5860992SSakthivel K &smp_cmd, pm8001_ha->smp_exp_mode, length); 3626f5860992SSakthivel K pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0); 3627f5860992SSakthivel K return 0; 3628f5860992SSakthivel K 3629f5860992SSakthivel K err_out_2: 3630f5860992SSakthivel K dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 3631f5860992SSakthivel K PCI_DMA_FROMDEVICE); 3632f5860992SSakthivel K err_out: 3633f5860992SSakthivel K dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 3634f5860992SSakthivel K PCI_DMA_TODEVICE); 3635f5860992SSakthivel K return rc; 3636f5860992SSakthivel K } 3637f5860992SSakthivel K 3638f5860992SSakthivel K static int check_enc_sas_cmd(struct sas_task *task) 3639f5860992SSakthivel K { 3640e73823f7SJames Bottomley u8 cmd = task->ssp_task.cmd->cmnd[0]; 3641e73823f7SJames Bottomley 3642e73823f7SJames Bottomley if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) 3643f5860992SSakthivel K return 1; 3644f5860992SSakthivel K else 3645f5860992SSakthivel K return 0; 3646f5860992SSakthivel K } 3647f5860992SSakthivel K 3648f5860992SSakthivel K static int check_enc_sat_cmd(struct sas_task *task) 3649f5860992SSakthivel K { 3650f5860992SSakthivel K int ret = 0; 3651f5860992SSakthivel K switch (task->ata_task.fis.command) { 3652f5860992SSakthivel K case ATA_CMD_FPDMA_READ: 3653f5860992SSakthivel K case ATA_CMD_READ_EXT: 3654f5860992SSakthivel K case ATA_CMD_READ: 3655f5860992SSakthivel K case ATA_CMD_FPDMA_WRITE: 3656f5860992SSakthivel K case ATA_CMD_WRITE_EXT: 3657f5860992SSakthivel K case ATA_CMD_WRITE: 3658f5860992SSakthivel K case ATA_CMD_PIO_READ: 3659f5860992SSakthivel K case ATA_CMD_PIO_READ_EXT: 3660f5860992SSakthivel K case ATA_CMD_PIO_WRITE: 3661f5860992SSakthivel K case ATA_CMD_PIO_WRITE_EXT: 3662f5860992SSakthivel K ret = 1; 3663f5860992SSakthivel K break; 3664f5860992SSakthivel K default: 3665f5860992SSakthivel K ret = 0; 3666f5860992SSakthivel K break; 3667f5860992SSakthivel K } 3668f5860992SSakthivel K return ret; 3669f5860992SSakthivel K } 3670f5860992SSakthivel K 3671f5860992SSakthivel K /** 3672f5860992SSakthivel K * pm80xx_chip_ssp_io_req - send a SSP task to FW 3673f5860992SSakthivel K * @pm8001_ha: our hba card information. 3674f5860992SSakthivel K * @ccb: the ccb information this request used. 3675f5860992SSakthivel K */ 3676f5860992SSakthivel K static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 3677f5860992SSakthivel K struct pm8001_ccb_info *ccb) 3678f5860992SSakthivel K { 3679f5860992SSakthivel K struct sas_task *task = ccb->task; 3680f5860992SSakthivel K struct domain_device *dev = task->dev; 3681f5860992SSakthivel K struct pm8001_device *pm8001_dev = dev->lldd_dev; 3682f5860992SSakthivel K struct ssp_ini_io_start_req ssp_cmd; 3683f5860992SSakthivel K u32 tag = ccb->ccb_tag; 3684f5860992SSakthivel K int ret; 36850ecdf00bSAnand Kumar Santhanam u64 phys_addr, start_addr, end_addr; 36860ecdf00bSAnand Kumar Santhanam u32 end_addr_high, end_addr_low; 3687f5860992SSakthivel K struct inbound_queue_table *circularQ; 3688f9cd6cbdSAnand Kumar Santhanam u32 q_index; 3689f5860992SSakthivel K u32 opc = OPC_INB_SSPINIIOSTART; 3690f5860992SSakthivel K memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 3691f5860992SSakthivel K memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 3692f5860992SSakthivel K /* data address domain added for spcv; set to 0 by host, 3693f5860992SSakthivel K * used internally by controller 3694f5860992SSakthivel K * 0 for SAS 1.1 and SAS 2.0 compatible TLR 3695f5860992SSakthivel K */ 3696f5860992SSakthivel K ssp_cmd.dad_dir_m_tlr = 3697f5860992SSakthivel K cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); 3698f5860992SSakthivel K ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 3699f5860992SSakthivel K ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 3700f5860992SSakthivel K ssp_cmd.tag = cpu_to_le32(tag); 3701f5860992SSakthivel K if (task->ssp_task.enable_first_burst) 3702f5860992SSakthivel K ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 3703f5860992SSakthivel K ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 3704f5860992SSakthivel K ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 3705e73823f7SJames Bottomley memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, 3706e73823f7SJames Bottomley task->ssp_task.cmd->cmd_len); 3707f9cd6cbdSAnand Kumar Santhanam q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM; 3708f9cd6cbdSAnand Kumar Santhanam circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 3709f5860992SSakthivel K 3710f5860992SSakthivel K /* Check if encryption is set */ 3711f5860992SSakthivel K if (pm8001_ha->chip->encrypt && 3712f5860992SSakthivel K !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { 3713f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3714f5860992SSakthivel K "Encryption enabled.Sending Encrypt SAS command 0x%x\n", 3715e73823f7SJames Bottomley task->ssp_task.cmd->cmnd[0])); 3716f5860992SSakthivel K opc = OPC_INB_SSP_INI_DIF_ENC_IO; 3717f5860992SSakthivel K /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ 3718f5860992SSakthivel K ssp_cmd.dad_dir_m_tlr = cpu_to_le32 3719f5860992SSakthivel K ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); 3720f5860992SSakthivel K 3721f5860992SSakthivel K /* fill in PRD (scatter/gather) table, if any */ 3722f5860992SSakthivel K if (task->num_scatter > 1) { 3723f5860992SSakthivel K pm8001_chip_make_sg(task->scatter, 3724f5860992SSakthivel K ccb->n_elem, ccb->buf_prd); 3725f5860992SSakthivel K phys_addr = ccb->ccb_dma_handle + 3726f5860992SSakthivel K offsetof(struct pm8001_ccb_info, buf_prd[0]); 3727f5860992SSakthivel K ssp_cmd.enc_addr_low = 3728f5860992SSakthivel K cpu_to_le32(lower_32_bits(phys_addr)); 3729f5860992SSakthivel K ssp_cmd.enc_addr_high = 3730f5860992SSakthivel K cpu_to_le32(upper_32_bits(phys_addr)); 3731f5860992SSakthivel K ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 3732f5860992SSakthivel K } else if (task->num_scatter == 1) { 3733f5860992SSakthivel K u64 dma_addr = sg_dma_address(task->scatter); 3734f5860992SSakthivel K ssp_cmd.enc_addr_low = 3735f5860992SSakthivel K cpu_to_le32(lower_32_bits(dma_addr)); 3736f5860992SSakthivel K ssp_cmd.enc_addr_high = 3737f5860992SSakthivel K cpu_to_le32(upper_32_bits(dma_addr)); 3738f5860992SSakthivel K ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 3739f5860992SSakthivel K ssp_cmd.enc_esgl = 0; 37400ecdf00bSAnand Kumar Santhanam /* Check 4G Boundary */ 37410ecdf00bSAnand Kumar Santhanam start_addr = cpu_to_le64(dma_addr); 37420ecdf00bSAnand Kumar Santhanam end_addr = (start_addr + ssp_cmd.enc_len) - 1; 37430ecdf00bSAnand Kumar Santhanam end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 37440ecdf00bSAnand Kumar Santhanam end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 37450ecdf00bSAnand Kumar Santhanam if (end_addr_high != ssp_cmd.enc_addr_high) { 37460ecdf00bSAnand Kumar Santhanam PM8001_FAIL_DBG(pm8001_ha, 37470ecdf00bSAnand Kumar Santhanam pm8001_printk("The sg list address " 37480ecdf00bSAnand Kumar Santhanam "start_addr=0x%016llx data_len=0x%x " 37490ecdf00bSAnand Kumar Santhanam "end_addr_high=0x%08x end_addr_low=" 37500ecdf00bSAnand Kumar Santhanam "0x%08x has crossed 4G boundary\n", 37510ecdf00bSAnand Kumar Santhanam start_addr, ssp_cmd.enc_len, 37520ecdf00bSAnand Kumar Santhanam end_addr_high, end_addr_low)); 37530ecdf00bSAnand Kumar Santhanam pm8001_chip_make_sg(task->scatter, 1, 37540ecdf00bSAnand Kumar Santhanam ccb->buf_prd); 37550ecdf00bSAnand Kumar Santhanam phys_addr = ccb->ccb_dma_handle + 37560ecdf00bSAnand Kumar Santhanam offsetof(struct pm8001_ccb_info, 37570ecdf00bSAnand Kumar Santhanam buf_prd[0]); 37580ecdf00bSAnand Kumar Santhanam ssp_cmd.enc_addr_low = 37590ecdf00bSAnand Kumar Santhanam cpu_to_le32(lower_32_bits(phys_addr)); 37600ecdf00bSAnand Kumar Santhanam ssp_cmd.enc_addr_high = 37610ecdf00bSAnand Kumar Santhanam cpu_to_le32(upper_32_bits(phys_addr)); 37620ecdf00bSAnand Kumar Santhanam ssp_cmd.enc_esgl = cpu_to_le32(1<<31); 37630ecdf00bSAnand Kumar Santhanam } 3764f5860992SSakthivel K } else if (task->num_scatter == 0) { 3765f5860992SSakthivel K ssp_cmd.enc_addr_low = 0; 3766f5860992SSakthivel K ssp_cmd.enc_addr_high = 0; 3767f5860992SSakthivel K ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 3768f5860992SSakthivel K ssp_cmd.enc_esgl = 0; 3769f5860992SSakthivel K } 3770f5860992SSakthivel K /* XTS mode. All other fields are 0 */ 3771f5860992SSakthivel K ssp_cmd.key_cmode = 0x6 << 4; 3772f5860992SSakthivel K /* set tweak values. Should be the start lba */ 3773e73823f7SJames Bottomley ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | 3774e73823f7SJames Bottomley (task->ssp_task.cmd->cmnd[3] << 16) | 3775e73823f7SJames Bottomley (task->ssp_task.cmd->cmnd[4] << 8) | 3776e73823f7SJames Bottomley (task->ssp_task.cmd->cmnd[5])); 3777f5860992SSakthivel K } else { 3778f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3779f5860992SSakthivel K "Sending Normal SAS command 0x%x inb q %x\n", 3780f9cd6cbdSAnand Kumar Santhanam task->ssp_task.cmd->cmnd[0], q_index)); 3781f5860992SSakthivel K /* fill in PRD (scatter/gather) table, if any */ 3782f5860992SSakthivel K if (task->num_scatter > 1) { 3783f5860992SSakthivel K pm8001_chip_make_sg(task->scatter, ccb->n_elem, 3784f5860992SSakthivel K ccb->buf_prd); 3785f5860992SSakthivel K phys_addr = ccb->ccb_dma_handle + 3786f5860992SSakthivel K offsetof(struct pm8001_ccb_info, buf_prd[0]); 3787f5860992SSakthivel K ssp_cmd.addr_low = 3788f5860992SSakthivel K cpu_to_le32(lower_32_bits(phys_addr)); 3789f5860992SSakthivel K ssp_cmd.addr_high = 3790f5860992SSakthivel K cpu_to_le32(upper_32_bits(phys_addr)); 3791f5860992SSakthivel K ssp_cmd.esgl = cpu_to_le32(1<<31); 3792f5860992SSakthivel K } else if (task->num_scatter == 1) { 3793f5860992SSakthivel K u64 dma_addr = sg_dma_address(task->scatter); 3794f5860992SSakthivel K ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 3795f5860992SSakthivel K ssp_cmd.addr_high = 3796f5860992SSakthivel K cpu_to_le32(upper_32_bits(dma_addr)); 3797f5860992SSakthivel K ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 3798f5860992SSakthivel K ssp_cmd.esgl = 0; 37990ecdf00bSAnand Kumar Santhanam /* Check 4G Boundary */ 38000ecdf00bSAnand Kumar Santhanam start_addr = cpu_to_le64(dma_addr); 38010ecdf00bSAnand Kumar Santhanam end_addr = (start_addr + ssp_cmd.len) - 1; 38020ecdf00bSAnand Kumar Santhanam end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 38030ecdf00bSAnand Kumar Santhanam end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 38040ecdf00bSAnand Kumar Santhanam if (end_addr_high != ssp_cmd.addr_high) { 38050ecdf00bSAnand Kumar Santhanam PM8001_FAIL_DBG(pm8001_ha, 38060ecdf00bSAnand Kumar Santhanam pm8001_printk("The sg list address " 38070ecdf00bSAnand Kumar Santhanam "start_addr=0x%016llx data_len=0x%x " 38080ecdf00bSAnand Kumar Santhanam "end_addr_high=0x%08x end_addr_low=" 38090ecdf00bSAnand Kumar Santhanam "0x%08x has crossed 4G boundary\n", 38100ecdf00bSAnand Kumar Santhanam start_addr, ssp_cmd.len, 38110ecdf00bSAnand Kumar Santhanam end_addr_high, end_addr_low)); 38120ecdf00bSAnand Kumar Santhanam pm8001_chip_make_sg(task->scatter, 1, 38130ecdf00bSAnand Kumar Santhanam ccb->buf_prd); 38140ecdf00bSAnand Kumar Santhanam phys_addr = ccb->ccb_dma_handle + 38150ecdf00bSAnand Kumar Santhanam offsetof(struct pm8001_ccb_info, 38160ecdf00bSAnand Kumar Santhanam buf_prd[0]); 38170ecdf00bSAnand Kumar Santhanam ssp_cmd.addr_low = 38180ecdf00bSAnand Kumar Santhanam cpu_to_le32(lower_32_bits(phys_addr)); 38190ecdf00bSAnand Kumar Santhanam ssp_cmd.addr_high = 38200ecdf00bSAnand Kumar Santhanam cpu_to_le32(upper_32_bits(phys_addr)); 38210ecdf00bSAnand Kumar Santhanam ssp_cmd.esgl = cpu_to_le32(1<<31); 38220ecdf00bSAnand Kumar Santhanam } 3823f5860992SSakthivel K } else if (task->num_scatter == 0) { 3824f5860992SSakthivel K ssp_cmd.addr_low = 0; 3825f5860992SSakthivel K ssp_cmd.addr_high = 0; 3826f5860992SSakthivel K ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 3827f5860992SSakthivel K ssp_cmd.esgl = 0; 3828f5860992SSakthivel K } 3829f5860992SSakthivel K } 3830f9cd6cbdSAnand Kumar Santhanam q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM; 3831f9cd6cbdSAnand Kumar Santhanam ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 3832f9cd6cbdSAnand Kumar Santhanam &ssp_cmd, q_index); 3833f5860992SSakthivel K return ret; 3834f5860992SSakthivel K } 3835f5860992SSakthivel K 3836f5860992SSakthivel K static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 3837f5860992SSakthivel K struct pm8001_ccb_info *ccb) 3838f5860992SSakthivel K { 3839f5860992SSakthivel K struct sas_task *task = ccb->task; 3840f5860992SSakthivel K struct domain_device *dev = task->dev; 3841f5860992SSakthivel K struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 3842f5860992SSakthivel K u32 tag = ccb->ccb_tag; 3843f5860992SSakthivel K int ret; 3844f9cd6cbdSAnand Kumar Santhanam u32 q_index; 3845f5860992SSakthivel K struct sata_start_req sata_cmd; 3846f5860992SSakthivel K u32 hdr_tag, ncg_tag = 0; 38470ecdf00bSAnand Kumar Santhanam u64 phys_addr, start_addr, end_addr; 38480ecdf00bSAnand Kumar Santhanam u32 end_addr_high, end_addr_low; 3849f5860992SSakthivel K u32 ATAP = 0x0; 3850f5860992SSakthivel K u32 dir; 3851f5860992SSakthivel K struct inbound_queue_table *circularQ; 3852c6b9ef57SSakthivel K unsigned long flags; 3853f5860992SSakthivel K u32 opc = OPC_INB_SATA_HOST_OPSTART; 3854f5860992SSakthivel K memset(&sata_cmd, 0, sizeof(sata_cmd)); 3855f9cd6cbdSAnand Kumar Santhanam q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM; 3856f9cd6cbdSAnand Kumar Santhanam circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; 3857f5860992SSakthivel K 3858f5860992SSakthivel K if (task->data_dir == PCI_DMA_NONE) { 3859f5860992SSakthivel K ATAP = 0x04; /* no data*/ 3860f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n")); 3861f5860992SSakthivel K } else if (likely(!task->ata_task.device_control_reg_update)) { 3862f5860992SSakthivel K if (task->ata_task.dma_xfer) { 3863f5860992SSakthivel K ATAP = 0x06; /* DMA */ 3864f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n")); 3865f5860992SSakthivel K } else { 3866f5860992SSakthivel K ATAP = 0x05; /* PIO*/ 3867f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n")); 3868f5860992SSakthivel K } 3869f5860992SSakthivel K if (task->ata_task.use_ncq && 3870f5860992SSakthivel K dev->sata_dev.command_set != ATAPI_COMMAND_SET) { 3871f5860992SSakthivel K ATAP = 0x07; /* FPDMA */ 3872f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n")); 3873f5860992SSakthivel K } 3874f5860992SSakthivel K } 3875c6b9ef57SSakthivel K if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { 3876c6b9ef57SSakthivel K task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 3877f5860992SSakthivel K ncg_tag = hdr_tag; 3878c6b9ef57SSakthivel K } 3879f5860992SSakthivel K dir = data_dir_flags[task->data_dir] << 8; 3880f5860992SSakthivel K sata_cmd.tag = cpu_to_le32(tag); 3881f5860992SSakthivel K sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 3882f5860992SSakthivel K sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 3883f5860992SSakthivel K 3884f5860992SSakthivel K sata_cmd.sata_fis = task->ata_task.fis; 3885f5860992SSakthivel K if (likely(!task->ata_task.device_control_reg_update)) 3886f5860992SSakthivel K sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 3887f5860992SSakthivel K sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 3888f5860992SSakthivel K 3889f5860992SSakthivel K /* Check if encryption is set */ 3890f5860992SSakthivel K if (pm8001_ha->chip->encrypt && 3891f5860992SSakthivel K !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { 3892f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3893f5860992SSakthivel K "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", 3894f5860992SSakthivel K sata_cmd.sata_fis.command)); 3895f5860992SSakthivel K opc = OPC_INB_SATA_DIF_ENC_IO; 3896f5860992SSakthivel K 3897f5860992SSakthivel K /* set encryption bit */ 3898f5860992SSakthivel K sata_cmd.ncqtag_atap_dir_m_dad = 3899f5860992SSakthivel K cpu_to_le32(((ncg_tag & 0xff)<<16)| 3900f5860992SSakthivel K ((ATAP & 0x3f) << 10) | 0x20 | dir); 3901f5860992SSakthivel K /* dad (bit 0-1) is 0 */ 3902f5860992SSakthivel K /* fill in PRD (scatter/gather) table, if any */ 3903f5860992SSakthivel K if (task->num_scatter > 1) { 3904f5860992SSakthivel K pm8001_chip_make_sg(task->scatter, 3905f5860992SSakthivel K ccb->n_elem, ccb->buf_prd); 3906f5860992SSakthivel K phys_addr = ccb->ccb_dma_handle + 3907f5860992SSakthivel K offsetof(struct pm8001_ccb_info, buf_prd[0]); 3908f5860992SSakthivel K sata_cmd.enc_addr_low = lower_32_bits(phys_addr); 3909f5860992SSakthivel K sata_cmd.enc_addr_high = upper_32_bits(phys_addr); 3910f5860992SSakthivel K sata_cmd.enc_esgl = cpu_to_le32(1 << 31); 3911f5860992SSakthivel K } else if (task->num_scatter == 1) { 3912f5860992SSakthivel K u64 dma_addr = sg_dma_address(task->scatter); 3913f5860992SSakthivel K sata_cmd.enc_addr_low = lower_32_bits(dma_addr); 3914f5860992SSakthivel K sata_cmd.enc_addr_high = upper_32_bits(dma_addr); 3915f5860992SSakthivel K sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 3916f5860992SSakthivel K sata_cmd.enc_esgl = 0; 39170ecdf00bSAnand Kumar Santhanam /* Check 4G Boundary */ 39180ecdf00bSAnand Kumar Santhanam start_addr = cpu_to_le64(dma_addr); 39190ecdf00bSAnand Kumar Santhanam end_addr = (start_addr + sata_cmd.enc_len) - 1; 39200ecdf00bSAnand Kumar Santhanam end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 39210ecdf00bSAnand Kumar Santhanam end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 39220ecdf00bSAnand Kumar Santhanam if (end_addr_high != sata_cmd.enc_addr_high) { 39230ecdf00bSAnand Kumar Santhanam PM8001_FAIL_DBG(pm8001_ha, 39240ecdf00bSAnand Kumar Santhanam pm8001_printk("The sg list address " 39250ecdf00bSAnand Kumar Santhanam "start_addr=0x%016llx data_len=0x%x " 39260ecdf00bSAnand Kumar Santhanam "end_addr_high=0x%08x end_addr_low" 39270ecdf00bSAnand Kumar Santhanam "=0x%08x has crossed 4G boundary\n", 39280ecdf00bSAnand Kumar Santhanam start_addr, sata_cmd.enc_len, 39290ecdf00bSAnand Kumar Santhanam end_addr_high, end_addr_low)); 39300ecdf00bSAnand Kumar Santhanam pm8001_chip_make_sg(task->scatter, 1, 39310ecdf00bSAnand Kumar Santhanam ccb->buf_prd); 39320ecdf00bSAnand Kumar Santhanam phys_addr = ccb->ccb_dma_handle + 39330ecdf00bSAnand Kumar Santhanam offsetof(struct pm8001_ccb_info, 39340ecdf00bSAnand Kumar Santhanam buf_prd[0]); 39350ecdf00bSAnand Kumar Santhanam sata_cmd.enc_addr_low = 39360ecdf00bSAnand Kumar Santhanam lower_32_bits(phys_addr); 39370ecdf00bSAnand Kumar Santhanam sata_cmd.enc_addr_high = 39380ecdf00bSAnand Kumar Santhanam upper_32_bits(phys_addr); 39390ecdf00bSAnand Kumar Santhanam sata_cmd.enc_esgl = 39400ecdf00bSAnand Kumar Santhanam cpu_to_le32(1 << 31); 39410ecdf00bSAnand Kumar Santhanam } 3942f5860992SSakthivel K } else if (task->num_scatter == 0) { 3943f5860992SSakthivel K sata_cmd.enc_addr_low = 0; 3944f5860992SSakthivel K sata_cmd.enc_addr_high = 0; 3945f5860992SSakthivel K sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); 3946f5860992SSakthivel K sata_cmd.enc_esgl = 0; 3947f5860992SSakthivel K } 3948f5860992SSakthivel K /* XTS mode. All other fields are 0 */ 3949f5860992SSakthivel K sata_cmd.key_index_mode = 0x6 << 4; 3950f5860992SSakthivel K /* set tweak values. Should be the start lba */ 3951f5860992SSakthivel K sata_cmd.twk_val0 = 3952f5860992SSakthivel K cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | 3953f5860992SSakthivel K (sata_cmd.sata_fis.lbah << 16) | 3954f5860992SSakthivel K (sata_cmd.sata_fis.lbam << 8) | 3955f5860992SSakthivel K (sata_cmd.sata_fis.lbal)); 3956f5860992SSakthivel K sata_cmd.twk_val1 = 3957f5860992SSakthivel K cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | 3958f5860992SSakthivel K (sata_cmd.sata_fis.lbam_exp)); 3959f5860992SSakthivel K } else { 3960f5860992SSakthivel K PM8001_IO_DBG(pm8001_ha, pm8001_printk( 3961f5860992SSakthivel K "Sending Normal SATA command 0x%x inb %x\n", 3962f9cd6cbdSAnand Kumar Santhanam sata_cmd.sata_fis.command, q_index)); 3963f5860992SSakthivel K /* dad (bit 0-1) is 0 */ 3964f5860992SSakthivel K sata_cmd.ncqtag_atap_dir_m_dad = 3965f5860992SSakthivel K cpu_to_le32(((ncg_tag & 0xff)<<16) | 3966f5860992SSakthivel K ((ATAP & 0x3f) << 10) | dir); 3967f5860992SSakthivel K 3968f5860992SSakthivel K /* fill in PRD (scatter/gather) table, if any */ 3969f5860992SSakthivel K if (task->num_scatter > 1) { 3970f5860992SSakthivel K pm8001_chip_make_sg(task->scatter, 3971f5860992SSakthivel K ccb->n_elem, ccb->buf_prd); 3972f5860992SSakthivel K phys_addr = ccb->ccb_dma_handle + 3973f5860992SSakthivel K offsetof(struct pm8001_ccb_info, buf_prd[0]); 3974f5860992SSakthivel K sata_cmd.addr_low = lower_32_bits(phys_addr); 3975f5860992SSakthivel K sata_cmd.addr_high = upper_32_bits(phys_addr); 3976f5860992SSakthivel K sata_cmd.esgl = cpu_to_le32(1 << 31); 3977f5860992SSakthivel K } else if (task->num_scatter == 1) { 3978f5860992SSakthivel K u64 dma_addr = sg_dma_address(task->scatter); 3979f5860992SSakthivel K sata_cmd.addr_low = lower_32_bits(dma_addr); 3980f5860992SSakthivel K sata_cmd.addr_high = upper_32_bits(dma_addr); 3981f5860992SSakthivel K sata_cmd.len = cpu_to_le32(task->total_xfer_len); 3982f5860992SSakthivel K sata_cmd.esgl = 0; 39830ecdf00bSAnand Kumar Santhanam /* Check 4G Boundary */ 39840ecdf00bSAnand Kumar Santhanam start_addr = cpu_to_le64(dma_addr); 39850ecdf00bSAnand Kumar Santhanam end_addr = (start_addr + sata_cmd.len) - 1; 39860ecdf00bSAnand Kumar Santhanam end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); 39870ecdf00bSAnand Kumar Santhanam end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); 39880ecdf00bSAnand Kumar Santhanam if (end_addr_high != sata_cmd.addr_high) { 39890ecdf00bSAnand Kumar Santhanam PM8001_FAIL_DBG(pm8001_ha, 39900ecdf00bSAnand Kumar Santhanam pm8001_printk("The sg list address " 39910ecdf00bSAnand Kumar Santhanam "start_addr=0x%016llx data_len=0x%x" 39920ecdf00bSAnand Kumar Santhanam "end_addr_high=0x%08x end_addr_low=" 39930ecdf00bSAnand Kumar Santhanam "0x%08x has crossed 4G boundary\n", 39940ecdf00bSAnand Kumar Santhanam start_addr, sata_cmd.len, 39950ecdf00bSAnand Kumar Santhanam end_addr_high, end_addr_low)); 39960ecdf00bSAnand Kumar Santhanam pm8001_chip_make_sg(task->scatter, 1, 39970ecdf00bSAnand Kumar Santhanam ccb->buf_prd); 39980ecdf00bSAnand Kumar Santhanam phys_addr = ccb->ccb_dma_handle + 39990ecdf00bSAnand Kumar Santhanam offsetof(struct pm8001_ccb_info, 40000ecdf00bSAnand Kumar Santhanam buf_prd[0]); 40010ecdf00bSAnand Kumar Santhanam sata_cmd.addr_low = 40020ecdf00bSAnand Kumar Santhanam lower_32_bits(phys_addr); 40030ecdf00bSAnand Kumar Santhanam sata_cmd.addr_high = 40040ecdf00bSAnand Kumar Santhanam upper_32_bits(phys_addr); 40050ecdf00bSAnand Kumar Santhanam sata_cmd.esgl = cpu_to_le32(1 << 31); 40060ecdf00bSAnand Kumar Santhanam } 4007f5860992SSakthivel K } else if (task->num_scatter == 0) { 4008f5860992SSakthivel K sata_cmd.addr_low = 0; 4009f5860992SSakthivel K sata_cmd.addr_high = 0; 4010f5860992SSakthivel K sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4011f5860992SSakthivel K sata_cmd.esgl = 0; 4012f5860992SSakthivel K } 4013f5860992SSakthivel K /* scsi cdb */ 4014f5860992SSakthivel K sata_cmd.atapi_scsi_cdb[0] = 4015f5860992SSakthivel K cpu_to_le32(((task->ata_task.atapi_packet[0]) | 4016f5860992SSakthivel K (task->ata_task.atapi_packet[1] << 8) | 4017f5860992SSakthivel K (task->ata_task.atapi_packet[2] << 16) | 4018f5860992SSakthivel K (task->ata_task.atapi_packet[3] << 24))); 4019f5860992SSakthivel K sata_cmd.atapi_scsi_cdb[1] = 4020f5860992SSakthivel K cpu_to_le32(((task->ata_task.atapi_packet[4]) | 4021f5860992SSakthivel K (task->ata_task.atapi_packet[5] << 8) | 4022f5860992SSakthivel K (task->ata_task.atapi_packet[6] << 16) | 4023f5860992SSakthivel K (task->ata_task.atapi_packet[7] << 24))); 4024f5860992SSakthivel K sata_cmd.atapi_scsi_cdb[2] = 4025f5860992SSakthivel K cpu_to_le32(((task->ata_task.atapi_packet[8]) | 4026f5860992SSakthivel K (task->ata_task.atapi_packet[9] << 8) | 4027f5860992SSakthivel K (task->ata_task.atapi_packet[10] << 16) | 4028f5860992SSakthivel K (task->ata_task.atapi_packet[11] << 24))); 4029f5860992SSakthivel K sata_cmd.atapi_scsi_cdb[3] = 4030f5860992SSakthivel K cpu_to_le32(((task->ata_task.atapi_packet[12]) | 4031f5860992SSakthivel K (task->ata_task.atapi_packet[13] << 8) | 4032f5860992SSakthivel K (task->ata_task.atapi_packet[14] << 16) | 4033f5860992SSakthivel K (task->ata_task.atapi_packet[15] << 24))); 4034f5860992SSakthivel K } 4035c6b9ef57SSakthivel K 4036c6b9ef57SSakthivel K /* Check for read log for failed drive and return */ 4037c6b9ef57SSakthivel K if (sata_cmd.sata_fis.command == 0x2f) { 4038c6b9ef57SSakthivel K if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || 4039c6b9ef57SSakthivel K (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || 4040c6b9ef57SSakthivel K (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { 4041c6b9ef57SSakthivel K struct task_status_struct *ts; 4042c6b9ef57SSakthivel K 4043c6b9ef57SSakthivel K pm8001_ha_dev->id &= 0xDFFFFFFF; 4044c6b9ef57SSakthivel K ts = &task->task_status; 4045c6b9ef57SSakthivel K 4046c6b9ef57SSakthivel K spin_lock_irqsave(&task->task_state_lock, flags); 4047c6b9ef57SSakthivel K ts->resp = SAS_TASK_COMPLETE; 4048c6b9ef57SSakthivel K ts->stat = SAM_STAT_GOOD; 4049c6b9ef57SSakthivel K task->task_state_flags &= ~SAS_TASK_STATE_PENDING; 4050c6b9ef57SSakthivel K task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 4051c6b9ef57SSakthivel K task->task_state_flags |= SAS_TASK_STATE_DONE; 4052c6b9ef57SSakthivel K if (unlikely((task->task_state_flags & 4053c6b9ef57SSakthivel K SAS_TASK_STATE_ABORTED))) { 4054c6b9ef57SSakthivel K spin_unlock_irqrestore(&task->task_state_lock, 4055c6b9ef57SSakthivel K flags); 4056c6b9ef57SSakthivel K PM8001_FAIL_DBG(pm8001_ha, 4057c6b9ef57SSakthivel K pm8001_printk("task 0x%p resp 0x%x " 4058c6b9ef57SSakthivel K " stat 0x%x but aborted by upper layer " 4059c6b9ef57SSakthivel K "\n", task, ts->resp, ts->stat)); 4060c6b9ef57SSakthivel K pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4061c6b9ef57SSakthivel K return 0; 4062c6b9ef57SSakthivel K } else if (task->uldd_task) { 4063c6b9ef57SSakthivel K spin_unlock_irqrestore(&task->task_state_lock, 4064c6b9ef57SSakthivel K flags); 4065c6b9ef57SSakthivel K pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4066c6b9ef57SSakthivel K mb();/* ditto */ 4067c6b9ef57SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 4068c6b9ef57SSakthivel K task->task_done(task); 4069c6b9ef57SSakthivel K spin_lock_irq(&pm8001_ha->lock); 4070c6b9ef57SSakthivel K return 0; 4071c6b9ef57SSakthivel K } else if (!task->uldd_task) { 4072c6b9ef57SSakthivel K spin_unlock_irqrestore(&task->task_state_lock, 4073c6b9ef57SSakthivel K flags); 4074c6b9ef57SSakthivel K pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); 4075c6b9ef57SSakthivel K mb();/*ditto*/ 4076c6b9ef57SSakthivel K spin_unlock_irq(&pm8001_ha->lock); 4077c6b9ef57SSakthivel K task->task_done(task); 4078c6b9ef57SSakthivel K spin_lock_irq(&pm8001_ha->lock); 4079c6b9ef57SSakthivel K return 0; 4080c6b9ef57SSakthivel K } 4081c6b9ef57SSakthivel K } 4082c6b9ef57SSakthivel K } 4083f9cd6cbdSAnand Kumar Santhanam q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM; 4084f5860992SSakthivel K ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, 4085f9cd6cbdSAnand Kumar Santhanam &sata_cmd, q_index); 4086f5860992SSakthivel K return ret; 4087f5860992SSakthivel K } 4088f5860992SSakthivel K 4089f5860992SSakthivel K /** 4090f5860992SSakthivel K * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND 4091f5860992SSakthivel K * @pm8001_ha: our hba card information. 4092f5860992SSakthivel K * @num: the inbound queue number 4093f5860992SSakthivel K * @phy_id: the phy id which we wanted to start up. 4094f5860992SSakthivel K */ 4095f5860992SSakthivel K static int 4096f5860992SSakthivel K pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4097f5860992SSakthivel K { 4098f5860992SSakthivel K struct phy_start_req payload; 4099f5860992SSakthivel K struct inbound_queue_table *circularQ; 4100f5860992SSakthivel K int ret; 4101f5860992SSakthivel K u32 tag = 0x01; 4102f5860992SSakthivel K u32 opcode = OPC_INB_PHYSTART; 4103f5860992SSakthivel K circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4104f5860992SSakthivel K memset(&payload, 0, sizeof(payload)); 4105f5860992SSakthivel K payload.tag = cpu_to_le32(tag); 4106f5860992SSakthivel K 4107f5860992SSakthivel K PM8001_INIT_DBG(pm8001_ha, 4108f5860992SSakthivel K pm8001_printk("PHY START REQ for phy_id %d\n", phy_id)); 4109f5860992SSakthivel K /* 4110f5860992SSakthivel K ** [0:7] PHY Identifier 4111f5860992SSakthivel K ** [8:11] link rate 1.5G, 3G, 6G 4112f5860992SSakthivel K ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode 4113f5860992SSakthivel K ** [14] 0b disable spin up hold; 1b enable spin up hold 4114f5860992SSakthivel K ** [15] ob no change in current PHY analig setup 1b enable using SPAST 4115f5860992SSakthivel K */ 4116a9a923e5SAnand Kumar Santhanam if (!IS_SPCV_12G(pm8001_ha->pdev)) 4117f5860992SSakthivel K payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4118f5860992SSakthivel K LINKMODE_AUTO | LINKRATE_15 | 4119f5860992SSakthivel K LINKRATE_30 | LINKRATE_60 | phy_id); 4120a9a923e5SAnand Kumar Santhanam else 4121a9a923e5SAnand Kumar Santhanam payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4122a9a923e5SAnand Kumar Santhanam LINKMODE_AUTO | LINKRATE_15 | 4123a9a923e5SAnand Kumar Santhanam LINKRATE_30 | LINKRATE_60 | LINKRATE_120 | 4124a9a923e5SAnand Kumar Santhanam phy_id); 4125a9a923e5SAnand Kumar Santhanam 4126f5860992SSakthivel K /* SSC Disable and SAS Analog ST configuration */ 4127f5860992SSakthivel K /** 4128f5860992SSakthivel K payload.ase_sh_lm_slr_phyid = 4129f5860992SSakthivel K cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | 4130f5860992SSakthivel K LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | 4131f5860992SSakthivel K phy_id); 4132f5860992SSakthivel K Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need 4133f5860992SSakthivel K **/ 4134f5860992SSakthivel K 4135aa9f8328SJames Bottomley payload.sas_identify.dev_type = SAS_END_DEVICE; 4136f5860992SSakthivel K payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4137f5860992SSakthivel K memcpy(payload.sas_identify.sas_addr, 4138f5860992SSakthivel K pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4139f5860992SSakthivel K payload.sas_identify.phy_id = phy_id; 4140f5860992SSakthivel K ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); 4141f5860992SSakthivel K return ret; 4142f5860992SSakthivel K } 4143f5860992SSakthivel K 4144f5860992SSakthivel K /** 4145f5860992SSakthivel K * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4146f5860992SSakthivel K * @pm8001_ha: our hba card information. 4147f5860992SSakthivel K * @num: the inbound queue number 4148f5860992SSakthivel K * @phy_id: the phy id which we wanted to start up. 4149f5860992SSakthivel K */ 4150f5860992SSakthivel K static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4151f5860992SSakthivel K u8 phy_id) 4152f5860992SSakthivel K { 4153f5860992SSakthivel K struct phy_stop_req payload; 4154f5860992SSakthivel K struct inbound_queue_table *circularQ; 4155f5860992SSakthivel K int ret; 4156f5860992SSakthivel K u32 tag = 0x01; 4157f5860992SSakthivel K u32 opcode = OPC_INB_PHYSTOP; 4158f5860992SSakthivel K circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4159f5860992SSakthivel K memset(&payload, 0, sizeof(payload)); 4160f5860992SSakthivel K payload.tag = cpu_to_le32(tag); 4161f5860992SSakthivel K payload.phy_id = cpu_to_le32(phy_id); 4162f5860992SSakthivel K ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); 4163f5860992SSakthivel K return ret; 4164f5860992SSakthivel K } 4165f5860992SSakthivel K 4166f5860992SSakthivel K /** 4167f5860992SSakthivel K * see comments on pm8001_mpi_reg_resp. 4168f5860992SSakthivel K */ 4169f5860992SSakthivel K static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4170f5860992SSakthivel K struct pm8001_device *pm8001_dev, u32 flag) 4171f5860992SSakthivel K { 4172f5860992SSakthivel K struct reg_dev_req payload; 4173f5860992SSakthivel K u32 opc; 4174f5860992SSakthivel K u32 stp_sspsmp_sata = 0x4; 4175f5860992SSakthivel K struct inbound_queue_table *circularQ; 4176f5860992SSakthivel K u32 linkrate, phy_id; 4177f5860992SSakthivel K int rc, tag = 0xdeadbeef; 4178f5860992SSakthivel K struct pm8001_ccb_info *ccb; 4179f5860992SSakthivel K u8 retryFlag = 0x1; 4180f5860992SSakthivel K u16 firstBurstSize = 0; 4181f5860992SSakthivel K u16 ITNT = 2000; 4182f5860992SSakthivel K struct domain_device *dev = pm8001_dev->sas_device; 4183f5860992SSakthivel K struct domain_device *parent_dev = dev->parent; 4184f5860992SSakthivel K circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4185f5860992SSakthivel K 4186f5860992SSakthivel K memset(&payload, 0, sizeof(payload)); 4187f5860992SSakthivel K rc = pm8001_tag_alloc(pm8001_ha, &tag); 4188f5860992SSakthivel K if (rc) 4189f5860992SSakthivel K return rc; 4190f5860992SSakthivel K ccb = &pm8001_ha->ccb_info[tag]; 4191f5860992SSakthivel K ccb->device = pm8001_dev; 4192f5860992SSakthivel K ccb->ccb_tag = tag; 4193f5860992SSakthivel K payload.tag = cpu_to_le32(tag); 4194f5860992SSakthivel K 4195f5860992SSakthivel K if (flag == 1) { 4196f5860992SSakthivel K stp_sspsmp_sata = 0x02; /*direct attached sata */ 4197f5860992SSakthivel K } else { 4198aa9f8328SJames Bottomley if (pm8001_dev->dev_type == SAS_SATA_DEV) 4199f5860992SSakthivel K stp_sspsmp_sata = 0x00; /* stp*/ 4200aa9f8328SJames Bottomley else if (pm8001_dev->dev_type == SAS_END_DEVICE || 4201aa9f8328SJames Bottomley pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || 4202aa9f8328SJames Bottomley pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) 4203f5860992SSakthivel K stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4204f5860992SSakthivel K } 4205f5860992SSakthivel K if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 4206f5860992SSakthivel K phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4207f5860992SSakthivel K else 4208f5860992SSakthivel K phy_id = pm8001_dev->attached_phy; 4209f5860992SSakthivel K 4210f5860992SSakthivel K opc = OPC_INB_REG_DEV; 4211f5860992SSakthivel K 4212f5860992SSakthivel K linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4213f5860992SSakthivel K pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4214f5860992SSakthivel K 4215f5860992SSakthivel K payload.phyid_portid = 4216f5860992SSakthivel K cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) | 4217f5860992SSakthivel K ((phy_id & 0xFF) << 8)); 4218f5860992SSakthivel K 4219f5860992SSakthivel K payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | 4220f5860992SSakthivel K ((linkrate & 0x0F) << 24) | 4221f5860992SSakthivel K ((stp_sspsmp_sata & 0x03) << 28)); 4222f5860992SSakthivel K payload.firstburstsize_ITNexustimeout = 4223f5860992SSakthivel K cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4224f5860992SSakthivel K 4225f5860992SSakthivel K memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4226f5860992SSakthivel K SAS_ADDR_SIZE); 4227f5860992SSakthivel K 4228f5860992SSakthivel K rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4229f5860992SSakthivel K 4230f5860992SSakthivel K return rc; 4231f5860992SSakthivel K } 4232f5860992SSakthivel K 4233f5860992SSakthivel K /** 4234f5860992SSakthivel K * pm80xx_chip_phy_ctl_req - support the local phy operation 4235f5860992SSakthivel K * @pm8001_ha: our hba card information. 4236f5860992SSakthivel K * @num: the inbound queue number 4237f5860992SSakthivel K * @phy_id: the phy id which we wanted to operate 4238f5860992SSakthivel K * @phy_op: 4239f5860992SSakthivel K */ 4240f5860992SSakthivel K static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4241f5860992SSakthivel K u32 phyId, u32 phy_op) 4242f5860992SSakthivel K { 4243f5860992SSakthivel K struct local_phy_ctl_req payload; 4244f5860992SSakthivel K struct inbound_queue_table *circularQ; 4245f5860992SSakthivel K int ret; 4246f5860992SSakthivel K u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4247f5860992SSakthivel K memset(&payload, 0, sizeof(payload)); 4248f5860992SSakthivel K circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4249f5860992SSakthivel K payload.tag = cpu_to_le32(1); 4250f5860992SSakthivel K payload.phyop_phyid = 4251f5860992SSakthivel K cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); 4252f5860992SSakthivel K ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); 4253f5860992SSakthivel K return ret; 4254f5860992SSakthivel K } 4255f5860992SSakthivel K 4256f5860992SSakthivel K static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha) 4257f5860992SSakthivel K { 4258f5860992SSakthivel K u32 value; 4259f5860992SSakthivel K #ifdef PM8001_USE_MSIX 4260f5860992SSakthivel K return 1; 4261f5860992SSakthivel K #endif 4262f5860992SSakthivel K value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4263f5860992SSakthivel K if (value) 4264f5860992SSakthivel K return 1; 4265f5860992SSakthivel K return 0; 4266f5860992SSakthivel K 4267f5860992SSakthivel K } 4268f5860992SSakthivel K 4269f5860992SSakthivel K /** 4270f5860992SSakthivel K * pm8001_chip_isr - PM8001 isr handler. 4271f5860992SSakthivel K * @pm8001_ha: our hba card information. 4272f5860992SSakthivel K * @irq: irq number. 4273f5860992SSakthivel K * @stat: stat. 4274f5860992SSakthivel K */ 4275f5860992SSakthivel K static irqreturn_t 4276f5860992SSakthivel K pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) 4277f5860992SSakthivel K { 4278f5860992SSakthivel K pm80xx_chip_interrupt_disable(pm8001_ha, vec); 4279f5860992SSakthivel K process_oq(pm8001_ha, vec); 4280f5860992SSakthivel K pm80xx_chip_interrupt_enable(pm8001_ha, vec); 4281f5860992SSakthivel K return IRQ_HANDLED; 4282f5860992SSakthivel K } 4283f5860992SSakthivel K 4284f5860992SSakthivel K const struct pm8001_dispatch pm8001_80xx_dispatch = { 4285f5860992SSakthivel K .name = "pmc80xx", 4286f5860992SSakthivel K .chip_init = pm80xx_chip_init, 4287f5860992SSakthivel K .chip_soft_rst = pm80xx_chip_soft_rst, 4288f5860992SSakthivel K .chip_rst = pm80xx_hw_chip_rst, 4289f5860992SSakthivel K .chip_iounmap = pm8001_chip_iounmap, 4290f5860992SSakthivel K .isr = pm80xx_chip_isr, 4291f5860992SSakthivel K .is_our_interupt = pm80xx_chip_is_our_interupt, 4292f5860992SSakthivel K .isr_process_oq = process_oq, 4293f5860992SSakthivel K .interrupt_enable = pm80xx_chip_interrupt_enable, 4294f5860992SSakthivel K .interrupt_disable = pm80xx_chip_interrupt_disable, 4295f5860992SSakthivel K .make_prd = pm8001_chip_make_sg, 4296f5860992SSakthivel K .smp_req = pm80xx_chip_smp_req, 4297f5860992SSakthivel K .ssp_io_req = pm80xx_chip_ssp_io_req, 4298f5860992SSakthivel K .sata_req = pm80xx_chip_sata_req, 4299f5860992SSakthivel K .phy_start_req = pm80xx_chip_phy_start_req, 4300f5860992SSakthivel K .phy_stop_req = pm80xx_chip_phy_stop_req, 4301f5860992SSakthivel K .reg_dev_req = pm80xx_chip_reg_dev_req, 4302f5860992SSakthivel K .dereg_dev_req = pm8001_chip_dereg_dev_req, 4303f5860992SSakthivel K .phy_ctl_req = pm80xx_chip_phy_ctl_req, 4304f5860992SSakthivel K .task_abort = pm8001_chip_abort_task, 4305f5860992SSakthivel K .ssp_tm_req = pm8001_chip_ssp_tm_req, 4306f5860992SSakthivel K .get_nvmd_req = pm8001_chip_get_nvmd_req, 4307f5860992SSakthivel K .set_nvmd_req = pm8001_chip_set_nvmd_req, 4308f5860992SSakthivel K .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4309f5860992SSakthivel K .set_dev_state_req = pm8001_chip_set_dev_state_req, 4310f5860992SSakthivel K }; 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